WO2023093096A1 - 一种正交系统架构以及网络设备 - Google Patents

一种正交系统架构以及网络设备 Download PDF

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Publication number
WO2023093096A1
WO2023093096A1 PCT/CN2022/107813 CN2022107813W WO2023093096A1 WO 2023093096 A1 WO2023093096 A1 WO 2023093096A1 CN 2022107813 W CN2022107813 W CN 2022107813W WO 2023093096 A1 WO2023093096 A1 WO 2023093096A1
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WIPO (PCT)
Prior art keywords
circuit board
connector
board
electrically connected
system architecture
Prior art date
Application number
PCT/CN2022/107813
Other languages
English (en)
French (fr)
Inventor
温海
王罗
Original Assignee
华为技术有限公司
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Publication of WO2023093096A1 publication Critical patent/WO2023093096A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/71—Coupling devices for rigid printing circuits or like structures
    • H01R12/72—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures
    • H01R12/73—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/71—Coupling devices for rigid printing circuits or like structures
    • H01R12/72—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures
    • H01R12/73—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
    • H01R12/735—Printed circuits including an angle between each other
    • H01R12/737—Printed circuits being substantially perpendicular to each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits

Definitions

  • the present application relates to the technical field of network equipment, and in particular to an orthogonal system architecture and network equipment.
  • SerDeserializer Serializer/deserializer
  • the method to reduce the loss of high-speed SerDes links is mainly to install multiple clock data recovery (Clock Data Recovery, CDR) chips on the switching fabric board or line card board.
  • CDR clock Data Recovery
  • the CDR chip requires additional peripheral circuits, such as power supply circuits, clock circuits, etc., this will increase the complexity of the layout, number of layers and wiring of the printed circuit board (PCB) of the switching network board, thereby Increase production cost.
  • PCB printed circuit board
  • an additional radiator needs to be installed to dissipate heat from the CDR chip, but too many CDRs will increase the system power consumption and noise of the network device. Therefore, how to realize network equipment with low loss and low power consumption is an urgent problem to be solved.
  • the present application provides an orthogonal system architecture and network equipment, so as to reduce system loss and power consumption, and realize network equipment with low loss and low power consumption.
  • the present application provides an orthogonal system architecture.
  • the orthogonal system architecture includes a first circuit board, a second circuit board, a first connector, a second connector and a flexible connection assembly.
  • the first circuit board and the second circuit board may be vertically arranged to form a vertical structure.
  • the first circuit board is provided with a chip component, and the chip component is electrically connected with the first circuit board.
  • the first connector can be electrically connected with the chip component through the flexible connection component, and the second connector is arranged on the second circuit board and electrically connected with the second circuit board.
  • the first connector and the second connector can be plugged together to realize the electrical connection between the first circuit board and the second circuit board.
  • the high-speed SerDes link between the first circuit board and the second circuit board can be formed by a chip component, a flexible connection component, a first connector and a second connector to reduce The PCB trace length of the first circuit board and its design complexity, and reduce the number of layers of the first circuit board used for the high-speed SerDes link, thereby reducing the fabrication cost of the orthogonal system architecture, and reducing the system loss and power of the network equipment consumption.
  • the flexible connection component may include a flexible transmission line.
  • One end of the flexible transmission line is electrically connected to the first connector, and the other end is electrically connected to the chip component.
  • the flexible transmission line may be directly connected to the chip component, or the flexible transmission line may be indirectly connected to the chip component. Utilizing the flexibility and flexibility of the flexible transmission line, the specific position of the first circuit board can be set according to actual application scenarios, without limiting the first circuit board to a fixed position.
  • the specific type of the above-mentioned flexible transmission line may not be limited, for example, it may be a flexible cable, a flexible circuit board or a rigid-flex board.
  • the flexible connection assembly may also include a board end connector.
  • the board end connector is disposed on the first circuit board.
  • the board end connector can be electrically connected to the chip component through the wiring of the first circuit board.
  • One end of the flexible transmission line may be electrically connected to the first connector, and the other end may be electrically connected to the board connector.
  • the high-speed SerDes link between the chip component and the board-end connector adopts PCB wiring
  • the high-speed SerDes link between the board-end connector and the first connector adopts a flexible transmission line.
  • the board end connector can be arranged around the chip component, so that the board end connection is as close as possible to the chip component, thereby reducing the PCB trace length from the board end connector to the chip component.
  • the above board end connector may include a first board end connector and a second board end connector.
  • the first board end connector may be disposed on one side surface of the first circuit board, and the second board end connector may be disposed on a side surface of the first circuit board away from the first board end connector.
  • this setting can shorten the total PCB trace length from the first board-end connector and the second board-end connector to the chip component respectively, so as to reduce system loss; space on one side of the circuit board, thereby improving the space utilization rate of the first circuit board.
  • the projection of the first board end connector on the first circuit board is the first projection, and the projection of the second board end connector on the first circuit board for the second projection.
  • the first projection can overlap the second projection to further improve the space utilization of the orthogonal system architecture and thus reduce the size of the first circuit board.
  • the side of the board connector facing the first connector may be provided with an output port, and the flexible transmission line may be directly electrically connected to the output port, so as to reduce the length of the flexible transmission line, thereby reducing system loss.
  • the footprint of the flexible transmission line is also reduced, further improving the space utilization of the orthogonal system architecture.
  • the chip component may include a chip substrate and a chip body disposed on the chip substrate.
  • the chip body is electrically connected to the wires of the chip substrate.
  • One end of the flexible transmission line can be electrically connected to the first connector, and the other end can be electrically connected to the chip substrate, so that zero PCB trace arrangement between the chip component and the first connector can be realized, and the loss of the orthogonal system architecture can be further reduced.
  • the first circuit board may also have conductive vias.
  • the flexible transmission line is electrically connected to the chip component through the conductive via hole without changing the structure of the chip component. In this way, without changing the structure of the chip component, zero PCB routing arrangement can also be realized between the chip component and the first connector, thereby reducing the loss of the orthogonal system architecture.
  • the flexible transmission line can be directly electrically connected to the conductive vias.
  • an adapter seat may also be provided on the first circuit board. The adapter seat is located on the side of the first circuit board away from the chip component. The chip component is electrically connected to the adapter seat through the conductive via hole, and the flexible transmission line is electrically connected to the adapter seat.
  • the orthogonal system architecture may further include a fixed board, and the first connector may be disposed on the fixed board.
  • the fixing plate is arranged between the first circuit board and the second circuit board, and the fixing plate is spaced apart from the first circuit board. In this way, the first connector and the first circuit board can be spaced apart, so that the specific position of the first circuit board can be set according to the actual application scene, regardless of the positions of the second circuit board, the second connector and the first connector. limit.
  • the plane where the fixing board is located is the first plane
  • the plane where the first circuit board is located is the second plane.
  • the first plane and the second plane can be the same plane, so that the first circuit board can be arranged in one-to-one correspondence with the fixing board, which facilitates the assembly and disassembly of the orthogonal system architecture.
  • the first plane and the second plane may also be different planes. In this way, corresponding to one fixed board, multiple stacked first circuit boards may be provided, thereby improving the space utilization rate of the orthogonal system architecture.
  • the orthogonal system architecture may include a plurality of first connectors, and these first connectors may be arranged along a first direction.
  • the first circuit board is provided with a plurality of chip components, and these chip components can be arranged along the second direction. Wherein, the first direction is perpendicular to the second direction. In this way, the flexible connection components of each chip component to the first connector can avoid that the projections on the plane where the first circuit board is located intersect with each other; length, thereby reducing system losses.
  • the plurality of chip components may include a first chip component and a second chip component, and the second chip component may be disposed on a side of the first chip component away from the first connector.
  • the first chip assembly may include first and second pins, and the second chip assembly may include third and fourth pins.
  • Orthogonal system architecture includes multiple flexibly connected components.
  • the above-mentioned plurality of flexible connection components may include a first flexible connection component, a second flexible connection component and a third flexible connection component. When specifically set, the first pin is electrically connected to the first flexible connection component, the second pin is electrically connected to the second flexible connection component, the third pin is electrically connected to the third flexible connection component, and the fourth pin is electrically connected to the first flexible connection component.
  • the wiring on the circuit board is electrically connected to the second pin.
  • these redundant high-speed SerDes channels can be used as relays, thereby forming a second chip component, a first chip component, a second flexible connection component, a first connector and a second chip component.
  • a high-speed SerDes link composed of two connectors is used to reduce the length of the flexible connection component from the second chip component to the first connector and reduce system loss.
  • the plurality of chip components may also include a third chip component and a fourth chip component, and the fourth chip component is disposed on a side of the third chip component away from the first connector.
  • the third chip assembly may include fifth, sixth and seventh pins, and the fourth chip assembly may include eighth, ninth and tenth pins.
  • Orthogonal system architecture includes multiple flexibly connected components.
  • the above-mentioned plurality of flexible connection components may include a fourth flexible connection component, a fifth flexible connection component, a sixth flexible connection component and a seventh flexible connection component.
  • the fifth pin is electrically connected to the fourth flexible connection component
  • the sixth pin is electrically connected to the fifth flexible connection component
  • the eighth pin is electrically connected to the sixth flexible connection component
  • the ninth pin is electrically connected to the seventh flexible connection component.
  • the flexible connection component is electrically connected
  • the seventh pin is electrically connected to the ninth pin through the wiring of the first circuit board
  • the tenth pin is electrically connected to the sixth pin through the wiring of the first circuit board.
  • the first high-speed SerDes link composed of the first connector and the second connector, and the second High-speed SerDes link which can also reduce the PCB trace length and design complexity of the first circuit board, and can reduce the number of layers of the first circuit board for the high-speed SerDes link, thereby reducing the fabrication of the orthogonal system architecture Cost and system loss, and reduce power consumption of network equipment.
  • the above-mentioned orthogonal system architecture may further include a first angled connector and a second angled connector.
  • the first angled connector may be disposed on the first circuit board.
  • the first angled connector can be electrically connected to the chip component through the wiring of the first circuit board.
  • the second angle connector can be arranged on the second circuit board and electrically connected with the second circuit board.
  • the first angled connector and the second angled connector can be plugged directly, so as to realize the electrical connection between the first circuit board and the second circuit board, thereby reducing the number of flexible connection components, thereby reducing the size of the first circuit board and the space between the second circuit board.
  • the above-mentioned first angled connector may be an angled male connector, and the above-mentioned second angled connector may be an angled female connector.
  • the above-mentioned first angled connector may be an angled female connector, and the above-mentioned second angled connector may be an angled male connector.
  • the first circuit board can also be provided with a power module.
  • the power module can be arranged on the side of the first circuit board away from the chip component, and the power module is electrically connected to the chip component through the wiring of the first circuit board. Utilizing the space on the side of the first circuit board away from the chip component, the power module may not occupy the space of the chip component on the first circuit board, thereby improving the space utilization rate of the first circuit board.
  • the projection of the chip assembly on the first circuit board is the third projection
  • the projection of the power module on the first circuit board is the fourth projection.
  • the third projection at least partly coincides with the fourth projection, so that the resistance from the power module to the chip assembly can be reduced, and the number of layers for making power traces in the first circuit board can be reduced.
  • the specific types of the first circuit board and the second circuit board are not limited.
  • the first circuit board may be a switching fabric board
  • the second circuit board may be a line card board.
  • the first circuit board may be a line card board
  • the second circuit board may be a switching fabric board.
  • the present application provides a network device, including the orthogonal system architecture of the first aspect.
  • the high-speed SerDes link between the first circuit board and the second circuit board can be formed by a chip assembly, a flexible connection assembly, a first connector, and a second connector to reduce the size of the first circuit board.
  • the PCB trace length and its design complexity are reduced, and the number of layers of the first circuit board used for the high-speed SerDes link is reduced, thereby reducing the fabrication cost of the orthogonal system architecture, and reducing the system loss and power consumption of the network equipment.
  • Fig. 1 is the structural block diagram of the network device in the embodiment of the present application.
  • Fig. 2 is a schematic structural diagram of the first connector and the flexible connection assembly in the embodiment of the present application
  • Fig. 3 is another schematic structural view of the first connector and the flexible connection assembly in the embodiment of the present application.
  • Fig. 4 is a schematic structural diagram of the first circuit board and the flexible connection assembly in the embodiment of the present application.
  • Fig. 5 is another schematic structural diagram of the first circuit board and the flexible connection assembly in the embodiment of the present application.
  • FIG. 6 is another structural schematic diagram of the first circuit board and the flexible connection assembly in the embodiment of the present application.
  • FIG. 7 is another schematic structural diagram of the orthogonal system architecture in the embodiment of the present application.
  • FIG. 8 is another schematic structural diagram of an orthogonal system architecture in an embodiment of the present application.
  • FIG. 9 is another schematic structural diagram of the orthogonal system architecture in the embodiment of the present application.
  • FIG. 10 is another schematic structural diagram of the orthogonal system architecture in the embodiment of the present application.
  • FIG. 11 is another schematic structural diagram of the orthogonal system architecture in the embodiment of the present application.
  • FIG. 12 is another schematic structural diagram of the orthogonal system architecture in the embodiment of the present application.
  • FIG. 13 is another schematic structural diagram of the orthogonal system architecture in the embodiment of the present application.
  • FIG. 14 is another schematic structural diagram of the orthogonal system architecture in the embodiment of the present application.
  • FIG. 15 is another schematic structural diagram of the orthogonal system architecture in the embodiment of the present application.
  • FIG. 16 is another schematic structural diagram of an orthogonal system architecture in an embodiment of the present application.
  • 1501-rigid printed circuit 1502-flexible printed circuit
  • the system architecture of network equipment generally adopts an orthogonal system architecture.
  • a specific orthogonal system architecture may include line card boards and switching fabric boards, where the line card boards and switching fabric boards are arranged vertically to form a vertical architecture.
  • the line card board is provided with a line card board chip and a line card board connector, and the line card board chip is connected to the line card board connector through the PCB routing of the line card board.
  • the SFU is provided with a SFU chip and a SFU connector, and the SFU chip is connected to the SFU connector through the PCB routing of the SFU.
  • Existing orthogonal system architectures include two modes with a backplane and without a backplane.
  • a backplane is arranged between the line card board and the switching fabric board, and the backplane is a mid-plane backplane.
  • the PCB traces of the line card board and the switching fabric board are too long.
  • the PCB trace between the chip and the SFU connector may be as long as 25 inches, resulting in high system loss and power consumption.
  • an embodiment of the present application provides an orthogonal system architecture and network equipment, so as to reduce system loss and power consumption, and realize network equipment with low loss and low power consumption.
  • FIG. 1 is a structural block diagram of a network device in an embodiment of the present application.
  • a network device 01 includes an orthogonal system architecture 10 .
  • the structure type of the network device 01 is not specifically limited, for example, it may be a frame-type network device or a box-type network device.
  • the type of the network device 01 is not specifically limited, for example, it may be a switch, a server or a router.
  • the orthogonal system architecture 10 includes a first circuit board 11 , a second circuit board 12 , a first connector 13 , a second connector 14 and a flexible connection assembly 15 .
  • the first circuit board 11 and the second circuit board 12 are vertically arranged to realize a vertical structure.
  • the first circuit board 11 is provided with a chip component 111 , and the chip component 111 is electrically connected to the first circuit board 11 .
  • the first connector 13 can be electrically connected to the chip component 111 through the flexible connection component 15 .
  • the second connector 14 is disposed on the second circuit board 12 and is electrically connected to the second circuit board 12 .
  • the first connector 13 can be inserted into the second connector 14 , so as to realize the electrical connection between the first circuit board 11 and the second circuit board 12 .
  • the flexible connection assembly 15 in FIG. 1 is only a schematic diagram, and is not used to limit the quantity, structure and position of the flexible connection assembly 15 with other components.
  • the chip component 111, the flexible connection component 15, the first connector 13 and the second connector 14 can form a high-speed SerDes link between the first circuit board 11 and the second circuit board 12 , to improve the high-speed signal transmission performance of the system.
  • the high-speed SerDes link can reduce the length of the PCB wiring of the first circuit board 11 and the complexity of wiring design, thereby reducing the fabrication cost and system loss of the orthogonal system architecture 10 and reducing the power consumption of the network device 01 .
  • the position of the first circuit board 11 can be set according to actual application scenarios, so that the orthogonal system architecture 10 can be applied to more scenarios.
  • the specific types of the first circuit board 11 and the second circuit board 12 are not limited, for example, they may be line card boards, switching fabric boards or processing boards.
  • the first circuit board 11 may be a switching fabric board
  • the second circuit board 12 may be a line card board.
  • the first circuit board 11 may be a line card board
  • the second circuit board 12 may be a switching fabric board.
  • the specific quantity of the first circuit board 11 and the second circuit board 12 is not limited, for example, the quantity of the first circuit board 11 can be 1, 2, 4, 8, 10 Or 16 etc., the number of the second circuit board 12 can be 1, 2, 4, 8, 10 or 16 etc.
  • the orthogonal system architecture 10 may include 16 first circuit boards 11 and 8 second circuit boards 12 .
  • the above-mentioned 16 first circuit boards 11 can be stacked along the direction perpendicular to the page in FIG. 1
  • the above-mentioned 8 second circuit boards 12 can be stacked along the vertical direction shown by the arrow in FIG. 1 .
  • a first circuit board 11 is used as an example for description below.
  • FIG. 2 is a schematic structural diagram of the first connector and the flexible connection assembly in the embodiment of the present application
  • FIG. 3 is another schematic structural diagram of the first connector and the flexible connection assembly in the embodiment of the present application.
  • the flexible connection assembly 15 may include a flexible transmission line 150a.
  • One end of the flexible transmission line 150 a may be electrically connected to the first connector 13 , and the other end may be electrically connected to the chip assembly 111 .
  • the flexibility of the flexible transmission line 150a can be used to set the specific position of the first circuit board 11 without limiting the first circuit board 11 to a certain fixed position.
  • the type of the flexible transmission line 150a may not be limited.
  • the flexible transmission line 150a may be a flexible cable.
  • the flexible cable may be a high-speed cable, and the high-speed cable has characteristics of low loss and high bandwidth. In the case of the same length, the loss of high-speed cables is about 1/4 of the loss of PCB traces.
  • the high-speed cable can be plugged directly into the input port of the first connector 13 .
  • the flexible transmission line 150a can also be a flexible circuit board (Flexible Printed Circuit, FPC), and its loss is also lower than that of PCB wiring.
  • FPC Flexible Printed Circuit
  • the FPC can be directly electrically connected to the input port of the first connector 13 .
  • the connection method between the FPC and the input port of the first connector 13 is not specifically limited, for example, it may be welding or clamping.
  • the FPC may include one or more signal layers. When the FPC includes multiple signal layers, a shielding layer may be provided between two adjacent signal layers, so that the signal transmission of each signal layer in the FPC may not affect each other.
  • one first connector 13 can be connected to multiple pins of the chip component 111 through one FPC, so as to realize the system architecture of "one-to-many" interconnection.
  • FPC has a higher wiring density, it can also be designed into a required shape according to the wiring path.
  • the flexible transmission line 150a adopts FPC, which is conducive to reducing wind resistance and assembly, and can improve the heat dissipation capability of the system and reduce the design cost of the system. It should be noted that, in the embodiments of the present application, "multiple" means that the number is greater than or equal to 2.
  • the flexible transmission line 150a may also be a rigid-flex board.
  • the rigid-flex board includes a rigid board printed circuit 1501 and a flex board printed circuit 1502 .
  • the rigid-flex board may include a rigid board printed circuit 1501.
  • the rigid printed circuit 1501 can be crimped on the first connector 13 and electrically connected to the first connector 13 .
  • the flexible printed circuit 1502 can be crimped on the side of the rigid printed circuit 1501 away from the first connector 13 , and electrically connected to the rigid printed circuit 1501 . That is to say, the flexible printed circuit 1502 can be electrically connected to the first connector 13 through the rigid printed circuit 1501 .
  • the rigid-flex board may also include two rigid-board printed circuits 1501 , that is, a first rigid-board printed circuit and a second rigid-board printed circuit.
  • first rigid printed circuit can be crimped to the first connector 13 and electrically connected to the first connector 13 .
  • the flexible printed circuit 1502 can be crimped on the side of the first rigid printed circuit away from the first connector 13 , and electrically connected to the first rigid printed circuit.
  • the second rigid printed circuit can be crimped on the side of the flexible printed circuit 1502 away from the first rigid printed circuit, and electrically connected with the first rigid printed circuit and the flexible printed circuit 1502 . That is to say, the first rigid printed circuit and the second rigid printed circuit are crimped on both sides of the flexible printed circuit 1502, and the flexible printed circuit 1502 passes through the first rigid printed circuit and the first rigid printed circuit. Connector 13 is connected.
  • the outgoing direction of the rigid board printed circuit 1501 is not specifically limited.
  • the outgoing line direction of the rigid printed circuit 1501 may face the first circuit board 11 ; or, the outgoing line direction may also face other directions, such as the vertical direction shown in FIG. 3 .
  • the end of the flex printed circuit 1502 electrically connected to the chip component 111 may also be A plurality of bifurcated structures are formed, and these bifurcated structures can be respectively electrically connected to different pins of the chip component 111 .
  • FIG. 4 is a schematic structural diagram of the first circuit board and the flexible connection assembly in the embodiment of the present application.
  • the chip component 111 may include a chip substrate 112 and a chip body 113 .
  • the chip body 113 is a die formed by dicing a wafer.
  • the bare chip has bonding pads for packaging, and the bare chip is electrically connected to the traces of the chip substrate 112 through the bonding pads.
  • one end of the flexible transmission line 150 a may be electrically connected to the first connector 13 , and the other end may be electrically connected to the chip substrate 112 .
  • the chip component 111 and the first connector 13 can be electrically connected only through the flexible transmission line 150a, so that the zero PCB trace setting between the chip component 111 and the first connector 13 can be realized, that is, the chip component 111 does not need to pass through the first connector 13.
  • the wires of the circuit board 11 are electrically connected to the first connector 13 , so that the loss of the orthogonal system architecture 10 can be reduced.
  • the first circuit board 11 only needs to provide signal carriers such as power supply to the chip component 111 , which can further reduce the manufacturing cost and layer design of the first circuit board 11 .
  • the chip component 111 and the first connector 13 are interconnected through the flexible transmission line 150a, which can be applied to application scenarios with higher rates such as 112Gbit/s or 224Gbit/s.
  • FIG. 5 is another schematic structural view of the first circuit board and the flexible connection assembly in the embodiment of the present application
  • FIG. 6 is another structural schematic view of the first circuit board and the flexible connection assembly in the embodiment of the present application.
  • the first circuit board 11 has a conductive via 114
  • the flexible transmission line 150 a can be electrically connected to the chip component 111 through the conductive via 114 .
  • pads 116 are respectively provided on the two side surfaces of the first circuit board 11 .
  • the pad 116 may cover the conductive via 114 and be electrically connected to the conductive via 114 .
  • the chip component 111 may be disposed on one side of the first circuit board 11 and be directly electrically connected to the pad 116 on the side.
  • the flexible transmission line 150 a may be disposed on a side of the first circuit board 11 away from the chip component 111 , and be directly electrically connected to the pad 116 on this side.
  • pads 116 are respectively provided on the two side surfaces of the first circuit board 11 .
  • the pad 116 may cover the conductive via 114 and be electrically connected to the conductive via 114 .
  • the chip component 111 may be disposed on one side of the first circuit board 11 and be directly electrically connected to the pad 116 on the side.
  • the side of the first circuit board 11 away from the chip assembly 111 may be provided with an adapter seat 117 , and the adapter seat 117 is electrically connected to the pad 116 on this side.
  • the flexible transmission line 150 a can be directly electrically connected to the adapter base 117 , so as to realize the electrical connection between the flexible transmission line 150 a and the chip component 111 through the adapter base 117 and the conductive via 114 . All of the above embodiments can realize zero PCB routing between the chip component 111 and the first connector 13, thereby reducing the loss and power consumption of the orthogonal system architecture 10.
  • FIG. 7 is another schematic structural diagram of the orthogonal system architecture in the embodiment of the present application
  • FIG. 8 is another structural schematic diagram of the orthogonal system architecture in the embodiment of the present application.
  • the flexible transmission line 150 a may also be indirectly connected to the chip component 111 .
  • the first circuit board 11 may be provided with a board header connector 150b.
  • the board end connector 150 b can be electrically connected to the chip component 111 through the wiring of the first circuit board 11 .
  • One end of the flexible transmission line 150a may be electrically connected to the first connector 13, and the other end may be electrically connected to the board end connector 150b.
  • the board end connector 150b can be directly installed on the first circuit board 11 by screwing or crimping.
  • the chip assembly 111 and the first connector 13 are electrically connected by a combination of PCB wiring and the flexible connection assembly 15, without changing the structure of the chip assembly 111, different types of chip assemblies 111 Both can be applied to the orthogonal system architecture 10, thereby enhancing the versatility of the orthogonal system architecture 10.
  • the board end connector 150b can be arranged close to the chip component 111, thereby reducing the length of PCB traces and reducing system loss.
  • the first circuit board 11 may be provided with a plurality of board end connectors 150b.
  • These board connectors 150 b can be disposed on the peripheral side of the chip assembly 111 .
  • the distance from the board end connector 150b to the chip assembly 111 is smaller than the distance from the board end connector 150b to the edge of the first circuit board 11, so that the board end connection is as close as possible to the chip assembly 111, thereby reducing the size of the board end connector.
  • 150b to the PCB trace length of chip assembly 111.
  • a plurality of header connectors 150b may be arranged in two rows. Two rows of board connectors 150b are disposed on two sides of the chip assembly 111 and extend along the second direction B.
  • a plurality of board connectors 150b may also be arranged in four rows.
  • the four-row board connectors 150b are disposed on two sides of the chip assembly 111 and extend along the second direction B. As shown in FIG. For one side of the chip assembly 111, the two rows of board connectors 150b may be staggered and/or aligned.
  • the output port of each board connector 150b can be arranged on a side away from the chip assembly 111 . In this way, the flexible transmission lines 150a between these board end connectors 150b and the first connector 13 will not cross, and there is a larger space for cable management, which facilitates the assembly and disassembly of the orthogonal system architecture 10 .
  • the orthogonal system architecture 10 may include a plurality of first connectors 13 arranged along the first direction A.
  • the first circuit board 11 may be provided with a plurality of chip components 111 , and these chip components 111 may be arranged along the second direction B.
  • the first direction A is perpendicular to the second direction B, so that the flexible connection assembly 15 from each chip assembly 111 to the first connector 13 can be avoided, and the projection intersection on the plane where the first circuit board 11 is located; and can reduce The total length of the high-speed SerDes links from all chip components 111 to the first connector 13 is reduced, thereby reducing system loss.
  • the position of the second circuit board 12 is set first. Since the second connector 14 is arranged on the second circuit board 12, and the first connector 13 needs to be plugged with the second connector 14, after the position of the second circuit board 12 is determined, the installation position of the first connector 13 is also determined, that is to say the first direction A is also determined.
  • FIG. 9 is another schematic structural diagram of an orthogonal system architecture in an embodiment of the present application.
  • the side of the board connector 150 b facing the first connector 13 is provided with an output port, and the flexible transmission line 150 a can be electrically connected to the output port.
  • the wire outlet direction of the board end connector 150b can directly face the first connector 13 without setting the wire outlet direction perpendicular to the first circuit board 11 (as shown in the vertical direction in FIG. 9 ).
  • the board end connector 150b may include a first board end connector 1503 and a second board end connector 1504 .
  • the second board end connector 1504 may be disposed on a side surface of the first circuit board 11 away from the first board end connector 1503 . That is to say, the first board end connector 1503 and the second board end connector 1504 can be arranged on both sides of the first circuit board 11, thereby shortening the connection between the chip assembly 111 and the first board end connector 1503 and the second board end connector.
  • the PCB trace length of the device 1504 is used to reduce system loss.
  • the output port of the first board end connector 1503 is the first output port 1505
  • the output port of the second board end connector 1504 is the second output port 1506 .
  • the first output port 1505 can be arranged on the side of the first board end connector 1503 away from the chip assembly 111
  • the second output port 1506 can be arranged on the second board end connector 1504 facing the second circuit board 12 and the first output port 1505 and the second output port 1506 are respectively electrically connected to the flexible transmission line 150a.
  • FIG. 10 is another schematic structural diagram of an orthogonal system architecture in an embodiment of the present application.
  • the first board end connector 1503 and the second board end connector 1504 may also be attached to both sides of the first circuit board 11 . That is to say, the projection of the first board end connector 1503 on the first circuit board 11 may overlap with the projection of the second board end connector 1504 on the first circuit board 11 .
  • the orthogonal system architecture 10 may further include a heat sink 17 .
  • the heat sink 17 is used to dissipate heat to the chip assembly 111, and can directly cover the chip assembly 111 and the board end connector 150b arranged on the same side, without the need to set the avoidance structure of the flexible connection assembly 15, thereby increasing the heat dissipation area and improving The cooling capability of the system architecture.
  • the heat sink 17 can be directly attached to the surface of the chip assembly 111, so that the heat dissipation efficiency of the heat sink 17 is high, and there is no need to arrange too many heat sinks 17, thereby reducing system noise.
  • FIG. 11 is another schematic structural diagram of an orthogonal system architecture in an embodiment of the present application.
  • the second board end connector 1504 can be provided with a second output port 1506 on the side facing the first connector 13 instead of facing away from the first circuit board 11
  • One side of the second output port 1506 is set, so that the space occupied by the connection between the second board end connector 1504 and the flexible transmission line 150a can be reduced, and the line space of the flexible transmission line 150a can be increased, and then the first output port can be connected according to specific needs.
  • the space between the connector 13 and the first circuit board 11 is set to be small.
  • FIG. 12 is another schematic structural diagram of an orthogonal system architecture in an embodiment of the present application.
  • the first circuit board 11 can also be provided with a power module 115 , and the power module 115 is used to provide power to the chip component 111 .
  • the power module 115 may be disposed on a side of the first circuit board 11 away from the chip component 111 , and the power module 115 is electrically connected to the chip component 111 through the wiring of the first circuit board 11 .
  • This design of disposing the chip component 111 and the power module 115 on both sides of the first circuit board 11 can reduce the occupied space on the side of the first circuit board 11 with the chip component 111 on the one hand, and improve the device integration of the first circuit board 11. degree, thereby the area of the first circuit board 11 can be reduced; There is more space to arrange other electronic devices.
  • the projection of the chip component 111 on the first circuit board 11 and the projection of the power module 115 on the first circuit board 11 can at least partially overlap, which can reduce the distance between the power module 115 and the chip component 111. resistance, and reduce the number of layers for making power wiring in the first circuit board 11 . Therefore, the first circuit board 11 only needs to install the chip assembly 111, the power supply module 115 and the board end connector 150b, and does not need to set a CDR chip, so that a system architecture with low power consumption and low loss can be realized; and the first circuit board can also be reduced.
  • the large size requirement of the circuit board 11 simplifies the routing design of the first circuit board 11 .
  • the projection of the chip component 111 on the first circuit board 11 and the projection of the power module 115 on the first circuit board 11 may coincide in the center.
  • the orthogonal system architecture 10 may further include a fixed plate 16 .
  • the fixing plate 16 is located between the first circuit board 11 and the second circuit board 12 .
  • the first connector 13 can be disposed on the fixing board 16 so that the first connector 13 is spaced apart from the first circuit board 11 . In this way, the specific position of the first circuit board 11 can be set according to the actual application scenario, without being limited by the positions of the second circuit board 12 , the second connector 14 and the first connector 13 .
  • the plane where the fixing board 16 is located is the first plane M
  • the plane where the first circuit board 11 is located is the second plane N.
  • the first plane M and the second plane N can be the same plane, so that the first circuit board 11 and the fixing board 16 can be provided in one-to-one correspondence, which facilitates the assembly and disassembly of the orthogonal system architecture 10 .
  • the first plane M is a simplified plane of the fixing plate 16 .
  • the first plane M is the surface of the fixed plate 16; when considering the thickness of the fixed plate 16, the first plane M is the plane where the midline of the fixed plate 16 thickness is located.
  • the second plane N is a simplified plane of the first circuit board 11 .
  • the second plane N is the surface of the first circuit board 11; when considering the thickness of the first circuit board 11, the second plane N is where the midline of the first circuit board 11 thickness plane.
  • FIG. 13 is another schematic structural diagram of an orthogonal system architecture in an embodiment of the present application.
  • the first plane M and the second plane N can also be different planes. In this way, corresponding to one fixed plate 16, multiple stacked first circuit boards 11 can be arranged, thereby improving the performance of the orthogonal system architecture 10. Space utilization.
  • a corresponding heat sink 17 may be provided on the side of each first circuit board 11 having the chip assembly 111 for dissipating heat from the heat-generating electronic components of the first circuit board 11 .
  • the heat sink 17 can cover the entire first circuit board 11, thereby increasing the heat dissipation area and improving the heat dissipation efficiency.
  • the number and type of the chip components 111 , the parameters of the board connector 150b and the parameters of the second connector 14 can be set respectively according to the requirements of the application scenario.
  • the network device 01 may include a chassis with 16 slots.
  • the chassis has 16 slots.
  • the orthogonal system architecture 10 includes 1 first circuit board 11 and 16 second circuit boards 12 .
  • the first circuit board 11 is provided with a first chip assembly 111a and a second chip assembly 111b.
  • the first circuit board 11 is electrically connected to 16 first connectors 13 .
  • Each first connector 13 has 96 pairs of differential lines.
  • the first circuit board 11 is provided with 64 board end connectors 150b, and each board end connector 150b has 24 pairs of differential lines.
  • Each first connector 13 can be connected to four board end connectors 150b of a first circuit board 11 through a flexible transmission line 150a, wherein two board end connectors 150b are connected to the first chip assembly 111a, and the other two board end connectors 150b are connected to the first chip assembly 111a.
  • the connector 150b is connected to the second chip assembly 111b.
  • the first connector 13 is connected to the chip component 111 through 1536 flexible transmission lines 150a, and each chip component 111 has more than or equal to 384 SerDes channels.
  • Table 1 below shows several examples of setting up the orthogonal system architecture 10 for different types of network devices 01 . It should be noted that the embodiments of the present application are not limited to these examples, and specifically, different settings may be made according to actual application scenarios.
  • one first connector 13 can be connected to multiple board end connectors 150b through the flexible transmission line 150a to realize the system architecture of "one-to-many" interconnection, so that the length of the flexible transmission line 150a can be flexibly set, and The PCB trace length between the board end connector 150b and the chip component 111 is used to reduce system loss.
  • each first connector 13 can be electrically connected to the chip assembly 111 of the same first circuit board 11 .
  • each first connector 13 may also be electrically connected to a plurality of chip components 111 of the first circuit board 11 .
  • the orthogonal system architecture 10 includes 16 first circuit boards 11 , 8 second circuit boards 12 , 64 first connectors 13 and 64 second connectors 14 .
  • the 8 second circuit boards 12 are stacked along the first direction A
  • the 16 first circuit boards 11 are stacked along the direction perpendicular to the first direction A.
  • Each second circuit board 12 is provided with 8 second connectors 14 .
  • the orthogonal system architecture 10 further includes a fixed board 16 on which the 64 first connectors 13 are disposed.
  • Each first connector 13 is correspondingly inserted into a second connector 14 .
  • the above-mentioned 16 first circuit boards 11 are divided into 8 groups of circuit board units, and each group of circuit board units includes two adjacent first circuit boards 11 .
  • the first plane M and the second plane N are different planes, so that the orthogonal system architecture 10 can be provided with more first circuit boards 11 .
  • the first plane M and the second plane N may be the same plane under the condition that too many first circuit boards 11 are not required. Specifically, it can be set according to the actual application scenario, and details will not be repeated here.
  • first circuit boards 11 are connected to eight first connectors 13 (only one first connector 13 is schematically shown in FIG. 13 ), each The first circuit board 11 is provided with two chip components 111 and two board connectors 150b.
  • the first connector 13 has 96 pairs of differential lines, and the board end connector 150b has 24 pairs of 96 pairs of differential lines.
  • the four board end connectors 150b of the two first circuit boards 11 of the same group of circuit board units can be electrically connected to the same first connector 13, so that the first circuit board 11 can be connected along the
  • the space on both sides of the first direction A makes the orthogonal system architecture 10 applicable to a multi-chip scenario and provides a larger PCB layout space.
  • the number of high-speed SerDes channels of the chip needs to be greater than or equal to the number of high-speed SerDes links required.
  • the redundant high-speed SerDes channels can be used as relays.
  • FIG. 14 is another schematic structural diagram of an orthogonal system architecture in an embodiment of the present application.
  • the orthogonal system architecture 10 may include a first chip assembly 111a and a second chip assembly 111b, wherein the second chip assembly 111b may be disposed on the first chip assembly 111a away from the first connection One side of device 13.
  • the first chip component 111a may include a first pin P1 and a second pin P2
  • the second chip component 111b may include a third pin P3 and a fourth pin P4.
  • the orthogonal system architecture 10 includes a plurality of flexible connection assemblies 15 , such as a first flexible connection assembly 151 , a second flexible connection assembly 152 and a third flexible connection assembly 153 as shown in FIG. 14 .
  • the first pin P1 is electrically connected to the first flexible connection component 151
  • the second pin P2 is electrically connected to the second flexible connection component 152
  • the third pin P3 is electrically connected to the third flexible connection component 153
  • the second pin P3 is electrically connected to the third flexible connection component 153.
  • the four pins P4 are electrically connected to the second pin P2 through the wiring of the first circuit board 11 .
  • the first chip assembly 111a When the first chip assembly 111a has redundant high-speed SerDes channels, these redundant high-speed SerDes channels can be used as relays, thereby forming a second chip assembly 111b, the first chip assembly 111a, the second flexible connection
  • the high-speed SerDes link formed by the connector 13 and the second connector 14 is used to reduce the length of the flexible connection component 15 from the second chip component 111b to the first connector 13 and reduce system loss.
  • the specific number of the above-mentioned pins is not limited.
  • the first chip assembly 111a may include 512 pins, among which 384 pins are the first pins P1, and the remaining 128 pins are the second pins P2.
  • the second chip assembly 111b may include 512 pins, among which 372 pins are the third pins P3 , 12 pins are the fourth pins P4 , and the remaining pins are not electrically connected to the first connector 13 .
  • FIG. 15 is another schematic structural diagram of an orthogonal system architecture in an embodiment of the present application.
  • the orthogonal system architecture 10 may include a third chip component 111c and a fourth chip component 111d, and the fourth chip component 111d is disposed on the third chip component 111c away from the first connector 13 side.
  • the third chip assembly 111c may include fifth pins P5, sixth pins P6, and seventh pins P7, and the fourth chip assembly 111d may include eighth pins P8, ninth pins P9, and tenth pins P10.
  • the orthogonal system architecture 10 includes a plurality of flexible connection assemblies 15 .
  • the above-mentioned plurality of flexible connection components 15 may include a fourth flexible connection component 154 , a fifth flexible connection component 155 , a sixth flexible connection component 156 and a seventh flexible connection component 157 .
  • the fifth pin P5 is electrically connected to the fourth flexible connection component 154
  • the sixth pin P6 is electrically connected to the fifth flexible connection component 155
  • the eighth pin P8 is electrically connected to the sixth flexible connection component 156
  • the sixth pin P6 is electrically connected to the fifth flexible connection component 156.
  • the nine pins P9 are electrically connected to the seventh flexible connection assembly 157, the seventh pin P7 is electrically connected to the ninth pin P9 through the wiring of the first circuit board 11, and the tenth pin P10 is electrically connected to the ninth pin P9 through the wiring of the first circuit board 11.
  • the wire is electrically connected to the sixth pin P6.
  • the third chip assembly 111c and the fourth chip assembly 111d have redundant high-speed SerDes channels
  • these redundant high-speed SerDes channels can be used as relays, so that the third chip assembly 111c, the fourth chip assembly 111d, and the fourth chip assembly 111d can be formed
  • the first high-speed SerDes link composed of seven flexible connection components 157, the first connector 13 and the second connector 14, and the fourth chip component 111d, the third chip component 111c, the fifth flexible connection component 155, the first connection
  • the second high-speed SerDes link composed of the connector 13 and the second connector 14 can also reduce the wiring length and design complexity of the first circuit board 11, and can reduce the use of the first circuit board 11 for the high-speed SerDes link.
  • the number of layers of the road thereby reducing the production cost and system loss of the orthogonal system architecture 10, and reducing the power consumption of the network device 01.
  • the third chip assembly 111c may include 512 pins, wherein 372 pins are the fifth pin P5, 128 pins are the sixth pin P6, and 12 pins are the sixth pin P6. Seven pins P7.
  • the fourth chip assembly 111d may include 512 pins, among which 372 pins are the eighth pin P8, 128 pins are the ninth pin P9, and 12 pins are the tenth pin P10.
  • FIG. 16 is another schematic structural diagram of an orthogonal system architecture in an embodiment of the present application. As shown in FIG. 16 , in some embodiments of the present application, the orthogonal system architecture 10 further includes a first angled connector 18 .
  • the first angled connector 18 is disposed on the first circuit board 11 , and the first angled connector 18 can be electrically connected to the chip assembly 111 through the wiring of the first circuit board 11 .
  • the orthogonal system architecture 10 may further include a second angled connector plugged into the first angled connector 18 .
  • the second angled connector is disposed on the second circuit board 12 and is electrically connected to the second circuit board 12 .
  • the first angled connector 18 is mated with the second angled connector to achieve vertical inter-plugging between the first circuit board 11 and the second circuit board 12, thereby reducing the number of flexible transmission lines 150a
  • the quantity can further reduce the space between the fixing plate 16 and the first circuit board 11 and improve the space utilization rate of the network device 01 .
  • the above-mentioned first angled connector 18 may be an angled male connector, and the above-mentioned second angled connector may be an angled female connector.
  • the above-mentioned first angled connector 18 may be an angled female connector, and the above-mentioned second angled connector may be an angled male connector.
  • references to “one embodiment” or “some embodiments” or the like in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application.
  • the phrases “in one embodiment”, “in another embodiment”, “in some embodiments”, “in other embodiments”, “in “In some other embodiment” etc. do not necessarily all refer to the same embodiment, but mean “one or more but not all of the embodiments” unless specifically emphasized otherwise.
  • the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless specifically stated otherwise.

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Abstract

本申请提供一种正交系统架构以及网络设备。正交系统架构包括第一电路板、第二电路板、第一连接器、第二连接器和柔性连接组件。第一电路板与第二电路板相互垂直设置。第一电路板设置有芯片组件，芯片组件与第一电路板电连接。第一连接器通过柔性连接组件与芯片组件电连接，第二连接器设置于第二电路板并与第二电路板电连接。第一连接器与第二连接器插接，以电连接第一电路板与第二电路板。该正交系统架构在具体应用时，芯片组件、柔性连接组件、第一连接器和第二连接器形成第一电路板和第二电路板之间的高速SerDes链路，以减小第一电路板的PCB走线长度以及走线设计的复杂度，从而降低系统损耗和功耗，实现低损耗低功耗的网络设备。

Description

一种正交系统架构以及网络设备
相关申请的交叉引用
本申请要求在2021年11月23日提交中国专利局、申请号为202111394994.6、申请名称为“一种正交系统架构以及网络设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及网络设备技术领域，尤其涉及一种正交系统架构以及网络设备。
背景技术
随着网络业务的不断发展，对网络设备交换能力的要求也越来越高。在网络设备中，通常采用高速串行器/解串器(Serializer/Deserializer，SerDes)链路来提高信号传输速率。然而，随着高速SerDes速率的提高，高速SerDes链路的损耗也逐渐增加。
目前减少高速SerDes链路损耗的方法主要是在交换网板或线卡板设置多个时钟数据恢复(Clock Data Recovery，CDR)芯片。然而，由于CDR芯片需要额外的外围电路，例如电源电路、时钟电路等，这会导致交换网板的印制电路板(Printed Circuit Board，PCB)布局、层数和走线的复杂度增加，从而增加制作成本。另外，由于CDR芯片在工作状态下会发热，还需要设置额外的散热器对CDR芯片进行散热，但是过多的CDR会使网络设备的系统功耗和噪声增加。因此，如何实现低损耗低功耗的网络设备是亟待解决的问题。
发明内容
本申请提供了一种正交系统架构以及网络设备，以降低系统损耗和功耗，实现低损耗低功耗的网络设备。
第一方面，本申请提供了一种正交系统架构。正交系统架构包括第一电路板、第二电路板、第一连接器、第二连接器和柔性连接组件。具体的，第一电路板与第二电路板可以相互垂直设置，形成垂直架构。第一电路板设置有芯片组件，芯片组件与第一电路板电连接。第一连接器可以通过柔性连接组件与芯片组件电连接，第二连接器设置于第二电路板并与第二电路板电连接。第一连接器与第二连接器可以插接，实现第一电路板与第二电路板的电连接。
上述正交系统架构应用于网络设备时，第一电路板和第二电路板之间的高速SerDes链路可以由芯片组件、柔性连接组件、第一连接器和第二连接器形成，以减小第一电路板的PCB走线长度及其设计复杂度，并且减少第一电路板用于高速SerDes链路的层数，从而降低正交系统架构的制作成本，并降低网络设备的系统损耗和功耗。
具体设置柔性连接组件时，柔性连接组件可以包括柔性传输线。柔性传输线的一端与第一连接器电连接，另一端与芯片组件电连接。具体的，柔性传输线可以与芯片组件直接连接，或者柔性传输线也可以与芯片组件间接连接。利用柔性传输线的柔性和灵活性，可以根据实际应用场景来设置第一电路板的具体位置，而不会将第一电路板局限于固定位置。
在本申请的技术方案中，上述柔性传输线的具体类型可以不作限制，例如可以为柔性线缆、柔性电路板或刚柔板。
具体设置时，柔性连接组件还可以包括板端连接器。板端连接器设置于第一电路板。板端连接器可以通过第一电路板的走线与芯片组件电连接。上述柔性传输线的一端可以与第一连接器电连接，另一端可以与板端连接器电连接。在该技术方案中，芯片组件与板端连接器之间的高速SerDes链路采用PCB走线，板端连接器与第一连接器之间的高速SerDes链路采用柔性传输线。这样不仅可以减小芯片组件与第一连接器之间的PCB走线，并且由于板端连接器可以通过PCB走线与芯片组件的引脚连接，因此不需要对芯片组件本身的结构进行改变。这样，不同型号的芯片组件都可以应用于正交系统架构，从而增强正交系统架构的通用性。
上述板端连接器的具体位置不作限制。例如，在一个具体的技术方案中，板端连接器可以设置于芯片组件周侧，以使板端连接尽量靠近芯片组件，从而减小板端连接器到芯片组件的PCB走线长度。
在具体的技术方案中，上述板端连接器可以包括第一板端连接器和第二板端连接器。第一板端连接器可以设置于第一电路板的一侧表面，第二板端连接器可以设置于第一电路板背离第一板端连接器的一侧表面。一方面，这种设置可以缩短第一板端连接器和第二板端连接器分别到芯片组件的总PCB走线长度，以降低系统损耗；另一方面，可以利用第一电路板背离芯片组件的一侧的空间，从而提高第一电路板的空间利用率。
具体设置第一板端连接器和第二板端连接器时，第一板端连接器在第一电路板上的投影为第一投影，第二板端连接器在第一电路板上的投影为第二投影。第一投影可以与第二投影重叠，以进一步提高正交系统架构的空间利用率，并且因此可以减小第一电路板的尺寸。
在具体的技术方案中，板端连接器朝向第一连接器的一侧可以设置有输出端口，柔性传输线可以与输出端口直接电连接，以减小柔性传输线的长度，从而降低系统损耗。另外，由于长度减小，柔性传输线的占用空间也减小，从而进一步提高正交系统架构的空间利用率。
具体设置上述芯片组件时，芯片组件可以包括芯片基板、以及设置于芯片基板的芯片本体。芯片本体与芯片基板的走线电连接。柔性传输线的一端可以与第一连接器电连接，另一端可以与芯片基板电连接，从而可以实现芯片组件与第一连接器之间的零PCB走线设置，进一步降低正交系统架构的损耗。
在另外的技术方案中，第一电路板也可以具有导电过孔。柔性传输线通过导电过孔与芯片组件电连接，而不需要改变芯片组件的结构。这样，在不改变芯片组件的结构的情况下，芯片组件与第一连接器之间也可以实现零PCB走线设置，从而降低正交系统架构的损耗。
当第一电路板具有导电过孔时，柔性传输线可以直接与导电过孔电连接。或者，也可以在第一电路板设置转接座。转接座位于第一电路板背离芯片组件的一侧。芯片组件通过导电过孔与转接座电连接，柔性传输线与转接座电连接。
在其他的技术方案中，正交系统架构还可以包括固定板，第一连接器可以设置于固定板。固定板设置于第一电路板和第二电路板之间，并且固定板与第一电路板间隔设置。这样可以将第一连接器与第一电路板间隔设置，使第一电路板的具体位置可以根据实际应用 场景来设置，而不受第二电路板、第二连接器和第一连接器的位置限制。
具体设置固定板时，固定板所在的平面为第一平面，第一电路板所在的平面为第二平面。第一平面与第二平面可以为同一平面，这样，第一电路板可以与固定板一一对应设置，便于正交系统架构的组装和拆卸。或者，第一平面与第二平面也可以为不同的平面，这样，对应一个固定板，可以设置多个层叠的第一电路板，从而提高正交系统架构的空间利用率。
在具体的技术方案中，正交系统架构可以包括多个第一连接器，这些第一连接器可以沿第一方向排列。第一电路板设置有多个芯片组件，这些芯片组件可以沿第二方向排列。其中，第一方向垂直于第二方向。这样，每个芯片组件到第一连接器的柔性连接组件可以避免在第一电路板所在的平面上的投影相互交叉；并且可以减小所有芯片组件到第一连接器的高速SerDes链路的总长度，从而降低系统损耗。
上述多个芯片组件可以包括第一芯片组件和第二芯片组件，第二芯片组件可以设置于第一芯片组件远离第一连接器的一侧。第一芯片组件可以包括第一引脚和第二引脚，第二芯片组件可以包括第三引脚和第四引脚。正交系统架构包括多个柔性连接组件。上述多个柔性连接组件可以包括第一柔性连接组件、第二柔性连接组件和第三柔性连接组件。具体设置时，第一引脚与第一柔性连接组件电连接，第二引脚与第二柔性连接组件电连接，第三引脚与第三柔性连接组件电连接，第四引脚通过第一电路板的走线与第二引脚电连接。当第一芯片组件具有多余的高速SerDes通道时，这些多余的高速SerDes通道可以用作中继，从而形成由第二芯片组件、第一芯片组件、第二柔性连接组件、第一连接器和第二连接器组成的高速SerDes链路，以减小第二芯片组件到第一连接器的柔性连接组件长度，降低系统损耗。
或者，上述多个芯片组件也可以包括第三芯片组件和第四芯片组件，第四芯片组件设置于第三芯片组件远离第一连接器的一侧。第三芯片组件可以包括第五引脚、第六引脚和第七引脚，第四芯片组件可以包括第八引脚、第九引脚和第十引脚。正交系统架构包括多个柔性连接组件。上述多个柔性连接组件可以包括第四柔性连接组件、第五柔性连接组件、第六柔性连接组件和第七柔性连接组件。具体设置时，第五引脚与第四柔性连接组件电连接，第六引脚与第五柔性连接组件电连接，第八引脚与第六柔性连接组件电连接，第九引脚与第七柔性连接组件电连接，第七引脚通过第一电路板的走线与第九引脚电连接，第十引脚通过第一电路板的走线与第六引脚电连接。当第三芯片组件和第四芯片组件分别具有多余的高速SerDes通道时，这些多余的高速SerDes通道可以用作中继，从而可以形成由第三芯片组件、第四芯片组件、第七柔性连接组件、第一连接器和第二连接器组成的第一高速SerDes链路，以及由第四芯片组件、第三芯片组件、第五柔性连接组件、第一连接器和第二连接器组成的第二高速SerDes链路，这样也可以减小第一电路板的PCB走线长度及其设计复杂度，并且可以减少第一电路板用于高速SerDes链路的层数，从而降低正交系统架构的制作成本以及系统损耗，并降低网络设备功耗。
另外，上述正交系统架构还可以包括第一弯式连接器和第二弯式连接器。具体的，第一弯式连接器可以设置于第一电路板。第一弯式连接器可以通过第一电路板的走线与芯片组件电连接。第二弯式连接器可以设置于第二电路板，并与第二电路板电连接。第一弯式连接器与第二弯式连接器可以直接插接，从而实现第一电路板与第二电路板的电连接，从而可以减少柔性连接组件的数量，进而可以减小第一电路板与第二电路板之间的空间。
上述第一弯式连接器可以为弯公连接器，上述第二弯式连接器可以为弯母连接器。或 者，上述第一弯式连接器可以为弯母连接器，上述第二弯式连接器可以为弯公连接器。
此外，第一电路板还可以设置有电源模块。电源模块可以设置于第一电路板背离芯片组件的一侧，电源模块通过第一电路板的走线与芯片组件电连接。利用第一电路板背离芯片组件一侧的空间，电源模块可以不占用芯片组件在第一电路板上的空间，从而提高第一电路板的空间利用率。
上述芯片组件在第一电路板上的投影为第三投影，电源模块在第一电路板上的投影为第四投影。第三投影至少部分与第四投影重合，这样可以减少电源模块到芯片组件的电阻，并且降低第一电路板中制作电源走线的层数。
在本申请的技术方案中，第一电路板和第二电路板的具体类型不限。例如，第一电路板可以为交换网板，第二电路板可以为线卡板。或者，第一电路板可以为线卡板，第二电路板可以为交换网板。
第二方面，本申请提供了一种网络设备，包括第一方面的正交系统架构。在正交系统架构中，第一电路板和第二电路板之间的高速SerDes链路可以由芯片组件、柔性连接组件、第一连接器和第二连接器形成，以减小第一电路板的PCB走线长度及其设计复杂度，并且减少第一电路板用于高速SerDes链路的层数，从而降低正交系统架构的制作成本，并降低网络设备的系统损耗和功耗。
附图说明
图1为本申请实施例中网络设备的结构框图；
图2为本申请实施例中第一连接器和柔性连接组件的一种结构示意图；
图3为本申请实施例中第一连接器和柔性连接组件的另一种结构示意图；
图4为本申请实施例中第一电路板与柔性连接组件的一种结构示意图；
图5为本申请实施例中第一电路板与柔性连接组件的另一种结构示意图；
图6为本申请实施例中第一电路板与柔性连接组件的另一种结构示意图；
图7为本申请实施例中正交系统架构的另一种结构示意图；
图8为本申请实施例中正交系统架构的另一种结构示意图；
图9为本申请实施例中正交系统架构的另一种结构示意图；
图10为本申请实施例中正交系统架构的另一种结构示意图；
图11为本申请实施例中正交系统架构的另一种结构示意图；
图12为本申请实施例中正交系统架构的另一种结构示意图；
图13为本申请实施例中正交系统架构的另一种结构示意图；
图14为本申请实施例中正交系统架构的另一种结构示意图；
图15为本申请实施例中正交系统架构的另一种结构示意图；
图16为本申请实施例中正交系统架构的另一种结构示意图。
附图标记：
01-网络设备；                     10-正交系统架构；
11-第一电路板；                   12-第二电路板；
13-第一连接器；                   14-第二连接器；
15-柔性连接组件；                 16-固定板；
17-散热器；                       18-第一弯式连接器；
111-芯片组件；                     112-芯片基板；
113-芯片本体；                     114-导电过孔；
115-电源模块；                     116-焊盘；
117-转接座；                       111a-第一芯片组件；
111b-第二芯片组件；                111c-第三芯片组件；
111d-第四芯片组件；                150a-柔性传输线；
150b-板端连接器；                  151-第一柔性连接组件；
152-第二柔性连接组件；             153-第三柔性连接组件；
154-第四柔性连接组件；             155-第五柔性连接组件；
156-第六柔性连接组件；             157-第七柔性连接组件；
1501-刚板印制电路；                1502-柔板印制电路；
1503-第一板端连接器；              1504-第二板端连接器。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
目前，网络设备的系统架构通常采用正交系统架构。具体的正交系统架构可以包括线卡板和交换网板，其中，线卡板和交换网板垂直设置，形成垂直架构。具体的，线卡板设置有线卡板芯片和线卡板连接器，线卡板芯片通过线卡板的PCB走线与线卡板连接器连接。交换网板设置有交换网板芯片和交换网板连接器，交换网板芯片通过交换网板的PCB走线与交换网板连接器连接。
现有的正交系统架构包括有背板和无背板两种方式。对于有背板的正交系统架构，线卡板和交换网板之间设置有背板，该背板即中置背板。然而，无论正交系统架构是否有背板，线卡板和交换网板的PCB走线都过长。例如，对于尺寸为800mm-1200mm的交换网板，芯片与交换网板连接器之间的PCB走线可能长达25英寸，导致系统损耗和功耗较大。
为了解决交换网板的PCB走线损耗的问题，目前采用在交换网板或线卡板设置多个CDR芯片。然而，由于CDR芯片需要额外的电源电路、时钟电路等，因此导致PCB走线设计的复杂度增加，制作成本增加；此外，这些CDR芯片本身还需要散热，使得系统架构需要增加散热器，导致系统功耗和噪声增加。
基于此，本申请实施例提供了一种正交系统架构以及网络设备，以降低系统损耗和功耗，实现低损耗低功耗的网络设备。
图1为本申请实施例中网络设备的结构框图。如图1所示，网络设备01包括正交系统架构10。在本申请的实施例中，网络设备01的结构类型不作具体限制，例如可以为框架式网络设备或者盒式网络设备。另外，网络设备01的类型也不作具体限制，例如可以为交换机、服务器或路由。正交系统架构10包括第一电路板11、第二电路板12、第一连接器13、第二连接器14和柔性连接组件15。具体的，第一电路板11和第二电路板12相互垂直设置，以实现垂直架构。第一电路板11设置有芯片组件111，芯片组件111与第一电路板11电连接。第一连接器13可以通过柔性连接组件15与芯片组件111电连接。第二连接器14设置于第二电路板12，并且与第二电路板12电连接。在组装正交系统架构10时，第一连接器13可以与第二连接器14插接，从而实现第一电路板11和第二电路板12 的电连接。需要说明的是，图1中的柔性连接组件15仅是示意图，并不用于限定柔性连接组件15的数量、结构以及与其他部件之间的位置。
在正交系统架构10具体应用时，芯片组件111、柔性连接组件15、第一连接器13和第二连接器14可以形成第一电路板11和第二电路板12之间的高速SerDes链路，提升系统高速信号传输性能。高速SerDes链路可以减小第一电路板11的PCB走线长度以及走线设计的复杂度，从而降低正交系统架构10的制作成本以及系统损耗，并降低网络设备01功耗。另外，由于柔性连接组件15的柔性和灵活性特征，可以根据实际应用场景来设置第一电路板11的位置，使正交系统架构10能够应用于更多的场景。
上述第一电路板11和第二电路板12的具体类型不限，例如可以为线卡板、交换网板或处理板。例如，在一些实施例中，第一电路板11可以为交换网板，第二电路板12可以为线卡板。在其他一些实施例中，第一电路板11可以为线卡板，第二电路板12可以为交换网板。在本申请的实施例中，第一电路板11和第二电路板12的具体数量不限，例如，第一电路板11的数量可以为1个、2个、4个、8个、10个或16个等，第二电路板12的数量可以为1个、2个、4个、8个、10个或16个等。以16槽位的网络设备01为例，在一个具体的实施例中，正交系统架构10可以包括16个第一电路板11和8个第二电路板12。具体的，上述16个第一电路板11可以沿图1中垂直于页面的方向层叠设置，上述8个第二电路板12可以沿图1中箭头所示的竖直方向层叠设置。为了便于说明，除非有明确的指示，下文以一个第一电路板11为示例进行说明。
图2为本申请实施例中第一连接器和柔性连接组件的一种结构示意图，图3为本申请实施例中第一连接器和柔性连接组件的另一种结构示意图。如图2和图3所示，柔性连接组件15可以包括柔性传输线150a。柔性传输线150a的一端可以与第一连接器13电连接，另一端可以与芯片组件111电连接。采用柔性传输线150a连接第一连接器13和芯片组件111，可以利用柔性传输线150a的灵活性来设置第一电路板11的具体位置，而不需要将第一电路板11局限于某一固定位置。
在具体设置柔性传输线150a时，柔性传输线150a的类型可以不作限制。例如，如图2所示，柔性传输线150a可以为柔性线缆。例如，在一个具体的实施例中，柔性线缆可以为高速线缆，高速线缆具有低损耗和高带宽的特性。在相同长度的情况下，高速线缆的损耗约为PCB走线损耗的1/4。高速线缆可以直接插接于第一连接器13的输入端口。
或者，柔性传输线150a也可以为柔性电路板(Flexible Printed Circuit，FPC)，其损耗也比PCB走线的损耗更低。FPC可以直接与第一连接器13的输入端口电连接。FPC与第一连接器13的输入端口的连接方式不作具体限制，例如可以为焊接或卡接等方式。在具体设置FPC时，FPC可以包括一个或多个信号层。当FPC包括多个信号层时，相邻两个信号层之间可以设置有屏蔽层，因此，FPC内的各个信号层的信号传输可以互不影响。这样，一个第一连接器13可以通过一个FPC与芯片组件111的多个引脚连接，从而实现“一分多”互连的系统架构。另外，由于FPC具有更高的布线密度，并且还可以按照布线路径设计成需要的形状。柔性传输线150a采用FPC，有利于降低风阻和组装，并且可以提升系统的散热能力，降低系统的设计成本。需要说明的是，在本申请的实施例中，“多个”是指数量大于或等于2。
如图3所示，柔性传输线150a也可以为刚柔板。具体的，刚柔板包括刚板印制电路1501和柔板印制电路1502。在一个具体的实施例中，刚柔板可以包括一个刚板印制电路 1501。刚板印制电路1501可以压接于第一连接器13，并与第一连接器13电连接。柔板印制电路1502可以压接于刚板印制电路1501背离第一连接器13的一侧，并与刚板印制电路1501电连接。也就是说，柔板印制电路1502可以通过刚板印制电路1501与第一连接器13电连接。在另一个具体的实施例中，刚柔板也可以包括两个刚板印制电路1501，即第一刚板印制电路和第二刚板印制电路。其中，第一刚板印制电路可以压接于第一连接器13，并与第一连接器13电连接。柔板印制电路1502可以压接于第一刚板印制电路背离第一连接器13的一侧，并与第一刚板印制电路电连接。第二刚板印制电路可以压接于柔板印制电路1502背离第一刚板印制电路的一侧，并与第一刚板印制电路和柔板印制电路1502电连接。也就是说，第一刚板印制电路和第二刚板印制电路压接于柔板印制电路1502的两侧，并且柔板印制电路1502通过第一刚板印制电路与第一连接器13连接。
上述实施例中，刚板印制电路1501的出线方向不作具体限制。例如，刚板印制电路1501的出线方向可以朝向第一电路板11；或者，出线方向也可以朝向其他方向，如图3所示的竖直方向。
请继续参考图3，由于柔板印制电路1502可以包括多个信号层，且每个信号层的信号传输互不影响，因此，柔板印制电路1502与芯片组件111电连接的一端也可以形成多个分叉结构，这些分叉结构可以分别与芯片组件111的不同引脚电连接。
图4为本申请实施例中第一电路板与柔性连接组件的一种结构示意图。如图4所示，在第一电路板11中，芯片组件111可以包括芯片基板112和芯片本体113。需要说明的是，在本申请的实施例中，芯片本体113为晶圆被切割形成的裸片(die)。裸片具有用于封装的压焊点，裸片通过压焊点与芯片基板112的走线电连接。在该实施例中，柔性传输线150a的一端可以与第一连接器13电连接，另一端与芯片基板112电连接。因此，芯片组件111与第一连接器13可以仅通柔性传输线150a电连接，从而可以实现芯片组件111与第一连接器13之间的零PCB走线设置，即芯片组件111不需要通过第一电路板11的走线与第一连接器13电连接，从而可以减少正交系统架构10的损耗。这样，第一电路板11只需要向芯片组件111提供电源等信号载体，可以进一步降低第一电路板11的制作成本和层数设计。此外，芯片组件111与第一连接器13通过柔性传输线150a实现互连，可以适用于112Gbit/s或224Gbit/s等更高速率的应用场景。
图5为本申请实施例中第一电路板与柔性连接组件的另一种结构示意图，图6为本申请实施例中第一电路板与柔性连接组件的另一种结构示意图。如图5和图6所示，在其他一些实施例中，第一电路板11具有导电过孔114，柔性传输线150a可以通过导电过孔114与芯片组件111电连接。具体的，如图5所示，在一个具体的实施例中，第一电路板11的两侧表面分别设置有焊盘116。焊盘116可以覆盖导电过孔114，并与导电过孔114电连接。芯片组件111可以设置于第一电路板11的一侧，并直接与该侧的焊盘116电连接。柔性传输线150a可以设置于第一电路板11背离芯片组件111的一侧，并直接与该侧的焊盘116电连接。或者，如图6所示，在另一个具体的实施例中，第一电路板11的两侧表面分别设置有焊盘116。焊盘116可以覆盖导电过孔114，并与导电过孔114电连接。芯片组件111可以设置于第一电路板11的一侧，并直接与该侧的焊盘116电连接。第一电路板11背离芯片组件111的一侧可以设置有转接座117，转接座117与该侧的焊盘116电连接。柔性传输线150a可以直接与转接座117电连接，从而通过转接座117和导电过孔114实现柔性传输线150a与芯片组件111的电连接。上述实施例均可以实现芯片组件111与第一连 接器13之间的零PCB走线，从而减少正交系统架构10的损耗和功耗。
图7为本申请实施例中正交系统架构的另一种结构示意图，图8为本申请实施例中正交系统架构的另一种结构示意图。如图7和图8所示，在本申请的其他实施例中，柔性传输线150a也可以与芯片组件111间接连接。第一电路板11可以设置有板端连接器150b。板端连接器150b可以通过第一电路板11的走线与芯片组件111电连接。柔性传输线150a的一端可以与第一连接器13电连接，另一端可以与板端连接器150b电连接。其中，板端连接器150b可以通过螺钉或压接直接安装于第一电路板11。在该实施例中，芯片组件111与第一连接器13之间采用PCB走线与柔性连接组件15的组合方式电连接，而不需要对芯片组件111的结构进行改变，不同型号的芯片组件111都可以应用于正交系统架构10，从而可以增强正交系统架构10的通用性。此外，板端连接器150b可以靠近芯片组件111设置，从而减少PCB走线长度，以减少系统损耗。
在具体的实施例中，第一电路板11可以设置有多个板端连接器150b。这些板端连接器150b可以设置于芯片组件111的周侧。换句话说，板端连接器150b到芯片组件111的距离，小于板端连接器150b到第一电路板11边缘的距离，以使板端连接尽量靠近芯片组件111，从而减小板端连接器150b到芯片组件111的PCB走线长度。例如，如图7所示，多个板端连接器150b可以设置为两行。两行板端连接器150b设置于芯片组件111的两侧，并沿第二方向B延伸。或者，如图8所示，多个板端连接器150b也可以设置为四行。四行板端连接器150b设置于芯片组件111的两侧，并沿第二方向B延伸。对于芯片组件111的一侧，两行板端连接器150b可以交错设置和/或对齐设置。当多个板端连接器150b交错设置时，每个板端连接器150b的输出端口可以设置于背离芯片组件111的一侧。这样，这些板端连接器150b与第一连接器13之间的柔性传输线150a不会交叉，并且具有较大的理线空间，便于正交系统架构10的组装和拆卸。
请继续参考图7和图8，正交系统架构10可以包括沿第一方向A排列的多个第一连接器13。第一电路板11可以设置有多个芯片组件111，这些芯片组件111可以沿第二方向B排列。其中，第一方向A垂直于第二方向B，这样可以避免每个芯片组件111到第一连接器13的柔性连接组件15，在第一电路板11所在的平面上的投影交叉；并且可以减小所有芯片组件111到第一连接器13的高速SerDes链路的总长度，从而减小系统损耗。
在具体应用时，首先设置第二电路板12的位置。由于第二连接器14设置于第二电路板12，并且第一连接器13需要与第二连接器14插接，因此当第二电路板12的位置确定后，第一连接器13的安装位置也被确定，也就是说第一方向A也被确定。
图9为本申请实施例中正交系统架构的另一种结构示意图。如图9所示，板端连接器150b朝向第一连接器13的一侧设置有输出端口，柔性传输线150a可以与输出端口电连接。采用这种结构设计，板端连接器150b的出线方向可以直接朝向第一连接器13，而不需要设置垂直于第一电路板11的出线方向(如图9中的竖直方向)。
请继续参考图9。在一个具体的实施例中，板端连接器150b可以包括第一板端连接器1503和第二板端连接器1504。具体的，第二板端连接器1504可以设置于第一电路板11背离第一板端连接器1503的一侧表面。也就是说，第一板端连接器1503和第二板端连接器1504可以设置于第一电路板11的两侧，从而缩短芯片组件111到第一板端连接器1503和第二板端连接器1504的PCB走线长度，以降低系统损耗。第一板端连接器1503的输出端口为第一输出端口1505，第二板端连接器1504的输出端口为第二输出端口1506。为了 提高空间利用率，第一输出端口1505可以设置于第一板端连接器1503远离芯片组件111的一侧，第二输出端口1506可以设置于第二板端连接器1504朝向第二电路板12的一侧，并且第一输出端口1505和第二输出端口1506分别与柔性传输线150a电连接。
图10为本申请实施例中正交系统架构的另一种结构示意图。如图10所示，第一板端连接器1503也可以与第二板端连接器1504对帖于第一电路板11的两侧。也就是说，第一板端连接器1503在第一电路板11上的投影可以与第二板端连接器1504在第一电路板11上的投影重叠。
请继续参考图10。在一个具体的实施例中，正交系统架构10还可以包括散热器17。散热器17用于对芯片组件111进行散热，并且可以直接覆盖设置于同侧的芯片组件111和板端连接器150b，而不需要设置柔性连接组件15的避让结构，从而可以增加散热面积，提高系统架构的散热能力。并且，散热器17可以直接贴合芯片组件111的表面，使得散热器17的散热效率较高，而不需要设置过多的散热器17，从而可以降低系统噪声。
图11为本申请实施例中正交系统架构的另一种结构示意图。如图11所示，以第二板端连接器1504为例，第二板端连接器1504可以在朝向第一连接器13的一侧设置第二输出端口1506，而不是背离第一电路板11的一侧设置第二输出端口1506，从而可以减小第二板端连接器1504与柔性传输线150a的连接处的占用空间，增大柔性传输线150a的理线空间，进而根据具体需要可以将第一连接器13与第一电路板11之间的空间设置得较小。
图12为本申请实施例中正交系统架构的另一种结构示意图。如图12所示，第一电路板11还可以设置有电源模块115，电源模块115用于向芯片组件111提供电源。具体的，电源模块115可以设置于第一电路板11背离芯片组件111的一侧，电源模块115通过第一电路板11的走线与芯片组件111电连接。这种将芯片组件111和电源模块115设置于第一电路板11两侧的设计，一方面可以减少第一电路板11具有芯片组件111一侧的占用空间，提升第一电路板11的器件集成度，从而可以减小第一电路板11的面积；另一方面，将电源模块115设置于第一电路板11背离芯片组件111的一侧，可以使第一电路板11具有芯片组件111一侧具有更多的空间来设置其他的电子器件。
在一个具体的实施例中，芯片组件111在第一电路板11上的投影，与电源模块115在第一电路板11上的投影可以至少部分重合，这样可以减少电源模块115到芯片组件111的电阻，并且降低第一电路板11中制作电源走线的层数。因此，第一电路板11只需要安装芯片组件111、电源模块115以及板端连接器150b，而不需要设置CDR芯片，就可以实现低功耗低损耗的系统架构；并且也可以减小第一电路板11的大尺寸需求，简化第一电路板11的走线设计。具体的，如图12所示，在一个具体的实施例中，芯片组件111在第一电路板11上的投影，与电源模块115在第一电路板11上的投影可以中心重合。
请继续参考图12。在本申请的一些实施例中，正交系统架构10还可以包括固定板16。固定板16位于第一电路板11和第二电路板12之间。第一连接器13可以设置于固定板16，使第一连接器13与第一电路板11间隔设置。这样，第一电路板11的具体位置可以根据实际应用场景来设置，而不受第二电路板12、第二连接器14和第一连接器13的位置限制。
具体设置固定板16时，固定板16所在的平面为第一平面M，第一电路板11所在的平面为第二平面N。如图12所示，第一平面M与第二平面N可以为同一平面，这样，第一电路板11可以与固定板16一一对应设置，便于正交系统架构10的组装和拆卸。
需要说明的是，第一平面M是固定板16简化后的平面。当固定板16的厚度可以忽略 时，第一平面M为固定板16的表面；当考虑固定板16的厚度时，第一平面M为固定板16厚度的中线所在的平面。第二平面N是第一电路板11简化后的平面。当第一电路板11的厚度可以忽略时，第二平面N为第一电路板11的表面；当考虑第一电路板11的厚度时，第二平面N为第一电路板11厚度的中线所在的平面。
图13为本申请实施例中正交系统架构的另一种结构示意图。如图13所示，第一平面M与第二平面N也可以为不同的平面，这样，对应一个固定板16，可以设置多个层叠的第一电路板11，从而提高正交系统架构10的空间利用率。
在上述实施例中，每个第一电路板11具有芯片组件111的一侧都可以设置对应的散热器17，用于对第一电路板11的发热电子器件进行散热。散热器17可以覆盖整个第一电路板11，从而增大散热面积，提高散热效率。
在具体应用中，根据应用场景的需要，可以分别设置芯片组件111的数量和型号、板端连接器150b的参数以及第二连接器14的参数。例如，在一个具体的实施例中，网络设备01可以包括16槽位机箱。机箱具有16个槽位。正交系统架构10包括1个第一电路板11和16个第二电路板12。第一电路板11设置有第一芯片组件111a和第二芯片组件111b。第一电路板11与16个第一连接器13电连接。每个第一连接器13具有96对差分线。第一电路板11设置有64个板端连接器150b，每个板端连接器150b具有24对差分线。每个第一连接器13可以通过柔性传输线150a与一个第一电路板11的4个板端连接器150b连接，其中两个板端连接器150b与第一芯片组件111a连接，另外两个板端连接器150b与第二芯片组件111b连接。
针对上述正交系统架构10，通过1536个柔性传输线150a将第一连接器13和芯片组件111连接，每个芯片组件111的SerDes通道大于或等于384个。下面的表1示出针对不同类型的网络设备01设置正交系统架构10的多个示例。需要注意的是，本申请的实施例并不限于这些示例，具体的，可以根据实际应用场景来进行不同的设置。
表1
Figure PCTCN2022107813-appb-000001
在上述实施例中，一个第一连接器13可以通过柔性传输线150a与多个板端连接器150b连接，实现“一分多”互连的系统架构，从而可以灵活设置柔性传输线150a的长度、以及板端连接器150b与芯片组件111之间的PCB走线长度，以降低系统损耗。
上述实施例中，每个第一连接器13可以与同一个第一电路板11的芯片组件111电连 接。或者，每个第一连接器13也可以与多个第一电路板11的芯片组件111电连接。例如，在一个具体的实施例中，正交系统架构10包括16个第一电路板11、8个第二电路板12、64个第一连接器13和64个第二连接器14。具体的，上述8个第二电路板12沿第一方向A层叠设置，上述16个第一电路板11沿垂直于第一方向A的方向层叠设置。每个第二电路板12设置有8个第二连接器14。正交系统架构10还包括固定板16，64个第一连接器13设置于固定板16。每个第一连接器13对应地与一个第二连接器14插接。上述16个第一电路板11分为8组电路板单元，每组电路板单元包括相邻的两个第一电路板11。在该实施例中，第一平面M与第二平面N为不同的平面，从而使正交系统架构10可以设置更多的第一电路板11。在本申请的其他实施例中，在不需要设置过多第一电路板11的情况下，第一平面M与第二平面N可以为同一平面。具体的，可以根据实际应用场景来进行设置，这里不再一一赘述。
请继续参考图13，针对上述每组电路板单元，两个第一电路板11连接至8个第一连接器13(图13中仅示意性地示出一个第一连接器13)，每个第一电路板11设置有2个芯片组件111以及2个板端连接器150b。第一连接器13具有96对差分线，板端连接器150b具有24对96对差分线。在连接高速SerDes链路时，同一组电路板单元的两个第一电路板11的4个板端连接器150b，可以与同一个第一连接器13电连接，从而可以第一电路板11沿第一方向A的两侧空间，进而使正交系统架构10可以适用于多芯片的场景，提供更大的PCB布局空间。
在实际应用中，芯片的高速SerDes通道数量需要大于等于需要的高速SerDes链路数量。当芯片的高速SerDes通道数量大于需要的高速SerDes链路数量时，多余高速SerDes通道可以用作中继。
图14为本申请实施例中正交系统架构的另一种结构示意图。如图14所示，在一些实施例中，正交系统架构10可以包括第一芯片组件111a和第二芯片组件111b，其中，第二芯片组件111b可以设置于第一芯片组件111a远离第一连接器13的一侧。具体的，第一芯片组件111a可以包括第一引脚P1和第二引脚P2，第二芯片组件111b可以包括第三引脚P3和第四引脚P4。正交系统架构10包括多个柔性连接组件15，如图14中所示的第一柔性连接组件151、第二柔性连接组件152和第三柔性连接组件153。具体设置时，第一引脚P1与第一柔性连接组件151电连接，第二引脚P2与第二柔性连接组件152电连接，第三引脚P3与第三柔性连接组件153电连接，第四引脚P4通过第一电路板11的走线与第二引脚P2电连接。当第一芯片组件111a具有多余的高速SerDes通道时，这些多余的高速SerDes通道可以用作中继，从而形成由第二芯片组件111b、第一芯片组件111a、第二柔性连接组件152、第一连接器13和第二连接器14组成的高速SerDes链路，以减小第二芯片组件111b到第一连接器13的柔性连接组件15长度，降低系统损耗。需要说明的是，上述引脚的具体数量不作限制。例如，在一个具体的实施例中，第一芯片组件111a可以包括512个引脚，其中，384个引脚为第一引脚P1，其余的128个引脚为第二引脚P2。第二芯片组件111b可以包括512个引脚，其中，372个引脚为第三引脚P3，12个引脚为第四引脚P4，其余的引脚不与第一连接器13电连接。
图15为本申请实施例中正交系统架构的另一种结构示意图。如图15所示，在其他一些实施例中，正交系统架构10可以包括第三芯片组件111c和第四芯片组件111d，第四芯片组件111d设置于第三芯片组件111c远离第一连接器13的一侧。第三芯片组件111c可 以包括第五引脚P5、第六引脚P6和第七引脚P7，第四芯片组件111d可以包括第八引脚P8、第九引脚P9和第十引脚P10。正交系统架构10包括多个柔性连接组件15。上述多个柔性连接组件15可以包括第四柔性连接组件154、第五柔性连接组件155、第六柔性连接组件156和第七柔性连接组件157。具体设置时，第五引脚P5与第四柔性连接组件154电连接，第六引脚P6与第五柔性连接组件155电连接，第八引脚P8与第六柔性连接组件156电连接，第九引脚P9与第七柔性连接组件157电连接，第七引脚P7通过第一电路板11的走线与第九引脚P9电连接，第十引脚P10通过第一电路板11的走线与第六引脚P6电连接。当第三芯片组件111c和第四芯片组件111d分别具有多余的高速SerDes通道时，这些多余的高速SerDes通道可以用作中继，从而可以形成由第三芯片组件111c、第四芯片组件111d、第七柔性连接组件157、第一连接器13和第二连接器14组成的第一高速SerDes链路，以及由第四芯片组件111d、第三芯片组件111c、第五柔性连接组件155、第一连接器13和第二连接器14组成的第二高速SerDes链路，这样也可以减小第一电路板11的走线长度及其设计复杂度，并且可以减少第一电路板11用于高速SerDes链路的层数，从而降低正交系统架构10的制作成本以及系统损耗，并降低网络设备01功耗。
在一个具体的实施例中，第三芯片组件111c可以包括512个引脚，其中，372个引脚为第五引脚P5，128个引脚为第六引脚P6，12个引脚为第七引脚P7。第四芯片组件111d可以包括512个引脚，其中，372个引脚为第八引脚P8，128个引脚为第九引脚P9，12个引脚为第十引脚P10。图16为本申请实施例中正交系统架构的另一种结构示意图。如图16所示，在本申请的一些实施例中，正交系统架构10还包括第一弯式连接器18。第一弯式连接器18设置于第一电路板11，第一弯式连接器18可以通过第一电路板11的走线与芯片组件111电连接。对应的，正交系统架构10还可以包括与第一弯式连接器18插接的第二弯式连接器。第二弯式连接器设置于第二电路板12，并与第二电路板12电连接。采用这种结构设计，第一弯式连接器18与第二弯式连接器插接配合，可以实现第一电路板11和第二电路板12之间的垂直互插，从而可以减少柔性传输线150a的数量，进而可以减小固定板16与第一电路板11之间的空间，提高网络设备01的空间利用率。
具体的，上述第一弯式连接器18可以为弯公连接器，上述第二弯式连接器可以为弯母连接器。或者，上述第一弯式连接器18可以为弯母连接器，上述第二弯式连接器可以为弯公连接器。
以上实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在另一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本 申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (21)

  1. 一种正交系统架构，其特征在于，包括第一电路板、第二电路板、第一连接器、第二连接器和柔性连接组件；
    所述第一电路板与所述第二电路板相互垂直设置；
    所述第一电路板设置有芯片组件，所述芯片组件与所述第一电路板电连接；
    所述第一连接器通过所述柔性连接组件与所述芯片组件电连接，所述第二连接器设置于所述第二电路板并与所述第二电路板电连接；
    所述第一连接器与所述第二连接器插接，以电连接所述第一电路板与所述第二电路板。
  2. 如权利要求1所述的正交系统架构，其特征在于，所述柔性连接组件包括柔性传输线，所述柔性传输线的一端与所述第一连接器电连接，另一端与所述芯片组件电连接。
  3. 如权利要求2所述的正交系统架构，其特征在于，所述柔性连接组件还包括板端连接器，所述板端连接器设置于所述第一电路板，所述板端连接器通过所述第一电路板的走线与所述芯片组件电连接；
    所述柔性传输线的一端与所述第一连接器电连接，另一端与所述板端连接器电连接。
  4. 如权利要求3所述的正交系统架构，其特征在于，所述板端连接器包括第一板端连接器和第二板端连接器，所述第二板端连接器设置于所述第一电路板背离所述第一板端连接器的一侧表面。
  5. 如权利要求4所述的正交系统架构，其特征在于，所述第一板端连接器在所述第一电路板上的投影为第一投影，所述第二板端连接器在所述第一电路板上的投影为第二投影，所述第一投影与所述第二投影重叠。
  6. 如权利要求2至5中任一项所述的正交系统架构，其特征在于，所述板端连接器朝向所述第一连接器的一侧设置有输出端口，所述柔性传输线与所述输出端口电连接。
  7. 如权利要求2至6中任一项所述的正交系统架构，其特征在于，所述板端连接器设置于所述芯片组件周侧。
  8. 如权利要求2所述的正交系统架构，其特征在于，所述芯片组件包括芯片基板，以及设置于所述芯片基板的芯片本体；
    所述柔性传输线的一端与所述第一连接器电连接，另一端与所述芯片基板电连接。
  9. 如权利要求2所述的正交系统架构，其特征在于，所述第一电路板具有导电过孔，所述柔性传输线通过所述导电过孔与所述芯片组件电连接。
  10. 如权利要求2所述的正交系统架构，其特征在于，所述第一电路板具有导电过孔，所述第一电路板设置有转接座，所述转接座设置于所述第一电路板背离所述芯片组件的一侧，所述芯片组件通过所述导电过孔与所述转接座电连接，所述柔性传输线与所述转接座电连接。
  11. 如权利要求2至10中任一项所述的正交系统架构，其特征在于，所述柔性传输线为柔性线缆或柔性电路板或刚柔板。
  12. 如权利要求1至11中任一项所述的正交系统架构，其特征在于，所述正交系统架构还包括固定板，所述固定板设置于所述第一电路板和所述第二电路板之间，且所述固定板与所述第一电路板间隔设置，所述第一连接器设置于所述固定板。
  13. 如权利要求12所述的正交系统架构，其特征在于，所述固定板所在的平面为第一 平面，所述第一电路板所在的平面为第二平面，所述第一平面与所述第二平面为同一平面或为不同平面。
  14. 如权利要求1至13中任一项所述的正交系统架构，其特征在于，所述正交系统架构包括沿第一方向排列的多个所述第一连接器；
    所述第一电路板设置有沿第二方向排列的多个所述芯片组件，所述第二方向垂直于所述第一方向。
  15. 如权利要求14所述的正交系统架构，其特征在于，所述正交系统架构包括多个所述柔性连接组件，多个所述柔性连接组件包括第一柔性连接组件、第二柔性连接组件和第三柔性连接组件；
    多个所述芯片组件包括第一芯片组件和第二芯片组件，所述第二芯片组件设置于所述第一芯片组件远离所述第一连接器的一侧，所述第一芯片组件包括第一引脚和第二引脚，所述第二芯片组件包括第三引脚和第四引脚；
    所述第一引脚与所述第一柔性连接组件电连接，所述第二引脚与所述第二柔性连接组件电连接，所述第三引脚与所述第三柔性连接组件电连接，所述第四引脚通过所述第一电路板的走线与所述第二引脚电连接。
  16. 如权利要求14所述的正交系统架构，其特征在于，所述正交系统架构包括多个所述柔性连接组件，多个所述柔性连接组件包括第四柔性连接组件、第五柔性连接组件、第六柔性连接组件和第七柔性连接组件；
    多个所述芯片组件包括第三芯片组件和第四芯片组件，所述第四芯片组件设置于所述第三芯片组件远离所述第一连接器的一侧，所述第三芯片组件包括第五引脚、第六引脚和第七引脚，所述第四芯片组件包括第八引脚、第九引脚和第十引脚；
    所述第五引脚与所述第四柔性连接组件电连接，所述第六引脚与所述第五柔性连接组件电连接，所述第八引脚与所述第六柔性连接组件电连接，所述第九引脚与所述第七柔性连接组件电连接，所述第七引脚通过所述第一电路板的走线与所述第九引脚电连接，所述第十引脚通过所述第一电路板的走线与所述第六引脚电连接。
  17. 如权利要求1至16中任一项所述的正交系统架构，其特征在于，所述正交系统架构还包括第一弯式连接器和第二弯式连接器；
    所述第一弯式连接器设置于所述第一电路板，所述第一弯式连接器通过所述第一电路板的走线与所述芯片组件电连接；
    所述第二弯式连接器设置于所述第二电路板，并与所述第二电路板电连接；
    所述第一弯式连接器与所述第二弯式连接器插接，以电连接所述第一电路板与所述第二电路板。
  18. 如权利要求1至17中任一项所述的正交系统架构，其特征在于，所述第一电路板设置有电源模块，所述电源模块设置于所述第一电路板背离所述芯片组件的一侧，所述电源模块通过所述第一电路板的走线与所述芯片组件电连接。
  19. 如权利要求18所述的正交系统架构，其特征在于，所述芯片组件在所述第一电路板上的投影为第三投影，所述电源模块在所述第一电路板上的投影为第四投影，所述第三投影至少部分与所述第四投影重合。
  20. 如权利要求1至19中任一项所述的正交系统架构，其特征在于，所述第一电路板为交换网板，所述第二电路板为线卡板；或者，所述第一电路板为线卡板，所述第二电路 板为交换网板。
  21. 一种网络设备，其特征在于，包括如权利要求1至20中任一项所述的正交系统架构。
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