WO2023092905A1

WO2023092905A1 - Clock link and electronic device

Info

Publication number: WO2023092905A1
Application number: PCT/CN2022/081535
Authority: WO
Inventors: 杨彬彬
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2021-11-29
Filing date: 2022-03-17
Publication date: 2023-06-01
Also published as: CN116185925A

Abstract

Provided in the present disclosure is a clock link. The clock link comprises multiple stages of buffer modules and a plurality of clock signal output ends, wherein each of the clock signal output ends corresponds to a corresponding buffer module, and the clock signal output end is electrically connected to an output end of the corresponding buffer module; the buffer module is configured to shape a clock signal, which is input into the buffer module, so as to obtain an output clock signal that meets a timing requirement corresponding to the buffer module; and in two adjacent stages of buffer modules, an input end of the latter stage of the buffer module is electrically connected to an output end of the former stage of the buffer module, and the time delay of a clock signal that is output by the latter stage of the buffer module relative to a clock signal that is input into a first-stage buffer module is greater than the time delay of a clock signal that is output by the former stage of the buffer module relative to the clock signal that is input into the first-stage buffer module. Further provided in the present disclosure is an electronic device.

Description

Clock Links, Electronics

Cross References to Related Applications

This application claims priority to Patent Application No. 202111435953.7 filed with the China Patent Office on November 29, 2021, the entire contents of which are hereby incorporated by reference.

technical field

The present disclosure relates to, but is not limited to, the field of electronic devices.

Background technique

As the integrated circuit manufacturing process enters the nanometer level, the working speed of such as serial/deserializer (SerDes) is getting faster and faster, and the clock corresponding to the demand is also faster and faster.

For high-speed serial/deserializers, the clock driver generally adopts a tree-structured clock link to perform multi-path buffering separately, and finally drives a super-large load in a lumped manner. However, at higher speeds, the above-mentioned tree structure occupies a larger area and consumes a lot of power.

Contents of the invention

The present disclosure provides a clock link and an electronic device including the clock link.

As a first aspect of the present disclosure, a clock link is provided, wherein the clock link includes a multi-level buffer module and a plurality of clock signal output terminals, and each of the clock signal output terminals corresponds to a corresponding buffer module, the clock signal output terminal is electrically connected to the output terminal of the corresponding buffer module; the buffer module is configured to shape the clock signal input to the buffer module to obtain an output that meets the timing requirements corresponding to the buffer module Clock signal, in the adjacent two-stage buffer module, the input end of the latter stage buffer module is electrically connected to the output end of the former stage buffer module, and the clock signal output by the latter stage buffer module is relatively input to the first stage buffer The time delay of the clock signal of the module is greater than the time delay of the clock signal output by the previous buffer module relative to the clock signal input to the first buffer module.

As a second aspect of the present disclosure, an electronic device is provided, the electronic device includes a clock link and a plurality of load modules, wherein the clock link is the clock link provided in the first aspect of the present disclosure, The clock signal input end of the load module is electrically connected to the clock signal output end of the buffer module corresponding to the load module.

Description of drawings

FIG. 1 is a schematic diagram of a clock chain provided by the present disclosure;

FIG. 2 is a schematic layout diagram of an electronic device provided by the present disclosure.

Detailed ways

In order for those skilled in the art to better understand the technical solution of the present disclosure, the clock link provided by the present disclosure and the electronic device including the clock link will be described in detail below with reference to the accompanying drawings.

Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the case of no conflict, each embodiment and each feature in the embodiment of the present disclosure can be combined with each other.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that when the terms "comprising" and/or "consisting of" are used in this specification, the stated features, integers, steps, operations, elements and/or components are specified to be present but not excluded to be present or Add one or more other features, integers, steps, operations, elements, components and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art and the present disclosure, and will not be interpreted as having idealized or excessive formal meanings, Unless expressly so limited herein.

As a first aspect of the present disclosure, a clock chain is provided, wherein, as shown in FIG. 1 , the clock chain includes a multi-level buffer module and a plurality of clock signal output terminals, each of the clock signal output Each corresponds to a corresponding buffer module, and the clock signal output end is electrically connected to the output end of the corresponding buffer module.

The buffer module is configured to shape the clock signal input to the buffer module to obtain an output clock signal that meets the timing requirements corresponding to the buffer module.

In adjacent two-stage buffer modules, the input end of the latter stage buffer module is electrically connected to the output end of the former stage buffer module, and the clock signal output by the latter stage buffer module is relative to the clock input to the first stage buffer module The time delay of the signal is greater than the time delay of the clock signal output by the previous buffer module relative to the clock signal input to the first buffer module.

In the clock chain, the input signal of the first-level buffer module is an unshaped signal (for ease of description, it will be referred to as the first signal hereinafter), after the shaping process of the first-level buffer module, the second The time delay of the clock signal output by the output terminal of the first-level buffer module relative to the first signal is Δt1, and the input signal of the second-level buffer module is the output signal of the first buffer module. After shaping processing by the second-level buffer module, The time delay of the output signal of the second-stage buffer module relative to the first signal is Δt1+Δt2, and so on, and the time delay of the output signal of the Mth-stage buffer module relative to the first signal is Δt1+Δt2+...+Δtm. It can be seen that the subsequent buffer module further buffers the signal on the basis of the time delay generated by the previous buffer module. Compared with simply buffering the first signal and obtaining the time delay of Δt1+Δt2+...+Δtm, further buffering the signal on the basis of the time delay generated by the previous buffer module saves more energy consumption .

In the embodiment shown in FIG. 1 , the clock link includes three-level buffer modules, which are respectively a first-level buffer module 110, a second-level buffer module 120, and a third-level buffer module 130, and the first-level buffer module 110 The output end is electrically connected to the input end of the second-level buffer module 120 , and the output end of the second-level buffer module 120 is electrically connected to the input end of the third-level buffer module 130 .

In the present disclosure, there is no special limitation on the specific number of clock signal output terminals in the clock chain. The number of clock signal outputs of a clock link is the same as the number of loads of the clock link. As an exemplary implementation manner, each level of buffer modules has a corresponding load, and the number of clock signal output ends of the clock link is also the same as the number of buffer modules.

For a buffer module connected with a load, in addition to shaping the clock signal input to the buffer module, the buffer module is also configured to increase the driving capability of the clock signal input to the buffer module, so that the buffer module The output clock signal can not only drive the buffer module of the next stage, but also drive the load of the buffer module of the current stage. In other words, the i-th buffer module is configured to increase the driving capability of the clock signal output by the i-1th buffer module, so that the clock signal output by the i-th buffer module can drive the load corresponding to the i-th buffer module, and i+1 stage buffer modules, wherein, i is a positive integer, and 2≤i≤M-1, and M is the total number of stages of buffer modules in the clock chain.

In the embodiment shown in FIG. 1 , the clock signal CK2P/2M_F2S output by the first-level buffer module 110 is configured to drive the load (ie, the serializer 200 ) of the first-level buffer module 110 and the second-level buffer module 120.

After the second-level buffer module 120 receives the clock signal CK2P/2M_F2S output by the first-level buffer module 110, it performs shaping on the clock signal CK2P/2M_F2S and enhances the driving capability to obtain a load capable of driving the second-level buffer module 120 (i.e. , retimer 300) and the clock signal CK2P/2M_LATCH of the third-level buffer module 130.

After the third-level buffer module 130 receives the clock signal CK2P/2M_LATCH output by the second-level buffer module 120, it performs shaping on the clock signal CK2P/2M_LATCH and enhances the driving capability to obtain a load capable of driving the third-level buffer module 130 (i.e. , the clock signal CK2P/2M of the driver 400 and the duty ratio sensor 810).

In the present disclosure, there is no special limitation on the specific structures of the buffer modules at all levels. As an exemplary embodiment, the buffer module is a buffer, and the buffer includes parallel multi-stage inverters. The inverter can use the smallest size within the process range to ensure that it occupies the smallest area under the condition of providing sufficient driving capability.

In the embodiment shown in FIG. 1, the clock signal output by the third-stage buffer module needs to drive the load (that is, the driver 400 and the duty ratio sensor 810), and the load capacitance of the driver 400 is relatively large, so the third-stage The buffer module needs to provide greater driving capability to ensure the clock quality. That is to say, in the third-level buffer module, the number of unit inverters is large.

Usually, the duty cycle of the clock signal is constant and satisfies a predetermined duty cycle (for example, the duty cycle of the clock signal is 50%). Therefore, the duty cycle of the first signal provided to the first-level buffer module should also be the predetermined duty cycle. In the present disclosure, the first signal is obtained from the initial clock signal. The initial clock signal provided by the signal source is transmitted through the wiring and reaches the input end of the clock link.

In the present disclosure, in order to make the first signal input to the first-level buffer module have the predetermined duty cycle, for example, the clock link further includes a self-biased DC coupling module 600, the self-biased DC The input terminal of the coupling module 600 is configured to receive the initial clock signal CK_IN, and the output terminal of the self-biased DC coupling module 600 is electrically connected to the input terminal of the first-stage buffer module 110 .

The self-bias DC coupling module 600 is configured to provide a DC bias point for the initial clock signal, so that the clock signal input to the first-stage buffer module satisfies a predetermined duty cycle.

As mentioned above, the duty cycle of the clock signal is usually 50% (that is, the predetermined duty cycle is 50%), and the DC bias point can be set at VDD/2, so that the initial clock signal can be Coarse adjustment is made towards 50% duty cycle. "VDD" is the power supply voltage of the self-biased DC-coupled module, as shown in Figure 1.

In order to expand the application range of the clock link, for example, the clock link may further include a frequency divider 700, and the frequency divider 700 is configured to divide the signal received at the input end of the frequency divider 700 according to the frequency division requirement. Perform frequency division processing, and input a clock signal of a predetermined frequency to the input end of the buffer module at the first stage.

In the present disclosure, there is no special limitation on how to provide the "frequency division requirement" to the frequency divider. For example, a frequency division control signal carrying frequency division ratio information may be generated according to a frequency division requirement, and provided to the frequency divider 700, and the frequency divider 700 realizes the frequency division ratio according to the frequency division control signal.

In the present disclosure, there is no special limitation on the frequency division ratio that can be realized by the frequency divider 700 . For example, the frequency divider 700 can respectively implement frequency division ratios of division by 2, division by 4, and division by 8.

That is to say, the frequency division requirement is selected from any one of the following frequency division requirements:

Full-rate, half-rate, quarter-rate, 1/8-rate.

When the frequency division ratio information carried by the control signal is the full rate, the first signal is directly input to the first-level buffer module, and the frequency divider 700 can be bypassed at this time, thereby avoiding the clock path of the frequency divider 700 to the full rate make an impact.

When the working mode selects any one of the half-rate mode, quarter-rate mode, and one-eighth rate mode, the full-rate clock path is bypassed, and the clock signal with the corresponding frequency is obtained after the clock signal passes through the frequency divider. the first signal, and provide the first signal to the first-level buffer module.

As mentioned above, the duty cycle of the clock signal should satisfy a predetermined duty cycle (for example, 50%), and as the clock signal is transmitted along the wiring, the duty cycle may attenuate. In order to make the duty ratio of the clock signal output by the buffer module satisfy a predetermined condition, for example, the clock chain further includes a duty ratio correction module 800 configured to detect the The duty cycle of the output clock signal of at least one buffer module, and the duty cycle correction module 800 is also configured to: when the duty cycle of the detected output clock signal of the buffer module does not meet the predetermined duty cycle range, Adjust the duty ratio of the clock signal output by the module preceding the detected buffer module.

In the present disclosure, there is no special limitation on the "module before the detected buffer module". For example, the "module before the detected buffer module" may be a previous stage buffer module of the detected buffer module, or any one stage buffer module before the detected buffer module.

The duty cycle correction is performed on the clock signal output by the module before the detected buffer module, so that the duty cycle of the clock signal output by the detected buffer module can finally meet the predetermined duty cycle range.

In the present disclosure, there is no special limitation on the specific implementation of the duty ratio correction module. As an exemplary implementation, the duty cycle correction module 800 may include a duty cycle sensor 810, a digital logic unit 820 (for example, a digital logic circuit), a duty cycle correction unit 830 (for example, a duty cycle corrector ).

The duty ratio sensor 810 is configured to perform low-pass filtering on the received clock signal to obtain a DC potential, and perform calculation and comparison on the DC potential to obtain a comparison result.

The digital logic unit 820 is configured to judge whether the duty cycle of the clock signal detected by the duty cycle sensor meets a predetermined duty cycle range according to the comparison result, and the logic digital unit 820 is also configured to determine whether the duty cycle of the clock signal detected by the duty cycle sensor 810 satisfies a predetermined duty cycle range. When the duty ratio of the clock signal does not satisfy the predetermined duty ratio range, an adjustment control signal is generated, and the adjustment control signal is provided to the duty ratio correction unit 830 .

The duty ratio correction unit 830 is configured to generate a duty ratio correction signal according to the received adjustment control signal, and provide the duty ratio correction signal to a module preceding the detected buffer module.

In the present disclosure, there is no special limitation on how the duty ratio sensor 810 detects the duty ratio of the clock signal received by the duty ratio sensor 810 . The clock signal is a differential clock signal. As an exemplary embodiment, the duty ratio sensor 810 performs low-pass filtering on the received clock signal to obtain a DC potential of the clock signal. Then compare the obtained DC potential through the operational amplifier to generate a comparison result SWAP signal.

As mentioned above, the clock signal CK2P/2M is a differential clock signal, including the CK2P signal and the CK2M signal. After receiving the SWAP signal, the digital logic unit 820 judges the difference between the duty cycles of the CK2P signal and the CK2M signal.

When the duty cycles of the CK2P signal and the CK2M signal fall within the predetermined gap range, it indicates that the duty cycle of the clock signal CK2P/2M falls within the predetermined duty cycle range. At this time, the digital logic unit 820 outputs a signal indicating that the duty ratio of the clock signal satisfies a predetermined duty ratio range, and the duty ratio correction unit stops correction when receiving the signal.

When the duty cycles of the CK2P signal and the CK2M signal are no longer within the predetermined gap range, it indicates that the duty cycle of the clock signal CK2P/2M is not within the predetermined duty cycle range. At this time, the digital logic unit 820 outputs an adjustment control signal indicating that the duty ratio of the clock signal does not meet the predetermined duty ratio range, and the duty ratio correction unit 830 adjusts the driving current by adjusting the control signal when receiving the adjustment control signal. , so as to control the current intensity of charge and discharge, and then control the speed of the rising and falling edges of the clock signal to achieve the purpose of controlling the phase of the clock signal and correcting the duty cycle.

In the present disclosure, there is no special limitation on the specific form of the adjustment control signal. For example, the digital logic unit may output code<5:0>, and the duty cycle correction unit 830 adjusts the driving current through the code word.

As an implementation manner of the present disclosure, the duty cycle of the clock signal can be adjusted to 50%.

When the duty ratio of the clock signal is within the predetermined duty ratio range, the bit error rate can be reduced.

As an exemplary implementation, the duty cycle sensor 810 is configured to detect the output clock signal of the last stage buffer module. Furthermore, the duty cycle correction unit 830 is configured to correct the input clock signal of the second-level buffer module.

As a second aspect of the present disclosure, an electronic device is provided. As shown in FIG. 1 , the electronic device includes a clock link and multiple load modules, wherein the clock link is the first aspect of the present disclosure. A clock link is provided, and the clock signal input end of the load module is electrically connected to the clock signal output end of the buffer module corresponding to the load module.

As mentioned above, the clock chain consumes less energy, thereby reducing the overall energy consumption of the electronic device.

Moreover, in an exemplary embodiment, the duty cycle of the clock signal output by the buffer module satisfies a preset duty cycle range, thereby reducing bit errors and improving the precision of the electronic device.

In the present disclosure, there is no special limitation on the specific structure of the electronic device. For example, the electronic device may be any one of a radio frequency transmitter, a radio frequency receiver, and a serial/deserializer.

In an embodiment where the electronic device is a serial/serializer, the clock chain includes three stages of buffer modules, and the multiple load modules include a serializer 200 , a retimer 300 , and a driver 400 .

The clock signal input end of the serializer 200 is electrically connected to the clock signal output end of the first-level buffer module 110, the clock signal input end of the retimer 300 is electrically connected to the clock signal output end of the second-level buffer module 120, and the driver 400 The clock signal input end of the third-level buffer module 130 and the clock signal output end of the third-level buffer module 130 .

The role of the serializer 200 is to perform serial processing on low-speed parallel data in the Serdes system, and multiplex D16_IN<15:0> to D2<1:0> step by step.

The output clock CK2P/2M_LATCH of the second-level buffer module 120 is used to retime the D2<1:0> output by the serializer to avoid errors in data and clock timing caused by different paths of multiple data paths , and avoid bit errors.

In the present disclosure, there is no special limitation on the specific arrangement of the components in the electronic device. For example, as shown in Figure 2, the circuit layout of the electronic device includes a first circuit layout 10, a second circuit layout 20 and a third circuit layout 30, the number of the first circuit layout 10 is at least one, each first circuit layout The layout 10 is respectively configured to carry at least a part of the clock chain, the second circuit layout 20 is configured to carry the serializer, and the third circuit layout 30 is configured to carry the driver.

Both the first circuit layout 10 and the second circuit layout 20 are located on the same side of the third circuit layout 30 .

According to the above-mentioned embodiment, each part of the electronic device is laid out, and the distance between the clock link and each load is similar, and the distance between the clock link and each load is also relatively short, so that it can ensure that the clock signal reaches each load. Less skew, lower bit error rate.

In the present disclosure, there is no special limitation on the specific number of the first circuit layout 10 . In case the electronic device comprises one first circuit layout 10, the entirety of the clock chain is carried on the first circuit layout.

In the case that the electronic device includes a plurality of first circuit layouts 10 , each first circuit layout 10 bears a part of the clock chain.

In the present disclosure, there is no special limitation on the specific number of the first circuit layout 10. For example, the electronic device includes two first circuit layouts 10, and the second circuit layout 20 is located in the two first circuit layouts 10. between, and the first circuit layout 10 and the second circuit layout 20 are arranged along the first direction (the up-down direction in FIG. direction), the first direction intersects the second direction.

In the embodiment shown in Fig. 2, the first direction and the second direction are perpendicular.

As an exemplary implementation, the first circuit layout 10 , the second circuit layout 20 and the third circuit layout 30 may be formed as one body.

In the above embodiments, the clock path can be divided into upper and lower parts, and clock signals are respectively provided to drive the load, thereby reducing clock skew caused by path differences.

example

The initial clock signal of the input clock link is a differential clock signal, specifically the clock signal CK_INP and the clock signal CK_INM. After a long period of routing on the layout, the duty cycle of the differential clock signal will decay to 40%-60 %, when passing through the self-biased DC coupling module 600, the self-biased DC coupling module 600 has a certain intrinsic adjustment effect on the duty cycle of the initial clock signal, and the adjustment effect depends on the rise and fall times of the input clock, The longer the rise and fall times are, the stronger the adjustment capability of the bias DC coupling module 600 is. Setting the DC bias point of the bias DC coupling module 600 at the position of VDD/2 can roughly adjust the initial clock signal to the position of 50% duty cycle to obtain the first signal.

Next, there are two situations. When the working mode is selected as full-rate, the output clock signal (ie, the first signal) of the self-biased DC coupling module 600 is directly input to the first-stage buffer module 110, Bypass the parallel frequency divider 700 so that it does not affect the full-rate clock path; when the operating mode is selected as half-rate, quarter-rate and one-eighth rate (1/8-rate), the full-rate clock path is bypassed, and the output clock signal of the self-biased DC coupling module 600 reaches the first-level buffer module after passing through the frequency divider.

The output load of the first-level buffer module 110 is the serializer 200 and the second-level buffer module 120. After the output clock CK2P/2M_F2S is input to the serializer 200, it will undergo three-level frequency division by two to divide D16_IN<15:0> one by one The stage is multiplexed to D2<1:0>. In this process, the data will have a certain delay on the clock edge, which is called the setting time (setting time), which is recorded as ST ₁ .

In addition to being input to the serializer 200, CK2P/2M_F2S also passes through the second-level buffer module 120. The load of the second-level buffer module 120 is the retimer 300 and the third-level buffer module 130, so the second-level buffer module 120 must Provide sufficient driving capability to ensure the quality of the output clock CK2P/2M_LATCH. The input of the retimer 200 is the final output D2<1:0> of the serializer 200. As mentioned earlier, D2<1:0> will have a certain delay ST ₁ on the clock edge of CK2P/2M_F2S, so the second stage The buffer module 120 must also generate enough delay DT ₂ (DT ₂ > ST ₁ ), to ensure that the output clock of the second-level buffer module 120 lags behind the output data signal of the serializer 200, so as to ensure the accuracy of sampling and eliminate errors. code. At the same time, after the retimer 300 has sampled the data signal, it will also generate a delay ST ₂ for the data when outputting.

The main load of the CK2P/2M is the driver 400 , which is equivalent to 254 inverters with the smallest size, so the driving capability of the third-level buffer module 130 is highly required. In addition to ensuring the driving capability, the third-level buffer module 130 also needs to ensure that the distance difference of the clock path to each point of the load is as small as possible on the layout, so as to ensure that the clock skew to the load is as small as possible. As shown in FIG. 2, since the entire driver 400 is vertically laid out (that is, the third circuit layout 30 is vertically arranged), if the clock link is laid out on the central axis of the driver, then the clock paths to both ends of the driver are compared to those in the middle of the driver. The clock path is much longer, resulting in increased clock skew. This disclosure adopts the method of dividing the clock path into the upper and lower parts of the layout, and changes the lumped clock path into a distributed one. The upper and lower parts respectively provide clock signals CK2P/2M to drive the load, thereby helping to reduce The clock skew brought by the difference, instead of increasing the number of unit buffer modules like a large process, thereby reducing power consumption. In addition to the requirements of driving capability, the same third-level buffer module also needs to provide a certain delay DT ₃ >ST ₂ to ensure that the output clock of the second-level buffer module 120 lags behind the output data signal of the serializer 200 to ensure Sampling accuracy, eliminating bit errors.

The CK2P/2M signal is input to the duty cycle sensor 810. After the duty cycle sensor 810 extracts the DC signal respectively, it is input to the operational amplifier. The analog circuit part (operational amplifier) only completes the SWAP action, and the digital circuit part respectively SWAP=0 and 1. Do two codes scans, one from code=0 to code=63, one from code=63 to code is the second locked value, assuming that the code values of the two records are decimal code1=31 and code2=33 respectively, then Output code=(code1+code2)/2=31, to achieve the purpose of eliminating the DC mismatch of the comparator. Through this method, the design requirements of the analog part on the DC mismatch index of the operational amplifier are also reduced. The final stable output of CK2P/2M is at 50% duty cycle.

Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, the functional modules/units in the system, and the device can be implemented as software, firmware, hardware, and an appropriate combination thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components. Components cooperate to execute. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit .

Example embodiments have been disclosed herein, and while specific terms have been employed, they are used and should be construed in a general descriptive sense only and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics and/or elements described in connection with a particular embodiment may be used alone, or may be described in combination with other embodiments, unless expressly stated otherwise. Combinations of features and/or elements. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

A clock link, comprising a multi-level buffer module and a plurality of clock signal output terminals, each of the clock signal output terminals corresponds to a corresponding buffer module, and the clock signal output terminals are electrically connected to the output terminals of the corresponding buffer modules connect;

The buffer module is configured to shape the clock signal input to the buffer module to obtain an output clock signal that meets the timing requirements corresponding to the buffer module,

In adjacent two-stage buffer modules, the input end of the latter stage buffer module is electrically connected to the output end of the former stage buffer module, and the clock signal output by the latter stage buffer module is relative to the clock input to the first stage buffer module The time delay of the signal is greater than the time delay of the clock signal output by the previous buffer module relative to the clock signal input to the first buffer module.
The clock link according to claim 1, wherein the clock link further comprises a self-biased DC coupling module, the input end of the self-biased DC coupling module is configured to receive an initial clock signal, and the self-biased The output end of the DC coupling module is electrically connected to the input end of the buffer module in the first stage,

The self-biased DC coupling module is configured to provide a DC bias point for the initial clock signal, so that the clock signal input to the first-stage buffer module satisfies a predetermined duty cycle range.
The clock link according to claim 2, wherein the DC bias point is set at a position of VDD/2, wherein VDD is a power supply voltage of the self-biased DC coupling module.
The clock chain according to claim 1, wherein the clock chain further comprises a frequency divider, and the frequency divider is configured to divide the frequency of the signal received by the input terminal of the frequency divider according to the frequency division requirement processing, and input a clock signal of a predetermined frequency to the input end of the buffer module of the first stage.
The clock chain according to claim 4, wherein the frequency division requirement is selected from any one of the following frequency division requirements:

Full rate, half rate, quarter rate, eighth rate.
The clock chain according to any one of claims 1 to 5, wherein the clock chain further comprises a duty cycle correction module configured to detect at least one of the multi-stage buffer modules The duty cycle of the output clock signal of the stage buffer module, and the duty cycle correction module is also configured to, when the detected output clock signal of the buffer module does not meet the predetermined duty cycle range, the detected buffer The duty ratio of the clock signal output by the buffer module before the module is adjusted.
The clock link according to claim 6, wherein the duty ratio correction module comprises a duty ratio sensor, a digital logic unit, and a duty ratio correction unit,

The duty ratio sensor is configured to perform low-pass filtering on the received clock signal to obtain a DC potential, and perform calculation and comparison on the DC potential to obtain a comparison result;

The digital logic unit is configured to judge whether the duty cycle of the clock signal detected by the duty cycle sensor satisfies a predetermined duty cycle range according to the comparison result, and the logic digital unit is also configured to When the duty ratio of the clock signal detected by the sensor does not meet the predetermined duty ratio range, an adjustment control signal is generated, and the adjustment control signal is provided to the duty ratio correction unit;

The duty ratio correction unit is configured to generate a duty ratio correction signal according to the received adjustment control signal, and provide the duty ratio correction signal to a module preceding the detected buffer module.
The clock chain according to claim 7, wherein the duty cycle sensing is configured to detect the output clock signal of the last stage buffer module.
The clock chain according to claim 7, wherein the duty cycle correction unit is configured to correct the input clock signal of the second-level buffer module.
The clock chain according to any one of claims 1 to 5, wherein the clock chain comprises three stages of the buffer modules.
The clock chain according to claim 10, wherein the output end of the buffer module in the first stage is configured to be electrically connected to the clock signal input end of the serializer, and the output end of the buffer module in the second stage is configured to be connected to the clock signal input end of the serializer. The clock signal input end of the retimer is electrically connected, and the output end of the buffer module in the third stage is configured to be electrically connected to the driver.
The clock chain according to any one of claims 1 to 5, wherein the i-th level buffer module is configured to increase the driving capability of the clock signal output by the i-1th level buffer module, so that the i-th level buffer module The output clock signal can drive the load corresponding to the i-th buffer module and the i+1-th buffer module, where i is a positive integer, and 2≤i≤M-1, and M is the buffer module in the clock link total series.
An electronic device comprising a clock link and a plurality of load modules, wherein the clock link is the clock link according to any one of claims 1 to 12, and the clock signal of the load module The input terminal is electrically connected to the clock signal output terminal of the buffer module corresponding to the load module.
The electronic device according to claim 13, wherein the clock chain includes three stages of the buffer module, and a plurality of the load modules include a serializer, a retimer, and a driver, and the clock signal of the serializer The input end is electrically connected to the clock signal output end of the first-level buffer module, the clock signal input end of the retimer is electrically connected to the clock signal output end of the second-level buffer module, and the clock signal input end of the driver is connected to the second-level buffer module. The clock signal output terminal of the three-level buffer module.
The electronic device according to claim 14, wherein the circuit layout of the electronic device includes a first circuit layout, a second circuit layout and a third circuit layout, the number of the first circuit layout is at least one, each of the The first circuit layout is respectively configured to carry at least a part of a clock link, the second circuit layout is configured to carry the serializer, and the third circuit layout is configured to carry the driver,

Both the first circuit layout and the second circuit layout are located on the same side of the third circuit layout.
The electronic device according to claim 15, wherein the electronic device comprises two first circuit layouts, the two first circuit layouts carry a part of the clock link respectively, and the second circuit layout Located between the two first circuit layouts, and the first circuit layout and the second circuit layout are arranged along a first direction, and the second circuit layout and the third circuit layout are arranged along a second direction , the first direction intersects the second direction.