CN116185925A - Clock link and electronic device - Google Patents

Clock link and electronic device Download PDF

Info

Publication number
CN116185925A
CN116185925A CN202111435953.7A CN202111435953A CN116185925A CN 116185925 A CN116185925 A CN 116185925A CN 202111435953 A CN202111435953 A CN 202111435953A CN 116185925 A CN116185925 A CN 116185925A
Authority
CN
China
Prior art keywords
clock signal
buffer module
clock
module
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111435953.7A
Other languages
Chinese (zh)
Inventor
杨彬彬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanechips Technology Co Ltd
Original Assignee
Sanechips Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanechips Technology Co Ltd filed Critical Sanechips Technology Co Ltd
Priority to CN202111435953.7A priority Critical patent/CN116185925A/en
Priority to PCT/CN2022/081535 priority patent/WO2023092905A1/en
Publication of CN116185925A publication Critical patent/CN116185925A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The clock link comprises a plurality of stages of buffer modules and a plurality of clock signal output ends, wherein each clock signal output end corresponds to a corresponding buffer module, and the clock signal output end is electrically connected with the output end of the corresponding buffer module; the buffer module is used for shaping the clock signal input to the buffer module so as to obtain an output clock signal meeting the time sequence requirement corresponding to the buffer module, in the two adjacent buffer modules, the input end of the next buffer module is electrically connected with the output end of the previous buffer module, and the time delay of the clock signal output by the next buffer module relative to the clock signal input to the first buffer module is larger than the time delay of the clock signal output by the previous buffer module relative to the clock signal input to the first buffer module. The disclosure also provides an electronic device.

Description

Clock link and electronic device
Technical Field
The present disclosure relates to the field of electronic devices, and in particular, to a clock link and an electronic device including the clock link.
Background
As integrated circuit fabrication processes enter the nanometer scale, so too does the speed of operation of serial/deserializers (SerDes).
For the high-speed serializer/deserializer, the clock driving generally adopts a clock link with a tree structure to perform multipath separate buffering, and finally the ultra-large load is driven in a lumped mode. However, at higher speeds, the tree structure occupies a larger area and consumes a great deal of power.
Disclosure of Invention
Embodiments of the present disclosure provide a clock link and an electronic device including the clock link.
As a first aspect of the present disclosure, there is provided a clock link, wherein the clock link includes a multi-stage buffer module and a plurality of clock signal output terminals, each of the clock signal output terminals corresponds to a corresponding buffer module, and the clock signal output terminals are electrically connected with output terminals of the corresponding buffer modules;
the buffer module is used for shaping the clock signal input to the buffer module to obtain an output clock signal meeting the time sequence requirement corresponding to the buffer module,
in the adjacent two-stage buffer modules, the input end of the next-stage buffer module is electrically connected with the output end of the previous-stage buffer module, and the time delay of the clock signal output by the next-stage buffer module relative to the clock signal input to the first-stage buffer module is larger than the time delay of the clock signal output by the previous-stage buffer module relative to the clock signal input to the first-stage buffer module.
Optionally, the clock link further comprises a self-bias direct current coupling module, an input end of the self-bias direct current coupling module is used for receiving an initial clock signal, an output end of the self-bias direct current coupling module is electrically connected with an input end of the buffer module of the first stage,
the self-bias DC coupling module is used for providing a DC bias point for the initial clock signal so that the clock signal input into the buffer module of the first stage meets the preset duty ratio range.
Optionally, the dc bias point is set at a position of VDD/2.
Optionally, the clock link further includes a frequency divider, where the frequency divider is configured to divide a signal received by an input terminal of the frequency divider according to a frequency division requirement, and input a clock signal with a predetermined frequency to an input terminal of the buffer module of the first stage.
Optionally you, the frequency division requirement is selected from any one of the following frequency division requirements:
full rate, half rate, quarter rate, eighth rate.
Optionally, the clock link further includes a duty cycle correction module, where the duty cycle correction module is configured to determine a duty cycle of an output clock signal of at least one stage of the multi-stage buffer modules, and the duty cycle correction module is further configured to perform duty cycle adjustment on a clock signal output by a module preceding the detected buffer module if the detected output clock signal of the buffer module does not meet a predetermined duty cycle range.
Optionally, the duty cycle correction module comprises a duty cycle sensor, a digital logic unit, a duty cycle correction unit,
the duty ratio sensor is used for performing low-pass filtering processing on the received clock signal to obtain a direct current potential, and performing operation comparison on the direct current potential to obtain a comparison result;
the digital logic unit is used for judging whether the duty ratio of the clock signal detected by the duty ratio sensor meets a preset duty ratio range or not according to the comparison result, and the logic digital unit is also used for generating an adjustment control signal when the duty ratio of the clock signal detected by the duty ratio sensor does not meet the preset duty ratio range and providing the adjustment control signal to the duty ratio correction unit;
the duty cycle correction unit is used for generating a duty cycle correction signal according to the received adjustment control signal and providing the duty cycle correction signal to a module before the detected buffer module.
Optionally, the duty ratio sensor is configured to detect an output clock signal of the last stage buffer module.
Optionally, the duty ratio correction unit is configured to correct an input clock signal of the second stage buffer module.
Optionally, the clock link includes three levels of the buffer modules.
Optionally, the output end of the first stage of the buffer module is used for being electrically connected with the clock signal input end of the serializer, the output end of the second stage of the buffer module is used for being electrically connected with the clock signal input end of the re-timer, and the output end of the third stage of the buffer module is used for being electrically connected with the driver.
Optionally, the ith buffer module is configured to increase driving capability of a clock signal output by the ith-1 st buffer module, so that the clock signal output by the ith buffer module can drive a load corresponding to the ith buffer module and the (i+1) th buffer module, where i is a positive integer, i is 2-1, and M is the total number of stages of the buffer modules in the clock link.
As a second aspect of the present disclosure, there is provided an electronic device, including a clock link and a plurality of load modules, where the clock link is the clock link provided in the first aspect of the present disclosure, and a clock signal input terminal of the load module is electrically connected to a clock signal output terminal of a buffer module corresponding to the load module.
Optionally, the clock link includes three stages of the buffer modules, and the plurality of load modules include a serializer, a retimer, and a driver, where a clock signal input end of the serializer is electrically connected with a clock signal output end of the first stage buffer module, a clock signal input end of the retimer is electrically connected with a clock signal output end of the second stage buffer module, and a clock signal input end of the driver is electrically connected with a clock signal output end of the third stage buffer module.
Optionally, the electronic device includes a first circuit layout, a second circuit layout and a third circuit layout, where the number of the first circuit layouts is at least one, each of the first circuit layouts is used for carrying at least a part of a clock link, the second circuit layout is used for carrying the serializer, the third circuit layout is used for carrying the driver,
the first circuit layout and the second circuit layout are both positioned on the same side of the third circuit layout.
Optionally, the electronic device includes two first circuit layouts, the two first circuit layouts respectively bear a part of the clock link, the second circuit layout is located between the two first circuit layouts, the first circuit layout and the second circuit layout are arranged along a first direction, the second circuit layout and the third circuit layout are arranged along a second direction, and the first direction intersects the second direction.
In the clock link, the input signal of the first stage buffer module is an unshaped signal (for convenience of description, hereinafter referred to as a first signal), after the shaping process of the first stage buffer module, the delay of the clock signal output by the output end of the first stage buffer module relative to the first signal is Δt1, the input signal of the second stage buffer module is the output signal of the first stage buffer module, after the shaping process of the second stage buffer module, the delay of the output signal of the second stage buffer module relative to the first signal is Δt1+Δt2, and so on, and the delay of the output signal of the nth stage buffer module relative to the first signal is Δt1+Δt2+ … +Δtn. It can be seen that the signal is further buffered by the next stage buffer module based on the delay already generated by the previous stage buffer module. Compared with the method that the first signal is simply buffered to obtain the delay of delta t1+ delta t2+ … + delta tn, the method of further buffering the signal based on the delay generated by the buffer module at the previous stage is more energy-saving.
Drawings
FIG. 1 is a schematic diagram of one embodiment of a clock link provided by the present disclosure;
fig. 2 is a schematic diagram of a layout of an electronic device provided by the present disclosure.
Detailed Description
For a better understanding of the technical solutions of the present disclosure, the clock link and the electronic device including the clock link provided in the present disclosure are described in detail below with reference to the accompanying drawings.
Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Embodiments of the disclosure and features of embodiments may be combined with each other without conflict.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As a first aspect of the present disclosure, there is provided a clock link, wherein, as shown in fig. 1, the clock link includes a plurality of buffer modules and a plurality of clock signal output terminals, each of the clock signal output terminals corresponds to a corresponding buffer module, and the clock signal output terminals are electrically connected with output terminals of the corresponding buffer modules.
The buffer module is used for shaping the clock signal input to the buffer module so as to obtain an output clock signal meeting the time sequence requirement corresponding to the buffer module.
In the adjacent two-stage buffer modules, the input end of the next-stage buffer module is electrically connected with the output end of the previous-stage buffer module, and the time delay of the clock signal output by the next-stage buffer module relative to the clock signal input to the first-stage buffer module is larger than the time delay of the clock signal output by the previous-stage buffer module relative to the clock signal input to the first-stage buffer module.
In the clock link, the input signal of the first stage buffer module is an unshaped signal (for convenience of description, hereinafter referred to as a first signal), after the shaping process of the first stage buffer module, the delay of the clock signal output by the output end of the first stage buffer module relative to the first signal is Δt1, the input signal of the second stage buffer module is the output signal of the first stage buffer module, after the shaping process of the second stage buffer module, the delay of the output signal of the second stage buffer module relative to the first signal is Δt1+Δt2, and so on, and the delay of the output signal of the mth stage buffer module relative to the first signal is Δt1+Δt2+ … +Δtm. It can be seen that the signal is further buffered by the next stage buffer module based on the delay already generated by the previous stage buffer module. Compared with the method that the first signal is simply buffered to obtain the delay of delta t1+ delta t2+ … + delta tm, the method that the signal is further buffered on the basis of the delay generated by the buffer module at the previous stage saves more energy.
In the embodiment shown in fig. 1, the clock link includes three stages of buffer modules, namely, a first stage buffer module 110, a second stage buffer module 120, and a third stage buffer module 130, where an output of the first stage buffer module 110 is electrically connected to an input of the second stage buffer module 120, and an output of the second stage buffer module 120 is electrically connected to an input of the third stage buffer module 130.
In this application, the specific number of clock signal output terminals in the pair Zhong Lianlu is not particularly limited. The number of clock signal outputs of a clock link is the same as the number of loads of the clock link. As an alternative implementation, each stage of buffer module corresponds to a load, and then the number of clock signal output ends of the clock link is the same as the number of buffer modules.
For the buffer module connected with the load, besides shaping the clock signal input to the buffer module, the buffer module should also be used for increasing the driving capability of the clock signal input to the buffer module, so that the clock signal output by the buffer module can drive the next-stage buffer module and the load of the current-stage buffer module. In other words, the ith buffer module is configured to increase driving capability of the clock signal output by the ith-1 st buffer module, so that the clock signal output by the ith buffer module can drive the load corresponding to the ith buffer module and the (i+1) th buffer module, where i is a positive integer, i is 2.ltoreq.i.ltoreq.M-1, and M is the total number of stages of the buffer modules in the clock link.
In the embodiment shown in fig. 1, the clock signal CK2P/m_f2s output from the first stage buffer module 110 is used to drive the load (i.e., the serializer 200) of the first stage buffer module 110 and the second stage buffer module 120.
After the second-stage buffer module 120 receives the clock signal CK2P/m_f2s output by the first-stage buffer module 110, the second-stage buffer module 120 shapes and enhances the driving capability of the clock signal CK2P/m_f2s to obtain the clock signal CK2P/m_latch capable of driving the load (i.e. the retimer 300) of the second-stage buffer module 120 and the third-stage buffer module 130.
After the third stage buffer module 130 receives the clock signal CK2P/m_latch output by the second stage buffer module 120, the clock signal CK2P/m_latch is shaped and the driving capability is enhanced, so as to obtain the clock signal CK2P/M capable of driving the load (i.e. the driver 400 and the duty ratio sensor 810) of the third stage buffer module 130.
In the present disclosure, the specific structure of each stage of buffer module is not particularly limited. As an alternative embodiment, the buffer comprises a plurality of inverters connected in parallel. The inverter may take a minimum size within the process to ensure that it occupies a minimum area under conditions that provide sufficient driving capability.
In the embodiment shown in fig. 1, the clock signal output by the third stage buffer module needs to drive the load (i.e., the driver 400 and the duty cycle sensor 810), and the load capacitance of the driver 400 is large, so the third stage buffer module needs to provide a large driving capability to ensure clock quality. That is, in the third stage buffer module, the number of unit inverters is large.
Typically, the duty cycle of the clock signal is fixed and a predetermined duty cycle is satisfied (e.g., the duty cycle of the clock signal is 50%). Therefore, the duty cycle of the first signal provided to the first stage buffer module should also be the predetermined duty cycle. In the present disclosure, the first signal is obtained from an initial clock signal. An initial clock signal provided by a signal source is transmitted through the wiring and reaches the input end of the clock link.
In the present disclosure, in order to make the first signal input to the first stage buffer module have the predetermined duty ratio, it is preferable that the clock link further includes a self-biased dc coupling module 600, an input terminal of the self-biased dc coupling module 600 is used to receive the initial clock signal, and an output terminal of the self-biased dc coupling module 600 is electrically connected to an input terminal of the first stage buffer module 110.
The self-bias dc-coupling module 600 is configured to provide a dc bias point to the initial clock signal, so that the clock signal input to the buffer module of the first stage satisfies a predetermined duty cycle.
As described above, the duty cycle of the clock signal is typically 50% (i.e., the predetermined duty cycle is 50%), and the dc bias point may be set at VDD/2 so that the initial clock signal may be coarsely adjusted toward the 50% duty cycle.
In order to expand the application range of the clock link, optionally, the clock link may further include a frequency divider 700, where the frequency divider 700 is configured to divide a signal received by an input terminal of the frequency divider 700 according to a frequency division requirement, and input a clock signal with a predetermined frequency to an input terminal of the buffer module of the first stage.
In the present disclosure, there is no particular limitation on how to provide the "frequency division requirement" to the frequency divider. For example, a frequency division control signal carrying frequency division ratio information may be generated according to the frequency division requirement and provided to the frequency divider 700, and the frequency divider 700 implements the frequency division ratio according to the frequency division control signal.
In the present disclosure, the division ratio that can be achieved by the divider 700 is not particularly limited. For example, divider 700 may implement divide ratios divided by 2, divided by 4, and divided by 8, respectively.
That is, the frequency division requirement is selected from any one of the following frequency division requirements:
full rate (full-rate), half rate (half-rate), quarter rate (quarter-rate), eighth rate (1/8-rate).
When the frequency division ratio information carried by the control signal is full-rate, the first signal is directly input to the first-stage buffer module, and the frequency divider 700 can be bypassed at the moment, so that the influence of the frequency divider 700 on the full-rate clock path is avoided.
When the working mode selects any one of the half rate mode, the quarter rate mode and the eighth rate mode, the clock path with full rate is bypassed, the clock signal passes through the frequency divider to obtain a first signal with corresponding frequency, and the first signal is provided to the first stage buffer module.
As described above, the duty cycle of the clock signal should satisfy a predetermined duty cycle (e.g., 50%), and as the clock signal is transmitted along the trace, a duty cycle decay may occur. In order to make the duty ratio of the clock signal output by the buffer modules meet the predetermined condition, optionally, the clock link further includes a duty ratio correction module 800, where the duty ratio correction module 800 is configured to determine the duty ratio of the output clock signal of at least one stage of buffer modules in the multi-stage buffer modules, and the duty ratio correction module 800 is further configured to perform duty ratio adjustment on the clock signal output by the module preceding the detected buffer module if the detected duty ratio of the output clock signal of the buffer module does not meet the predetermined duty ratio range.
In the present disclosure, the "module before the detected buffer module" is not particularly limited. For example, the "module before the detected buffer module" may be the buffer module of the previous stage of the detected buffer module, or may be any buffer module of the previous stage of the detected buffer module.
The duty ratio of the clock signal output by the detected buffer module can finally meet the preset duty ratio range by carrying out duty ratio correction on the clock signal output by the module before the detected buffer module.
In the present disclosure, the specific implementation of the duty cycle correction module is not particularly limited. As an alternative embodiment, the duty cycle correction module 800 may include a duty cycle sensor 810, a digital logic unit 820, and a duty cycle correction unit 830.
The duty ratio sensor 810 is configured to perform low-pass filtering on the received clock signal to obtain a dc potential, and perform operation comparison on the dc potential to obtain a comparison result.
The digital logic unit 820 is configured to determine whether the duty ratio of the clock signal detected by the duty ratio sensor satisfies a predetermined duty ratio range according to the comparison result, and the logic digital unit 820 is further configured to generate an adjustment control signal when the duty ratio of the clock signal detected by the duty ratio sensor 810 does not satisfy the predetermined duty ratio range, and provide the adjustment control signal to the duty ratio correction unit 830.
The duty cycle correction unit 830 is configured to generate a duty cycle correction signal according to the received adjustment control signal, and provide the duty cycle correction signal to a module before the detected buffer module.
In the present disclosure, there is no particular limitation on how the duty ratio sensor 810 detects the duty ratio of the clock signal received from the duty ratio sensor 810. The clock signal is a differential clock signal, and as an alternative embodiment, the duty cycle sensor 810 performs low pass filtering on the received clock signal to obtain the dc potential of the clock signal. And then comparing the obtained direct current potential through an operational amplifier to generate a comparison result SWAP signal.
As described above, the clock signal CK2P/M is a differential clock signal, including CK2P signals and CK2M signals. Digital logic unit 820 determines the magnitude of the duty cycle gap between the CK2P signal and the CK2M signal after receiving the SWAP signal.
When the duty ratios of the CK2P signal and the CK2M signal occupy a predetermined gap range, it is indicated that the duty ratio of the clock signal CK2P/M falls within the predetermined duty ratio range. At this time, the digital logic unit 820 outputs a signal indicating that the duty ratio of the clock signal satisfies the predetermined duty ratio range, and the duty ratio correction unit stops correction when receiving the signal.
When the duty ratios of the CK2P signal and the CK2M signal occupy no longer within the predetermined gap range, then it is indicated that the duty ratio of the clock signal CK2P/M is no longer within the predetermined duty ratio range. At this time, the digital logic unit 820 outputs an adjustment control signal indicating that the duty ratio of the clock signal does not satisfy the predetermined duty ratio range, and the duty ratio correction unit 830 adjusts the driving current by adjusting the control signal when receiving the adjustment control signal, thereby controlling the current intensity of the charge and discharge, and further controlling the speeds of the rising edge and the falling edge of the clock signal, thereby achieving the purposes of controlling the phase of the clock signal and correcting the duty ratio.
In the present disclosure, the specific form of the adjustment control signal is not particularly limited. For example, the digital logic unit may output a code <5:0>, and the duty cycle correction unit 830 adjusts the driving current by the codeword.
As one embodiment of the present disclosure, the duty cycle of the clock signal may be adjusted to 50%.
When the duty cycle of the clock signal is within a predetermined duty cycle range, the bit error rate can be reduced.
As an alternative embodiment, the duty cycle sensor 810 is used to detect the output clock signal of the last stage buffer module. And, the duty ratio correction unit 830 is used for correcting the input clock signal of the second stage buffer module.
As a second aspect of the present disclosure, there is provided an electronic device, as shown in fig. 1, where the electronic device includes a clock link and a plurality of load modules, where the clock link is the clock link provided in the first aspect of the present disclosure, and a clock signal input terminal of the load module is electrically connected to a clock signal output terminal of a buffer module corresponding to the load module.
As described above, the power consumption of the clock link is lower, so that the overall power consumption of the electronic device can be reduced.
In addition, in an alternative implementation mode, the duty ratio of the clock signal output by the buffer module meets the preset duty ratio range, so that error codes can be reduced, and the precision of the electronic equipment is improved.
In the present disclosure, the specific structure of the electronic apparatus is not particularly limited. For example, the electronic device may be any of a radio frequency transmitter, a radio frequency receiver, a serializer/deserializer.
In the embodiment where the electronic device is a serializer/deserializer, the clock link includes three stages of the buffer modules, and the plurality of load modules includes a serializer 200, a retimer 300, and a driver 400.
The clock signal input of the serializer 200 is electrically connected to the clock signal output of the first stage buffer module 110, the clock signal input of the retimer 300 is electrically connected to the clock signal output of the second stage buffer module 120, and the clock signal input of the driver 400 is electrically connected to the clock signal output of the third stage buffer module 130.
The function of serializer 200 is to serially process low speed parallel data IN the Serdes system, multiplexing D16_IN <15:0> step-by-step to D2<1:0>.
The output clock CK2P/m_latch of the second stage buffer 120 is used for retiming the D2<1:0> output by the serializer, so as to avoid errors in data and clock timing caused by different paths of a plurality of data paths and avoid generating errors.
In the present disclosure, the specific arrangement of each component in the electronic device is not particularly limited. For example, as shown in fig. 2, the circuit layout of the electronic device includes a first circuit layout 10, a second circuit layout 20 and a third circuit layout 30, the number of the first circuit layouts 10 is at least one, each first circuit layout 10 is used for carrying at least a part of a clock link, the second circuit layout 20 is used for carrying the serializer, and the third circuit layout 30 is used for carrying the driver.
The first circuit layout 10 and the second circuit layout 20 are both located on the same side of the third circuit layout 30.
According to the embodiment, the parts of the electronic equipment are distributed, the distance between the clock link and each load is approximate, and the distance between the clock link and each load is short, so that the skew of the clock signal reaching each load is small, and the error rate is reduced.
In the present disclosure, the specific number of the first circuit layout 10 is not particularly limited. In the case of an electronic device comprising one first circuit layout 10, all of the clock links are carried on the first circuit layout.
In the case of an electronic device comprising a plurality of first circuit layouts 10, each first circuit layout 10 carries a part of the clock link thereon.
In the present disclosure, the specific number of the first circuit layouts 10 is not particularly limited, and optionally, the electronic device includes two first circuit layouts 10, the second circuit layout 20 is located between the two first circuit layouts 10, the first circuit layout 10 and the second circuit layout 20 are arranged along a first direction (up-down direction in fig. 2), the second circuit layout 20 and the third circuit layout 30 are arranged along a second direction (left-right direction in fig. 2), and the first direction intersects with the second direction.
In the embodiment shown in fig. 2, the first direction and the second direction are perpendicular.
As an alternative embodiment, the first circuit layout 10, the second circuit layout 20 and the third circuit layout 30 may be formed as one body.
In the above embodiment, the clock path may be divided into upper and lower portions, and clock signals may be respectively supplied to drive the load, so that clock skew due to path differences may be reduced.
Examples
The initial clock signal of the input clock link is a differential clock signal, specifically, the clock signal ck_inp and the clock signal ck_inm respectively, after a relatively long section of wiring on the layout, the duty ratio of the differential clock signal is attenuated to 40% -60%, when the self-bias dc-link module 600 passes, the self-bias dc-link module 600 has a certain intrinsic adjustment effect on the duty ratio of the initial clock signal, the adjustment effect depends on the rising and falling time of the input clock, and the greater the rising and falling time, the stronger the adjustment capability of the self-bias dc-link module 600. Setting the dc bias point of the bias dc-link module 600 at the VDD/2 position may coarsely adjust the initial clock signal to a 50% duty cycle position to obtain the first signal.
Next, two cases are divided, when the operation mode is selected to be full-rate, the output clock signal (i.e., the first signal) of the self-bias dc coupling module 600 is directly input to the first stage buffer module 110, and the parallel frequency divider 700 is bypassed so as not to affect the full-rate clock path; when the operation mode is selected to be half rate (half-rate), quarter rate (quarter-rate) and eighth rate (1/8-rate), the full rate clock path is bypassed and the output clock signal of the self-biased dc coupling module 600 reaches the first stage buffer after passing through the frequency divider.
The output load of the first stage buffer module 110 is the serializer 200 and the output load of the second stage buffer module 120, and the output clock CK2P/M_F2S is input into the serializer 200 and then subjected to three-stage two-division to divide the frequency into D16_IN<15:0>Multiplexing to D2 step by step<1:0>In this process, the data will have a delay on the clock edge, called the Setup Time (ST) 1 。
The CK2P/m_f2s is input to the serializer 200 and also passes through the second stage buffer module 120, and the load of the second stage buffer module 120 is the retimer 300 and the third stage buffer module 130, so the second stage buffer module 120 must provide sufficient driving capability to ensure the quality of the output clock CK2P/m_latch. The input to the retimer 200 is the final output D2 of the serializer 200<1:0>The foregoing mention of D2<1:0>Will have a certain delay ST at the clock edge of CK2P/M_F2S 1 The second stage buffer module 120 must also generate a sufficient delay DT 2 (DT 2 ＞ST 1 ) To ensure the output of the second stage buffer module 120The output clock lags the output data signal of the serializer 200 to ensure the accuracy of sampling and eliminate bit errors. At the same time, the re-timer 300 also generates a delay ST for the data at the output time after sampling the data signal 2 。
The main load of CK2P/M is the driver 400, and the driver 400 corresponds to 254 minimum-sized inverters, so that there is a high requirement for the driving capability of the third-stage buffer module 130. The third stage buffer module 130 needs to ensure that the clock path distance difference to each point of the load is as small as possible in addition to ensuring the driving capability, so as to ensure that the clock skew to the load is as small as possible. As shown in fig. 2, since the entire driver 400 is in a portrait layout (i.e., the third circuit layout 30 is arranged vertically), if clock links are laid out on the driver axis, the clock paths to both ends of the driver are much longer than the clock paths to the middle of the driver, resulting in an increase in clock skew. The method adopts a mode of dividing the clock path into an upper part and a lower part and arranging the layout, changes the lumped clock path into a distributed type, and respectively provides clock signals CK2P/M for the upper part and the lower part to drive the load, thereby being beneficial to reducing clock deflection caused by path difference, not increasing the number of unit buffers like a large process, and further reducing the power consumption. In addition to the driving capability requirement, the same third stage buffer also needs to provide a certain delay DT3 > ST2 to ensure that the output clock of the second stage buffer module 120 lags the output data signal of the serializer 200, so as to ensure the accuracy of sampling and eliminate the error code.
The CK2P/M signal is input to the duty ratio sensor 810, the duty ratio sensor 810 extracts the dc signal respectively, and then inputs the dc signal to the operational amplifier, the analog circuit part (operational amplifier) only completes the SWAP operation, the digital circuit part performs swap=0 and performs two scans at 1 time, one from code=0 to code=63, and one from code=63 to code is a second locking value, and assuming that the code values recorded twice are decimal code 1=31 and code 2=33, respectively, the code= (code 1+code 2)/2=31 is output, thereby achieving the purpose of eliminating the dc mismatch of the comparator. By the method, the design requirement of the analog part on the direct current mismatch index of the operational amplifier is also reduced. The final stable output CK2P/M is at 50% duty cycle.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, it will be apparent to one skilled in the art that features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with other embodiments unless explicitly stated otherwise. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.

Claims (16)

1. The clock link is characterized by comprising a plurality of stages of buffer modules and a plurality of clock signal output ends, wherein each clock signal output end corresponds to a corresponding buffer module, and the clock signal output end is electrically connected with the output end of the corresponding buffer module;
the buffer module is used for shaping the clock signal input to the buffer module to obtain an output clock signal meeting the time sequence requirement corresponding to the buffer module,
in the adjacent two-stage buffer modules, the input end of the next-stage buffer module is electrically connected with the output end of the previous-stage buffer module, and the time delay of the clock signal output by the next-stage buffer module relative to the clock signal input to the first-stage buffer module is larger than the time delay of the clock signal output by the previous-stage buffer module relative to the clock signal input to the first-stage buffer module.
2. The clock link of claim 1, further comprising a self-biasing DC coupling module having an input for receiving an initial clock signal, an output of the self-biasing DC coupling module being electrically coupled to the input of the buffer module of the first stage,
the self-bias DC coupling module is used for providing a DC bias point for the initial clock signal so that the clock signal input into the buffer module of the first stage meets the preset duty ratio range.
3. The clock link of claim 2, wherein the dc bias point is set at a position of VDD/2.
4. The clock link of claim 1, further comprising a frequency divider for dividing a signal received at an input of the frequency divider according to a frequency division requirement, and inputting a clock signal of a predetermined frequency to an input of the buffer module of the first stage.
5. The clock link of claim 4, wherein the divide requirement is selected from any one of the following divide requirements:
full rate, half rate, quarter rate, eighth rate.
6. The clock link according to any one of claims 1 to 5, further comprising a duty cycle correction module for determining a duty cycle of an output clock signal of at least one of the multi-stage buffer modules, and for duty cycle adjustment of a clock signal output by a module preceding the detected buffer module if the detected output clock signal of the buffer module does not satisfy a predetermined duty cycle range.
7. The clock link of claim 6, wherein the duty cycle correction module comprises a duty cycle sensor, a digital logic unit, a duty cycle correction unit,
the duty ratio sensor is used for performing low-pass filtering processing on the received clock signal to obtain a direct current potential, and performing operation comparison on the direct current potential to obtain a comparison result;
the digital logic unit is used for judging whether the duty ratio of the clock signal detected by the duty ratio sensor meets a preset duty ratio range or not according to the comparison result, and the logic digital unit is also used for generating an adjustment control signal when the duty ratio of the clock signal detected by the duty ratio sensor does not meet the preset duty ratio range and providing the adjustment control signal to the duty ratio correction unit;
the duty cycle correction unit is used for generating a duty cycle correction signal according to the received adjustment control signal and providing the duty cycle correction signal to a module before the detected buffer module.
8. The clock link of claim 7, wherein the duty cycle sensor is configured to detect an output clock signal of a last stage buffer module.
9. The clock link of claim 7, wherein the duty cycle correction unit is configured to correct an input clock signal of the second stage buffer module.
10. The clock link of any one of claims 1 to 5, wherein the clock link comprises three levels of the buffer modules.
11. The clock link of claim 10, wherein the output of the first stage of the buffer module is configured to be electrically connected to the clock signal input of the serializer, the output of the second stage of the buffer module is configured to be electrically connected to the clock signal input of the retimer, and the output of the third stage of the buffer module is configured to be electrically connected to the driver.
12. The clock link according to any one of claims 1 to 5, wherein the i-th stage buffer module is configured to increase driving capability of a clock signal output by the i-1-th stage buffer module, so that the clock signal output by the i-th stage buffer module can drive a load corresponding to the i-th stage buffer module and the i+1-th stage buffer module, where i is a positive integer, and 2.ltoreq.i.ltoreq.m-1, and M is a total number of stages of the buffer modules in the clock link.
13. An electronic device comprising a clock link and a plurality of load modules, wherein the clock link is as claimed in any one of claims 1 to 12, and the clock signal input of the load module is electrically connected to the clock signal output of a buffer module corresponding to the load module.
14. The electronic device of claim 13, wherein the clock link comprises three stages of the buffer modules, the plurality of load modules comprises a serializer, a retimer, and a driver, the clock signal input of the serializer is electrically connected to the clock signal output of the first stage buffer module, the clock signal input of the retimer is electrically connected to the clock signal output of the second stage buffer module, and the clock signal input of the driver is electrically connected to the clock signal output of the third stage buffer module.
15. The electronic device of claim 14, wherein the circuit layout of the electronic device comprises a first circuit layout, a second circuit layout and a third circuit layout, the number of the first circuit layout is at least one, each of the first circuit layout is used for carrying at least a part of a clock link, the second circuit layout is used for carrying the serializer, the third circuit layout is used for carrying the driver,
the first circuit layout and the second circuit layout are both positioned on the same side of the third circuit layout.
16. The electronic device of claim 15, wherein the electronic device comprises two first circuit layouts each carrying a portion of the clock link, the second circuit layout is located between the two first circuit layouts, and the first and second circuit layouts are arranged in a first direction, and the second and third circuit layouts are arranged in a second direction, the first direction intersecting the second direction.
CN202111435953.7A 2021-11-29 2021-11-29 Clock link and electronic device Pending CN116185925A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202111435953.7A CN116185925A (en) 2021-11-29 2021-11-29 Clock link and electronic device
PCT/CN2022/081535 WO2023092905A1 (en) 2021-11-29 2022-03-17 Clock link and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111435953.7A CN116185925A (en) 2021-11-29 2021-11-29 Clock link and electronic device

Publications (1)

Publication Number Publication Date
CN116185925A true CN116185925A (en) 2023-05-30

Family

ID=86442879

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111435953.7A Pending CN116185925A (en) 2021-11-29 2021-11-29 Clock link and electronic device

Country Status (2)

Country Link
CN (1) CN116185925A (en)
WO (1) WO2023092905A1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9225324B2 (en) * 2014-04-21 2015-12-29 Qualcomm Incorporated Circuit for generating accurate clock phase signals for high-speed SERDES
CN105591649B (en) * 2014-10-22 2018-03-30 京微雅格（北京）科技有限公司 A kind of clock data signal restoring circuit based on over-sampling structure
US11056171B1 (en) * 2019-12-30 2021-07-06 Micron Technology, Inc. Apparatuses and methods for wide clock frequency range command paths
US11153129B1 (en) * 2020-06-01 2021-10-19 International Business Machines Corporation Feedforward equalizer with programmable roaming taps

Also Published As

Publication number Publication date
WO2023092905A1 (en) 2023-06-01

Similar Documents

Publication Publication Date Title
US11005466B2 (en) Measurement and correction of multiphase clock duty cycle and skew
US10181844B1 (en) Clock duty cycle calibration and frequency multiplier circuit
US8286022B2 (en) Intra-pair differential skew compensation method and apparatus for high-speed cable data transmission systems
US7330058B2 (en) Clock and data recovery circuit and method thereof
US6911853B2 (en) Locked loop with dual rail regulation
US7545190B2 (en) Parallel multiplexing duty cycle adjustment circuit with programmable range control
EP2296278A2 (en) System with dual rail regulated locked loop
CN110957998B (en) Circuit for accurately correcting duty ratio of clock signal
US7266169B2 (en) Phase interpolater and applications thereof
JP2007060655A (en) Eye size measurement circuit, receiver of data communication system, and eye size measurement method
US7482841B1 (en) Differential bang-bang phase detector (BBPD) with latency reduction
CN112335180A (en) High speed digital phase interpolator with duty cycle correction circuit
CN101494456B (en) Delay-locked loop and a stabilizing method thereof
US9154291B2 (en) Differential signal skew adjustment method and transmission circuit
US11349459B2 (en) Multiple adjacent slicewise layout of voltage-controlled oscillator
US7330502B2 (en) Input/output circuit and semiconductor integrated circuit
EP1421689B1 (en) Differential ring oscillator stage
US7977990B2 (en) Duty correction circuit, duty correction system, and duty correction method
CN116185925A (en) Clock link and electronic device
US8698536B2 (en) Variable delay circuit
US20130265179A1 (en) Digital phase locked loop circuitry and methods
CN115576884B (en) Duty ratio adjustable single-end clock-to-differential circuit
CN115225083A (en) Clock data correction circuit
CN117639735B (en) Duty cycle detection circuit and duty cycle adjustment system
CN117879542A (en) Clock duty cycle calibration circuit and method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication