WO2023087808A1

WO2023087808A1 - Semiconductor device and manufacturing method therefor

Info

Publication number: WO2023087808A1
Application number: PCT/CN2022/112356
Authority: WO
Inventors: 周耀辉; 张松; 刘群; 王德进
Original assignee: 无锡华润上华科技有限公司
Priority date: 2021-11-19
Filing date: 2022-08-15
Publication date: 2023-05-25
Also published as: CN116153782A

Abstract

The present invention provides a semiconductor device and a manufacturing method therefor, applicable to the field of semiconductors. The present invention provides a method for forming a double SOI (DSOI) device structure on a DSOI substrate on the basis of the prior art and without adding an additional process. Specifically, the step of forming back gate openings in the prior art is adjusted before the step of forming a gate structure, and then the formed back gate openings are filled with a gate material layer deposited in the gate structure forming process at the same time, so that after the subsequent etching step and conductive plug filling step, conductive plugs formed by means of the back gate openings comprise not only a conductive material, but also a gate material. Thus, after an interlayer dielectric layer is deposited, and when the conductive plugs are formed in a CT etching process, a process risk caused by extreme step difference caused by the DSOI substrate being relatively thick in the DSOI structure is avoided.

Description

Semiconductor device and manufacturing method thereof

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

Silicon on Insulator (SOI, Silicon on Insulator) materials have an insulating layer (usually silicon dioxide) between the top silicon film and the substrate as isolation. The integrated circuit technology using this material makes MOS (metal oxide semiconductor field effect transistor) and other devices on the top silicon film, which is a kind of full dielectric isolation technology. This technology completely eliminates the latch-up effect of the traditional bulk silicon process; it has the advantages of small parasitic capacitance, high speed, low power consumption, and high integration. However, due to the existence of the electrically neutral body region and the influence of the full dielectric isolation structure, when the MOS device is in a bulk suspension state, electron-hole pairs generated by carrier impact ionization will flow to the body region and accumulate in the body region. Raise the body potential. This brings a series of parasitic effects, such as "Kink" effect (warping effect), single-tube latch-up effect and memory effect, etc., which affect the characteristics of MOS transistors and integrated circuit performance. In order to solve the body suspension effect, the body region is usually drawn out of the source region or grounded to form a discharge path for the body region charge.

The Double Silicon On Insulator (DSOI) is formed by adding a silicon dioxide layer (SiO2) and a single crystal silicon layer (Si) on the basis of the Silicon On Insulator (SOI). It not only has the excellent anti-single event effect ability of the SOI structure, It also adds the advantage of using the middle silicon layer to lead out the back gate terminal and applying different back bias voltage modulations to different devices. Compared with ordinary bulk silicon technology and SOI technology, the DSOI structure has great improvements in radiation resistance, circuit-sensor crosstalk suppression and chip area saving, and has been widely used in the industry.

Figure 1 is a schematic diagram of a typical DSOI structure back gate modulation device, in which BW1 and BW2 are different back gate openings, which are led out from the opening to the back gate, and different potentials are applied to modulate the device respectively. It can be seen from the schematic diagram that a major risk of this process is that when the contact hole is etched, the step difference between the highest point and the lowest point is close to

(the distance difference from the bottom of the conductive plug 270 on the top surface of the gate structure 350 to the bottom of the conductive plug 270 formed in BW2), usually, the thickness of the interlayer dielectric layer (ILD) is

That is to say, the deepest CT formed on the DSOI substrate can reach

When multiple CTs of the device are formed on the DSOI substrate, as shown in Figure 1, it is necessary to ensure that the contact hole CT in the deepest BW2 is etched clean, and to ensure the contact on the top surface of the shallowest gate structure 350 Hole CT will not be over-etched, that is, the CT etching standard is very high, not only the error tolerance space is very small, but also there are major hidden dangers in the process.

For the problem, the industry currently has no good solution. Usually, the size CD of the contact hole CT is artificially increased and the etching process of the contact hole CT is adjusted to the limit to meet the demand as much as possible. However, in practice, the effect is not good. good.

Contents of the invention

The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof, to propose a method for forming a DSOI device structure on the basis of the prior art without adding an additional process double SOI substrate, to solve the problem of DSOI device structure The problem of the small etching tolerance space of the contact hole formed due to the double SOI substrate.

In order to solve the above technical problems, the present invention provides a manufacturing method of a semiconductor device, the manufacturing method comprising:

A double SOI substrate having a gate region and a back gate region is provided, the double SOI substrate has a bottom semiconductor layer, a first buried insulating layer, a middle semiconductor layer, a second buried insulating layer and a top semiconductor layer stacked sequentially from bottom to top semiconductor layer;

Etching and filling the top semiconductor layer and the middle semiconductor layer in the double SOI substrate to form a shallow trench isolation in the remaining double SOI substrate in the gate region and the back gate region respectively structure;

performing an etching process on the double SOI substrate corresponding to the back gate region to form a first back gate opening whose bottom exposes the rest of the middle semiconductor layer and a bottom in the double SOI substrate in the back gate region a second back gate opening exposing a remaining portion of the bottom semiconductor layer;

forming a gate material layer overlying the surface of the remaining top semiconductor layer in the gate region and the surface of the remaining shallow trench isolation structure in the back gate region while simultaneously filling at least the back gate region the first back gate opening and the second back gate opening formed in;

performing an etching process on the gate material layer to form a gate stack structure in the gate region, and at the same time selectively remove the gate material filled in the first back gate opening and the second back gate opening a partial thickness layer of gate material;

Conductive plugs are formed on the surface of the gate stack structure and the remaining gate material layer in the first and second back gate openings.

Further, the material of the bottom semiconductor layer, the middle semiconductor layer and the top semiconductor layer may include silicon, and the material of the first buried insulating layer and the second buried insulating layer may include silicon dioxide.

Further, the top semiconductor layer and the middle semiconductor layer in the double SOI substrate are etched and filled, so as to respectively form a shallow SOI substrate in the gate region and the back gate region. The steps of the trench isolation structure may include:

sequentially forming a pad oxide layer, a silicon nitride layer and a first photoresist layer on the surface of the double SOI substrate;

Using the first photoresist layer as a mask, etch the silicon nitride layer, the pad oxide layer and the top semiconductor layer for the first time, so as to retain part of the top semiconductor layer covering the gate region , while removing all of the top semiconductor layer overlying the back gate region;

performing a second etching on the second buried insulating layer and the middle semiconductor layer to respectively form a bottom exposed part of the first double SOI substrate in the gate region and the back gate region; a shallow trench for the insulating buried layer;

Filling the shallow trench with an insulating isolation dielectric layer to form the shallow trench isolation structure, and the insulating isolation dielectric layer extends to cover the surface of the second insulating buried layer exposed after the first etching .

Further, an etching process is performed on the double SOI substrate corresponding to the back gate region, so as to form a first back gate opening whose bottom exposes the rest of the middle semiconductor layer in the double SOI substrate of the back gate region and a step of exposing the bottom of the second back gate opening of the remaining portion of the bottom semiconductor layer may include:

forming a second photoresist layer on the surface of the shallow trench isolation structure and on the surface of the part of the top semiconductor layer covering the gate region after the first etching;

Using the second photoresist layer as a mask, etching the insulating isolation dielectric layer in the back gate region and the second insulating buried layer thereunder to form the first back gate opening ;

Form a third photoresist layer on the surface of the double SOI substrate formed with the first back gate opening, and use the third photoresist layer as a mask to form a The shallow trench isolation structure and the first buried insulating layer are etched to form the second back gate opening.

Further, the etching process for forming the gate stack structure in the gate region may be dry etching or wet etching.

Further, the gate material layer may include doped polysilicon material, and the doping ion type of the polysilicon material may be N-type ions.

Further, after forming the gate stack structure and before forming the conductive plug, the method may further include:

A sidewall material layer is deposited on the surface of the double SOI substrate in the gate region, and an etching process is performed on the sidewall material layer to form a sidewall on the sidewall of the gate stack structure.

Further, the step of forming a conductive plug on the surface of the gate stack structure and on the surface of the remaining gate material layer in the first back gate opening and the second back gate opening may include:

An interlayer dielectric layer is deposited on the double SOI substrate on which the gate stack structure is formed, and an etching process is performed on the interlayer dielectric layer, so that on the surface of the gate stack structure and the first Contact holes are respectively formed on the surface of the back gate opening and the remaining gate material layer in the second back gate opening, and the bottom of the contact hole exposes the top surface of the gate stack structure, the gate in the first back gate opening the surface of the electrode material layer or the surface of the gate material layer in the second back gate opening;

A conductive material is filled in the contact hole to form a conductive plug in the contact hole.

Further, before forming the conductive plug in the contact hole, the method for preparing the semiconductor structure may further include:

forming a metal layer on the bottom surface exposed in the contact hole;

A silicide process is performed on the double SOI substrate formed with the metal layer to form a gold silicide layer at the bottom in the contact hole.

Based on the above-mentioned manufacturing method of the semiconductor device, the present invention also provides a semiconductor device manufactured by the manufacturing method.

Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

The present invention provides a method for forming a DSOI device structure on a double SOI substrate without adding additional processes on the basis of the prior art. Specifically, it adjusts the steps of forming the back gate opening in the prior art Before the step of forming the gate structure, then, using the gate material layer deposited during the formation of the gate structure will simultaneously fill up the formed back gate opening, so that after the subsequent etching step and conductive plug filling step Afterwards, the conductive plug formed through the back gate opening contains not only the conductive material, but also the gate material, so that the DSOI structure is avoided when the conductive plug is formed in the CT etching process after depositing the interlayer dielectric layer The process risk caused by the extreme step difference caused by the thick double SOI substrate.

Description of drawings

Fig. 1 is a schematic structural diagram of a typical DSOI structure back gate modulation device in the prior art;

Fig. 2 is a kind of manufacturing method flowchart of semiconductor device provided by the present invention;

3a to 3g are structural schematic diagrams of a semiconductor device during the manufacturing process in an embodiment of the present invention;

Wherein, the reference signs are as follows:

100-double SOI substrate; 101-bottom semiconductor layer;

102-the first insulating buried layer; 103/103’/203’-the middle semiconductor layer;

104/104’-second insulating buried layer; 105/105’/205’-top semiconductor layer;

201-shallow trench isolation structure; 110-pad oxide layer;

120-silicon nitride layer; 130-the first photoresist layer;

140-second photoresist layer; 150/150'-gate material layer;

BW1-the first back gate opening; BW2-the second back gate opening;

250/350-gate stack structure; 251-side wall;

160/260-interlayer dielectric layer; 170/270-conductive plug.

Detailed ways

As described in the background technology, as shown in Figure 1, Figure 1 is a schematic diagram of a typical DSOI structure back gate modulation device, wherein BW1 and BW2 are different back gate openings, which are drawn from the opening to the back gate, and different potentials are applied to the device. Modulate separately. It can be seen from the schematic diagram that a major risk of this process is that when the contact hole is etched, the step difference between the highest point and the lowest point is close to

That is to say, the deepest CT formed on the DSOI substrate can reach

For this reason, the present invention provides a kind of semiconductor device and manufacturing method thereof, to propose a method for forming a DSOI device structure on the basis of the prior art without adding an additional process on a double SOI substrate, to solve the problem of DSOI In the device structure, due to the double SOI substrate, the etching fault tolerance space of the contact hole formed is small.

Referring to FIG. 2 , FIG. 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, the manufacturing method of the semiconductor device includes the following steps:

Step S100, providing a double SOI substrate with a gate region and a back gate region, the double SOI substrate has a bottom semiconductor layer, a first buried insulating layer, a middle semiconductor layer, a second buried insulating layer stacked in sequence from bottom to top. layer and the top semiconductor layer.

Step S200, etching and filling the top semiconductor layer and the middle semiconductor layer in the double SOI substrate, so as to respectively form a shallow SOI substrate in the gate region and the back gate region. Trench isolation structure.

Step S300, performing an etching process on the double SOI substrate corresponding to the back gate region, so as to form a first back gate opening in the double SOI substrate in the back gate region, the bottom of which exposes the rest of the middle semiconductor layer and a second back gate opening at the bottom exposing the remaining portion of the bottom semiconductor layer.

Step S400, forming a gate material layer, the gate material layer covers the surface of the remaining top semiconductor layer in the gate region and the surface of the remaining shallow trench isolation structure in the back gate region, and at the same time fills up at least The first back gate opening and the second back gate opening are formed in the back gate region.

Step S500, performing an etching process on the gate material layer to form a gate stack structure in the gate region, and at the same time selectively remove A partial thickness layer of gate material in the opening.

Step S600 , forming conductive plugs on the surface of the gate stack structure and the remaining gate material layer in the first back gate opening and the second back gate opening.

That is, the present invention provides a method for forming a DSOI device structure on a double SOI substrate without adding additional processes on the basis of the prior art. The step is adjusted to before the step of forming the gate structure, and then, the gate material layer deposited during the formation of the gate structure will simultaneously fill up the formed back gate opening, so that after subsequent etching steps and conductive plugs After the filling step, the conductive plug formed through the back gate opening contains not only the conductive material but also the gate material, thereby avoiding The process risk caused by the extreme step difference caused by the thick double SOI substrate in the DSOI structure.

The manufacturing method of the semiconductor device proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that all the drawings are in very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

3a to 3g are schematic structural diagrams of a semiconductor device during the manufacturing process in an embodiment of the present invention.

In step S100, specifically referring to FIG. 3a, a double SOI substrate 100 having a gate region A and a back gate region B is provided, and the double SOI substrate 100 has a bottom semiconductor layer 101, which is stacked sequentially from bottom to top. The first buried insulating layer 102 , the middle semiconductor layer 103 , the second buried insulating layer 104 and the top semiconductor layer 105 . Wherein, the double SOI substrate 100 is used to provide an operation platform for producing high-precision pixel sensors (eg, CMOS image sensors) in subsequent processes. Exemplarily, the double SOI substrate 100 is formed by a silicon-on-insulator substrate SOI stacked with a buried insulating layer and a silicon layer. Moreover, the materials of the bottom semiconductor layer 101, the middle semiconductor layer 103, and the top semiconductor layer 105 may all include silicon, while the materials of the first buried insulating layer 102 and the second buried insulating layer 104 are both Silica may be included.

In this embodiment, because the substrate material of the 0.18um 1.8V/5V DSOI process used to form the high-precision pixel sensor is a double SOI substrate, and the thickness superimposition effect of the double SOI substrate, resulting in the double SOI substrate When the conductive plug of the device structure is formed on the material, the step difference between the highest point (contact hole on the gate structure) and the lowest point (contact hole of the second back gate opening) is close to

Typically, the thickness of the interlayer dielectric layer (ILD) is

That is to say, the deepest CT formed on the double SOI substrate can reach

Therefore, in the prior art, when multiple CTs of the device are formed on the double SOI substrate, the CT etching of the contact hole will appear that the deepest hole is not etched cleanly, or there is overetching in the shallowest hole, which will damage the gate structure. The problem.

In step S200, as shown in FIG. 3b and FIG. 3c, the top semiconductor layer 105 and the middle semiconductor layer 103 in the double SOI substrate 100 are etched and filled, so that the gate region A and the A shallow trench isolation structure 201 is respectively formed in the remaining double SOI substrates in the back gate region B.

Specifically, in the embodiment of the present invention, it specifically provides a method of etching and filling the top semiconductor layer 105 and the middle semiconductor layer 103 in the double SOI substrate 100, so that the gate region A and the The specific implementation of forming a shallow trench isolation structure 201 in the remaining double SOI substrate in the back gate region B includes the following steps:

In step S201 , specifically referring to FIG. 3 b , a pad oxide layer 110 , a silicon nitride layer 120 and a first photoresist layer 130 are sequentially formed on the surface of the double SOI substrate 100 .

Step S202, continuing to refer to FIG. 3b, using the first photoresist layer 130 as a mask to etch the silicon nitride layer 120, the pad oxide layer 110 and the top semiconductor layer 105 for the first time, so as to A portion of the top semiconductor layer 105 ′ covering the gate region A remains, while all the top semiconductor layer covering the back gate region B is removed.

Step S203, specifically referring to FIG. 3c, performing a second etching on the second insulating buried layer 104 and the middle semiconductor layer 103, so that the remaining parts of the gate region A and the back gate region B A shallow trench whose bottom exposes part of the first buried insulating layer 102 is respectively formed in the double SOI substrate 100 .

Step S204, continue referring to FIG. 3c, filling the shallow trench with an insulating isolation dielectric layer to form the shallow trench isolation structure 201, and the insulating isolation dielectric layer extends to cover the first etching on the exposed surface of the second buried insulating layer 104 ′.

In this embodiment, a pad oxide layer 110, a silicon nitride layer 120, and a first photoresist layer 130 may be sequentially formed on the top surface of the double SOI substrate 100 provided in the above step S100, and then the pad oxide layer 110 and Under the protection of the silicon nitride layer 120, perform a dry or wet etching process on the top semiconductor layer 105 in the double SOI substrate 100, thereby removing part of the top semiconductor layer in the gate region A and the All of the top semiconductor layer in the back gate region B, so as to obtain a part of the top semiconductor layer 105' as shown in FIG. 3b. Afterwards, a photoresist layer (not shown) is formed again on the double SOI substrate 100 after the process is completed, so as to protect the second insulating buried layer 104 and the middle semiconductor layer 104 in the double SOI substrate 100. Layer 103 is etched to form a second buried insulating layer 104' and a middle semiconductor layer 103' as shown in FIG. The two shallow trenches exposed by 100 are filled with an insulating isolation dielectric layer, thereby forming two shallow trench isolation structures 201 as shown in FIG. 3c.

In step S300, specifically referring to FIG. 3d, an etching process is performed on the double SOI substrate corresponding to the back gate region B to form a bottom in the double SOI substrate of the back gate region B to expose the remaining A portion of the first back gate opening BW1 of the middle semiconductor layer 103 ′ and a second back gate opening BW2 of a bottom exposing the rest of the bottom semiconductor layer 101 .

In this embodiment, after the structure shown in FIG. 3c is formed in step S200, a layer of photoresist layer 140 with a certain thickness can be formed on the surface of the structure, so that the gate region A and the unformed back gate The other back gate regions of the openings are protected, and then, the structure formed with the photoresist layer 140 is etched twice by using photolithography and/or etching process, so as to form the first back gate opening BW1 and the first back gate opening BW1. Describe the second back gate opening BW2.

Specifically, the present invention provides an etching process for the double SOI substrate corresponding to the back gate region B, so as to form a middle part in the double SOI substrate of the back gate region B with the bottom exposed A specific implementation of the first back gate opening BW1 of the semiconductor layer 103' and the second back gate opening BW2 of a bottom that exposes the remaining part of the bottom semiconductor layer 101 may include the following steps:

Step S301, forming a second photoresist layer 140 on the surface of the shallow trench isolation structure 201 and on the surface of the part of the top semiconductor layer 105' covered in the gate region A after the first etching.

Step S302, using the second photoresist layer 140 as a mask, etch the insulating and isolating dielectric layer in the back gate region B and the second insulating buried layer 104' under it, to form The first back gate opening BW1.

Step S303, forming a third photoresist layer (not shown) on the surface of the double SOI substrate formed with the first back gate opening BW1, and using the third photoresist layer as a mask and etching the shallow trench isolation structure 201 and the first buried insulating layer 102 formed in the back gate region B to form the second back gate opening BW2.

It can be understood that, in the accompanying drawing 3d provided in this embodiment, in order to simplify the figure, only one layer of photoresist layer 140 is drawn, which is essentially the first back gate opening BW1 and the second back gate opening BW1. The gate opening BW2 is exposed and developed by using different photoresist layers, which includes the deposition and removal of multi-layer film layers, and this content is the prior art, so the present invention does not specifically limit it.

In step S500, specifically referring to FIG. 3e, a gate material layer 150 is formed, and the gate material layer 150 covers the surface of the remaining top semiconductor layer 105' in the gate region A and the remaining surface of the back gate region B. on the surface of the shallow trench isolation structure 201 , and at least fill up the first back gate opening BW1 and the second back gate opening BW2 formed in the back gate region B at the same time. Wherein, the gate material layer 150 includes doped polysilicon material, and the doping ion type of the polysilicon material is N-type ions.

In this embodiment, the step of forming the back gate opening in the prior art is adjusted before the step of forming the gate structure, and then, the gate material layer deposited during the formation of the gate structure will simultaneously fill up the existing The back gate opening is formed, so that after the subsequent etching step and the conductive plug filling step, the conductive plug formed through the back gate opening contains not only the conductive material, but also the gate material, so that when the interlayer dielectric is deposited After the layer, and when the conductive plug is formed in the CT etching process, the process risk caused by the extreme step difference caused by the thick dual SOI substrate thickness in the DSOI structure is avoided.

In step S600, specifically referring to FIG. 3f, an etching process is performed on the gate material layer 150 to form a gate stack structure 250 in the gate region A, and at the same time selectively remove and fill in the Partial thickness of the gate material layer 150 in the first back gate opening BW1 and the second back gate opening BW2.

In this embodiment, the gate material layer 150 may be etched by dry etching or wet etching, so as to form the gate stack structure 250 . When the gate material layer 150 is etched, the end point detection method can be used, that is, by controlling the etching process parameters of the etching process to determine the amount of etching removal, and then, in this embodiment , the depths of the first back gate opening BW1 and the second back gate opening BW2 are relatively deep, so that when the gate material layer 150 is etched by the endpoint detection method, most of the gate material layer 150 covered by the area is covered It is etched away, and the gate material layers of the first back gate opening BW1 and the second back gate opening BW2 are left due to their relatively thick thickness, thereby forming a structure as shown in FIG. 3f.

Further, after forming the gate stack structure 250 and before forming the conductive plug in the following step S600, the manufacturing method of the semiconductor device provided by the present invention may further include the following steps:

Step S501, depositing a sidewall material layer (not shown) on the surface of the double SOI substrate in the gate region A, and performing an etching process on the sidewall material layer, so that the gate stack structure Side walls 251 are formed on the side walls of 250 .

In step S600, as shown in FIG. A conductive plug 170 is formed.

In this embodiment, after forming the structure shown in FIG. Parts of the electrode stack structure 250, the first back gate opening BW1 and the second back gate opening BW2 are subjected to a photolithography and/or etching process to form corresponding contact holes, and then, the contact holes are filled with a conductive material, thereby The conductive plug 170 is formed. Since the conductive plugs 170 formed in the first back gate opening BW1 and the second back gate opening BW2 in the present invention are not directly formed from the bottom of the openings, but a gate material layer 150' with a certain thickness is deposited first, Therefore, the process risk caused by the extreme step difference caused by the thick double SOI substrate in the DSOI structure is avoided.

Specifically, the present invention also provides a method of forming on the surface of the gate stack structure 250 and the remaining gate material layer 150' in the first back gate opening BW1 and the second back gate opening BW2. The specific implementation of the conductive plug 170 includes the following steps:

Step S601, depositing an interlayer dielectric layer 160 on the double SOI substrate on which the gate stack structure 250 is formed, and performing an etching process on the interlayer dielectric layer 160, so that the gate stack structure 250 Contact holes are respectively formed on the surface and the remaining gate material layer 150' in the first back gate opening BW1 and the second back gate opening BW2, and the bottom of the contact holes exposes the gate stack structure 250. The top surface, the surface of the gate material layer 150' in the first back gate opening BW1 or the surface of the gate material layer 150' in the second back gate opening BW2.

Step S602 , filling the contact hole with a conductive material to form a conductive plug 170 in the contact hole.

In addition, before forming the conductive plug 170 in the contact hole, the manufacturing method of the semiconductor structure provided by the present invention may further include the following steps:

Step S601.1, forming a metal layer (not shown) on the exposed bottom surface of the contact hole.

Step S601.2, performing a silicide process on the double SOI substrate formed with the metal layer, so as to form a gold silicide layer (not shown) at the bottom of the contact hole.

In addition, based on the manufacturing method of the above-mentioned semiconductor device, the present invention also provides a semiconductor device. For the specific forming method, refer to the above-mentioned manufacturing method of the semiconductor device, which will not be repeated here.

In summary, the present invention provides a method for forming a DSOI device structure on a double SOI substrate without adding additional processes on the basis of the prior art. The step of gate opening is adjusted before the step of forming the gate structure, and then, the gate material layer deposited in the process of forming the gate structure will be used to fill up the formed back gate opening at the same time, so that after subsequent etching steps and After the conductive plug filling step, the conductive plug formed through the back gate opening contains not only the conductive material, but also the gate material, so that after the deposition of the interlayer dielectric layer, and when the conductive plug is formed by the CT etching process , which avoids the process risk caused by the extreme step difference caused by the thick double SOI substrate in the DSOI structure.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the protection scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures belong to the protection scope of the present invention.

In addition, it should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings according to exemplary embodiments of the present invention. .

For ease of description, spatially relative terms may be used here, such as "under", "over", "below", "above", "above", "upper" and "Lower layer" and the like are used to describe the spatial positional relationship between one element or feature and other elements or features as shown in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "beneath" the other elements or features. other elements or features". Thus, the exemplary term "below" can encompass both an orientation of "above" and "beneath". The device may be oriented in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terms used herein are for describing specific embodiments only, and are not intended to limit exemplary embodiments according to the present invention. As used herein, singular forms are intended to include plural forms unless the context clearly dictates otherwise. In addition, it should also be understood that when the terms "comprising" and/or "comprising" are used in this specification, it indicates the presence of the features, integers, steps, operations, elements and/or components, but does not exclude the presence or One or more other features, integers, steps, operations, elements, components and/or combinations thereof are added.

The foregoing are only preferred embodiments of the present invention, and do not limit the present invention in any way. Any person skilled in the technical field, within the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the technical solution of the present invention. The content still belongs to the protection scope of the present invention.

Claims

A method for manufacturing a semiconductor device, comprising:

A double SOI substrate having a gate region and a back gate region is provided, the double SOI substrate has a bottom semiconductor layer, a first buried insulating layer, a middle semiconductor layer, a second buried insulating layer and a top semiconductor layer stacked sequentially from bottom to top semiconductor layer;

Etching and filling the top semiconductor layer and the middle semiconductor layer in the double SOI substrate to form a shallow trench isolation in the remaining double SOI substrate in the gate region and the back gate region respectively structure;

performing an etching process on the double SOI substrate corresponding to the back gate region to form a first back gate opening whose bottom exposes the rest of the middle semiconductor layer and a bottom in the double SOI substrate in the back gate region a second back gate opening exposing a remaining portion of the bottom semiconductor layer;

forming a gate material layer overlying the surface of the remaining top semiconductor layer in the gate region and the surface of the remaining shallow trench isolation structure in the back gate region while simultaneously filling at least the back gate region the first back gate opening and the second back gate opening formed in;

performing an etching process on the gate material layer to form a gate stack structure in the gate region, and at the same time selectively remove the gate material filled in the first back gate opening and the second back gate opening a partial thickness layer of gate material;

Conductive plugs are formed on the surface of the gate stack structure and the remaining gate material layer in the first and second back gate openings.
The manufacturing method of a semiconductor device according to claim 1, wherein the material of the bottom semiconductor layer, the middle semiconductor layer and the top semiconductor layer comprises silicon, and the first insulating buried layer and the second insulating buried layer The material includes silicon dioxide.
The manufacturing method of a semiconductor device as claimed in claim 1, wherein the top semiconductor layer and the middle semiconductor layer in the double SOI substrate are etched and filled, so that the gate region and the back The step of forming a shallow trench isolation structure respectively in the remaining double SOI substrate in the gate region includes:

A pad oxide layer, a silicon nitride layer and a first photoresist layer are sequentially formed on the surface of the double SOI substrate;

Using the first photoresist layer as a mask, etch the silicon nitride layer, the pad oxide layer and the top semiconductor layer for the first time, so as to retain part of the top semiconductor layer covering the gate region , while removing all of the top semiconductor layer overlying the back gate region;

performing a second etching on the second buried insulating layer and the middle semiconductor layer to respectively form a bottom exposed part of the first double SOI substrate in the gate region and the back gate region; a shallow trench for the insulating buried layer;

Filling the shallow trench with an insulating isolation dielectric layer to form the shallow trench isolation structure, and the insulating isolation dielectric layer extends to cover the surface of the second insulating buried layer exposed after the first etching .
The method for manufacturing a semiconductor device according to claim 3, wherein an etching process is performed on the double SOI substrate corresponding to the back gate region to form a bottom in the double SOI substrate in the back gate region The step of exposing a first back gate opening of the remaining part of the middle semiconductor layer and a second back gate opening at the bottom of which exposing the remaining part of the bottom semiconductor layer comprises:

forming a second photoresist layer on the surface of the shallow trench isolation structure and on the surface of the part of the top semiconductor layer covering the gate region after the first etching;

Using the second photoresist layer as a mask, etching the insulating isolation dielectric layer in the back gate region and the second insulating buried layer thereunder to form the first back gate opening ;

Form a third photoresist layer on the surface of the double SOI substrate formed with the first back gate opening, and use the third photoresist layer as a mask to form a The shallow trench isolation structure and the first buried insulating layer are etched to form the second back gate opening.
The method for manufacturing a semiconductor device according to claim 1, wherein the etching process for forming the gate stack structure in the gate region is dry etching or wet etching.
The manufacturing method of a semiconductor device according to claim 1, wherein the gate material layer comprises a doped polysilicon material, and the doping ion type of the polysilicon material is N-type ions.
The method for manufacturing a semiconductor device according to claim 1, wherein after forming the gate stack structure and before forming the conductive plug, the method further comprises:

A sidewall material layer is deposited on the surface of the double SOI substrate in the gate region, and an etching process is performed on the sidewall material layer to form a sidewall on the sidewall of the gate stack structure.
The method for manufacturing a semiconductor device according to claim 1, wherein on the surface of the gate stack structure and the surface of the remaining gate material layer in the first back gate opening and the second back gate opening The steps of forming the conductive plug include:

An interlayer dielectric layer is deposited on the double SOI substrate on which the gate stack structure is formed, and an etching process is performed on the interlayer dielectric layer, so that on the surface of the gate stack structure and the first Contact holes are respectively formed on the surface of the back gate opening and the remaining gate material layer in the second back gate opening, and the bottom of the contact hole exposes the top surface of the gate stack structure, the gate in the first back gate opening the surface of the electrode material layer or the surface of the gate material layer in the second back gate opening;

A conductive material is filled in the contact hole to form a conductive plug in the contact hole.
The method for preparing a semiconductor structure according to claim 8, wherein, before forming the conductive plug in the contact hole, the method for preparing the semiconductor structure further comprises:

forming a metal layer on the bottom surface exposed in the contact hole;

A silicide process is performed on the double SOI substrate formed with the metal layer to form a gold silicide layer at the bottom in the contact hole.
A semiconductor device, characterized in that it is manufactured by the manufacturing method according to any one of claims 1 to 9.