WO2023082702A1 - Puce pour transmission de signaux à haute vitesse, et structure d'empilement de puces - Google Patents

Puce pour transmission de signaux à haute vitesse, et structure d'empilement de puces Download PDF

Info

Publication number
WO2023082702A1
WO2023082702A1 PCT/CN2022/107767 CN2022107767W WO2023082702A1 WO 2023082702 A1 WO2023082702 A1 WO 2023082702A1 CN 2022107767 W CN2022107767 W CN 2022107767W WO 2023082702 A1 WO2023082702 A1 WO 2023082702A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
ground pad
transmission line
electrically connected
signal
Prior art date
Application number
PCT/CN2022/107767
Other languages
English (en)
Chinese (zh)
Inventor
胡立辉
李志伟
于飞
史文俊
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2023082702A1 publication Critical patent/WO2023082702A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps

Definitions

  • the present application relates to the field of chip technology, and in particular to a chip for high-speed signal transmission, a chip stacking structure, a chip packaging structure and electronic equipment.
  • the transmission rate of signals between any two chips needs to be further improved (for example, requires The transmission rate is increased to 200Gbps), so that the transmission rate of the communication link of the communication system to which any two chips belong is also increased.
  • bandwidth is an important factor affecting the transmission rate. Specifically, the larger the bandwidth, the higher the transmission rate; the smaller the bandwidth, the lower the transmission rate. For two chips, the greater the bandwidth between them, the greater the signal transmission rate between the two chips.
  • two chips are usually connected by wire bonding (WB).
  • the first chip 31 and the second chip 32 are connected by wires 5 .
  • the present application provides a chip for high-speed signal transmission and a chip stacking structure, which are used to solve the problem of limited signal transmission rate between two chips in the prior art.
  • the present application also provides a chip packaging structure and electronic equipment including the aforementioned chip or the aforementioned chip stacking structure.
  • the present application provides a chip, which includes a signal pad, a first ground pad, an active area, a first transmission line, and a second transmission line.
  • the signal pad is electrically connected to the active area through the first transmission line
  • the first ground pad is electrically connected to the active area through the second transmission line.
  • the length of the second transmission line is less than the distance between the signal pad and the first ground pad and the first The sum of the lengths of the transmission lines.
  • the signal pad is closer to the first edge of the chip relative to the active area, the first ground pad is closer to the first edge of the chip than the active area, or the distance between the first ground pad and the first edge and the active area The distance from the region to the first edge is equal.
  • reducing the equivalent inductance of the second transmission line by reducing the length of the second transmission line is conducive to improving the resonant frequency of the transmission link between any two chips, thereby improving the inductance of any two chips. transfer rate between.
  • the second transmission line connecting the first ground pad and the active region If it is perpendicular to the first transmission line, it can be considered to meet the equality defined here. However, the first ground pad and the active area can be located on the second transmission line, and it is not necessary to limit that their geometric centers must be located on the second transmission line. Transmission line.
  • the second transmission line is a straight line or a broken line.
  • the first transmission line is a straight line.
  • the chip further includes a second ground pad and a third transmission line, and the second ground pad and the active region pass through The third transmission line is electrically connected, and the length of the third transmission line is less than the sum of the distance from the signal pad to the second ground pad and the length of the first transmission line.
  • the signal pad is closer to the first edge of the chip relative to the active area
  • the second ground pad is closer to the first edge of the chip than the active area, or the distance between the second ground pad and the first edge and the active area The distance from the region to the first edge is equal.
  • reducing the equivalent inductance of the third transmission line by reducing the length of the third transmission line is conducive to improving the resonant frequency of the transmission link between any two chips, thereby improving the inductance of any two chips. transfer rate between.
  • the third transmission line is a straight line or a broken line.
  • the chip further includes a first auxiliary ground pad, and the first The second transmission line includes a first section of transmission line and a second section of transmission line.
  • the first auxiliary ground pad is electrically connected to the active area through a first transmission line
  • the first auxiliary ground pad is electrically connected to the first ground pad through a second transmission line.
  • the equivalent capacitance of the transmission link is reduced by increasing the first auxiliary ground pad, which is conducive to improving the resonant frequency of the transmission link between any two chips, thereby improving the transfer rate between.
  • the chip is a photodiode PD chip, or, the The above chip is a transimpedance amplifier TIA chip.
  • the present application further provides a chip stacking structure, the chip stacking structure includes a first chip and a second chip arranged in a stack.
  • Both the above-mentioned first chip and the above-mentioned second chip are the chips described in the first aspect or any implementation manner of the first aspect.
  • the signal pads of the first chip are electrically connected to the signal pads of the second chip
  • the first ground pads of the first chip are electrically connected to the first ground pads of the second chip.
  • the first chip and the second chip are stacked, which is beneficial to shorten the interconnection path between the two chips, thereby increasing the rate of signal transmission between the first chip and the second chip.
  • both the first chip and the second chip include a first auxiliary ground pad, and the first auxiliary ground pad of the first chip and the second chip The first auxiliary ground pad is electrically connected.
  • both the first chip and the second chip include a second ground pad, and the first chip's The second ground pad is electrically connected to the second ground pad of the second chip.
  • both the first chip and the second chip include a second auxiliary ground
  • the second auxiliary ground pad of the first chip is electrically connected to the second auxiliary ground pad of the second chip.
  • the signal pad of the first chip and the first The signal pads of the two chips are electrically connected by soldering material.
  • the first ground pad of the first chip is electrically connected to the first ground pad of the second chip through soldering material.
  • the present application further provides a chip packaging structure, which includes a packaging substrate and the chip stack structure according to any one of the implementation manners of the second aspect, and the packaging substrate is electrically connected to the chip stack structure.
  • the present application further provides an electronic device, the electronic device includes a printed circuit board and the chip packaging structure described in the third aspect, the printed circuit board is electrically connected to the chip packaging structure.
  • Figure 1 is a schematic structural diagram of a WB connection between any two chips
  • FIG. 2 is a schematic structural diagram of the electronic device 1;
  • FIG. 3 is a schematic diagram of the internal structure of the optical module
  • FIG. 4 is a schematic structural view of the first chip 31
  • FIG. 5 is a schematic structural view of the second chip 32
  • FIG. 6 is a schematic structural diagram of a first chip 31 and a second chip 32 stacked
  • 7A-7B are simulation data diagrams of signal transmission performance between the first chip 31 and the second chip 32;
  • FIG. 9 is an equivalent circuit diagram in which the first chip 31 and the second chip 32 are electrically connected by FC;
  • 10A-10B are simulation data diagrams of signal transmission performance between the first chip 31 and the second chip 32 .
  • the embodiment of the present application provides an electronic device 1 .
  • the electronic device 1 includes, but is not limited to, an optical communication device, where the optical communication device may be, for example, an optical module, an optical engine, and an optical device.
  • the electronic device 1 includes a chip package structure 10, a printed circuit board (printed circuit board, PCB) 11 and an electrical connection structure 12, and the chip package structure 10 is electrically connected to the PCB 11 through the electrical connection structure 12, so that the chip package The structure 10 can realize signal transmission with other devices on the PCB 11 .
  • a chip package structure 10 a printed circuit board (printed circuit board, PCB) 11 and an electrical connection structure 12, and the chip package structure 10 is electrically connected to the PCB 11 through the electrical connection structure 12, so that the chip package The structure 10 can realize signal transmission with other devices on the PCB 11 .
  • the electrical connection structure 12 may be a ball grid array (BGA), or a flexible printed circuit (FPC).
  • BGA ball grid array
  • FPC flexible printed circuit
  • the electrical connection structure 12 can also use a connection terminal with a slot-type fixing structure. (socket), the connection terminal can also be called a connector or a socket.
  • Figure 3 shows the main functional modules and connections between modules in a typical optical module.
  • the electronic device 1 may also include a transmitting optical component (Transmitter Optical Sub-Assembly, TOSA), a clock signal recovery (Clock Data Recovery, CDR) or an optical digital signal processing (Optical Digital Signal Process, oDSP).
  • TOSA Transmitter Optical Sub-Assembly
  • CDR clock Data Recovery
  • oDSP optical digital signal processing
  • the above-mentioned chip package structure 10 can be used as a Receiver Optical Sub-Assembly (ROSA).
  • ROSA Receiver Optical Sub-Assembly
  • the signal flow direction in the optical module is: the electrical signal transmitted from the PCB11 is shaped by the CDR or oDSP and transmitted to the TOSA.
  • the TOSA is used to convert the electrical signal into an optical signal and transmit the optical signal into the optical fiber.
  • ROSA receives the optical signal from the optical fiber, converts the optical signal into an electrical signal, and transmits the electrical signal to the CDR or oDSP, and the CDR or oDSP restores the electrical signal.
  • the chip package structure 10 will be described below.
  • the chip package structure 10 includes a chip stack structure 20 , a package substrate 21 and a solder bump 22 .
  • the chip stack structure 20 is fixed on a package substrate 21 , and the package substrate 21 is used to carry the chip stack structure 20 .
  • the chip stack structure 20 can be electrically connected to the packaging substrate 21 through bumps 22 .
  • the embodiment of the present application also provides a chip stacking structure 20 .
  • the chip stack structure 20 includes a first chip 31 , a second chip 32 and soldering materials.
  • the first chip 31 and the second chip 32 are stacked and arranged, and the first chip 31 and the second chip 32 are electrically connected by soldering material.
  • the soldering material may be a copper pillar (Copper Pillar) or a flip-chip flip-chip soldering bump (Controlled Collapsed Chip Connection Bump, C4Bump) or a gold bump (Gold Bump).
  • the first chip 31 and the second chip 32 are connected in a flip chip (Flip Chip, FC) manner.
  • FC Flip Chip
  • the interconnection path between the first chip 31 and the second chip 32 can be shortened, thereby increasing the rate of signal transmission between the first chip 31 and the second chip 32 .
  • the first chip 31 includes an active area 310 , a first ground pad 311 , a second ground pad 312 , a signal pad 313 , a first transmission line 314 , a second transmission line 315 and a third transmission line 316 .
  • the active area 310 is the part where the first chip 31 performs functions
  • the signal pad 313 is used for signal transmission
  • the first ground pad 311 and the second ground pad 312 are used for ground protection.
  • the signal pad 313 is electrically connected to the active area 310 through the first transmission line 314; the first ground pad 311 is electrically connected to the active area 310 through the second transmission line 315; the second ground pad 312 is electrically connected to the active area 310 through the third
  • the transmission line 316 is electrically connected.
  • the second chip 32 includes an active area 320, a first ground pad 321, a second ground pad 322, a signal pad 323, a first transmission line 324, a second transmission line 325 and a third transmission line 326 .
  • the active area 320 is the part where the second chip 32 performs functions
  • the signal pad 323 is used for signal transmission
  • the first ground pad 321 and the second ground pad 322 are used for ground protection.
  • the signal pad 323 is electrically connected to the active area 320 through the first transmission line 324; the first ground pad 321 is electrically connected to the active area 320 through the second transmission line 325; the second ground pad 322 is electrically connected to the active area 320 through the third
  • the transmission line 326 is electrically connected.
  • the first chip 31 and the second chip 32 are connected in a FC manner.
  • the first ground pad 311 , the second ground pad 312 and the signal pad 313 of the first chip 31 are regularly arranged, that is, the above three pads are located on the same straight line.
  • the first ground pad 321 , the second ground pad 322 and the signal pad 323 of the second chip 32 are regularly arranged, that is, the above three pads are located on the same straight line.
  • the first ground pad 311 of the first chip 31 is electrically connected to the first ground pad 321 of the second chip 32; the second ground pad 312 of the first chip 31 is electrically connected to the second ground pad 322 of the second chip 32 Connection; the signal pad 313 of the first chip 31 is electrically connected to the signal pad 323 of the second chip 32 .
  • the above-mentioned first chip 31 may be an optical chip, such as a photodiode (Photo Diode, PD) or APD (Avalanche Photo Diode, avalanche photodiode).
  • the above-mentioned second chip 32 may be an electrical chip, such as a TIA (Trans-impedance Amplifier, transimpedance amplifier).
  • the chip packaging structure 10 may be a ROSA.
  • the signal flow direction in the chip packaging structure 10 is: the optical signal transmitted from the optical fiber is transmitted to the PD, the PD converts the optical signal into an electrical signal, and transmits the electrical signal to the TIA, and the TIA amplifies the electrical signal, and
  • the amplified electrical signal is transmitted to other electrical processing chips on the electronic device 1 , such as CDR or oDSP, and the amplified electrical signal is further processed by the CDR or oDSP.
  • FIG. 7A is used to analyze the resonance and 3dB bandwidth of the transmission link between the first chip 31 and the second chip 32
  • FIG. 7B is used to analyze the group of the transmission link between the first chip 31 and the second chip 32. Latency performance.
  • bandwidth is an important factor affecting the transmission rate. Specifically, the larger the bandwidth, the higher the transmission rate; the smaller the bandwidth, the lower the transmission rate. Correspondingly, the greater the bandwidth between the two chips, the greater the signal transmission rate between the two chips. Resonance is an important factor that limits the bandwidth between any two chips, and at the same time, resonance will cause the group delay performance of the signal to deteriorate. Among them, resonance refers to the resonance that occurs in the transmission link between two chips.
  • the 3dB bandwidth refers to the corresponding frequency bandwidth when the amplitude of the signal is equal to twice the root of half of the maximum value.
  • the group delay performance is used to characterize the phase of each frequency component of the signal. The smaller the group delay, the smaller the phase difference of each frequency component transmission, which is more conducive to high-speed signal transmission.
  • the abscissa represents the frequency, and the unit is GHz; the ordinate represents the insertion loss of the signal attenuation, and the unit is dB. It can be seen from FIG. 7A that the signal has a large resonance at 110 GHz, and the 3dB bandwidth is 78 GHz.
  • the abscissa represents the frequency, and the unit is GHz; the ordinate represents the group delay Group Delay of the signal on the transmission link, and the unit is ps.
  • the group delay curve becomes significantly curved, that is, the flatness of the group delay curve decreases.
  • the reduced flatness of the group delay curve means that the group delay performance of the signal deteriorates sharply, which is not conducive to achieving a higher transmission rate of the signal between the first chip 31 and the second chip 32 .
  • the present application further provides a chip, which may be the above-mentioned first chip 31 or the above-mentioned second chip 32 .
  • the chip is described below through a specific embodiment.
  • the first chip 31 includes an active area 310, a first ground pad 311, a second ground pad 312, a signal pad 313, a first transmission line 314, a second transmission line 315 and The third transmission line 316 .
  • the signal pad 313 is electrically connected to the active area 310 through the first transmission line 314;
  • the first ground pad 311 is electrically connected to the active area 310 through the second transmission line 315;
  • the second ground pad 312 is electrically connected to the active area 310 through
  • the third transmission line 316 is electrically connected.
  • the length of the second transmission line 315 is less than the sum of the distance from the signal pad 313 to the first ground pad 311 and the length of the first transmission line 314 .
  • the signal pad 313 is closer to the first edge 100 of the first chip 31 relative to the active region 310
  • the first ground pad 311 is closer to the first edge 100 of the first chip 31 relative to the active region 310, or, the first The distance between the ground pad 311 and the first edge 100 and the distance between the active region 310 and the first edge 100 are equal.
  • the first transmission line 314 is a straight line.
  • the second transmission line 315 is a straight line or a broken line.
  • the third transmission line 316 is a straight line or a broken line.
  • the equality here should be based on the understanding of those skilled in the art, and should not be rigidly understood as absolute equality in the mathematical sense.
  • the second transmission line connecting the first ground pad and the active region is perpendicular to the first
  • the transmission lines can be considered to be equal as defined here. However, it is only necessary that the first ground pad and the active area be located on the second transmission line, and it is not necessary to define that their geometric centers must be located on the second transmission line.
  • the second transmission line 315 is perpendicular to the first transmission line 314
  • the third transmission line 316 is perpendicular to the first transmission line 314
  • the included angle between the second transmission line 315 and the first transmission line 314 is an acute angle
  • the included angle between the third transmission line 316 and the first transmission line 314 is an acute angle.
  • the positions of the first ground pad 311 and the second ground pad 312 may be unchanged or changed.
  • the length of the part of the second transmission line 315 parallel to the first transmission line 314 is shorter than the length of the first transmission line 314, and the length of the part of the third transmission line 316 parallel to the first transmission line 314 The length is less than the length of the first transmission line 314 .
  • the first ground pad 311 is closer to the active area 310
  • the second ground pad 312 is closer to the active area 310 .
  • the second chip 32 includes an active area 320 , a first ground pad 321 , a second ground pad 322 , a signal pad 323 , a first transmission line 324 , a second transmission line 325 and a third transmission line 326 .
  • the signal pad 323 is electrically connected to the active area 320 through the first transmission line 324;
  • the first ground pad 321 is electrically connected to the active area 320 through the second transmission line 325;
  • the second ground pad 322 is electrically connected to the active area 320 through
  • the third transmission line 326 is electrically connected.
  • the pads and transmission lines on the second chip 32 adopt the same arrangement as the pads and transmission lines on the first chip 31 , and the first chip 31 and the second chip 32 are electrically connected by FC. Specifically, the first ground pad 311 of the first chip 31 is electrically connected to the first ground pad 321 of the second chip 32; the second ground pad 312 of the first chip 31 is connected to the second ground pad of the second chip 32 The pads 322 are electrically connected; the signal pads 313 of the first chip 31 are electrically connected to the signal pads 323 of the second chip 32 .
  • C1 is the equivalent capacitance of the signal pad 313 of the first chip 31;
  • C2 is the common equivalent capacitance of the first ground pad 311 of the first chip 31 and the second ground pad 312 of the first chip 31.
  • C3 is the equivalent capacitance of the signal pad 323 of the second chip 32 ;
  • C4 is the common equivalent capacitance of the first ground pad 321 of the second chip 32 and the second ground pad 322 of the second chip 32 .
  • the above pads are all connected to ground.
  • B1 is a solder material between the signal pad 312 of the first chip 31 and the signal pad 323 of the second chip 32 .
  • B2 is between the first ground pad 311 of the first chip 31 and the first ground pad 321 of the second chip 32, and the second ground pad 312 of the first chip 31 and the first ground pad of the second chip 32. Solder material between discs 322.
  • L1 is the equivalent inductance of the first transmission line 314 of the first chip 31
  • L2 is the overall equivalent inductance of the second transmission line 315 of the first chip 31 and the third transmission line 316 of the first chip 31
  • L3 is the equivalent inductance of the first transmission line 324 of the second chip 32
  • L4 is the overall equivalent inductance of the second transmission line 325 of the second chip 32 and the third transmission line 326 of the second chip 32 .
  • the resonant frequency F of the transmission link between the first chip 31 and the second chip 32 is proportional to the reciprocal of the square root of (L*C), that is, the resonant frequency F is inversely proportional to the square root of (L*C).
  • C represents the equivalent total capacitance of the transmission link
  • L represents the equivalent total inductance of the transmission link, that is, L includes L1, L2, L3, and L4. Therefore, by reducing the length of the transmission line, the equivalent inductance of the transmission link between the first chip 31 and the second chip 32 is reduced, which is conducive to improving the resonant frequency of the transmission link, thereby improving bandwidth and group delay performance , so as to increase the transmission rate between the first chip 31 and the second chip 32 .
  • the above-mentioned first chip 31 may be an optical chip, such as PD (Photo Diode, photodiode) or APD (Avalanche Photo Diode, avalanche photodiode).
  • the above-mentioned second chip 32 may be an electrical chip, such as a TIA (Trans-impedance Amplifier, transimpedance amplifier).
  • Fig. 10A is used for analyzing the resonance and 3dB bandwidth of the transmission link between the first chip 31 and the second chip 32
  • Fig. 10B is used for analyzing the group of the transmission link between the first chip 31 and the second chip 32 Latency performance.
  • the abscissa represents the frequency, and the unit is GHz; the ordinate represents the insertion loss of the signal attenuation, and the unit is dB.
  • the WB interconnection and the traditional FC interconnection.
  • the resonant frequency of the above embodiment is extended from 110 GHz to 160 GHz, and the 3dB bandwidth is increased from 74 GHz to 105 GHz.
  • the abscissa represents the frequency, and the unit is GHz; the ordinate represents the group delay Group Delay of the signal on the transmission link, and the unit is ps.
  • the group delay curve of the above embodiment is flatter, that is, each frequency component of the signal sent by the first chip 31, after passing through the transmission link, are transmitted to the second chip 32 almost simultaneously, which shows that the above embodiment can greatly improve the group delay performance of the transmission link.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente demande concerne une puce destinée à la transmission de signaux à haute vitesse. La puce comprend une plage de signal, une première plage de masse, une zone active, une première ligne de transmission et une deuxième ligne de transmission. La longueur de la deuxième ligne de transmission est inférieure à la somme de la distance entre la plage de signal et la première plage de masse et la longueur de la première ligne de transmission. La présente demande concerne en outre une autre puce destinée à la transmission de signaux à grande vitesse. Une première plage de masse auxiliaire de la puce est électriquement connectée à la zone active au moyen de la deuxième ligne de transmission; et la première plage de masse auxiliaire est électriquement connectée à la première plage de masse au moyen d'une troisième ligne de transmission. À l'aide des deux puces fournies dans la présente demande, le débit de transmission de signaux entre deux puces quelconques peut être amélioré, ce qui permet d'améliorer le débit de transmission d'une liaison de communication d'un système de communication auquel appartiennent les deux quelconques puces. De plus, la présente demande concerne en outre une structure d'empilement de puces utilisant les puces, une structure d'encapsulation de puces et un dispositif électronique.
PCT/CN2022/107767 2021-11-09 2022-07-26 Puce pour transmission de signaux à haute vitesse, et structure d'empilement de puces WO2023082702A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111320892.X 2021-11-09
CN202111320892.XA CN116110879A (zh) 2021-11-09 2021-11-09 用于高速信号传输的芯片及芯片堆叠结构

Publications (1)

Publication Number Publication Date
WO2023082702A1 true WO2023082702A1 (fr) 2023-05-19

Family

ID=86253174

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/107767 WO2023082702A1 (fr) 2021-11-09 2022-07-26 Puce pour transmission de signaux à haute vitesse, et structure d'empilement de puces

Country Status (2)

Country Link
CN (1) CN116110879A (fr)
WO (1) WO2023082702A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110019457A1 (en) * 2009-07-23 2011-01-27 Mao Bang Electronic Co., Ltd. Flash memory
US20120112365A1 (en) * 2010-03-26 2012-05-10 Infineon Technologies Ag Semiconductor Packages and Methods For Producing The Same
JP2013131711A (ja) * 2011-12-22 2013-07-04 Taiyo Yuden Co Ltd 電子部品
US20150028477A1 (en) * 2013-07-29 2015-01-29 Yoonha JUNG Semiconductor packages having semiconductor chips disposed in opening in shielding core plate
US20190057944A1 (en) * 2017-08-18 2019-02-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110019457A1 (en) * 2009-07-23 2011-01-27 Mao Bang Electronic Co., Ltd. Flash memory
US20120112365A1 (en) * 2010-03-26 2012-05-10 Infineon Technologies Ag Semiconductor Packages and Methods For Producing The Same
JP2013131711A (ja) * 2011-12-22 2013-07-04 Taiyo Yuden Co Ltd 電子部品
US20150028477A1 (en) * 2013-07-29 2015-01-29 Yoonha JUNG Semiconductor packages having semiconductor chips disposed in opening in shielding core plate
US20190057944A1 (en) * 2017-08-18 2019-02-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package

Also Published As

Publication number Publication date
CN116110879A (zh) 2023-05-12

Similar Documents

Publication Publication Date Title
US9921379B2 (en) Compact optical transceiver by hybrid multichip integration
US10120150B2 (en) Optical transceiver by FOWLP and DOP multichip integration
US11221452B2 (en) Communication receiver
JP4662986B2 (ja) 光−電気インターフェース、フレキシブルオプトエレクトロニクス相互接続、光トランスポンダ
US7668414B2 (en) System and method for the fabrication of an electro-optical module
JP6287105B2 (ja) 光通信デバイス、受信装置、送信装置及び送受信システム
US20210193638A1 (en) Optical Communication Apparatus
US9703058B2 (en) Package framework for photoelectric conversion module
TW201419774A (zh) 具有遠離轉阻放大器之光偵測器的接收機光學總成（ｒｏａｓ）及其相關元件、電路與方法
US11177219B1 (en) Photonic integrated circuit with integrated optical transceiver front-end circuitry for photonic devices and methods of fabricating the same
WO2023082702A1 (fr) Puce pour transmission de signaux à haute vitesse, et structure d'empilement de puces
KR100883128B1 (ko) 광 하이브리드 모듈
US20200225430A1 (en) Optical engine
CN107479148B (zh) 一种光模块封装结构及制作方法
CN214954233U (zh) 一种光模块
WO2020135561A1 (fr) Appareil d'interconnexion de puce et de connecteur de fond de panier, et dispositif de communication
CN102436042A (zh) 一种灵活耦合的高速光电器件
US11139412B2 (en) Electrical coupling assemblies and methods for optoelectronic modules
JP7074012B2 (ja) 光モジュール
US9035411B2 (en) Semiconductor device
JP7113325B2 (ja) 光モジュール構造体
WO2021009912A1 (fr) Fibre photoélectrique et dispositif de communication
WO2024137429A1 (fr) Communication de puces à l'aide d'un substrat de communication optique
WO2020201539A1 (fr) Moteur optique
CN116068704A (zh) 一种光模块

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22891511

Country of ref document: EP

Kind code of ref document: A1