WO2023082702A1

WO2023082702A1 - Chip for high-speed signal transmission, and chip stacking structure

Info

Publication number: WO2023082702A1
Application number: PCT/CN2022/107767
Authority: WO
Inventors: 胡立辉; 李志伟; 于飞; 史文俊
Original assignee: 华为技术有限公司
Priority date: 2021-11-09
Filing date: 2022-07-26
Publication date: 2023-05-19
Also published as: CN116110879A

Abstract

Provided in the present application is a chip for high-speed signal transmission. The chip comprises a signal pad, a first ground pad, an active area, a first transmission line, and a second transmission line. The length of the second transmission line is less than the sum of the distance from the signal pad to the first ground pad and the length of the first transmission line. Further provided in the present application is another chip for high-speed signal transmission. A first auxiliary ground pad of the chip is electrically connected to the active area by means of the second transmission line; and the first auxiliary ground pad is electrically connected to the first ground pad by means of a third transmission line. By using the two chips provided in the present application, the signal transmission rate between any two chips can be improved, thereby improving the transmission rate of a communication link of a communication system to which the any two chips belong. In addition, further provided in the present application are a chip stacking structure using the chips, a chip packaging structure, and an electronic device.

Description

Chip and chip stack structure for high-speed signal transmission

This application claims the priority of the Chinese patent application with the application number 202111320892.X and the application name "chip and chip stack structure for high-speed signal transmission" submitted to the China Patent Office on November 09, 2021, the entire content of which is passed References are incorporated in this application.

technical field

The present application relates to the field of chip technology, and in particular to a chip for high-speed signal transmission, a chip stacking structure, a chip packaging structure and electronic equipment.

Background technique

Nowadays, communication systems require higher and higher transmission rates between their internal chips. Taking the quad small form factor pluggable (Quad Small Form Factor Pluggable-Dual Density, QSFP-DD) module with double density as an example, the transmission rate of signals between any two chips needs to be further improved (for example, requires The transmission rate is increased to 200Gbps), so that the transmission rate of the communication link of the communication system to which any two chips belong is also increased. It should be known that bandwidth is an important factor affecting the transmission rate. Specifically, the larger the bandwidth, the higher the transmission rate; the smaller the bandwidth, the lower the transmission rate. For two chips, the greater the bandwidth between them, the greater the signal transmission rate between the two chips. Currently, two chips are usually connected by wire bonding (WB). As shown in FIG. 1 , the first chip 31 and the second chip 32 are connected by wires 5 . Two chips bonded by WB, because the bandwidth between them is too small, the signal transmission rate between them is small, and this signal transmission rate can no longer meet the transmission rate requirements of the current communication system for the communication link.

Contents of the invention

The present application provides a chip for high-speed signal transmission and a chip stacking structure, which are used to solve the problem of limited signal transmission rate between two chips in the prior art. In addition, the present application also provides a chip packaging structure and electronic equipment including the aforementioned chip or the aforementioned chip stacking structure.

In a first aspect, the present application provides a chip, which includes a signal pad, a first ground pad, an active area, a first transmission line, and a second transmission line. The signal pad is electrically connected to the active area through the first transmission line, and the first ground pad is electrically connected to the active area through the second transmission line. The length of the second transmission line is less than the distance between the signal pad and the first ground pad and the first The sum of the lengths of the transmission lines. The signal pad is closer to the first edge of the chip relative to the active area, the first ground pad is closer to the first edge of the chip than the active area, or the distance between the first ground pad and the first edge and the active area The distance from the region to the first edge is equal. In the above technical solution, reducing the equivalent inductance of the second transmission line by reducing the length of the second transmission line is conducive to improving the resonant frequency of the transmission link between any two chips, thereby improving the inductance of any two chips. transfer rate between.

It should be noted that the above equality should be based on the understanding of those skilled in the art, and should not be rigidly understood as absolute equality in the mathematical sense. The second transmission line connecting the first ground pad and the active region If it is perpendicular to the first transmission line, it can be considered to meet the equality defined here. However, the first ground pad and the active area can be located on the second transmission line, and it is not necessary to limit that their geometric centers must be located on the second transmission line. Transmission line.

With reference to the first aspect, in a first possible implementation manner, the second transmission line is a straight line or a broken line.

It should be noted that, in this application, the first transmission line is a straight line.

With reference to the first aspect or the first possible implementation of the first aspect, in the second possible implementation, the chip further includes a second ground pad and a third transmission line, and the second ground pad and the active region pass through The third transmission line is electrically connected, and the length of the third transmission line is less than the sum of the distance from the signal pad to the second ground pad and the length of the first transmission line. The signal pad is closer to the first edge of the chip relative to the active area, the second ground pad is closer to the first edge of the chip than the active area, or the distance between the second ground pad and the first edge and the active area The distance from the region to the first edge is equal. In the above technical solution, reducing the equivalent inductance of the third transmission line by reducing the length of the third transmission line is conducive to improving the resonant frequency of the transmission link between any two chips, thereby improving the inductance of any two chips. transfer rate between.

With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner, the third transmission line is a straight line or a broken line.

In combination with the first aspect or any one of the first to third possible implementations of the first aspect, in a fourth possible implementation, the chip further includes a first auxiliary ground pad, and the first The second transmission line includes a first section of transmission line and a second section of transmission line. The first auxiliary ground pad is electrically connected to the active area through a first transmission line, and the first auxiliary ground pad is electrically connected to the first ground pad through a second transmission line.

In the above technical solution, the equivalent capacitance of the transmission link is reduced by increasing the first auxiliary ground pad, which is conducive to improving the resonant frequency of the transmission link between any two chips, thereby improving the transfer rate between.

In combination with the first aspect or any one of the first to fourth possible implementations of the first aspect, in a fifth possible implementation, the chip is a photodiode PD chip, or, the The above chip is a transimpedance amplifier TIA chip.

In a second aspect, the present application further provides a chip stacking structure, the chip stacking structure includes a first chip and a second chip arranged in a stack. Both the above-mentioned first chip and the above-mentioned second chip are the chips described in the first aspect or any implementation manner of the first aspect. Wherein, the signal pads of the first chip are electrically connected to the signal pads of the second chip, and the first ground pads of the first chip are electrically connected to the first ground pads of the second chip. In the above technical solution, the first chip and the second chip are stacked, which is beneficial to shorten the interconnection path between the two chips, thereby increasing the rate of signal transmission between the first chip and the second chip.

With reference to the second aspect, in a first possible implementation manner, both the first chip and the second chip include a first auxiliary ground pad, and the first auxiliary ground pad of the first chip and the second chip The first auxiliary ground pad is electrically connected.

With reference to the second aspect or the first possible implementation manner of the second aspect, in the second possible implementation manner, both the first chip and the second chip include a second ground pad, and the first chip's The second ground pad is electrically connected to the second ground pad of the second chip.

With reference to the second aspect, the first possible implementation manner or the second possible implementation manner of the second aspect, in a third possible implementation manner, both the first chip and the second chip include a second auxiliary ground The second auxiliary ground pad of the first chip is electrically connected to the second auxiliary ground pad of the second chip.

With reference to the second aspect or any possible implementation manner of the first to third implementation manners of the second aspect, in a fourth possible implementation manner, the signal pad of the first chip and the first The signal pads of the two chips are electrically connected by soldering material. The first ground pad of the first chip is electrically connected to the first ground pad of the second chip through soldering material.

In a third aspect, the present application further provides a chip packaging structure, which includes a packaging substrate and the chip stack structure according to any one of the implementation manners of the second aspect, and the packaging substrate is electrically connected to the chip stack structure.

In a fourth aspect, the present application further provides an electronic device, the electronic device includes a printed circuit board and the chip packaging structure described in the third aspect, the printed circuit board is electrically connected to the chip packaging structure.

Description of drawings

Figure 1 is a schematic structural diagram of a WB connection between any two chips;

FIG. 2 is a schematic structural diagram of the electronic device 1;

FIG. 3 is a schematic diagram of the internal structure of the optical module;

FIG. 4 is a schematic structural view of the first chip 31;

FIG. 5 is a schematic structural view of the second chip 32;

FIG. 6 is a schematic structural diagram of a first chip 31 and a second chip 32 stacked;

7A-7B are simulation data diagrams of signal transmission performance between the first chip 31 and the second chip 32;

8A-8C are schematic structural views of the first chip 31;

FIG. 9 is an equivalent circuit diagram in which the first chip 31 and the second chip 32 are electrically connected by FC;

10A-10B are simulation data diagrams of signal transmission performance between the first chip 31 and the second chip 32 .

Detailed ways

The following will describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The embodiment of the present application provides an electronic device 1 . The electronic device 1 includes, but is not limited to, an optical communication device, where the optical communication device may be, for example, an optical module, an optical engine, and an optical device.

Referring to Fig. 2, the electronic device 1 includes a chip package structure 10, a printed circuit board (printed circuit board, PCB) 11 and an electrical connection structure 12, and the chip package structure 10 is electrically connected to the PCB 11 through the electrical connection structure 12, so that the chip package The structure 10 can realize signal transmission with other devices on the PCB 11 .

The electrical connection structure 12 may be a ball grid array (BGA), or a flexible printed circuit (FPC). In an optional embodiment, if the size of the chip package structure 10 is relatively large, in order to ensure the reliability of the electrical connection between the chip package structure 10 and the PCB 11, the electrical connection structure 12 can also use a connection terminal with a slot-type fixing structure. (socket), the connection terminal can also be called a connector or a socket.

The following description will be made by taking the electronic device 1 as an optical module as an example. Please refer to Figure 3. Figure 3 shows the main functional modules and connections between modules in a typical optical module. In the case that the electronic device 1 is an optical module, the electronic device 1 may also include a transmitting optical component (Transmitter Optical Sub-Assembly, TOSA), a clock signal recovery (Clock Data Recovery, CDR) or an optical digital signal processing (Optical Digital Signal Process, oDSP). In this case, the above-mentioned chip package structure 10 can be used as a Receiver Optical Sub-Assembly (ROSA).

The signal flow direction in the optical module is: the electrical signal transmitted from the PCB11 is shaped by the CDR or oDSP and transmitted to the TOSA. The TOSA is used to convert the electrical signal into an optical signal and transmit the optical signal into the optical fiber. ROSA receives the optical signal from the optical fiber, converts the optical signal into an electrical signal, and transmits the electrical signal to the CDR or oDSP, and the CDR or oDSP restores the electrical signal.

The chip package structure 10 will be described below.

Please refer to FIG. 2 , the chip package structure 10 includes a chip stack structure 20 , a package substrate 21 and a solder bump 22 . Wherein, the chip stack structure 20 is fixed on a package substrate 21 , and the package substrate 21 is used to carry the chip stack structure 20 . The chip stack structure 20 can be electrically connected to the packaging substrate 21 through bumps 22 .

The embodiment of the present application also provides a chip stacking structure 20 .

Please refer to FIG. 2 , the chip stack structure 20 includes a first chip 31 , a second chip 32 and soldering materials. Wherein, the first chip 31 and the second chip 32 are stacked and arranged, and the first chip 31 and the second chip 32 are electrically connected by soldering material. Exemplarily, the soldering material may be a copper pillar (Copper Pillar) or a flip-chip flip-chip soldering bump (Controlled Collapsed Chip Connection Bump, C4Bump) or a gold bump (Gold Bump).

Specifically, the first chip 31 and the second chip 32 are connected in a flip chip (Flip Chip, FC) manner. By adopting the FC method, the interconnection path between the first chip 31 and the second chip 32 can be shortened, thereby increasing the rate of signal transmission between the first chip 31 and the second chip 32 .

Referring to FIG. 4 , the first chip 31 includes an active area 310 , a first ground pad 311 , a second ground pad 312 , a signal pad 313 , a first transmission line 314 , a second transmission line 315 and a third transmission line 316 . Wherein, the active area 310 is the part where the first chip 31 performs functions, the signal pad 313 is used for signal transmission, and the first ground pad 311 and the second ground pad 312 are used for ground protection. The signal pad 313 is electrically connected to the active area 310 through the first transmission line 314; the first ground pad 311 is electrically connected to the active area 310 through the second transmission line 315; the second ground pad 312 is electrically connected to the active area 310 through the third The transmission line 316 is electrically connected.

Correspondingly, referring to FIG. 5, the second chip 32 includes an active area 320, a first ground pad 321, a second ground pad 322, a signal pad 323, a first transmission line 324, a second transmission line 325 and a third transmission line 326 . Wherein, the active area 320 is the part where the second chip 32 performs functions, the signal pad 323 is used for signal transmission, and the first ground pad 321 and the second ground pad 322 are used for ground protection. The signal pad 323 is electrically connected to the active area 320 through the first transmission line 324; the first ground pad 321 is electrically connected to the active area 320 through the second transmission line 325; the second ground pad 322 is electrically connected to the active area 320 through the third The transmission line 326 is electrically connected.

In an optional implementation manner, as shown in FIG. 6 , the first chip 31 and the second chip 32 are connected in a FC manner. The first ground pad 311 , the second ground pad 312 and the signal pad 313 of the first chip 31 are regularly arranged, that is, the above three pads are located on the same straight line. Correspondingly, the first ground pad 321 , the second ground pad 322 and the signal pad 323 of the second chip 32 are regularly arranged, that is, the above three pads are located on the same straight line. The first ground pad 311 of the first chip 31 is electrically connected to the first ground pad 321 of the second chip 32; the second ground pad 312 of the first chip 31 is electrically connected to the second ground pad 322 of the second chip 32 Connection; the signal pad 313 of the first chip 31 is electrically connected to the signal pad 323 of the second chip 32 .

The above-mentioned first chip 31 may be an optical chip, such as a photodiode (Photo Diode, PD) or APD (Avalanche Photo Diode, avalanche photodiode). The above-mentioned second chip 32 may be an electrical chip, such as a TIA (Trans-impedance Amplifier, transimpedance amplifier).

In the case that the first chip 31 is a PD and the second chip 32 is a TIA, the chip packaging structure 10 may be a ROSA.

The signal flow direction in the chip packaging structure 10 is: the optical signal transmitted from the optical fiber is transmitted to the PD, the PD converts the optical signal into an electrical signal, and transmits the electrical signal to the TIA, and the TIA amplifies the electrical signal, and The amplified electrical signal is transmitted to other electrical processing chips on the electronic device 1 , such as CDR or oDSP, and the amplified electrical signal is further processed by the CDR or oDSP.

Taking the first chip 31 as PD and the second chip 32 as TIA as an example, when the first chip 31 and the second chip 32 are interconnected by FC, the corresponding inter-chip signal transmission performance is simulated, and the result is shown in FIG. 7A and shown in Figure 7B. Wherein, FIG. 7A is used to analyze the resonance and 3dB bandwidth of the transmission link between the first chip 31 and the second chip 32, and FIG. 7B is used to analyze the group of the transmission link between the first chip 31 and the second chip 32. Latency performance.

In the field of high-speed interconnection, bandwidth is an important factor affecting the transmission rate. Specifically, the larger the bandwidth, the higher the transmission rate; the smaller the bandwidth, the lower the transmission rate. Correspondingly, the greater the bandwidth between the two chips, the greater the signal transmission rate between the two chips. Resonance is an important factor that limits the bandwidth between any two chips, and at the same time, resonance will cause the group delay performance of the signal to deteriorate. Among them, resonance refers to the resonance that occurs in the transmission link between two chips. The 3dB bandwidth refers to the corresponding frequency bandwidth when the amplitude of the signal is equal to twice the root of half of the maximum value. The wider the frequency bandwidth corresponding to the 3dB bandwidth, the less attenuation of the signal, which is more conducive to the high-speed transmission of the signal. The group delay performance is used to characterize the phase of each frequency component of the signal. The smaller the group delay, the smaller the phase difference of each frequency component transmission, which is more conducive to high-speed signal transmission.

As shown in FIG. 7A , the abscissa represents the frequency, and the unit is GHz; the ordinate represents the insertion loss of the signal attenuation, and the unit is dB. It can be seen from FIG. 7A that the signal has a large resonance at 110 GHz, and the 3dB bandwidth is 78 GHz.

As shown in FIG. 7B , the abscissa represents the frequency, and the unit is GHz; the ordinate represents the group delay Group Delay of the signal on the transmission link, and the unit is ps. It can be seen from FIG. 7B that, after 110 GHz, the group delay curve becomes significantly curved, that is, the flatness of the group delay curve decreases. The reduced flatness of the group delay curve means that the group delay performance of the signal deteriorates sharply, which is not conducive to achieving a higher transmission rate of the signal between the first chip 31 and the second chip 32 .

It can be seen that in the above implementation manner, there are still problems of resonance and poor group delay performance, which further lead to a limited transmission rate between the two chips. The above-mentioned embodiment is also referred to as a conventional FC method. In order to solve the above problems and further increase the signal transmission rate between the two chips, the present application further provides a chip, which may be the above-mentioned first chip 31 or the above-mentioned second chip 32 . The chip is described below through a specific embodiment.

Taking the chip as the first chip 31 as an example, the first chip 31 includes an active area 310, a first ground pad 311, a second ground pad 312, a signal pad 313, a first transmission line 314, a second transmission line 315 and The third transmission line 316 . Wherein, the signal pad 313 is electrically connected to the active area 310 through the first transmission line 314; the first ground pad 311 is electrically connected to the active area 310 through the second transmission line 315; the second ground pad 312 is electrically connected to the active area 310 through The third transmission line 316 is electrically connected.

It should be noted that, in this embodiment, the length of the second transmission line 315 is less than the sum of the distance from the signal pad 313 to the first ground pad 311 and the length of the first transmission line 314 . The signal pad 313 is closer to the first edge 100 of the first chip 31 relative to the active region 310, the first ground pad 311 is closer to the first edge 100 of the first chip 31 relative to the active region 310, or, the first The distance between the ground pad 311 and the first edge 100 and the distance between the active region 310 and the first edge 100 are equal.

Optionally, the first transmission line 314 is a straight line.

Optionally, the second transmission line 315 is a straight line or a broken line.

Optionally, the third transmission line 316 is a straight line or a broken line. The equality here should be based on the understanding of those skilled in the art, and should not be rigidly understood as absolute equality in the mathematical sense. The second transmission line connecting the first ground pad and the active region is perpendicular to the first The transmission lines can be considered to be equal as defined here. However, it is only necessary that the first ground pad and the active area be located on the second transmission line, and it is not necessary to define that their geometric centers must be located on the second transmission line.

Specifically, in one implementation manner, as shown in FIG. 8A , the second transmission line 315 is perpendicular to the first transmission line 314 , and the third transmission line 316 is perpendicular to the first transmission line 314 . In another embodiment, as shown in FIG. 8B , the included angle between the second transmission line 315 and the first transmission line 314 is an acute angle, and the included angle between the third transmission line 316 and the first transmission line 314 is an acute angle. Compared with FIG. 4 , the positions of the first ground pad 311 and the second ground pad 312 may be unchanged or changed. In another embodiment, as shown in FIG. 8C, the length of the part of the second transmission line 315 parallel to the first transmission line 314 is shorter than the length of the first transmission line 314, and the length of the part of the third transmission line 316 parallel to the first transmission line 314 The length is less than the length of the first transmission line 314 . Compared with FIG. 4 , the first ground pad 311 is closer to the active area 310 , and the second ground pad 312 is closer to the active area 310 .

Correspondingly, the second chip 32 includes an active area 320 , a first ground pad 321 , a second ground pad 322 , a signal pad 323 , a first transmission line 324 , a second transmission line 325 and a third transmission line 326 . Wherein, the signal pad 323 is electrically connected to the active area 320 through the first transmission line 324; the first ground pad 321 is electrically connected to the active area 320 through the second transmission line 325; the second ground pad 322 is electrically connected to the active area 320 through The third transmission line 326 is electrically connected.

The pads and transmission lines on the second chip 32 adopt the same arrangement as the pads and transmission lines on the first chip 31 , and the first chip 31 and the second chip 32 are electrically connected by FC. Specifically, the first ground pad 311 of the first chip 31 is electrically connected to the first ground pad 321 of the second chip 32; the second ground pad 312 of the first chip 31 is connected to the second ground pad of the second chip 32 The pads 322 are electrically connected; the signal pads 313 of the first chip 31 are electrically connected to the signal pads 323 of the second chip 32 .

The beneficial effects of the above embodiment will be described below in conjunction with the equivalent circuit diagram when the first chip 31 and the second chip 32 are electrically connected by FC.

Please refer to FIG. 9, C1 is the equivalent capacitance of the signal pad 313 of the first chip 31; C2 is the common equivalent capacitance of the first ground pad 311 of the first chip 31 and the second ground pad 312 of the first chip 31. capacitance. C3 is the equivalent capacitance of the signal pad 323 of the second chip 32 ; C4 is the common equivalent capacitance of the first ground pad 321 of the second chip 32 and the second ground pad 322 of the second chip 32 . The above pads are all connected to ground.

B1 is a solder material between the signal pad 312 of the first chip 31 and the signal pad 323 of the second chip 32 . B2 is between the first ground pad 311 of the first chip 31 and the first ground pad 321 of the second chip 32, and the second ground pad 312 of the first chip 31 and the first ground pad of the second chip 32. Solder material between discs 322.

L1 is the equivalent inductance of the first transmission line 314 of the first chip 31 , and L2 is the overall equivalent inductance of the second transmission line 315 of the first chip 31 and the third transmission line 316 of the first chip 31 . L3 is the equivalent inductance of the first transmission line 324 of the second chip 32 , and L4 is the overall equivalent inductance of the second transmission line 325 of the second chip 32 and the third transmission line 326 of the second chip 32 .

By reducing the length of the second transmission line 315 and the length of the third transmission line 316 of the first chip 31, and reducing the lengths of the second transmission line 325 and the third transmission line 326 of the second chip 32, thereby reducing the length of the first chip 31 The equivalent inductance L2 of the second transmission line 315 and the third transmission line 316 and the equivalent inductance L4 of the second transmission line 325 and the third transmission line 326 of the second chip 32 are reduced. And according to the principle of resonance:

F∝1/[2*pi*sqrt(L*C)],

That is, the resonant frequency F of the transmission link between the first chip 31 and the second chip 32 is proportional to the reciprocal of the square root of (L*C), that is, the resonant frequency F is inversely proportional to the square root of (L*C). Wherein, C represents the equivalent total capacitance of the transmission link, and L represents the equivalent total inductance of the transmission link, that is, L includes L1, L2, L3, and L4. Therefore, by reducing the length of the transmission line, the equivalent inductance of the transmission link between the first chip 31 and the second chip 32 is reduced, which is conducive to improving the resonant frequency of the transmission link, thereby improving bandwidth and group delay performance , so as to increase the transmission rate between the first chip 31 and the second chip 32 .

The above-mentioned first chip 31 may be an optical chip, such as PD (Photo Diode, photodiode) or APD (Avalanche Photo Diode, avalanche photodiode). The above-mentioned second chip 32 may be an electrical chip, such as a TIA (Trans-impedance Amplifier, transimpedance amplifier).

Taking the first chip 31 as PD and the second chip 32 as TIA as an example, when the first chip 31 and the second chip 32 are interconnected by FC, the corresponding inter-chip signal transmission performance is simulated, and the result is shown in the figure 10A and 10B. Wherein, Fig. 10A is used for analyzing the resonance and 3dB bandwidth of the transmission link between the first chip 31 and the second chip 32, and Fig. 10B is used for analyzing the group of the transmission link between the first chip 31 and the second chip 32 Latency performance.

As shown in FIG. 10A , the abscissa represents the frequency, and the unit is GHz; the ordinate represents the insertion loss of the signal attenuation, and the unit is dB. There are three curves in the figure, which respectively correspond to the interconnection of the first chip 31 and the second chip 32 in the above-mentioned embodiment, the WB interconnection and the traditional FC interconnection. It can be seen from FIG. 10A that, compared with the traditional FC solution, the resonant frequency of the above embodiment is extended from 110 GHz to 160 GHz, and the 3dB bandwidth is increased from 74 GHz to 105 GHz.

As shown in FIG. 10B , the abscissa represents the frequency, and the unit is GHz; the ordinate represents the group delay Group Delay of the signal on the transmission link, and the unit is ps. It can be seen from FIG. 10B that, compared with the WB and traditional FC solutions, the group delay curve of the above embodiment is flatter, that is, each frequency component of the signal sent by the first chip 31, after passing through the transmission link, are transmitted to the second chip 32 almost simultaneously, which shows that the above embodiment can greatly improve the group delay performance of the transmission link.

Combining Figure 10A and Figure 10B, it can be concluded that the resonant frequency of the transmission link between the first chip 31 and the second chip 32 is increased, the 3dB bandwidth is increased, and the group delay performance of the transmission link is also improved, which is beneficial to The transmission rate of signals between the first chip 31 and the second chip 32 is increased.

In the description of this specification, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in an appropriate manner.

The above is only the specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the application, and should cover Within the protection scope of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

A chip, characterized by comprising: a signal pad, a first ground pad, an active area, a first transmission line, and a second transmission line;

The signal pad is electrically connected to the active region through the first transmission line,

The first ground pad is electrically connected to the active area through the second transmission line, and the length of the second transmission line is shorter than the distance from the signal pad to the first ground pad and the first the sum of the lengths of the transmission lines;

The signal pad is closer to the first edge of the chip relative to the active area, the first ground pad is closer to the first edge of the chip relative to the active area, or, the The distance between the first ground pad and the first edge and the distance between the active region and the first edge are equal.
The chip according to claim 1, wherein the second transmission line is a straight line or a broken line.
The chip according to claim 1 or 2, characterized in that,

The chip also includes a second ground pad and a third transmission line,

The second ground pad is electrically connected to the active area through the third transmission line, and the length of the third transmission line is shorter than the distance from the signal pad to the second ground pad and the first the sum of the lengths of the transmission lines;

The signal pad is closer to the first edge of the chip relative to the active area, the second ground pad is closer to the first edge of the chip relative to the active area, or, the The distance between the second ground pad and the first edge and the distance between the active area and the first edge are equal.
The chip according to claim 3, wherein the third transmission line is a straight line or a broken line.
The chip according to any one of claims 1 to 4, characterized in that,

The chip also includes a first auxiliary ground pad,

The second transmission line includes a first section of transmission line and a second section of transmission line;

The first auxiliary ground pad is electrically connected to the active region through the first transmission line;

The first auxiliary ground pad is electrically connected to the first ground pad through the second transmission line.
A chip stack structure, characterized in that it includes a first chip and a second chip stacked;

Both the first chip and the second chip are the chips described in any one of claims 1 to 5;

Wherein, the signal pads of the first chip are electrically connected to the signal pads of the second chip;

The first ground pad of the first chip is electrically connected to the first ground pad of the second chip.
The chip stack structure according to claim 6, characterized in that,

Both the first chip and the second chip include a first auxiliary ground pad,

The first auxiliary ground pad of the first chip is electrically connected to the first auxiliary ground pad of the second chip.
The chip stack structure according to claim 6 or 7, characterized in that,

Both the first chip and the second chip include a second ground pad,

The second ground pad of the first chip is electrically connected to the second ground pad of the second chip.
The chip stack structure according to any one of claims 6 to 8, characterized in that,

Both the first chip and the second chip include a second auxiliary ground pad,

The second auxiliary ground pad of the first chip is electrically connected to the second auxiliary ground pad of the second chip.
The chip stack structure according to any one of claims 6 to 9, characterized in that,

The signal pads of the first chip and the signal pads of the second chip are electrically connected by soldering material;

The first ground pad of the first chip is electrically connected to the first ground pad of the second chip through soldering material.
A chip package structure, characterized in that it comprises a package substrate and the chip stack structure according to any one of claims 6 to 10, the package substrate is electrically connected to the chip stack structure.
An electronic device, characterized by comprising a printed circuit board and the chip packaging structure according to claim 11, the printed circuit board being electrically connected to the chip packaging structure.