WO2023082197A1

WO2023082197A1 - Semiconductor chip package

Info

Publication number: WO2023082197A1
Application number: PCT/CN2021/130432
Authority: WO
Inventors: 杨方旭; 石林; 孙世虎
Original assignee: 华为技术有限公司
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2023-05-19
Also published as: CN117678327A

Abstract

Embodiments of the present disclosure relate to a semiconductor chip package. In the semiconductor chip package, a first pair of pads transmit differential signals and are electrically connected to a first pair of plating holes. A second pair of pads also transmit differential signals and are electrically connected to a second pair of plating holes. The polarities of signals transmitted by adjacent pads among the two pairs of pads are the same, and the polarities of signals transmitted by adjacent plating holes among the two pairs of plating holes are opposite, and vice versa. In this way, differential crosstalk in a semiconductor chip package can be at least partially counteracted.

Description

Semiconductor Chip Packaging

technical field

Embodiments of the present disclosure relate to the field of semiconductors, and more particularly, to semiconductor chip packaging.

Background technique

In the fields of high-speed serializer-deserializer (Serializer-Deserializer, SerDes), converter, clock, etc., the crosstalk between package differential signal solder balls has become a key factor limiting the further improvement of system performance. In existing solutions, package differential crosstalk is reduced by adding more ground ball isolation. This increases the size of the semiconductor chip package, resulting in a decrease in chip competitiveness.

Contents of the invention

Embodiments of the present disclosure aim to provide a solution for reducing differential crosstalk of an interconnection structure in a semiconductor chip package without significantly increasing the size of the semiconductor chip package.

In some embodiments, a semiconductor chip package is provided. The semiconductor chip package includes a first differential interconnect assembly and a second differential interconnect assembly adjacent to the first differential interconnect assembly. Each differential interconnection assembly includes a pair of pads for transmitting differential signals and a pair of plated-through holes electrically connected to the pair of pads, respectively. If the polarities of adjacent pads between the first differential interconnection component and the second differential interconnection component are opposite in the planar projection of the semiconductor chip package, the first differential interconnection component and the second differential interconnection component are reversed in the planar projection of the semiconductor chip package. Adjacent plated-through holes between the second differential interconnection components have the same polarity. Conversely, if the polarities of adjacent pads between the first differential interconnection component and the second differential interconnection component are the same in the planar projection of the semiconductor chip package, the first differential interconnection in the planar projection of the semiconductor chip package The polarity of adjacent plated-through holes between the component and the second differential interconnect component is reversed.

The crosstalk between adjacent plated holes is just opposite in polarity to the crosstalk between adjacent pads, and therefore, can at least partially cancel the crosstalk between adjacent pads, thereby reducing the size of the semiconductor chip package significantly. Basically reduce the differential crosstalk of the bonding pads in the semiconductor chip package. Further, the embodiments of the present disclosure can keep the pin map (also referred to as pad arrangement) unchanged, thus having good compatibility. In addition, the embodiments of the present disclosure may not increase or add as little isolation ground pads between differential pairs as possible.

In some embodiments, the first differential interconnection component includes: a first pad and a second pad, disposed on the substrate, for transmitting the first differential signal. The first differential interconnection assembly further includes a first plated-through hole and a second plated-through hole disposed in the substrate and electrically connected to the first pad and the second pad respectively. The second differential interconnection component is adjacent to the first differential interconnection component, and the second differential interconnection component includes: a third pad and a fourth pad, arranged on the substrate, and used for transmitting the second differential signal. The second differential interconnection assembly includes a third plated-through hole and a fourth plated-through hole, disposed in the substrate, and electrically connected to the third pad and the fourth pad, respectively. In the planar projection of the semiconductor chip package, the second pad in the first differential interconnection assembly is adjacent to the third pad in the second differential interconnection assembly, and the first plated-through hole in the first differential interconnection assembly Adjacent to the third plated through hole in the second differential interconnect assembly. The polarity of the signal transmitted by the second pad and the third pad is the same, and the polarity of the signal transmitted by the first plated hole and the third plated hole is opposite; or, the signal transmitted by the second pad and the third pad The polarities of the signals are reversed, and the signals carried by the first plated-through hole and the third plated-through hole are of the same polarity.

In some embodiments, in the planar projection of the semiconductor chip package, the connection line between the first pad and the second pad and the connection line between the first plated hole and the second plated hole are perpendicular to each other, and The connection line between the third pad and the fourth pad and the connection line between the third plated hole and the fourth plated hole are perpendicular to each other. By placing the pad perpendicular to the plated hole, the position of the plated hole and the pad can be staggered from each other. In this way, it is possible to achieve differences in the crosstalk polarity of the pads and plated-through holes, thereby creating a mutually canceling effect.

In some embodiments, the first pad in the first differential interconnect assembly is adjacent to the fourth pad in the second differential interconnect assembly.

In some embodiments, the first plated-through hole is located on one side of the first pad and the second pad, and the second plated-through hole is located on the other side of the first pad and the second pad.

In some embodiments, the first pad and the fourth pad are arranged in a first row, and the second pad and the third pad are arranged in a second row adjacent to the first row.

In some embodiments, the second pads and the third pads are arranged in adjacent rows and adjacent columns.

In some embodiments, the first to fourth pads are arranged in a row, and the first to fourth plated holes are located at one side of the row.

In some embodiments, the connection line between the first pad and the second pad and the connection line between the third pad and the fourth pad are perpendicular to each other.

In some embodiments, the line between the first pad and the second pad is perpendicular to the line between the first plated hole and the second plated hole, and the line between the third pad and the fourth pad The connection line between the third plated hole and the fourth plated hole is parallel to each other, and the connection line between the first pad and the second pad and the connection line between the third pad and the fourth pad The connecting lines are perpendicular to each other.

In some embodiments, the first pads are arranged in a first row, the second pads are arranged in a second row, and the third pads and fourth pads are arranged in a third row.

In some embodiments, the semiconductor chip package further includes one or more plated-through holes for electrical connection to ground, disposed in the substrate, between the first pad and the second pad in a planar projection of the semiconductor chip package and/or one or more plated-through holes for electrical connection to ground, disposed in the substrate between the third pad and the fourth pad in the planar projection of the semiconductor chip package. Quantitative adjustment of impedance control and crosstalk elimination can be realized by setting one or more ground holes in the semiconductor chip package.

In some embodiments, the first pad and the second pad are respectively connected to the first plated hole and the second plated hole through a double helix blind buried hole; and/or the third pad and the fourth pad are connected through The double helix blind buried holes are respectively connected with the first plated hole and the second plated hole. The double-helix blind buried holes include a first plurality of blind buried holes electrically connected to each other and a second plurality of blind buried holes electrically connected to each other, the first plurality of blind buried holes are stacked along the first direction, and the second plurality of blind buried holes The buried vias are stacked along a second direction opposite to the first direction. In this way, a flexible outlet can be achieved and wire winding can be prevented.

In some embodiments, the substrate includes a laminated substrate or a printed circuit board (Printed Circuit Board, PCB).

In some embodiments, the semiconductor chip package further includes a third differential interconnection component and a fourth differential interconnection component. The third differential interconnection assembly includes: a fifth pad and a sixth pad disposed on the substrate for transmitting a third differential signal; and a fifth plated hole and a sixth plated hole disposed in the substrate, and are electrically connected to the fifth pad and the sixth pad respectively. The fourth differential interconnection assembly includes: a seventh pad and an eighth pad disposed on the substrate for transmitting a fourth differential signal; and a seventh plated hole and an eighth plated hole disposed in the substrate, and are electrically connected to the seventh pad and the eighth pad respectively. The sixth pad in the third differential interconnection component is adjacent to the seventh pad in the fourth differential interconnection component, and the fifth pad in the third differential interconnection component is adjacent to the seventh pad in the fourth differential interconnection component. The eight pads are adjacent, and the fifth plated through hole in the third differential interconnection assembly is adjacent to the sixth plated through hole in the fourth differential interconnection assembly. The polarity of the signal transmitted by the sixth pad and the seventh pad is the same, and the polarity of the signal transmitted by the fifth plated hole and the sixth plated hole is opposite; or the signal transmitted by the sixth pad and the seventh pad The polarity of the plated-through hole is opposite, and the polarity of the signal transmitted by the fifth plated-through hole and the sixth plated-through hole is the same. In the planar projection of the semiconductor chip package, the fifth pad and the eighth pad are arranged in the third row, and the sixth pad and the seventh pad are arranged in the fourth row adjacent to the third row. The pad and the second pad are arranged in the first column, the fifth pad and the sixth pad are arranged in the second column adjacent to the first column, and the third pad and the fourth pad are arranged in the same column as the second column. In the adjacent third column, the seventh pad and the eighth pad are arranged in the fourth column adjacent to the third column. In this manner, crosstalk between each pair of the four differential interconnect assemblies can be reduced.

In some embodiments, the first differential interconnection component, the second differential interconnection component, the third differential interconnection component and the fourth differential interconnection component form a basic unit and are periodically arranged on the substrate. In this arrangement, the crosstalk between each pair of differential interconnection components can be reduced.

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or principal characteristics of the disclosure, nor is it intended to limit the scope of the disclosure.

Description of drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing the exemplary embodiments of the present disclosure in more detail with reference to the accompanying drawings, wherein, in the exemplary embodiments of the present disclosure, the same reference numerals are generally represent the same part.

FIG. 1 shows a planar projection of a semiconductor chip package according to a known solution.

FIG. 2 shows a planar projection of a semiconductor chip package according to some embodiments of the present disclosure.

FIG. 3 illustrates a partial cross-sectional view of a semiconductor chip package according to some embodiments of the present disclosure.

FIG. 4 shows the principle of crosstalk cancellation for the semiconductor chip package shown in FIG. 2 .

FIG. 5 shows the principle of crosstalk cancellation for the semiconductor chip package shown in FIG. 2 .

FIG. 6 shows a planar projection of a semiconductor chip package according to some embodiments of the present disclosure.

FIG. 7 shows a planar projection of a semiconductor chip package according to some embodiments of the present disclosure.

FIG. 8 shows a planar projection of a semiconductor chip package according to some embodiments of the present disclosure.

FIG. 9 illustrates a partial cross-sectional view of a semiconductor chip package according to some embodiments of the present disclosure.

FIG. 10 shows a planar projection of a semiconductor chip package according to some embodiments of the present disclosure.

Figure 11 illustrates the effect of crosstalk cancellation according to some embodiments of the present disclosure.

Figure 12 illustrates the effect of crosstalk cancellation according to some embodiments of the present disclosure.

Figure 13 illustrates the effect of crosstalk cancellation according to some embodiments of the present disclosure.

Figure 14 illustrates the effect of crosstalk cancellation according to some embodiments of the present disclosure.

Figure 15 illustrates the effect of crosstalk cancellation according to some embodiments of the present disclosure.

Fig. 16 shows the outlet scheme according to the existing scheme.

FIG. 17 shows a schematic diagram of an outlet scheme according to some embodiments of the present disclosure.

FIG. 18 shows a schematic diagram of an outlet scheme according to some embodiments of the present disclosure.

FIG. 19 shows a schematic diagram of an outlet scheme according to some embodiments of the present disclosure.

Figure 20 shows a schematic diagram of a ground hole layout according to some embodiments of the present disclosure.

Figure 21 shows a schematic diagram of a ground hole layout according to some embodiments of the present disclosure.

Figure 22 shows a schematic diagram of a ground hole layout according to some embodiments of the present disclosure.

In accordance with common practice, the various features shown in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. Additionally, some figures may not depict all components of a given system, method, or device. Finally, like reference numerals may be used to refer to like features throughout the specification and drawings.

Detailed ways

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein; A more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for exemplary purposes only, and are not intended to limit the protection scope of the present disclosure.

In the description of the embodiments of the present disclosure, the term "comprising" and its similar expressions should be interpreted as an open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be read as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same object. The term "and/or" means at least one of the two items associated with it. For example "A and/or B" means A, B, or A and B. Other definitions, both express and implied, may also be included below.

Any reference to direction or orientation is for convenience of description only and does not limit the scope of the present disclosure in any way. For example, "lower", "upper", "horizontal", "vertical", "above", "below", "upward", "downward", "top" and "bottom" and their derivatives (such as "horizontal "ground", "upward", "downward", etc.) and related terms are used in the discussion to refer to orientations described below or shown in the accompanying drawings. These relative terms are for convenience of description only and do not require the device to be constructed or operated in a particular orientation.

It should be understood that for the technical solutions provided by the embodiments of the present application, in the introduction of the following specific embodiments, some repetitions may not be repeated, but it should be considered that these specific embodiments have been referred to each other and can be combined with each other.

FIG. 1 shows a planar projection of a semiconductor chip package according to an existing solution, which shows the arrangement of solder balls and plated through holes (Plated Through Holes, PTHs). In one solution, in planar projection, the spacing between two PTHs is smaller than the spacing between two differential solder balls, ie "tight coupling". For example, in the planar projection shown in FIG. 1, the solder ball 101 and the PTH 103 partially overlap, so the solder ball 101 and the PTH 103 are tightly coupled. Similarly, in the planar projection shown in FIG. 1 , solder ball 102 partially overlaps with PTH 104 , solder ball 109 partially overlaps with PTH 111 , and solder ball 110 partially overlaps with PTH 112 . For example, the solder ball 101 is electrically connected to the PTH 103, and is used to transmit a positive polarity signal in the differential signal, and the solder ball 102 is electrically connected to the PTH 104, and is used to transmit a negative polarity signal in the differential signal. Similarly, the solder ball 109 is electrically connected to the PTH 111 for transmitting a positive polarity signal in the differential signal, and the solder ball 110 is electrically connected to the PTH 112 for transmitting a negative polarity signal in the differential signal. For convenience, below, the solder ball 101 and the solder ball 102 are referred to as a first differential pair, and the solder ball 109 and the solder ball 110 are referred to as a second differential pair.

In another approach, the solder balls are aligned with the PTH in planar projection. The solder ball "aligned" with the PTH in planar projection means that the centers of the solder ball and the PTH overlap each other in the planar projection. For example, in the planar projection shown in FIG. 1, solder ball 105 is aligned with PTH 107, solder ball 106 is aligned with PTH 108, solder ball 113 is aligned with PTH 115, and solder ball 114 is aligned with PTH 116. For example, the solder ball 105 is electrically connected to the PTH 107, and is used to transmit a positive polarity signal in the differential signal, and the solder ball 106 is electrically connected to the PTH 108, and is used to transmit a negative polarity signal in the differential signal. Similarly, the solder ball 113 is electrically connected to the PTH 115 for transmitting a positive polarity signal in the differential signal, and the solder ball 114 is electrically connected to the PTH 116 for transmitting a negative polarity signal in the differential signal. For convenience, the solder ball 105 and the solder ball 106 are referred to as the third differential pair, and the solder ball 113 and the solder ball 114 are referred to as the fourth differential pair.

It should be understood that, for the sake of convenience, FIG. 1 shows two different solutions, and usually only one solution may be implemented in a specific implementation process. In the following, FIG. 1 only shows the "alignment" scheme as an example for explanation. It should be understood that the following description is also applicable to the "tight coupling" scheme.

As shown in FIG. 1, there is crosstalk between the first differential pair and the third differential pair. For example, in-phase crosstalk exists between adjacent solder balls, that is, in-phase crosstalk exists between solder ball 101 and solder ball 105 , and in-phase crosstalk exists between solder ball 102 and solder ball 106 . Similarly, in-phase crosstalk also exists between adjacent PTHs, that is, in-phase crosstalk exists between PTH 103 and PTH 107, and in-phase crosstalk exists between PTH 104 and PTH 108. These in-phase crosstalks add to each other, enhancing the crosstalk between different differential pairs. In addition, there is also crosstalk between the first differential pair and the second differential pair. For example, reverse phase crosstalk exists between adjacent solder balls (ie, solder ball 102 and solder ball 109), and reverse phase crosstalk exists between adjacent PTHs (ie, PTH 104 and PTH 111). These anti-phase crosstalks add to each other, enhancing the crosstalk between different differential pairs.

Crosstalk between differential pairs can be reduced by providing ground solder balls. FIG. 1 shows a plurality of ground solder balls 120 located on ground pads of a package substrate. As shown in FIG. 1 , a column of ground solder balls is arranged between the first differential pair and the third differential pair to isolate crosstalk between differential signals. In order to reduce the crosstalk between the differential signals of the first differential pair and the third differential pair, one or more columns of ground solder balls can be added between the first differential pair and the third differential pair, which will increase the size of the semiconductor chip package. Similarly, in order to reduce the crosstalk between the differential signals of the first differential pair and the second differential pair, one or more rows of ground solder balls can be added between the first differential pair and the second differential pair, which will also increase the package size.

At least one object of embodiments of the present disclosure is to provide a technical solution for reducing differential signal crosstalk without significantly increasing the size of a semiconductor chip package. FIG. 2 shows a planar projection of a semiconductor chip package according to some embodiments of the present disclosure. In the example shown in FIG. 2, the solder ball 201 is electrically connected to the PTH 203, and is used to transmit a positive polarity signal in the differential signal, and the solder ball 202 is electrically connected to the PTH 204, and is used to transmit a negative polarity signal in the differential signal. Although not shown in FIG. 2 , solder balls 201 can be placed on pads on the package substrate, and such pads are also called ball landing pads (Ball Landing Pad). These structures will be described in detail below with reference to FIG. 3 . Similarly, the solder ball 205 is electrically connected to the PTH 207, and is used to transmit the positive polarity signal in the differential signal, and the solder ball 206 is electrically connected to the PTH 208, and is used to transmit the negative polarity signal in the differential signal; the solder ball 209 is electrically connected to the PTH 211 connection, used to transmit positive polarity signals, solder ball 210 and PTH 212 are electrically connected, used to transmit negative polarity signals in differential signals; solder balls 213 and PTH 215 are electrically connected, used to transmit positive polarity signals in differential signals, solder The ball 214 is electrically connected to the PTH 216 for transmitting the negative polarity signal in the differential signal. Additionally, FIG. 2 shows a plurality of ground solder balls 220 . It should be understood that in the embodiments of the present disclosure, positive polarity and negative polarity are provided as examples only, and positive polarity and negative polarity can generally be interchanged with each other.

In the embodiment of FIG. 2, the first differential interconnection assembly includes solder balls 201, solder balls 202, PTH 203, and PTH 204, and the second differential interconnection assembly includes solder balls 209, solder balls 210, PTH 211, and PTH 212, The third differential interconnect assembly includes solder ball 205, solder ball 206, PTH 207, and PTH 208, and the fourth differential interconnect assembly includes solder ball 213, solder ball 214, PTH 215, and PTH 216. In addition, for convenience of description, the solder ball 201 and the solder ball 202 are referred to as the first differential pair, the solder ball 209 and the solder ball 210 are referred to as the second differential pair, and the solder ball 205 and the solder ball 206 are referred to as the third differential pair , the solder ball 213 and the solder ball 214 are referred to as a fourth differential pair.

In the first differential interconnection component, the connection line between the solder ball 201 and the solder ball 202 may be perpendicular to the connection line between the PTH 203 and the PTH 204, and other differential interconnection components may also have the same positional relationship. As shown in FIG. 2 ,

solder balls

201 and 205 are located in the first row,

solder balls

202 and 206 are located in the second row, solder balls 209 are located in the third row, and solder balls 210 are located in the fourth row. Therefore, the third differential pair is arranged in parallel with the first differential pair. In addition, the

solder balls

201 and 202 are located in the first column, and the

solder balls

209 and 210 are located in the second column. Therefore, the second differential pair is arranged diagonally to the first differential pair.

In some embodiments, the structures shown in FIG. 2 can be periodically arranged as basic units on the substrate to form an arrangement array. In this arrangement, the crosstalk between each pair of differential interconnection components can be reduced.

In order to facilitate understanding of the three-dimensional structure of various components in FIG. 2 , FIG. 3 shows a cross-sectional view of a part of a semiconductor chip package according to some embodiments of the present disclosure. FIG. 3 shows a solder ball 324 and a PTH 309 electrically connected to the solder ball 324. PTH 309 passes through core 310 of the package substrate. The core 310 occupies most of the thickness of the package substrate, therefore, the PTH 309 is an interconnection structure in the package substrate that is mainly used to realize the function of vertical interconnection. Solder ball 324 may be any one of solder ball 201 , solder ball 202 , solder ball 305 , solder ball 206 , solder ball 209 , solder ball 210 , solder ball 213 and solder ball 214 shown in FIG. 2 . Correspondingly, the PTH 309 may be any one of the PTH 203, PTH 204, PTH 207, PTH 208, PTH 211, PTH 212, PTH 215 and PTH 216 shown in FIG. 2 .

As shown in FIG. 3 , solder balls 324 are disposed on a packaging substrate, which may be a laminated substrate. As shown in FIG. 3 , the packaging substrate includes dielectric layers 301-308, wiring layers 331-338, and a core 310 located between

wiring layers

334 and 335, wherein wiring layer 331 is located between

dielectric layers

301 and 302, and the wiring layer 332 is located between the

dielectric layers

302 and 303, the wiring layer 333 is located between the

dielectric layers

303 and 304, the wiring layer 334 is located between the dielectric layer 304 and the core 310, and the wiring layer 335 is located between the core 310 and the dielectric layer 305 The wiring layer 336 is located between the

dielectric layers

305 and 306 , the wiring layer 337 is located between the

dielectric layers

306 and 307 , and the wiring layer 338 is located between the

dielectric layers

307 and 308 . The dielectric layer 301 is provided with a blind buried via (Blind Buried Via, BB Via) 311, and the blind buried via is a vertical interconnection inside the package substrate, and is used to connect the interconnection outside the package substrate to the PTH. Similarly, the dielectric layer 302 is provided with a blind buried hole 312, the dielectric layer 303 is provided with a blind buried hole 313, the dielectric layer 304 is provided with a blind buried hole 314, and the dielectric layer 305 is provided with a blind buried hole 315. 306 is provided with blind and buried holes 316 , the dielectric layer 307 is provided with blind and buried holes 317 , and the dielectric layer 308 is provided with blind and buried holes 318 . In addition, the core 310 is provided with a PTH 309 for interconnecting the wiring layers 334 and 335. The wiring layer 331 interconnects the blind buried

holes

311 and 312, the wiring layer 332 interconnects the blind buried

holes

312 and 313, the wiring layer 333 interconnects the blind buried

holes

313 and 314, and the wiring layer 334 interconnects the blind buried holes 314 and the PTH 309 Interconnection, the wiring layer 335 interconnects the PTH 309 and the blind buried hole 315, the wiring layer 336 interconnects the blind

buried hole

315 and 316, the wiring layer 337 interconnects the blind

buried hole

316 and 317, and the wiring layer 338 interconnects the blind

buried hole

317 and 318 are interconnected.

The semiconductor chip package also includes a die 322, which is in contact with the blind buried hole 311 through a bump 323, and is further electrically connected with the solder ball 324 through the blind buried holes 312-318 and the PTH 309, thereby transmitting signals. In addition, the semiconductor chip package may further include a resin 321 . It should be understood that in other embodiments, the resin 321 may also be replaced by a metal cover or the like.

In FIG. 3 , the solder ball 324 may be disposed on a pad (not shown) on the package substrate, that is, the solder ball may be disposed between the solder ball 324 and the blind buried hole 318 . In addition, the bump 323 may also be disposed on a pad (not shown) on the package substrate, that is, a pad may be disposed between the bump 323 and the blind buried hole 311 . Due to the corresponding relationship between the solder balls and the solder pads, the description about the solder balls here is also applicable to the solder pads corresponding to the solder balls.

FIG. 4 and FIG. 5 respectively illustrate the principle of crosstalk cancellation between adjacent differential interconnection components in FIG. 2 . If the characteristics of the interference between the closest PTHs and the interference between the closest solder balls between two adjacent differential interconnection components are opposite to each other, the two kinds of interference can cancel each other out. For example, if the interference between the closest PTHs between two adjacent differential interconnect assemblies is in-phase interference, the interference between the closest solder balls between two adjacent differential interconnect assemblies is in-phase interference. If they interfere with each other, the two interferences can be canceled out. For another example, if the interference between the closest PTHs between two adjacent differential interconnect components is anti-phase interference, the interference between the closest solder balls between two adjacent differential interconnect components If it is in-phase interference, the two interferences can also be canceled out. Here, "adjacent" means that no other differential interconnection components are included between two differential interconnection components.

FIG. 4 shows the principle of crosstalk cancellation between the first differential interconnection component and the third differential interconnection component in FIG. 2 . As shown in FIG. 4 , the solder ball 201 in the first differential interconnection assembly is adjacent to the solder ball 205 in the third differential interconnection assembly and transmits signals of the same polarity, so there is in-phase crosstalk between them. The "adjacent" here means that the solder ball 201 in the first differential interconnection component and the solder ball 205 in the third differential interconnection component do not include other components in the first differential interconnection component and the third differential interconnection component. Solder balls. The solder ball 202 in the first differential interconnection assembly is adjacent to the solder ball 206 in the third differential interconnection assembly and transmits signals of the same polarity, therefore, there is also in-phase crosstalk between the two. That is, the interference between the closest solder balls between the first differential interconnection component and the third differential interconnection component is in-phase interference. However, PTH 203 in the first differential interconnection assembly is adjacent to PTH 208 in the third differential interconnection assembly and carries signals of opposite polarity, therefore, there is reverse crosstalk between the two. That is, the interference between the closest PTHs between the first differential interconnection component and the third differential interconnection component is anti-phase interference, which will at least partially cancel the interaction between the first differential interconnection component and the third differential interconnection component. In-phase crosstalk between solder balls. The "adjacent" here means that the PTH 203 in the first differential interconnection component and the PTH 208 in the third differential interconnection component do not include other PTHs in the first differential interconnection component and the third differential interconnection component.

FIG. 5 shows the principle of crosstalk cancellation between the first differential interconnection component and the second differential interconnection component in FIG. 2 . As shown in FIG. 5, the solder ball 202 in the first differential interconnection assembly is adjacent to the solder ball 209 in the second differential interconnection assembly and transmits signals of opposite polarity, therefore, there is anti-phase crosstalk between the two . That is, the interference between the closest solder balls between the first differential interconnection component and the second differential interconnection component is anti-phase interference. PTH 203 in the first differential interconnection assembly is adjacent to PTH 211 in the second differential interconnection assembly and transmits signals of the same polarity, therefore, there is in-phase crosstalk between the two, i.e., the first differential interconnection assembly The interference between the closest PTH and the second differential interconnection component is in-phase interference, which will at least partially offset the anti-phase crosstalk between the solder balls of the first differential interconnection component and the third differential interconnection component.

FIG. 6 shows a planar projection of a semiconductor chip package according to some embodiments of the present disclosure. As shown in FIG. 6, the first differential interconnection assembly includes a solder ball 401, a solder ball 402, a PTH 403, and a PTH 404, wherein the solder ball 401 and the solder ball 402 are electrically connected to the PTH 404 and the PTH 403, respectively. The second differential interconnect assembly includes solder ball 405, solder ball 406, PTH 407, and PTH 408, wherein solder ball 405 and solder ball 406 are electrically connected to PTH 408 and PTH 407, respectively. For example,

solder balls

401, 402, 405, 406 and

PTHs

403, 404, 407, and 408 can be implemented by the embodiment shown in FIG. 3 .

In FIG. 6 , the

solder balls

401 , 402 , 405 and 406 may be arranged in a straight line or in a row so as to be conveniently arranged at the edge of the semiconductor chip package. The

solder balls

401 and 402 may be located on the edge of the semiconductor chip package, so that the

PTHs

403 and 404 cannot be arranged on both sides of the connection line between the

solder balls

401 and 402, but on the same side. Similarly, the

solder balls

405 and 406 may be located at the edge of the semiconductor chip package, so that the

PTHs

407 and 408 cannot be placed on both sides of the connection between the

solder balls

405 and 406, but on the same side.

As shown in FIG. 6 , the solder ball 402 in the first differential interconnection assembly is adjacent to the solder ball 405 in the second differential interconnection assembly, and transmits signals of opposite polarity, so there is reverse crosstalk. That is, the interference between the closest solder balls between the first differential interconnection component and the second differential interconnection component is anti-phase interference. However, PTH 403 in the first differential interconnection is adjacent to PTH 407 in the second differential interconnection and transmits signals of the same polarity, so there is in-phase crosstalk, and PTH 404 in the first differential interconnection is adjacent to PTH 407 in the second differential interconnection. The PTHs 408 in the second differential interconnect are adjacent and carry signals of the same polarity, so there is in-phase crosstalk. That is, the interference between the closest PTHs between the first differential interconnection component and the second differential interconnection component is in-phase interference. In this way, in-phase and anti-phase crosstalk can cancel each other out.

FIG. 7 shows a planar projection of a semiconductor chip package according to some embodiments of the present disclosure. As shown in FIG. 7, the first differential interconnection assembly includes a solder ball 501, a solder ball 502, a PTH 503, and a PTH 504, wherein the solder ball 501 and the solder ball 502 are electrically connected to the PTH 503 and the PTH 504, respectively. The second differential interconnect assembly includes solder ball 505, solder ball 506, PTH 507, and PTH 508, wherein solder ball 505 and solder ball 506 are electrically connected to PTH 507 and PTH 508, respectively. For example,

solder balls

501, 502, 505, 506 and

PTHs

503, 504, 507, and 508 can be implemented by the embodiment shown in FIG. 3 . This arrangement can be flexibly arranged at the corner of the semiconductor chip package, for example, the upper right corner of FIG. 7 may correspond to the corner of the semiconductor chip package. Due to the limitation of the space at the corner, the spatial arrangement of the solder balls is limited, and the solder balls cannot be arranged according to the layout shown in FIG. 2 . In the embodiment shown in FIG. 7, the connection between the solder ball 501 and the solder ball 502 in the first differential interconnection assembly is the same as the connection between the solder ball 505 and the solder ball 506 in the second differential interconnection assembly. The lines are perpendicular to each other to accommodate the space requirements at the corners of the semiconductor chip package. In addition, the connection between PTH 503 and PTH 504 in the first differential interconnection component and the connection between PTH 507 and PTH 508 in the second differential interconnection component are parallel to each other.

As shown in FIG. 7 , the solder ball 502 in the first differential interconnection assembly is adjacent to the solder ball 506 in the second differential interconnection assembly and transmits signals of the same polarity, so there is in-phase crosstalk. That is, the interference between the closest solder balls between the first differential interconnection component and the second differential interconnection component is in-phase interference. However, PTH 504 in the first differential interconnect assembly is adjacent to PTH 507 in the second differential interconnect assembly and carries signals of opposite polarity, so there is anti-phase crosstalk. That is, the interference between the closest PTHs between the first differential interconnection component and the second differential interconnection component is anti-phase interference. In this way, in-phase and anti-phase crosstalk can cancel each other out.

FIG. 8 shows a planar projection of a semiconductor chip package according to some embodiments of the present disclosure. As shown in FIG. 8, the first differential interconnection assembly includes a solder ball 601, a solder ball 602, a PTH 603, and a PTH 604, wherein the solder ball 601 and the solder ball 602 are electrically connected to the PTH 604 and the PTH 603, respectively. The second differential interconnect assembly includes solder ball 605, solder ball 606, PTH 607, and PTH 608, wherein solder ball 605 and solder ball 606 are electrically connected to PTH 607 and PTH 608, respectively. For example,

solder balls

601, 602, 605, 606 and

PTHs

603, 604, 607, and 608 can be implemented by the embodiment shown in FIG. 3 . This arrangement can be flexibly arranged at the corner of the semiconductor chip package, for example, the upper right corner of FIG. 8 may correspond to the corner of the semiconductor chip package. In the embodiment shown in FIG. 8, the connection between the solder ball 601 and the solder ball 602 in the first differential interconnect assembly is the same as the connection between the solder ball 605 and the solder ball 606 in the second differential interconnect assembly. The lines are perpendicular to each other. However, the wiring between PTH 603 and PTH 604 in the first differential interconnection assembly and the wiring between PTH 607 and PTH 608 in the second differential interconnection assembly are parallel to each other so as to fit the corner of the semiconductor chip package. space requirements. From another point of view, the connection line between solder ball 601 and solder ball 602 and the connection line between PTH 603 and PTH 604 are perpendicular to each other, and the connection line between solder ball 605 and solder ball 606 is perpendicular to PTH 607 and The connections between the PTHs 608 are parallel to each other.

As shown in FIG. 8 , the solder ball 602 in the first differential interconnection assembly is adjacent to the solder ball 606 in the second differential interconnection assembly, and transmits signals of the same polarity, so there is in-phase crosstalk. However, PTH 604 in the first differential interconnection assembly is adjacent to PTH 608 in the second differential interconnection assembly and carries signals of opposite polarity, thus presenting anti-phase crosstalk. In this way, in-phase and anti-phase crosstalk can cancel each other out.

FIG. 9 illustrates a cross-sectional view of a portion of a semiconductor chip package according to some embodiments of the present disclosure. Compared with FIG. 3 , in FIG. 9 , solder balls 324 are connected to a printed circuit board (Printed Circuit Board, PCB) to form a next-level package, wherein the printed circuit board includes layers 731-733. As shown in FIG. 9 , the layer 731 is provided with a trace 741, the layer 731 is provided with a PTH 742, and the layer 733 is provided with a trace 743. The above embodiments shown in conjunction with FIGS. 2 and 4-8 can also be applied to solder balls 324 and PTH 742. For example, solder ball 324 may be any one of solder ball 201 , solder ball 202 , solder ball 305 , solder ball 206 , solder ball 209 , solder ball 210 , solder ball 213 and solder ball 214 shown in FIG. 2 . Correspondingly, the PTH 742 may be any one of the PTH 203, PTH 204, PTH 207, PTH 208, PTH 211, PTH 212, PTH 215 and PTH 216 shown in FIG. 2 .

FIG. 10 shows a planar projection of a semiconductor chip package according to some embodiments of the present disclosure. Compared with FIG. 2, FIG. 10 further shows PTH 801 to PTH 805 located between the two differential interconnect components, and these PTHs all serve as ground vias. For example, PTH 801 to PTH 804 may be arranged symmetrically. However, it should be understood that the PTH 805 may also not be included. Between the first differential pair (solder ball 201 and solder ball 202) there is a PTH 806 and a PTH 807, also serving as a ground via. The connecting line of PTH 806 and PTH 807 passes through the midpoint of PTH 203 and PTH 204. In addition, the connection of PTH 203 and PTH 204 can also pass through the midpoint of PTH 806 and PTH 807. It should be understood that there may also be the same PTH between the solder ball 205 and the solder ball 206 , however, for simplicity, the PTH between the solder ball 205 and the solder ball 206 is omitted in FIG. 10 . In addition, PTH 806 and PTH 807 can also be replaced by other numbers of PTH holes such as one or three.

In Fig. 10, the distance from PTH 801-PTH 804 to the corresponding signal PTH hole is represented as R, the angle between PTH 801-PTH 804 and the corresponding signal PTH hole is represented as α, and the distance between PTH 806 and PTH 807 The angle between the connection line and the horizontal direction is expressed as β. For example, the distance between PTH 801 and PTH 203 is R, the distance between PTH 802 and PTH 203 is R, the distance between PTH 803 and PTH 208 is R, and the distance between PTH 804 and PTH 208 is R. By adjusting the distance R and the angle β, the impedance continuity can be optimized, and by adjusting the angle α and the presence or absence of PTH 805, the optimization of crosstalk elimination can be realized. Figure 11 shows the effect of crosstalk cancellation at different α angles.

It should be understood that FIG. 10 and FIG. 11 are described in conjunction with the first differential interconnection assembly and the third differential interconnection assembly shown in FIG. 2 . However, those skilled in the art should understand that this structure is also applicable to the first differential interconnection component and the second differential interconnection component as shown in FIG. 2 . For example, in the first differential interconnection component and the second differential interconnection component as shown in FIG. 2 , adjusting the size of the angle α can also optimize the effect of crosstalk cancellation.

FIG. 12 illustrates crosstalk between the first differential interconnection assembly and the third differential interconnection assembly as shown in FIG. 2 when located at the edge of a semiconductor chip package. As shown in FIG. 12 , compared with FIG. 1 , the first differential interconnection component and the third differential interconnection component of FIG. 2 have a gain of 10 dB+ in a wider frequency band (DC˜40 GHz).

FIG. 13 illustrates crosstalk between the first differential interconnection assembly and the third differential interconnection assembly as shown in FIG. 2 when located inside a semiconductor chip package. As shown in FIG. 13 , compared with FIG. 1 , the first differential interconnection component and the third differential interconnection component of FIG. 2 have a gain of 10dB+ in a wider frequency band (15GHz˜40GHz).

FIG. 14 illustrates crosstalk between the first differential interconnect assembly and the second differential interconnect assembly as shown in FIG. 2 . As shown in FIG. 14 , compared with FIG. 1 , the first differential interconnection assembly and the second differential interconnection assembly of FIG. 2 have a gain of 10 dB+ in a wider frequency band (DC˜40 GHz).

FIG. 15 illustrates crosstalk between the first differential interconnect assembly and the second differential interconnect assembly as shown in FIG. 6 . As shown in FIG. 15, compared with FIG. 1, the first differential interconnection component and the second differential interconnection component in FIG. 10dB+ gain.

FIG. 16 shows a schematic diagram of package routing due to differential polarity reversal on the bump and ball sides. As shown in FIG. 16 , the solder ball 901 and the solder ball 902 are respectively used to transmit a positive polarity signal and a negative polarity signal in the differential signal. The

bumps

905 and 906 are respectively used to transmit the positive polarity signal and the negative polarity signal in the differential signal. Therefore, at the time of connection, there is a case where the package is wound.

FIG. 17 shows a schematic diagram of an outlet layout according to some embodiments of the present disclosure. For brevity, Figure 17 omits the solder balls. Compared with FIG. 10 , FIG. 17 also shows blind and buried holes 1003 to 1008 . The blind and buried holes 1003 to 1008 present a ladder-like structure, similar to a DNA double helix structure. Specifically, the blind and buried

holes

1003, 1005 and 1007 are stacked along a first direction, wherein the first direction represents the direction from the blind and buried holes 1003 to the blind and buried holes 1007; the blind and buried

holes

1004, 1006 and 1008 are stacked along the One direction is opposite to the stacking in a second direction, wherein the second direction represents the direction from the blind buried hole 1004 to the blind buried hole 1008 . Blind and buried

vias

1004, 1006 and 1008 are used to electrically connect the bumps to the PTH 203, and blind and buried

vias

1003, 1005 and 1007 are used to electrically connect the bumps to the PTH 204. Therefore, the lead wire 1011 has a negative polarity, and the lead wire 1012 has a positive polarity. For example, the blind and buried

vias

1003 , 1005 and 1007 may respectively correspond to the blind and buried

vias

314 , 313 and 312 as shown in FIG. 9 . Correspondingly, the lead 1011 may correspond to the wiring layer 331 as shown in FIG. 9 , and is used for connecting with the bump 323 . For example, blind and buried

vias

1004 , 1006 and 1008 may correspond to blind and buried

vias

314 , 313 and 312 as shown in FIG. 9 , respectively. Correspondingly, the lead 1012 may correspond to the wiring layer 331 as shown in FIG. 9 , and is used for connecting with the bump 323 . FIG. 17 does not show the blind and buried vias between the PTH and the solder balls. It should be understood that the blind and buried vias between the PTH and the solder balls can also be similarly arranged.

FIG. 18 shows a schematic diagram of an outlet layout according to some embodiments of the present disclosure. For brevity, Figure 18 omits the solder balls. Compared with FIG. 10 , FIG. 18 also shows blind and buried holes 1003 to 1008 . The blind and buried holes 1003 to 1008 present a ladder-like structure, similar to a DNA double helix structure. Therefore, the lead wire 1111 has a positive polarity, and the lead wire 1112 has a negative polarity. For example, the blind and buried

vias

1003 , 1005 and 1007 may respectively correspond to the blind and buried

vias

314 , 313 and 312 as shown in FIG. 9 . Correspondingly, the lead 1111 may correspond to the wiring layer 331 as shown in FIG. 9 , and is used for connecting with the bump 323 . For example, blind and buried

vias

1004 , 1006 and 1008 may correspond to blind and buried

vias

314 , 313 and 312 as shown in FIG. 9 , respectively. Correspondingly, the lead 1112 may correspond to the wiring layer 331 as shown in FIG. 9 , and is used for connecting with the bump 323 . FIG. 18 does not show the blind and buried vias between the PTH and the solder balls. It should be understood that the blind and buried vias between the PTH and the solder balls can also be similarly arranged. In Figure 17, the leads are drawn out from the left, while in Figure 18 the leads are drawn out from the right, which will lead to a switching of the polarity, so that a flexible wiring scheme can be realized and wire winding can be prevented.

FIG. 19 shows a schematic diagram of an outlet layout according to some embodiments of the present disclosure. For brevity, Figure 19 omits the solder balls. FIG. 19 shows PTH 1201 and PTH 1202, which are respectively used to transmit negative polarity signals and positive polarity signals in differential signals.

PTHs

1221 and 1222 are used for grounding, corresponding to

PTHs

806 and 807 shown in Figure 10. The blind and buried holes 1203 to 1208 present a stepped structure. Therefore, the lead wire 1211 is of negative polarity, and the lead wire 1212 is of positive polarity. For example, the blind and buried

vias

1203 , 1205 and 1207 may respectively correspond to the blind and buried

vias

314 , 313 and 312 as shown in FIG. 9 . Correspondingly, the lead 1211 may correspond to the wiring layer 331 as shown in FIG. 9 , and is used for connecting with the bump 323 . For example, blind and buried

vias

1204 , 1206 and 1208 may correspond to blind and buried

vias

314 , 313 and 312 as shown in FIG. 9 , respectively. Correspondingly, the lead 1212 may correspond to the wiring layer 331 as shown in FIG. 9 , and is used for connecting with the bump 323 . FIG. 19 does not show the blind and buried vias between the PTH and the solder balls. It should be understood that the blind and buried vias between the PTH and the solder balls can also be similarly arranged. The solution shown in FIG. 19 is a middle outlet solution, which can be used to replace the left side outlet solution shown in FIG. 17 .

FIG. 20 shows a schematic diagram of a layout of ground holes according to some embodiments of the present disclosure. Compared to Figure 17, one ground hole PTH 1301 replaces two

ground holes PTH

406 and 407. As shown in Figure 20, PTH 1301 is located between PTH 203 and PTH 204.

FIG. 21 shows a schematic diagram of a layout of ground holes according to some embodiments of the present disclosure. Compared with FIG. 17, three ground holes PTH 1401 to PTH 1403 replace two

ground holes PTH

406 and 407. As shown in Figure 21, PTH 1402 is located between PTH 203 and PTH 204.

FIG. 22 shows a schematic diagram of a layout of ground holes according to some embodiments of the present disclosure. Compared with FIG. 17, three ground holes PTH 1501 to PTH 1503 replace two

ground holes PTH

406 and 407. As shown in Figure 22, PTH 1502 is located between PTH 203 and PTH 204.

Although the embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can easily understand from this disclosure that, according to this disclosure, existing or future developed processes and machine devices that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described in this disclosure can be used , manufacture, composition of matter, tool, method or step. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and combinations of individual claims and embodiments are within the scope of the present disclosure.

Claims

A semiconductor chip package, characterized in that it comprises:

A first differential interconnection component, the first differential interconnection component comprising:

The first pad and the second pad are arranged on the substrate and are used to transmit the first differential signal; and

A first plated-through hole and a second plated-through hole are disposed in the substrate and electrically connected to the first pad and the second pad, respectively; and

The second differential interconnection component is adjacent to the first differential interconnection component, and the second differential interconnection component includes:

The third pad and the fourth pad are arranged on the substrate and are used to transmit the second differential signal; and

a third plated-through hole and a fourth plated-through hole arranged in the substrate and electrically connected to the third pad and the fourth pad respectively,

Wherein, in the planar projection of the semiconductor chip package, the second pad in the first differential interconnection assembly is adjacent to the third pad in the second differential interconnection assembly, and the first differential the first plated-through hole in the interconnect assembly is adjacent to the third plated-through hole in the second differential interconnect assembly; and

Wherein, the polarities of the signals transmitted by the second pad and the third pad are the same, and the polarities of the signals transmitted by the first plated hole and the third plated hole are opposite; or, the The polarities of the signals transmitted by the second pad and the third pad are opposite, and the polarities of the signals transmitted by the first plated hole and the third plated hole are the same.
The semiconductor chip package according to claim 1, wherein, in the plane projection of the semiconductor chip package:

The line between the first pad and the second pad is perpendicular to the line between the first plated hole and the second plated hole, and the third pad and The connection line between the fourth pads and the connection line between the third plated hole and the fourth plated hole are perpendicular to each other.
The semiconductor chip package according to claim 1 or 2, wherein, in the planar projection of the semiconductor chip package:

The first pad in the first differential interconnect assembly is adjacent to the fourth pad in the second differential interconnect assembly.
The semiconductor chip package according to any one of claims 1-3, wherein, in the planar projection of the semiconductor chip package:

The first plated through hole is located on one side of the first pad and the second pad, and the second plated hole is located on the other side of the first pad and the second pad .
The semiconductor chip package according to any one of claims 1-4, wherein, in the planar projection of the semiconductor chip package:

The first pad and the fourth pad are arranged in a first row, and the second pad and the third pad are arranged in a second row adjacent to the first row.
The semiconductor chip package according to claim 1, 2 or 4, wherein, in the planar projection of the semiconductor chip package:

The second pads and the third pads are arranged in adjacent rows and adjacent columns.
The semiconductor chip package according to claim 1 or 2, wherein, in the planar projection of the semiconductor chip package:

The first to fourth pads are arranged in a row, and the first to fourth plated holes are located at one side of the row.
The semiconductor chip package according to claim 1, 2 or 4, wherein, in the planar projection of the semiconductor chip package:

The connection line between the first pad and the second pad and the connection line between the third pad and the fourth pad are perpendicular to each other.
The semiconductor chip package according to claim 1, wherein, in the plane projection of the semiconductor chip package:

The connection line between the first pad and the second pad and the connection line between the first plated hole and the second plated hole are perpendicular to each other, and the third pad and the The connection line between the fourth pad and the connection line between the third plated hole and the fourth plated hole are parallel to each other, and the connection between the first pad and the second pad and the connection line between the third pad and the fourth pad are perpendicular to each other.
The semiconductor chip package according to claim 8 or 9, wherein, in the planar projection of the semiconductor chip package:

The first pads are arranged in a first row, the second pads are arranged in a second row, and the third pads and the fourth pads are arranged in a third row.
The semiconductor chip package according to any one of claims 1-10, further comprising:

one or more plated-through holes for electrical connection to ground are provided in the substrate between the first pad and the second pad in planar projection of the semiconductor chip package; and /or

One or more plated-through holes for electrical connection to ground are provided in the substrate between the third pad and the fourth pad in planar projection of the semiconductor chip package.
The semiconductor chip package according to any one of claims 1-11, characterized in that,

The first pad and the second pad are respectively connected to the first plated hole and the second plated hole through a double helix blind buried hole; and/or

The third pad and the fourth pad are respectively connected to the first plated hole and the second plated hole through a double helix blind buried hole, wherein the double helix blind buried hole includes A first plurality of blind buried holes electrically connected to each other and a second plurality of blind buried holes electrically connected to each other, the first plurality of blind buried holes are stacked along a first direction, and the second plurality of blind buried holes are stacked along a first direction stacking in a second direction opposite to the first direction.
The semiconductor chip package according to any one of claims 1-12, characterized in that,

The substrate includes a laminated substrate or a printed circuit board (PCB).
The semiconductor chip package according to claim 5, further comprising:

A third differential interconnection component, where the third differential interconnection component includes:

The fifth pad and the sixth pad are arranged on the substrate and are used to transmit the third differential signal; and

fifth plated-through holes and sixth plated-through holes are disposed in the substrate and are electrically connected to the fifth pad and the sixth pad; and

A fourth differential interconnection component, where the fourth differential interconnection component includes:

The seventh pad and the eighth pad are arranged on the substrate and are used to transmit the fourth differential signal; and

The seventh plated-through hole and the eighth plated-through hole are arranged in the substrate and are electrically connected to the seventh pad and the eighth pad respectively,

Wherein, the sixth pad in the third differential interconnection assembly is adjacent to the seventh pad in the fourth differential interconnection assembly, and the fifth pad in the third differential interconnection assembly is adjacent to the seventh pad in the third differential interconnection assembly. The eighth pad in the fourth differential interconnection assembly is adjacent, and the fifth plated-through hole in the third differential interconnection assembly is adjacent to the sixth plated-through hole in the fourth differential interconnection assembly;

Wherein, the polarities of the signals transmitted by the sixth pad and the seventh pad are the same, and the polarities of the signals transmitted by the fifth plated hole and the sixth plated hole are opposite; or the The polarities of the signals transmitted by the sixth pad and the seventh pad are opposite, and the polarities of the signals transmitted by the fifth plated hole and the sixth plated hole are the same; and

Wherein, in the planar projection of the semiconductor chip package, the fifth pad and the eighth pad are arranged in the third row, and the sixth pad and the seventh pad are arranged in the same row as the The fourth row adjacent to the third row, the first pad and the second pad are arranged in the first column, the fifth pad and the sixth pad are arranged in the same row as the first The second column adjacent to the column, the third pad and the fourth pad are arranged in the third column adjacent to the second column, the seventh pad and the eighth pad are arranged In the fourth column adjacent to said third column.
The semiconductor chip package according to claim 14, wherein,

The first differential interconnection component, the second differential interconnection component, the third differential interconnection component and the fourth differential interconnection component are periodically arranged as units on the substrate.