WO2023077772A1 - Cellule solaire et son procédé de préparation - Google Patents

Cellule solaire et son procédé de préparation Download PDF

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WO2023077772A1
WO2023077772A1 PCT/CN2022/093351 CN2022093351W WO2023077772A1 WO 2023077772 A1 WO2023077772 A1 WO 2023077772A1 CN 2022093351 W CN2022093351 W CN 2022093351W WO 2023077772 A1 WO2023077772 A1 WO 2023077772A1
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layer
silicon substrate
electrode
type silicon
silicon
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PCT/CN2022/093351
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English (en)
Chinese (zh)
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张东威
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西安隆基乐叶光伏科技有限公司
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Priority claimed from CN202111314179.4A external-priority patent/CN114256381B/zh
Priority claimed from CN202111648529.0A external-priority patent/CN114388633A/zh
Application filed by 西安隆基乐叶光伏科技有限公司 filed Critical 西安隆基乐叶光伏科技有限公司
Publication of WO2023077772A1 publication Critical patent/WO2023077772A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
    • H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention generally relates to the technical field of solar cells, in particular to a solar cell and a preparation method thereof.
  • Perc battery benefits from the development of alumina passivation technology, which greatly reduces the recombination of the back surface of the battery, and is currently the mainstream battery product in the photovoltaic market. With the upgrading of process and equipment technology, the efficiency improvement of Perc battery has encountered a bottleneck.
  • a solar cell provided by an embodiment of the present application includes: a P-type silicon substrate, the P-type silicon substrate has a front side and a back side, the back side is a smooth structure, and the back side is sequentially provided with tunneling silicon oxide from top to bottom layer, a phosphorus-doped polysilicon layer, a first passivation layer and a back electrode, and the back electrode is in contact with the phosphorus-doped polysilicon layer;
  • the front is a suede structure, and the front is provided with a second passivation layer and a front electrode in sequence from bottom to top.
  • the front electrode is in contact with the P-type silicon substrate, and a P+ layer is formed in the area where the front electrode contacts the P-type silicon substrate.
  • the back passivation effect is good, and the back electrode is not directly in contact with the P-type silicon substrate, effectively The metal recombination is reduced, thereby increasing the open circuit voltage of the battery.
  • the front electrode contacts the passivation layer and forms a P+ layer at the same time, which can effectively conduct current and play a field passivation role, which is conducive to enhancing the PN junction to shunt photogenerated carriers. The effect of reducing recombination loss and improving battery efficiency.
  • the thickness of the silicon oxide layer is less than 2 nm, and the thickness of the phosphorus-doped polysilicon layer is 110 nm-130 nm.
  • the thickness of the silicon oxide layer is 1.3nm-1.7nm.
  • the first passivation layer is a silicon nitride layer.
  • the second passivation layer is an aluminum oxide and silicon nitride layer.
  • the back electrode is a silver electrode and the front electrode is an aluminum electrode.
  • the N-type TOPCon cell includes an N-type monocrystalline silicon substrate, a front electrode and a back electrode, wherein the N-type monocrystalline silicon substrate has a P+ doped layer on the front, and the front electrode and the The P+ doped layer is in direct contact, and the area where the P+ doped layer is not in contact with the front electrode is covered with a front passivation layer; the back of the N-type single crystal silicon substrate has an N+ doped layer, and the back electrode In direct contact with the N+ doped layer, the area where the N+ doped layer and the corresponding monocrystalline silicon substrate are in contact with the back electrode has a textured pyramid structure, and the N+ doped layer is not in contact with the back electrode
  • the area of is a square shape, and the square size in the square shape is 20 ⁇ m ⁇ 2 ⁇ m.
  • the embodiments of the present application provide a method for preparing a solar cell according to the first aspect, comprising the following steps:
  • a tunneling silicon oxide layer and a polysilicon layer are sequentially deposited in a low-pressure chemical vapor deposition furnace;
  • the front electrode and the back electrode are printed respectively.
  • the P-type silicon substrate is polished in a cleaning machine filled with polishing liquid, wherein the polishing liquid includes water, lye and additives, the additives include surfactants, sodium citrate, and sodium benzoate, and the temperature of the polishing treatment is 53°C- 57°C, the time is 215s-225s.
  • the polishing liquid includes water, lye and additives
  • the additives include surfactants, sodium citrate, and sodium benzoate
  • the temperature of the polishing treatment is 53°C- 57°C
  • the time is 215s-225s.
  • the reflectivity of the front and back surfaces of the P-type silicon substrate is 38%-44%.
  • the front side of the P-type silicon substrate before the front side of the P-type silicon substrate is textured to form a textured structure, it also includes:
  • the front side of the P-type silicon substrate is placed in a washing solution filled with hydrofluoric acid at room temperature to remove the PSG on the front side of the P-type silicon substrate; wherein, the mass concentration of the washing solution of hydrofluoric acid is 8%-12%.
  • the front side of the P-type silicon substrate is textured to form a textured structure, including:
  • the P-type silicon substrate is immersed in the texturing liquid for texturing; wherein, the texturing liquid includes KOH solution, and the mass concentration of the KOH solution is 0.5%-1.5%; the temperature of the texturing liquid is 77°C-83°C, and the P-type silicon
  • the time for the substrate to be immersed in the texturing solution is 495s-505s.
  • the front surface of the P-type silicon substrate is textured to form a textured structure, wherein the reflectance of the textured structure is 8.7%-9.3%.
  • before printing the front electrode on the front side of the P-type silicon substrate including:
  • the front electrode is printed on the front surface of the P-type silicon substrate, wherein the paste for the front electrode is aluminum paste.
  • the method includes:
  • step (3) depositing a silicon oxide compound layer on the back side of the silicon wafer obtained in step (2);
  • step (4) Carry out backside etching treatment to the silicon wafer that step (4) obtains, and remove the silicon oxide compound layer of non-laser region;
  • the metal gate line on the back side of the silicon wafer is arranged at a position corresponding to the groove pattern.
  • the polished The etching amount is 0.58g ⁇ 0.05g, wherein, the temperature of the polishing treatment is 65°C ⁇ 3°C, the time is 400s ⁇ 20s, the polishing solution used includes alkali and polishing additives, and the alkali includes KOH and/or NaOH , the volume concentration of the alkali is 4v% ⁇ 0.2v%.
  • step (2) in the square shape, the square size is 20 ⁇ m ⁇ 2 ⁇ m.
  • the back reflectance of the silicon wafer obtained in step (2) is 42% ⁇ 1%.
  • the thickness of the silicon oxide compound layer is 90-150 nm.
  • step (4) the power of the laser grooving is 20W ⁇ 5W, and the frequency is 40000Hz ⁇ 2000Hz.
  • the temperature of the etching treatment is 80°C ⁇ 3°C, and the time is 120s ⁇ 10s, wherein the etching solution used in the etching treatment includes alkali, the The base includes KOH and/or NaOH, and the volume concentration of the base is 1v% ⁇ 0.2v%.
  • the method for preparing an N-type TopCon cell further includes: (7) taking the side of the silicon wafer with boron diffusion as the front side, implanting phosphorus into the polysilicon layer on the back of the silicon wafer, And remove the polysilicon layer on the front side of the silicon wafer; (8) deposit an aluminum oxide layer and a silicon nitride layer on the front side of the silicon wafer in sequence to form a front passivation layer; (9) deposit a silicon nitride layer on the back side of the silicon wafer to form a passivation layer on the back side (10) printing electrode paste on the front and back of the silicon wafer and sintering to obtain battery sheets.
  • FIG. 1 is a schematic structural view of a solar cell provided by an embodiment of the present invention
  • Fig. 2 is a flow chart of a method for preparing an N-type TopCon battery sheet according to an embodiment of the present invention
  • Fig. 3 is a schematic structural diagram of an N-type TopCon cell obtained by a method for preparing an N-type TopCon cell according to an embodiment of the present invention.
  • a solar cell according to an embodiment of the present invention is described below with reference to FIG. 1 .
  • the solar cell according to the embodiment of the present application includes: a P-type silicon substrate 1.
  • the P-type silicon substrate 1 has a front surface and a back surface.
  • the front side is a suede structure, and the second passivation layer 6 and the front electrode 7 are stacked in sequence on the front side, the front electrode 7 is in contact with the P-type silicon substrate 1, and the area where the front electrode 7 contacts the P-type silicon substrate 1 forms There are P+ layer 8.
  • the first passivation layer 4 on the back mainly plays a protective role and reduces metal recombination.
  • the specific type of the first passivation layer 4 is not limited, and those skilled in the art can select according to actual needs, such as the first passivation layer 4
  • the nitride layer 4 can be a silicon nitride layer, or a mixture layer of other metal oxides and silicon nitride; the smooth structure on the back makes the back have a good passivation effect; the textured structure on the front is conducive to increasing the front electrode 7
  • the contact area with the silicon substrate improves the contact resistance and reduces surface recombination; wherein, the textured structure on the front side can be a pyramid textured structure.
  • the back electrode 5 and the front electrode 7 may be commonly used metal electrodes, such as silver metal grid line electrodes and aluminum metal grid line electrodes.
  • aluminum paste or silver-aluminum paste can generally be used during the printing process of the front electrode. Since the number of valence electrons of aluminum is 3, the aluminum paste forms an aluminum-silicon alloy during the printing and sintering process with the silicon substrate. In this way, the P+ layer is formed, on the one hand, it plays the role of conducting current, on the other hand, it plays the role of field passivation, thereby enhancing the effect of PN junction shunting photogenerated carriers, reducing recombination loss, and improving battery efficiency.
  • the back passivation effect is good, and the back electrode is not directly in contact with the P-type silicon substrate, effectively The metal recombination is reduced, thereby increasing the open circuit voltage of the battery.
  • the front electrode contacts the passivation layer and forms a P+ layer at the same time, which can effectively conduct current and play a field passivation role, which is conducive to enhancing the PN junction to shunt photogenerated carriers. The effect of reducing recombination loss and improving battery efficiency.
  • the thickness of the tunneling silicon oxide layer 2 is less than 2 nm, and the thickness of the phosphorus-doped polysilicon layer 3 is 110 nm-130 nm.
  • the thickness of the tunneling silicon oxide layer 2 is 1.3nm-1.7nm, such as 1.3nm, 1.5nm, 1.7nm; the thickness of the phosphorus-doped polysilicon layer 3 is 110nm-130nm, such as 110nm , 115nm, 120nm, 125nm, 130nm.
  • the thickness of the silicon oxide layer and the thickness of the phosphorus-doped polysilicon layer in this embodiment ensure that the backside of the silicon substrate has an excellent passivation effect on the metal contact, effectively reducing the recombination under the metal contact on the backside, thereby increasing the open circuit voltage.
  • the first passivation layer is a silicon nitride layer.
  • the second passivation layer is an aluminum oxide and silicon nitride layer.
  • the back electrode is a silver electrode
  • the front electrode is an aluminum electrode
  • step S1 in the low-pressure chemical vapor deposition furnace sequentially deposits the deposition of the silicon oxide layer and the deposition of the polysilicon layer on the surface of the P-type silicon substrate, and the low-pressure chemical vapor deposition furnace can realize tunneling respectively.
  • the deposition of the silicon oxide layer and the deposition of the polysilicon layer do not need to take out the silicon substrate and then deposit the polysilicon layer after the tunneling silicon oxide layer is deposited, the operation is simple and convenient, and the process flow is saved;
  • step S2 the silicon substrate treated in step S1 is put into a phosphorus diffusion furnace, and phosphorus is doped on the back side of the silicon substrate to form a PSG layer, which further improves the passivation effect of the back side, and PSG can effectively protect the back side.
  • PSG phosphorus
  • the subsequent texturing process there is no need for mask protection on the back side, which can ensure that the back structure will not be etched.
  • the dewinding process is omitted, and the process steps are further shortened, which in turn helps to reduce the cost of battery manufacturing;
  • step S3 the front side of the silicon substrate is textured, and the silicon substrate is immersed in a tank-type texturing cleaning machine containing a texturing liquid, and the texturing liquid etches the front side of the silicon substrate, wherein the etching time and temperature are controlled to ensure the amount of etching At 0.6 ⁇ 0.05g, a front suede structure is formed.
  • the temperature and time should be controlled to avoid excessive time or high temperature from affecting the back structure, and at the same time prolong the time of the entire process;
  • step S4, S5 and S6 are executed in sequence to obtain the solar cell.
  • the cell is a back-junction cell, the PN junction is on the back side, and the photogenerated carriers are mainly transported vertically in the range from the front surface to the PN junction, and the lateral transport is less, so the front electrode and silicon
  • the substrate contact is good enough, there is no need to do boron doping on the front of the silicon substrate, which simplifies the process flow and reduces the manufacturing cost.
  • it avoids the impact of the high temperature process of the boron diffusion route on the life of the silicon substrate, and also avoids boron paste + laser The problem of damage to the silicon substrate caused by the route laser;
  • the texturing process can remove the front PSG layer and realize single-sided texturing on the front, and the back PSG layer is a mask to protect the back structure from being etched. Compared with the traditional process route, the dewinding and plating process is omitted, and the process is further shortened steps, reducing battery manufacturing costs;
  • S1 sequentially depositing a tunneling silicon oxide layer and depositing a polysilicon layer on the back of the P-type silicon substrate, it also includes:
  • the P-type silicon substrate is polished in a cleaning machine filled with polishing liquid, wherein the polishing liquid includes water, lye and additives, the additives include surfactants, sodium citrate, and sodium benzoate, and the temperature of the polishing treatment is 53°C- 57°C, the time is 215s-225s; the manufacturer of the additives can be Topband BP51, and in specific use, the ratio of H 2 O:KOH:additives in the polishing solution can be 340:16:4.
  • the lye in the polishing solution can be a potassium hydroxide solution with a mass concentration of about 4%, and of course it can also be other lye;
  • the polishing treatment temperature and time disclosed in this embodiment are conducive to ensuring the etching amount of the silicon substrate 0.2 ⁇ 0.02g, which is conducive to cleaning the surface of the silicon substrate, so that the reflectivity of the surface of the silicon substrate can meet a certain requirement, and at the same time ensure the reliable progress of the subsequent steps.
  • the reflectivity of the front and back surfaces of the P-type silicon substrate is 38%-44%.
  • the front side of the P-type silicon substrate before the front side of the P-type silicon substrate is textured to form a textured structure, it also includes:
  • the front side of the P-type silicon substrate is placed in a washing solution filled with hydrofluoric acid at room temperature to remove the PSG on the front side of the P-type silicon substrate; wherein, the mass concentration of the washing solution of hydrofluoric acid is 8%-12%.
  • step S2 when the polysilicon layer is doped with phosphorus, a PSG layer is also formed on the front side of the silicon substrate.
  • the process conditions of the texturing step are reduced. Therefore, the silicon substrate can be placed in the chain-type PSG cleaning machine, so that the front of the silicon substrate contacts the texturing liquid in the cleaning machine, and at the same time, the back is protected by spraying water to ensure that the hydrofluoric acid cleaning solution only etches the PSG on the front of the silicon substrate. , forming a suede structure on the front to ensure a smooth structure on the back.
  • the front side of the P-type silicon substrate is textured to form a textured structure, including:
  • the P-type silicon substrate is immersed in the texturing liquid for texturing; wherein, the texturing liquid includes KOH solution, and the mass concentration of the KOH solution is 0.5%-1.5%; the temperature of the texturing liquid is 77°C-83°C, and the P-type silicon
  • the time for the substrate to be immersed in the texturing solution is 495s-505s.
  • the suede liquid also includes some additives, the additives include surfactants, nucleating agents, dispersants, catalysts and defoamers, for example, the manufacturer is Shichuang TS53 additives .
  • the temperature of the texturing liquid can be 77°C, 78°C, 80°C, 81°C, 83°C
  • the time for the P-type silicon substrate to be immersed in the texturing liquid can be 495s, 497s, 499s, 501s, 503s, 505s.
  • the temperature and time disclosed in this embodiment are beneficial to ensure the formation of a suitable suede structure on the front side without etching the back side.
  • the conditions are mild and easy to implement.
  • the front surface of the P-type silicon substrate is textured to form a textured structure, wherein the reflectance of the textured structure is 8.7%-9.3%.
  • before printing the front electrode on the front side of the P-type silicon substrate including:
  • the area on the front side of the P-type silicon substrate where the front electrode needs to be provided is subjected to laser treatment to open the second passivation layer.
  • the second passivation layer is opened by laser to facilitate the printing of the front electrode and ensure the contact between the front electrode and the silicon substrate.
  • the front electrode is printed on the front surface of the P-type silicon substrate, wherein the paste for the front electrode is aluminum paste.
  • the aluminum paste replaces the traditional silver-aluminum paste, which has low cost and further reduces the battery manufacturing cost.
  • the first step is to place the P-type silicon substrate in a cleaning machine filled with polishing liquid for polishing.
  • the side length of the P-type silicon substrate is 182mm, the thickness is 175um, and the chamfer is 247mm.
  • the polishing liquid includes water, KOH and additives. Additives For Topband BP51, the temperature of the polishing treatment is 55°C, the time is 220s, the weighing before and after polishing shows that the etching amount is about 0.2g, and the reflectivity of the front and back of the silicon substrate is about 41%;
  • the second step is to sequentially deposit a tunneling silicon oxide layer and a polysilicon layer on the back of the P-type silicon substrate in a low-pressure chemical vapor deposition furnace; wherein, the thickness of the tunneling silicon oxide layer is 1.5nm, and the thickness of the P polysilicon layer is 120nm;
  • the silicon substrate is placed in a phosphorus diffusion furnace to perform phosphorus doping on the polysilicon layer to obtain a phosphorus-doped polysilicon layer;
  • Step 4 Use hydrofluoric acid with a mass concentration of 10% in the chain-type PSG removal machine at room temperature, so that the front side of the silicon substrate enters the hydrofluoric acid, spray water on the back side, and remove the front PSG layer;
  • the amount of substrate etching is about 0.6g, after testing, the reflectivity of the front is about 9%;
  • the sixth step is to deposit aluminum oxide and silicon nitride layers on the front side of the P-type silicon substrate after texturing to form a second passivation layer;
  • Step 7 depositing a silicon nitride layer on the phosphorus-doped polysilicon layer to form a first passivation layer;
  • the eighth step is to perform laser treatment on the front side of the P-type silicon substrate to open the second passivation layer;
  • Step 9 Open the second passivation layer on the front of the P-type silicon substrate and the back of the P-type silicon substrate by screen printing and sintering aluminum electrodes and silver electrodes respectively, and test sorting.
  • Example 1 After testing, the battery prepared in Example 1 was compared with the conventional Perc battery, and the results are shown in Table 1:
  • Eta represents conversion efficiency
  • Isc short circuit current
  • Uoc represents open circuit voltage
  • FF fill factor
  • the battery prepared by the method of the embodiment of the present application is superior to the existing Perc battery in terms of conversion efficiency, short-circuit current, open-circuit voltage and fill factor, further illustrating the preparation method of the embodiment of the present application
  • the prepared battery can effectively improve the performance of the existing Perc battery, break through the efficiency bottleneck of the Perc battery, and is expected to replace the Perc battery.
  • the invention provides a solar cell and a preparation method thereof.
  • the method includes:
  • the N-type silicon wafer containing boron diffusion on one side can be obtained by performing double-sided texturing and boron diffusion treatment on the N-type bare silicon wafer, and removing the BSG layer on the back side.
  • double-sided texturing on the N-type bare silicon wafer
  • a pyramid-shaped textured structure can be formed on the surface of the silicon substrate.
  • boron diffusion treatment is performed on the silicon wafer after texturing
  • a BSG layer can be formed on the surface of the silicon wafer. Before polishing, only the BSG layer on the backside of the silicon wafer can be removed, and the BSG layer on the front side of the silicon wafer can be retained.
  • process conditions used for double-sided texturing, boron diffusion treatment, and removal of the BSG layer on the back of the silicon wafer for the N-type bare silicon wafer are not particularly limited, and those skilled in the art can choose according to actual needs.
  • the N-type bare silicon wafer can be put into a tank-type texturing cleaning machine for alkali texturing treatment, wherein the texturing liquid can include alkali and texturing additives, and the alkali and texturing additives in the texturing liquid
  • the kind of velvet additive is not particularly limited, and those skilled in the art can select according to actual needs, for example, alkali can be KOH and/or NaOH, and the concentration of alkali can be about 1wt%, and velvet additive can be conventional in this field.
  • the temperature of the texturing liquid can be 80°C ⁇ 3°C
  • the time of texturing treatment can be 500s ⁇ 15s.
  • the double-sided textured silicon wafer can be placed in a boron diffusion furnace tube for boron diffusion treatment, wherein the boron diffusion temperature can be 950°C ⁇ 50°C, wherein the boron diffusion can be made
  • the square resistance of the processed silicon wafer reaches 120 ⁇ /sq ⁇ 20 ⁇ /sq, which is more conducive to combining with the subsequent process to make the final battery sheet have an ideal square resistance value.
  • the silicon wafer obtained by boron diffusion treatment can be treated with hydrofluoric acid so as to remove the BSG layer on the back of the silicon wafer.
  • the silicon wafer obtained by boron diffusion treatment can be placed in a chain In the type BSG cleaning machine, hydrofluoric acid with a concentration of 40 ⁇ 5wt% is used to remove the BSG layer on the back of the silicon wafer, and the controlled process temperature can be about 20°C, thereby ensuring that the BSG layer on the back of the silicon wafer can be cleaned. Effective removal.
  • the silicon wafer With the side of the silicon wafer facing away from the boron diffusion as the back, the silicon wafer is subjected to back polishing treatment to form a square shape of expected size on the back of the silicon wafer
  • the inventors have found that the passivation film on the back of the silicon wafer is more densely deposited on a larger square and flat silicon substrate, and the passivation effect is better.
  • the silicon wafer The size of the alkali throwing square on the back side cannot be too large, and it can only be controlled at about 5 ⁇ m at present.
  • the main purpose of the present invention is to break the limitation of the size of the alkali throwing square on the back side of the silicon wafer to the contact performance of the metal on the back of the battery. Purpose, the inventor imagined that the structure of the non-metal contact area on the back of the battery (i.e.
  • the area where the back of the silicon wafer is not in contact with the electrodes) and the structure of the metal contact area i.e. the area where the back of the silicon wafer is in contact with the electrodes
  • the square size of the small square structure on the back of the silicon wafer can be increased, thereby improving the passivation effect on the back, and for the metal contact area on the back of the battery, laser slotting (wherein laser opening The groove area is shown as 17 in Figure 3) and the texture process forms a textured pyramid structure in the metal contact area on the back of the silicon wafer, thereby improving the contact effect between the back of the silicon wafer and the electrode, and improving the conductivity, thereby effectively solving the problem of silicon wafer
  • the size of the alkali-polished square on the back side limits the contact performance of the metal on the back of the battery, which can not only improve the passivation effect on the back of the silicon wafer, but also ensure good contact
  • the square size in the square shape formed by the back polishing process, can be 20 ⁇ m ⁇ 2 ⁇ m, for example, it can be 19 ⁇ m, 19.5 ⁇ m, 20 ⁇ m, 20.5 ⁇ m or 21 ⁇ m, etc.
  • the inventors found that if the silicon wafer If the square size on the back side is too small, it is difficult to effectively improve the passivation effect on the back side of the silicon wafer, and if the square size on the back side of the silicon wafer is too large, the amount of etching will be larger, the silicon wafer will become thinner, and the reliability of the battery will be reduced.
  • the reflectivity of the backside of the silicon wafer can reach 42% ⁇ 1%.
  • the smoother, and the larger size of the silicon wafer can also improve the reflectivity of the silicon wafer backside.
  • by controlling the reflectivity of the silicon wafer backside to the above range it can be ensured that a denser passivation film can be formed on the silicon wafer substrate backside. The passivation effect can thus be further ensured.
  • the 182 silicon wafers with a thickness of 170 ⁇ m ⁇ 10 ⁇ m, a side length of 182 mm ⁇ 0.25 mm, and a chamfer diameter of 247 mm ⁇ 0.25 mm are used as a reference (or a thickness of 170 ⁇ m ⁇ 10 ⁇ m 182 chips with a plane area of 330.15cm2 as the reference), the etching amount of the back polishing treatment can be 0.58g ⁇ 0.05g, and the etching amount of the back polishing treatment in the conventional process is about 0.16g, but the inventor It is found that if the etching amount of the back polishing treatment is too small, it is difficult to fully remove the side and back of the battery, and if the etching amount of the back polishing treatment is too large, the silicon wafer will become thinner and the reliability of the battery will be reduced.
  • the reaction time is relatively long, which will reduce production efficiency and increase costs.
  • the present invention by controlling the above-mentioned etching amount range, it can ensure that the side and back of the battery can be completely removed, ensuring better parallel resistance of the battery and preventing leakage. It also ensures the reliability of the battery.
  • the polishing liquid used may include alkali and polishing additives, alkali and polishing additives in the polishing liquid.
  • the kind of polishing additive is not particularly limited, and those skilled in the art can select according to actual needs, for example, alkali can comprise KOH and/or NaOH, and polishing additive can be the polishing additive commonly used in this field, further, the volume concentration of alkali It can be 4v% ⁇ 0.2v%.
  • the temperature of the polishing treatment can be 65°C ⁇ 3°C, and the time can be 400s ⁇ 20s, wherein the backside of the silicon wafer can be polished in a tank cleaning machine.
  • the inventor After a large number of experiments and verifications, it is found that based on the 182 chip with a thickness of 170 ⁇ m ⁇ 10 ⁇ m and a silicon wafer plane area of 330.15cm 2 , by controlling the above polishing conditions, it is more conducive to obtaining a back surface with a size of 20 ⁇ m ⁇ 2 ⁇ m and a back reflectivity.
  • the etching amount is 0.58g ⁇ 0.05g, which is not only more conducive to the better passivation effect of the non-metallic area on the back of the final cell, but also ensures a higher A good battery is connected in parallel to prevent leakage.
  • a layer of SiOx can be deposited on the back of the battery in an atmospheric pressure chemical vapor deposition device (APCVD), specifically a silicon dioxide layer, wherein the thickness of the silicon oxide layer can be 90-150 nm , for example, can be 95nm, 100nm, 105nm, 115nm, 125nm, 135nm or 145nm, etc.
  • APCVD atmospheric pressure chemical vapor deposition device
  • the alkali in the texturing solution cannot effectively prevent the damage to the silicon matrix, and if the thickness of the silicon oxide compound layer is too large, it will not only affect the production efficiency but also lead to waste of raw materials, and will also increase the subsequent laser grooving. Difficulty, in the present invention, by controlling the thickness of the silicon oxide compound layer to the above range, it can not only protect the silicon substrate better, but also help to improve the production efficiency of the entire production process.
  • Partial laser grooving is performed on the silicon oxide compound layer to remove the silicon oxide compound layer at the grooved part and burn the underlying silicon to form an inverted pyramid structure
  • the silicon oxide compound layer (SiOx layer) on the battery backside can be laser-grooved on the ultraviolet laser (the laser region is shown as 17 in Fig. 3), and the pattern of groove here is the same as that in the subsequent silicon oxide layer.
  • the pattern of metal fine grid lines formed on the back of the chip is consistent.
  • the laser burns the underlying silicon at the same time to form an inverted pyramid structure.
  • Mark points are marked on the 4 corners of the battery for the subsequent wire Alignment during screen printing.
  • the metal grid line formed on the back of the silicon wafer is set at the position corresponding to the groove pattern, and the silicon oxide compound layer on the back of the battery is laser grooved to expose the silicon substrate and form an inverted pyramid structure.
  • the silicon substrate contacts the metal paste through an inverted pyramid structure, the mutual contact area is larger, the contact resistance is smaller, and the series resistance is correspondingly smaller, which can further improve the conductive effect. Therefore, even if the non-metallic contact on the back of the battery has a larger size of the alkali-polished square, it can ensure a good contact effect between the silicon substrate and the electrode, and improve the conductivity.
  • the power of laser grooving can be 20W ⁇ 5W, and the frequency can be 40000Hz ⁇ 2000Hz.
  • the inventors found that if the laser power is too small or the frequency is too low, it is difficult to achieve better laser grooving effect and the burning effect on the lower silicon, and if the laser power is too high or the frequency is too high, it is difficult to control the laser level, which is not conducive to the formation of the expected pyramid structure.
  • by controlling the above laser conditions it can be ensured that the silicon wafer
  • the metal contact area on the back forms a better inverted pyramid structure, which is more conducive to improving the contact effect between the back of the silicon wafer and the electrode, and improving conductivity.
  • step (4) Carry out backside etching treatment to the silicon wafer that step (4) obtains, and remove the silicon oxide compound layer of non-laser region;
  • the main purpose of carrying out the backside etching treatment on the silicon wafer is to eliminate the damaged layer formed by laser ablation in the previous step, and modify the inverted pyramid structure at the same time.
  • the SiOx layer in the non-laser area can be removed by hydrofluoric acid .
  • silicon wafers can be put into a tank-type texturing cleaning machine for backside corrosion treatment, wherein the corrosion solution can include alkali and corrosion additives, and the types of alkali and corrosion additives in the corrosion solution are not subject to special restrictions.
  • the alkali can be KOH and/or NaOH
  • the volume concentration of the alkali can be 1v% ⁇ 0.2v%
  • the corrosion additive can be the conventional corrosion additive in this field
  • the corrosion solution The temperature can be 80°C ⁇ 3°C
  • the corrosion treatment time can be 120s ⁇ 10s.
  • the deposition of the back tunneling oxide layer (SiO2) and the polysilicon (Poly) layer can be carried out in a low pressure chemical vapor deposition furnace (LPCVD), wherein the thicknesses of the tunneling oxide layer and the polysilicon layer are not affected by Especially limited, those skilled in the art can choose according to actual needs, for example, the thickness of the tunnel oxide layer can be about 1.5nm, and the thickness of the polysilicon layer can be about 120nm.
  • LPCVD low pressure chemical vapor deposition furnace
  • the method for preparing an N-type TopCon cell can further include: (7) taking the side of the silicon wafer with boron diffusion as the front side, implanting phosphorus into the polysilicon layer on the back side of the silicon wafer to form a passivation
  • the contact structure wherein this step can be carried out in the rear phosphorus diffusion furnace, by preparing an ultra-thin tunnel oxide layer and a thin layer of phosphorus-doped polysilicon on the back of the battery to form a passivation contact structure, which can be a silicon wafer
  • the backside provides good surface passivation, and the ultra-thin oxide layer can allow the multi-carrier electrons to tunnel into the polysilicon layer while blocking the recombination of the minority carrier-holes, and then the electrons are transported laterally in the polysilicon layer and collected by the metal, which can greatly reduce the metal contact recombination current , to increase the open circuit voltage and short circuit current of the battery.
  • the method for preparing N-type TopCon cells may further include: removing the polysilicon layer on the front side of the silicon wafer, specifically, a polishing solution may be used in a tank cleaning machine, wherein the polishing solution may include KOH And polishing additive, the concentration of KOH in the polishing liquid can be 4wt% effect, and polishing additive can be the polishing additive conventional in this field, and polishing temperature can be 66 °C ⁇ 3 °C, and process time can be 200s ⁇ 20s, by controlling this condition can Effectively remove the polysilicon layer on the front side of the silicon wafer.
  • a polishing solution may include KOH And polishing additive
  • the concentration of KOH in the polishing liquid can be 4wt% effect
  • polishing additive can be the polishing additive conventional in this field
  • polishing temperature can be 66 °C ⁇ 3 °C
  • process time can be 200s ⁇ 20s
  • the method for preparing an N-type TopCon battery sheet may further include: (8) depositing an aluminum oxide layer and a silicon nitride layer in sequence on the front side of the silicon wafer to form a front passivation layer; (9) Depositing a silicon nitride layer on the back of the silicon wafer to form a back passivation layer; (10) printing electrode paste on the front and back of the silicon wafer and sintering to obtain a battery sheet.
  • the method for preparing an N-type TopCon battery sheet deposits a silicon oxide compound layer on the backside of the silicon wafer after the back polishing treatment, and performs laser grooving on the silicon oxide compound layer and grooves the silicon oxide compound layer.
  • Burning the silicon in the lower layer can form an inverted pyramid structure on the surface of the silicon wafer, and then further texturing can remove the damaged surface caused by laser burning and modify the inverted pyramid structure.
  • the modified texture can be used
  • the pyramid structure is in contact with the metal electrode on the back, which increases the contact effect between the back of the silicon wafer and the metal electrode, improves conductivity, and allows a larger square size in the non-contact area, thereby achieving a better passivation effect.
  • this preparation process has at least the following advantages: 1. When polishing the back of the silicon wafer, a larger square shape can be formed on the back of the silicon wafer, for example, the size of the square can reach about 20 ⁇ m, compared with the existing back polishing.
  • the present invention can form a larger square size topography, and then make the passivation film deposited on a larger square, flat silicon substrate more dense, and the passivation effect is better;
  • the back of the silicon wafer When forming a larger square shape, the amount of etching controlled by the back polishing is also larger than that of the conventional process, which can ensure that the side and back of the battery are completely removed, ensuring better parallel resistance of the battery and preventing Leakage; 3.
  • the metallized area on the back of the silicon wafer that is, the area in contact with the back electrode
  • the silicon substrate contacts the metal paste through an inverted pyramid structure, and the mutual contact area is larger, so that the contact resistance is smaller and the series resistance is correspondingly smaller. 4.
  • the battery prepared by this method is compatible with the performance of good contact between the back passivation and the back metal paste and the silicon substrate, the resistance is lower, and the open circuit voltage, fill factor and conversion efficiency of the battery are all consistent.
  • the series resistance can be reduced by 1.5m ⁇ or more
  • the open circuit voltage can be increased by 5mV or more
  • the fill factor can be increased by 0.4% or more
  • the conversion efficiency of the battery can be increased by 0.3% or more.
  • an N-type TOPCon cell prepared by the method for preparing an N-type TopCon cell.
  • an N-type TOPCon cell can include an N-type monocrystalline silicon substrate 10, a front electrode 11 (such as an Ag/Al electrode) and a back electrode 12 (such as an Ag electrode) , wherein, the front side of the N-type single crystal silicon substrate 10 has a P+ doped layer 13, the front electrode 11 is in direct contact with the P+ doped layer 13, the area where the P+ doped layer 13 contacts the front electrode 11 has a textured pyramid structure, and the P+ doped
  • the area of the impurity layer 13 that is not in contact with the front electrode 11 is covered with a front passivation layer 14, wherein the front passivation layer 14 is sequentially formed with an aluminum oxide layer and a silicon nitride layer in a direction away from the front surface of the single crystal silicon substrate 10, and the
  • the square size in the square shape is 20 ⁇ m ⁇ 2 ⁇ m, and the square shape is covered with back passivation.
  • Layer 16 wherein the rear passivation layer 16 is formed in sequence with a polysilicon doped layer and a silicon nitride layer in a direction away from the rear surface of the single crystal silicon substrate 10.
  • the N-type TopCon battery has a larger square shape and better passivation effect, and the part of the back of the battery that is in contact with the back electrode is an inverted pyramid textured structure, which has a better contact effect with the electrode and conducts electricity.
  • the first step of the process is to put the N-type bare silicon wafer into the tank-type texturing cleaning machine for alkali texturing process.
  • the solution is 1 ⁇ 0.2v% concentration of KOH+texturing additive solution, and the solution temperature is 80°C ⁇ 3°C , the process time is 500s ⁇ 15s, the etching amount is 0.58 ⁇ 0.05g, and the reflectivity is 9 ⁇ 0.5%;
  • the cells after texturing are subjected to a boron diffusion process in a boron diffusion furnace tube, with a square resistance of 120 ⁇ 20 ⁇ /sq and a process temperature of 950 ⁇ 50°C;
  • the third step is to remove the back BSG layer in the chain type BSG cleaning machine, the solution is hydrofluoric acid with a concentration of 40 ⁇ 5wt%, and the process temperature is 20 ⁇ 3°C;
  • the fourth step is to carry out alkali polishing on the back side in a tank cleaning machine.
  • the solution is 4 ⁇ 0.2v% volume concentration of KOH+polishing additive, the solution temperature is 65 ⁇ 3°C, the process time is 400 ⁇ 20s, and the size of the back surface is 20 ⁇ m ⁇ 2 ⁇ m square, the back reflectivity is 42 ⁇ 1%;
  • the fifth step is to deposit a layer of SiOx on the back of the battery in the atmospheric pressure chemical vapor deposition equipment (APCVD), with a film thickness of 100 ⁇ 10nm;
  • APCVD atmospheric pressure chemical vapor deposition equipment
  • the sixth step is to laser groove the SiOx layer on the back of the battery on the ultraviolet laser.
  • the laser power is 20W and the frequency is 40000Hz.
  • the pattern of the groove here is consistent with the pattern of the metal fine grid line on the back.
  • the laser burns the lower layer of silicon at the same time to form an inverted pyramid structure, and finally mark points on the four corners of the battery for alignment during subsequent screen printing;
  • the seventh step is to carry out alkali corrosion in the tank cleaning machine.
  • the solution is KOH+corrosion additive with a concentration of 1 ⁇ 0.2v% (volume ratio), the solution temperature is 80 ⁇ 3°C, and the process time is 120 ⁇ 10s.
  • the main purpose is to eliminate the above The damaged layer formed by the first step of laser ablation, while modifying the inverted pyramid structure, and finally remove the SiOx film in the non-laser area in the hydrofluoric acid tank behind;
  • the eighth step is to deposit the back tunneling oxide layer (SiO2) and polysilicon (Poly) layer in a low-pressure chemical vapor deposition furnace (LPCVD).
  • the thickness of the tunneling oxide layer is 1.5 ⁇ 0.2nm, and the thickness of Poly is 120 ⁇ 20nm;
  • phosphorus diffusion furnace on the back injects phosphorus into the Poly layer on the back to form a passivation contact structure
  • the tenth step is to remove the front side winding Poly layer in the tank cleaning machine, the solution is 4 ⁇ 0.2v% (volume ratio) concentration of KOH+polishing additive, the temperature is 66 ⁇ 3°C, and the process time is 200 ⁇ 20s;
  • the eleventh step is AlOx+SiNx on the front and SiNx passivation film coating on the back;
  • the first step of the process is to put the N-type bare silicon wafer into the tank-type texturing cleaning machine for alkali texturing process.
  • the solution is 1 ⁇ 0.2v% (volume ratio) concentration of KOH+texturing additive solution, and the solution temperature is 80 ⁇ 3°C, process time 500 ⁇ 15s, etching amount 0.58 ⁇ 0.05g, reflectivity 9 ⁇ 0.5%;
  • the cells after texturing are subjected to a boron diffusion process in a boron diffusion furnace tube, with a square resistance of 120 ⁇ 20 ⁇ /sq and a process temperature of 950 ⁇ 50°C;
  • the third step is to remove the back BSG layer in the chain type BSG cleaning machine, the solution is hydrofluoric acid with a concentration of 40 ⁇ 5wt%, and the process temperature is 20 ⁇ 3°C;
  • the fourth step is to carry out alkali polishing on the back in the tank cleaning machine.
  • the solution is 4 ⁇ 0.2v% concentration of KOH+polishing additive, the solution temperature is 65 ⁇ 3°C, the process time is 160 ⁇ 10s, and the size of the back surface is 5 ⁇ 0.5 ⁇ m square, the back reflectivity is 40 ⁇ 1%;
  • the fifth step is to deposit the back tunneling oxide layer (SiO2) and polysilicon (Poly) layer in a low-pressure chemical vapor deposition furnace (LPCVD).
  • the thickness of the tunneling oxide layer is 1.5 ⁇ 0.2nm, and the thickness of Poly is 120 ⁇ 20nm;
  • phosphorus diffusion furnace on the back injects phosphorus into the Poly layer on the back to form a passivation contact structure
  • the seventh step is to remove the front side winding Poly layer in the tank cleaning machine, the solution is 4 ⁇ 0.2v% (volume ratio)% KOH+polishing additive, the temperature is 66 ⁇ 3°C, and the process time is 200 ⁇ 20s;
  • the eighth step is AlOx+SiNx on the front and SiNx passivation film coating on the back;
  • the fourth step is to carry out alkali polishing on the back in the tank cleaning machine.
  • the solution is KOH+polishing additive with a concentration of 4 ⁇ 0.2v% (volume ratio), the solution temperature is 65 ⁇ 3°C, the process time is 800 ⁇ 20s, and the back surface is A square with a size of 40 ⁇ 2 ⁇ m, the reflectivity of the back is 43 ⁇ 1%;
  • the fourth step is to carry out alkali polishing on the back in a tank cleaning machine.
  • the solution is KOH+polishing additive with a concentration of 4 ⁇ 0.2v% (volume ratio) wt%, the solution temperature is 65 ⁇ 3°C, and the process time is 600 ⁇ 20s. Appearance is a square with a size of 30 ⁇ 2 ⁇ m, and the reflectivity of the back is 42.5 ⁇ 1%;
  • the fifth step is to deposit a layer of SiOx on the back of the battery in the atmospheric pressure chemical vapor deposition equipment (APCVD), with a film thickness of 100 ⁇ 10nm;
  • APCVD atmospheric pressure chemical vapor deposition equipment
  • the sixth step is to laser groove the SiOx layer on the back of the battery on the ultraviolet laser.
  • the laser power is 20W and the frequency is 40000Hz.
  • the pattern of the groove here is consistent with the pattern of the metal fine grid line on the back.
  • the laser burns the lower layer of silicon at the same time to form an inverted pyramid structure, and finally mark points on the four corners of the battery for alignment during subsequent screen printing;
  • the seventh step is to carry out alkali corrosion in the tank cleaning machine.
  • the solution is KOH+corrosion additive with a concentration of 1 ⁇ 0.2v% (volume ratio), the solution temperature is 80 ⁇ 3°C, and the process time is 120 ⁇ 10s.
  • the main purpose is to eliminate the above The damaged layer formed by the first step of laser ablation, while modifying the inverted pyramid structure, and finally remove the SiOx film in the non-laser area in the subsequent hydrofluoric acid tank.
  • Example 1 100 24.54 723 41.33 82.12 Comparative example 1 100 24.22 716 41.31 81.90 Comparative example 2 100 24.52 722 41.35 82.13 Example 2 100 24.47 721 41.34 82.10
  • Example 2 and The silicon wafer in the solar cell prepared in Comparative Example 2 is relatively thinner, the limit load that the solar cell can carry is also smaller, and the risk of the solar cell is greater.
  • the device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without any creative efforts.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware.
  • the use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

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Abstract

La présente invention concerne une cellule solaire et son procédé de préparation. La cellule solaire comprend un substrat de silicium de type P ayant une surface avant et une surface arrière. La surface arrière présente une structure lisse, et est fournie de manière séquentielle, de haut en bas, avec une couche d'oxyde de silicium à effet tunnel, une couche de polysilicium dopée au phosphore, une première couche de passivation et des électrodes arrière, les électrodes arrière étant en contact avec la couche de polysilicium dopée au phosphore. La surface avant est d'une structure texturée, et est fournie de manière séquentielle, de bas en haut, avec des secondes couches de passivation et des électrodes avant, les électrodes avant étant en contact avec le substrat de silicium de type P, et des couches P+ étant formées dans des zones où les électrodes avant sont en contact avec le substrat de silicium de type P. La structure de cellule solaire selon la présente invention présente une tension de circuit ouvert élevée et une efficacité de batterie élevée, est simple à traiter, et est ainsi appropriée pour une production de masse à grande échelle.
PCT/CN2022/093351 2021-11-08 2022-05-17 Cellule solaire et son procédé de préparation WO2023077772A1 (fr)

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CN117577708A (zh) * 2024-01-17 2024-02-20 金阳(泉州)新能源科技有限公司 基于p型硅片的联合钝化背接触电池及其制备和光伏组件

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CN116799091B (zh) * 2023-06-16 2024-02-20 扬州大学 一种基于Poly finger的叠层p型钝化接触结构及其制备方法
CN117040401A (zh) * 2023-08-22 2023-11-10 苏州赛福天新能源技术有限公司 一种perc高效电池片及电池片良率改善工艺
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CN117577708A (zh) * 2024-01-17 2024-02-20 金阳(泉州)新能源科技有限公司 基于p型硅片的联合钝化背接触电池及其制备和光伏组件
CN117577708B (zh) * 2024-01-17 2024-04-16 金阳(泉州)新能源科技有限公司 基于p型硅片的联合钝化背接触电池及其制备和光伏组件

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