WO2023077611A1 - 一种检测感应放大器失配的系统和方法 - Google Patents

一种检测感应放大器失配的系统和方法 Download PDF

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Publication number
WO2023077611A1
WO2023077611A1 PCT/CN2021/136583 CN2021136583W WO2023077611A1 WO 2023077611 A1 WO2023077611 A1 WO 2023077611A1 CN 2021136583 W CN2021136583 W CN 2021136583W WO 2023077611 A1 WO2023077611 A1 WO 2023077611A1
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Prior art keywords
bit line
voltage difference
test data
preset
sense amplifier
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PCT/CN2021/136583
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English (en)
French (fr)
Inventor
刘�东
第五天昊
楚西坤
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/664,058 priority Critical patent/US11862233B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Definitions

  • This application relates to the field of semiconductors, in particular to the field of DRAM (Dynamic Random Access Memory, Dynamic Random Access Memory).
  • DRAM Dynamic Random Access Memory
  • the sense amplifier is used to amplify the weak voltage difference between the bit line and the reference bit line, so that the logic data in the memory cell can be correctly identified.
  • the sense amplifiers produced have insufficient anti-interference ability, and the MOS tube is not turned on at the correct time when the sense amplifier is working, resulting in the sense amplifier flipping abnormally and reading failure.
  • the traditional method for testing the sense amplifier is to perform write and read operations on the storage unit while shortening the precharge time, and judge whether the sense amplifier is mismatched by comparing the output results. Because the pre-charging time of the existing traditional method is relatively loose, and the working environment of the induction amplifier is not bad enough, so some potential failures of the induction amplifier are not easy to be exposed, and the detection effect cannot meet expectations.
  • an embodiment of the present application provides a method for detecting sense amplifier mismatch, including:
  • test data set is converted into the first voltage difference between the bit line and the reference bit line, and input to the sense amplifier that delays the opening of the PMOS transistor or the NMOS transistor for precharging for a preset time, and the preset time is shorter than the standard pre-charge time;
  • the voltage difference to be measured is compared with the preset voltage difference to be measured, and if the voltage difference to be measured is in the same direction as the preset voltage difference to be measured, it is determined that the sense amplifier is mismatched.
  • before the acquisition of the test data set it also includes:
  • Obtaining a preset test data set converting the preset test data set into a third voltage difference between the bit line and the reference bit line, inputting it into the sense amplifier with the MOS transistor normally turned on for a standard precharge time pre-charging, amplifying the fourth voltage difference between the bit line obtained after pre-charging and the reference bit line through the sense amplifier to obtain the preset voltage difference to be measured.
  • the preset test data set and the data written in the test data set corresponding to the position of the bit line are reversed.
  • the converting the test data set into a first voltage difference between a bit line and a reference bit line includes:
  • test data set is written into the memory unit to be tested, and the test data set is converted into the first voltage difference between the bit line and the reference bit line through the memory unit to be tested.
  • test data set is written into the memory unit under test, and the test data set is converted into the first bit line between the bit line and the reference bit line through the memory unit under test.
  • a voltage difference comprising:
  • the test data group is sequentially written into the storage unit to be tested according to a preset interval
  • the data between the bit line and the reference bit line is read from the storage unit to be tested according to the test data group.
  • first voltage difference After the test data group is sequentially written into the storage unit to be tested according to a preset interval, the data between the bit line and the reference bit line is read from the storage unit to be tested according to the test data group.
  • writing the test data group into the storage unit to be tested sequentially according to a preset interval includes:
  • reading the first voltage difference between the bit line and the reference bit line from the memory cell under test according to the test data set includes:
  • the converting the preset test data set into the third voltage difference between the bit line and the reference bit line includes:
  • the preset test data set is written into the memory unit to be tested, and the preset test data set is converted into the third voltage difference between the bit line and the reference bit line through the memory unit to be tested.
  • the preset test data set is written into the memory unit to be tested, and the preset test data set is converted into the data between the bit line and the reference bit line through the memory unit to be tested.
  • the third voltage difference includes:
  • the bit line and the bit line are read from the storage unit under test according to the preset test data group.
  • sequentially writing the preset test data groups into the storage unit to be tested according to preset intervals includes:
  • the first voltage difference is input into the sense amplifier that delays the opening of the PMOS transistor or the NMOS transistor for precharging for a preset time, and the second voltage difference obtained after precharging is amplified by the sense amplifier, Obtain the voltage difference to be measured, including:
  • the inductive amplifier circuit amplifies to obtain the voltage difference to be measured, wherein the first NMOS transistor and the first PMOS transistor, and the second NMOS transistor and the second PMOS transistor in the inductive amplifier circuit of the inductive amplifier respectively constitute a CMOS inverter .
  • the embodiment of the present application also provides a system for detecting sense amplifier mismatch, including:
  • a data acquisition module configured to acquire a test data set
  • the data conversion module is used to convert the test data group into the first voltage difference between the bit line and the reference bit line, and input it to the inductive amplifier that delays the opening of the PMOS transistor or the NMOS transistor for precharging for a preset time.
  • the preset time is shorter than the standard precharge time, and is used to amplify the second voltage difference between the bit line obtained after precharging and the reference bit line through a sense amplifier to obtain a voltage difference to be measured;
  • a mismatch detection module configured to compare the voltage difference to be measured with a preset voltage difference to be measured, and if the voltage difference to be measured is in the same direction as the preset voltage difference to be measured, then judge the lost pair.
  • the data acquisition module is also used to acquire a preset test data set before acquiring the test data set.
  • the method for detecting the mismatch of the sense amplifier in the embodiment of the present application adopts the method of turning on the PMOS transistor or the NMOS transistor in the delay sense amplifier to speed up the test of the failed storage particles.
  • the Y-Page Write method executes the write operation on the basis of delaying the opening of the transistor, by turning on a word line, and after writing all the memory cells corresponding to the word line in sequence, turn off the word line, and then turn on the next word line Lines are written sequentially until all memory cells are written.
  • the X-Fast Read method is to sequentially turn on all word lines on the same bit line when performing a read operation, turn on a word line and sequentially read the content of a burst length (8bit) unit on this word line, and then turn off This word line, and then turn on the next word line to read sequentially until all the contents on the memory cells are read.
  • Write a data topology according to the Y-Page method based on the NMOS transistor or PMOS transistor of the delay sense amplifier and then read this data topology according to the X-Fast method under the premise of shortening the tRP time.
  • FIG. 1 is a working circuit diagram of an inductive amplifier in an optional embodiment of a method for detecting inductive amplifier mismatch provided by the present application;
  • FIG. 2 is a schematic flowchart of an optional embodiment of a method for detecting sense amplifier mismatch provided by the present application
  • FIG. 3 is a test data topology diagram of an optional embodiment of a method for detecting sense amplifier mismatch provided by the present application
  • FIG. 4 is a complete waveform diagram of an optional embodiment of a method for detecting sense amplifier mismatch provided by the present application
  • FIG. 5 is a waveform diagram of an inductive amplifier normally operating in an amplification stage in an optional embodiment of a method for detecting inductive amplifier mismatch provided by the present application;
  • Fig. 6 is a waveform diagram of working in the amplification stage when shortening tRP and PMOS tube delay opening in the sense amplifier of an optional embodiment of a method for detecting sense amplifier mismatch provided by the present application;
  • FIG. 7 is a flowchart of an optional embodiment of a method for detecting sense amplifier mismatch provided by the present application.
  • FIG. 8 is a schematic structural diagram of an optional embodiment of a system for detecting sense amplifier mismatch provided in the present application.
  • First NMOS tube 1. First NMOS tube; 2. Second NMOS tube; 3. First PMOS tube; 4. Second PMOS tube; 5. Induction amplifier circuit; 6. Pre-charging circuit; 7. Storage unit; 81. Data acquisition module ; 82. Data conversion module; 83. Mismatch detection module.
  • first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.
  • FIG. 1 it is a working circuit diagram of a sense amplifier in an alternative embodiment of a method for sensing amplifier mismatch provided in the present application.
  • the sense amplifier includes a sense amplifier circuit 5 , a precharge circuit 6 and a storage unit 7 .
  • the induction amplifier circuit 5 is composed of a first NMOS (Negative channel-Metal-Oxide-Semiconductor) tube 1, a second NMOS tube 2, a first PMOS tube (positive channel-Metal Oxide-Semiconductor) 3, a second PMOS tube 4, and a PCS power supply and NCS power supply. Both the drain of the first PMOS transistor 3 and the gate of the second PMOS transistor 4 are connected to the bit line BL, and the gate of the first PMOS transistor 3 and the drain of the second PMOS transistor 4 are both connected to the reference bit line /BL , the sources of the first PMOS transistor 3 and the second PMOS transistor 4 are both connected to the PCS power supply.
  • NMOS Negative channel-Metal-Oxide-Semiconductor
  • Both the gate of the first NMOS transistor 1 and the drain of the second NMOS transistor 2 are connected to the bit line BL, and the drain of the first NMOS transistor 1 and the gate of the second NMOS transistor 2 are both connected to the reference bit line /BL.
  • the sources of the first NMOS transistor 1 and the second NMOS transistor 2 are both connected to the NCS power supply.
  • the sense amplifier circuit 5 is composed of the first NMOS transistor 1, the second NMOS transistor 2, the first PMOS transistor 3, and the second PMOS transistor 4, wherein the first NMOS transistor 1 and the first NMOS transistor 1 are cross-coupled.
  • the PMOS transistor 3 , and the second NMOS transistor 2 and the second PMOS transistor 4 respectively constitute a CMOS inverter.
  • the PCS power supply is used to connect the source of the first PMOS transistor 3 to the power supply voltage VDD in response to the pull-up control signal.
  • the NCS power supply is used to ground the source of the first NMOS transistor 1 in response to the pull-down control signal.
  • the NCS power supply is turned on, the PCS power supply is turned on, and the first NMOS transistor 1, the second NMOS transistor 2, and the first PMOS transistor 3 .
  • the second PMOS transistor 4 forms two cross-coupled inverter positive feedback circuits, quickly amplifies the voltage difference between the bit line BL and the reference bit line /BL, and completes the induction amplifier circuit 5 pairing the bit line BL and the reference bit line /BL Amplification of the voltage difference between BL.
  • the PCS power supply may include a pull-up PMOS transistor, and the NCS power supply may include a pull-down NMOS transistor.
  • the PCS power supply can also be implemented using NMOS transistors, and the NCS power supply can also be implemented using PMOS transistors, and the PCS power supply or NCS power supply can contain more than one device, and can also include multiple devices that are turned on or off by different control signals , this application does not limit it.
  • the pre-charging circuit 6 is composed of three NMOS transistors, which are connected with the two output terminals of the sense amplifier circuit 5 .
  • the control terminal of the pre-charging circuit 6 receives the equalization control signal EQ.
  • the precharge circuit 6 can precharge the bit line BL, the reference bit line /BL and the two output terminal lines of the sense amplifier circuit 5 under the control of the equalization control signal EQ, and can charge the bit line BL and the reference bit line /BL BL is charged to the specified precharge voltage VBLP.
  • the pre-charging circuit 6 provided in this exemplary embodiment may also be any other replacement circuit, which is not specifically limited in this exemplary embodiment.
  • the YS is a column of bit line selection signals, for example, it can be composed of an NMOS transistor, the gate of the NMOS transistor is connected to the bit line selection signal YS, the source is connected to LIO, and YSW is used to control the NMOS Turn-on gate voltage difference.
  • the storage unit 7 includes a drive transistor and a storage capacitor, the gate of the drive transistor is connected to the word line WL, the drain is connected to the bit line BL, and the source is connected to the ground line through the storage capacitor .
  • the stored data is "0".
  • the storage capacitor is charged, it is usually charged to the working voltage VDD, and the stored data is "1".
  • the word line WL controls the turn-on or turn-off of the driving transistor, and then controls the charging and discharging of the storage capacitor, so as to implement data writing or reading.
  • FIG. 2 it is a schematic flowchart of an optional embodiment of a method for detecting sense amplifier mismatch provided by the present application, the method comprising:
  • test data set into the first voltage difference between the bit line and the reference bit line, and input it to the sense amplifier that delays the opening of the PMOS transistor or the NMOS transistor for precharging that lasts for a preset time, the preset time Less than the standard precharge time;
  • step S12 when the sense amplifier turned on by the delayed PMOS transistor or the NMOS transistor in step S12 corresponds to the sense amplifier circuit 5 in FIG.
  • the tubes delay the first NMOS tube 1 and the second NMOS tube 2 at the same time.
  • the preset test data group After obtaining the preset test data group, convert the preset test data group into the third voltage difference between the bit line BL and the reference bit line /BL, and input it into the sense amplifier with the MOS transistor normally turned on for a standard precharge time
  • the pre-charging, the fourth voltage difference obtained after pre-charging is amplified by the induction amplifier circuit 5, and the preset voltage difference to be measured is obtained; the corresponding bit line position where the preset test data group and the test data group are written Data inversion, wherein the MOS transistors refer to the first NMOS transistor 1, the second NMOS transistor 2, the first PMOS transistor 3, and the second PMOS transistor 4 in the sense amplifier circuit 5 of the sense amplifier.
  • FIG. 3 it is the data topology diagram of the test data group written in this embodiment.
  • W4C0_RS, W4C1_RS, W4C2_RS, W4C3_RS can be used as the preset test data group
  • W4C0B_RS, W4C1B_RS, W4C2B_RS, W4C3B_RS can be used as the test data
  • the two groups are interchangeable, but it is necessary to ensure that the preset test data group and the test data group are reversed at the bit line position where the data is written.
  • the data inversion at the position of the bit line is to create worse test conditions when testing the mismatch of the sense amplifier, making it easier to detect the failure of the sense amplifier when the precharge time is tightened.
  • the "0" or “1” stored in the storage unit 7 is represented by the weak voltage difference between the bit line BL and the reference bit line /BL in the storage unit 7, which is the first voltage difference. Due to the small size of the memory cell 7, the driving ability is very weak, and the voltage difference between the bit line BL and the reference bit line /BL is very small. If it is directly sent to the output buffer, it will not be able to recognize "0” or "1” in the memory cell 7. ”, therefore, the voltage difference between the bit line BL and the reference bit line /BL in the memory cell 7 needs to be input into the sense amplifier circuit 5 for amplification.
  • FIG. 4 it is a complete waveform diagram of an optional embodiment of a method for detecting sense amplifier mismatch provided by the present application.
  • the last operation was performed to read "1", and this operation is performed.
  • the operation of reading "1" is taken as an example to describe the change of the voltage difference between the bit line BL and the reference bit line /BL during a complete working process of the sense amplifier, and to observe the complete working process of the sense amplifier.
  • the tRP (Precharge command period) is the precharge time, also known as the row precharge time. After sending the precharge command, it will take a period of time before the RAS (Row Address Strobe, RAS) is allowed to be sent. row address strobe) active command to open a new working row.
  • RAS Row Address Strobe
  • row address strobe active command to open a new working row.
  • the tRCD is a delay from RAS to CAS (Column address strobe, column address strobe).
  • the sense amplifier After the data "1" is read, the sense amplifier also includes a recovery phase during operation.
  • the equalization control signal EQ is turned off, the word line signal is turned on, the PCS power supply and the NCS power supply are turned on, so that the reference bit line /BL is restored to a high level, and the bit line BL is restored to a low level.
  • the bit line BL is at a high level
  • the reference bit line /BL is at a low level
  • the Pre indicates that a precharge operation is started.
  • the sense amplifier circuit 5 is turned off (SAoff does not perform amplification operation)
  • the equalization control signal EQ is turned on, and both the bit line BL and the reference bit line /BL are charged to the precharge voltage VBLP.
  • the sense amplifier circuit 5 is turned on, the equalization control signal EQ is turned off, the word line signal is turned on, and the storage capacitor in the corresponding storage unit 7 is controlled to perform a charging operation.
  • Charge sharing is performed between the charge in the storage capacitor and the charge of the bit line BL. Since the data with a value of "1" is stored in the corresponding storage capacitor during the process, the voltage of the bit line BL rises by about 15-20 millivolts.
  • both the NMOS transistor and the PMOS transistor in the sense amplifier circuit 5 are turned on normally, wherein, the first NMOS transistor 1 and the first PMOS transistor 3, and the second NMOS transistor 2 and the second PMOS transistor 4 constitute CMOS inverters respectively. phase device. Since this operation is performed to read "1", at this time, the CMOS inverter composed of the first NMOS transistor 1 and the first PMOS transistor 3 is mainly used to amplify the voltage difference, thereby completing the data "1" in the memory cell 1. to read.
  • the anti-interference ability of the manufactured sense amplifier is insufficient, and the NMOS transistor or PMOS transistor in the sense amplifier circuit 5 is not turned on at the correct time point when the sense amplifier is working, which causes the sense amplifier to flip abnormally , the read failed.
  • the memory unit 7 when testing the sense amplifier, the memory unit 7 is written and read while the precharge time is shortened, and the output results are compared to determine whether the sense amplifier is mismatched.
  • the pre-charging time of the traditional method card is relatively loose, and the working environment of the induction amplifier is not bad enough, so some potential failures of the induction amplifier are not easy to be exposed, and the detection effect cannot meet expectations.
  • FIG. 5 it is a waveform diagram of the sense amplifier in an optional embodiment of a method for detecting sense amplifier mismatch provided by the present application in normal operation in the amplification stage, and the sense amplifier last time The execution operation is a read "0" operation, and this time the read "1" operation is performed.
  • the data written into the storage unit 7 by the provided preset test data group is “0”, and the data written into the storage unit 7 by the provided test data group is “1”.
  • Writing the preset test data set to the storage unit 7 and then reading it is a pre-operation of writing the test data set to the storage unit 7 and then reading it.
  • the memory cell 7 When performing the last read “0" operation, the memory cell 7 inputs a weak voltage difference between the bit line BL and the reference bit line /BL to the sense amplifier, and at this time, the weak voltage is the third voltage difference.
  • the sense amplifier first enters the precharge stage, and performs precharge on the two bit lines (that is, the bit line BL and the reference bit line /BL) for the standard precharge time, and pulls the voltage of the two bit lines to to the precharge voltage VBLP, at this time the voltage difference between the two bit lines is the fourth voltage difference.
  • the standard pre-charging time is based on the specific factory parameters specified by different companies and different models of products, and no specific regulations are made here.
  • the first NMOS transistor 1 , the first PMOS transistor 3 , the second NMOS transistor 2 , and the second PMOS transistor 4 are normally turned on by the induction amplifier circuit 5 to amplify and output to obtain a preset voltage difference. It can be known from the above embodiments that after the recovery phase of the sense amplifier is over, the reference bit line /BL is restored to a high level, and the bit line BL is restored to a low level.
  • the sense amplifier Since the read "0" operation was performed last time, before the sense amplifier is turned on, the reference bit line /BL is at high level, the bit line BL is at low level, and the voltage difference between the two bit lines is the first voltage difference.
  • the sense amplifier first enters the precharge stage Pre, and precharges the two bit lines for the standard precharge time, and pulls the voltage of the two bit lines to the precharge voltage VBLP. At this time, the voltage between the two bit lines The voltage difference is the second voltage difference.
  • the two pre-charged bit lines enter the induction amplifier circuit 5 as input, enter the first amplification stage, the word line signal is turned on, and the voltage of the bit line BL rises.
  • the first PMOS transistor 3 and The first NMOS transistor 1 is turned on according to a preset time, and the second PMOS transistor 4 and the second NMOS transistor 2 are turned off.
  • the bit line BL is at a relatively high level at this time, and due to the effect of the inverter, the voltage at the output terminal of the inverter continuously decreases in the first amplification stage , that is, the voltage of the reference bit line /BL keeps decreasing.
  • the voltage difference between the bit line BL and the reference bit line /BL will increase significantly, which helps to further amplify the voltage difference between the two, thereby increasing the speed of data reading , and it is beneficial to avoid data being magnified by mistake.
  • the induction amplifier circuit 5 then enters the second amplification stage, at this time, the first NMOS transistor 1 , the second NMOS transistor 2 , the first PMOS transistor 3 and the second PMOS transistor 4 are all turned on, forming a cross-coupling amplification structure.
  • the voltage on the bit line BL is higher than the voltage on the reference bit line /BL.
  • the first NMOS transistor 1 is turned on to discharge the voltage on the reference bit line /BL to the ground.
  • the second PMOS transistor 4 is turned on to increase the voltage on the bit line BL to Vary voltage.
  • the purpose of amplifying the small voltage read from the memory cell 7 by the bit line BL to 0 or 1 can be achieved.
  • the voltage difference output between the two bit lines of the sensing amplifier circuit 5 is the voltage difference to be measured.
  • bit line selection signal YS is turned on, the voltage difference to be measured outputted by the sense amplifier circuit 5 is read, and the data “1” in the storage unit 7 is recognized.
  • the working environment of the sense amplifier is deteriorated by shortening the tRP time and delaying the turn-on of the NMOS transistor or PMOS transistor, thereby detecting that the first NMOS transistor 1 and the first NMOS transistor 1 in the sense amplifier circuit 5 in the sense amplifier are
  • the PMOS transistor 3 , the second NMOS transistor 2 , and the second PMOS transistor 4 cannot be turned on on time when the memory is operating at high speed, and there is a potential failure of the sense amplifier.
  • FIG. 6 it is a waveform diagram of working in the amplification stage when tRP is shortened and the PMOS transistor is delayed to turn on in the sense amplifier of an optional embodiment of a method for detecting sense amplifier mismatch provided by the present application.
  • the sense amplifier The last execution operation was read “0" operation, and this time it is executed to read “1" operation.
  • the reference bit line /BL is at a high level, and the bit line BL is at a low level.
  • the voltage difference between the two bit lines is the first voltage difference.
  • the sense amplifier first enters the pre-charge stage Pre, and performs pre-charge on the two bit lines for a preset time.
  • the preset time is shorter than the standard pre-charge time. Due to the shortened tRP time, the pre-charge The circuit 6 fails to pull the voltages of the two bit lines to the precharge voltage VBLP, and the voltage difference between the two bit lines is the second voltage difference.
  • the reference bit line /BL is at a relatively high level relative to the bit line BL.
  • the voltage difference between the reference bit line /BL and the bit line BL is a relatively high level input into the sense amplifier circuit 5, enters the first amplification stage, the word line signal is turned on, the potential of the bit line BL rises, and the first NMOS transistor 1 according to The preset time is turned on, the delay first PMOS transistor 3 is turned on, and the second PMOS transistor 4 and the second NMOS transistor 2 are turned off.
  • the operating environment of the sense amplifier becomes worse and cannot raise the voltage of the bit line BL to a high level relative to the voltage of the reference bit line /BL within a predetermined time.
  • the sense amplifier then enters the second amplification stage, at this time, the first NMOS transistor 1 , the second NMOS transistor 2 , the first PMOS transistor 3 and the second PMOS transistor 4 are all turned on, forming a cross-coupling amplification structure.
  • the voltage on the bit line BL is lower than the voltage on the reference bit line /BL.
  • the second NMOS transistor 2 is turned on, and the voltage on the bit line BL is discharged to ground through the second NMOS transistor 2 .
  • the first PMOS transistor 3 is turned on to increase the voltage on the reference bit line /BL to Vary voltage. Unexpected flipping of the sense amplifier. At this moment, the voltage difference output between the two bit lines of the sense amplifier circuit 5 is the voltage difference to be measured.
  • bit line select signal YS is turned on, the voltage output by the sense amplifier is read, and the data in the memory cell 7 is misidentified as “0”.
  • the working environment of the sense amplifier can be deteriorated in the case of shortening tRP, so that it is possible that the first NMOS transistor 1, the first PMOS transistor 3, and the first NMOS transistor 3 cannot be turned on within the specified time.
  • the sense amplifiers of the second NMOS transistor 2 and the second PMOS transistor 4 are abnormally reversed, thereby realizing the detection of the mismatch sense amplifier.
  • delaying the turn-on of the PMOS transistor is taken as an example, which may also be replaced by delaying the turn-on of the NMOS transistor, or other methods that can also make the working environment of the sense amplifier worse, which is not specifically limited in this exemplary embodiment.
  • FIG. 7 it is a flowchart of an optional embodiment of a method for detecting sense amplifier mismatch provided in the present application.
  • the bold arrow in the box in Figure 7 indicates that the word line is written, and the arrow that is not bold indicates that the word line is not written.
  • the specific process is as follows:
  • step 1 the first PMOS transistor 3 and the second PMOS transistor 4 are turned on with a delay.
  • Step 2 use the Y-Page method to write the preset test data group W4C0_RS to the word line number 0/4/8/C..., and use the X-Fast method to read the word line 0/4/8/C under the premise of shortening tRP ...
  • Step 3 use the Y-Page method to write the preset test data group W4C1_RS to the word line number 1/5/9/D..., and use the X-Fast method to read the word line 1/5/9/D under the premise of shortening tRP ...
  • Step 4 use Y-Page method to write the preset test data group W4C2_RS to word line number 2/6/A/E..., and use X-Fast method to read word line 2/6/A/E under the premise of shortening tRP ...
  • Step 5 use the Y-Page method to write the preset test data group W4C3_RS to the word line number 3/7/B/F..., and use the X-Fast method to read the word line 3/7/B/F under the premise of shortening tRP ...
  • Step 6 Use the Y-Page method to write the test data group W4C0B_RS to the word line number 0/4/8/C..., and use the X-Fast method to read the word line 0/4/8/C... under the premise of shortening tRP.
  • Step 7 Use the Y-Page method to write the test data group W4C1B_RS to the word line number 1/5/9/D..., and use the X-Fast method to read the word line 1/5/9/D... under the premise of shortening tRP.
  • Step 8 Use Y-Page method to write test data group W4C2B_RS to word line number 2/6/A/E..., and use X-Fast method to read word line 2/6/A/E... under the premise of shortening tRP.
  • Step 9 Use the Y-Page method to write the test data group W4C3B_RS to the word line number 3/7/B/F..., and use the X-Fast method to read the word line 3/7/B/F... under the premise of shortening tRP.
  • step 10 the test mode is exited, and the first PMOS transistor 3 and the second PMOS transistor 4 return to a normal state.
  • Step 11 switch to the first NMOS transistor 1 and the second NMOS transistor 2 to be turned on with delay, and repeat steps 2 to 9.
  • the logical way of arrangement of the memory cells 7 is to determine the position of a certain memory cell 7 by giving the row address and the column address, but under the current memory technology, the operation of the column is determined by the burst length (burst Send Length, BL), where the burst length is determined by the JEDEC standard, and can also be set freely, that is, read and write multiple-bit (such as 8 or 16-bit) column addresses at a time, and write to each burst length Or read the data of 0 and 1 (for example, the address of the location is row 0, and the burst length is 8bit, then at the position of row 0 and column 0, the first 8 values of storage unit 7 are simultaneously written, and the second burst length Write the value of 9-16 digits in the storage unit 7, and write continuously.
  • burst length burst Send Length
  • test software When all the storage locations of one line are written, the test software repositions the address of the next line, and continues the operation of the previous line until the data is written in the entire disk. Read data It is also a similar operation), that is, in this embodiment, the test data is rewritten for the storage location of each row, such as the test data is 10101010101010, then the first row is written into 101010, and the second row is also written into 10101010.
  • the explanation for writing according to the preset interval is as follows: for example, if the preset interval is 1, then when the test data is written into the address of column 0, column 2, column 4, etc. on a certain row of the storage unit 7, the test data will not be written Addresses such as column 1, column 3, etc.
  • the interval between column 0 and column 2 of a certain row on storage unit 7 is the preset interval, that is, 1; if the preset interval is 2, then the test data
  • the test data When writing to addresses such as column 0, column 3, and column 6 on a row of storage unit 7, the test data is not written to addresses such as column 1, column 2, column 4, and column 5 on a row of storage unit 7, and the address of column 7 on storage unit 7
  • the interval between column 0 and column 3 in the previous row is the preset interval, that is, 2. Since the storage failure between multiple storage units 7 is generally a failure between adjacent storage units 7 , the storage failure between multiple storage units 7 can be identified by interval writing, reading and comparison.
  • test data is written into column 0 of a certain row on the storage unit 7 , 4 columns, 8 columns and other addresses, the test data is not written to addresses such as 1 column, 2 columns, 3 columns, 5 columns, 6 columns, and 7 columns on a certain row on the storage unit 7, and the 0
  • the interval between the column and the 4 columns is a preset interval, that is, 3.
  • W4CX_RS and W4CXB_RS represent a data group, and the two data groups are the test data group and the preset test data group.
  • W4CX_RS is the preset test data group
  • W4CXB_RS is the test data group.
  • W4CX_RS is the test data set
  • W4CXB_RS is the preset test data set
  • the data of the test data set and the preset test data set are reversed at the same bit line position.
  • the test system first obtains the preset test data group, and then extracts the first interval data from the preset test data group according to the preset interval.
  • the data 1010 at BL 0 is written in memory cell 7 at the positions of column 0, row 0, row 0, row 1, column 0, row 2, and row 0, row 0, from top to bottom according to the word lines WL0, WL1, WL2, and WL3.
  • test system After the test system reads the data in the storage unit 7 to be tested, it obtains the preset voltage difference to be tested, and completes the amplification preprocessing of the sense amplifier. In this operation, no specific provisions are made on the operation mode of writing and reading data.
  • the test system obtains the test data group, and extracts the second interval data according to the preset interval of the test data group, for example Using W4C0B_RS as the test data group, extract the data 0101 written at the bit line BL 0 in the order of 0 column 0 row, 0 column 1 row, 0 column from top to bottom according to the word line WL0, WL1, WL2, WL3.. 2 rows, 0 columns, 3 rows..
  • the storage unit at the location adopts the Y-PageWrite method to write data 0, 1, 0, 1.. and the first interval data is written in Y-PageWrite according to the preset interval of 3. In the Page mode, all storage units 7 to be tested are sequentially written.
  • the time threshold for delaying the turn-on of the first PMOS transistor 3 and the second PMOS transistor 4 and the shortest threshold of the shortened tRP are determined according to different models of products of different companies, and no specific regulations are made here.
  • the Y-Page Write mode is a Y-direction write operation mode. Before each write operation, a word line WL is turned on, and after all memory cells 7 corresponding to the word line WL are sequentially written, the word line WL is turned off. Then turn on the next word line WL and write all the memory cells 7 sequentially.
  • the X-Fast Read mode is a read operation mode in the X direction. Before each read operation, turn on all word lines WL on the same bit line BL sequentially, turn on a word line WL and sequentially read the content of a burst length (8bit) unit on this word line WL, and then turn off This word line WL, and then turn on the next word line WL, and then sequentially read the content of a burst length unit on this word line WL.
  • the test system After the test system reads the data in all the storage units 7, it obtains the preset voltage difference to be tested and the voltage difference to be measured, and then restores the first PMOS transistor 3 and the second PMOS transistor 4 to a normal working state.
  • the preset voltage difference to be measured and the voltage difference to be measured are output as data in the form of "0" or "1".
  • the test system scans all the voltage differences to be measured and the outputs of the preset voltage differences to be measured at the same location of the storage unit 7, and if they are in the same direction, then it is judged that the corresponding sense amplifier is mismatched.
  • the above process is to perform a round of sense amplifier mismatch detection. After a round of mismatch detection of the sense amplifiers corresponding to all the storage units 7 to be tested is completed, the delayed first PMOS transistor 3 and the second PMOS transistor are turned on and switched to delayed The first NMOS transistor 1 and the second NMOS transistor are turned on, and another round of testing is performed until the testing requirements are met.
  • FIG. 8 is a structural schematic diagram of an optional embodiment of a system for detecting sense amplifier mismatch provided by the present application, including:
  • Data acquisition module 81 for acquiring test data group
  • the data conversion module 82 is used to convert the test data group into the first voltage difference between the bit line and the reference bit line, and input it to the sense amplifier that delays the opening of the PMOS transistor or the NMOS transistor for precharging for a preset time, so The preset time is shorter than the standard pre-charging time, and is used to amplify the second voltage difference between the bit line obtained after pre-charging and the reference bit line through a sense amplifier to obtain a voltage difference to be measured;
  • a mismatch detection module 83 configured to compare the voltage difference to be measured with a preset voltage difference to be measured, and if the voltage difference to be measured is in the same direction as the preset voltage difference to be measured, then determine whether the induction Amplifier mismatch.
  • the data acquisition module 81 is also used to acquire a preset test data set before acquiring the test data set.
  • the data conversion module 82 is also used to convert the preset test data group into the third voltage difference between the bit line and the reference bit line, and input it to the sense amplifier with the MOS tube normally turned on for pre-charging of the standard pre-charging time, and the pre-charging
  • the fourth voltage difference between the bit line and the reference bit line obtained after charging is amplified by a sense amplifier to obtain a preset voltage difference to be tested, wherein the preset test data set and the corresponding bit line position where the test data set is written Data reversed.
  • each module in the above embodiment of the present application is the same as the embodiment of the above-mentioned method for detecting sense amplifier mismatch.
  • the embodiment of the above-mentioned method for detecting sense amplifier mismatch refers to the embodiment of the above-mentioned method for detecting sense amplifier mismatch. In order to avoid repetition, details are not repeated here.

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Abstract

本申请涉及半导体领域，特别涉及动态随机存取存储器领域，提供了一种检测感应放大器失配的方法和系统；所述方法通过延迟感应放大器中NMOS或PMOS管的开启和缩短行预充电时间来让感应放大器在较差的环境中工作，从而检测出由于工艺制造差异而导致失配的感应放大器。

Description

一种检测感应放大器失配的系统和方法
相关申请
本申请基于申请号为202111310551.4，申请日为2021年11月05日，申请名称为“一种检测感应放大器失配的系统和方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体领域，特别涉及DRAM(Dynamic Random Access Memory，动态随机存取存储器)领域。
背景技术
在DRAM中，由于存储单元尺寸很小，驱动能力很弱，位线与参考位线之间电压差很小，如果直接送入输出缓冲器，将无法识别逻辑0和1。感应放大器即是用于放大位线与参考位线之间的微弱电压差，从而使得存储单元中的逻辑数据可以被正确地识别。
目前，由于工艺制造差异的原因，导致制造出来的感应放大器抗干扰能力不足，以及在感应放大器工作时MOS管没有在正确的时间点开启，导致感应放大器异常翻转，读取失败。传统方法对感应放大器的测试采用的是在缩短预充电时间的情况下对存储单元进行写读操作，通过比对输出结果判断感应放大器是否失配。由于现有的传统方法卡的预充电时间较松，感应放大器的工作环境不够差，从而一些潜在的感应放大器的失效不容易暴露，检测效果达不到预期。
发明内容
基于此，有必要提高一种能够有效检测出由于工艺制造差异问题导致有着潜在失效可能的感应放大器的检测方法。
为了实现上述目的，本申请实施例提供一种检测感应放大器失配的方法，包括：
获取测试数据组；
将所述测试数据组转换为位线与参考位线间第一电压差，并输入至延迟PMOS管或NMOS管开启的感应放大器中进行持续预设时间的预充电，所述预设时间小于标准预充电时间；
将预充电后的得到的所述位线与所述参考位线间第二电压差通过所述感应放大器进行放大，得到待测电压差；
将所述待测电压差与预设待测电压差进行比对，若所述待测电压差与所述预设待测电压差同向则 判断所述感应放大器失配。
在一些实施例中，所述获取测试数据组前，还包括：
获取预设测试数据组，将所述预设测试数据组转换为所述位线与所述参考位线间第三电压差，输入到MOS管正常开启的所述感应放大器中进行标准预充电时间的预充电，将预充电后得到的所述位线与所述参考位线间第四电压差通过所述感应放大器进行放大，得到所述预设待测电压差。
在一些实施例中，所述预设测试数据组与所述测试数据组写入的对应所述位线位置处数据反向。
在一些实施例中，所述将所述测试数据组转换为位线与参考位线间第一电压差，包括：
将所述测试数据组写入待测存储单元，通过所述待测存储单元将所述测试数据组转换为所述位线与所述参考位线间所述第一电压差。
在一些实施例中，将所述测试数据组写入所述待测存储单元，通过所述待测存储单元将所述测试数据组转换为所述位线与所述参考位线间所述第一电压差，包括：
将所述测试数据组按照预设间隔依次写入所述待测存储单元后，根据所述测试数据组从所述待测存储单元中读取所述位线与所述参考位线间所述第一电压差。
在一些实施例中，将所述测试数据组按照预设间隔依次写入所述待测存储单元，包括：
将所述测试数据组按照预设间隔提取第一间隔数据，并按照所述预设间隔将所述第一间隔数据依次写入所有所述待测存储单元。
在一些实施例中，根据所述测试数据组从所述待测存储单元中读取所述位线与所述参考位线间所述第一电压差，包括：
沿X方向进行读操作，在每次执行所述读操作前，顺序开启同一条位线上的所有字线，开启一条字线并且顺序读取这条字线上一个突发长度所述待测存储单元的内容，关闭这条字线，再重复上述操作至对所有字线完成至少一次一个突发长度所述待测存储单元的所述读操作。
在一些实施例中，所述将预设测试数据组转换为位线与参考位线间第三电压差，包括：
将所述预设测试数据组写入待测存储单元，通过所述待测存储单元将所述预设测试数据组转换为所述位线与所述参考位线间所述第三电压差。
在一些实施例中，将所述预设测试数据组写入待测存储单元，通过所述待测存储单元将所述预设测试数据组转换为所述位线与所述参考位线间所述第三电压差，包括：
将所述预设测试数据组按照所述预设间隔依次写入所述待测存储单元后，根据所述预设测试数据组从所述待测存储单元中读取所述位线与所述参考位线间所述第三电压差。
在一些实施例中，将所述预设测试数据组按照预设间隔依次写入待测存储单元，包括：
将所述预设测试数据组按照所述预设间隔提取第二间隔数据，并按照所述预设间隔将所述第二间隔数据依次写入所有所述待测存储单元。
在一些实施例中，将第一电压差输入至延迟PMOS管或NMOS管开启的感应放大器中进行持续预设时间的预充电，将预充电后的得到的第二电压差通过感应放大器进行放大，得到待测电压差，具 体包括：
将所述第一电压差输入至延迟PMOS管或NMOS管开启的所述感应放大器中进行持续预设时间的预充电，将预充电后的得到的所述第二电压差通过所述感应放大器的感应放大电路进行放大，得到待测电压差，其中，所述感应放大器的感应放大电路中的第一NMOS管与第一PMOS管，以及第二NMOS管与第二PMOS管分别构成CMOS反相器。
本申请实施例还提供一种检测感应放大器失配的系统，包括：
数据获取模块，用于获取测试数据组；
数据转换模块，用于将所述测试数据组转换为位线与参考位线间第一电压差，输入至延迟PMOS管或NMOS管开启的感应放大器中进行持续预设时间的预充电，所述预设时间小于标准预充电时间，以及用于将预充电后的得到的所述位线与所述参考位线间第二电压差通过感应放大器进行放大，得到待测电压差；
失配检测模块，用于将所述待测电压差与预设待测电压差进行比对，若所述待测电压差与所述预设待测电压差同向，则判断所述感应放大器失配。
进一步地，数据获取模块还用于在获取所述测试数据组前，获取预设测试数据组。
本申请实施例中检测感应放大器失配的方法采用延迟感应放大器中PMOS管或者NMOS管开启的方式，加速测试失效的存储颗粒。Y-Page Write的方式执行写操作是在延迟晶体管开启的基础上，采用开启一条字线，顺序写完这条字线上对应的所有存储单元后，关闭这条字线，再开启下一条字线顺序写入，直至写完所有的存储单元。X-Fast Read的方式是执行读操作时，顺序开启同一条位线上的所有字线，开启一条字线并且顺序读取这条字线上一个突发长度(8bit)单元的内容后，关闭这条字线，再开启下一条字线顺序读取，直至读完所有的存储单元上的内容。在延迟感应放大器的NMOS管或者PMOS管的基础上按照Y-Page方式写入一种数据拓扑，然后在缩短tRP时间的前提下按照X-Fast方式读取此种数据拓扑。从而使得原本有潜在失效可能的感应放大器工作环境更差，从而有效测试出更纯净的感应放大器失效的颗粒。
附图说明
图1为本申请提供的一种检测感应放大器失配的方法的一个可选实施例的感应放大器工作电路图；
图2为本申请提供的一种检测感应放大器失配的方法的一个可选实施例的流程示意图；
图3为本申请提供的一种检测感应放大器失配的方法的一个可选实施例的测试数据拓扑图；
图4为本申请提供的一种检测感应放大器失配的方法的一个可选实施例的完整波形图；
图5为本申请提供的一种检测感应放大器失配的方法的一个可选实施例的感应放大器正常工作于放大阶段的波形图；
图6为本申请提供的一种检测感应放大器失配的方法的一个可选实施例的感应放大器中缩短 tRP且PMOS管延迟开启时工作于放大阶段的波形图；
图7为本申请提供的一种检测感应放大器失配的方法的一个可选实施例的流程图；
图8为本申请提供的一种检测感应放大器失配的系统的一个可选实施例的结构示意图。
附图标记：
1、第一NMOS管；2、第二NMOS管；3、第一PMOS管；4、第二PMOS管；5、感应放大电路；6、预充电电路；7、存储单元；81、数据获取模块；82、数据转换模块；83、失配检测模块。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请公开的一部分实施例，而不是全部的实施例。基于本申请公开的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。另外，贯穿说明书和跟随的权利要求中所使用的某些术语指代特定元件。本领域的技术人员会理解为，制造商可以用不同的名字指代元件。本文件不想要区分名字不同但是功能相同的元件。在以下的描述和实施例中，术语“包含”和“包括”都是开放式使用的，因此应该解读为“包含，但不限于……”。同样，术语“连接”想要表达间接或直接的电气连接。相应地，如果一个设备被连接到另一个设备上，连接可以通过直接的电气连接完成，或者通过其他设备和连接件的间接电气连接完成。
应当理解，尽管本文可以使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件和另一个元件区分开。例如，在不脱离本申请公开的范围的情况下，第一元件可以被称为第二元件，并且类似地，第二元件可以被称为第一元件。
在一个实施例中，如图1所示，为本申请提供的一种感应放大器失配的方法的一个可选实施例的感应放大器的工作电路图。感应放大器包括感应放大电路5、预充电电路6、存储单元7。
感应放大电路5由第一NMOS(Negative channel-Metal-Oxide-Semiconductor)管1、第二NMOS管2、第一PMOS管(positive channel-Metal Oxide-Semiconductor)3、第二PMOS管4、PCS电源和NCS电源构成。第一PMOS管3的漏极和第二PMOS管4的栅极均与位线BL相连接，第一PMOS管3的栅极和第二PMOS管4的漏极均与参考位线/BL连接，第一PMOS管3和第二PMOS管4的源极均与PCS电源连接。第一NMOS管1的栅极和第二NMOS管2的漏极均与位线BL相连接，第一NMOS管1的漏极和第二NMOS管2的栅极均与参考位线/BL相连接，第一NMOS管1和第二NMOS管2的源极均与NCS电源连接。由此可见，所述感应放大电路5由第一NMOS管1、第二 NMOS管2和第一PMOS管3、第二PMOS管4交叉耦合构成，其中，所述第一NMOS管1与第一PMOS管3，以及所述第二NMOS管2与第二PMOS管4分别构成CMOS反相器。
在本实施例中，所述PCS电源用于响应上拉控制信号将第一PMOS管3的源极与电源电压VDD连接。NCS电源用于响应下拉控制信号将第一NMOS管1的源极接地。
在本实施例中，位线BL与参考位线/BL之间的电压差达到一定值后，NCS电源开启，PCS电源开启，第一NMOS管1、第二NMOS管2、第一PMOS管3、第二PMOS管4形成两个交叉耦合的反相器正反馈电路，快速放大位线BL与参考位线/BL之间的电压差，完成感应放大电路5对位线BL与参考位线/BL之间电压差的放大。
在本实施例中，PCS电源可以包括上拉PMOS管，NCS电源可以包括下拉NMOS管。然而，PCS电源也可以使用NMOS管实现，NCS电源也可以使用PMOS管实现，并且PCS电源或NCS电源可以包含不止一个器件，也可以包括通过不同的控制信号控制导通或关断的多个器件，本申请对此不做限制。
预充电电路6由三个NMOS管组成，与感应放大电路5的两个输出端线相连接。预充电电路6的控制端接收均衡控制信号EQ。预充电电路6可以在均衡控制信号EQ的控制下对位线BL、参考位线/BL和感应放大电路5的两个输出端线进行预充电，并且可将所述位线BL和参考位线/BL充电至规定的预充电电压VBLP。在实现相同或者相近电路功能的情况下，本示例性实施方式中提供的预充电电路6也可以选用其他任意的替换电路，本示例性实施方式对此不做特殊限定。
在本实施中，所述YS为一列位线选择信号，例如可以由一个NMOS管组成，所述NMOS管的栅极与位线选择信号YS连接，源极与LIO连接，YSW为控制所述NMOS开启的栅极电压差。
在本实施例中，所述存储单元7，包括一个驱动晶体管和存储电容，所述驱动晶体管的栅极与字线WL连接，漏极与位线BL连接，源极通过存储电容连接与地线。当存储电容上的电荷被抽空(即放电)时，其存储资料为“0”，当存储电容被充电后，通常是被充电至工作电压VDD，其存储资料为“1”。所述字线WL通过控制所述驱动晶体管的导通或关断，进而控制所述存储电容的充放电，从而实现数据的写入或读出。
在一个实施例中，如图2所示，为本申请提供的一种检测感应放大器失配的方法的一个可选实施例的流程示意图，所述方法包括：
S11、获取测试数据组；
S12、将所述测试数据组转换为位线与参考位线间第一电压差，并输入至延迟PMOS管或NMOS管开启的感应放大器中进行持续预设时间的预充电，所述预设时间小于标准预充电时间；
S13、将预充电后的得到的所述位线与所述参考位线间第二电压差通过所述感应放大器进行放大，得到待测电压差；
S14、将所述待测电压差与预设待测电压差进行比对，若所述待测电压差与所述预设待测电压差同向则判断所述感应放大器失配。
具体地，步骤S12中的延迟PMOS管或NMOS管开启的感应放大器对应于图1中的感应放大电路5时，延迟PMOS管则为同时延迟第一PMOS管3和第二PMOS管4，延迟NMOS管则为同时延迟第一NMOS管1和第二NMOS管2。
获取预设测试数据组后，将预设测试数据组转换为所述位线BL与所述参考位线/BL间第三电压差，输入到MOS管正常开启的感应放大器中进行标准预充电时间的预充电，将预充电后得到的第四电压差通过感应放大电路5进行放大，得到的预设待测电压差；所述预设测试数据组与测试数据组写入的对应位线位置处数据反向，其中，所述MOS管指的是感应放大器的感应放大电路5中的第一NMOS管1、第二NMOS管2和第一PMOS管3、第二PMOS管4。
如图3所示，为本实施例中写入的测试数据组的数据拓扑图，图中W4C0_RS、W4C1_RS、W4C2_RS、W4C3_RS可作为预设测试数据组，W4C0B_RS、W4C1B_RS、W4C2B_RS、W4C3B_RS可作为测试数据组，二者可互换但需要保证所述预设测试数据组和测试数据组在写入的位线位置处数据反向，这里需要保证所述预设测试数据组和测试数据组在写入的位线位置处数据反向是为了在测试感应放大器的失配造就更差的测试条件，使得能够在卡紧预充电时间的时候更容易测到感应放大器的失效。
感应放大器工作时，存储单元7内以位线BL与参考位线/BL间的微弱电压差表达存储在存储单元7中的“0”或“1”，为所述第一电压差。由于存储单元7尺寸很小，驱动能力很弱，位线BL与参考位线/BL之间电压差很小，如果直接送入输出缓冲器，将无法识别存储单元7中“0”或“1”，因此需要将存储单元7内位线BL与参考位线/BL之间电压差输入到感应放大电路5中进行放大。
在本实施例中，如图4所示，为本申请提供的一种检测感应放大器失配的方法的一个可选实施例的完整波形图，以上次操作执行读“1”，此次操作执行读“1”操作为例，描述了感应放大器一次完整工作过程中位线BL与参考位线/BL之间电压差的变化，观察感应放大器的完整工作过程。
在本实施例中，所述tRP(Precharge command period)，为预充电时间，也被称为是行预充电时间，在发出预充电命令之后，要经过一段时间才能允许发送RAS(Row Address Strobe，行地址选通脉冲)有效命令打开新的工作行。其中，所述tRCD，为RAS至CAS(Column address strobe，列地址选通脉冲)延迟。在完成数据“1”读取后，感应放大器工作过程中还包括恢复阶段。在执行读“1”操作后，均衡控制信号EQ关闭，字线信号开启，PCS电源与NCS电源开启，令参考位线/BL恢复为高电平，位线BL恢复为低电平。
在本实施例中，由于上次操作为执行读“1”，故位线BL为高电平，参考位线/BL为低电平，所述Pre表示开始进行预充电操作，此时字线信号关闭，感应放大电路5关闭(SAoff未进行放大操作)，均衡控制信号EQ开启，将位线BL与参考位线/BL均充电至预充电压VBLP。
预充电阶段结束后，感应放大电路5开启，均衡控制信号EQ关闭，字线信号开启，控制对应的存储单元7中的存储电容进行充电操作。存储电容中的电荷与位线BL的电荷之间进行电荷分享，由于该过程中值为“1”的数据存储在对应的存储电容中，在电荷分享过程中，位线BL的电压升高约15-20 毫伏。
在此过程中，感应放大电路5中的NMOS管和PMOS管均正常开启，其中，第一NMOS管1与第一PMOS管3，以及第二NMOS管2与第二PMOS管4分别构成CMOS反相器。由于此次操作执行读“1”，则此时主要依靠第一NMOS管1与第一PMOS管3构成的CMOS反相器来完成电压差的放大，从而完成对存储单元1中数据“1”的读取。如果此次操作执行读“0”，则此时主要依靠第二NMOS管2与第二PMOS管4构成的CMOS反相器来完成电压差的放大，从而完成对存储单元1中数据“0”的读取。
目前，由于工艺制造差异的原因，导致制造出来的感应放大器抗干扰能力不足，以及在感应放大器工作时感应放大电路5中的NMOS管或者PMOS管没有在正确的时间点开启，导致感应放大器异常翻转，读取失败。传统方法在测试感应放大器时，通过在缩短预充电时间的情况下对存储单元7进行写读操作，将输出结果进行比对从而判断感应放大器是否失配。但是传统方法卡的预充电时间较松，感应放大器的工作环境不够差，从而一些潜在的感应放大器的失效不容易暴露，检测效果达不到预期。
在一个实施例中，如图5所示，为本申请提供的一种检测感应放大器失配的方法的一个可选实施例的感应放大器正常工作于放大阶段的波形图，所述感应放大器上一次执行操作为读“0”操作，本次执行读“1”操作。
在本实施例中，提供的预设测试数据组对存储单元7写入的数据为“0”，提供的测试数据组对存储单元7写入的数据为“1”。对预设测试数据组的写入存储单元7后读取，为测试数据组的写入存储单元7后读取的前置操作。
在执行上次读“0”操作时，存储单元7以位线BL与参考位线/BL间的微弱电压差输入感应放大器，此时，所述微弱电压为第三电压差。在tRP时间内，感应放大器先进入预充电阶段，对两条位线(即，位线BL与参考位线/BL)进行持续标准预充电时间的预充电，将两条位线的电压均拉至预充电压VBLP，此时两条位线间电压差为第四电压差。
所述标准预充电时间根据不同公司不同型号的产品具体规定的出厂参数，在此不作具体规定。通过第一NMOS管1、第一PMOS管3、第二NMOS管2、第二PMOS管4正常开启的感应放大电路5进行放大后输出，获得预设电压差。由上述实施例可知，在感应放大器的恢复阶段结束后，参考位线/BL恢复为高电平，位线BL恢复为低电平。
由于上次执行读“0”操作，故感应放大器开启前参考位线/BL为高电平，位线BL为低电平，两条位线间电压差为第一电压差。在tRP时间内，感应放大器先进入预充电阶段Pre，对两条位线进行持续标准预充电时间的预充电，将两条位线电压均拉至预充电压VBLP，此时两条位线间的电压差为第二电压差。
预充电工作完成后，经过预充电后的两条位线作为输入进入感应放大电路5，进入第一放大阶段，字线信号开启，位线BL的电压升高，此时第一PMOS管3和第一NMOS管1按照预设时间开启， 第二PMOS管4和第二NMOS管2关闭。
由于第一PMOS管3和第一NMOS管1构成CMOS反相器，此时位线BL为相对高电平，由于反相器的作用，使得反相器输出端的电压在第一放大阶段不断降低，即参考位线/BL的电压不断降低。
在感应放大电路5的第一放大阶段，位线BL与参考位线/BL之间的电压差会大幅度增大，有助于对二者电压差进行进一步放大，从而提高数据读取的速度，且有利于避免数据被错误放大。
感应放大电路5而后进入第二放大阶段，此时第一NMOS管1、第二NMOS管2、第一PMOS管3和第二PMOS管4皆开启，构成交叉耦合放大结构。
此时位线BL上的电压高于参考位线/BL上的电压，此时第一NMOS管1开启，将参考位线/BL上的电压放电至地。另外，第二PMOS管4开启，将位线BL上的电压升高至Vary电压。
由此，通过这种交叉耦合放大结构，可以实现位线BL从存储单元7中读取出来的小电压放大至0或1的目的。此时感应放大电路5两条位线间输出的电压差为待测电压差。
而后，位线选择信号YS开启，读取感应放大电路5输出的待测电压差，识别出存储单元7中的数据“1”。
本申请实施例通过缩短tRP时间和延迟NMOS管或PMOS管开启实现恶化感应放大器的工作环境，从而检测出由于工艺差异，导致感应放大器中的感应放大电路5中的第一NMOS管1、第一PMOS管3、第二NMOS管2、第二PMOS管4不能在存储器高速工作时按时开启，有潜在失效可能的感应放大器。
如图6所示，为本申请提供的一种检测感应放大器失配的方法的一个可选实施例的感应放大器中缩短tRP且PMOS管延迟开启时工作于放大阶段的波形图，所述感应放大器上一次执行操作为读“0”操作，本次执行读“1”操作。
由于上次执行读“0”操作，故感应放大器开启前参考位线/BL为高电平，位线BL为低电平，此时两条位线间电压差为第一电压差。在缩短后的tRP时间内，感应放大器先进入预充电阶段Pre，对两条位线进行执行持续预设时间的预充电，所述预设时间小于标准预充电时间，由于tRP时间缩短，预充电电路6未能将两条位线的电压均拉至预充电压VBLP，此时两条位线间电压差为第二电压差。此时参考位线/BL相对位线BL为相对高电平。
以参考位线/BL相对位线BL为相对高电平的电压差输入感应放大电路5中，进入第一放大阶段，字线信号开启，位线BL的电位升高，第一NMOS管1按照预设时间开启，延迟第一PMOS管3开启，第二PMOS管4和第二NMOS管2关闭。
感应放大器的工作环境变得更差，无法在预定时间内将位线BL的电压升至相对于参考位线/BL电压的高电平。
感应放大器而后进入第二放大阶段，此时第一NMOS管1、第二NMOS管2、第一PMOS管3和第二PMOS管4皆开启，构成交叉耦合放大结构。
此时位线BL上的电压低于参考位线/BL上的电压，此时，第二NMOS管2开启，将位线BL上 的电压通过第二NMOS管2放电至地。另外，第一PMOS管3开启，将参考位线/BL上的电压升高至Vary电压。感应放大器出现异常翻转。此时感应放大电路5的两条位线间输出的电压差为待测电压差。
而后，位线选择信号YS开启，读取感应放大器输出的电压，错误识别出存储单元7中的数据为“0”。
由此可见，通过延迟PMOS管开启后，在缩短tRP的情况下能够使得感应放大器的工作环境变差，使得有潜在可能无法在规定时间内开启第一NMOS管1、第一PMOS管3、第二NMOS管2、第二PMOS管4的感应放大器出现异常翻转，从而实现对失配感应放大器的检测。
在本实施例中，以延迟PMOS管开启为例，也可换为延迟NMOS管开启，或其他能够同样使得感应放大器工作环境变差的方式，本示例性实施方式对此不做特殊限定。
在一个实施例中，如图7所示，为本申请提供的一种检测感应放大器失配的方法的一个可选实施例的流程图。图7方框中加粗的箭头表示写入该条字线，不加粗的箭头表示不写入这条字线，具体流程如下：
步骤1，第一PMOS管3和第二PMOS管4延迟开启。
步骤2，采用Y-Page方式对字线编号0/4/8/C…写入预设测试数据组W4C0_RS，在缩短tRP前提下，采用X-Fast方式读字线0/4/8/C…。
步骤3，采用Y-Page方式对字线编号1/5/9/D…写入预设测试数据组W4C1_RS,在缩短tRP前提下，采用X-Fast方式读字线1/5/9/D…。
步骤4，采用Y-Page方式对字线编号2/6/A/E…写入预设测试数据组W4C2_RS,在缩短tRP前提下，采用X-Fast方式读字线2/6/A/E…。
步骤5，采用Y-Page方式对字线编号3/7/B/F…写入预设测试数据组W4C3_RS,在缩短tRP前提下，采用X-Fast方式读字线3/7/B/F…。
步骤6，采用Y-Page方式对字线编号0/4/8/C…写入测试数据组W4C0B_RS,在缩短tRP前提下，采用X-Fast方式读字线0/4/8/C…。
步骤7，采用Y-Page方式对字线编号1/5/9/D…写入测试数据组W4C1B_RS,在缩短tRP前提下，采用X-Fast方式读字线1/5/9/D…。
步骤8，采用Y-Page方式对字线编号2/6/A/E…写入测试数据组W4C2B_RS,在缩短tRP前提下，采用X-Fast方式读字线2/6/A/E…。
步骤9，采用Y-Page方式对字线编号3/7/B/F…写入测试数据组W4C3B_RS,在缩短tRP前提下，采用X-Fast方式读字线3/7/B/F…。
步骤10，测试模式退出，第一PMOS管3和第二PMOS管4恢复正常状态。
步骤11，切换到第一NMOS管1和第二NMOS管2延迟开启，重复步骤2到9。
在本实施例中，存储单元7排列的逻辑方式是通过给定行地址和列地址来确定某个存储单元7的位置，但是在当前的存储技术下，列的操作是通过突发长度(突发Length，BL)进行的，其中突发长度由JEDEC标准确定，也可以自由设置，即一次操作多位(如8或16位)列地址的读写，并对每个突发长度里写入或读取0和1的数据(例如定位的地址是0行，突发长度为8bit，那么在0行0列这个位置开始同时写入存储单元7的前8个数值，第二个突发长度写入存储单元7的9-16位数值，一直连续写入。当一行的存储位置全部写完时，测试软件重新定位下一行的地址，继续上一行的操作，直到全盘写入数据。读数据也是类似的操作)，即本实施方式中，对于每一行的存储位置上都是重新写入测试数据，比如测试数据为1010101010101010，则第一行写入10101010，第二行也写入10101010。
另外，对于按照预设间隔的写入解释如下：比如预设间隔为1，那么测试数据在写入存储单元7上某一行上0列、2列、4列等地址时，测试数据不写入存储单元7上某一行上1列、3列等地址，存储单元7上某一行的0列与2列之间的间隔则为预设间隔，即1；如果预设间隔为2，那么测试数据写入存储单元7上某一行上0列、3列、6列等地址时，测试数据不写入存储单元7上某一行上1列、2列、4列、5列等地址，存储单元7上某一行的0列与3列之间的间隔则为预设间隔，即2。由于多存储单元7之间的存储故障，一般是出现在相邻存储单元7之间的故障，因此间隔写入、读取和比较能够识别出多存储单元7之间的存储故障。图7方框中加粗的箭头表示写入该条字线，不加粗的箭头表示不写入这条字线，根据图7可知，测试数据在写入存储单元7上某一行上0列、4列、8列等地址时，测试数据不写入存储单元7上某一行上1列、2列、3列、5列、6列、7列等地址，存储单元7上某一行的0列与4列之间的间隔则为预设间隔，即3。
如图3所示，W4CX_RS和W4CXB_RS表示一种数据组，两种数据组互为测试数据组和预设测试数据组，当W4CX_RS为预设测试数据组时，W4CXB_RS即为测试数据组，同样的，当W4CX_RS为测试数据组时，W4CXB_RS即为预设测试数据组，测试数据组和预设测试数据组在相同位线位置处数据反向。
在本实施例中，测试系统先获取预设测试数据组，而后将所述预设测试数据组按照预设间隔提取第一间隔数据，例如采用W4C0_RS作为预设测试数据组，提取写入位线BL 0处的数据1010按照字线WL0、WL1、WL2、WL3的方式从上往下依次在0列0行、0列1行、0列2行、0列3行位置处的存储单元7写入数据1、0、1、0并按照所述预设间隔为3将所述第一间隔数据依次写入所有待测 的存储单元7。
测试系统读取所述待测存储单元7中的数据后，得到预设待测电压差，完成对感应放大器的放大预处理，在本次操作中对数据的写读的操作方式不作具体规定。
而后在存储器的TM(TESTMODE测试模式)中设置第一PMOS管3和第二PMOS管4延迟开启，测试系统获取测试数据组，将所述测试数据组按照预设间隔提取第二间隔数据，例如采用W4C0B_RS作为测试数据组，提取写入位线BL 0处的数据0101按照字线WL0、WL1、WL2、WL3..的方式从上往下依次在0列0行、0列1行、0列2行、0列3行..位置处的存储单元采用Y-PageWrite方式写入数据0、1、0、1..并按照所述预设间隔为3将所述第一间隔数据采用Y-Page方式依次写入所有待测的存储单元7。
在TEST MODE中设置所述第一PMOS管3和第二PMOS管4延迟开启的时间阈值和缩短的tRP的最短阈值根据不同公司不同型号的产品确定，在此不作具体规定。
所述Y-Page Write方式为一种Y方向写操作方式。在每一次执行写操作之前，开启一条字线WL，顺序写完这条字线WL上对应的所有存储单元7后，关闭这条字线WL。然后再开启下一条字线WL顺序写完所有的存储单元7。
而后在缩短tRP的条件下，采用X-Fast Read方式读取待测存储单元7中的数据。由于缩短了tRP时间，只有采用X-Fast Read方式才能卡到缩短后的tRP时间完成读取。
所述X-Fast Read方式为一种X方向读操作方式。在每一次执行读操作之前，顺序开启同一条位线BL上的所有字线WL，开启一条字线WL并且顺序读取这条字线WL上一个突发长度(8bit)单元的内容后，关闭这条字线WL，然后开启下一条字线WL再顺序读取这条字线WL上一个突发长度单元的内容。
测试系统读取所有存储单元7中的数据后，得到预设待测电压差和待测电压差，而后将第一PMOS管3和第二PMOS管4恢复到正常工作状态。所述预设待测电压差和待测电压差以“0”或者“1”的方式作为数据输出。测试系统浏览所有待测电压差和预设待测电压差在相同存储单元7位置处的输出，若同向，则判断对应的感应放大器失配。
上述过程为进行一轮感应放大器失配检测，在进行完一轮所有待测的存储单元7对应的感应放大器的失配检测后，将延迟第一PMOS管3和第二PMOS管开启切换为延迟第一NMOS管1和第二NMOS管开启，再进行一轮测试，直至满足测试需要。
本申请还提供一种检测感应放大器失配的系统，如图8所示，为本申请提供的一种检测感应放 大器失配的系统的一个可选实施例的结构示意图，包括：
数据获取模块81，用于获取测试数据组；
数据转换模块82，用于将所述测试数据组转换为位线与参考位线间第一电压差，输入至延迟PMOS管或NMOS管开启的感应放大器中进行持续预设时间的预充电，所述预设时间小于标准预充电时间，以及用于将预充电后的得到的所述位线与所述参考位线间第二电压差通过感应放大器进行放大，得到待测电压差；
失配检测模块83，用于将所述待测电压差与预设待测电压差进行比对，若所述待测电压差与所述预设待测电压差同向，则判断所述感应放大器失配。
所述数据获取模块81还用于在获取测试数据组前，获取预设测试数据组。
所述数据转换模块82还用于将预设测试数据组转换为位线与参考位线间第三电压差，输入到MOS管正常开启的灵敏放大器中进行标准预充电时间的预充电，将预充电后得到的位线与参考位线间第四电压差通过灵敏放大器进行放大，得到预设待测电压差，其中，所述预设测试数据组与测试数据组写入的对应位线位置处数据反向。
本申请上述实施例各模块的功能及实现方式与上述检测感应放大器失配方法的实施例相同，具体解析可以参照上述检测感应放大器失配方法的实施例，为了避免重复，在此不再赘述。
以上所述是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本申请的保护范围。

Claims (13)

  1. 一种检测感应放大器失配的方法，包括：
    获取测试数据组；
    将所述测试数据组转换为位线与参考位线间第一电压差，并输入至延迟PMOS管或NMOS管开启的感应放大器中进行持续预设时间的预充电，所述预设时间小于标准预充电时间；
    将预充电后的得到的所述位线与所述参考位线间第二电压差通过所述感应放大器进行放大，得到待测电压差；
    将所述待测电压差与预设待测电压差进行比对，若所述待测电压差与所述预设待测电压差同向则判断所述感应放大器失配。
  2. 如权利要求1所述的一种检测感应放大器失配的方法，其中，所述获取测试数据组前，还包括：
    获取预设测试数据组，将所述预设测试数据组转换为所述位线与所述参考位线间第三电压差，输入到MOS管正常开启的所述感应放大器中进行标准预充电时间的预充电，将预充电后得到的所述位线与所述参考位线间第四电压差通过所述感应放大器进行放大，得到所述预设待测电压差。
  3. 如权利要求2所述的一种检测感应放大器失配的方法，其中，所述预设测试数据组与所述测试数据组写入的对应所述位线位置处数据反向。
  4. 如权利要求1所述的一种检测感应放大器失配的方法，其中，所述将所述测试数据组转换为位线与参考位线间第一电压差，包括：
    将所述测试数据组写入待测存储单元，通过所述待测存储单元将所述测试数据组转换为所述位线与所述参考位线间所述第一电压差。
  5. 如权利要求4所述的一种检测感应放大器失配的方法，其中，将所述测试数据组写入所述待测存储单元，通过所述待测存储单元将所述测试数据组转换为所述位线与所述参考位线间所述第一电压差，包括：
    将所述测试数据组按照预设间隔依次写入所述待测存储单元后，根据所述测试数据组从所述待测存储单元中读取所述位线与所述参考位线间所述第一电压差。
  6. 如权利要求5所述的一种检测感应放大器失配的方法，其中，将所述测试数据组按照预设间隔依次写入所述待测存储单元，包括：
    将所述测试数据组按照预设间隔提取第一间隔数据，并按照所述预设间隔将所述第一间隔数据依次写入所有所述待测存储单元。
  7. 如权利要求5所述的一种检测感应放大器失配的方法，其中，根据所述测试数据组从所述待测存储单元中读取所述位线与所述参考位线间所述第一电压差，包括：
    沿X方向进行读操作，在每次执行所述读操作前，顺序开启同一条位线上的所有字线，开启一条字线并且顺序读取这条字线上一个突发长度所述待测存储单元的内容，关闭这条字线，再重复上述操作至对所有字线完成至少一次一个突发长度所述待测存储单元的所述读操作。
  8. 如权利要求3所述的一种检测感应放大器失配的方法，其中，所述将预设测试数据组转换为位线与参考位线间第三电压差，包括：
    将所述预设测试数据组写入待测存储单元，通过所述待测存储单元将所述预设测试数据组转换为所述位线与所述参考位线间所述第三电压差。
  9. 如权利要求8所述的一种检测感应放大器失配的方法，其中，将所述预设测试数据组写入待测存储单元，通过所述待测存储单元将所述预设测试数据组转换为所述位线与所述参考位线间所述第三电压差，包括：
    将所述预设测试数据组按照所述预设间隔依次写入所述待测存储单元后，根据所述预设测试数据组从所述待测存储单元中读取所述位线与所述参考位线间所述第三电压差。
  10. 如权利要求9所述的一种检测感应放大器失配的方法，其中，将所述预设测试数据组按照预设间隔依次写入待测存储单元，包括：
    将所述预设测试数据组按照所述预设间隔提取第二间隔数据，并按照所述预设间隔将所述第二间隔数据依次写入所有所述待测存储单元。
  11. 如权利要求1所述的一种检测感应放大器失配的方法，其中，将第一电压差输入至延迟PMOS管或NMOS管开启的感应放大器中进行持续预设时间的预充电，将预充电后的得到的第二电压差通过感应放大器进行放大，得到待测电压差，具体包括：
    将所述第一电压差输入至延迟PMOS管或NMOS管开启的所述感应放大器中进行持续预设时间的预充电，将预充电后的得到的所述第二电压差通过所述感应放大器的感应放大电路进行放大，得到待测电压差，其中，所述感应放大器的感应放大电路中的第一NMOS管与第一PMOS管，以及第二NMOS管与第二PMOS管分别构成CMOS反相器。
  12. 一种检测感应放大器失配的系统，包括：
    数据获取模块，用于获取测试数据组；
    数据转换模块，用于将所述测试数据组转换为位线与参考位线间第一电压差，输入至延迟PMOS管或NMOS管开启的感应放大器中进行持续预设时间的预充电，所述预设时间小于标准预充电时间，以及用于将预充电后的得到的所述位线与所述参考位线间第二电压差通过感应放大器进行放大，得到待测电压差；
    失配检测模块，用于将所述待测电压差与预设待测电压差进行比对，若所述待测电压差与所述预设待测电压差同向，则判断所述感应放大器失配。
  13. 根据权利要求12所述的检测感应放大器失配的系统，其中，所述数据获取模块还用于在获取测试数据组前，获取预设测试数据组。
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