WO2023071651A1 - 电路调整方法、装置、电子设备、存储介质及电路 - Google Patents

电路调整方法、装置、电子设备、存储介质及电路 Download PDF

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Publication number
WO2023071651A1
WO2023071651A1 PCT/CN2022/120966 CN2022120966W WO2023071651A1 WO 2023071651 A1 WO2023071651 A1 WO 2023071651A1 CN 2022120966 W CN2022120966 W CN 2022120966W WO 2023071651 A1 WO2023071651 A1 WO 2023071651A1
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Prior art keywords
data path
path circuit
circuit
delay
component
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PCT/CN2022/120966
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English (en)
French (fr)
Inventor
梁新理
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上海商汤智能科技有限公司
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Publication of WO2023071651A1 publication Critical patent/WO2023071651A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and in particular, relates to a circuit adjustment method, device, electronic equipment, computer-readable storage medium, and data path circuit.
  • An integrated circuit refers to a circuit with a specific function that integrates a certain number of commonly used electronic components, such as resistors, capacitors, transistors, etc., and the connections between these components, through a semiconductor process.
  • a chip is a general term for semiconductor component products, and is the carrier of an integrated circuit (IC), which is divided into wafers.
  • the present disclosure at least provides a circuit adjustment method, device, electronic equipment, computer-readable storage medium, and data path circuit.
  • the present disclosure provides a circuit adjustment method, including: determining a first data path circuit in an integrated circuit; wherein there are multiple target paths between different registers in the first data path circuit; based on the The device delay of the electronic components included in each of the target paths in the first data path circuit, and inserting a buffer into the first data path circuit to obtain a second data path circuit, wherein the second The delay of each target path in the data path circuit is consistent; the component adjustment operation is performed on the second data path circuit to obtain a third data path circuit; wherein, the first clock cycle corresponding to the third data path circuit is less than the second clock period corresponding to the second data path circuit, and in the third data path circuit, the delays of different input signals arriving at the same logic unit differ by integer multiples of the first clock period.
  • the second data path circuit is obtained, so that the second data path
  • the delays of the target paths in the circuit are consistent, which can avoid the generation of glitches in the second data path circuit, that is, avoid the generation of glitch power consumption, thus reducing the power consumption of the data path circuit.
  • the third data path circuit is obtained by performing component adjustment operations on the second data path circuit, wherein the delays of different input signals in the third data path circuit arriving at the same logic device differ by integer multiples of the first clock cycle, It can avoid glitch power consumption in the third data path circuit and reduce the static power consumption of the data path circuit. Therefore, on the basis of ensuring the low power consumption requirement of the data path circuit, the clock cycle of the third data path circuit is reduced. The clock frequency of the third data path circuit is increased, thereby ensuring the computing speed and computing capability of the integrated circuit.
  • a buffer is inserted in the first data path circuit based on the device delay of the electronic components included in each of the target paths in the first data path circuit
  • Obtaining the second data path circuit includes: determining each target in the first data path circuit based on the device delay of the electronic components included in each target path in the first data path circuit The path delay corresponding to the path; taking the maximum delay among the path delays corresponding to each of the target paths in the first data path circuit as the target delay; based on the target delay and the second A buffer is inserted into the first data path circuit for an intermediate delay between registers and logic devices included in each of the target paths in a data path circuit to obtain a second data path circuit.
  • a buffer is inserted in the first data path circuit to obtain the second data path circuit, In order to make the delays of the target paths in the second data path circuit consistent, thus avoiding the glitch power consumption of the data path circuit.
  • a first buffer exists between the input port of the first data path circuit and the first register, and a buffer exists between the second register of the first data path circuit and the output port.
  • performing a component adjustment operation on the second data path circuit includes: selecting a first component to be replaced and a second component to be replaced whose device delay matches the target delay, and replace the first buffer in the second data path circuit with the first component to be replaced and replace the second buffer in the second data path circuit with the second The components to be replaced obtain an intermediate data path circuit as an improved version of the second data path circuit.
  • the intermediate data path circuit is obtained by replacing the components of the first buffer and the second buffer, so that the intermediate data path circuit meets the circuit design requirements.
  • performing the component adjustment operation on the second data path circuit to obtain the third data path circuit includes: performing component replacement and component deletion on the second data path circuit At least one component adjustment operation of subtraction and component addition is performed to obtain the third data path circuit.
  • At least one component adjustment operation of component replacement, component deletion, and component addition can be performed on the second data path circuit to obtain the third data path circuit.
  • the types of component adjustment operations are relatively diverse, so that The third data path circuit is flexibly obtained.
  • the method further The method includes: selecting a third component to be replaced whose device delay matches the second clock cycle, and replacing the third buffer with the third component to be replaced to obtain a fourth data path circuit.
  • the method before determining the first data path circuit in the integrated circuit, the method further includes: using an integer linear programming method to calculate the initial device extension of each electronic component in the integrated circuit Integer processing is performed to obtain the device delay corresponding to an integer multiple of the target unit of each electronic component.
  • the integer linear programming method is used to integerize the initial device delay of each electronic component in the integrated circuit to obtain the integer corresponding to each electronic component times the device delay of the target unit, so that the device delay corresponding to each electronic component is an integer, so that the path delay of the target path can be determined more easily and quickly based on the device delay of each electronic component, and then The data path circuit can be adjusted more accurately based on the path delay to ensure that the adjusted data path circuit can meet the low power consumption requirement.
  • the present disclosure provides a circuit adjustment device, including: a determining module, configured to determine a first data path circuit in an integrated circuit; wherein, there are multiple registers between different registers in the first data path circuit Target path; a first adjustment module, configured to insert a buffer into the first data path circuit based on the device delay of the electronic components included in each of the target paths in the first data path circuit, to obtain The second data path circuit, wherein the delays of the target paths in the second data path circuit are consistent; the second adjustment module is configured to perform component adjustment operations on the second data path circuit to obtain the third A data path circuit; wherein the first clock cycle corresponding to the third data path circuit is less than the second clock cycle corresponding to the second data path circuit, and in the third data path circuit, different input signals arrive at the same
  • the difference between the delays of the logic unit is an integer multiple of the first clock period.
  • the first adjustment module is based on the device delay of the electronic components included in each of the target paths in the first data path circuit, and in the first data path
  • it is used to: determine the first data path based on the device delay of the electronic components included in each of the target paths in the first data path circuit The path delay corresponding to each of the target paths in the circuit; using the maximum delay among the path delays corresponding to each of the target paths in the first data path circuit as the target delay; based on the The target delay and the intermediate delay between the register and the logic included in each of the target paths in the first data path circuit, a buffer is inserted in the first data path circuit to obtain the second data access circuit.
  • a first buffer exists between the input port of the first data path circuit and the first register
  • a buffer exists between the second register of the first data path circuit and the output port.
  • the second adjustment module when performing component adjustment operations on the second data path circuit, is configured to: select the first to-be-replaced device whose delay matches the target delay component and a second component to be replaced, and replace the first buffer in the second data path circuit with the first component to be replaced and replace the second buffer with the first Two components to be replaced obtain an intermediate data path circuit as an improved version of the second data path circuit.
  • the second adjustment module is configured to: adjust the second data path circuit when performing a component adjustment operation on the second data path circuit to obtain a third data path circuit Perform at least one component adjustment operation of component replacement, component deletion, and component addition to obtain the third data path circuit.
  • the device further A replacement module is included, configured to: select a third component to be replaced whose device delay matches the second clock period, and replace the third buffer with the third component to be replaced to obtain fourth data access circuit.
  • the device before determining the first data path circuit in the integrated circuit, the device further includes a processing module, configured to: perform an integer linear programming method for each electronic element in the integrated circuit The initial device delay of the device is integerized to obtain the device delay corresponding to an integer multiple of the target unit of each electronic component.
  • the present disclosure provides a data path circuit, including: at least one component of a logic device, a register, and a buffer; wherein, the data path circuit is based on the first aspect or any implementation mode generated by the circuit tuning method.
  • the present disclosure provides an electronic device, including: a processor, a memory, and a bus, the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor The memory communicates with the memory through the bus, and when the machine-readable instructions are executed by the processor, the steps of the circuit adjustment method described in the first aspect or any implementation mode above are implemented.
  • the present disclosure provides an electronic device, including the data path circuit disclosed in the above third aspect.
  • the present disclosure provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is run by a processor, the circuit described in the above-mentioned first aspect or any implementation mode is executed. Steps in the tuning method.
  • FIG. 1 shows a schematic flowchart of a circuit adjustment method provided by an embodiment of the present disclosure
  • Fig. 2a shows a schematic diagram of a first data path circuit provided by an embodiment of the present disclosure
  • Fig. 2b shows a schematic diagram of a second data path circuit provided by an embodiment of the present disclosure
  • FIG. 2c shows a schematic diagram of an intermediate data path circuit provided by an embodiment of the present disclosure
  • Fig. 2d shows a schematic diagram of a third data path circuit provided by an embodiment of the present disclosure
  • FIG. 2e shows a schematic diagram of a fourth data path circuit provided by an embodiment of the present disclosure
  • FIG. 3 shows a schematic structural diagram of a circuit adjustment device provided by an embodiment of the present disclosure
  • Fig. 4 shows a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.
  • the power consumption of the chip is mainly divided into static power consumption and dynamic power consumption.
  • Static power consumption refers to the leakage power consumption when the circuit of the chip is maintained in an inactive state, that is, the power consumption without load;
  • dynamic power consumption is mainly the power consumption generated when the switch is flipped in response to input changes and/or glitches.
  • a glitch is a false flip experienced by a logic gate before reaching the steady-state value of the period. It is caused by the delay of the input path of the logic gate. The glitch not only has the risk of causing a chip function error, but also causes a loss of power consumption.
  • the embodiments of the present disclosure provide a circuit adjustment method, device, electronic equipment, computer-readable storage medium and data path circuit.
  • the execution body of the circuit adjustment method provided by the embodiments of the present disclosure may be a chip, a server, a terminal device, etc.
  • the terminal device may be a computer, a tablet, or the like.
  • FIG. 1 it is a schematic flowchart of a circuit adjustment method provided by an embodiment of the present disclosure.
  • the circuit adjustment method includes the following steps S101-S103.
  • the second data path circuit is obtained, so that the second data path
  • the delays of the target paths in the circuit are consistent, which can avoid the generation of glitches in the second data path circuit, that is, avoid the generation of glitch power consumption, thus reducing the power consumption of the data path circuit.
  • the third data path circuit is obtained by performing component adjustment operations on the second data path circuit, wherein the delays of different input signals in the third data path circuit arriving at the same logic device differ by integer multiples of the first clock cycle, It can avoid glitch power consumption in the third data path circuit and reduce the static power consumption of the data path circuit. Therefore, on the basis of ensuring the low power consumption requirement of the data path circuit, the clock cycle of the third data path circuit is reduced. The clock frequency of the third data path circuit is increased, thereby ensuring the computing speed and computing capability of the integrated circuit.
  • determining a first data path circuit in the integrated circuit where the first data path circuit may be the determined data path circuit to be adjusted. For example, a data path circuit with a glitch in the integrated circuit may be determined as the first data path circuit; and/or, a data path circuit with a relatively large delay in the integrated circuit may be determined as the first data path circuit.
  • the path through which data is transmitted between functional components is called a data path.
  • Functional components can be registers, logic devices, etc., and each functional component on the transmission path constitutes a data path circuit; a data path circuit with burrs For example, a circuit that can generate glitches due to inconsistent delays of input signals arriving from different paths to the same logic device.
  • FIG. 2a for a schematic diagram of a first data path circuit.
  • 2a includes buffer A, buffer B, AND gate logic C, AND gate logic D, buffer E, register R1, register R2 and register R3.
  • the first target path is: register R1>AND gate logic C>AND gate logic D>register R3;
  • the second target path is: register R2>buffer B>AND gate logic Device C>AND logic device D>register R3;
  • the third target path is: register R2>buffer B>AND logic device D>register R3.
  • the number corresponding to each electronic component in Fig. 2a indicates the device delay of the electronic component.
  • the method before determining the first data path circuit in the integrated circuit, further includes: using an integer linear programming method to calculate the initial device of each electronic component in the integrated circuit The delay is integerized to obtain the device delay corresponding to an integer multiple of the target unit for each electronic component.
  • the initial device delay of each electronic component is related to the performance and material of the electronic component.
  • the initial device delay of each electronic component can be determined in advance, and then the integer linear programming method is used to perform integer processing on the initial device delay of each electronic component to obtain the device corresponding to an integer multiple of the target unit of each electronic component Delay; and integer processing may be performed on the initial device delay of each candidate electronic component included in the component database to obtain a device delay corresponding to an integer multiple of the target unit of the candidate electronic component.
  • the initial device delay of electronic component 1 is 0.01s (seconds)
  • the initial device delay of electronic component 2 is 0.05s
  • the initial device delay of electronic component 3 is 0.07s
  • the device delay of electronic component 1 is 1 (indicating the device delay of 1 target unit)
  • the device delay of electronic component 2 is 5 (indicating the device delay of 5 target units)
  • the device of electronic component 3 The delay is 7 (representing a device delay of 7 target units), and each target unit is 0.01 seconds.
  • buffer A in Fig. 2a corresponds to a device delay of 3 target units.
  • the size of the target unit can be set according to the actual situation.
  • the integer linear programming method is used to integerize the initial device delay of each electronic component in the integrated circuit to obtain the integer corresponding to each electronic component times the device delay of the target unit, so that the device delay corresponding to each electronic component is an integer, so that the path delay of the target path can be determined more easily and quickly based on the device delay of each electronic component, and then The data path circuit can be adjusted more accurately based on the path delay, which ensures that the adjusted data path circuit can meet the low power consumption requirement.
  • the device delay based on the electronic components included in the target path in the first data path circuit is inserted into the first data path circuit
  • the buffer, to obtain the second data path circuit may include step A1-step A3.
  • Step A1 based on the device delay of the electronic components included in each of the target paths in the first data path circuit, determine the path delay corresponding to each of the target paths in the first data path circuit .
  • Step A2 taking the maximum delay among the path delays corresponding to each of the target paths in the first data path circuit as the target delay.
  • Step A3 inserting a buffer in the first data path circuit based on the target delay and the intermediate delay between the register and the logic included in each of the target paths in the first data path circuit , to obtain the second data path circuit.
  • the path delay of the target path can be determined according to the device delay of each electronic component included in the target path, and the path delay included in the first data path circuit can be obtained.
  • the path delay corresponding to each target path can further determine the maximum delay among the path delays corresponding to each target path in the first data path circuit, and use the maximum delay as the target delay.
  • the path delay of the first target path included in Figure 2a is 6 target units
  • the path delay of the second target path is 7 target units
  • the path delay of the third target path is 3 target units. Therefore, the path delay of the second target path is taken as the target delay, that is, the target delay is the delay of 7 target units.
  • An intermediate delay between registers and logic included in each target path in the first data path circuit is determined.
  • the intermediate delay between register R1 and AND gate logic C in Figure 2a is 0, the intermediate delay between register R2 and AND gate logic C is 1, and the intermediate delay between register R1 and AND gate logic D
  • the intermediate delay is 6, the intermediate delay of the first path between the register R2 and the AND logic device D is 7, and the intermediate delay of the second path is 3.
  • a buffer may be inserted into the first data path circuit to obtain a second data path circuit.
  • the buffer to be inserted into the first data path circuit may be selected from the component database according to performance information such as the size and device delay of each buffer stored in the component database.
  • the second data path circuit shown in Figure 2b is obtained, that is, a buffer with a device delay of 1 target unit is added to the first data path circuit a and the buffer b whose device delay is 4 target units make the delays of the target paths in the second data path circuit consistent, that is, the delays of the target paths are the target delays.
  • the second clock period of the second data path circuit shown in FIG. 2b is 7 target units.
  • a buffer is inserted in the first data path circuit to obtain the second data path circuit, In order to make the delays of the target paths in the second data path circuit consistent, thus avoiding the glitch power consumption of the data path circuit.
  • Step B1 selecting a first component to be replaced and a second component to be replaced whose component delay matches the target delay.
  • Step B2 replacing the first buffer in the second data path circuit with the first component to be replaced and replacing the second buffer with the second component to be replaced, to obtain an intermediate
  • the datapath circuit is an improved version of the second datapath circuit.
  • the first component to be replaced whose device delay matches the target delay can be selected from the component database, and the first buffer is replaced with the first component to be replaced; and the device delay is selected from the component database
  • the second component to be replaced matches the target delay, and the second buffer is replaced with the second component to be replaced.
  • the first buffer matches the size, performance, etc. of the first component to be replaced
  • the second buffer matches the size, performance, etc. of the second component to be replaced.
  • first buffer exists but the second buffer does not exist, select the first component to be replaced whose device delay matches the target delay from the component database, and replace the first buffer with the first component to be replaced ; If the second buffer exists but the first buffer does not exist, select the second component to be replaced whose device delay matches the target delay from the component database, and replace the second buffer with the second component to be replaced device.
  • the second data path circuit shown in FIG. 2b is taken as an example for illustration.
  • the second data path circuit in FIG. 2 b includes a first buffer A and a second buffer E, and the target delay is a delay of 7 target units.
  • the first buffer A can be replaced with the first component to be replaced A1 with a device delay of 7 target units
  • the second buffer E can be replaced with the second component to be replaced E1 with a device delay of 7 target units , to obtain the intermediate data path circuit shown in Figure 2c.
  • the intermediate data path circuit is obtained by replacing the components of the first buffer and the second buffer, so that the intermediate data path circuit meets the circuit design requirements, so as to ensure that the integrated circuit can work normally.
  • the performing the component adjustment operation on the second data path circuit to obtain the third data path circuit includes: performing component replacement on the second data path circuit, At least one component adjustment operation among deletion and component addition is performed to obtain a third data path circuit.
  • the input of the data path circuit is a clock signal, there is a certain clock cycle, and the clock cycle includes signals of multiple beats; in the data path circuit, if different signals input to the same logic device are of the same beat in the clock signal When different signals arrive at the same logic device with a difference of an integer multiple of the first clock period, the logic device in the data path circuit will not generate glitches.
  • at least one component adjustment operation of component replacement, component deletion, and component addition can be performed on the second data path circuit by using the method of clock deviation planning to obtain the third data path circuit.
  • the method of clock deviation planning is: the method of planning the clock cycle and components of the data path circuit with the goal that the delay of different input signals arriving at the same logic device differs by an integer multiple of the clock cycle.
  • the clock period is 4 seconds
  • the two signals input to the same logic device are the signal at the first second and the signal at the fifth second, then the signals input to the same logic device are the same signals in the clock signal A beat signal.
  • the target clock period (that is, the first clock period) may be determined, and at least one component adjustment operation of component replacement, component deletion, and component addition is performed on the second data path circuit or the intermediate data path circuit , to obtain the third data path circuit, so that the clock cycle of the third data path circuit is the target clock cycle.
  • the buffer A1 That is, the first component to be replaced (A1) is replaced with a buffer A2 with a device delay of 3 target units, and the buffer a is deleted to obtain a third data path circuit.
  • the first clock period of the third data path circuit is 4 target units. The first clock period of the third data path circuit may be determined according to the delay of each component included in the third data path circuit.
  • the delay for input signal 2 to reach AND gate logic D through the second path (buffer A2>register R2>buffer B>buffer b) is 8, and the delay for two input signals to reach AND gate logic D
  • the phase difference is 4, that is, the delay difference between different input signals arriving at the AND gate logic device D is 1 time of the first clock period.
  • At least one component adjustment operation of component replacement, component deletion, and component addition can be performed on the second data path circuit to obtain the third data path circuit.
  • the types of component adjustment operations are relatively diverse, so that The third data path circuit is flexibly obtained.
  • the method it also includes: selecting a third component to be replaced whose device delay matches the second clock period, and replacing the third buffer with the third component to be replaced to obtain a fourth data path circuit.
  • the third data path circuit shown in FIG. 2d is taken as an example for illustration.
  • the third data path circuit includes the third buffer E1
  • the third component to be replaced E2 whose device delay matches the second clock cycle can be selected from the component database, and the third buffer E1 can be replaced with the first Three to-be-replaced components E2 are obtained to obtain the fourth data path circuit as shown in FIG.
  • the writing order of each step does not mean a strict execution order and constitutes any limitation on the implementation process.
  • the specific execution order of each step should be based on its function and possible
  • the inner logic is OK.
  • the embodiment of the present disclosure also provides a circuit adjustment device.
  • the circuit adjustment device includes a determination module 301 , a first adjustment module 302 and a second adjustment module 303 .
  • the determination module 301 is configured to determine a first data path circuit in the integrated circuit; wherein there are multiple target paths between different registers in the first data path circuit.
  • the first adjustment module 302 is configured to insert a buffer into the first data path circuit based on the device delay of the electronic components included in each of the target paths in the first data path circuit to obtain the second data A path circuit, wherein the delays of the target paths in the second data path circuit are consistent.
  • the second adjustment module 303 is configured to perform component adjustment operations on the second data path circuit to obtain a third data path circuit; wherein, the first clock period corresponding to the third data path circuit is shorter than that of the second data path circuit
  • the circuit corresponds to the second clock period, and in the third data path circuit, the delays of different input signals arriving at the same logic unit differ by integer multiples of the first clock period.
  • the first adjustment module 302 based on the device delay of the electronic components included in each of the target paths in the first data path circuit, in the first data path
  • it is used to: determine the first data path based on the device delay of the electronic components included in each of the target paths in the first data path circuit The path delay corresponding to each of the target paths in the path circuit; taking the maximum delay among the path delays corresponding to each of the target paths in the first data path circuit as the target delay; based on The target delay and the intermediate delay between the register and the logic included in each of the target paths in the first data path circuit, a buffer is inserted in the first data path circuit to obtain the second data path circuit.
  • a first buffer exists between the input port of the first data path circuit and the first register, and a buffer exists between the second register of the first data path circuit and the output port.
  • the second adjustment module 303 is configured to: select the first waiting time that the device delay matches the target delay when performing the component adjustment operation on the second data path circuit. replacing the component and the second component to be replaced, replacing the first buffer in the second data path circuit with the first component to be replaced and replacing all the components in the second data path circuit The second buffer is replaced with the second component to be replaced, and an intermediate data path circuit is obtained as an improved version of the second data path circuit.
  • the second adjustment module 303 when performing component adjustment operations on the second data path circuit to obtain a third data path circuit, is configured to: The circuit performs at least one component adjustment operation among component replacement, component deletion, and component addition to obtain a third data path circuit.
  • the device further Including: a replacement module 304, configured to select a third component to be replaced whose device delay matches the second clock cycle, and replace the third buffer with the third component to be replaced, to obtain a fourth data path circuit.
  • a replacement module 304 configured to select a third component to be replaced whose device delay matches the second clock cycle, and replace the third buffer with the third component to be replaced, to obtain a fourth data path circuit.
  • the device before determining the first data path circuit in the integrated circuit, the device further includes: a processing module 305, configured to use an integer linear programming method to The initial device delay of the components is integerized to obtain the device delay corresponding to the integer multiple of the target unit of each electronic component.
  • a processing module 305 configured to use an integer linear programming method to The initial device delay of the components is integerized to obtain the device delay corresponding to the integer multiple of the target unit of each electronic component.
  • an embodiment of the present disclosure also provides a data path circuit, including: at least one component of a logic device, a register, and a buffer; wherein, the data path circuit is based on the above-mentioned implementation mode generated by the circuit tuning method.
  • the functions of the device provided by the embodiments of the present disclosure or the included templates can be used to execute the methods described in the above method embodiments, and its specific implementation can refer to the description of the above method embodiments. For brevity, here No longer.
  • an embodiment of the present disclosure also provides an electronic device.
  • the electronic device includes a processor 401 , a memory 402 and a bus 403 .
  • the memory 402 is used to store execution instructions, including a memory 4021 and an external memory 4022; the memory 4021 here is also called an internal memory, and is used to temporarily store the calculation data in the processor 401 and the data exchanged with the external memory 4022 such as a hard disk.
  • the processor 401 exchanges data with the external memory 4022 through the memory 4021.
  • the processor 401 communicates with the memory 402 through the bus 403, so that the processor 401 executes the following instructions: determine the first data in the integrated circuit A path circuit; wherein, there are multiple target paths between different registers in the first data path circuit; based on the device delay of the electronic components included in each of the target paths in the first data path circuit, A buffer is inserted into the first data path circuit to obtain a second data path circuit, wherein the delays of the target paths in the second data path circuit are consistent; A device adjustment operation to obtain a third data path circuit; wherein, the first clock cycle corresponding to the third data path circuit is smaller than the second clock cycle corresponding to the second data path circuit, and the third data path circuit Among them, the delays of different input signals arriving at the same logic device differ by integer multiples of the first clock cycle.
  • an embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the circuit adjustment method described in the above-mentioned method embodiments are executed.
  • the storage medium may be a volatile or non-volatile computer-readable storage medium.
  • the embodiment of the present disclosure also provides a computer program product, the computer program product carries a program code, and the instructions included in the program code can be used to execute the steps of the circuit adjustment method described in the above method embodiment, for details, please refer to the above method The embodiment will not be repeated here.
  • the above-mentioned computer program product may be specifically implemented by means of hardware, software or a combination thereof.
  • the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK) etc. wait.
  • a software development kit Software Development Kit, SDK
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor.
  • the technical solution of the present disclosure is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present disclosure.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

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Abstract

本公开提供了一种电路调整方法、装置、电子设备、存储介质及电路。该方法包括：确定集成电路中的第一数据通路电路；其中，所述第一数据通路电路中的不同寄存器之间存在多条目标通路；基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路，其中，所述第二数据通路电路中的各条目标通路的延时一致；对所述第二数据通路电路进行元器件调整操作，得到第三数据通路电路；其中，所述第三数据通路电路对应的第一时钟周期小于所述第二数据通路电路对应的第二时钟周期，并且在所述第三数据通路电路中，不同输入信号到达同一逻辑器的延时相差所述第一时钟周期的整数倍。

Description

电路调整方法、装置、电子设备、存储介质及电路
交叉引用声明
本申请要求于2021年10月29日提交中国专利局的申请号为202111275866.X的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及集成电路技术领域，具体而言，涉及一种电路调整方法、装置、电子设备、计算机可读存储介质及数据通路电路。
背景技术
随着科技的进步，集成电路在快速发展。集成电路是指把一定数量的常用电子元件，如电阻、电容、晶体管等，以及这些元件之间的连线，通过半导体工艺集成在一起的具有特定功能的电路。芯片是半导体元件产品的统称，是集成电路(integrated circuit，IC)的载体，由晶圆分割而成。
随着芯片的集成度越来越高，算力也越来越强，使得芯片的低功耗设计也越来越受到重视。因此，提出一种降低芯片功耗的电路调整方法尤为重要。
发明内容
有鉴于此，本公开至少提供一种电路调整方法、装置、电子设备、计算机可读存储介质及数据通路电路。
第一方面，本公开提供了一种电路调整方法，包括：确定集成电路中的第一数据通路电路；其中，所述第一数据通路电路中的不同寄存器之间存在多条目标通路；基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路，其中，所述第二数据通路电路中的各条目标通路的延时一致；对所述第二数据通路电路进行元器件调整操作，得到第三数据通路电路；其中，所述第三数据通路电路对应的第一时钟周期小于所述第二数据通路电路对应的第二时钟周期，并且在所述第三数据通路电路中，不同输入信号到达同一逻辑器的延时相差所述第一时钟周期的整数倍。
上述方法中，通过基于第一数据通路电路中的各条目标通路包括的电子元器件的器件延时，在第一数据通路电路中插入缓冲器，得到第二数据通路电路，使得第二数据通路电路中的各条目标通路的延时一致，能够避免第二数据通路电路中产生毛刺，即避免毛刺功耗的生成，因此，减少了数据通路电路的功耗。
进一步的，通过对第二数据通路电路进行元器件调整操作，得到第三数据通路电路，其中，第三数据通路电路中不同输入信号到达同一逻辑器的延时相差第一时钟周期的整数倍，能够避免第三数据通路电路中产生毛刺功耗，并减低数据通路电路的静态功耗，因此，在保障数据通路电路的低功耗要求的基础上，降低了第三数据通路电路的时钟周期，提高了第三数据通路电路的时钟频率，进而保障了集成电路的运算速度和运算能力。
在一种可能的实施方式中，所述基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路，包括：基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，确定所述第一数据通路电路中的各条所述目标通路对应的通路延时；将所述第一数据通路电路中的各条所述目标通路对应的所述通路延时中的最大延时作为目标延时；基于所述目标延时以及所述第一数据通路电路中的各条所述目标通路包括的寄存器至逻辑器之间的中间延时，在所述第一数据通路电路中插入缓冲器，得到第二数据 通路电路。
这里，可以基于目标延时和第一数据通路电路中的各条目标通路包括的寄存器至逻辑器之间的中间延时，在第一数据通路电路中插入缓冲器，得到第二数据通路电路，以使得第二数据通路电路中的各条目标通路的延时一致，因此，避免了数据通路电路产生毛刺功耗。
在一种可能的实施方式中，在所述第一数据通路电路的输入端口与第一寄存器之间存在第一缓冲器以及在所述第一数据通路电路的第二寄存器与输出端口之间存在第二缓冲器的情况下，对所述第二数据通路电路进行元器件调整操作，包括：选取器件延时与所述目标延时匹配的第一待替换元器件和第二待替换元器件，并将所述第二数据通路电路中的所述第一缓冲器替换为所述第一待替换元器件和将所述第二数据通路电路中的所述第二缓冲器替换为所述第二待替换元器件，得到中间数据通路电路作为所述第二数据通路电路的改进版本。
这里，通过对第一缓冲器和第二缓冲器进行元器件替换，得到中间数据通路电路，使得中间数据通路电路满足电路设计要求。
在一种可能的实施方式中，所述对所述第二数据通路电路进行元器件调整操作，得到第三数据通路电路，包括：对所述第二数据通路电路进行元器件替换、元器件删减、元器件增加中的至少一种元器件调整操作，得到所述第三数据通路电路。
这里，可以对第二数据通路电路进行元器件替换、元器件删减、元器件增加中的至少一种元器件调整操作，得到第三数据通路电路，元器件调整操作的类型较为多样，以便可以灵活的得到第三数据通路电路。
在一种可能的实施方式中，在所述第三数据通路电路的第三寄存器与输出端口之间存在第三缓冲器的情况下，在所述得到第三数据通路电路之后，所述方法还包括：选取器件延时与所述第二时钟周期匹配的第三待替换元器件，并将所述第三缓冲器替换为所述第三待替换元器件，得到第四数据通路电路。
在一种可能的实施方式中，在确定集成电路中的第一数据通路电路之前，所述方法还包括：利用整数线性规划方法，对所述集成电路中的每个电子元器件的初始器件延时进行整数化处理，得到所述每个电子元器件对应的整数倍目标单位的器件延时。
这里，在确定集成电路中的第一数据通路电路之前，利用整数线性规划方法，对集成电路中的每个电子元器件的初始器件延时进行整数化处理，得到每个电子元器件对应的整数倍目标单位的器件延时，使得每个电子元器件对应的器件延时为整数，以便后续可以基于每个电子元器件的器件延时较简便和较快速的确定目标通路的通路延时，进而可以基于通路延时较为准确的调整数据通路电路，保障调整后的数据通路电路能够满足低功耗要求。
以下装置、电子设备等的效果描述参见上述方法的说明，这里不再赘述。
第二方面，本公开提供了一种电路调整装置，包括：确定模块，用于确定集成电路中的第一数据通路电路；其中，所述第一数据通路电路中的不同寄存器之间存在多条目标通路；第一调整模块，用于基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路，其中，所述第二数据通路电路中的各条目标通路的延时一致；第二调整模块，用于对所述第二数据通路电路进行元器件调整操作，得到第三数据通路电路；其中，所述第三数据通路电路对应的第一时钟周期小于所述第二数据通路电路对应的第二时钟周期，并且在所述第三数据通路电路中，不同输入信号到达同一逻辑器的延时相差所述第一时 钟周期的整数倍。
在一种可能的实施方式中，所述第一调整模块，在基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路时，用于：基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，确定所述第一数据通路电路中的各条所述目标通路对应的通路延时；将所述第一数据通路电路中的各条所述目标通路对应的所述通路延时中的最大延时作为目标延时；基于所述目标延时以及所述第一数据通路电路中的各条所述目标通路包括的寄存器至逻辑器之间的中间延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路。
在一种可能的实施方式中，在所述第一数据通路电路的输入端口与第一寄存器之间存在第一缓冲器以及在所述第一数据通路电路的第二寄存器与输出端口之间存在第二缓冲器的情况下，所述第二调整模块，在对所述第二数据通路电路进行元器件调整操作时，用于：选取器件延时与所述目标延时匹配的第一待替换元器件和第二待替换元器件，并将所述第二数据通路电路中的所述第一缓冲器替换为所述第一待替换元器件和将所述第二缓冲器替换为所述第二待替换元器件，得到中间数据通路电路作为所述第二数据通路电路的改进版本。
在一种可能的实施方式中，所述第二调整模块，在对所述第二数据通路电路进行元器件调整操作，得到第三数据通路电路时，用于：对所述第二数据通路电路进行元器件替换、元器件删减、元器件增加中的至少一种元器件调整操作，得到所述第三数据通路电路。
在一种可能的实施方式中，在所述第三数据通路电路的第三寄存器与输出端口之间存在第三缓冲器的情况下，在所述得到第三数据通路电路之后，所述装置还包括替换模块，用于：选取器件延时与所述第二时钟周期匹配的第三待替换元器件，并将所述第三缓冲器替换为所述第三待替换元器件，得到第四数据通路电路。
在一种可能的实施方式中，在确定集成电路中的第一数据通路电路之前，所述装置还包括处理模块，用于：利用整数线性规划方法，对所述集成电路中的每个电子元器件的初始器件延时进行整数化处理，得到所述每个电子元器件对应的整数倍目标单位的器件延时。
第三方面，本公开提供一种数据通路电路，包括：逻辑器、寄存器、缓冲器中的至少一种元器件；其中，所述数据通路电路为基于第一方面或任一实施方式所述的电路调整方法生成的。
第四方面，本公开提供一种电子设备，包括：处理器、存储器和总线，所述存储器存储有所述处理器可执行的机器可读指令，当所述电子设备运行时，所述处理器与所述存储器之间通过所述总线通信，所述机器可读指令被所述处理器执行时实现如上述第一方面或任一实施方式所述的电路调整方法的步骤。
第五方面，本公开提供一种电子设备，包括上述第三方面公开的数据通路电路。
第六方面，本公开提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器运行时执行如上述第一方面或任一实施方式所述的电路调整方法的步骤。
为使本公开的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍。这些附图示出了符合本公开的实施例，并与说明书一起用于说明本公开的技术方案。应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1示出了本公开实施例所提供的一种电路调整方法的流程示意图；
图2a示出了本公开实施例所提供的一种第一数据通路电路的示意图；
图2b示出了本公开实施例所提供的一种第二数据通路电路的示意图；
图2c示出了本公开实施例所提供的一种中间数据通路电路的示意图；
图2d示出了本公开实施例所提供的一种第三数据通路电路的示意图；
图2e示出了本公开实施例所提供的一种第四数据通路电路的示意图；
图3示出了本公开实施例所提供的一种电路调整装置的架构示意图；
图4示出了本公开实施例所提供的一种电子设备的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。因此，以下对在附图中提供的本公开的实施例的详细描述无意限制要求保护的本公开的范围。基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
随着芯片的集成度越来越高，算力也越来越强，使得芯片的低功耗设计也越来越受到重视。其中，芯片的功耗主要分为静态功耗和动态功耗。静态功耗是指芯片的电路维持在未激活状态时的漏电功耗，即没有负载情况下的功耗；动态功耗主要是由响应输入变化和/或毛刺引起开关翻转时产生的功耗。毛刺是逻辑门在达到周期的稳态值之前所经历的虚假翻转，是由于逻辑门输入路径的延迟不同而引起的，毛刺不仅有引起芯片功能错误的风险，还会造成功耗的损失。
为了减少芯片的功耗，本公开实施例提供了一种电路调整方法、装置、电子设备、计算机可读存储介质及数据通路电路。
针对以上方案所存在的缺陷，均是发明人在经过实践并仔细研究后得出的结果，因此，上述问题的发现过程以及下文中本公开针对上述问题所提出的解决方案，都应该是发明人在本公开过程中对本公开做出的贡献。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
为便于对本公开实施例进行理解，首先对本公开实施例所公开的一种电路调整方法进行详细介绍。本公开实施例所提供的电路调整方法的执行主体可以为芯片、服务器、终端设备等，比如，终端设备可以为计算机、平板等设备。
参见图1所示，为本公开实施例所提供的电路调整方法的流程示意图。该电路调整方法包括以下步骤S101-S103。
S101，确定集成电路中的第一数据通路电路；其中，所述第一数据通路电路中的不同寄存器之间存在多条目标通路。
S102，基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路，其中，所述第二数据通路电路中的各条目标通路的延时一致。
S103，对所述第二数据通路电路进行元器件调整操作，得到第三数据通路电路；其中，所述第三数据通路电路对应的第一时钟周期小于所述第二数据通路电路对应的第二时钟周期，并且在所述第三数据通路电路中，不同输入信号到达同一逻辑器的延时相差所述第一时钟周期的整数倍。
上述方法中，通过基于第一数据通路电路中的各条目标通路包括的电子元器件的器件延时，在第一数据通路电路中插入缓冲器，得到第二数据通路电路，使得第二数据通路电路中的各条目标通路的延时一致，能够避免第二数据通路电路中产生毛刺，即避免毛刺功耗的生成，因此，减少了数据通路电路的功耗。
进一步的，通过对第二数据通路电路进行元器件调整操作，得到第三数据通路电路，其中，第三数据通路电路中不同输入信号到达同一逻辑器的延时相差第一时钟周期的整数倍，能够避免第三数据通路电路中产生毛刺功耗，并减低数据通路电路的静态功耗，因此，在保障数据通路电路的低功耗要求的基础上，降低了第三数据通路电路的时钟周期，提高了第三数据通路电路的时钟频率，进而保障了集成电路的运算速度和运算能力。
下述对S101至S103进行具体说明。
针对S101：确定集成电路中的第一数据通路电路，其中，第一数据通路电路可以为确定的待调整的数据通路电路。比如，可以将集成电路中存在毛刺的数据通路电路确定为第一数据通路电路；和/或，可以将集成电路中延时较大的数据通路电路确定为第一数据通路电路等。其中，数据在功能部件之间传送的路径称为数据通路，功能部件(元器件)比如可以为寄存器、逻辑器等，传送路径上的各个功能部件构成了数据通路电路；存在毛刺的数据通路电路比如可以为从不同路径到达同一逻辑器的输入信号的延时不一致而产生毛刺的电路。
其中，第一数据通路电路中的不同寄存器之间存在多条目标通路，第一数据通路电路的电路结构可以根据实际情况进行选取。参见图2a所示的一种第一数据通路电路的示意图。图2a中包括缓冲器A、缓冲器B、与门逻辑器C、与门逻辑器D、缓冲器E、寄存器R1、寄存器R2和寄存器R3。图2a中存在三条目标通路，第一条目标通路为：寄存器R1>与门逻辑器C>与门逻辑器D>寄存器R3；第二条目标通路为：寄存器R2>缓冲器B>与门逻辑器C>与门逻辑器D>寄存器R3；第三条目标通路为：寄存器R2>缓冲器B>与门逻辑器D>寄存器R3。图2a中的每个电子元器件对应的数字表示该电子元器件的器件延时。
在一种可选的实施方式中，在确定集成电路中的第一数据通路电路之前，所述方法还包括：利用整数线性规划方法，对所述集成电路中的每个电子元器件的初始器件延时进行整数化处理，得到每个电子元器件对应的整数倍目标单位的器件延时。
实施时，每个电子元器件的初始器件延时与电子元器件的性能、材质等相关。可以预先确定每个电子元器件的初始器件延时，再利用整数线性规划方法，对每个电子元器件的初始器件延时进行整数处理，得到每个电子元器件对应的整数倍目标单位的器件延时；以及还可以对元器件数据库中包括的每个候选电子元器件的初始器件延时进行整数处理，得到候选电子元器件对应的整数倍目标单位的器件延时。
比如，电子元器件1的初始器件延时为0.01s(秒)，电子元器件2的初始器件延时为0.05s，电子元器件3的初始器件延时为0.07s，则整数处理后，得到电子元器件1的器件延时为1(表示1个目标单位的器件延时)，电子元器件2的器件延时为5(表示5个目标单位的器件延时)，电子元器件3的器件延时为7(表示7个目标单位的器件延时)，每个目标单位为0.01秒。
可知，图2a中的缓冲器A对应有3个目标单位的器件延时。其中，目标单位的大小可以根据实际情况进行设置。
这里，在确定集成电路中的第一数据通路电路之前，利用整数线性规划方法，对集成电路中的每个电子元器件的初始器件延时进行整数化处理，得到每个电子元器件对应的整数倍目标单位的器件延时，使得每个电子元器件对应的器件延时为整数，以便后续可以基于每个电子元器件的器件延时较简便和较快速的确定目标通路的通路延时，进而可以基于通路延时较为准确的调整数据通路电路，保障了调整后的数据通路电路能够满足低功耗要求。
针对S102：在不同输入信号到达同一逻辑器的延时不同时，逻辑器会产生毛刺，使得电路存在毛刺功耗。故可以在电路中插入缓冲器，以避免毛刺的产生，从而减少电路产生的毛刺功耗。
在一种可选的实施方式中，在S102中，所述基于所述第一数据通路电路中的所述目标通路包括的电子元器件的器件延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路，可以包括步骤A1-步骤A3。
步骤A1，基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，确定所述第一数据通路电路中的各条所述目标通路对应的通路延时。
步骤A2，将所述第一数据通路电路中的各条所述目标通路对应的所述通路延时中的最大延时作为目标延时。
步骤A3，基于所述目标延时以及所述第一数据通路电路中的各条所述目标通路包括的寄存器至逻辑器之间的中间延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路。
实施时，针对第一数据通路电路中的每条目标通路，可以根据该目标通路中包括的各个电子元器件的器件延时确定该目标通路的通路延时，得到第一数据通路电路中包括的各条目标通路对应的通路延时，进而可以确定第一数据通路电路中各条目标通路对应的通路延时中的最大延时，并将该最大延时作为目标延时。
在第一数据通路电路为图2a所示的数据通路电路时，可知，图2a中包括的第一条目标通路的通路延时为6个目标单位，第二条目标通路的通路延时为7个目标单位，第三条目标通路的通路延时为3个目标单位。因此，将第二条目标通路的通路延时作为目标延时，即目标延时为7个目标单位的延时。
确定第一数据通路电路中的各条目标通路包括的寄存器至逻辑器之间的中间延时。比如，图2a中的寄存器R1至与门逻辑器C之间的中间延时为0，寄存器R2至与门逻辑器C之间的中间延时为1，寄存器R1至与门逻辑器D之间的中间延时为6，寄存器R2至与门逻辑器D之间的第一通路的中间延时为7、第二通路的中间延时为3。
进而可以基于目标延时和各个中间延时，在第一数据通路电路中插入缓冲器，得到第二数据通路电路。其中，可以根据元器件数据库中存储的各个缓冲器的尺寸、器件延时等性能信息，从元器件数据库中选取待插入第一数据通路电路中的缓冲器。
比如，在对图2a中的第一数据通路电路进行调整后，得到如图2b所示第二数据通 路电路，即在第一数据通路电路中添加了器件延时为1个目标单位的缓冲器a和器件延时为4个目标单位的缓冲器b，使得第二数据通路电路中的各条目标通路的延时一致，即各条目标通路的延时为目标延时。其中，图2b所示的第二数据通路电路的第二时钟周期为7个目标单位。
这里，可以基于目标延时和第一数据通路电路中的各条目标通路包括的寄存器至逻辑器之间的中间延时，在第一数据通路电路中插入缓冲器，得到第二数据通路电路，以使得第二数据通路电路中的各条目标通路的延时一致，因此，避免了数据通路电路产生毛刺功耗。
针对S103：在一种可选的实施方式中，在所述第一数据通路电路的输入端口与第一寄存器之间存在第一缓冲器以及在所述第一数据通路电路的第二寄存器与输出端口之间存在第二缓冲器的情况下，对所述第二数据通路电路进行元器件调整操作，包括步骤B1和步骤B2。
步骤B1，选取器件延时与所述目标延时匹配的第一待替换元器件和第二待替换元器件。
步骤B2，将所述第二数据通路电路中的所述第一缓冲器替换为所述第一待替换元器件和将所述第二缓冲器替换为所述第二待替换元器件，得到中间数据通路电路作为所述第二数据通路电路的改进版本。
实施时，可以从元器件数据库中选取器件延时与目标延时匹配的第一待替换元器件，将第一缓冲器替换为第一待替换元器件；以及从元器件数据库中选取器件延时与目标延时匹配的第二待替换元器件，将第二缓冲器替换为第二待替换元器件。其中，第一缓冲器与第一待替换元器件的尺寸、性能等相匹配，第二缓冲器与第二待替换元器件的尺寸、性能等相匹配。
若存在第一缓冲器但不存在第二缓冲器，则从元器件数据库中选取器件延时与目标延时匹配的第一待替换元器件，将第一缓冲器替换为第一待替换元器件；若存在第二缓冲器但不存在第一缓冲器，则从元器件数据库中选取器件延时与目标延时匹配的第二待替换元器件，将第二缓冲器替换为第二待替换元器件。
以图2b中展示的第二数据通路电路为例进行说明。图2b中的第二数据通路电路中包括第一缓冲器A和第二缓冲器E，目标延时为7个目标单位的延时。可以将第一缓冲器A替换为器件延时为7个目标单位的第一待替换元器件A1，将第二缓冲器E替换为器件延时为7个目标单位的第二待替换元器件E1，得到如图2c所示的中间数据通路电路。
这里，通过对第一缓冲器和第二缓冲器进行元器件替换，得到中间数据通路电路，使得中间数据通路电路满足电路设计要求，以保障集成电路能够正常工作。
在一种可选的实施方式中，所述对所述第二数据通路电路进行元器件调整操作，得到第三数据通路电路，包括：对所述第二数据通路电路进行元器件替换、元器件删减、元器件增加中的至少一种元器件调整操作，得到第三数据通路电路。
由于数据通路电路的输入为时钟信号，存在一定的时钟周期，时钟周期内包括多个节拍的信号；而在数据通路电路中，若输入到同一逻辑器件的不同信号是时钟信号中同一个节拍的信号(即不同信号到达同一逻辑器件的延时相差第一时钟周期的整数倍)时，数据通路电路中的该逻辑器件不会产生毛刺。基于此，可以利用时钟偏差规划的方法，对第二数据通路电路进行元器件替换、元器件删减、元器件增加中的至少一种元器件调整操作，得到第三数据通路电路。其中，时钟偏差规划的方法为：以不同输入信号 到达同一逻辑器件的延时相差时钟周期的整数倍为目标，对数据通路电路的时钟周期和元器件进行规划的方法。
示例性的，在时钟周期为4秒，若输入至同一逻辑器件的两个信号为第1秒时的信号和第5秒时的信号，则输入到同一逻辑器件的信号是时钟信号中的同一个节拍的信号。
比如，可以确定目标时钟周期(即第一时钟周期)，通过对第二数据通路电路或者对中间数据通路电路进行元器件替换、元器件删减、元器件增加中的至少一种元器件调整操作，得到第三数据通路电路，以使得第三数据通路电路的时钟周期为目标时钟周期。
对图2c所示的中间数据通路电路进行至少一种元器件调整操作，得到的第三数据通路电路如图2d所示，比如，可以将图2c中的中间数据通路电路中的缓冲器A1(即第一待替换元器件A1)替换为器件延时为3个目标单位的缓冲器A2，将缓冲器a删减，得到第三数据通路电路。其中，该第三数据通路电路的第一时钟周期为4个目标单位。第三数据通路电路的第一时钟周期可以根据第三数据通路电路中包括的各个元器件的延时进行确定。
由图2d可知，输入信号1到达与门逻辑器C的延时为0，输入信号2到达与门逻辑器C的延时为4，两个输入信号到达与门逻辑器C的延时相差为4，即不同输入信号到达与门逻辑器C的延时相差为第一时钟周期的1倍。输入信号1到达与门逻辑器D的延时为4，输入信号2经过第一通路(缓存器A2>寄存器R2>缓冲器B>与门逻辑器C)到达与门逻辑器D的延时为8，输入信号2经过第二通路(缓存器A2>寄存器R2>缓冲器B>缓冲器b)到达与门逻辑器D的延时为8，两个输入信号到达与门逻辑器D的延时相差为4，即不同输入信号到达与门逻辑器D的延时相差为第一时钟周期的1倍。
这里，可以对第二数据通路电路进行元器件替换、元器件删减、元器件增加中的至少一种元器件调整操作，得到第三数据通路电路，元器件调整操作的类型较为多样，以便可以灵活的得到第三数据通路电路。
在一种可选的实施方式中，在所述第三数据通路电路的第三寄存器与输出端口之间存在第三缓冲器的情况下，在所述得到第三数据通路电路之后，所述方法还包括：选取器件延时与所述第二时钟周期匹配的第三待替换元器件，并将所述第三缓冲器替换为所述第三待替换元器件，得到第四数据通路电路。
以图2d所示的第三数据通路电路为例进行说明。在第三数据通路电路中包括第三缓冲器E1时，可以从元器件数据库中选取器件延时与第二时钟周期匹配的第三待替换元器件E2，并将第三缓冲器E1替换为第三待替换元器件E2，得到如图2e所示的第四数据通路电路，以保障集成电路中与第四数据通路电路的第三待替换元器件相连的其他数据通路电路能够正常工作。
本领域技术人员可以理解，在具体实施方式的上述方法中，各步骤的撰写顺序并不意味着严格的执行顺序而对实施过程构成任何限定，各步骤的具体执行顺序应当以其功能和可能的内在逻辑确定。
基于相同的构思，本公开实施例还提供了一种电路调整装置。参见图3所示，为本公开实施例提供的电路调整装置的架构示意图，该电路调整装置包括确定模块301、第一调整模块302和第二调整模块303。
确定模块301用于确定集成电路中的第一数据通路电路；其中，所述第一数据通路电路中的不同寄存器之间存在多条目标通路。
第一调整模块302用于基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路，其中，所述第二数据通路电路中的各条目标通路的延时一致。
第二调整模块303用于对所述第二数据通路电路进行元器件调整操作，得到第三数据通路电路；其中，所述第三数据通路电路对应的第一时钟周期小于所述第二数据通路电路对应的第二时钟周期，并且在所述第三数据通路电路中，不同输入信号到达同一逻辑器的延时相差所述第一时钟周期的整数倍。
在一种可能的实施方式中，所述第一调整模块302，在基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路时，用于：基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，确定所述第一数据通路电路中的各条所述目标通路对应的通路延时；将所述第一数据通路电路中的各条所述目标通路对应的所述通路延时中的最大延时作为目标延时；基于所述目标延时以及所述第一数据通路电路中的各条所述目标通路包括的寄存器至逻辑器之间的中间延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路。
在一种可能的实施方式中，在所述第一数据通路电路的输入端口与第一寄存器之间存在第一缓冲器以及在所述第一数据通路电路的第二寄存器与输出端口之间存在第二缓冲器的情况下，所述第二调整模块303，在对所述第二数据通路电路进行元器件调整操作时，用于：选取器件延时与所述目标延时匹配的第一待替换元器件和第二待替换元器件，并将所述第二数据通路电路中的所述第一缓冲器替换为所述第一待替换元器件和将所述第二数据通路电路中的所述第二缓冲器替换为所述第二待替换元器件，得到中间数据通路电路作为所述第二数据通路电路的改进版本。
在一种可能的实施方式中，所述第二调整模块303，在对所述第二数据通路电路进行元器件调整操作，得到第三数据通路电路时，用于：对所述第二数据通路电路进行元器件替换、元器件删减、元器件增加中的至少一种元器件调整操作，得到第三数据通路电路。
在一种可能的实施方式中，在所述第三数据通路电路的第三寄存器与输出端口之间存在第三缓冲器的情况下，在所述得到第三数据通路电路之后，所述装置还包括：替换模块304，用于选取器件延时与所述第二时钟周期匹配的第三待替换元器件，并将所述第三缓冲器替换为所述第三待替换元器件，得到第四数据通路电路。
在一种可能的实施方式中，在确定集成电路中的第一数据通路电路之前，所述装置还包括：处理模块305，用于利用整数线性规划方法，对所述集成电路中的每个电子元器件的初始器件延时进行整数化处理，得到所述每个电子元器件对应的整数倍目标单位的器件延时。
基于相同的构思，本公开实施例还提供了一种数据通路电路，包括：逻辑器、寄存器、缓冲器中的至少一种元器件；其中，所述数据通路电路为基于上述实施方式所述的电路调整方法生成的。
在一些实施例中，本公开实施例提供的装置具有的功能或包含的模板可以用于执行上文方法实施例描述的方法，其具体实现可以参照上文方法实施例的描述，为了简洁，这里不再赘述。
基于同一技术构思，本公开实施例还提供了一种电子设备。参照图4所示，为本公开实施例提供的电子设备的结构示意图，该电子设备包括处理器401、存储器402和总线403。其中，存储器402用于存储执行指令，包括内存4021和外部存储器4022； 这里的内存4021也称内存储器，用于暂时存放处理器401中的运算数据，以及与硬盘等外部存储器4022交换的数据，处理器401通过内存4021与外部存储器4022进行数据交换，当电子设备400运行时，处理器401与存储器402之间通过总线403通信，使得处理器401执行以下指令：确定集成电路中的第一数据通路电路；其中，所述第一数据通路电路中的不同寄存器之间存在多条目标通路；基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路，其中，所述第二数据通路电路中的各条目标通路的延时一致；对所述第二数据通路电路进行元器件调整操作，得到第三数据通路电路；其中，所述第三数据通路电路对应的第一时钟周期小于所述第二数据通路电路对应的第二时钟周期，并且在所述第三数据通路电路中，不同输入信号到达同一逻辑器的延时相差所述第一时钟周期的整数倍。
其中，处理器401的具体处理流程可以参照上述方法实施例的记载，这里不再赘述。
此外，本公开实施例还提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器运行时执行上述方法实施例中所述的电路调整方法的步骤。其中，该存储介质可以是易失性或非易失的计算机可读取存储介质。
本公开实施例还提供一种计算机程序产品，该计算机程序产品承载有程序代码，所述程序代码包括的指令可用于执行上述方法实施例中所述的电路调整方法的步骤，具体可参见上述方法实施例，在此不再赘述。
其中，上述计算机程序产品可以具体通过硬件、软件或其结合的方式实现。在一个可选实施例中，所述计算机程序产品具体体现为计算机存储介质，在另一个可选实施例中，计算机程序产品具体体现为软件产品，例如软件开发包(Software Development Kit，SDK)等等。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统和装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。在本公开所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，又例如，多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些通信接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个处理器可执行的非易失的计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读 存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (11)

  1. 一种电路调整方法，其特征在于，包括：
    确定集成电路中的第一数据通路电路；其中，所述第一数据通路电路中的不同寄存器之间存在多条目标通路；
    基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路，其中，所述第二数据通路电路中的各条目标通路的延时一致；
    对所述第二数据通路电路进行元器件调整操作，得到第三数据通路电路；其中，所述第三数据通路电路对应的第一时钟周期小于所述第二数据通路电路对应的第二时钟周期，并且在所述第三数据通路电路中，不同输入信号到达同一逻辑器的延时相差所述第一时钟周期的整数倍。
  2. 根据权利要求1所述的方法，其特征在于，所述基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路，包括：
    基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，确定所述第一数据通路电路中的各条所述目标通路对应的通路延时；
    将所述第一数据通路电路中的各条所述目标通路对应的所述通路延时中的最大延时作为目标延时；
    基于所述目标延时以及所述第一数据通路电路中的各条所述目标通路包括的寄存器至逻辑器之间的中间延时，在所述第一数据通路电路中插入缓冲器，得到所述第二数据通路电路。
  3. 根据权利要求1或2所述的方法，其特征在于，在所述第一数据通路电路的输入端口与第一寄存器之间存在第一缓冲器、以及在所述第一数据通路电路的第二寄存器与输出端口之间存在第二缓冲器的情况下，对所述第二数据通路电路进行元器件调整操作，包括：
    选取器件延时与目标延时匹配的第一待替换元器件和第二待替换元器件，其中，所述目标延时为所述第一数据通路电路中的各条所述目标通路对应的所述通路延时中的最大延时；
    将所述第二数据通路电路中的所述第一缓冲器替换为所述第一待替换元器件；和
    将所述第二数据通路电路中的所述第二缓冲器替换为所述第二待替换元器件。
  4. 根据权利要求1至3任一项所述的方法，其特征在于，所述元器件调整操作包括以下至少一种：元器件替换、元器件删减和元器件增加。
  5. 根据权利要求1至4任一项所述的方法，其特征在于，在所述第三数据通路电路的第三寄存器与输出端口之间存在第三缓冲器的情况下，在得到所述第三数据通路电路之后，所述方法还包括：
    选取器件延时与所述第二时钟周期匹配的第三待替换元器件，并
    将所述第三缓冲器替换为所述第三待替换元器件，得到第四数据通路电路。
  6. 根据权利要求1至5任一项所述的方法，其特征在于，在所述确定集成电路中的第一数据通路电路之前，所述方法还包括：
    利用整数线性规划方法，对所述集成电路中的每个电子元器件的初始器件延时进行整数化处理，得到所述每个电子元器件对应的整数倍目标单位的器件延时。
  7. 一种电路调整装置，其特征在于，包括：
    确定模块，用于确定集成电路中的第一数据通路电路；其中，所述第一数据通路电路中的不同寄存器之间存在多条目标通路；
    第一调整模块，用于基于所述第一数据通路电路中的各条所述目标通路包括的电子元器件的器件延时，在所述第一数据通路电路中插入缓冲器，得到第二数据通路电路，其中，所述第二数据通路电路中的各条目标通路的延时一致；
    第二调整模块，用于对所述第二数据通路电路进行元器件调整操作，得到第三数据通路电路；其中，所述第三数据通路电路对应的第一时钟周期小于所述第二数据通路电路对应的第二时钟周期，并且在所述第三数据通路电路中，不同输入信号到达同一逻辑器的延时相差所述第一时钟周期的整数倍。
  8. 一种数据通路电路，其特征在于，包括：逻辑器、寄存器、缓冲器中的至少一种元器件；其中，所述数据通路电路为基于权利要求1至6任一项所述的电路调整方法生成的。
  9. 一种电子设备，其特征在于，包括：处理器、存储器和总线，其中，所述存储器存储有所述处理器可执行的机器可读指令，当所述电子设备运行时，所述处理器与所述存储器之间通过所述总线通信，所述机器可读指令被所述处理器执行时实现如权利要求1至6任一项所述的电路调整方法的步骤。
  10. 一种电子设备，其特征在于，包括如权利要求8所述的数据通路电路。
  11. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，其中，所述计算机程序被处理器运行时执行如权利要求1至6任一项所述的电路调整方法的步骤。
PCT/CN2022/120966 2021-10-29 2022-09-23 电路调整方法、装置、电子设备、存储介质及电路 WO2023071651A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010048333A1 (en) * 2000-05-23 2001-12-06 Nec Corporation Buffer circuit block and design method of semiconductor integrated circuit by using the same
JP2004038383A (ja) * 2002-07-01 2004-02-05 Fujitsu Ltd ディジタル回路のタイミング調整方法
CN106297893A (zh) * 2016-08-01 2017-01-04 上海华虹宏力半导体制造有限公司 存储器测量电路的时钟电路及其设计方法
CN112580278A (zh) * 2020-12-07 2021-03-30 海光信息技术股份有限公司 逻辑电路的优化方法、优化装置以及存储介质
CN113992193A (zh) * 2021-10-29 2022-01-28 上海阵量智能科技有限公司 电路调整方法、装置、电子设备、存储介质及电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010048333A1 (en) * 2000-05-23 2001-12-06 Nec Corporation Buffer circuit block and design method of semiconductor integrated circuit by using the same
JP2004038383A (ja) * 2002-07-01 2004-02-05 Fujitsu Ltd ディジタル回路のタイミング調整方法
CN106297893A (zh) * 2016-08-01 2017-01-04 上海华虹宏力半导体制造有限公司 存储器测量电路的时钟电路及其设计方法
CN112580278A (zh) * 2020-12-07 2021-03-30 海光信息技术股份有限公司 逻辑电路的优化方法、优化装置以及存储介质
CN113992193A (zh) * 2021-10-29 2022-01-28 上海阵量智能科技有限公司 电路调整方法、装置、电子设备、存储介质及电路

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