WO2023051217A1 - 集成电路的时序约束方法、装置、电子设备及芯片 - Google Patents

集成电路的时序约束方法、装置、电子设备及芯片 Download PDF

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WO2023051217A1
WO2023051217A1 PCT/CN2022/118057 CN2022118057W WO2023051217A1 WO 2023051217 A1 WO2023051217 A1 WO 2023051217A1 CN 2022118057 W CN2022118057 W CN 2022118057W WO 2023051217 A1 WO2023051217 A1 WO 2023051217A1
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module
target
delay
constraint
timing
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PCT/CN2022/118057
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English (en)
French (fr)
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陈文杰
徐宁仪
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上海商汤智能科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

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  • the present disclosure relates to the technical field of chip design, and in particular, to a timing constraint method, device, electronic equipment and chip of an integrated circuit.
  • the timing constraints between modules and modules are determined by the percentage of clock cycles.
  • it is difficult for this method to determine the actual timing of the module boundary which easily leads to low efficiency of timing constraints and failure of module timing to converge.
  • Embodiments of the present disclosure at least provide a timing constraint method, device, electronic device, and chip for an integrated circuit.
  • an embodiment of the present disclosure provides a timing constraint method for an integrated circuit, where the integrated circuit includes multiple modules, including: determining that there is a module that does not meet the timing convergence condition based on the current delay constraints of the multiple modules
  • the target module is determined, and the target module is logically synthesized to obtain the first comprehensive result corresponding to the function description information of the target module; the actual delay of the target module is determined based on the first comprehensive result time; updating the current delay constraint of the target module based on the actual delay time to obtain a target delay constraint.
  • the actual delay time of the corresponding module is determined through the comprehensive result of the logic synthesis processing of each module in the integrated circuit, and then the delay constraint of the corresponding module is adjusted according to the actual delay time, so that it can be more reasonably determined
  • the time constraint conditions of each module in the integrated circuit are obtained, and when the timing convergence of the integrated circuit is performed according to the time constraint conditions, the timing convergence speed among various modules in the integrated circuit can be accelerated.
  • the updating the current delay constraint of the target module based on the actual delay time to obtain the target delay constraint includes: obtaining the connection relationship between the multiple modules; The connection relationship determines an adjacent module connected to the target module among the plurality of modules; based on the actual delay time of the adjacent module and the actual delay time of the target module, update the target The current delay constraint of the module is obtained to obtain the target delay constraint.
  • the target delay constraint can be obtained, which can be more reasonably determined
  • the time constraint condition of the target module in the integrated circuit when the timing convergence of the integrated circuit is performed according to the time constraint condition, the timing convergence speed among various modules in the integrated circuit can be accelerated.
  • the current delay constraint of the target module is updated based on the actual delay time of the adjacent module and the actual delay time of the target module to obtain the target delay time Constraints, including: based on the actual delay time of the adjacent module and the actual delay time of the target module, determine that the signal is transmitted from the first-level sequential unit of the adjacent module to the first-level of the target module The target delay time of the sequential unit; updating the current delay constraint of the target module based on the target delay time to obtain the target delay constraint.
  • the current delay constraint of the target module is updated by transmitting the signal from the first-level sequential unit of the adjacent module to the target delay time of the first-level sequential unit of the target module, and a reasonable delay constraint can be obtained for each module. Constraints, which can speed up the timing closure between modules when the constraints are used for synthesis and place-and-route processing.
  • the current delay constraint includes an input delay constraint
  • the adjacent module is a module connected to the input boundary end of the target module
  • the updating of the The current delay constraint of the target module, obtaining the target delay constraint includes: determining the delay time for the signal to be transmitted from the output end of the first-level sequential unit of the adjacent module to the output boundary end of the adjacent module, Obtain a first delay; determine the proportion of the first delay in the target delay time to obtain the first proportion; update the input delay constraint based on the first proportion to obtain the target Enter a delay constraint in Delay Constraints.
  • the current delay constraint includes an output delay constraint;
  • the adjacent module is a module connected to the output boundary end of the target module;
  • the updating of the The current delay constraint of the target module, obtaining the target delay constraint also includes: determining the delay time for the signal to be transmitted from the input boundary end of the adjacent module to the first-level sequential unit of the adjacent module, and obtaining second delay; determining the proportion of the second delay in the target delay time to obtain a second proportion; updating the output delay constraint based on the second proportion to obtain the target delay The output delay constraint in the time constraint.
  • the input delay constraint is determined by calculating the ratio of the delay time for the signal to be transmitted from the output terminal of the first-level sequential unit of the adjacent module to the output boundary terminal of the adjacent module in the target delay time, which can Improve the rationality of input delay constraints.
  • the output can be improved. Rationality of delay constraints. After the input delay constraint and the output delay constraint are determined, the timing convergence of the integrated circuit is performed based on the delay constraint, which can improve the timing convergence speed between modules.
  • the method further includes: determining whether the target module satisfies the timing closure condition based on the target delay constraint; In the case of a convergence condition, place and route the target module based on the target delay constraint.
  • the manner of determining that the target module satisfies the timing convergence condition based on the target delay constraint includes: re-synthesizing the target module based on the target delay constraint to obtain the The second comprehensive result corresponding to the function description information of the target module; based on the second comprehensive result, update the actual delay time of the timing path between any two connected modules in the plurality of modules; the timing path is the signal transmission path between the first-level sequential units of the two connected modules; when the actual delay time of each timing path is determined to meet the preset clock requirement, it is determined that the target module meets the timing convergence condition.
  • the circuit of the target module can be optimized Logic, so that integrated circuits that meet the timing convergence conditions can be quickly obtained.
  • the method further includes: updating the path weight of the timing path corresponding to the target module based on the actual delay time of the timing path; Performing re-logic synthesis on the target module to obtain a second synthesis result corresponding to the function description information of the target module, including: performing re-logic on the target module based on the path weight and the target delay constraint comprehensive processing to obtain the second comprehensive result.
  • the credibility of the second synthesis result can be improved, thereby further speeding up the timing convergence speed between modules in the integrated circuit.
  • the method further includes: determining whether the target module meets the timing closure condition based on the target delay constraint; determining that the target module does not meet the timing closure condition based on the target delay constraint In the case of the timing convergence condition, determining the target delay constraint as the current delay constraint of the target module, re-determining a new target module, performing new logic synthesis processing on the new target module, A new actual delay time is determined, and a new target delay constraint is obtained, until it is determined based on the obtained new target delay constraint that the new target module satisfies the timing closure condition.
  • the circuit of the target module can be optimized Logic, so that integrated circuits that meet the timing convergence conditions can be quickly obtained.
  • determining the target module includes: determining the multiple modules as the target module; or determine that a module among the plurality of modules that does not satisfy the timing closure condition is the target module.
  • the delay constraints between modules are more accurate.
  • the amount of processed data can be reduced by determining the module that does not meet the timing convergence conditions as the target module, and performing timing constraint processing on the target module in the manner described above , so as to improve the efficiency of the timing constraints of the integrated circuit and shorten the time required for realizing the timing constraints.
  • an embodiment of the present disclosure further provides a timing constraint device for an integrated circuit, including: a first determination module, configured to determine that there is a timing constraint that does not meet the timing convergence condition based on the current delay constraints of multiple modules included in the integrated circuit.
  • a module determine the target module, and carry out logical synthesis processing on the target module to obtain the first comprehensive result corresponding to the function description information of the target module; the second determination module is used for based on the first comprehensive As a result, the actual delay time of the target module is determined; an update module is configured to update the current delay constraint of the target module based on the actual delay time, to obtain a target delay constraint.
  • an embodiment of the present disclosure further provides an electronic device, including: a processor, a memory, and a bus, the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processing
  • the processor communicates with the memory through a bus, and when the machine-readable instructions are executed by the processor, the above-mentioned first aspect, or the steps in any possible implementation manner of the first aspect are executed.
  • the embodiments of the present disclosure further provide a chip, which uses the timing constraint method of the integrated circuit described in the above first aspect or any possible implementation mode of the first aspect to perform timing constraints, and When it is determined based on the target delay constraint that the target module satisfies a timing closure condition, place and route the target module based on the target delay constraint.
  • the embodiments of the present disclosure also provide a computer-readable storage medium, on which a computer program is stored, and when the computer program is run by a processor, the above-mentioned first aspect, or any of the first aspects of the first aspect, can be executed. Steps in one possible implementation.
  • Embodiments of the present disclosure provide a timing constraint method, device, electronic device and storage medium for an integrated circuit.
  • the actual delay time of the corresponding module is determined through the comprehensive result of the logic synthesis processing of each module in the integrated circuit, and then the delay constraint of the corresponding module is adjusted according to the actual delay time, so that it can be more reasonable
  • the time constraint conditions of each module in the integrated circuit are accurately determined, and when the timing convergence of the integrated circuit is performed according to the time constraint conditions, the timing convergence speed among various modules in the integrated circuit can be accelerated.
  • FIG. 1 shows a flowchart of a timing constraint method for an integrated circuit provided by an embodiment of the present disclosure
  • FIG. 2 shows a schematic diagram of delay constraints of modules in an integrated circuit in a related art
  • FIG. 3 shows a schematic diagram of the actual delay time between multiple connected target modules in an integrated circuit provided by an embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of a timing path between module A and module B provided by an embodiment of the present disclosure
  • FIG. 5 shows a schematic diagram of a timing constraint device for an integrated circuit provided by an embodiment of the present disclosure
  • Fig. 6 shows a schematic diagram of an electronic device provided by an embodiment of the present disclosure.
  • the timing constraints between modules and modules are determined by the percentage of clock cycles.
  • it is difficult for this method to determine the actual timing of the module boundary which easily leads to low efficiency of timing constraints and failure of module timing to converge.
  • the present disclosure provides a timing constraint method, device, electronic device and storage medium for an integrated circuit.
  • the actual delay time of the corresponding module is determined through the comprehensive result of the logic synthesis processing of each module in the integrated circuit, and then the delay constraint of the corresponding module is adjusted according to the actual delay time, so that it can be more reasonable
  • the time constraint conditions of each module in the integrated circuit are accurately determined, and when the timing convergence of the integrated circuit is performed according to the time constraint conditions, the convergence speed of timing among various modules in the integrated circuit can be accelerated.
  • timing constraint method for an integrated circuit disclosed in the embodiment of the present disclosure.
  • the execution subject of the timing constraint method for an integrated circuit provided in the embodiment of the present disclosure generally has a certain computing power Electronic equipment such as computers, servers, etc.
  • FIG. 1 it is a flowchart of a timing constraint method for an integrated circuit provided by an embodiment of the present disclosure.
  • the method includes steps S101 to S105, wherein:
  • the integrated circuit is first divided into a plurality of modules.
  • the integrated circuit may be divided into multiple different functional modules according to the module functions, that is, the above-mentioned multiple modules.
  • the current delay constraints of multiple modules are the delay constraints of each module obtained from the last simulation update.
  • the delay constraint of each module includes an input delay constraint and an output delay constraint, wherein the delay constraint may also be called an I/O (Input/Output, input-output) constraint.
  • the current delay constraint of each module in the integrated circuit can be determined according to the percentage of the delay time of each module in the integrated circuit to the clock cycle.
  • the clock cycle is the most basic time unit in an integrated circuit, and is used to represent the time for a corresponding module in the integrated circuit to complete a most basic action.
  • FIG. 2 is a schematic diagram of the current delay constraint of module A in the integrated circuit at the initial moment.
  • the input delay constraint of module A can be set to 0.65clk (clock, clock cycle), 0.65clk is 65% of the clock cycle, and the output delay constraint of module A can be set to 0.45clk .
  • the integrated circuit may include multiple clocks, and different clocks correspond to different clock periods, for example, the clock period of a clock with a frequency of 100 MHz is 10 ns.
  • the implementation method of the present disclosure is described by taking constraint on multiple modules using the same first clock as an example. Those skilled in the art know that this method can also constrain multiple modules that use a second clock different from the first clock, constrain multiple modules that use a third clock, etc., and this disclosure does not limit this .
  • a module may include multiple I/O signals (or called I/O pins) using the same clock, and the present disclosure does not limit the number of I/O signals.
  • different signals of a module may be set with the same or different delay constraint conditions, and may also have the same or different delay constraint results, which is not limited in the present disclosure.
  • the EDA tool can be chip design assistant software, programmable chip assistant design software, system design assistant software, and the like.
  • the target module can be determined in the integrated circuit.
  • the target module may be all modules in the integrated circuit, and may also be a module in the integrated circuit that does not meet the timing convergence condition, which is not specifically limited in the present disclosure.
  • the EDA tool can determine the modules that do not meet the timing convergence conditions in the integrated circuit through the dynamic simulation results of the EDA tool; after that, the modules that do not meet the timing convergence conditions can be determined for the target module.
  • all modules of the integrated circuit may be determined as target modules.
  • the module meeting the timing convergence condition can be understood as: the module meets the timing requirement when processing the corresponding signal; otherwise, the timing convergence condition is not satisfied.
  • the module meeting the timing convergence conditions can be further understood as: for each I/O signal in the module, when processing the signal, the timing requirements are met; if at least one signal does not meet the timing requirements, the module does not meet the timing requirements. Timing closure conditions.
  • the target module can be logically synthesized in the above-mentioned EDA tool. Specifically, the target module can be logically synthesized through RTL (Register Transfer Level) coding, thereby obtaining First comprehensive result.
  • RTL Registered Transfer Level
  • logical synthesis processing may be performed on each target module.
  • RTL coding is used to describe the function of each block in the integrated circuit.
  • Logic synthesis processing can also be called physical synthesis processing, which is used to describe the functions of each module through RTL language, so as to realize the conversion of each module into a circuit structure with corresponding functions.
  • physical synthesis processing By performing physical synthesis processing on the target module, it is possible to determine the occupied area of the target module in the integrated circuit, and the physical structure information such as the positions of the input terminals and output terminals of the target module in the integrated circuit. Therefore, the above-mentioned first synthesis result is used to indicate the structure information of the logic circuit corresponding to the function description information of the module.
  • S103 Determine an actual delay time of the target module based on the first synthesis result, where the actual delay time is a time required for a signal to transmit between a boundary of the target module and a first-level sequential unit of the target module.
  • the boundary of the target module may include an input boundary terminal and an output boundary terminal of the target module.
  • the actual delay time includes the actual input delay and the actual output delay, where the actual input delay is used to characterize the delay time between the input boundary terminal of the target module and the first-level sequential unit, for example, the input port to the input port.
  • the delay between sequential devices such as registers/flip-flops connected to ports, the actual output delay is used to represent the delay time between the relevant sequential unit of the target module and the output boundary.
  • actual delay time, delay time, delay time, etc. may refer to delay time, for example, 650 ps (picosecond).
  • the logical connection relationship among the transistors in each module can be determined.
  • the above-mentioned actual input delay and actual output delay can be determined according to the logical connection relationship.
  • the actual input delay and actual output delay of each I/O pin can be obtained through logic synthesis.
  • module A, module B, and module C are all target modules and are arranged next to each other. Therefore, the distance between module A and module B, and between module B and module C Latency is negligible.
  • t1 represents the actual output delay of pin A1 of module A, and the actual output delay t1 is used to indicate that the signal on pin A1 arrives at module A from the first-level sequential unit connected to pin A1 on module A Since the delay between module A and module B is negligible, t1 in Figure 3 indicates the input boundary of module B instead of the output boundary of module A.
  • t 2 is the actual input delay of pin B1 of module B, and the actual input delay t 2 is used to indicate that the signal on pin B1 arrives from the input boundary end corresponding to pin B1 on module B to the corresponding pin on module B Timing of the first level sequential unit of pin B1.
  • t 3 represents the actual output delay of the pin B2 of module B, and the actual output delay t 3 is used to indicate that the signal on the pin B2 arrives at the corresponding time at the output boundary of pin B2; since the delay between modules B and C is negligible, t3 shown in Figure 3 indicates the input boundary of module C rather than the output boundary of module B .
  • t 4 is the actual input delay of pin C1 of module C, and the actual input delay t 4 is used to indicate that the signal on pin C1 arrives from the input boundary end corresponding to pin C1 on module C to the corresponding pin on module C The timing of the first level sequential unit of pin C1.
  • first-level sequential unit For simplicity, only one first-level sequential unit is shown in module B in FIG. 3 . Those skilled in the art know that there may be multiple first-level sequential units in module B. Level sequential units may or may not be the same sequential unit.
  • S105 Update the current delay constraint of the target module based on the actual delay time to obtain a target delay constraint.
  • the current delay constraint of the target module can be updated through the actual input delay and actual output delay in the actual delay time to obtain the target delay constraint.
  • the input delay constraint in the delay constraint can be understood as: the delay constraint information when the external output signal arrives at the input boundary of the module.
  • the module connected to a module and transmitting the signal to the module can be called the upstream module, and the external The output signal of can be understood as the signal output by the first-level sequential unit of the upstream module.
  • the output delay constraint in the delay constraint can be understood as: the signal is input from the input boundary terminal of the downstream module to the delay constraint information of the first-level sequential unit of the downstream module, in which, the output delay constraint connected to the target module and received by the target module A next-level module that transmits a signal may be referred to as a downstream module.
  • the input delay constraint in the case that the upstream module is close to the target module, the input delay constraint can also be understood as: delay constraint information that the external output signal reaches the output boundary end of the upstream module.
  • module B is a downstream module of module A
  • module A is an upstream module of module B.
  • the input delay constraint of module B is associated with the actual output delay t 1 of module A, after the actual output delay t 1 of module A is determined, the input delay constraint of module B is determined through the actual output delay;
  • module The output delay constraint of B is associated with the actual input delay t4 of module C, after determining the actual input delay t4 of module C, the output delay constraint of module B is determined through the actual input delay; this can Determine a more reasonable time constraint condition for module B, thereby speeding up the timing convergence between module A and module B, and between module B and module C.
  • each module in the integrated circuit meets the timing convergence condition can be understood as: each module in the integrated circuit satisfies the timing requirement when processing corresponding signals.
  • meeting the timing requirements here can be understood as the transmission of a signal from the first-level sequential unit of module A to the first-level sequential unit of module B needs to be completed within one clock cycle. Assuming that the clock period is 1 nanosecond, at this time, if the input delay constraint of the signal in module B is set to be no higher than 650ps, it can be understood that the signal is transmitted from the first-level sequential unit of module A to the time of module A The boundary must be completed within 650ps.
  • the signal is transmitted from the boundary of module B to the first-level sequential unit of module B to be completed within the remaining 350ps, that is, the signal is in the module.
  • the output delay constraint of A is that the delay is not higher than 350ps.
  • the actual delay time of the corresponding module is determined through the comprehensive result of the logic synthesis processing of each module in the integrated circuit, and then the delay constraint of the corresponding module is adjusted according to the actual delay time, so that it can be more reasonable
  • the time constraint conditions of each module in the integrated circuit are accurately determined, and when the timing convergence of the integrated circuit is performed according to the time constraint conditions, the timing convergence speed among various modules in the integrated circuit can be accelerated.
  • the method further includes: when it is determined based on the target delay constraint that the target module satisfies a timing closure condition, performing placement and routing on the target module based on the target delay constraint .
  • the target module can be simulated and run according to the target delay constraint by means of dynamic simulation, so as to determine whether the target module satisfies the timing convergence condition.
  • the EDA tool can simulate the layout and routing of the target module. If the target module meets the timing closure conditions, then the EDA tool can simulate the layout and routing of the target module. If the target module does not meet the timing convergence conditions, then the target delay constraint can be determined as the current delay constraint of the target module, and the above steps S101 to S105 are executed until a new target module is determined based on the obtained new target delay constraint The timing convergence condition is satisfied, that is, until it is determined that each module in the integrated circuit satisfies the timing convergence condition.
  • step S101 is to determine a target module when it is determined based on the current delay constraints of multiple modules that there is a module that does not meet the timing convergence condition, specifically including the following two situations.
  • Case 1 The multiple modules are determined to be the target modules.
  • each module in the integrated circuit can be individually determined as a target module. Since the various modules in the integrated circuit are connected to each other, in order to ensure the timing convergence between the connected modules, each module in the integrated circuit can be determined as the target module respectively. Then, perform timing constraint processing on each module in the manner described above.
  • Case 2 determining that a module among the plurality of modules that does not meet the timing convergence condition is the target module.
  • the modules that do not meet the timing convergence conditions in the integrated circuit can be determined through the dynamic simulation results of the EDA tool, and then the modules that do not meet the timing convergence conditions The module of the timing closure condition is determined as the target module.
  • the delay constraints among the various modules are made more accurate.
  • the amount of processed data can be reduced by determining the module that does not meet the timing convergence conditions as the target module, and performing timing constraint processing on the target module in the manner described above , so as to improve the efficiency of the timing constraints of the integrated circuit and shorten the time required for realizing the timing constraints.
  • step S105 is to update the current delay constraint of the target module based on the actual delay time to obtain the target delay constraint, which specifically includes the following process:
  • S1052 Determine, among the multiple modules, adjacent modules connected to the target module based on the connection relationship.
  • S1053 Based on the actual delay time of the adjacent module and the actual delay time of the target module, update the current delay constraint of the target module to obtain the target delay constraint.
  • the connection relationship of multiple modules can be determined based on the dynamic simulation results of the dynamic simulation, wherein the connection relationship can use multiple modules The module ID representation.
  • the adjacent modules connected to the target module are determined.
  • the modules connected with the target module can be divided into upstream modules and/or downstream modules. Specifically, the transmission direction of the signal is from the upstream module to the target module, and/or from the target module to the downstream module.
  • the adjacent module connected to the input end of the target module is the upstream module
  • the target The adjacent modules to which the outputs of the modules are connected are downstream modules.
  • module A and module C are modules connected to the target module, where module A is the upstream module, and module C is the downstream module. At this time, module A is the The input terminals of B are connected to adjacent modules. If module A is the target module, then module B is the downstream module connected to the target module.
  • the actual delay time of modules A, B, and C can be determined, so that based on the above-mentioned actual delay time, the current delay constraint of the above-mentioned module B can be updated to obtain the target of the module B Delay constraint, the specific process can be described as follows: Based on the actual output delay of the adjacent module and the actual input delay of the target module, the current delay constraint of the target module is updated to obtain the target delay constraint of the target module.
  • the input of module B can be updated based on the actual output delay t 1 of module A, the actual input delay t 2 and actual output delay t 3 of module B, and the actual input delay t 4 of module C. Delay constraints and output delay constraints, so as to obtain the target delay constraints of module B.
  • the target delay constraint can be obtained, which can be more reasonably determined
  • the time constraint condition of the target module in the integrated circuit when the timing convergence of the integrated circuit is performed according to the time constraint condition, the timing convergence speed among various modules in the integrated circuit can be accelerated.
  • S1053 based on the actual delay time of the adjacent module and the actual delay time of the target module, update the current delay constraint of the target module to obtain the target delay Constraints, specifically include the following processes.
  • module B is a target module
  • module A is an adjacent module of the target module.
  • each module in the integrated circuit satisfies timing requirements when processing corresponding signals. That is, the target delay time for the signal to be transmitted from the first-level sequential unit of the upstream module to the first-level sequential unit of the target module must satisfy one clock cycle, for example, not exceed one clock cycle.
  • meeting the timing requirements here can be understood as the transmission of a signal from the first-level sequential unit of module A to the first-level sequential unit of module B needs to be completed within one clock cycle.
  • t1 is used to characterize the transmission time of the signal from the output terminal of the first-level sequential unit of module A to the output boundary terminal of module A, wherein, since module A and module B are arranged next to each other, module A and The delay between modules B is negligible, and t1 in Figure 4 indicates the input boundary of module B rather than the output boundary of module A.
  • t 2 is used to represent the transmission time of the signal from the input boundary terminal of module B to the input terminal of the first-level sequential unit of module B.
  • the above target delay time can be determined based on t1 and t2 .
  • the current delay constraint of the target module is updated to obtain the target delay constraint.
  • I/O constraints include input delay constraints (Input delay) and output delay constraints (Output delay).
  • input delay constraint of module B can be understood as the delay constraint information that the signal output by the first-level sequential unit of module A reaches the input boundary of module B. Therefore, the input delay constraint of the module B is related to the actual output delay of the module A.
  • the output delay constraint of module A can be understood as the delay constraint information of a signal input from the input boundary terminal of module B to the first-level sequential unit of module B. Therefore, the output delay constraint of the module A is related to the actual input delay of the module B.
  • the current delay of the target module can be updated through the actual output delay of module A and the actual input delay of module B constraints to obtain the target delay constraints.
  • the current delay constraint of the target module can be updated based on the target delay time to obtain the target delay constraint of the target module.
  • Case 1 The current delay constraint includes the input delay constraint of the above target module.
  • the actual delay time (that is, the actual output delay of module A) t 1 of the signal transmitted from the output terminal of the first-level sequential unit of module A to the output boundary terminal of module A can be obtained, and
  • the actual output delay t1 is determined as the above-mentioned first delay.
  • t2 is the actual delay time for the signal to be transmitted from the input boundary end of module B to the input end of the first-level sequential unit of module B (that is, the actual input delay of module B)
  • clk period is the clock of the integrated circuit cycle.
  • clk uncertainty represents the clock uncertainty, which is used to represent the difference and change between the actual arrival time of the clock edge and the theoretical arrival time.
  • clk uncertainty clk skew + clk jitter .
  • clk skew is the time difference of the clock cycle due to different transmission paths
  • clk jitter is the time difference of the cycle edge due to the instability of the clock source between adjacent clock cycles. Therefore, the result of clk period -clk uncentainty should be the clock period clk of the signal in the above integrated circuit during the actual transmission process.
  • the first ratio B input can be updated as the input delay constraint of the target module. It should be understood that, if the target module is required to meet the timing convergence condition, the sum of the actual delay time t1 of the above-mentioned adjacent modules and the actual delay time t2 of the target module should satisfy the clock cycle of the integrated circuit, for example, t 1 +t 2 should be less than or equal to the time value of one clock cycle, but if t 1 +t 2 is greater than the time value of one clock cycle, the target module does not meet the timing convergence condition.
  • the current delay constraint includes the output delay constraint of the above target module.
  • module A is a target module
  • module B is an adjacent module of the target module
  • t2 is used to represent the delay time for the signal to be transmitted from the input boundary end of module B to the first-level sequential unit of module B, that is, the second delay. Then, the output delay constraint of module A can be determined based on the second delay t2 .
  • the proportion of the second delay in the target delay time may be calculated to obtain the second proportion B output , and then, the output delay constraint in the target delay constraint is determined according to the second proportion.
  • the proportion of the second delay in the target delay time can be calculated by the following formula (2):
  • t2 is the delay time for the signal to be transmitted from the input boundary end of the adjacent module to the first-level sequential unit of the adjacent module, that is, the above-mentioned second delay time
  • clk period is the clock period of the integrated circuit.
  • clk uncertainty represents the clock uncertainty, which is used to represent the difference and change between the actual arrival time of the clock edge and the theoretical arrival time.
  • the result of clk period -clk uncentainty should be the clock period clk of the signal in the above integrated circuit during the actual transmission process.
  • the second ratio B output can be updated as the output delay constraint of the target module.
  • the target module if the target module is required to meet the timing convergence condition, then the sum of the actual delay time t1 of the above-mentioned adjacent modules and the actual delay time t2 of the target module should satisfy the clock period of the integrated circuit, for example, t1 +t 2 is less than or equal to the time value of one clock cycle, but if t 1 +t 2 is greater than the time value of one clock cycle, the target module does not meet the timing convergence condition.
  • the input delay constraint is determined by calculating the ratio of the delay time for the signal to be transmitted from the output terminal of the first-level sequential unit of the adjacent module to the output boundary terminal of the adjacent module in the target delay time, which can Improve the rationality of input delay constraints.
  • the output can be improved. Rationality of delay constraints. After the input delay constraint and the output delay constraint are determined, the timing convergence of the integrated circuit is performed based on the delay constraint, which can improve the timing convergence speed between modules.
  • S31 Perform re-logic synthesis processing on the target module based on the target delay constraint, to obtain a second synthesis result corresponding to the function description information of the target module.
  • the target delay constraint after the target delay constraint is determined, it may be determined based on the target delay constraint whether the target module satisfies the timing convergence condition. At this time, based on the target delay constraint, the target module can be re-synthesized in the EDA tool, so as to obtain the second synthesis result.
  • the process of re-executing the logic synthesis process on the target module is the same as the process of the logic synthesis process described in the above step S101.
  • the target module can be logically synthesized through RTL coding, so as to obtain the second synthesis result.
  • RTL coding is used to describe the function of each block in the integrated circuit.
  • Logic synthesis processing can also be called physical synthesis processing, which is used to describe the functions of each module through RTL language, so as to realize the conversion of each module into a circuit structure with corresponding functions.
  • physical synthesis processing By performing physical synthesis processing on the target module, it is possible to determine the occupied area of the target module in the integrated circuit, and the physical structure information such as the positions of the input terminals and output terminals of the target module in the integrated circuit. Therefore, the above-mentioned second synthesis result is used to indicate the structure information of the logic circuit corresponding to the function description information of the module.
  • the actual delay time of the timing path between any two connected modules among the multiple modules of the integrated circuit is updated. Assume that any two connected modules are module A and module B. At this time, the actual delay time is the sum of the actual output delay of module A and the actual input delay of module B after re-processing the logic synthesis .
  • the actual delay time of the timing path between any two connected modules in the plurality of modules it can be judged whether the actual delay time meets the preset clock requirement. For example, it may be determined whether the actual delay time is less than or equal to the aforementioned clock cycle. If the actual delay time is less than or equal to the above clock cycle, it is determined that the preset clock requirement is met, and at this time, it can be determined that the target module meets the timing convergence condition. If it is judged that the preset clock requirement is not met, the target delay constraint can be used as the current delay constraint, and the execution of steps S101-S105 is returned until the target delay constraint meeting the timing convergence condition is obtained.
  • module A, module B, and module C are target modules.
  • the above-mentioned target modules include two timing paths L 1 and L 2 , where L 1 is the signal from module A.
  • L 1 is the signal from module A.
  • L 2 is a path for signals from the output terminal of the first-level sequential unit of module B to the input terminal of the first-level sequential unit of module C.
  • the actual delay time of each timing path can be determined, and then whether the actual delay time meets the preset clock requirement can be determined.
  • timing path L1 it can be determined whether the actual delay time of the timing path L1 (that is, the sum of the actual output delay of module A and the actual input delay of module B) is within one clock cycle. If it is judged yes, it is determined that the timing path L 1 meets the preset clock requirement, and at this time, it can be determined that the timing path between module A and module B meets the timing convergence condition.
  • timing path L2 it can be determined whether the actual delay time of the timing path L2 (that is, the sum of the actual output delay of module B and the actual input delay of module C) is within one clock cycle. If it is judged yes, it is determined that the timing path L 2 meets the preset clock requirement. At this time, it can be determined that the timing path L 2 between the module C and the module B meets the timing convergence condition.
  • the circuit of the target module can be optimized Logic, so that integrated circuits that meet the timing convergence conditions can be quickly obtained.
  • the method also includes the following steps:
  • the path weight of the timing path corresponding to the target module is updated.
  • the above steps perform re-logic synthesis on the target module based on the target delay constraint to obtain a second synthesis result corresponding to the function description information of the target module, including: based on the path weight and The target delay constraint performs re-logic synthesis processing on the target module to obtain the second synthesis result.
  • the module can be calculated based on the actual input delay t2 and the actual output delay t3
  • the path weight B weight of the timing path corresponding to B is described in formula (3):
  • the target module can be re-synthesized by combining the weight B weight of the path L 1 and the target delay constraint to obtain the second synthesis result.
  • the average value of the actual output delay of each I/O pin can be used as t 3 , so that t 3 can be used to calculate the corresponding The path weight B weight of the timing path L1.
  • the path weight and the target delay constraint can be input into the EDA tool, and then the logic synthesis processing of the target module is re-executed according to the EDA tool based on the path weight and the target delay constraint.
  • a large path weight will affect the timing convergence result of the internal circuit of the integrated circuit after logic synthesis; however, when the path weight is small, it is impossible to give a reasonable I/O constraint for each module in the integrated circuit, resulting in each path The I/O constraints are too loose or too tight.
  • the writing order of each step does not mean a strict execution order and constitutes any limitation on the implementation process.
  • the specific execution order of each step should be based on its function and possible
  • the inner logic is OK.
  • the embodiment of the present disclosure also provides an integrated circuit timing constraint device corresponding to the timing constraint method of the integrated circuit, because the problem-solving principle of the device in the embodiment of the present disclosure is the same as that of the above-mentioned integrated circuit in the embodiment of the present disclosure
  • the time sequence constraint method is similar, so the implementation of the device can refer to the implementation of the method, and the repetition will not be repeated.
  • the device includes: a first determination module 51, a second determination module 52, and an update module 53; wherein,
  • the first determination module 51 is configured to determine a target module when it is determined based on the current delay constraints of multiple modules that there is a module that does not meet the timing convergence condition, and perform logic synthesis processing on the target module to obtain the same as the The first comprehensive result corresponding to the function description information of the target module;
  • the second determination module 52 is configured to determine the actual delay time of the target module based on the first comprehensive result
  • the update module 53 is configured to update the current delay constraint of the target module based on the actual delay time to obtain a target delay constraint.
  • the actual delay time of the corresponding module is determined through the comprehensive result of the logic synthesis of each module in the integrated circuit, and then the delay constraint mode of the corresponding module is adjusted according to the actual delay time, which can be determined more reasonably
  • the time constraint conditions of each module in the integrated circuit are obtained, and when the timing convergence of the integrated circuit is performed according to the time constraint condition, the convergence speed among the various modules in the integrated circuit can be accelerated.
  • the update module 53 is further configured to: obtain the connection relationship among the multiple modules; An adjacent module; based on the actual delay time of the adjacent module and the actual delay time of the target module, update the current delay constraint of the target module to obtain the target delay constraint.
  • the update module 53 is further configured to: based on the actual delay time of the adjacent module and the actual delay time of the target module, determine that the signal from the first stage of the adjacent module The sequential unit transmits the target delay time of the first-level sequential unit of the target module; based on the target delay time, the current delay constraint of the target module is updated to obtain the target delay constraint.
  • the current delay constraint includes an input delay constraint
  • the adjacent module is a module connected to the input boundary terminal of the target module
  • the update module 53 is further configured to: determine the signal from the The delay time for the output terminal of the first-level sequential unit of the adjacent module to be transmitted to the output boundary end of the adjacent module to obtain the first delay; determine the proportion of the first delay in the target delay time ratio to obtain a first ratio; and update the input delay constraint based on the first ratio to obtain an input delay constraint in the target delay constraint.
  • the current delay constraint includes an output delay constraint;
  • the adjacent module is a module connected to the output boundary terminal of the target module;
  • the update module 53 is also used to: determine the signal from the The input boundary end of the adjacent module is transmitted to the delay time of the first-level sequential unit of the adjacent module to obtain a second delay; determine the proportion of the second delay in the target delay time, Obtaining a second proportion; updating the output delay constraint based on the second proportion to obtain an output delay constraint in the target delay constraint.
  • the device is further configured to: determine whether the target module satisfies the timing closure condition based on the target delay constraint; In the case of a condition, place and route the target module based on the target delay constraint.
  • the device is further configured to: re-synthesize the target module based on the target delay constraint to obtain a second synthesis result corresponding to the function description information of the target module;
  • the second synthesis result updates the actual delay time of the timing path between any two connected modules in the plurality of modules; the timing path is the first-level timing of the signal in the two connected modules A transmission path between units; when it is determined that the actual delay time of each timing path satisfies a preset clock requirement, it is determined that the target module meets a timing convergence condition.
  • the device is further configured to: update the path weight of the timing path corresponding to the target module based on the actual delay time of the timing path; Re-synthesis processing is performed on the target module according to time constraints to obtain the second synthesis result.
  • the device is further configured to: determine whether the target module satisfies the timing closure condition based on the target delay constraint; In the case of the above timing convergence condition, determine the target delay constraint as the current delay constraint of the target module, and re-determine a new target module, perform new logic synthesis processing on the new target module, and determine A new actual delay time and a new target delay constraint are obtained until it is determined based on the obtained new target delay constraint that the new target module satisfies the timing convergence condition.
  • the first determining module 51 is further configured to: determine the plurality of modules as the target module; or determine a module among the plurality of modules that does not meet the timing convergence condition as The target module.
  • the embodiment of the present disclosure also provides an electronic device 600, as shown in FIG. 6, which is a schematic structural diagram of the electronic device 600 provided by the embodiment of the present disclosure, including:
  • Processor 61 memory 62, and bus 63; memory 62 is used for storing and executing instruction, comprises memory 621 and external memory 622; memory 621 here is also called internal memory, is used for temporarily storing computing data in processor 61, and The data exchanged by the external memory 622 such as hard disk, the processor 61 exchanges data with the external memory 622 through the memory 621, and when the electronic device 600 is running, the processor 61 communicates with the memory 62 through the bus 63, so that The processor 61 executes the following instructions:
  • determine the target module When it is determined based on the current delay constraints of multiple modules that there is a module that does not meet the timing convergence condition, determine the target module, and perform logic synthesis processing on the target module to obtain the function description information corresponding to the target module.
  • a first synthesis result determining an actual delay time of the target module based on the first synthesis result; updating a current delay constraint of the target module based on the actual delay time to obtain a target delay constraint.
  • An embodiment of the present disclosure also provides a chip, which uses the above-mentioned integrated circuit timing constraint method to perform timing constraints before layout and wiring of the chip, and determines that the target module satisfies the timing convergence condition based on the target delay constraint Next, place and route the target module based on the target delay constraint.
  • An embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is run by a processor, the timing constraint method for an integrated circuit described in the foregoing method embodiments is executed. step.
  • the storage medium may be a volatile or non-volatile computer-readable storage medium.
  • An embodiment of the present disclosure also provides a computer program product, which carries a program code, and the instructions included in the program code can be used to execute the steps of the timing constraint method for an integrated circuit described in the method embodiment above, specifically, Refer to the foregoing method embodiments, and details are not repeated here.
  • the above-mentioned computer program product may be specifically implemented by means of hardware, software or a combination thereof.
  • the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK) etc. wait.
  • a software development kit Software Development Kit, SDK
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor.
  • the computer software product is stored in a storage medium, including several
  • the instructions are used to make an electronic device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present disclosure.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

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Abstract

一种集成电路的时序约束方法、装置、电子设备及芯片，其中，方法包括：在基于多个模块的当前延时约束确定存在不满足时序收敛条件的模块的情况下，确定目标模块，并对目标模块进行逻辑综合处理，得到与目标模块的功能描述信息对应的第一综合结果；基于第一综合结果确定目标模块的实际延时时间；基于实际延时时间更新目标模块的当前延时约束，得到目标延时约束。

Description

集成电路的时序约束方法、装置、电子设备及芯片
相关申请的交叉引用
本公开要求于2021年9月30日提交的、申请号为202111156729.4的中国专利公开的优先权，该中国专利公开的全部内容以引用的方式并入本文中。
技术领域
本公开涉及芯片设计的技术领域，具体而言，涉及一种集成电路的时序约束方法、装置、电子设备及芯片。
背景技术
随着电子技术的发展，当集成电路工艺发展到深亚微米时，数字集成电路的时序收敛(Timing Closure)变得越来越具有挑战性。同时，随着集成电路的功能越来越复杂，集成电路中所包含的晶体管数量也增大到百亿级别。因此，在芯片实现的过程中，通常需要将集成电路划分成多个模块，然后，通过在模块跟模块之间设置时序约束来进行时序收敛。
在相关技术的时序约束方法中，通过时钟周期的百分比确定模块和模块之间的时序约束。但是，该方法很难确定模块边界的实际时序情况，从而容易导致时序约束效率较低，以及模块时序无法收敛。
发明内容
本公开实施例至少提供一种集成电路的时序约束方法、装置、电子设备及芯片。
第一方面，本公开实施例提供了一种集成电路的时序约束方法，所述集成电路包含多个模块，包括：在基于多个模块的当前延时约束确定存在不满足时序收敛条件的模块的情况下，确定目标模块，并对所述目标模块进行逻辑综合处理，得到与所述目标模块的功能描述信息对应的第一综合结果；基于所述第一综合结果确定所述目标模块的实际延时时间；基于所述实际延时时间更新所述目标模块的当前延时约束，得到目标延时约束。
上述实施方式中，通过集成电路中各个模块的逻辑综合处理的综合结果确定对应模块的实际延时时间，进而根据该实际延时时间调整对应模块的延时约束，由此，可以更加合理的确定出集成电路中各个模块的时间约束条件，在根据该时间约束条件进行集成电路的时序收敛时，可以加快集成电路中各个模块之间的时序收敛速度。
一种可选的实施方式中，所述基于所述实际延时时间更新所述目标模块的当前延时约束，得到目标延时约束，包括：获取所述多个模块之间的连接关系；基于所述连接关系在所述多个模块中确定与所述目标模块相连接的相邻模块；基于所述相邻模块的实际延时时间和所述目标模块的实际延时时间，更新所述目标模块的当前延时约束，得到所述目标延时约束。
上述实施方式中，通过基于与目标模块相连接的模块的实际延时时间和该目标模块的实际延时时间来更新目标模块的当前延时约束，得到目标延时约束，可以更加合理的确定出集成电路中目标模块的时间约束条件，在根据该时间约束条件进行集成电路的时 序收敛时，可以加快集成电路中各个模块之间的时序收敛速度。
一种可选的实施方式中，所述基于所述相邻模块的实际延时时间和所述目标模块的实际延时时间，更新所述目标模块的当前延时约束，得到所述目标延时约束，包括：基于所述相邻模块的实际延时时间和所述目标模块的实际延时时间，确定信号从所述相邻模块的第一级时序单元传输至所述目标模块的第一级时序单元的目标延时时间；基于所述目标延时时间更新所述目标模块的当前延时约束，得到所述目标延时约束。
上述实施方式中，通过信号从相邻模块的第一级时序单元传输至目标模块的第一级时序单元的目标延时时间来更新目标模块的当前延时约束，可以为每个模块得到合理的约束条件，在采用该约束条件进行综合和布局布线处理时，可以加快模块之间的时序收敛速度。
一种可选的实施方式中，所述当前延时约束包含输入延时约束，所述相邻模块为与目标模块的输入边界端连接的模块；所述基于所述目标延时时间更新所述目标模块的当前延时约束，得到所述目标延时约束，包括：确定信号从所述相邻模块的第一级时序单元的输出端传输至所述相邻模块的输出边界端的延时时间，得到第一延时；确定所述第一延时在所述目标延时时间中的占比，得到第一占比；基于所述第一占比更新所述输入延时约束，得到所述目标延时约束中的输入延时约束。
一种可选的实施方式中，所述当前延时约束包含输出延时约束；所述相邻模块为与目标模块的输出边界端连接的模块；所述基于所述目标延时时间更新所述目标模块的当前延时约束，得到所述目标延时约束，还包括：确定信号从所述相邻模块的输入边界端传输至所述相邻模块的第一级时序单元的延时时间，得到第二延时；确定所述第二延时在所述目标延时时间中的占比，得到第二占比；基于所述第二占比更新所述输出延时约束，得到所述目标延时约束中的输出延时约束。
上述实施方式中，通过计算信号从相邻模块的第一级时序单元的输出端传输至相邻模块的输出边界端的延时时间在目标延时时间中的占比来确定输入延时约束，可以提高输入延时约束的合理性。同样地，通过计算信号从所述目标模块的输入边界端传输至所述目标模块的第一级时序单元的延时时间在目标延时时间中的占比来确定输出延时约束，可以提高输出延时约束的合理性。在确定输入延时约束和输出延时约束之后，基于该延时约束进行集成电路的时序收敛，可以提高模块之间的时序收敛速度。
一种可选的实施方式中，所述方法还包括：基于所述目标延时约束确定所述目标模块是否满足所述时序收敛条件；在基于所述目标延时约束确定所述目标模块满足时序收敛条件的情况下，基于所述目标延时约束对所述目标模块进行布局布线。
一种可选的实施方式中，基于所述目标延时约束确定所述目标模块满足时序收敛条件的方式包括：基于所述目标延时约束对所述目标模块进行重新逻辑综合处理，得到与所述目标模块的功能描述信息对应的第二综合结果；基于所述第二综合结果，更新所述多个模块中任意两个相连接模块之间的时序路径的实际延时时间；所述时序路径为信号在所述两个相连接模块的第一级时序单元之间的传输路径；在确定每个时序路径的实际延时时间满足预设时钟要求的情况下，确定所述目标模块满足时序收敛条件。
上述实施方式中，由于通过上述所描述的方式确定出的目标延时约束的合理性更强，因此，在基于该目标延时约束对目标模块进行重新逻辑综合处理时，可以优化目标模块的电路逻辑，从而能够快速的得到满足时序收敛条件的集成电路。
一种可选的实施方式中，所述方法还包括：基于所述时序路径的所述实际延时时间，更新所述目标模块所对应时序路径的路径权重；所述基于所述目标延时约束对所述目标模块进行重新逻辑综合处理，得到与所述目标模块的功能描述信息对应的第二综合结果， 包括：基于所述路径权重和所述目标延时约束对所述目标模块进行重新逻辑综合处理，得到所述第二综合结果。
上述实施方式中，通过结合路径权重以及目标延时约束对目标模块重新进行逻辑综合处理，可以提高第二综合结果可信度，从而进一步加快集成电路中模块之间的时序收敛的速度。
一种可选的实施方式中，所述方法还包括：基于所述目标延时约束确定所述目标模块是否满足所述时序收敛条件；在基于所述目标延时约束确定所述目标模块不满足所述时序收敛条件的情况下，将所述目标延时约束确定为所述目标模块的当前延时约束，并重新确定新的目标模块、对所述新的目标模块进行新的逻辑综合处理、确定新的实际延时时间、以及得到新的目标延时约束，直至基于得到的所述新的目标延时约束确定所述新的目标模块满足所述时序收敛条件。
上述实施方式中，由于通过上述所描述的方式确定出的目标延时约束的合理性更强，因此，在基于该目标延时约束对目标模块进行重新逻辑综合处理时，可以优化目标模块的电路逻辑，从而能够快速的得到满足时序收敛条件的集成电路。
一种可选的实施方式中，所述在基于多个模块的当前延时约束确定存在不满足时序收敛条件的模块的情况下，确定目标模块，包括：确定所述多个模块为所述目标模块；或者确定所述多个模块中存在的不满足所述时序收敛条件的模块为所述目标模块。
上述实施方式中，通过将集成电路中的多个模块均确定为目标模块，从而使得各个模块之间的延时约束更加准确。在集成电路中包含的模块的数量较多的情况下，通过将不满足时序收敛条件的模块确定为目标模块，并通过上述描述的方式对该目标模块进行时序约束处理，可以减少处理的数据量，从而提高集成电路的时序约束的效率，缩短实现时序约束所需的时间。
第二方面，本公开实施例还提供一种集成电路的时序约束装置，包括：第一确定模块，用于在基于集成电路包含的多个模块的当前延时约束确定存在不满足时序收敛条件的模块的情况下，确定目标模块，并对所述目标模块进行逻辑综合处理，得到与所述目标模块的功能描述信息对应的第一综合结果；第二确定模块，用于基于所述第一综合结果确定所述目标模块的实际延时时间；更新模块，用于基于所述实际延时时间更新所述目标模块的当前延时约束，得到目标延时约束。
第三方面，本公开实施例还提供一种电子设备，包括：处理器、存储器和总线，所述存储器存储有所述处理器可执行的机器可读指令，当电子设备运行时，所述处理器与所述存储器之间通过总线通信，所述机器可读指令被所述处理器执行时执行上述第一方面，或第一方面中任一种可能的实施方式中的步骤。
第四方面，本公开实施例还提供一种芯片，所述芯片采用上述第一方面，或第一方面中任一种可能的实施方式所述的集成电路的时序约束方法进行时序约束，并在基于所述目标延时约束确定所述目标模块满足时序收敛条件的情况下，基于所述目标延时约束对所述目标模块进行布局布线。
第五方面，本公开实施例还提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器运行时执行上述第一方面，或第一方面中任一种可能的实施方式中的步骤。
本公开实施例提供的一种集成电路的时序约束方法、装置、电子设备及存储介质。在本公开技术方案中，通过集成电路中各个模块的逻辑综合处理的综合结果确定对应模块的实际延时时间，进而根据该实际延时时间调整对应模块的延时约束，由此，可以更 加合理的确定出集成电路中各个模块的时间约束条件，在根据该时间约束条件进行集成电路的时序收敛时，可以加快集成电路中各个模块之间的时序收敛速度。
为使本公开的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，此处的附图被并入说明书中并构成本说明书中的一部分，这些附图示出了符合本公开的实施例，并与说明书一起用于说明本公开的技术方案。应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1示出了本公开实施例所提供的一种集成电路的时序约束方法的流程图；
图2示出了一种相关技术中集成电路中模块的延时约束的示意图；
图3示出了本公开实施例所提供的一种集成电路中多个相连接的目标模块之间的实际延时时间的示意图；
图4示出了本公开实施例所提供的一种模块A和模块B之间的时序路径的示意图；
图5示出了本公开实施例所提供的一种集成电路的时序约束装置的示意图；
图6示出了本公开实施例所提供的一种电子设备的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。因此，以下对在附图中提供的本公开的实施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
本文中术语“和/或”，仅仅是描述一种关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中术语“至少一种”表示多种中的任意一种或多种中的至少两种的任意组合，例如，包括A、B、C中的至少一种，可以表示包括从A、B和C构成的集合中选择的任意一个或多个元素。
在相关技术的时序约束方法中，通过时钟周期的百分比确定模块和模块之间的时序约束。但是，该方法很难确定模块边界的实际时序情况，从而容易导致时序约束效率较低，以及模块时序无法收敛。
基于上述研究，本公开提供了一种集成电路的时序约束方法、装置、电子设备及存储介质。在本公开技术方案中，通过集成电路中各个模块的逻辑综合处理的综合结果确定对应模块的实际延时时间，进而根据该实际延时时间调整对应模块的延时约束，由此，可以更加合理的确定出集成电路中各个模块的时间约束条件，在根据该时间约束条件进 行集成电路的时序收敛时，可以加快集成电路中各个模块之间时序的收敛速度。
为便于对本实施例进行理解，首先对本公开实施例所公开的一种集成电路的时序约束方法进行详细介绍，本公开实施例所提供的集成电路的时序约束方法的执行主体一般为具有一定计算能力的电子设备，如计算机、服务器等。
参见图1所示，为本公开实施例提供的一种集成电路的时序约束方法的流程图，所述方法包括步骤S101～S105，其中：
S101：在基于集成电路的多个模块的当前延时约束确定存在不满足时序收敛条件的模块的情况下，确定目标模块，并对所述目标模块进行逻辑综合处理，得到与所述目标模块的功能描述信息对应的第一综合结果。
在本公开实施例中，首先将集成电路划分为多个模块。例如，可以根据模块功能将该集成电路划分成多个不同的功能模块，即上述多个模块。
这里，多个模块的当前延时约束为上一次仿真处理更新得到的每个模块的延时约束。其中，每个模块的延时约束包含输入延时约束和输出延时约束，其中，延时约束又可以称为I/O(Input/Output，输入输出)约束。
在初始时刻，如第一次进行仿真处理之前，集成电路中每个模块的当前延时约束可以根据该集成电路中每个模块的延时时间占时钟周期的百分比来确定。其中，时钟周期为集成电路中最基本时间单位，用于表征该集成电路中对应模块完成一个最基本的动作的时间。
如图2所示为集成电路中模块A在初始时刻的当前延时约束的示意图。如图2所示，在初始时刻，模块A的输入延时约束可以设置为0.65clk(clock，时钟周期)，0.65clk即65％的时钟周期，模块A的输出延时约束可以设置为0.45clk。
集成电路中可包括多种时钟，而不同的时钟对应不同的时钟周期，例如频率为100MHz的时钟的时钟周期为10ns。为了简单起见，本公开实施例中，以对使用相同的第一时钟的多个模块进行约束为例，说明本公开的实现方法。本领域技术人员可知，本方法还可以对使用与第一时钟不同的第二时钟的多个模块进行约束，对使用第三时钟的多个模块进行约束，等等，本公开对此不做限制。此外，一个模块可能包括多个使用同一时钟的I/O信号(或称I/O管脚)，本公开不限制I/O信号的数量。本领域技术人员可知，一个模块的不同信号可以设置相同或不同的延时约束条件，也可以具有相同或不同的延时约束结果，本公开对此不做限制。
在确定出上述多个模块的当前约束延时之后，就可以确定多个模块中是否存在不满足时序收敛条件的模块。具体的，可以通过动态仿真的方式来确定出是否存在不满足时序收敛条件的模块，例如，通过EDA(Electronic Design Automation，电子设计自动化)工具对集成电路进行动态仿真，从而确定出是否存在不满足时序收敛条件的模块。该EDA工具可以为芯片设计辅助软件、可编程芯片辅助设计软件、系统设计辅助软件等。
在根据模块的动态仿真结果确认集成电路中包含不满足时序收敛条件的模块的情况下，可以在集成电路中确定目标模块。这里，目标模块可以为集成电路中的全部模块，还可以为集成电路中不满足时序收敛条件的模块，本公开对此不作具体限定。
具体实施时，通过EDA工具对集成电路进行动态仿真之后，就可以确定出集成电路是否存在不满足时序收敛条件的模块。如果确定出存在不满足时序收敛条件的模块，则可以由EDA工具通过EDA工具的动态仿真结果确定该集成电路中不满足时序收敛条件的模块；之后，可以将该不满足时序收敛条件的模块确定为目标模块。除此之外，还可以在确定出集成电路中包含不满足时序收敛条件的模块的情况下，将该集成电路的全 部模块确定为目标模块。
这里，模块满足时序收敛条件可以理解为：模块在处理对应信号时，满足时序要求；否则不满足时序收敛条件。
由于一个模块可包括多个I/O信号，示例性的，若其中一个I/O管脚不满足时序收敛条件，则可以认为该模块不满足时序收敛条件。因此，模块满足时序收敛条件可以进一步理解为：对于该模块中的每个I/O信号，在处理该信号时，均满足时序要求；若至少有一个信号不满足时序要求，则该模块不满足时序收敛条件。
在确定出目标模块后，就可以在上述EDA工具中对该目标模块进行逻辑综合处理，具体的，可以通过RTL(Register Transfer Level，寄存器传输级别)编码对该目标模块进行逻辑综合处理，从而得到第一综合结果。本公开实施例中，在确定出多个目标模块的情况下，可以分别针对每个目标模块进行逻辑综合处理。
这里，RTL编码用于描述集成电路中每个模块的功能。逻辑综合处理又可以称为物理综合处理，用于通过RTL语言描述各个模块的功能，从而实现将每个模块转换为具有相应功能的电路结构。通过对目标模块进行物理综合处理，可以确定该目标模块在集成电路中的占用面积，以及该目标模块中的输入端和输出端在集成电路中的位置等物理结构信息。因此，上述第一综合结果用于指示与模块的功能描述信息对应的逻辑电路的结构信息。
S103：基于所述第一综合结果确定所述目标模块的实际延时时间，所述实际延时时间为信号在目标模块的边界与目标模块的第一级时序单元之间传输所需的时间。
这里，目标模块的边界可以包括目标模块的输入边界端、输出边界端。实际延时时间包含实际输入延时和实际输出延时，其中，实际输入延时用于表征目标模块的输入边界端到第一级时序单元之间的延时时间，例如输入端口到与该输入端口相连的寄存器/触发器等时序器件之间的延时，实际输出延时用于表征目标模块的相关时序单元到输出边界端之间的延时时间。本公开实施例中，实际延时时间、延时、延时时间等可以指延迟时长，例如650ps(皮秒)。
在得到第一综合结果之后，就可以确定出每个模块中各个晶体管之间的逻辑连接关系，此时，就可以根据该逻辑连接关系确定出上述实际输入延时和实际输出延时。
对于每个模块中的各个I/O管脚来讲，可以通过逻辑综合处理得到每个I/O管脚的实际输入延时和实际输出延时。
在本公开实施例中，如图3所示，假设，模块A、模块B和模块C均为目标模块且彼此紧邻设置，因此，模块A和模块B之间、模块B和模块C之间的延时忽略不计。其中，t 1表示模块A的管脚A1实际输出延时，该实际输出延时t 1用于表示管脚A1上的信号从模块A上与管脚A1相连的第一级时序单元到达模块A上对应于管脚A1的输出边界端的时间，由于模块A和模块B之间的延时可以忽略不计，因此，图3中t 1指示模块B的输入边界端而非模块A的输出边界端。t 2为模块B的管脚B1实际输入延时，该实际输入延时t 2用于表示管脚B1上的信号从模块B上对应于管脚B1的输入边界端到达模块B上对应于管脚B1的第一级时序单元的时间。t 3表示模块B的管脚B2实际输出延时，该实际输出延时t 3用于表示管脚B2上的信号从模块B上对应于管脚B2的第一级时序单元到达模块B上对应于管脚B2的输出边界端的时间；由于模块B与模块C之间的延时可以忽略不计，因此，图3中示出的t 3指示模块C的输入边界端而非模块B的输出边界端。t 4为模块C的管脚C1实际输入延时，该实际输入延时t 4用于表示管脚C1上的信号从模块C上对应于管脚C1的输入边界端到达模块C上对应于管脚C1的第一级时序单元的时间。
为简单起见，图3中模块B中只显示了一个第一级时序单元，本领域技术人员可知，模块B中可以有多个第一级时序单元，管脚B1和管脚B2相连的第一级时序单元可以是或不是同一个时序单元。
S105：基于所述实际延时时间更新所述目标模块的当前延时约束，得到目标延时约束。
在确定出目标模块的实际延时时间之后，就可以通过实际延时时间中的实际输入延时和实际输出延时，更新目标模块的当前延时约束，得到目标延时约束。
延时约束中的输入延时约束可以理解为：外部的输出信号到达模块的输入边界端的延时约束信息，其中，与一模块相连接且传输信号至该模块的模块可以称为上游模块，外部的输出信号可以理解为上游模块的第一级时序单元输出的信号。延时约束中的输出延时约束可以理解为：信号从下游模块的输入边界端输入至该下游模块的第一级时序单元的延时约束信息，其中，与目标模块相连接且接收目标模块所传输信号的下一级模块可以称为下游模块。本公开实施例中，在上游模块与目标模块紧邻的情况下，输入延时约束也可以理解为：外部的输出信号到达上游模块的输出边界端的延时约束信息。
如图3所示，此时，模块B为模块A的下游模块，模块A为模块B的上游模块。模块B的输入延时约束与模块A的实际输出延时t 1相关联，在确定出模块A的实际输出延时t 1之后，通过该实际输出延时确定模块B的输入延时约束；模块B的输出延时约束与模块C的实际输入延时t 4相关联，在确定出模块C的实际输入延时t 4之后，通过该实际输入延时确定模块B的输出延时约束；这样可以为模块B确定出一个更加合理的时间约束条件，从而加快模块A和模块B、模块B和模块C之间的时序收敛。
通过上述描述可知，集成电路中的各个模块满足时序收敛条件可以理解为：集成电路中的各个模块在处理对应信号时，满足时序要求。如图3所示，这里的满足时序要求可以理解为一个信号从模块A的第一级时序单元传输到模块B的第一级时序单元需要在一个时钟周期内完成。假设该时钟周期是1纳秒，此时，若设置该信号在模块B的输入延时约束为延时不高于650ps，可以理解为信号从模块A的第一级时序单元传输到模块A的边界要在650ps内完成，此时，为了满足时序收敛条件，要求在该信号从模块B的边界传输至模块B的第一级时序单元在剩下的350ps内完成，也即，该信号在模块A的输出延时约束为延时不高于350ps。
在本公开技术方案中，通过集成电路中各个模块的逻辑综合处理的综合结果确定对应模块的实际延时时间，进而根据该实际延时时间调整对应模块的延时约束，由此，可以更加合理的确定出集成电路中各个模块的时间约束条件，在根据该时间约束条件进行集成电路的时序收敛时，可以加快集成电路中各个模块之间的时序收敛速度。
在一个可选的实施方式中，该方法还包括：在基于所述目标延时约束确定所述目标模块满足时序收敛条件的情况下，基于所述目标延时约束对所述目标模块进行布局布线。
在本公开实施例中，在确定出上述目标模块的目标延时约束后，就可以通过动态仿真的方式，按照目标延时约束，对目标模块进行模拟运行，从而确定出目标模块是否满足时序收敛条件。
若目标模块满足时序收敛条件，那么EDA工具就可以对该目标模块进行模拟布局布线。若目标模块不满足时序收敛条件，那么可以将该目标延时约束确定为目标模块的当前延时约束，返回执行上述步骤S101至S105，直至基于得到的新的目标延时约束确定新的目标模块满足所述时序收敛条件，即直至确定出集成电路中的每个模块满足时序收敛条件。
在一个可选的实施方式中，步骤S101，在基于多个模块的当前延时约束确定存在不满足时序收敛条件的模块的情况下，确定目标模块，具体包括以下两种情况。
情况一：确定所述多个模块为所述目标模块。
在此情况下，可以将集成电路中的每个模块分别确定为目标模块。由于集成电路中 各个模块之间是相互连接的，因此，为了保证相连接模块之间的时序收敛性，可以将集成电路中的每个模块分别确定为目标模块。然后，通过上述描述的方式对每个模块进行时序约束处理。
情况二：确定所述多个模块中存在的不满足所述时序收敛条件的模块为所述目标模块。
在本公开实施例中，在检测到上述多个模块中存在不满足时序收敛条件的模块时，可以通过EDA工具的动态仿真结果确定该集成电路中不满足时序收敛条件的模块，进而将不满足时序收敛条件的模块确定为目标模块。
通过上述描述可知，在本公开实施例中，通过将集成电路中的多个模块均确定为目标模块，从而使得各个模块之间的延时约束更加准确。在集成电路中包含的模块的数量较多的情况下，通过将不满足时序收敛条件的模块确定为目标模块，并通过上述描述的方式对该目标模块进行时序约束处理，可以减少处理的数据量，从而提高集成电路的时序约束的效率，缩短实现时序约束所需的时间。
在一个可选的实施方式中，步骤S105，基于所述实际延时时间更新所述目标模块的当前延时约束，得到目标延时约束，具体包括如下过程：
S1051：获取多个模块之间的连接关系。
S1052：基于连接关系在多个模块中确定与目标模块相连接的相邻模块。
S1053：基于所述相邻模块的实际延时时间和所述目标模块的实际延时时间，更新所述目标模块的当前延时约束，得到所述目标延时约束。
在本公开实施例中，在通过上述EDA工具对目标模块进行动态仿真时，就可以通过基于该动态仿真的动态仿真结果确定出多个模块的连接关系，其中，该连接关系可以利用多个模块的模块标识表示。在确定出多个模块的连接关系的基础上，基于目标模块的模块标识，确定出与该目标模块相连接的相邻模块。其中，与该目标模块相连接的模块可以分为上游模块和/或下游模块。具体的，信号的传输方向为从上游模块传输至目标模块，和/或从目标模块传输至下游模块，本公开技术方案中与目标模块的输入端相连接的相邻模块为上游模块，与目标模块的输出端相连接的相邻模块为下游模块。
如图3所示，若模块B为目标模块，那么模块A以及模块C为该目标模块相连接的模块，其中，模块A为上游模块，模块C为下游模块，此时，模块A为与模块B的输入端相连接的相邻模块。若模块A为目标模块，那么模块B为该目标模块相连接的下游模块。
在确定出上述相邻模块后，就可以确定模块A、B和C的实际延时时间，从而基于上述实际延时时间，对上述模块B的当前延时约束进行更新，得到该模块B的目标延时约束，具体过程可以描述如下：基于相邻模块的实际输出延时和目标模块的实际输入延时，对目标模块的当前延时约束进行更新，从而得到该目标模块的目标延时约束。
如图3所示，可以基于模块A的实际输出延时t 1、模块B的实际输入延时t 2和实际输出延时t 3以及模块C的实际输入延时t 4，更新模块B的输入延时约束和输出延时约束，从而得到模块B的目标延时约束。
上述实施方式中，通过基于与目标模块相连接的模块的实际延时时间和该目标模块的实际延时时间来更新目标模块的当前延时约束，得到目标延时约束，可以更加合理的确定出集成电路中目标模块的时间约束条件，在根据该时间约束条件进行集成电路的时序收敛时，可以加快集成电路中各个模块之间的时序收敛速度。
在一个可选的实施方式中，S1053，基于所述相邻模块的实际延时时间和所述目标模块的实际延时时间，更新所述目标模块的当前延时约束，得到所述目标延时约束，具体包括如下过程。
S11，基于所述相邻模块的实际延时时间和所述目标模块的实际延时时间，确定信号在所述相邻模块的第一级时序单元与所述目标模块的第一级时序单元之间传输所用 的目标延时时间。
S12，基于所述目标延时时间更新所述目标模块的当前延时约束，得到所述目标延时约束。
在本公开实施例中，如图4所示，模块B为目标模块，模块A为该目标模块的相邻模块。
通过上述描述可知，模块满足时序收敛条件可以理解为：集成电路中的各个模块在处理对应信号时，满足时序要求。即信号从上游模块的第一级时序单元传输至目标模块的第一级时序单元的目标延时时间，要满足一个时钟周期，如不超过一个时钟周期。例如，如图4所示，这里的满足时序要求可以理解为一个信号从模块A的第一级时序单元传输到模块B的第一级时序单元需要在一个时钟周期内完成。
例如，在图4中，t 1用于表征信号从模块A的第一级时序单元的输出端传输至模块A的输出边界端的传输时间，其中，由于模块A和模块B紧邻设置，模块A和模块B之间的延时忽略不计，图4中t 1指示模块B的输入边界端而非模块A的输出边界端。t 2用于表征信号从模块B的输入边界端传输至模块B的第一级时序单元的输入端的传输时间。此时，就可以基于t 1和t 2确定上述目标延时时间。进而，基于该目标延时时间更新目标模块的当前延时约束，得到目标延时约束。
通过上述描述可知，I/O约束包含输入延时约束(Input delay)和输出延时约束(Output delay)。通过上述描述可知，模块B的输入延时约束可以理解为模块A的第一级时序单元输出的信号到达模块B的输入边界端的延时约束信息。因此，该模块B的输入延时约束与模块A的实际输出延时相关联。模块A的输出延时约束可以理解为信号从模块B的输入边界端输入至该模块B的第一级时序单元的延时约束信息。因此，该模块A的输出延时约束与模块B的实际输入延时相关联。
又由于模块A的实际输出延时和模块B的实际输入延时要求满足一个时钟周期，因此，可以通过模块A的实际输出延时和模块B的实际输入延时，更新目标模块的当前延时约束，得到所述目标延时约束。
通过上述描述可知，通过信号从相邻模块的第一级时序单元传输至目标模块的第一级时序单元的目标延时时间来更新目标模块的当前延时约束，可以为每个模块得到合理的约束条件，在采用该约束条件进行综合和布局布线处理时，可以加快模块之间的时序收敛速度。
在本公开实施例中，在确定出目标延时时间后，就可以基于该目标延时时间更新目标模块的当前延时约束，得到目标模块的目标延时约束。
情况一：当前延时约束包括上述目标模块的输入延时约束。
上述步骤：基于所述目标延时时间更新所述目标模块的当前延时约束，得到所述目标延时约束，具体包括如下过程：
S21，确定信号从所述相邻模块的第一级时序单元的输出端传输至所述相邻模块的输出边界端的延时时间，得到第一延时。
S22，确定所述第一延时在所述目标延时时间中的占比，得到第一占比。
S23，基于所述第一占比更新所述输入延时约束，得到所述目标延时约束中的输入延时约束。
在本公开实施例中，可以获取信号从模块A的第一级时序单元的输出端传输至模块A的输出边界端的实际延时时间(也即模块A的实际输出延时)t 1，并将该实际输出延时t 1确定为上述第一延时。
在基于上述第一延时以及目标延时时间计算第一占比B input时，具体可以通过下述公式(1)进行计算：
Figure PCTCN2022118057-appb-000001
其中，t 2为信号从模块B的输入边界端传输至模块B的第一级时序单元的输入端的实际延时时间(也即，模块B的实际输入延时)，clk period为集成电路的时钟周期。clk uncentainty表示时钟不确定性，用于表示时钟边沿实际到达时间与理论到达时间之间的差异和变化。
具体的，clk uncentainty＝clk skew+clk jitter。其中，clk skew为时钟周期由于传输路径不同而导致的时间差异，clk jitter为相邻的时钟周期间由于时钟源不稳定而产生的周期边沿的时间差异。因此，clk period-clk uncentainty的结果应为上述集成电路中的信号在实际传输过程中的时钟周期clk。
在确定出上述第一占比B input后，就可以将该第一占比B input更新为目标模块的输入延时约束。应理解的是，若需要目标模块满足时序收敛条件，那么，上述相邻模块的实际延时时间t 1以及目标模块的实际延时时间t 2的和应满足集成电路的时钟周期，例如，t 1+t 2应小于或等于一个时钟周期的时间值，但是若t 1+t 2大于一个时钟周期的时间值，则目标模块不满足时序收敛条件。
示例性地，若上述时钟周期clk为1纳秒(ns)，t 1为650皮秒(ps)，t 2为450皮秒，此时，t 1+t 2大于一个时钟周期的时间值，即650ps+450ps＝1100ps＝1.1ns＞1ns，因此该目标模块不满足时序收敛条件。然后，就可以计算得到上述第一延时t 1在目标延时时间中的第一占比，即模块B的输入延时约束B input＝0.59clk。
情况二：当前延时约束包括上述目标模块的输出延时约束。
上述步骤：基于所述目标延时时间更新所述目标模块的当前延时约束，得到所述目标延时约束，具体还包括如下过程：
(1)、确定信号从所述相邻模块的输入边界端传输至所述相邻模块的第一级时序单元的延时时间，得到第二延时。
(2)、确定所述第二延时在所述目标延时时间中的占比，得到第二占比。
(3)、基于所述第二占比更新所述输出延时约束，得到所述目标延时约束中的输出延时约束。
在本公开实施例中，模块A为目标模块，模块B为该目标模块的相邻模块。
具体的，如图4所示，t 2用于表征信号从模块B的输入边界端传输至模块B的第一级时序单元的延时时间，即第二延时。然后，就可以基于第二延时t 2确定模块A的输出延时约束。
这里，可以计算第二延时在目标延时时间中的占比，得到第二占比B output，进而，根据该第二占比确定目标延时约束中的输出延时约束。可以通过下述公式(2)计算第二延时在目标延时时间中的占比：
Figure PCTCN2022118057-appb-000002
其中，t 2为信号从相邻模块的输入边界端传输至所述相邻模块的第一级时序单元的延时时间，即上述第二延时，clk period为集成电路的时钟周期。clk uncentainty表示时钟不确定性，用于表示时钟边沿实际到达时间与理论到达时间之间的差异和变化。clk period-clk uncentainty的结果应为上述集成电路中的信号在实际传输过程中的时钟周期clk。
在本公开实施例中，在确定出上述第二占比B output后，就可以将该第二占比B output更新为目标模块的输出延时约束。
应理解的是，若需要目标模块满足时序收敛条件，那么，上述相邻模块的实际延时时间t 1以及目标模块的实际延时时间t 2的和应满足集成电路的时钟周期，例如t 1+t 2小于或等于一个时钟周期的时间值，但是若t 1+t 2大于一个时钟周期的时间值，则目标模块不满足时序收敛条件。
示例性地，若上述时钟周期clk为1纳秒(ns)，t 1为650皮秒(ps)，t 2为450皮秒，那么，t 1+t 2大于一个时钟周期的时间值。然后，就可以计算得到第二延时t 2在对应的目标延时时间中的第二占比，即模块A的输出延时约束B output＝0.41clk。
上述实施方式中，通过计算信号从相邻模块的第一级时序单元的输出端传输至相邻模块的输出边界端的延时时间在目标延时时间中的占比来确定输入延时约束，可以提高输入延时约束的合理性。同样地，通过计算信号从所述目标模块的输入边界端传输至所述目标模块的第一级时序单元的延时时间在目标延时时间中的占比来确定输出延时约束，可以提高输出延时约束的合理性。在确定输入延时约束和输出延时约束之后，基于该延时约束进行集成电路的时序收敛，可以提高模块之间的时序收敛速度。
在一个可选的实施方式中，上述步骤：基于所述目标延时约束确定所述目标模块是否满足时序收敛条件，具体包括如下过程。
S31：基于所述目标延时约束对所述目标模块进行重新逻辑综合处理，得到与所述目标模块的功能描述信息对应的第二综合结果。
S32：基于所述第二综合结果，更新所述多个模块中任意两个相连接模块之间的时序路径的实际延时时间；所述时序路径为信号在所述两个相连接模块的第一级时序单元之间的传输路径。
S33：在确定每个时序路径的实际延时时间满足预设时钟要求的情况下，确定所述目标模块满足时序收敛条件。
S34：在基于所述目标延时约束确定所述目标模块不满足所述时序收敛条件的情况下，基于所述目标模块的实际延时时间更新所述目标模块的当前延时约束，直至满足所述时序收敛条件。
在本公开实施例中，在确定出目标延时约束之后，可以基于该目标延时约束确定目标模块是否满足时序收敛条件。此时，可以基于目标延时约束，在EDA工具中对该目标模块重新进行逻辑综合处理，从而得到第二综合结果。
这里，对目标模块重新进行逻辑综合处理的过程与上述步骤S101中所描述的逻辑综合处理的过程相同。具体实施时，可以通过RTL编码对目标模块进行逻辑综合处理，从而得到第二综合结果。
这里，RTL编码用于描述集成电路中每个模块的功能。逻辑综合处理又可以称为物理综合处理，用于通过RTL语言描述各个模块的功能，从而实现将每个模块转换为 具有相应功能的电路结构。通过对目标模块进行物理综合处理，可以确定该目标模块在集成电路中的占用面积，以及该目标模块中的输入端和输出端在集成电路中的位置等物理结构信息。因此，上述第二综合结果用于指示与模块的功能描述信息对应的逻辑电路的结构信息。
在确定出上述第二综合结果后，更新集成电路的多个模块中任意两个相连接模块之间的时序路径的实际延时时间。假设，任意两个相连接模块为模块A和模块B，此时，该实际延时时间为重新进行逻辑综合处理之后，模块A的实际输出延时和模块B的实际输入延时之间的总和。
在确定出多个模块中任意两个相连接模块之间的时序路径的实际延时时间之后，就可以判断该实际延时时间是否满足预设时钟要求。例如，可以判断该实际延时时间是否小于或者等于上述时钟周期。如果实际延时时间小于或者等于上述时钟周期，则确定满足预设时钟要求，此时，可以确定目标模块满足时序收敛条件。如果判断出不满足预设时钟要求，则可以将目标延时约束作为当前延时约束，返回执行步骤S101-步骤S105，直至得到满足所述时序收敛条件的目标延时约束。
示例性地，如图3所示，模块A、模块B和模块C为目标模块，为简单起见，上述目标模块包括两条时序路径L 1和L 2，其中，L 1即信号从模块A的第一级时序单元的输出端到达模块B的第一级时序单元的输入端的路径。另外，L 2为信号从模块B的第一级时序单元的输出端到达模块C的第一级时序单元的输入端的路径。
在确定出上述时序路径之后，可以确定每个时序路径的实际延时时间，进而确定该实际延时时间是否满足预设时钟要求。
以时序路径L 1为例，可以判断该时序路径L 1的实际延时时间(即模块A的实际输出延时和模块B的实际输入延时之和)是否在一个时钟周期内。如果判断出是，则确定该时序路径L 1满足预设时钟要求，此时，可以确定出模块A和模块B之间的时序路径满足时序收敛条件。
以时序路径L 2为例，可以判断该时序路径L 2的实际延时时间(即模块B的实际输出延时和模块C的实际输入延时之和)是否在一个时钟周期内。如果判断出是，则确定该时序路径L 2满足预设时钟要求，此时，可以确定出模块C和模块B之间的时序路径L 2满足时序收敛条件。
上述实施方式中，由于通过上述所描述的方式确定出的目标延时约束的合理性更强，因此，在基于该目标延时约束对目标模块进行重新逻辑综合处理时，可以优化目标模块的电路逻辑，从而能够快速的得到满足时序收敛条件的集成电路。
在一个可选的实施方式中，该方法还包括如下步骤：
基于所述时序路径的实际延时时间，更新所述目标模块所对应时序路径的路径权重。
在此情况下，上述步骤基于所述目标延时约束对所述目标模块进行重新逻辑综合处理，得到与所述目标模块的功能描述信息对应的第二综合结果，包括：基于所述路径权重和所述目标延时约束对所述目标模块进行重新逻辑综合处理，得到所述第二综合结果。
在本公开实施例中，在确定出目标模块B的实际输入延时t 2以及模块B的实际输出延时t 3之后，就可以基于实际输入延时t 2和实际输出延时t 3计算模块B所对应的时序路径的路径权重B weight，具体计算公式描述如公式(3)：
Figure PCTCN2022118057-appb-000003
在确定出上述路径权重之后，就可以结合该路径L 1的权重B weight以及上述目标延 时约束对该目标模块重新进行逻辑综合处理，得到上述第二综合结果。本公开实施例中，在模块B包含多个I/O管脚的情况下，可以将各I/O管脚的实际输出延时的平均值作为t 3，从而利用t 3计算模块B所对应的时序路径L1的路径权重B weight。
具体实施时，可以将路径权重和目标延时约束输入到EDA工具中，进而根据该EDA工具基于该路径权重和目标延时约束对目标模块重新进行逻辑综合处理。
路径权重较大会影响逻辑综合处理之后集成电路的内部电路的时序收敛结果；然而，当路径权重较小时，无法为集成电路中的每个模块给出合理的I/O约束，从而导致每个路径的I/O约束过松或者过紧。采用本公开所提供的路径权重的优化方式，可以在保证每个路径的I/O约束不会过松，也不会过紧的情况下，得到一个时序收敛效果较好的综合结果。
通过上述描述可知，在本公开实施例中，通过结合路径权重以及目标延时约束对目标模块重新进行逻辑综合处理，可以提高第二综合结果可信度，从而进一步加快集成电路中模块之间的时序收敛的速度。
本领域技术人员可以理解，在具体实施方式的上述方法中，各步骤的撰写顺序并不意味着严格的执行顺序而对实施过程构成任何限定，各步骤的具体执行顺序应当以其功能和可能的内在逻辑确定。
基于同一发明构思，本公开实施例中还提供了与集成电路的时序约束方法对应的集成电路的时序约束装置，由于本公开实施例中的装置解决问题的原理与本公开实施例上述集成电路的时序约束方法相似，因此装置的实施可以参见方法的实施，重复之处不再赘述。
参照图5所示，为本公开实施例提供的一种集成电路的时序约束装置的示意图，所述装置包括：第一确定模块51、第二确定模块52、更新模块53；其中，
第一确定模块51，用于在基于多个模块的当前延时约束确定存在不满足时序收敛条件的模块的情况下，确定目标模块，并对所述目标模块进行逻辑综合处理，得到与所述目标模块的功能描述信息对应的第一综合结果；
第二确定模块52，用于基于所述第一综合结果确定所述目标模块的实际延时时间；
更新模块53，用于基于所述实际延时时间更新所述目标模块的当前延时约束，得到目标延时约束。
在本公开技术方案中，通过集成电路中各个模块的逻辑综合的综合结果确定对应模块的实际延时时间，进而根据该实际延时时间调整对应模块的延时约束的方式，可以更加合理的确定出集成电路中各个模块的时间约束条件，在根据该时间约束条件进行集成电路的时序收敛时，可以加快集成电路中各个模块之间的收敛速度。
一种可能的实施方式中，更新模块53，还用于：获取所述多个模块之间的连接关系；基于所述连接关系在所述多个模块中确定与所述目标模块相连接的相邻模块；基于所述相邻模块的实际延时时间和所述目标模块的实际延时时间，更新所述目标模块的当前延时约束，得到所述目标延时约束。
一种可能的实施方式中，更新模块53，还用于：基于所述相邻模块的实际延时时间和所述目标模块的实际延时时间，确定信号从所述相邻模块的第一级时序单元传输至所述目标模块的第一级时序单元的目标延时时间；基于所述目标延时时间更新所述目标模块的当前延时约束，得到所述目标延时约束。
一种可能的实施方式中，所述当前延时约束包含输入延时约束，所述相邻模块为与目标模块的输入边界端连接的模块，更新模块53，还用于：确定信号从所述相邻模块的第一级时序单元的输出端传输至所述相邻模块的输出边界端的延时时间，得到第一延时；确定所述第一延时在所述目标延时时间中的占比，得到第一占比；基于所述第一占比更新所述输入延时约束，得到所述目标延时约束中的输入延时约束。
一种可能的实施方式中，所述当前延时约束包含输出延时约束；所述相邻模块为 与目标模块的输出边界端连接的模块；更新模块53，还用于：确定信号从所述相邻模块的输入边界端传输至所述相邻模块的第一级时序单元的延时时间，得到第二延时；确定所述第二延时在所述目标延时时间中的占比，得到第二占比；基于所述第二占比更新所述输出延时约束，得到所述目标延时约束中的输出延时约束。
一种可能的实施方式中，该装置还用于：基于所述目标延时约束确定所述目标模块是否满足所述时序收敛条件；在基于所述目标延时约束确定所述目标模块满足时序收敛条件的情况下，基于所述目标延时约束对所述目标模块进行布局布线。
一种可能的实施方式中，该装置还用于：基于所述目标延时约束对所述目标模块进行重新逻辑综合处理，得到与所述目标模块的功能描述信息对应的第二综合结果；基于所述第二综合结果，更新所述多个模块中任意两个相连接模块之间的时序路径的实际延时时间；所述时序路径为信号在所述两个相连接模块的第一级时序单元之间的传输路径；在确定每个时序路径的实际延时时间满足预设时钟要求的情况下，确定所述目标模块满足时序收敛条件。
一种可能的实施方式中，该装置还用于：基于所述时序路径的所述实际延时时间，更新所述目标模块所对应时序路径的路径权重；基于所述路径权重和所述目标延时约束对所述目标模块进行重新逻辑综合处理，得到所述第二综合结果。
一种可能的实施方式中，该装置还用于：基于所述目标延时约束确定所述目标模块是否满足所述时序收敛条件；在基于所述目标延时约束确定所述目标模块不满足所述时序收敛条件的情况下，将所述目标延时约束确定为所述目标模块的当前延时约束，并重新确定新的目标模块、对所述新的目标模块进行新的逻辑综合处理、确定新的实际延时时间、以及得到新的目标延时约束，直至基于得到的所述新的目标延时约束确定所述新的目标模块满足所述时序收敛条件。
一种可能的实施方式中，第一确定模块51，还用于：确定所述多个模块为所述目标模块；或者确定所述多个模块中存在的不满足所述时序收敛条件的模块为所述目标模块。
关于装置中的各模块的处理流程、以及各模块之间的交互流程的描述可以参照上述方法实施例中的相关说明，这里不再详述。
对应于图1中的集成电路的时序约束方法，本公开实施例还提供了一种电子设备600，如图6所示，为本公开实施例提供的电子设备600结构示意图，包括：
处理器61、存储器62、和总线63；存储器62用于存储执行指令，包括内存621和外部存储器622；这里的内存621也称内存储器，用于暂时存放处理器61中的运算数据，以及与硬盘等外部存储器622交换的数据，处理器61通过内存621与外部存储器622进行数据交换，当所述电子设备600运行时，所述处理器61与所述存储器62之间通过总线63通信，使得所述处理器61执行以下指令：
在基于多个模块的当前延时约束确定存在不满足时序收敛条件的模块的情况下，确定目标模块，并对所述目标模块进行逻辑综合处理，得到与所述目标模块的功能描述信息对应的第一综合结果；基于所述第一综合结果确定所述目标模块的实际延时时间；基于所述实际延时时间更新所述目标模块的当前延时约束，得到目标延时约束。
本公开实施例还提供一种芯片，该芯片在布局布线之前，采用上述的集成电路的时序约束方法进行时序约束，并在基于所述目标延时约束确定所述目标模块满足时序收敛条件的情况下，基于所述目标延时约束对所述目标模块进行布局布线。
本公开实施例还提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器运行时执行上述方法实施例中所述的集成电路的时序约束方法的步骤。其中，该存储介质可以是易失性或非易失的计算机可读取存储介质。
本公开实施例还提供一种计算机程序产品，该计算机程序产品承载有程序代码，所述程序代码包括的指令可用于执行上述方法实施例中所述的集成电路的时序约束方 法的步骤，具体可参见上述方法实施例，在此不再赘述。
其中，上述计算机程序产品可以具体通过硬件、软件或其结合的方式实现。在一个可选实施例中，所述计算机程序产品具体体现为计算机存储介质，在另一个可选实施例中，计算机程序产品具体体现为软件产品，例如软件开发包(Software Development Kit，SDK)等等。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统和装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。在本公开所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，又例如，多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些通信接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个处理器可执行的非易失的计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对相关技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台电子设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上所述实施例，仅为本公开的具体实施方式，用以说明本公开的技术方案，而非对其限制，本公开的保护范围并不局限于此，尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，其依然可以对前述实施例所记载的技术方案进行修改或可轻易想到变化，或者对其中部分技术特征进行等同替换；而这些修改、变化或者替换，并不使相应技术方案的本质脱离本公开实施例技术方案的精神和范围，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应所述以权利要求的保护范围为准。

Claims (14)

  1. 一种集成电路的时序约束方法，其特征在于，所述集成电路包含多个模块，所述方法包括：
    在基于所述多个模块的当前延时约束确定存在不满足时序收敛条件的模块的情况下，确定目标模块；
    对所述目标模块进行逻辑综合处理，得到与所述目标模块的功能描述信息对应的第一综合结果；
    基于所述第一综合结果确定所述目标模块的实际延时时间；
    基于所述实际延时时间更新所述目标模块的当前延时约束，得到目标延时约束。
  2. 根据权利要求1所述的方法，其特征在于，所述基于所述实际延时时间更新所述目标模块的当前延时约束，得到目标延时约束，包括：
    获取所述多个模块之间的连接关系；
    基于所述连接关系在所述多个模块中确定与所述目标模块相连接的相邻模块；
    基于所述相邻模块的实际延时时间和所述目标模块的实际延时时间，更新所述目标模块的当前延时约束，得到所述目标延时约束。
  3. 根据权利要求2所述的方法，其特征在于，所述基于所述相邻模块的实际延时时间和所述目标模块的实际延时时间，更新所述目标模块的当前延时约束，得到所述目标延时约束，包括：
    基于所述相邻模块的实际延时时间和所述目标模块的实际延时时间，确定信号从所述相邻模块的第一级时序单元传输至所述目标模块的第一级时序单元的目标延时时间；
    基于所述目标延时时间更新所述目标模块的当前延时约束，得到所述目标延时约束。
  4. 根据权利要求3所述的方法，其特征在于，所述当前延时约束包含输入延时约束，所述相邻模块为与所述目标模块的输入边界端连接的模块；
    所述基于所述目标延时时间更新所述目标模块的当前延时约束，得到所述目标延时约束，包括：
    确定信号从所述相邻模块的所述第一级时序单元的输出端传输至所述相邻模块的输出边界端的延时时间，得到第一延时；
    确定所述第一延时在所述目标延时时间中的占比，得到第一占比；
    基于所述第一占比更新所述输入延时约束，得到所述目标延时约束中的输入延时约束。
  5. 根据权利要求3或4所述的方法，其特征在于，所述当前延时约束包含输出延时约束；所述相邻模块为与所述目标模块的输出边界端连接的模块；
    所述基于所述目标延时时间更新所述目标模块的当前延时约束，得到所述目标延时约束，还包括：
    确定信号从所述相邻模块的输入边界端传输至所述相邻模块的所述第一级时序单元的延时时间，得到第二延时；
    确定所述第二延时在所述目标延时时间中的占比，得到第二占比；
    基于所述第二占比更新所述输出延时约束，得到所述目标延时约束中的输出延时约 束。
  6. 根据权利要求1至5中任一项所述的方法，其特征在于，所述方法还包括：
    基于所述目标延时约束确定所述目标模块是否满足所述时序收敛条件；
    在基于所述目标延时约束确定所述目标模块满足所述时序收敛条件的情况下，基于所述目标延时约束对所述目标模块进行布局布线。
  7. 根据权利要求6所述的方法，其特征在于，基于所述目标延时约束确定所述目标模块满足所述时序收敛条件的方式，包括：
    基于所述目标延时约束对所述目标模块进行重新逻辑综合处理，得到与所述目标模块的功能描述信息对应的第二综合结果；
    基于所述第二综合结果，更新所述多个模块中任意两个相连接模块之间的时序路径的实际延时时间；所述时序路径为信号在所述两个相连接模块的第一级时序单元之间的传输路径；
    在确定每个时序路径的实际延时时间满足预设时钟要求的情况下，确定所述目标模块满足所述时序收敛条件。
  8. 根据权利要求7所述的方法，其特征在于，
    所述方法还包括：基于所述时序路径的所述实际延时时间，更新所述目标模块所对应时序路径的路径权重；
    所述基于所述目标延时约束对所述目标模块进行重新逻辑综合处理，得到与所述目标模块的功能描述信息对应的第二综合结果，包括：基于所述路径权重和所述目标延时约束对所述目标模块进行重新逻辑综合处理，得到所述第二综合结果。
  9. 根据权利要求1至5中任一项所述的方法，其特征在于，所述方法还包括：
    基于所述目标延时约束确定所述目标模块是否满足所述时序收敛条件；
    在基于所述目标延时约束确定所述目标模块不满足所述时序收敛条件的情况下，将所述目标延时约束确定为所述目标模块的当前延时约束，并重新确定新的目标模块、对所述新的目标模块进行新的逻辑综合处理、确定新的实际延时时间、以及得到新的目标延时约束，直至基于得到的所述新的目标延时约束确定所述新的目标模块满足所述时序收敛条件。
  10. 根据权利要求1至9中任一项所述的方法，其特征在于，所述在基于所述多个模块的当前延时约束确定存在不满足时序收敛条件的模块的情况下，确定目标模块，包括：
    确定所述多个模块为所述目标模块；或者
    确定所述多个模块中存在的不满足所述时序收敛条件的模块为所述目标模块。
  11. 一种集成电路的时序约束装置，其特征在于，包括：
    第一确定模块，用于在基于集成电路包含的多个模块的当前延时约束确定存在不满足时序收敛条件的模块的情况下，确定目标模块，并对所述目标模块进行逻辑综合处理，得到与所述目标模块的功能描述信息对应的第一综合结果；
    第二确定模块，用于基于所述第一综合结果确定所述目标模块的实际延时时间；
    更新模块，用于基于所述实际延时时间更新所述目标模块的当前延时约束，得到目标延时约束。
  12. 一种电子设备，其特征在于，包括：处理器、存储器和总线，所述存储器存储有所述处理器可执行的机器可读指令，当电子设备运行时，所述处理器与所述存储器之间通过总线通信，所述机器可读指令被所述处理器执行时执行如权利要求1至10任意一项所述的集成电路的时序约束方法的步骤。
  13. 一种芯片，其特征在于，所述芯片采用如权利要求1至10任意一项所述的集成电路的时序约束方法进行时序约束，并在基于所述目标延时约束确定所述目标模块满足时序收敛条件的情况下，基于所述目标延时约束对所述目标模块进行布局布线。
  14. 一种计算机可读存储介质，其特征在于，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器运行时执行如权利要求1至10任意一项所述的集成电路的时序约束方法的步骤。
PCT/CN2022/118057 2021-09-30 2022-09-09 集成电路的时序约束方法、装置、电子设备及芯片 WO2023051217A1 (zh)

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