WO2023071500A1 - 一种dma配置方法和配置电路 - Google Patents

一种dma配置方法和配置电路 Download PDF

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Publication number
WO2023071500A1
WO2023071500A1 PCT/CN2022/115901 CN2022115901W WO2023071500A1 WO 2023071500 A1 WO2023071500 A1 WO 2023071500A1 CN 2022115901 W CN2022115901 W CN 2022115901W WO 2023071500 A1 WO2023071500 A1 WO 2023071500A1
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dma
configuration
instruction
packet
module
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PCT/CN2022/115901
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English (en)
French (fr)
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潘卫星
王维伟
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北京希姆计算科技有限公司
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Publication of WO2023071500A1 publication Critical patent/WO2023071500A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of data access, in particular to a DMA configuration method and a configuration circuit.
  • the DMA (Direct Memory Access) module can transfer data between two different addresses, such as from memory to peripheral registers, or from peripheral registers to memory, or from memory to memory transfer.
  • the DMA module is usually configured by the core processor.
  • the processor due to the long physical distance between the DMA module and the core processor, it takes a long time for the processor to configure the DMA through software, which seriously affects the execution efficiency of the DMA.
  • a DMA configuration method including: storing the DMA configuration instruction packet in the instruction emission slot; wherein the DMA configuration instruction packet to be sent in the instruction emission slot is Target DMA configuration instruction package;
  • the target DMA configuration instruction packet being an instruction packet to be executed, start a state machine; based on the started state machine and configuration parameter data in the CSR register, configure the DMA module.
  • the target DMA configuring the instruction packet as an instruction packet to be executed in response to the target DMA configuring the instruction packet as an instruction packet to be executed, and before starting the state machine, it also includes:
  • the method in response to the received DMA configuration instruction being an instruction packet to be executed, and before determining that the target DMA configuration instruction packet has no address correlation, the method further includes: decoding the DMA configuration instruction, and determining the The first address range information of the DMA configuration command generates a DMA configuration command packet; the DMA configuration command packet includes the first address range information;
  • the step of determining that the target DMA configuration instruction packet has no address dependency includes:
  • the step of configuring the DMA module based on the started state machine and the configuration parameter data in the CSR register includes:
  • the configuration of the DMA module is performed based on the started state machine and the configuration parameter data in the CSR register; wherein, the configuration of the DMA module includes at least one of the following : Corresponding control register, source data address, destination data address, transmission data type.
  • the DMA module after performing the configuration of the DMA module, it also includes:
  • a DMA configuration circuit including an instruction transmission slot and a DMA control module, the DMA control module including a data selector, a CSR register and a state machine control unit;
  • the instruction emission slot is configured to store a DMA configuration instruction packet; wherein the DMA configuration instruction packet to be sent in the instruction emission slot is a target DMA configuration instruction packet;
  • the data selector is configured to send the CSR register configuration packet to the CSR register in response to the target DMA configuration instruction packet being a CSR register configuration packet, so that the CSR register is configured according to the CSR register Package update configuration parameter data;
  • the state machine control unit is configured to start a state machine in response to the target DMA configuration instruction packet as an instruction packet to be executed; based on the state machine started and the configuration parameter data in the CSR register, perform DMA module Configuration.
  • an address dependency detection module is further included, configured to determine that the target DMA configuration instruction packet has no address dependency in response to the target DMA configuration instruction packet being an instruction packet to be executed.
  • it also includes a decoding module configured to decode the DMA configuration instruction and determine the first address range information of the DMA configuration instruction in response to the received DMA configuration instruction being an instruction packet to be executed , generating a DMA configuration instruction packet; the DMA configuration instruction packet includes the first address range information;
  • the address dependency detection module is also configured to obtain status information of the currently executing instruction, where the status information includes the second address range information of the executing instruction; and obtain the first address of the target DMA configuration instruction packet address range information, determining that the first address range information does not overlap with the second address range information.
  • the DMA control module further includes a bus port driver module, and the state machine control unit is also configured to read the channel information of the DMA module based on the state machine started; and respond to the DMA module The channel information is not occupied, and the configuration parameter data in the CSR register is sent to the DMA module through the bus port driver module, so that the DMA module performs configuration; wherein, the configuration of the DMA module includes at least one of the following: corresponding Control register, source data address, destination data address, transfer data type.
  • a chip including the DMA configuration circuit described in the above embodiments.
  • a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the DMA configuration method described in the above-mentioned embodiments is implemented.
  • a computer device including a memory, a processor, and a computer program stored on the memory and operable on the processor.
  • the processor executes the program, the above-mentioned The DMA configuration method described in the embodiment.
  • the read and write register commands and data are sent to the DMA module to realize the configuration of the DMA module, which solves the long configuration delay caused by the long distance between the NP processor and the DMA module, and the efficiency
  • the low problem improves the efficiency of data handling.
  • Fig. 1 is a flowchart of a DMA configuration method shown according to an exemplary embodiment
  • Fig. 2 is a schematic structural diagram showing a DMA configuration circuit according to an exemplary embodiment
  • Fig. 3 is a schematic structural diagram showing a DMA control module according to an exemplary embodiment
  • Fig. 4 is a processing logic block diagram showing a DMA configuration circuit according to an exemplary embodiment
  • Fig. 5 is a processing logic block diagram showing a DMA control module according to an exemplary embodiment
  • Fig. 6 is a block diagram illustrating processing logic of a DMA state machine according to an exemplary embodiment.
  • the embodiment of this application provides a DMA configuration method, including:
  • the DMA configuration instruction package includes two types, namely a CSR register configuration package and a pending instruction package, and the CSR register configuration package is used to instruct to update the configuration parameter data in the CSR register.
  • the to-be-executed instruction packet is used to instruct the configuration of the DMA module.
  • a DMA module needs two DMA configuration instruction packets to complete the configuration, that is, a DMA configuration instruction packet of the CSR register configuration packet type, and a DMA configuration instruction packet of the to-be-executed instruction packet type.
  • a DMA configuration instruction packet of the CSR register configuration packet type is sent to the emission slot first, and then the DMA configuration instruction packet of the instruction packet type to be executed is sent to the emission slot.
  • the DMA configuration instruction packet of the CSR register configuration packet type can be sent first to update the CSR register data, and then the instruction to be executed
  • the DMA configuration instruction packet of packet type is issued to perform the configuration of the DMA module according to the data in the CSR register.
  • the DMA configuration instruction packet includes data related to the configuration of the DMA module, and multiple DMA configuration instruction packets can be stored in the instruction emission slot. Multiple DMA configuration command packets can be sequentially sent to the corresponding DMA modules for configuration. Furthermore, the DMA configuration instruction packet can be directly received and processed through the configured hardware environment, so as to realize the rapid configuration of the DMA module, and solve the problem that the processor takes a long time to configure the DMA module through software. Further, multiple command emission slots can be set to store more DMA configuration command packets, which improves the configuration efficiency of the DMA module.
  • the DMA configuration instruction before storing the DMA configuration instruction package into the instruction emission slot, it also includes: performing abnormal judgment on the decoded DMA configuration instruction to determine whether the DMA configuration instruction is executable; wherein, the judgment includes the DMA configuration instruction Encoding abnormality judgment, and/or first address range abnormality judgment; wherein, if it is judged that there is an abnormality, it means that the instruction cannot be executed, and abnormal processing is performed.
  • the encoding abnormality includes encoding format abnormality, encoding syntax abnormality, etc.
  • the first address range abnormality includes its read address exceeding the range, or its writing address exceeding the range, and the like. If there is no abnormality, the decoding result of the DMA configuration instruction is packaged into a DMA configuration instruction packet, and sent to the instruction emission slot.
  • the process of configuring the DMA module is controlled according to the target DMA configuration command package, and in response to the target DMA configuration command package being a CSR register configuration package, the DMA configuration command package of the CSR register configuration package type is sent to the corresponding register , to make the register update the configuration parameter data according to the DMA configuration instruction packet of the CSR register configuration packet type; respond to the target DMA configuration instruction packet as the instruction packet to be executed, start the state machine; based on the state machine started and the configuration parameters stored in the CSR register data, read the channel information of the DMA module, and configure the DMA module in response to the fact that the channel information of the DMA module is not occupied.
  • the DMA module can be configured.
  • the configuration of the DMA module includes at least one of the following: a corresponding control register, a source data address, a destination data address, and a transfer data type. That is, in the process of configuring the DMA module, configure the corresponding control register, or configure the source data address, or configure the destination data address, or configure the transmission data type.
  • the control register is used to control operations such as starting and ending of the DMA module.
  • the DMA module starts the state machine and generates read and write DMA register commands and data, and reads the occupancy information corresponding to the DMA channel information based on the started state machine , to determine whether the channel is idle, if it is idle, the read and write DMA register command and data will be sent to the remote DMA module through the bus, and the configuration will be performed in the order of hardware configuration.
  • the execution sequence is configured through hardware, the configuration sequence is fixed during execution, but the hardware configuration sequence can be adjusted.
  • the above configuration includes configuring the control register, configuring the data type of the DMA transfer, configuring the shape of the DMA transfer, configuring the source address and the destination address of the DMA transfer, so as to enable the channel of the DMA module to execute data transport.
  • the target DMA configuration instruction packet in response to the target DMA configuration instruction packet being a pending instruction packet, and prior to starting the state machine, it is determined that the target DMA configuration instruction packet has no address dependency. Since the configuration process of the DMA module may be related to other operations, for example, the write operation being performed in the CSR register will affect the data read in the CSR register during the configuration process of the DMA module, so the type of instruction package to be executed needs to be correlated Detection, the CSR register configuration package does not need to perform dependency detection.
  • the DMA configuration instruction Decoding is performed, and the first address range information of the DMA configuration instruction is determined to generate a DMA configuration instruction packet; the DMA configuration instruction packet includes the first address range information.
  • the first address range information includes first read address range information and/or first write address range information of the DMA configuration instruction.
  • the state information of the instruction currently being executed is obtained, and the state information includes the second address range information of the instruction being executed.
  • the type of the instruction being executed may be an instruction packet to be executed, or a CSR register configuration packet.
  • the second address range information includes second read address range information and/or second write address range information of the instruction being executed.
  • the first address range information of the target DMA configuration instruction packet is acquired, and it is determined that the first address range information does not overlap with the second address range information.
  • the overlapping includes address crossing and address duplication.
  • the overlapping of the first address range information and the second address range information includes: the first read address range information overlaps with the second write address range information (that is, the read and write addresses overlap), and the first write address range information overlaps with the second read address range information (that is, the write and read addresses overlap), and the first write address range information overlaps with the second write address range information (that is, the write and write addresses overlap).
  • the detection of the address correlation of the target DMA configuration instruction packet is performed by performing address dependency detection on the DMA configuration instruction packet of the type of instruction packet to be executed at the top of the instruction emission slot and the instruction being executed.
  • the execution information of the instructions being executed or executed will be uniformly stored in a module, and the status information of the instructions being executed can be obtained through this module to determine whether the first DMA configuration instruction packet in the instruction emission slot is the same as the one being executed. address dependencies between instructions. Among them, if there is an overlap or intersection between the address of reading and writing, reading and writing, and writing and writing between the DMA configuration instruction packet of the instruction packet type to be executed and the instruction being executed, it is considered to be related.
  • the number of specific instructions being executed can be one or more. If it is determined that there is a dependency, wait for the execution of all the instructions being executed that have dependencies to be completed, so as to release the address between the DMA configuration instruction packet of the instruction packet type to be executed at the top of the instruction emission slot and the instruction being executed Dependence, and then send the DMA configuration instruction packet to the downstream, so as to configure the DMA module according to the DMA configuration instruction packet. On the contrary, if there is no address correlation between the frontmost DMA configuration instruction packet in the instruction emission slot and the instruction being executed, the instruction emission slot directly sends the DMA configuration instruction packet downstream.
  • the method further includes receiving DMA configuration feedback information.
  • the feedback information includes control register configuration, data type configuration of DMA transfer, shape configuration of DMA transfer, source address configuration of DMA transfer, feedback information of destination address configuration success or configuration failure, and the feedback information is transmitted through the bus.
  • multiple DMA modules can be configured simultaneously. And a plurality of command emission slots can be set to store more DMA configuration command packets, so that more operations of DMA module configuration can be performed at the same time, and the configuration efficiency can be further improved.
  • a DMA configuration circuit including an instruction issue slot and a DMA control module, where the DMA control module includes a data selector, a CSR register, and a state machine control unit.
  • the instruction sending slot is configured to store a DMA configuration instruction packet; the DMA configuration instruction packet to be sent in the instruction sending slot is a target DMA configuration instruction packet.
  • the data selector is configured to send the CSR register configuration packet to the CSR register in response to the target DMA configuration instruction packet being a CSR register configuration packet, so that the CSR register updates configuration parameter data according to the CSR register configuration packet.
  • the state machine control unit is configured to start the state machine in response to the target DMA configuration instruction packet as the instruction packet to be executed; configure the DMA module based on the started state machine and the configuration parameter data in the CSR register.
  • the NP (Network Processor, network processor) processor includes at least one NP core, and all NP cores are connected with the DMA module of the SOC (System on Chip, SOC) system through the bus NOC, and the DMA configuration circuit is set on the NP core.
  • the main control processor of the DMA configuration circuit in the NP core receives the DMA configuration instruction, the DMA configuration instruction is used for the configuration of the DMA module, the instruction emission slot can store the DMA configuration instruction packet, and the DMA control module can communicate with the remote DMA through the bus
  • the modules are connected, and then according to the DMA configuration command packet, the configuration of the DMA module is realized.
  • the DMA configuration circuit further includes an address dependency detection module configured to determine that the target DMA configuration instruction packet has no address dependency in response to the target DMA configuration instruction packet being an instruction packet to be executed.
  • the DMA configuration circuit further includes a decoding module.
  • the decoding module is configured to respond to the received DMA configuration instruction as an instruction packet to be executed, decode the DMA configuration instruction, determine the first address range information of the DMA configuration instruction, and generate a DMA configuration instruction packet; in the DMA configuration instruction packet Information about the first address range is included.
  • the address dependency detection module is also configured to acquire the state information of the instruction currently being executed, the state information includes the second address range information of the instruction being executed; and acquire the first address range information of the target DMA configuration instruction packet, and determine the second address range information of the instruction packet being executed. The first address range information does not overlap with the second address range information.
  • the DMA configuration circuit further includes a master processor.
  • the main control processor is configured to send the received DMA configuration instruction of the instruction packet type to be executed to the decoding module through the ACE interface. Since the DMA configuration command is a custom address mapping command, it needs to be transmitted through a specific interface.
  • the ACE interface is a coprocessor interface for receiving the self-defined instruction.
  • the DMA control module includes: an instruction packet receiving unit, a data selector, a CSR register, a state machine control unit, and a bus port driver module; wherein, the instruction packet receiving unit is configured to receive a target DMA configuration instruction packet; data selection The device is configured to determine whether the target DMA configuration instruction packet is a CSR register configuration packet according to the parsing result of the instruction packet receiving unit; and send the DMA configuration instruction packet of the determined CSR register configuration packet type to the CSR register, and send the instruction to be executed
  • the DMA configuration instruction packet (non-CSR register configuration packet) of the packet type is sent to the state machine control unit; the CSR register is configured to update the configuration parameter data according to the DMA configuration instruction packet of the CSR register configuration packet type; the state machine control unit is configured to The DMA configuration instruction packet of the instruction packet type to be executed starts the state machine; the bus port driver module is configured to send the configuration parameter data to the DMA module through the bus according to the control of the state machine control unit, so that the started
  • the DMA control module further includes an abnormal judgment unit.
  • the abnormality judging unit is configured to receive the decoding result of the decoding module to judge whether the DMA configuration instruction is abnormal, and the decoding module sends the DMA configuration instruction packet to the instruction emission slot in response to the non-abnormal DMA configuration instruction.
  • the abnormal judgment unit performs abnormal judgment on the decoded DMA configuration instruction to judge whether the DMA configuration instruction is executable; wherein, the judgment includes an abnormal judgment on the encoding of the DMA configuration instruction, and/or an abnormal judgment on the first address range; Wherein, if it is judged that there is an abnormality, the exception processing is performed; if there is no abnormality, the decoding result of the DMA configuration instruction is packaged into a DMA configuration instruction packet, and sent to the instruction emission slot.
  • the abnormal judgment includes encoding abnormal judgment, and/or abnormal judgment of the read/write address range in the instruction. Since the DMA configuration instruction of the CSR register configuration package type also involves reading or writing data, the read-write address in this instruction refers to the address of the read-write operation in the DMA configuration instruction of the CSR register configuration package type. If the abnormality judging unit determines that the DMA configuration instruction of the CSR register configuration package type has no abnormality, it can directly package the DMA configuration instruction to obtain a DMA configuration instruction package of the CSR register configuration package type.
  • the DMA module of the SOC system is connected to the DMA control module of the NP core.
  • the NP core includes a DMA control module, an address correlation detection module, an instruction emission slot, a decoding module and a main control processor.
  • the DMA module is connected to the DMA control module of the NP core through the NOC bus.
  • the address dependency detection module is connected with the instruction emission slot.
  • the command launch slots are respectively connected with the DMA control module and the decoding module.
  • the decoding module is connected with the main control processor and the DMA control module, wherein the main control processor can send DMA configuration instructions to the decoding module through the ACE (Adaptive Communication Environment) interface.
  • ACE Adaptive Communication Environment
  • an instruction emission slot is set in the NP core for independently storing DMA configuration instruction packets, which can reduce the impact on the performance of the NP processor during the configuration process and improve configuration efficiency.
  • multiple DMA modules can be configured at the same time, and the feedback of configuration completion of multiple DMA modules can be received at the same time.
  • there are 4 DMA configuration instruction packets stored in the instruction emission slot including 2 CSR register configuration packets and 2 to-be-executed instruction packets, namely CSR register configuration packet A, to-be-executed instruction packet A and CSR register configuration packet B
  • the instruction package B to be executed is sequentially stored in the instruction emission slot, wherein, the CSR register configuration package A and the instruction package A to be executed are used to configure the DMA module A, and the CSR register configuration package B and the instruction package B to be executed are used to configure the DMA Module B is configured.
  • the CSR register configuration package A is sent to the DMA control module in the instruction emission slot, wherein, after the command package receiving unit of the DMA control module receives the CSR register configuration package A, the CSR register configuration package A is transmitted to the data selector, and the data selection If the device determines that the received instruction packet is a CSR register configuration packet, it sends the CSR register configuration packet A to the CSR register, so that the CSR register updates the configuration parameter data corresponding to the DMA module A according to the CSR register configuration packet A.
  • the address correlation of the command package A to be executed is detected by the address correlation detection module, and after no address correlation is determined, the command launch slot sends the command package A to be executed to the DMA control module , wherein, after the instruction packet receiving unit of the DMA control module receives the instruction packet A to be executed, it transmits the instruction packet A to be executed to the data selector, and the data selector judges that the received instruction packet is the instruction packet to be executed, and then the instruction packet to be executed is The instruction packet A is sent to the state machine control unit.
  • the state machine control unit starts the state machine according to the instruction package A to be executed, and determines that the channel of the DMA module A is not occupied based on the state machine of the start, then the bus port driver module passes the configuration parameter data of the DMA module A stored in the CSR register through The bus NOC will send to the remote DMA module A, and then execute the configuration of DMA module A. After the configuration of DMA module A is completed, the feedback information can be sent to the DMA control module through the bus NOC.
  • the CSR register configuration package B is sent to the DMA control module in the command launch slot, wherein, after the command package receiving unit of the DMA control module receives the CSR register configuration package B, the CSR register configuration package B is sent to the DMA control module.
  • the packet B is transmitted to the data selector, and the data selector judges that the received instruction packet is a CSR register configuration packet, and then sends the CSR register configuration packet B to the CSR register, so that the CSR register updates the corresponding DMA module B according to the CSR register configuration packet B.
  • Configuration parameter data is transmitted to the data selector, and the data selector judges that the received instruction packet is a CSR register configuration packet, and then sends the CSR register configuration packet B to the CSR register, so that the CSR register updates the corresponding DMA module B according to the CSR register configuration packet B.
  • the address correlation of the command package B to be executed is detected by the address correlation detection module, and after no address correlation is determined, the command launch slot sends the command package B to be executed to the DMA control module , wherein, after the instruction packet receiving unit of the DMA control module receives the instruction packet B to be executed, it transmits the instruction packet B to be executed to the data selector, and the data selector judges that the received instruction packet is the instruction packet to be executed, and then the instruction packet to be executed is The instruction packet B is sent to the state machine control unit.
  • the state machine control unit starts the state machine according to the instruction package B to be executed, and determines that the channel of the DMA module B is not occupied based on the state machine of the start, then the bus port driver module passes the configuration parameter data of the DMA module B stored in the CSR register through The bus NOC will be sent to the remote DMA module B, and then the configuration of DMA module B will be executed. After the configuration of DMA module B is completed, the feedback information can be sent to the DMA control module through the bus NOC.
  • DMA module A and DMA module B do not affect each other and can be configured at the same time, and after the configuration is completed, it can be reported that it has been completed, thereby realizing the simultaneous configuration of multiple DMA modules and improving configuration efficiency.
  • the processing logic of the DMA configuration circuit includes: S201.
  • the main control processor receives the DMA configuration instruction;
  • the main control processor sends the DMA configuration instruction to the decoding module through the ACE interface;
  • the decoding module is configured to decode the DMA configuration instruction in response to the received DMA configuration instruction as an instruction packet to be executed, determine the first address range information of the DMA configuration instruction, and generate a DMA configuration instruction packet; DMA configuration instruction The packet includes first address range information;
  • the DMA configuration instruction packet is stored in the instruction emission slot; the DMA configuration instruction packet to be sent in the instruction emission slot is the target DMA configuration instruction packet;
  • the address dependency detection module is configured to determine that the target DMA configuration instruction packet has no address dependency in response to the target DMA configuration instruction packet being an instruction packet to be executed;
  • the DMA control module is configured to receive and analyze the target DMA configuration instruction packet; according to the analysis result, determine whether the target DMA configuration instruction packet is a CSR register configuration packet;
  • the DMA configuration instruction packet of the determined CSR register configuration packet type is sent to the CSR register to update the configuration parameter data
  • the DMA configuration instruction packet (non-CSR register configuration packet) of the instruction packet type to be executed is sent to the state machine control unit , start the state machine
  • the CSR register is configured to update the configuration parameter data according to the DMA configuration instruction packet of the CSR register configuration packet type
  • the state machine control unit is configured to start the state machine according to the DMA configuration instruction packet of the instruction packet type to be executed
  • the remote DMA module configures the DMA module according to the configuration parameter data.
  • the configuration parameter data is the configuration parameter data corresponding to the DMA module updated in the CSR register.
  • the DMA control module detects that the transmission of the DMA module of the remote SOC is completed, and ends the configuration of the DMA module.
  • the DMA control module includes an instruction packet receiving unit, a data selector, a CSR register, a state machine control unit, a bus port driver module and an abnormal judgment unit, and the abnormal judgment unit is connected with the main control processor and the decoding module respectively.
  • the instruction packet receiving unit is respectively connected with the data selector and the instruction sending slot.
  • the data selector is connected with the CSR register and the state machine control unit respectively.
  • the state machine control unit is connected with the bus port driver module.
  • the processing logic of the DMA control module includes:
  • the instruction packet receiving unit parses after receiving the target DMA configuration instruction packet, and determines the CSR register configuration packet and the instruction packet to be executed;
  • the data selector is configured to respond to the target DMA configuration instruction package as the CSR register configuration package, and send the CSR register configuration package to the CSR register, so that the CSR register updates the configuration parameter data according to the CSR register configuration package; the state machine control unit according to The instruction packet to be executed starts the state machine;
  • the DMA control module waits for the completion of the transmission of the DMA module of the remote SOC
  • the DMA control module returns to the idle state according to the transmission completion information.
  • the processing logic of the state machine includes:
  • DMA configuration feedback information includes control register configuration, DMA transfer data type configuration, DMA transfer shape configuration, DMA transfer source address configuration, and destination address configuration Feedback information on success or configuration failure;
  • the read and write register commands and data are sent to the DMA module to realize the configuration of the DMA module, which solves the long configuration delay caused by the long distance between the NP processor and the DMA module, and the efficiency
  • the low problem improves the efficiency of data handling.
  • a chip including the DMA configuration circuit described in the above embodiments.
  • a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the DMA configuration method described in the above-mentioned embodiments is implemented.
  • a computer device including a memory, a processor, and a computer program stored on the memory and operable on the processor.
  • the processor executes the program, the above-mentioned The DMA configuration method described in the embodiment.

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Abstract

本申请提供了一种DMA配置方法和配置电路，方法包括：将DMA配置指令包存储至指令发射槽；其中指令发射槽中待发送的DMA配置指令包为目标DMA配置指令包；响应于所述目标DMA配置指令包为CSR寄存器配置包，将所述CSR寄存器配置包发送至CSR寄存器，以使所述CSR寄存器根据所述CSR寄存器配置包更新配置参数数据；响应于所述目标DMA配置指令包为待执行指令包，启动状态机；基于启动的所述状态机以及所述CSR寄存器中的配置参数数据，进行DMA模块的配置。本申请实施例中，基于状态机的配置，将读写寄存器命令和数据发送至处理器的DMA模块，用于处理器内的控制寄存器（CSR）的配置，解决了NP处理器与处理器间因距离远，导致的延时长，效率低的问题，提升数据搬运的效率。

Description

一种DMA配置方法和配置电路
本申请要求了2021年10月26日提交的、申请号为202111248565.8、发明名称为“一种DMA配置方法和配置电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据访问技术领域，特别涉及一种DMA配置方法和配置电路。
背景技术
多核系统中，DMA(Direct Memory Access，直接存储器访问)模块可以将数据在两个不同的地址之间进行传递，如从存储器到外设寄存器，或外设寄存器到存储器传递，也可以从存储器到存储器进行传递。现有方案中，DMA模块通常由核内处理器配置。但是，由于DMA模块和核内处理器的物理距离远，导致处理器通过软件的方式配置DMA的耗时长，这样就严重影响DMA的执行效率。
因此，如何解决上述问题，成为本领域技术人员亟待解决的问题。
发明内容
为解决上述问题，根据本申请实施例的第一个方面,提供了一种DMA配置方法，包括：将DMA配置指令包存储至指令发射槽；其中指令发射槽中待发送的DMA配置指令包为目标DMA配置指令包；
响应于所述目标DMA配置指令包为CSR寄存器配置包，将所述CSR寄存器配置包发送至CSR寄存器，以使所述CSR寄存器根据所述CSR寄存器配置包更新配置参数数据；
响应于所述目标DMA配置指令包为待执行指令包，启动状态机；基于启动的所述状态机以及所述CSR寄存器中的配置参数数据，进行DMA模块的配置。
一些实施例中，响应于所述目标DMA配置指令包为待执行指令包，以及在所述启动状态机之前，还包括：
确定所述目标DMA配置指令包无地址相关性。
一些实施例中，响应于接收的DMA配置指令为待执行指令包，以及在确定所述目 标DMA配置指令包无地址相关性之前，还包括：对所述DMA配置指令进行译码，并确定所述DMA配置指令的第一地址范围信息，生成DMA配置指令包；所述DMA配置指令包中包括所述第一地址范围信息；
确定所述目标DMA配置指令包无地址相关性的步骤，包括：
获取当前正在执行的指令的状态信息，所述状态信息包括所述正在执行的指令的第二地址范围信息；
获取所述目标DMA配置指令包的第一地址范围信息，确定所述第一地址范围信息与所述第二地址范围信息无重叠。
一些实施例中，基于启动的所述状态机以及所述CSR寄存器中的配置参数数据，进行DMA模块的配置的步骤，包括：
基于启动的所述状态机，读取DMA模块的通道信息；
响应于所述DMA模块的通道信息没有被占用，基于启动的所述状态机以及所述CSR寄存器中的配置参数数据，进行DMA模块的配置；其中，所述DMA模块的配置至少包括以下一种：对应的控制寄存器，源数据地址，目的数据地址，传输数据类型。
一些实施例中，在进行DMA模块的配置之后，还包括：
接收DMA配置的反馈信息。
根据本申请实施例的第二个方面,提供了一种DMA配置电路，包括指令发射槽和DMA控制模块，所述DMA控制模块包括数据选择器、CSR寄存器和状态机控制单元；其中
所述指令发射槽，被配置为存储DMA配置指令包；其中指令发射槽中待发送的DMA配置指令包为目标DMA配置指令包；
所述数据选择器，被配置为响应于所述目标DMA配置指令包为CSR寄存器配置包，将所述CSR寄存器配置包发送至所述CSR寄存器，以使所述CSR寄存器根据所述CSR寄存器配置包更新配置参数数据；
所述状态机控制单元，被配置为响应于所述目标DMA配置指令包为待执行指令包，启动状态机；基于启动的所述状态机以及所述CSR寄存器中的配置参数数据，进行DMA模块的配置。
一些实施例中，还包括地址相关性检测模块，被配置为响应于所述目标DMA配置指令包为待执行指令包，确定所述目标DMA配置指令包无地址相关性。
一些实施例中，还包括译码模块，被配置为响应于接收的DMA配置指令为待执行 指令包，对所述DMA配置指令进行译码，并确定所述DMA配置指令的第一地址范围信息，生成DMA配置指令包；所述DMA配置指令包中包括所述第一地址范围信息；
地址相关性检测模块，还被配置为获取当前正在执行的指令的状态信息，所述状态信息包括所述正在执行的指令的第二地址范围信息；以及获取所述目标DMA配置指令包的第一地址范围信息，确定所述第一地址范围信息与所述第二地址范围信息无重叠。
一些实施例中，DMA控制模块还包括总线端口驱动模块，所述状态机控制单元，还被配置为基于启动的所述状态机，读取DMA模块的通道信息；以及响应于所述DMA模块的通道信息没有被占用，通过所述总线端口驱动模块将CSR寄存器中的配置参数数据发送至DMA模块，以使所述DMA模块执行配置；其中，所述DMA模块的配置至少包括以下一种：对应的控制寄存器，源数据地址，目的数据地址，传输数据类型。
根据本申请实施例的第三个方面,提供了一种芯片，包括上述实施例所述的DMA配置电路。
根据本申请实施例的第四个方面,提供了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现上述实施例所述的DMA配置方法。
根据本申请实施例的第五个方面,提供了一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现上述实施例所述的DMA配置方法。
本申请的上述技术方案具有如下有益的技术效果：
本申请实施例中，基于状态机的配置，将读写寄存器命令和数据发送至DMA模块，实现DMA模块的配置，解决了NP处理器与DMA模块间因距离远导致的配置延时长，效率低的问题，提升了数据搬运的效率。
附图说明
图1是根据一示例性实施例示出的DMA配置方法的流程图；
图2是根据一示例性实施例示出DMA配置电路的结构示意图；
图3是根据一示例性实施例示出DMA控制模块的结构示意图；
图4是根据一示例性实施例示出DMA配置电路的处理逻辑框图；
图5是根据一示例性实施例示出DMA控制模块的处理逻辑框图；
图6是根据一示例性实施例示出DMA状态机的处理逻辑框图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中使用的术语“和/或”包括相关所列项目的任何及所有组合。
如图1所示，本申请实施例提供了一种DMA配置方法，包括：
S101、将DMA配置指令包存储至指令发射槽；其中指令发射槽中待发送的DMA配置指令包为目标DMA配置指令包；待发送的DMA配置指令包即为指令发射槽中最前面的DMA配置指令包。
S103、响应于目标DMA配置指令包为CSR寄存器配置包，将CSR寄存器配置包发送至CSR寄存器，以使CSR寄存器根据CSR寄存器配置包更新配置参数数据；其中，CSR(Control and Status Register)寄存器中存储有DMA模块的配置参数数据，该配置参数包括源地址、目的地址、数据类型、数据长度、传输形状(shape)、步长(stride)或者DMA模块的通道信息等，可根据该配置参数数据对DMA模块进行配置。以及，DMA配置指令包包括两种类型，分别为CSR寄存器配置包和待执行指令包，CSR寄存器配置包用于指示对CSR寄存器中的配置参数数据进行更新。待执行指令包用于指示对DMA模块执行配置。
S105、响应于目标DMA配置指令包为待执行指令包，启动状态机；基于启动的状态机以及CSR寄存器中的配置参数数据，进行DMA模块的配置。
一般一个DMA模块完成配置，需要两个DMA配置指令包，即一个CSR寄存器配置 包类型的DMA配置指令包，和一个待执行指令包类型的DMA配置指令包。可选的，向指令发射槽发送DMA配置指令包时，一般会先将CSR寄存器配置包类型的DMA配置指令包发送至发射槽，然后再将待执行指令包类型的DMA配置指令包发送至发射槽，以便在根据指令发射槽中存储的多个DMA配置指令包进行DMA模块配置时，可先将CSR寄存器配置包类型的DMA配置指令包发出以进行CSR寄存器数据更新，然后再将待执行指令包类型的DMA配置指令包发出，以根据CSR寄存器中的数据执行DMA模块的配置。
其中，DMA配置指令包中包括DMA模块配置相关的数据，且指令发射槽中可存储多个DMA配置指令包，在该多个待执行指令包类型的DMA配置指令包无地址相关性情况下，可依次将多个DMA配置指令包发送至对应的DMA模块进行配置。进而，可通过配置的硬件环境直接接收并处理该DMA配置指令包，以实现DMA模块的快速配置，解决了处理器通过软件配置DMA模块耗时长的问题。进一步，可设置多个指令发射槽，进而存储更多的DMA配置指令包，提高了DMA模块的配置效率。
一些实施例中，将DMA配置指令包存储至指令发射槽之前，还包括：将译码处理后的DMA配置指令进行异常判断，以判断DMA配置指令是否可执行；其中，判断包括对DMA配置指令编码异常判断，和/或第一地址范围异常判断；其中，若判断出有异常，说明指令不可执行，则进行异常处理。示例性的，编码异常包括编码格式异常、编码语法异常等，第一地址范围异常包括其读地址超范围、或者其写地址超范围等。若无异常，则将该DMA配置指令的译码结果打包为DMA配置指令包，且发送至指令发射槽。
一些实施例中，根据目标DMA配置指令包控制进行DMA模块的配置的过程，响应于目标DMA配置指令包为CSR寄存器配置包，则将CSR寄存器配置包类型的DMA配置指令包发送至对应的寄存器，以使寄存器根据CSR寄存器配置包类型的DMA配置指令包更新配置参数数据；响应于目标DMA配置指令包为待执行指令包，启动状态机；基于启动的状态机以及CSR寄存器中存储的配置参数数据，读取DMA模块的通道信息，响应于DMA模块的通道信息没有被占用，进行DMA模块的配置。在该DMA模块具有多个通道的情况下，确定该DMA模块具有空闲通道的情况下，即可进行DMA模块的配置。其中，DMA模块的配置至少包括以下一种：对应的控制寄存器，源数据地址，目的数据地址，传输数据类型。即在DMA模块的配置的过程中，进行对应的控制寄存器配置，或者进行源数据地址配置，或者进行目的数据地址配置，或者进行传输数据类型的配 置。其中，该控制寄存器用于控制DMA模块的启动、结束等操作。
具体地，如果判断出解析后的DMA配置指令包不是CSR寄存器配置包，则DMA模块启动状态机并且产生读写DMA寄存器命令和数据，基于启动的状态机，读取对应DMA通道信息的占用信息，判断通道是否空闲，若空闲的话，则将通过总线将该读写DMA寄存器命令和数据发送一并给远程的DMA模块，按照硬件配置的顺序进行配置。其中，因为通过硬件配置了执行顺序，所以执行过程中配置顺序是固定的，但该硬件配置的顺序是可以调整的。进一步，上述的配置包括对控制寄存器进行配置、DMA传输的数据类型进行配置、DMA传输的形状进行配置、DMA传输的源地址、目的地址进行配置，以向DMA模块的通道进行使能以执行数据搬运。
一些实施例中，响应于目标DMA配置指令包为待执行指令包，以及在启动状态机之前，确定目标DMA配置指令包无地址相关性。由于DMA模块执行配置过程中，与其他操作可能有关联，例如CSR寄存器中正在执行的写操作会影响DMA模块执行配置过程中在CSR寄存器进行数据读取，所以需要对待执行指令包类型进行相关性检测，CSR寄存器配置包无需进行相关性检测。
一些实施例中，响应于接收的DMA配置指令为待执行指令包，即接收的DMA配置指令的类型为待执行指令包，则在确定目标DMA配置指令包无地址相关性之前，对DMA配置指令进行译码，并确定DMA配置指令的第一地址范围信息，生成DMA配置指令包；DMA配置指令包中包括第一地址范围信息。第一地址范围信息包括DMA配置指令的第一读地址范围信息和/或第一写地址范围信息。
在确定待执行指令包类型的目标DMA配置指令包无地址相关性的过程中，获取当前正在执行的指令的状态信息，状态信息包括正在执行的指令的第二地址范围信息。其中，正在执行的指令的类型可以是待执行指令包，也可以是CSR寄存器配置包。该第二地址范围信息包括正在执行的指令的第二读地址范围信息和/或第二写地址范围信息。以及，获取目标DMA配置指令包的第一地址范围信息，确定第一地址范围信息与第二地址范围信息无重叠。其中，该重叠包括地址交叉、地址重复的情况。第一地址范围信息与第二地址范围信息重叠包括：第一读地址范围信息与第二写地址范围信息重叠(即读写地址重叠)，第一写地址范围信息与第二读地址范围信息重叠(即写读地址重叠)，第一写地址范围信息与第二写地址范围信息重叠(即写写地址重叠)。
可以理解的是，检测目标DMA配置指令包的地址相关性，是通过对指令发射槽中最前面的待执行指令包类型的DMA配置指令包与正在执行的指令进行地址相关性检测。 具体地，正在执行或已经执行完的指令的执行信息会统一存储到一个模块，通过该模块获取正在执行的指令的状态信息，以判断该指令发射槽中最前面的DMA配置指令包与正在执行的指令间的地址相关性。其中，该指令发射槽中最前面的待执行指令包类型的DMA配置指令包与正在执行的指令间如果存在读写、写读和写写地址重叠或交叉，则认为具有相关性，该具有相关性的正在执行的指令的数量可以是一个，也可以是多个。如果判断出有相关性的话，则等待具有相关性的正在执行的所有指令执行完成，以解除该指令发射槽中最前面的待执行指令包类型的DMA配置指令包和正在执行的指令间的地址相关性，然后将该DMA配置指令包发送至下游，以根据该DMA配置指令包进行DMA模块的配置。反之，若该指令发射槽中最前面的DMA配置指令包与正在执行的指令间无地址相关性，则指令发射槽直接将该DMA配置指令包发送至下游。
一些实施例中，根据目标DMA配置指令包控制进行DMA配置之后，还包括，接收DMA配置的反馈信息。其中，反馈信息包括控制寄存器配置、DMA传输的数据类型配置、DMA传输的形状配置、DMA传输的源地址配置、目的地址配置成功或配置失败的反馈信息，且反馈信息都是通过总线传输。
一些实施例中，可以同时对多个DMA模块进行配置。以及可设置多个指令发射槽，以用于存储更多的DMA配置指令包，使得同时进行DMA模块配置的操作更多，进一步提升了配置效率。
根据本申请实施例的第二个方面,提供了一种DMA配置电路，包括指令发射槽和DMA控制模块，DMA控制模块包括数据选择器、CSR寄存器和状态机控制单元。指令发射槽，被配置为存储DMA配置指令包；其中指令发射槽中待发送的DMA配置指令包为目标DMA配置指令包。数据选择器，被配置为响应于目标DMA配置指令包为CSR寄存器配置包，将CSR寄存器配置包发送至CSR寄存器，以使CSR寄存器根据CSR寄存器配置包更新配置参数数据。状态机控制单元，被配置为响应于目标DMA配置指令包为待执行指令包，启动状态机；基于启动的状态机以及CSR寄存器中的配置参数数据，进行DMA模块的配置。
NP(Network Processor，网络处理器)处理器包括至少一个NP核，所有NP核通过总线NOC与SOC(System on Chip，SOC)系统的DMA模块连接，以及DMA配置电路设置在NP核上。其中，NP核中的DMA配置电路的主控处理器接收DMA配置指令，DMA配置指令用于DMA模块的配置，指令发射槽可存储DMA配置指令包，DMA控制模块可通过总线NOC与远程的DMA模块连接，进而根据该DMA配置指令包，实现DMA模 块的配置。
一些实施例中，DMA配置电路还包括地址相关性检测模块，被配置为响应于目标DMA配置指令包为待执行指令包，确定目标DMA配置指令包无地址相关性。
一些实施例中，DMA配置电路还包括译码模块。译码模块被配置为响应于接收的DMA配置指令为待执行指令包，对DMA配置指令进行译码，并确定DMA配置指令的第一地址范围信息，生成DMA配置指令包；DMA配置指令包中包括第一地址范围信息。地址相关性检测模块，还被配置为获取当前正在执行的指令的状态信息，状态信息包括正在执行的指令的第二地址范围信息；以及获取目标DMA配置指令包的第一地址范围信息，确定第一地址范围信息与第二地址范围信息无重叠。
一些实施例中，DMA配置电路还包括主控处理器。主控处理器被配置为将接收的待执行指令包类型的DMA配置指令并通过ACE接口发送至译码模块。由于DMA配置指令为自定义的地址映射的指令，需要通过特定的接口传输。该ACE接口为一种协处理器接口，用于接收该自定义指令。
一些实施例中，DMA控制模块包括：指令包接收单元、数据选择器、CSR寄存器、状态机控制单元、总线端口驱动模块；其中，指令包接收单元被配置为接收目标DMA配置指令包；数据选择器被配置为根据指令包接收单元的解析结果，确定目标DMA配置指令包是否为CSR寄存器配置包；并将确定的CSR寄存器配置包类型的DMA配置指令包发送至CSR寄存器，并将待执行指令包类型的DMA配置指令包(非CSR寄存器配置包)发送至状态机控制单元；CSR寄存器被配置为根据CSR寄存器配置包类型的DMA配置指令包更新配置参数数据；状态机控制单元被配置为根据待执行指令包类型的DMA配置指令包启动状态机；总线端口驱动模块被配置为根据状态机控制单元的控制，通过总线将配置参数数据发送至DMA模块，使得启动的状态机读取DMA模块的通道信息，以及响应于DMA模块的通道信息没有被占用，根据配置参数数据进行DMA模块的配置。其中，配置参数数据为CSR寄存器中更新的该DMA模块对应的配置参数数据。
一些实施例中，DMA控制模块还包括异常判断单元。异常判断单元被配置为接收译码模块的译码结果，以判断DMA配置指令是否异常，译码模块响应于无异常的DMA配置指令，将DMA配置指令包发送至指令发射槽。
具体地，异常判断单元将译码处理后的DMA配置指令进行异常判断，以判断DMA配置指令是否可执行；其中，判断包括对DMA配置指令编码异常判断，和/或第一地址范围异常判断；其中，若判断出有异常，则进行异常处理；若无异常，则将该DMA 配置指令的译码结果打包为DMA配置指令包，且发送至指令发射槽。若主控处理器向译码模块发送的DMA配置指令为CSR寄存器配置包类型，则可不用译码，译码模块将该CSR寄存器配置包类型的DMA配置指令直接发送至异常判断单元进行异常判断，该异常判断包括编码异常判断，和/或指令中读写地址范围的异常判断。由于CSR寄存器配置包类型的DMA配置指令也涉及数据的读取或者写入，所以该指令中读写地址是指CSR寄存器配置包类型的DMA配置指令中读写操作的地址。若异常判断单元确定CSR寄存器配置包类型的DMA配置指令无异常，则可直接将该DMA配置指令进行打包，得到CSR寄存器配置包类型的DMA配置指令包。
参考图2，DMA配置电路中，SOC系统的DMA模块与NP核的DMA控制模块连接。NP核包括DMA控制模块、地址相关性检测模块、指令发射槽、译码模块和主控处理器。具体地，DMA模块与NP核的DMA控制模块通过NOC总线连接。地址相关性检测模块与指令发射槽连接。指令发射槽分别与DMA控制模块和译码模块连接。译码模块与主控处理器和DMA控制模块连接，其中，主控处理器可以通过ACE(Adaptive Communication Environment)接口将DMA配置指令发送至译码模块连接。
本申请实施例中，在NP核中设置指令发射槽，以用于独立存储DMA配置指令包，可降低配置过程中对NP处理器的性能影响，提升配置效率。
根据本发明实施例的DMA配置电路，可以同时对多个DMA模块进行配置，以及，同时接收多个DMA模块配置完成的反馈。例如，指令发射槽中存储有4个DMA配置指令包，其中包括2个CSR寄存器配置包和2个待执行指令包，即CSR寄存器配置包A、待执行指令包A和CSR寄存器配置包B、待执行指令包B依次存储在指令发射槽中，其中，CSR寄存器配置包A、待执行指令包A用于对DMA模块A进行配置，CSR寄存器配置包B、待执行指令包B用于对DMA模块B进行配置。
具体的，指令发射槽中发送CSR寄存器配置包A至DMA控制模块，其中，DMA控制模块的指令包接收单元接收CSR寄存器配置包A之后，将CSR寄存器配置包A传输给数据选择器，数据选择器判断接收的指令包为CSR寄存器配置包，则将该CSR寄存器配置包A发送至CSR寄存器，使得CSR寄存器根据CSR寄存器配置包A更新DMA模块A对应的配置参数数据。
指令发射槽中将CSR寄存器配置包A发出之后，通过地址相关性检测模块检测待执行指令包A的地址相关性，确定无地址相关性后，指令发射槽发送待执行指令包A至DMA控制模块，其中，DMA控制模块的指令包接收单元接收待执行指令包A之后， 将待执行指令包A传输给数据选择器，数据选择器判断接收的指令包为待执行指令包，则将该待执行指令包A发送至状态机控制单元。状态机控制单元根据待执行指令包A启动状态机，基于该启动的状态机，确定DMA模块A的通道没有被占用，则总线端口驱动模块将CSR寄存器中存储的DMA模块A的配置参数数据通过总线NOC将发送至远程的DMA模块A，进而执行DMA模块A的配置。DMA模块A配置完成后，可通过总线NOC将反馈信息发送至DMA控制模块。
指令发射槽中将CSR寄存器配置包A发出之后，指令发射槽中发送CSR寄存器配置包B至DMA控制模块，其中，DMA控制模块的指令包接收单元接收CSR寄存器配置包B之后，将CSR寄存器配置包B传输给数据选择器，数据选择器判断接收的指令包为CSR寄存器配置包，则将该CSR寄存器配置包B发送至CSR寄存器，使得CSR寄存器根据CSR寄存器配置包B更新DMA模块B对应的配置参数数据。
指令发射槽中将CSR寄存器配置包B发出之后，通过地址相关性检测模块检测待执行指令包B的地址相关性，确定无地址相关性后，指令发射槽发送待执行指令包B至DMA控制模块，其中，DMA控制模块的指令包接收单元接收待执行指令包B之后，将待执行指令包B传输给数据选择器，数据选择器判断接收的指令包为待执行指令包，则将该待执行指令包B发送至状态机控制单元。状态机控制单元根据待执行指令包B启动状态机，基于该启动的状态机，确定DMA模块B的通道没有被占用，则总线端口驱动模块将CSR寄存器中存储的DMA模块B的配置参数数据通过总线NOC将发送至远程的DMA模块B，进而执行DMA模块B的配置。DMA模块B配置完成后，可通过总线NOC将反馈信息发送至DMA控制模块。
上述DMA模块A和DMA模块B之间的配置相互不影响，可同时进行配置，且配置完成后，即可反馈已完成，进而实现了同时对多个DMA模块进行配置，提升了配置效率。
基于上述硬件连接关系，参考图4，DMA配置电路的处理逻辑包括：S201、主控处理器接收DMA配置指令；
S202、主控处理器通过ACE接口将DMA配置指令发送到译码模块；
S203、译码模块被配置为响应于接收的DMA配置指令为待执行指令包，对DMA配置指令进行译码，并确定DMA配置指令的第一地址范围信息，生成DMA配置指令包；DMA配置指令包中包括第一地址范围信息；
其中，DMA配置指令包存储于指令发射槽；指令发射槽中待发送的DMA配置指令 包为目标DMA配置指令包；
S204、地址相关性检测模块被配置为响应于目标DMA配置指令包为待执行指令包，确定目标DMA配置指令包无地址相关性；
S205、DMA控制模块被配置为接收目标DMA配置指令包并进行解析；根据解析结果，以确定目标DMA配置指令包是否为CSR寄存器配置包；
其中，将确定的CSR寄存器配置包类型的DMA配置指令包发送至CSR寄存器，以更新配置参数数据，将待执行指令包类型的DMA配置指令包(非CSR寄存器配置包)发送至状态机控制单元，启动状态机；CSR寄存器被配置为根据CSR寄存器配置包类型的DMA配置指令包更新配置参数数据；状态机控制单元被配置为根据待执行指令包类型的DMA配置指令包启动状态机；
S206、远程的DMA模块根据配置参数数据进行DMA模块的配置。其中，配置参数数据为CSR寄存器中更新的该DMA模块对应的配置参数数据。
S207、DMA控制模块检测到远程SOC的DMA模块传输完成，结束DMA模块配置。
参考图3，DMA控制模块包括指令包接收单元、数据选择器、CSR寄存器、状态机控制单元、总线端口驱动模块和异常判断单元，异常判断单元分别与主控处理器和译码模块连接。指令包接收单元分别与数据选择器和指令发射槽连接。数据选择器分别与CSR寄存器和状态机控制单元连接。状态机控制单元与总线端口驱动模块连接。
基于上述硬件连接关系，参考图5，DMA控制模块的处理逻辑包括：
S301、指令包接收单元收到目标DMA配置指令包后解析，确定出CSR寄存器配置包和待执行指令包；
其中，数据选择器被配置为响应于目标DMA配置指令包为CSR寄存器配置包，将CSR寄存器配置包发送至CSR寄存器，以使CSR寄存器根据CSR寄存器配置包更新配置参数数据；状态机控制单元根据待执行指令包，启动状态机；
S302、DMA控制模块等待远程SOC的DMA模块的传输完成；
S303、DMA控制模块根据传输完成信息回到空闲状态。
参考图6，状态机的处理逻辑包括：
S401、根据收到的待执行指令包(非CSR寄存器配置包)启动；
S402、读取DMA模块的通道信息，响应于DMA模块的通道信息没有被占用，进行DMA模块的配置；
S403、接收DMA配置的反馈信息，直到所有的配置反馈全部收到；其中，反馈信 息包括控制寄存器配置、DMA传输的数据类型配置、DMA传输的形状配置、DMA传输的源地址配置、目的地址配置成功或配置失败的反馈信息；
S405、根据全部的DMA配置反馈信息，结束DMA模块配置。
本申请实施例中，基于状态机的配置，将读写寄存器命令和数据发送至DMA模块，实现DMA模块的配置，解决了NP处理器与DMA模块间因距离远导致的配置延时长，效率低的问题，提升了数据搬运的效率。
根据本申请实施例的第三个方面,提供了一种芯片，包括上述实施例所述的DMA配置电路。
根据本申请实施例的第四个方面,提供了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现上述实施例所述的DMA配置方法。
根据本申请实施例的第五个方面,提供了一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现上述实施例所述的DMA配置方法。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种DMA配置方法，其特征在于，包括：
    将DMA配置指令包存储至指令发射槽；其中指令发射槽中待发送的DMA配置指令包为目标DMA配置指令包；
    响应于所述目标DMA配置指令包为CSR寄存器配置包，将所述CSR寄存器配置包发送至CSR寄存器，以使所述CSR寄存器根据所述CSR寄存器配置包更新配置参数数据；
    响应于所述目标DMA配置指令包为待执行指令包，启动状态机；基于启动的所述状态机以及所述CSR寄存器中的配置参数数据，进行DMA模块的配置。
  2. 如权利要求1所述的DMA配置方法，其特征在于，响应于所述目标DMA配置指令包为待执行指令包，以及在启动状态机之前，还包括：
    确定所述目标DMA配置指令包无地址相关性。
  3. 如权利要求2所述的DMA配置方法，其特征在于，
    响应于接收的DMA配置指令为待执行指令包，以及在确定所述目标DMA配置指令包无地址相关性之前，还包括：对所述DMA配置指令进行译码，并确定所述DMA配置指令的第一地址范围信息，生成DMA配置指令包；所述DMA配置指令包中包括所述第一地址范围信息；
    确定所述目标DMA配置指令包无地址相关性的步骤，包括：
    获取当前正在执行的指令的状态信息，所述状态信息包括所述正在执行的指令的第二地址范围信息；
    获取所述目标DMA配置指令包的第一地址范围信息，确定所述第一地址范围信息与所述第二地址范围信息无重叠。
  4. 如权利要求1-3任一项所述的DMA配置方法，其特征在于，基于启动的所述状态机以及所述CSR寄存器中的配置参数数据，进行DMA模块的配置的步骤，包括：
    基于启动的所述状态机，读取DMA模块的通道信息；
    响应于所述DMA模块的通道信息没有被占用，基于启动的所述状态机以及所述CSR寄存器中的配置参数数据，进行DMA模块的配置；其中，所述DMA模块的配置至少包括以下一种：对应的控制寄存器，源数据地址，目的数据地址，传输数据类型。
  5. 如权利要求1-3任一项所述的DMA配置方法，其特征在于，在进行DMA模块的配置之后，还包括：
    接收DMA配置的反馈信息。
  6. 如权利要求3-5任一项所述的DMA配置方法，其特征在于，所述生成DMA配置指令包，包括：
    将译码处理后的DMA配置指令进行异常判断，其中，所述异常判断包括对DMA配置指令编码异常的判断，和/或，第一地址范围异常的判断；
    响应于所述DMA配置指令无异常，生成DMA配置指令包。
  7. 一种DMA配置电路，其特征在于，包括指令发射槽和DMA控制模块，所述DMA控制模块包括数据选择器、CSR寄存器和状态机控制单元；其中
    所述指令发射槽，被配置为存储DMA配置指令包；其中指令发射槽中待发送的DMA配置指令包为目标DMA配置指令包；
    所述数据选择器，被配置为响应于所述目标DMA配置指令包为CSR寄存器配置包，将所述CSR寄存器配置包发送至所述CSR寄存器，以使所述CSR寄存器根据所述CSR寄存器配置包更新配置参数数据；
    所述状态机控制单元，被配置为响应于所述目标DMA配置指令包为待执行指令包，启动状态机；基于启动的所述状态机以及所述CSR寄存器中的配置参数数据，进行DMA模块的配置。
  8. 如权利要求7所述的DMA配置电路，其特征在于，还包括地址相关性检测模块，被配置为响应于所述目标DMA配置指令包为待执行指令包，确定所述目标DMA配置指令包无地址相关性。
  9. 如权利要求8所述的DMA配置电路，其特征在于，还包括译码模块，被配置为响应于接收的DMA配置指令为待执行指令包，对所述DMA配置指令进行译码，并确定所述DMA配置指令的第一地址范围信息，生成DMA配置指令包；所述DMA配置指令包中包括所述第一地址范围信息；
    地址相关性检测模块，还被配置为获取当前正在执行的指令的状态信息，所述状态信息包括所述正在执行的指令的第二地址范围信息；以及获取所述目标DMA配置指令包的第一地址范围信息，确定所述第一地址范围信息与所述第二地址范围信息无重叠。
  10. 如权利要求7-9任一项所述的DMA配置电路，其特征在于，DMA控制模块还包括总线端口驱动模块；
    其中，所述状态机控制单元还被配置为基于启动的所述状态机，读取DMA模块的 通道信息；以及响应于所述DMA模块的通道信息没有被占用，通过所述总线端口驱动模块将CSR寄存器中的配置参数数据发送至DMA模块，以使所述DMA模块执行配置；其中，所述DMA模块的配置至少包括以下一种：对应的控制寄存器，源数据地址，目的数据地址，传输数据类型。
  11. 如权利要求9-10任一项所述的DMA配置电路，其特征在于，DMA控制模块还包括异常判断单元；
    所述异常判断单元被配置为接收所述译码模块的译码结果，以判断所述DMA配置指令是否异常，所述译码模块响应于无异常的DMA配置指令，将DMA配置指令包发送至指令发射槽。
  12. 如权利要求7-11任一项所述的DMA配置电路，其特征在于，所述DMA模块与所述DMA控制模块通过NOC总线连接。
  13. 如权利要求12所述的DMA配置电路，其特征在于，所述DMA控制模块通过所述NOC总线接收DMA配置的反馈信息。
  14. 一种芯片，包括：如权利要求7-13中任一项所述的DMA配置电路。
  15. 一种计算机设备，其特征在于，所述设备包括：
    至少一个处理器；以及，
    与所述至少一个处理器通信连接的存储器；其中，
    所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以实现如权利要求1-6中任一项所述的DMA配置方法。
  16. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求1-6中任一项所述的DMA配置方法。
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US20050138233A1 (en) * 2003-12-23 2005-06-23 Intel Corporation Direct memory access control
CN102231142A (zh) * 2011-07-21 2011-11-02 浙江大学 一种带有仲裁器的多通道dma控制器
CN109710548A (zh) * 2018-12-21 2019-05-03 荆门博谦信息科技有限公司 一种dma控制数据传输方法、系统及设备
CN112711550A (zh) * 2021-01-07 2021-04-27 无锡沐创集成电路设计有限公司 Dma自动配置模块和片上系统soc

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US20050138233A1 (en) * 2003-12-23 2005-06-23 Intel Corporation Direct memory access control
CN102231142A (zh) * 2011-07-21 2011-11-02 浙江大学 一种带有仲裁器的多通道dma控制器
CN109710548A (zh) * 2018-12-21 2019-05-03 荆门博谦信息科技有限公司 一种dma控制数据传输方法、系统及设备
CN112711550A (zh) * 2021-01-07 2021-04-27 无锡沐创集成电路设计有限公司 Dma自动配置模块和片上系统soc

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