WO2023070574A1 - 显示基板及其制造方法和显示装置 - Google Patents

显示基板及其制造方法和显示装置 Download PDF

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Publication number
WO2023070574A1
WO2023070574A1 PCT/CN2021/127628 CN2021127628W WO2023070574A1 WO 2023070574 A1 WO2023070574 A1 WO 2023070574A1 CN 2021127628 W CN2021127628 W CN 2021127628W WO 2023070574 A1 WO2023070574 A1 WO 2023070574A1
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WIPO (PCT)
Prior art keywords
contact pads
dummy
group
display
electrode
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PCT/CN2021/127628
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English (en)
French (fr)
Inventor
王孝林
付鹏程
董职福
翁鸿韬
李志勇
王武
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/127628 priority Critical patent/WO2023070574A1/zh
Priority to CN202180003205.3A priority patent/CN116601770A/zh
Publication of WO2023070574A1 publication Critical patent/WO2023070574A1/zh

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  • Embodiments of the disclosure relate to a display substrate, a manufacturing method thereof, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • TFT liquid crystal displays can be divided into Twisted Nematic (TN) type, In Plane Switching (IPS) type and Advanced Super Dimension Switch (Advanced Super Dimension Switch, ADS) type according to the display mode.
  • TN Twisted Nematic
  • IPS In Plane Switching
  • ADS Advanced Super Dimension Switch
  • the improved technologies of ADS technology include high transmittance I-ADS technology, high aperture ratio H-ADS and high resolution S-ADS technology, etc.
  • Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • a display substrate comprising: a display area and a peripheral area located at least one side of the display area, the display substrate further comprising: a plurality of signal lines located in the display area, configured to provide signals to the display area; a plurality of contact pads, located in the peripheral area, configured to be electrically connected to the plurality of signal lines; at least two conductive connection lines, located in the peripheral area and located in the The plurality of contact pads are away from the side of the display area, the at least two conductive connection lines are arranged at intervals, and the at least two conductive connection lines are included in the first direction from the display area to the peripheral area.
  • the first conductive connecting line that is closest to the plurality of contact pads upward; wherein, at least part of the plurality of contact pads are located on the first conductive layer, the first conductive connecting line is located on the second conductive layer, and the first conductive layer and said second conductive layer are arranged as different layers.
  • the plurality of contact pads includes a first group of contact pads and a second group of contact pads, the first group of contact pads and the second group of contact pads are staggered by a certain distance along the first direction and The second group of contact pads is further away from the first conductive connection line than the first group of contact pads; the first group of contact pads is located on the first conductive layer.
  • the first group of contact pads and the second group of contact pads are offset by x contact pad positions along the first direction, where 0.5 ⁇ x ⁇ 1.5; the first group of contact pads The pad and the second group of contact pads do not overlap with the at least two conductive connection lines in a direction perpendicular to the display substrate.
  • the peripheral region includes a peripheral bonding region and a peripheral transition region between the peripheral bonding region and the display region.
  • the display substrate further includes: a plurality of leads located in the peripheral transition area and connected to the plurality of signal lines; the plurality of contact pads located in the peripheral bonding area and connected to the plurality of leads.
  • the plurality of signal lines includes a first group of signal lines and a second group of signal lines, and the plurality of leads includes a first group of leads and a second group of leads; the first group of leads is close to the first group of signal lines One side of the line is connected to the first set of signal lines and the side close to the first set of contact pads is connected to the first set of contact pads.
  • the first group of signal lines, the first group of leads and the first group of contact pads are all located on the first conductive layer.
  • the second set of lead wires is connected to the second set of signal lines on a side close to the second set of signal lines and connected to the first set of lead wires on a side close to the second set of contact pads.
  • Two groups of contact pads are connected; the second group of signal lines is located on the first conductive layer, and the second group of leads and the second group of contact pads are located on the second conductive layer.
  • the display substrate further includes: a base substrate; and a display pixel array located on the base substrate, the display pixel array is located in the display area, and the display pixel array includes: a display A pixel driving circuit, a first display electrode, a passivation layer, and a second display electrode configured to generate an electric field.
  • the display pixel driving circuit includes a thin film transistor, and the thin film transistor includes: a gate, source and drain electrodes and an interlayer insulating layer, and the interlayer insulating layer is located on the gate in a direction perpendicular to the base substrate and between the source and drain electrodes; the first display electrode and the source and drain electrodes are arranged on the same layer, and the first display electrode is electrically connected to the source and drain electrodes; the passivation layer is located on the first A side of the display electrode away from the base substrate; the second display electrode is located on a side of the passivation layer away from the first display electrode.
  • One of the first conductive layer and the second conductive layer is set on the same layer as the gate, and the other of the first conductive layer and the second conductive layer is set on the same layer as the source-drain electrode .
  • the source and drain electrodes are located on a side of the gate away from the base substrate; the first conductive layer is located on a side of the second conductive layer away from the base substrate ; The first conductive layer and the source-drain electrodes are set to the same layer and the same material, and the second conductive layer and the gate are set to the same layer and the same material.
  • the passivation layer and the interlayer insulating layer further extend to the peripheral region, and the interlayer insulating layer is located on a side of the second group of leads away from the substrate,
  • the second group of signal lines is located on a side of the interlayer insulating layer away from the second group of leads, and the passivation layer is located on a side of the second group of signal lines and the interlayer insulating layer away from the side of the base substrate.
  • the peripheral transition area is also provided with a first via hole, a second via hole and a transfer conductive pattern, the first via hole penetrates the passivation layer to expose at least one signal line in the second group of signal lines , the second via hole penetrates the passivation layer and the interlayer insulating layer to expose at least one lead corresponding to the at least one signal line in the second group of leads, and the transfer conductive pattern covers the The first via hole and the second via hole are used to electrically connect the at least one signal line and the at least one lead wire.
  • the at least two conductive connection lines further include: a second conductive connection line located on a side of the first conductive connection line away from the plurality of contact pads, and the second conductive connection line is located on At least one of the first conductive layer and the second conductive layer.
  • the first conductive connecting wire and the second conductive connecting wire are configured to transmit signals provided by an external circuit.
  • the display substrate further includes: a base substrate; a display pixel array located on the base substrate, the display pixel array located in the display area; and a display pixel array located on the base substrate
  • a dummy pixel array area, the dummy pixel array area includes a plurality of dummy pixels arranged in at least one row along at least part of the periphery of the display pixel array. Each of the dummy pixels is configured to be electrically connected to one of the plurality of contact pads.
  • the dummy pixel includes a dummy pixel driving circuit, a first dummy electrode and a second dummy electrode
  • the dummy pixel driving circuit includes a first dummy thin film transistor
  • the first dummy thin film transistor includes: a first A dummy gate and a first dummy source-drain electrode
  • the first dummy electrode is set on the same layer as the first dummy source-drain electrode
  • the second dummy electrode is located on the side of the first dummy electrode away from the base substrate One side of the dummy electrode and set apart from the first dummy electrode
  • the first dummy electrode is configured to be electrically connected to the first dummy source-drain electrode
  • the first dummy source-drain electrode is configured to be connected to the plurality of leads One of the electrical connections.
  • the first dummy electrode includes a first dummy sub-electrode and a second dummy sub-electrode, and the first dummy sub-electrode and the second dummy sub-electrode are spaced apart in the first direction and are insulated from each other; the second dummy sub-electrode is located on a side of the first dummy sub-electrode close to the display area.
  • one of the first dummy electrode and the second dummy electrode is a dummy pixel electrode, and the other is a dummy common electrode, and the dummy pixel electrode and the dummy common electrode are perpendicular to the substrate.
  • the direction of the base substrate overlaps with each other; the dummy pixel electrodes are plate-like electrodes, and the dummy common electrodes are slit-like electrodes.
  • the dummy pixel array area further includes: a plurality of second dummy thin film transistors located on a side of the plurality of dummy pixels away from the display area, and the plurality of second dummy thin film transistors are located along the At least part of the periphery of the dummy pixel array is arranged in at least one row.
  • Each of the second dummy thin film transistors includes: a second dummy gate and a second dummy source-drain electrode, and the second dummy source-drain electrode is configured to be electrically connected to one of the plurality of leads.
  • each of at least part of the plurality of contact pads extends along the first direction, and the extending direction of at least a part of each of the conductive connecting lines intersects with the first direction.
  • the minimum first distance between the first conductive connection line and at least some of the plurality of contact pads in the first direction is greater than or equal to 10 microns.
  • the extending direction of at least a part of each of the conductive connecting lines is perpendicular to the first direction.
  • a first distance between the first conductive connection line and at least some of the plurality of contact pads in the first direction is greater than or equal to 10 microns.
  • the first pitch is smaller than the line width of the first conductive connecting line.
  • the display substrate further includes a plurality of input contact pads disposed in the peripheral area, the plurality of input contact pads include at least two groups of input contact pads, and the at least two groups of input contact pads include A first group of input contact pads and a second group of input contact pads, each of the conductive connection lines is electrically connected between the first group of input contact pads and the second group of input contact pads.
  • the first group of input contact pads is configured to receive an external signal provided by an external circuit; each of the conductive connecting lines is configured to transmit the external signal received by the first group of input contact pads to the second group of input contact pad.
  • a display device including the above-mentioned display substrate.
  • the display device further includes a driving chip
  • the display substrate further includes a plurality of input contact pads disposed in the peripheral area, wherein the plurality of input contact pads include at least two groups of input contacts pads, the at least two sets of input contact pads include a first set of input contact pads and a second set of input contact pads, each of the conductive connecting lines is electrically connected to the first set of input contact pads and the second set of input contact pads.
  • the plurality of contact pads are electrically connected to the driving chip and used as output contact pads of the driving chip, and the driving chip provides control signals to the plurality of contact pads.
  • a method for manufacturing a display substrate including: forming a plurality of signal lines, a plurality of contact pads, and at least two conductive connection lines, wherein the plurality of signal lines are located on the display substrate of the display substrate.
  • the plurality of contact pads are located in the peripheral area of the display substrate and are electrically connected to the plurality of signal lines, and the at least two conductive connection lines are located in the peripheral area area and located on the side of the plurality of contact pads away from the display area, the at least two conductive connection lines are arranged at intervals, and the at least two conductive connection lines are included in the direction from the display area to the periphery
  • the first conductive layer and the second conductive layer are provided as different layers.
  • a first group of contact pads of the plurality of contact pads is located on the first conductive layer.
  • the manufacturing method further includes: forming a plurality of leads, the plurality of leads are located in the peripheral transition region of the peripheral region and are electrically connected to the plurality of signal lines, and the plurality of contact pads are connected to the plurality of contact pads.
  • the plurality of leads are electrically connected; wherein, the first group of signal lines among the plurality of signal lines, the first group of leads among the plurality of leads, and the first group of contact pads are all located on the first conductive layer and integrally formed.
  • the second group of signal lines in the plurality of signal lines is located on the first conductive layer, the second group of leads in the plurality of leads and the second group in the plurality of contact pads
  • the second contact pad is located on the second conductive layer and integrally formed.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a partially enlarged structure of a region M of the display substrate shown in FIG. 1;
  • Fig. 3 is a schematic cross-sectional view along line A1-A1 of Fig. 2;
  • Fig. 4 is a schematic cross-sectional view along line A2-A2 of Fig. 2;
  • Fig. 5 is a schematic cross-sectional view along the line B1-B1 of Fig. 2;
  • Fig. 6 is a schematic cross-sectional view along the line B2-B2 of Fig. 2;
  • Fig. 7 is a schematic cross-sectional view along the I-I line of Fig. 2;
  • Fig. 8 is a schematic cross-sectional view along the line II-II of Fig. 2;
  • FIG. 9 is a schematic partial cross-sectional view of a liquid crystal display device provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a partially enlarged structure of a region N of the display substrate shown in FIG. 1;
  • Fig. 11 is a schematic cross-sectional view along the C-C line of Fig. 10;
  • Fig. 12 is a schematic cross-sectional view along the D-D line of Fig. 10;
  • Fig. 13 is a schematic cross-sectional view along the E-E line of Fig. 10;
  • Fig. 14 is a schematic cross-sectional view along the F-F line of Fig. 10;
  • FIG. 15 is a schematic structural diagram of a peripheral bonding region of a display substrate provided by an embodiment of the present disclosure.
  • 16 is a simplified schematic cross-sectional view of a peripheral bonding region of a display substrate provided by an embodiment of the present disclosure
  • FIG. 17 is a flowchart of a method for manufacturing a display substrate provided by an embodiment of the present disclosure.
  • some special manufacturing processes may cause static electricity.
  • static electricity will be formed through friction or redistribution of charges due to mutual attraction of charges.
  • the inventors have found that when the static electricity is broken down, the static electricity generated by the above-mentioned friction may flow into the display area from the non-display area, thereby causing poor display to occur in the display area.
  • the performance of poor display can be bright lines (such as X bright lines ) or bright spots, and, with the increase in the number of times the rubbing cloth is used, the incidence of such defects is gradually increasing, which seriously affects the display effect of the display device.
  • the display substrate of the present disclosure includes a peripheral area in which a plurality of contact pads are arranged, and each signal line in the display area is electrically connected to the plurality of contact pads, and is electrically connected to an external circuit through the plurality of contact pads.
  • a plurality of input contact pads and conductive connection lines are also arranged in the peripheral area, and a part of the input contact pads are connected with external circuits for receiving signals provided by the external circuits.
  • the conductive connection wires are electrically connected between a part of the input contact pads and another part of the input contact pads, and are used to transmit external signals on a part of the input contact pads to the other part of the input contact pads.
  • Another part of the input contact pads transmits external signals to the driver chip (the driver chip is bonded in the peripheral area), and the driver chip provides external signals to a plurality of contact pads and transmits control signals to the display area through the plurality of contact pads.
  • At least one embodiment of the present disclosure provides a display substrate, including a display area and a peripheral area located on at least one side of the display area.
  • the display substrate further includes: a plurality of signal lines, a plurality of contact pads and at least two conductive connection lines.
  • the plurality of signal lines are located in the display area and configured to provide signals to the display area.
  • the plurality of contact pads are located in the peripheral area and are electrically connected to the plurality of signal lines.
  • the at least two conductive connection lines are located in the peripheral area and located on a side of the plurality of contact pads away from the display area.
  • the at least two conductive connecting wires are arranged at intervals.
  • the at least two conductive connection lines include a first conductive connection line closest to the plurality of contact pads in a first direction directed from the display area to the peripheral area.
  • the at least part of the plurality of contact pads is located on the first conductive layer
  • the first conductive connection line is located on the second conductive layer
  • the first conductive layer and the second conductive layer are arranged as different layers.
  • At least part of the contact pad and the first conductive connection line closest to the at least part of the contact pad are respectively arranged in two conductive layers of different layers, which can avoid at least part of the contact pad A sharp electric field is formed between the contact pad and the first conductive connection line, thereby preventing electrostatic discharge and conduction, reducing or even eliminating display defects in the display area.
  • a display substrate includes a base substrate and multiple layers stacked on each other formed on the base substrate, each layer representing a level.
  • component A is configured to be electrically connected to component B
  • component A is electrically connected to component B under certain circumstances, and does not mean that component A is always electrically connected to component B.
  • part A is electrically connected to part B, and in other cases part A is not electrically connected to part B.
  • first direction R1 and the second direction R2 are parallel to the plane of the base substrate, and the third direction R3 is perpendicular to the plane of the base substrate SUB.
  • “multiple” means two or more.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a partially enlarged structure of a region M of the display substrate shown in FIG. 1 .
  • a display substrate 100 provided by at least one embodiment of the present disclosure includes a display area AA and a peripheral area PA surrounding the display area AA.
  • the display area AA is used to display images
  • the peripheral area PA is a non-display area.
  • the peripheral area PA includes a peripheral bonding area PBA located on one side of the display area AA (such as the lower side shown in the figure) and a peripheral transition between the peripheral bonding area PBA and the display area AA. District PTA. It can be understood that the peripheral bonding area PBA and the peripheral transition area PTA can also be provided on other sides of the display area AA (for example, the left side of the display area AA), which are omitted in the figure for the sake of simplification.
  • the display substrate 100 includes a base substrate SUB, and the display area AA, the peripheral transition area PTA and the peripheral bonding area PBA are all located on the base substrate SUB, that is, the orthographic projection of each of the above regions is located on the base substrate SUB.
  • the display area AA includes a pixel array and scan lines (gate lines), data lines, power lines, etc. that provide control signals, data signals, voltage signals, etc. for the pixel array.
  • the display substrate 100 includes a plurality of first signal lines and a plurality of second signal lines, the first signal lines are, for example, data lines DL extending along a first direction R1, and the second signal lines are, for example, a second direction R2 (for example, A gate line GL extending in a direction perpendicular to the first direction R1).
  • a plurality of data lines DL and a plurality of gate lines GL intersect each other to define a plurality of display pixel regions, and display pixels PX are disposed in each display pixel region.
  • a plurality of display pixels PX are arranged in an array to form a display pixel array.
  • the data line DL and the gate line GL in FIG. This is not limited.
  • the gate line GL and the data line DL may extend or route to the peripheral bonding area PBA located at least one side of the display area AA.
  • a plurality of lead wires W are arranged in the peripheral transition area PTA, and a plurality of data lines DL are electrically connected to the plurality of lead wires W in one-to-one correspondence. out) electrical connection.
  • a plurality of gate lines GL can also be electrically connected to other plurality of lead wires (not shown) in one-to-one correspondence, thereby being electrically connected to another driver chip (not shown) in the peripheral bonding area on the left side of the display area AA. connect.
  • Embodiments of the present disclosure are described by taking the data line DL and the lead wire W located in the peripheral transition area PTA below the display area AA as an example.
  • the peripheral bonding area PBA is located on the side of the peripheral transition area PTA away from the display area AA.
  • the peripheral bonding area PBA is used to electrically connect the external circuit with the display substrate 100 through a bonding process.
  • the external circuit may include a flexible circuit board or the like for providing external signals to the plurality of contact pads P. Referring to FIG. A plurality of contact pads P are disposed in the peripheral bonding area PBA, and the plurality of contact pads P are located on a side of the plurality of lead wires W away from the display area AA and are electrically connected to the plurality of lead wires W in one-to-one correspondence.
  • the lead wire W is formed in the same layer as the data line DL in the display area AA, and thus can be integrally formed, or formed in a different layer, and thus needs to be electrically connected to each other through a via hole in the insulating layer between the two.
  • two conductive connecting wires Z are also arranged in the peripheral bonding area PAB for transmitting different external signals.
  • the two conductive connection lines Z are located on a side of the plurality of contact pads P away from the display area AA, and they are arranged at intervals.
  • the two conductive connecting lines Z include a first conductive connecting line Z1 and a second conductive connecting line Z2, wherein the first conductive connecting line Z1 is closest to the first direction R1 from the display area AA to the peripheral area PA. close to the plurality of contact pads P.
  • the second conductive connection line Z2 is located on a side of the first conductive connection line Z1 away from the plurality of contact pads P. As shown in FIG.
  • the first conductive connection line Z1 is used for transmitting the working voltage VDD, and the second conductive connection line Z2 is used for grounding.
  • the first conductive connecting wire Z1 and the second conductive connecting wire Z2 are insulated from each other.
  • FIG. 1 only shows two conductive connecting wires Z1 and Z2. It can be understood that more conductive connecting wires can be set in the peripheral bonding area PAB, which is not limited in this embodiment of the present disclosure. .
  • the first direction R1 is taken as the vertical direction as an example for illustration. It can be understood that the term "the first direction from the display area AA to the peripheral area PA" refers to an orientation, as long as the direction from the display area to the peripheral area is included in the category of the first direction, therefore, the first
  • the direction R1 is not necessarily a vertical direction, but may also be an oblique direction inclined at a certain angle to the vertical direction, or even a horizontal direction.
  • the second direction R2 is a direction perpendicular to the first direction R1.
  • Fig. 3 is a schematic cross-sectional view along line A1-A1 of Fig. 2 .
  • Fig. 4 is a schematic cross-sectional view along line A2-A2 of Fig. 2 .
  • Fig. 5 is a schematic cross-sectional view along line B1-B1 of Fig. 2 .
  • Fig. 6 is a schematic cross-sectional view along line B2-B2 in Fig. 2 .
  • Fig. 7 is a schematic cross-sectional view along line I-I of Fig. 2 .
  • FIG. 8 is a schematic cross-sectional view along line II-II of FIG. 2 .
  • the plurality of contact pads P includes a first group of contact pads P1 and a second group of contact pads P2 .
  • the first group of contact pads P1 includes a plurality of first contact pads P1, and the second group of contact pads P2 includes a plurality of second contact pads P2.
  • the plurality of data lines DL includes a first group of data lines DL1 and a second group of data lines DL2.
  • the first group of data lines D1 includes a plurality of first data lines D1, and the second group of data lines D2 includes a plurality of second data lines D2.
  • the plurality of wires W includes a first group of wires W1 and a second group of wires W2.
  • the first group of wires W1 includes a plurality of first wires W1, and the second group of wires W2 includes a plurality of second wires W2.
  • the first group of lead wires W1 is electrically connected to the first group of data lines DL1 on the side close to the first group of data lines DL1 and is electrically connected to the side close to the first group of contact pads P1.
  • the first set of contact pads P1 are electrically connected.
  • the second group of lead wires W2 is electrically connected to the second group of data lines DL2 on a side close to the second group of data lines DL2 and is electrically connected to the second group of contact pads P2 on a side close to the second group of data lines DL2.
  • Group contact pads P2 are electrically connected.
  • a plurality of first ends (not marked) of the plurality of first lead wires W1 close to the first data line D1 are electrically connected to the plurality of first data lines D1 in one-to-one correspondence, and the plurality of first lead wires W1
  • a plurality of second ends (not marked) close to the first contact pads D1 are electrically connected to the plurality of first contact pads P1 in one-to-one correspondence.
  • a plurality of first ends (not marked) of the plurality of second lead wires W2 close to the second data line D2 are electrically connected to the plurality of second data lines D2 in one-to-one correspondence, and the plurality of second lead wires W2 close to the first end portion
  • Multiple second ends (not shown) of the two contact pads D1 are electrically connected to the multiple second contact pads P2 in one-to-one correspondence.
  • first end and the second end of the first lead W1 and the first end and the second end of the second lead W2 are used to describe the technical features more clearly.
  • first end and the second end of the second lead W2 A lead W1 or a second lead W2 does not have a clear boundary defining the first end and the second end.
  • the display substrate 100 further includes a first insulating layer (such as an interlayer insulating layer IL) and a second insulating layer (such as an interlayer insulating layer IL) and a second insulating layer that are sequentially located on the base substrate SUB and extend from the display area AA to the peripheral area PA.
  • the insulating layer (for example, the passivation layer PVX) further includes a first conductive layer ECL1 and a second conductive layer ECL2 located in the peripheral area PA.
  • the first conductive layer ECL1 is located between the interlayer insulating layer IL and the passivation layer PVX in the direction perpendicular to the base substrate SUB
  • the second conductive layer ECL2 is located between the base substrate SUB and the interlayer insulating layer in the direction perpendicular to the base substrate SUB. between layers IL.
  • the first group of contact pads P1 is located on the first conductive layer ECL1, and the first conductive connection line Z1 is located on the second conductive layer ECL2. Since the first conductive layer ECL1 and the substrate SUB are separated and insulated from each other by the interlayer insulating layer IL, the first conductive layer ECL1 is not in direct contact with the substrate SUB. The second conductive layer ECL2 is in direct contact with the base substrate SUB. Since the first conductive layer ECL1 and the second conductive layer ECL2 are located in different layers, the first group of contact pads P1 and the first conductive connection line Z1 are also located in different layers.
  • each of at least a part of the contact pads in the plurality of contact pads extends along the first direction, and the extension direction of at least a part of each of the conductive connection lines is mutually opposite to the first direction. cross.
  • each of the plurality of contact pads P extends along the first direction R1
  • at least a portion of the first conductive connection line Z1 extends along the second direction R2.
  • the contact pads P that is, the first group of contact pads P1
  • the first conductive connection line Z1 in different layers, it is possible to avoid A sharp electric field is formed between them. In this way, even if static electricity is generated in the peripheral bonding area PBA, the risk of being transferred to the display area can be reduced, thereby reducing or even eliminating the display defects in the display area.
  • the first data line DL1 and the first lead W1 are located on the first conductive layer ECL1, thus, the first data line DL1, the first lead W1 and the first contact pad P1 are all located on the first conductive layer ECL1 , that is, the first group of data lines DL1 , the first group of lead wires W1 and the first group of contact pads P1 are all located on the first conductive layer ECL1 .
  • the first group of contact pads P1, the first group of data lines DL1 electrically connected to the first group of contact pads P1, and the first group of lead wires W1 are all located on the first conductive layer ECL1 makes the first group of data lines DL1 electrically connected to the first group of contact pads P1 without passing through the transfer holes, reducing the risk of static electricity being introduced into the data lines with transfer holes, thereby eliminating the risk of the transfer holes being damaged by static electricity.
  • the second group of contact pads P2, the second group of data lines DL2 and the second group of lead wires W2 electrically connected to the second group of contact pads P2 can be located in the same conductive layer (for example, the first conductive layer ECL1 or the second conductive layer
  • the second conductive layer ECL2) can also be located in two different conductive layers.
  • the manufacturing process can be simplified.
  • the signal line uses the transfer hole structure for layer-changing design, which can reduce the space occupied by the signal line or lead wire in the surrounding area and improve the space utilization rate of the surrounding area. The following description will be made by taking the second group of contact pads P2 , the second group of data lines DL2 , and the second group of lead wires W2 located on different layers as an example.
  • the second group of contact pads P2 is located on the second conductive layer ECL2 .
  • the second group of lead wires W2 electrically connected to the second group of contact pads P2 are located on the second conductive layer ECL2 ;
  • the second group of data lines DL2 electrically connected to the second group of lead wires W2 are located on the first conductive layer ECL1 . That is, the second group of contact pads P2 and the second group of lead wires W2 are disposed in a different layer from the second group of data lines DL2.
  • the second lead W2 passes through the first via hole VH1, the second via hole VH2, and the transitions located in the first via hole VH1 and the second via hole VH2.
  • the conductive pattern DWP is electrically connected to the second data line D2, so that the second group of data lines DL2 is electrically connected to the second group of contact pads P2 through via holes such as the first via hole VH1 and the second via hole VH2.
  • the spacing between the multiple leads is designed to be narrow.
  • the spacing between the leads is too close, there may be a problem of signal crosstalk.
  • the first lead W1 and the second lead W2 are located on the same conductive layer (for example, the first conductive layer ECL1 ), the signal crosstalk problem will be more obvious.
  • the second lead W2 is located on the second conductive layer ECL2 by adopting the design of the via hole. Since the first conductive layer ECL1 and the second conductive layer ECL2 are insulated from each other, even if the first lead W1 and the second lead W2 The distance between them is relatively close, and the problem of signal crosstalk between the two can also be avoided. In this way, without affecting the signal transmission of the first lead W1 and the second lead W2, the distance between the first lead W1 and the second lead W2 can be further reduced, and the space utilization rate of the peripheral area can be improved.
  • the layer change of the second data line DL2 is realized through the first via hole VH1 penetrating the passivation layer PVX, the second via hole VH2 penetrating the passivation layer PVX and the interlayer insulating layer IL, and the transfer conductive pattern DWP.
  • other via hole structures may also be used to realize the layer change of the second data line DL2.
  • a via hole may be formed in the interlayer insulating layer IL, the via hole exposing the second lead W2, and then the second data line DL2 on the interlayer insulating layer IL may be formed to cover the via hole to communicate with the exposed second lead wire. W2 is electrically connected, therefore, the embodiments of the present disclosure do not limit the layer-changing structure.
  • a first conductive pattern EDP1 is further disposed on a side of the passivation layer PVX away from the base substrate SUB.
  • the passivation layer PVX covers the edge of the first contact pad P1 and is provided with a first contact hole CH1.
  • the first conductive pattern EDP1 is electrically connected to the first contact pad P1 through the first contact hole CH1. In this way, the first contact pad P1 can be electrically connected to an external circuit through the first conductive pattern EDP1, thereby realizing signal transmission.
  • a second conductive pattern EDP2 is further disposed on a side of the passivation layer PVX away from the base substrate SUB.
  • An insulating layer stack composed of a passivation layer PVX and an interlayer insulating layer IL covers the edge of the second contact pad P2 and is provided with a second contact hole CH2.
  • the second conductive pattern EDP2 is electrically connected to the second contact pad P2 through the second contact hole CH2. In this way, the second contact pad P2 can be electrically connected with an external circuit through the second conductive pattern EDP2, thereby realizing signal transmission.
  • the edge of the contact pad includes an edge extending along the periphery of the contact pad.
  • the first group of contact pads P1 and the second group of contact pads P2 do not overlap with the two conductive connection lines Z1 and Z2 in a direction perpendicular to the display substrate, and each A set of contact pads and two conductive connection lines Z1, Z2 are mutually insulated.
  • the "direction perpendicular to the display substrate” refers to the direction perpendicular to the plane where the display substrate is located, and can also be understood as the direction perpendicular to the plane where the base substrate SUB is located. In other words, there is no intersection between the orthographic projections of the first group of contact pads P1 and the second group of contact pads P2 on the substrate SUB and the orthographic projections of the two conductive connecting lines Z1 and Z2 on the substrate SUB. stack.
  • both the first group of contact pads P1 and the second group of contact pads P2 extend along the first direction R1, and there is a certain distance between them, so that the second group of contact pads P2 is larger than the first group of contact pads P1. farther away from the first conductive connection line Z1.
  • staggered means that the center point of the first contact pad P1 in the first group of contact pads P1 and the center point of the second contact pad P2 in the second group of contact pads P2 are not arranged on the same straight line in the second direction R2 superior.
  • the second group of contact pads P2 are electrically connected to the second group of data lines DL2 having a transfer hole structure, by disposing the second group of contact pads P2 farther away from the first conductive connection than the first group of contact pads P1
  • the line Z1 can reduce the risk of frictional static electricity being introduced into the second group of contact pads P2, and avoid static electricity from damaging the transfer hole structure on the second group of data lines DL2.
  • the term "stagger" is not limited to the length of the first group of contact pads P1 in the first direction R1 and the length of the second group of contact pads P2 in the first direction R1, nor does it necessarily mean that a contact is staggered.
  • the length of the pad It is sufficient as long as the center point of the first contact pad P1 and the center point of the second contact pad P2 are not arranged on the same straight line in the second direction R2.
  • the first group of contact pads P1 and the second group of contact pads P2 may also overlap along the second direction R2, which is not limited in the present disclosure.
  • the length of the first contact pad P1 in the first direction R1 and the length of the second contact pad P2 in the first direction R1 may be the same or different.
  • the length of the first contact pad P1 is equal to the length of the second contact pad P2, and the first contact pad P1 and the second contact pad P2 are staggered by at least one contact along the first direction R1. Pad position. In this case, not only the manufacturing process can be simplified, but also the introduction of static electricity into the second contact pad P2 can be avoided.
  • the relative position between the first contact pad P1 and the second contact pad P2 shown in FIG. 2 is only schematic. It can be understood that in other embodiments, the first contact pad P1 and the second The positions of the contact pads P2 may be offset by x contact pads (the first contact pad P1 or the second contact pad P2 ) along the first direction R1, where 0.5 ⁇ x ⁇ 1.5.
  • the number of first contact pads P1 and the number of second contact pads P2 may be the same or different; multiple first contact pads P1 may be arranged at equal or unequal intervals; multiple second contact pads P2 may be set at equal or unequal intervals, which is not limited in this embodiment of the present disclosure.
  • first contact pads P1 and the second contact pads P2 in FIG. A first contact pad P1 is disposed between them. It can be understood that, in other embodiments, two, three or more first contact pads P1 may be arranged between every adjacent two second contact pads P2; or, every adjacent two first contact pads P2 Two, three or more second contact pads P2 may be disposed between the contact pads P1, which is not limited in the present disclosure.
  • first contact pads P1 and the second contact pads P2 may be arranged in an alternating manner, or only a part of the second contact pads P2 and the first contact pads P1 may be arranged in an alternating manner , can realize the object of the present invention equally.
  • the second conductive connection line Z2 includes a first conductive portion Z2C1 located in the first conductive layer ECL1 and a second conductive portion Z2C2 located in the second conductive layer ECL2 .
  • the first conductive part Z2C1 and the second conductive part Z2C2 overlap in a direction perpendicular to the base substrate SUB.
  • the first conductive connection line Z1 is only arranged in one When the pad P1 extends in the extending direction (for example, the second direction R2), it has a larger line width, and the second conductive connection line Z2 is arranged in two conductive layers, along the direction perpendicular to the extending direction of the first contact pad P1 ( When the second direction R2) extends, it may have a smaller line width.
  • the second conductive connection line Z2 by arranging the second conductive connection line Z2 to be located in the first conductive layer ECL1 and the second conductive layer ECL2, it is possible to reduce the number of the second conductive connection line Z2 while ensuring that the transmission signal is not disturbed. The space occupied in the bonding zone.
  • the line widths of the first conductive connection line Z1 and the second conductive connection line Z2 are only schematic, and those skilled in the art can design according to actual needs, which is not limited in the embodiment of the present disclosure.
  • the arrangement of the second conductive connection line Z2 in this embodiment is only schematic.
  • the second conductive connection line Z2 can also be located only on the first conductive layer ECL1 or only It is located in the second conductive layer ECL2, which is not limited in the embodiments of the present disclosure.
  • the first set of contact pads P1 and the second set of contact pads P2 extend along said first direction R1. At least part of the first conductive connection line Z1 and at least part of the second conductive connection line Z2 extend along the second direction R2. Therefore, the included angle between the extending direction of the first group of contact pads P1 and the second group of contact pads P2 and the extending direction of at least part of the first conductive connection line Z1 and at least part of the second conductive connection line Z2 is equal to 90 degrees.
  • the above-mentioned angle may not be 90 degrees, such as greater than 0 degrees and less than 90 degrees, as long as at least part of the first conductive connection line Z1 and at least part of the second conductive connection line Z2 extend in the same direction as the first group of contact pads.
  • the extension directions of the P1 and the second group of contact pads P2 only need to cross each other, which is not limited in the present disclosure.
  • the formation of a sharp electric field between the plurality of contact pads P and the conductive connection lines can be further avoided. , thereby preventing static electricity from being introduced into the contact pad P.
  • the first distance L1 between the first conductive connection line Z1 and the first group of contact pads P1 in the first direction R1 is greater than or equal to 10 microns, optionally, for example, greater than or equal to Equal to 10 microns and less than or equal to 400 microns.
  • the first distance L1 may be 10 microns, 20 microns, 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns or 100 microns.
  • a second distance L2 between the second conductive connection line Z2 and the first group of contact pads P1 in the first direction R1 is greater than the first distance L1 .
  • the second conductive connection line Z2 By arranging the second conductive connection line Z2 farther away from the first group of contact pads P1 than the first conductive connection line Z1, the formation of a sharp electric field between the second conductive connection line Z2 and the first group of contact pads P1 can be avoided, thereby reducing the second conductive connection line Z2. It is possible for the static electricity on the two conductive connecting lines Z2 to enter the display area through the first group of contact pads P1.
  • the first distance L1 is smaller than the line width of the first conductive connecting line Z1.
  • the first distance L1 is smaller than the line width of the first conductive connecting line Z1, which is beneficial for the display panel to achieve a narrow frame.
  • the first distance L1 and the second distance L2 in this embodiment are illustrated by taking the extending direction of the first conductive connection line Z1 and the extending direction of the first group of contact pads P1 being perpendicular to each other as an example. It can be understood that when the extension direction of the first conductive connection line Z1 is not perpendicular to the extension direction of the first group of contact pads P1, the first conductive connection line Z1 and the first group of contact pads P1 are in the first direction.
  • R1 has the smallest first distance L1.
  • the smallest first distance L1 is, for example, greater than or equal to 10 microns, optionally, for example, greater than or equal to 10 microns and less than or equal to 400 microns.
  • the smallest first pitch may be 10 microns, 20 microns, 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns or 100 microns, etc.
  • the minimum first distance L1 is smaller than the line width of the first conductive connection line Z1.
  • the base substrate SUB may be a glass plate, a quartz plate, a metal plate or a resin plate or the like.
  • the material of the base substrate may include an organic material, for example, the organic material may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and resin materials such as polyethylene naphthalate, the substrate SUB may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.
  • the materials of the first insulating layer and the second insulating layer may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include polyimide, polyimide, polyamide , acrylic resin, benzocyclobutene or phenolic resin and other organic insulating materials.
  • inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride
  • polyimide, polyimide, polyamide , acrylic resin, benzocyclobutene or phenolic resin and other organic insulating materials Embodiments of the present disclosure do not specifically limit the material of the first insulating layer.
  • the material of the lead may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium.
  • Materials of the first conductive layer and the second conductive layer may include metal materials or alloy materials, such as metal single-layer or multi-layer structures formed of molybdenum, aluminum and titanium.
  • FIG. 9 is a schematic partial cross-sectional view of a liquid crystal display device provided by an embodiment of the present disclosure.
  • the liquid crystal display device includes a liquid crystal display panel, and the liquid crystal display panel includes an array substrate 200 and an opposite substrate 300 disposed opposite to each other in the third direction R3, and filling the array substrate 200 and the opposite substrate 300 between the liquid crystal layer LC.
  • the array substrate 200 and the color filter substrate 300 form a closed liquid crystal cell through a cell-assembly process with a sealant (not shown), and the liquid crystal layer LC is sealed in the liquid crystal cell.
  • the array substrate 200 includes a base substrate SUB and a display pixel PX formed on the base substrate SUB, and the display pixel PX includes a display pixel driving circuit, a pixel electrode PE (that is, a first display electrode), a passivation layer PVX, The common electrode CE (ie, the second display electrode) and the first alignment layer PI1.
  • the display pixel driving circuit includes a thin film transistor TFT and a storage capacitor (not shown), and the embodiments of the present disclosure are not limited to the display pixel driving circuit.
  • the thin film transistor TFT may be of a top-gate type or a bottom-gate type, and the embodiment of the present disclosure takes a bottom-gate type TFT as an example for illustration.
  • the thin film transistor TFT includes: a gate GE, source and drain electrodes SE/DE, an active layer AT and an interlayer insulating layer IL.
  • the gate GE is arranged on the same layer as the gate line GL, and the source-drain electrodes SE/DE are arranged on the same layer as the data line DL.
  • the interlayer insulating layer IL is located between the gate GE and the source-drain electrodes SE/DE in the third direction R3, for example, between the gate GE and the active layer AT.
  • the source-drain electrodes SE/DE are located on the side of the active layer AT away from the gate GE and cover the active layer AT.
  • an etching stopper layer may be provided on a side of the source-drain electrodes SE/DE away from the substrate SUB to prevent damage to the source-drain electrodes SE/DE by the etching process.
  • the pixel electrode PE is located on a side of the interlayer insulating layer away from the base substrate, and is arranged on the same layer as the source-drain electrodes SE/DE.
  • the data line DL is electrically connected to the source SE of the thin film transistor TFT, and the pixel electrode PE is electrically connected to the drain DE, so that the data line signal in the data line DL is loaded to the pixel electrode PE.
  • the passivation layer PVX is located on the side of the pixel electrode PE away from the substrate SUB, and the common electrode CE is located on the side of the passivation layer PVX away from the pixel electrode PE, thus, the pixel electrode PE and the The common electrodes CE are insulated from each other by the passivation layer PVX.
  • the pixel electrode PE applies the data line voltage VData
  • the common electrode CE applies the common voltage Vcom
  • a transverse electric field is formed between the two, and the transverse electric field acts on the liquid crystal layer LC.
  • the liquid crystal molecules in the liquid crystal the liquid crystal molecules are deflected to a certain extent.
  • the pixel electrode PE is a plate-shaped electrode
  • the common electrode CE is a slit-shaped electrode, including a plurality of slit-shaped electrodes. It can be understood that, the pixel electrode PE may also be a slit-shaped electrode, and the common electrode CE may be a plate-shaped electrode, which is not limited in the embodiments of the present disclosure.
  • the pixel electrode PE and the common electrode CE are formed of transparent conductive materials, such as, but not limited to transparent conductive oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) wait.
  • transparent conductive oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) wait.
  • the opposite substrate 300 includes an opposite base substrate SUB', a color filter layer CF, a black matrix layer BM, and a second alignment layer PI2 disposed on the opposite base substrate SUB'.
  • the color filter layer CF can be provided in the same layer as the black matrix layer BM, and is used to convert the light passing through the liquid crystal layer LC into light having a color corresponding to the color of the color filter layer CF, thereby realizing color display.
  • the color filter layer CF includes color filter units (such as RGB color filter units) arranged in an array.
  • the material of the color filter unit includes photosensitive resin.
  • the black matrix BM and the color filter layer CF are covered with a planarization layer OC to planarize the surface of the opposite substrate 300 .
  • the black matrix layer BM is used to prevent crosstalk or light leakage between display pixels PX.
  • the orthographic projection of the thin film transistor TFT on the substrate SUB along the third direction R3 falls into the orthographic projection of the black matrix layer BM on the substrate SUB along the third direction R3.
  • the color filter layer CF may also be provided in a different layer from the black matrix layer BM, which is not limited in the embodiments of the present disclosure.
  • the black matrix layer and the color filter layer may no longer be formed on the opposite substrate 300.
  • the material of the black matrix layer BM includes pigments with light-shielding properties to prevent light leakage between pixels.
  • the material of the black matrix layer BM may include carbon (C) or chromium (Cr).
  • the first alignment layer PI1 and the second alignment layer PI2 are disposed opposite to each other in the third direction R3 for aligning liquid crystal molecules in the liquid crystal layer LC.
  • the first alignment layer PI1 is located on a side of the common electrode CE of the array substrate 200 close to the liquid crystal layer LC.
  • the second alignment layer PI2 is located on the side of the planarization layer OC of the color filter substrate 300 close to the liquid crystal layer.
  • the material of the first alignment layer PI1 and the second alignment layer PI2 is, for example, polyimide.
  • a plurality of columnar spacers SP are disposed between the array substrate 200 and the color filter substrate 300 .
  • the column spacer SP is formed of, for example, a shape memory polymer material. When the rigidity of the spacer SP is high, it can play a good supporting role for the color filter substrate 300 and prevent the color filter substrate 300 from being deformed under the action of external force.
  • the liquid crystal display panel further includes a backlight module (not shown) disposed on the side of the array substrate 200 away from the opposite substrate 300.
  • the backlight module is on the non-display side of the liquid crystal display panel and is used to provide a light source for display.
  • the backlight module can be a side-illuminated type or a direct-lit type, and the light source used can be a cold-cathode fluorescent lamp, a light-emitting diode (LED), etc., and embodiments of the present invention are not limited thereto.
  • the liquid crystal display panel can be transmissive or transflective.
  • the liquid crystal display panel may be of reflective type, so that there is no need to additionally provide a backlight module for the liquid crystal display panel.
  • the liquid crystal display substrate shown in FIG. 9 may be applicable to a liquid crystal panel in an advanced super dimension switch (Advanced Super Dimension Switch, ADS) mode or a variant thereof.
  • ADS Advanced Super Dimension Switch
  • the base substrate SUB, the interlayer insulating layer IL, and the passivation layer PVX extend into the peripheral area PA. Therefore, in the embodiment of the present disclosure, the hierarchical structure of each functional layer in FIG. 3 to FIG. 8 may be described with reference to the hierarchical structure in FIG. 9 .
  • the first conductive layer ECL1 located in the peripheral area PA and the source-drain electrodes SE/DE in the display area AA are arranged in the same layer, that is, the first Both the conductive layer ECL1 and the source-drain electrodes SE/DE are located on the interlayer insulating layer IL.
  • the second conductive portion Z2C2 of the second conductive connection line Z2 may also be formed at the same time as the source-drain electrodes SE/DE are formed, thereby simplifying the manufacturing process of the second conductive connection line Z2.
  • the second conductive layer ECL2 located in the peripheral area PA can be arranged on the same layer as the gate GE in the display area AA, that is, the second conductive layer ECL2 and the gate GE are all located on the base substrate SUB.
  • the second group of contact pads P2 and the second group of leads W2 located on the second conductive layer ECL1 can be formed simultaneously with the formation of the gate GE, thereby simplifying the manufacturing process.
  • first conductive portion Z2C1 of the first conductive connection line Z1 and the second conductive connection line Z2 may also be formed while forming the gate GE, thereby simplifying the manufacturing process of the conductive connection lines Z1 and Z2 .
  • the source-drain electrodes SE/DE are located on the side of the gate GE away from the substrate SUB.
  • the first conductive layer ECL1 is located on a side of the second conductive layer ECL2 away from the base substrate SUB.
  • the first conductive layer ECL1 and the source-drain electrodes SE/DE are set in the same layer and the same material, and the second conductive layer ECL2 and the gate GE are set in the same layer and the same material.
  • “same layer and same material” means that two functional layers (for example, the second conductive layer ECL2 and the gate GE) are formed in the same layer and the same material in the hierarchical structure of the display substrate.
  • the two functional layers can be formed from the same material layer, and the required pattern and structure can be formed through the same patterning process, for example, the material layer can be formed through a patterning process after the material layer is formed first.
  • the first conductive pattern EDP1 in FIG. 3, the second conductive pattern EDP2 in FIG. 5, and the transfer conductive pattern DWP in FIG. 6 can be of the same layer and material as the common electrode CE in FIG. .
  • FIG. 10 is a schematic diagram of a partially enlarged structure of a region N of the display substrate in FIG. 1 .
  • the display substrate 100 further includes a dummy pixel array area DPA located in the display area AA and close to the peripheral area PA, such as the peripheral transition area PTA.
  • a dummy pixel array area DPA located in the display area AA and close to the peripheral area PA, such as the peripheral transition area PTA.
  • the peripheral area PA such as the peripheral transition area PTA.
  • two adjacent gate lines GL intersect with multiple first data lines DL1 and multiple second data lines DL2 to form multiple dummy pixel areas, and each dummy pixel area
  • a dummy pixel DP is set in .
  • a plurality of dummy pixels DP are arranged in an array to form a dummy pixel array.
  • the dummy pixel DP may have the same or different structure as that of the display pixel PX.
  • the structures of the dummy pixel DP and the display pixel PX are the same, it is more favorable for the dummy pixel DP to simulate the working state of the display pixel PX, so that it is more favorable for static electricity to be released from the dummy pixel DP, that is, breakdown occurs at the dummy pixel DP.
  • the dummy pixel DP has the same structure as the display pixel PX shown in FIG. 9 .
  • each dummy pixel DP is electrically connected to the lead wire W, so that when static electricity is introduced from the lead wire W into the display area, the static charge can be discharged through the dummy pixel DP first, thereby avoiding the discharge of static electricity at the display pixel PX. .
  • the plurality of dummy pixels DP are arranged in at least one row along at least part of the periphery of the display pixel array.
  • the inventors have found that the location of poor display (for example, poor bright spots) in the display area AA is usually in the row of display pixels closest to the peripheral area PA in the display pixel array. Direct contact between two objects with different electrostatic levels will cause the electrostatic charges of the two objects to be displaced. When the electrostatic electric field reaches a certain energy, the two objects will be broken down and discharge. This is the process of electrostatic discharge.
  • the dummy pixels DP can simulate the working state of the display pixels PX, and electrostatic charges are more likely to generate electrostatic contact at a distance
  • the dummy pixel DP closer to the pad is released, and the first dummy thin film transistor in the dummy pixel DP is broken down, so that the display pixel PX in the display area can be protected, thereby avoiding defective display.
  • a row of dummy pixels DP is arranged along the outer periphery of the lower side of the display pixel array formed by a plurality of display pixels PX, and the plurality of dummy pixels DP are arranged along the second direction R2.
  • the dummy pixels DP can also be arranged in multiple rows, so that when static electricity is introduced from the lead W into the display area, static charges can be discharged through two or more dummy pixels DP. Therefore, the embodiments of the present disclosure do not specifically limit the number of virtual pixels DP and the number of rows.
  • FIG. 1 only shows a row of dummy pixels DP arranged along the periphery of the lower side of the display pixel array. It can be understood that a row of dummy pixels DP can also be arranged along the periphery of the left, right and upper sides of the display pixel array. or multiple rows of dummy pixels DP. For example, in one example, a column of dummy pixel settings can also be arranged along the periphery of the left side of the display pixel array, so that static electricity entering the display area from another peripheral bonding area on the left side of the display area AA can be effectively released.
  • FIG. 11 is a schematic cross-sectional view along line C-C of Fig. 10 .
  • FIG. 12 is a schematic cross-sectional view along line D-D of FIG. 10 .
  • Fig. 13 is a schematic cross-sectional view along line E-E of Fig. 10 .
  • each dummy pixel DP includes a dummy pixel driving circuit formed on the substrate SUB, a dummy pixel electrode PE1 (ie, the first dummy electrode), a passivation layer PVX, a dummy common electrode CE1 (ie the second dummy electrode).
  • the dummy pixel driving circuit includes a first dummy thin film transistor D-TFT1, and the first dummy thin film transistor D-TFT1 has exactly the same structure as the thin film transistor TFT shown in FIG. 9 .
  • the first dummy thin film transistor D-TFT1 is also a bottom-gate TFT.
  • the first dummy thin film transistor D-TFT1 may have the same or different structure as that of the thin film transistor TFT in the display pixel PX.
  • the structure of the first dummy thin film transistor D-TFT1 is the same as that of the thin film transistor TFT in the display pixel PX, it is more beneficial for the first dummy thin film transistor D-TFT1 to simulate the working state of the thin film transistor TFT in the display pixel PX, so that the second A dummy thin film transistor D-TFT1 is more likely to be broken down, which is more conducive to the discharge of static electricity from the first dummy pixel DP.
  • the first dummy thin film transistor D-TFT1 has the same structure as the thin film transistor TFT shown in FIG. 9 .
  • the first dummy thin film transistor D-TFT1 by making the first dummy thin film transistor D-TFT1 have the same structure as the thin film transistor TFT, the first dummy thin film transistor D-TFT1 can completely simulate the structure of the display pixel PX, which is more beneficial in the first dummy TFT.
  • the thin film transistor D-TFT1 is released, so as to avoid display defects caused by static electricity introduced into the display pixel PX in the display area.
  • the first dummy thin film transistor D-TFT1 includes: a first dummy gate GE1, a first dummy active layer AT1, a first dummy source-drain electrode SE1/DE1 and an interlayer insulating layer IL.
  • the first dummy gate GE1 is arranged on the same layer as the gate line GL, and the first dummy source-drain electrode SE1/DE1 is arranged on the same layer as the first data line DL1.
  • the interlayer insulating layer IL is located between the first dummy gate GE1 and the first dummy source-drain electrode SE1/DE1 in the third direction R3, for example, between the first dummy gate GE1 and the first dummy electrode SE1/DE1. Between source layers AT1.
  • the first dummy source-drain electrodes SE1/DE1 are located on a side of the first dummy active layer AT1 away from the first dummy gate GE1.
  • the dummy pixel electrode PE1 is located on the side of the interlayer insulating layer IL away from the substrate SUB, and is connected to the first dummy source-drain electrode SE1/DE1 and the first data line DL1.
  • the first data line DL1 is electrically connected to the first dummy source SE1 of the first dummy thin film transistor D-TFT
  • the dummy pixel electrode PE1 is electrically connected to the first dummy drain DE1, so that the first data line
  • the data line signal in DL1 is loaded on the dummy pixel electrode PE1.
  • the dummy pixel electrode PE1 is electrically connected to the first data line DL1 through the first dummy drain electrode DE1
  • the first dummy source electrode SE1 will Conducting with the first dummy drain electrode DE1
  • static electricity can be released from the dummy pixel electrode PE1, thereby preventing static electricity from entering the display pixels PX in the display area AA.
  • the control signal can normally be input to the first group of first lead wires W1 and the first data line DL1 through the first group of contact pads P1 .
  • the passivation layer PVX is located on the side of the dummy pixel electrode PE1 away from the substrate SUB, and the dummy common electrode CE1 is located on the side of the passivation layer PVX away from the dummy pixel electrode PE1, thus, the virtual The pixel electrode PE1 and the dummy common electrode CE1 are insulated from each other by the passivation layer PVX.
  • the dummy pixel DP may or may not emit light.
  • the dummy pixel electrode PE1 and the dummy common electrode CE1 overlap each other in a direction perpendicular to the substrate SUB, and when a voltage is applied between the dummy pixel electrode PE1 and the dummy common electrode CE1, a lateral direction is formed between them.
  • An electric field the transverse electric field acts on the liquid crystal molecules in the liquid crystal layer LC, causing the liquid crystal molecules to deflect to a certain extent.
  • the dummy pixel electrode PE1 is a plate-shaped electrode
  • the dummy common electrode CE1 is a slit-shaped electrode, including a plurality of slit-shaped electrodes.
  • the dummy pixel electrode PE1 includes a plate-shaped first dummy sub-electrode PE11 and a plate-shaped second dummy sub-electrode PE12, the first dummy sub-electrode PE11 and the The second dummy sub-electrodes PE12 are arranged at intervals in the first direction R1 and are insulated from each other.
  • the second dummy sub-electrode PE12 is located on a side of the first dummy sub-electrode PE11 close to the display area AA.
  • the first dummy sub-electrode is electrically connected to the first dummy drain DE1, and the second dummy sub-electrode PE12 is not electrically connected to any conductive structure.
  • the second dummy sub-electrode PE12 by dividing the dummy pixel electrode into the first dummy sub-electrode PE11 and the second dummy sub-electrode PE12 that are independent of each other, when the first dummy sub-electrode PE11 discharges static electricity, since the dummy pixel electrode closer to the display area AA
  • the second dummy sub-electrode PE12 is insulated from the first dummy sub-electrode PE11.
  • the first dummy sub-electrode PE11 discharges static electricity, it is difficult for the static electricity to be conducted to the second dummy sub-electrode PE12, so it is even more difficult to transfer the static electricity to the display pixel PX.
  • the second dummy sub-electrode PE12 can protect the display pixel PX.
  • the dummy pixel electrode PE1 can also be set as a slit-shaped electrode, and the dummy common electrode CE1 can be set as a plate-shaped electrode, which is not limited in this embodiment of the present disclosure.
  • the dummy pixel electrode PE1 and the pixel electrode PE may be set in the same layer and material, and the dummy common electrode CE1 and the common electrode CE may be set in the same layer and material.
  • the first dummy source-drain electrodes SE1/DE1 and the source-drain electrodes SE/DE may be set in the same layer and the same material.
  • the first dummy gate GE1 and the gate GE may be set in the same layer and the same material.
  • the first dummy active layer AT1 and the active layer AT may be set in the same layer and the same material. In this way, the dummy pixel DP can be formed while the display pixel PX is formed, thereby simplifying the manufacturing process and reducing process steps.
  • Fig. 14 is a schematic cross-sectional view along line F-F of Fig. 10 .
  • the plurality of dummy pixel array areas DPA further includes a plurality of second dummy thin film transistors D-TFT2 .
  • the display substrate 100 further includes two auxiliary gate lines AGL, and the two auxiliary gate lines AGL and the gate lines GL are parallel to each other. Two adjacent auxiliary gate lines AGL intersect with multiple first data lines DL1 and multiple second data lines DL2 to form multiple dummy thin film transistor regions, and each dummy thin film transistor region is provided with a second dummy thin film transistor D- TFT2.
  • a plurality of second dummy thin film transistors D-TFT2 are arranged in an array.
  • the second dummy thin film transistor D-TFT2 may have the same or different structure as that of the thin film transistor TFT in the display pixel PX.
  • the second dummy thin film transistor D-TFT2 can simulate the working state of the thin film transistor TFT in the display pixel PX, which is more conducive to static electricity released from the second dummy thin film transistor D-TFT2.
  • the second dummy thin film transistor D-TFT2 may have the same structure as the thin film transistor TFT of the display pixel PX, for example, the structure of the TFT shown in FIG. 9 .
  • each second dummy thin film transistor D-TFT2 is electrically connected to the lead W, so that when the static electricity generated on the contact pad is introduced into the display area from the lead W, since the distance between the second dummy thin film transistor D-TFT2 and the dummy pixel DP is The contact pads that generate static electricity are closer, and all or most of the static charges can be released through the second dummy thin film transistor D-TFT2 first, so that the second dummy thin film transistor D-TFT2 is broken down. If there is still a small amount of static charge, it can also be discharged through the dummy pixel DP.
  • a plurality of second dummy thin film transistors D-TFT2 are located on a side of the plurality of dummy pixels DP away from the display area AA.
  • the plurality of second dummy thin film transistors D-TFT2 are arranged in at least one row along at least part of the periphery of the dummy pixel array.
  • two rows of second dummy thin film transistors D-TFT2 are arranged along the periphery of the lower side of the dummy pixel array composed of a plurality of dummy display pixels DP, thereby increasing the probability of electrostatic discharge. Therefore, the embodiment of the present disclosure does not specifically limit the quantity and the number of rows of the second dummy thin film transistors D-TFT2.
  • the second dummy pixel DP can be set on the side away from the display area AA.
  • dummy thin film transistor D-TFT2 and connect the second dummy thin film transistor D-TFT2 to the same signal line as the dummy pixel DP, so that when the static electricity is introduced from the lead connected to the signal line, it is more conducive to the static electricity on the second dummy pixel DP.
  • the thin film transistor D-TFT2 is released.
  • each of the second dummy thin film transistors D-TFT2 includes a second dummy gate GE2 , a second dummy active layer AT2 , and a second dummy source-drain electrode SE2 / DE2 .
  • the second dummy gate GE2 and the auxiliary gate line AGL are arranged in the same layer and the same material and are electrically connected to each other.
  • the auxiliary gate line AGL is configured to provide a gate signal to the second dummy gate GE2.
  • the second virtual source SE2 is electrically connected to the first data line DL1.
  • the second dummy source-drain electrodes SE2/DE2 and the first dummy source-drain electrodes SE1/DE1 can be set in the same layer and the same material.
  • the second dummy gate GE2 and the first dummy gate GE1 may be set in the same layer and the same material.
  • the second dummy active layer AT2 and the first dummy active layer AT1 may be set to be the same layer and material. In this way, the second dummy thin film transistor D-TFT2 can be formed at the same time as the first dummy thin film transistor D-TFT1 is formed, thereby simplifying the manufacturing process and reducing process steps.
  • FIG. 15 is a schematic structural diagram of a peripheral bonding region of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate 100 is further provided with a plurality of input contact pads located in the peripheral bonding area PBA, and the driving chip IC is bonded in the peripheral bonding area PBA.
  • the plurality of input contact pads includes at least two groups of input contact pads, and the at least two groups of input contact pads include a first group of input contact pads INP1 and a second group of input contact pads INP2.
  • the first group of input contact pads INP1 is configured to receive external signals provided by an external circuit (such as a flexible printed circuit board FPC), and the external signals include but not limited to power supply voltage, common voltage, ground and the like.
  • the first conductive connection line Z1 and the second conductive connection line Z2 are electrically connected between the first set of input contact pads INP1 and the second set of input contact pads INP2 and are configured to connect the first set of input contact pads INP1 The received external signal is transmitted to the second set of input contact pads INP2.
  • the second group of input contact pads INP2 is configured to transmit the external signal to the driving chip IC.
  • the plurality of contact pads P are electrically connected to the driver chip IC and used as output contact pads of the driver chip IC, the driver chip IC provides control signals to the plurality of contact pads P, and then through the plurality of contact pads P Control signals are supplied to the respective signal lines in the display area AA.
  • a conductive connection line such as the first conductive connection line Z1 or the second conductive connection line Z2 between the first group of input contact pads INP1 and the second group of input contact pads INP2
  • the second group of input contact pads INP2 includes a plurality of first input contact pads CP1 and a plurality of second input contact pads CP2 disposed on the same side edge of the peripheral bonding area PBA and arranged at intervals.
  • the first set of input contact pads INP1 includes a plurality of third input contact pads CP3.
  • the first conductive connection line Z1 includes a first connection portion Z101, and the first connection portion Z101 is electrically connected between the third input contact pad CP3 and the first input contact pad CP1, and is used for connecting external signals (such as power supply voltage signals) to From the third input contact pad CP3 to the first input contact pad CP1.
  • external signals such as power supply voltage signals
  • the first conductive connection line Z1 further includes a second connection portion Z102, and the second connection portion Z102 is electrically connected to the first input contact pad CP1 and the second input contact pad CP2, for connecting the first input contact pad CP1 to The supply voltage signal on is transmitted to the second input contact pad CP2.
  • the second connecting portion Z102 is provided to realize signal transmission between the first input contact pad CP1 and the second input contact pad CP2 while keeping the signals on the two first input contact pads CP1 consistent.
  • the first conductive connection line Z1 further includes a third connection portion Z103, which is electrically connected between the two first input contact pads CP1, and is used to realize signal connection between the two first input contact pads CP1. transmission.
  • a third connection portion Z103 which is electrically connected between the two first input contact pads CP1, and is used to realize signal connection between the two first input contact pads CP1. transmission.
  • the stability and consistency of signals on the two first input contact pads CP1 can be ensured.
  • by disposing the third connection portion Z103 and the first connection portion Z101 (and the second connection portion Z102 ) respectively on opposite sides of the plurality of first input contact pads CP1 along the first direction R1 can improve the space utilization rate on the display substrate.
  • the second conductive connection line Z2 is used to transmit external signals different from the first conductive connection line Z1 , for example, to transmit a ground signal.
  • the second conductive connection line Z2 includes a first connection portion Z201.
  • the first connection part Z201 is electrically connected between the third input contact pad CP3 and the first input contact pad CP1 for transmitting the ground signal from the third input contact pad CP3 to the first input contact pad CP1 .
  • the second conductive connection line Z2 further includes a second connection portion Z202, and the second connection portion Z202 is electrically connected between the first input contact pad CP1 and the second input contact pad CP2 for A ground signal is transmitted from the first input contact pad CP1 to the second input contact pad CP2.
  • the second connection part Z202 by setting the second connection part Z202, signal transmission can be realized between the first input contact pad CP1 and the second input contact pad CP2 while maintaining the signal on the first input contact pad CP1 and the second input contact pad CP2. The signals agree.
  • the second conductive connection line Z2 further includes a third connection portion Z203, which is electrically connected between the first input contact pad CP1 and the second input contact pad CP2 (such as the three first input pads shown in the figure).
  • the contact pad CP1 and the two second input contact pads CP2 ) are used to implement signal transmission between these input contact pads, so as to ensure the stability and consistency of signals on these input contact pads.
  • the third connecting portion Z203 and the first connecting portion Z201 (and the second connecting portion Z202) on opposite sides of the plurality of first input contact pads CP1 along the first direction R1 respectively, it is possible to Improve the utilization of space on the display substrate.
  • the stability of signal transmission can also be achieved without increasing the width of the lower frame of the display substrate.
  • the first group of contact pads P1 and the second group of contact pads P2 all need to be bonded to the driver chip IC, in order to reduce the frame size, the first group of contact pads P1,
  • the distance between the second contact pad P2 and the first conductive connection line Z1 and the second conductive connection line Z2 is relatively short, and the design of the embodiment of the present disclosure can avoid static electricity caused by too close a distance between the connection line and the contact pad. Bad display.
  • the routing manner of the first conductive connection line Z1 and the second conductive connection line Z2 in the peripheral area is related to the layout of multiple input contact pads.
  • the routing of the first conductive connection line Z1 and the second conductive connection line Z2 shown in Figure 15 is only schematic, and those skilled in the art can design the first conductive connection line Z1 and the second conductive connection line according to actual needs. Other routing manners of the line Z2 are not limited in this embodiment of the present disclosure.
  • FIG. 16 is a simplified schematic cross-sectional view of a peripheral bonding region of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate includes a display side
  • the peripheral bonding area PBA includes a first surface SF1 on the display side and a second surface SF2 opposite to the display side.
  • a plurality of contact pads P, a plurality of input contact pads INP, a first conductive connection line Z1 , a second conductive connection line Z2 and the driving chip IC are all located on the first surface SF1 .
  • FIG. 16 shows only the driver chip IC.
  • FIG. 17 is a flowchart of a method for manufacturing a display substrate provided by an embodiment of the present disclosure.
  • at least one embodiment of the present disclosure further provides a method for manufacturing the display substrate 100 shown in FIG. 1 , including:
  • S100 Form a plurality of data lines D, a plurality of contact pads P and at least two conductive connection lines Z1, Z2.
  • the plurality of data lines D are located in the display area AA of the display substrate 100 and are configured to provide signals to the display area AA, and the plurality of contact pads P are located in the peripheral area PA of the display substrate and connected to the plurality of contact pads P.
  • a data line D is electrically connected, the at least two conductive connection lines Z1, Z2 are located in the peripheral area PA and located on the side of the plurality of contact pads P away from the display area AA, the at least two The conductive connecting wires Z1 and Z2 are arranged at intervals and insulated from each other.
  • the first group of contact pads P1 among the plurality of contact pads P is located on the first conductive layer ECL1
  • the first conductive connection line Z1 is located on the second conductive layer ECL2
  • the two conductive layers ECL2 are set as different layers.
  • the first group of contact pads P1 and the first conductive connection line Z1 closest to the first group of contact pads P1 are respectively arranged on two conductive wires of different layers. layer, it can avoid the formation of a sharp electric field between the first group of contact pads P1 and the first conductive connection line Z1, thereby preventing electrostatic discharge and conduction, and reducing or even eliminating display defects in the display area.
  • the above manufacturing method may also include:
  • S200 Form a plurality of leads W, the plurality of leads W are located in the peripheral transition area PTA of the peripheral area PA, one end of each lead W is electrically connected to the data line D, and the other end is electrically connected to the contact pad P .
  • the first group of data lines DL1 among the plurality of data lines D, the first group of lead wires W1 among the plurality of lead wires W, and the first group of contact pads P1 are all located on the first conductive layer ECL2 and One piece.
  • the first conductive material layer is formed first, and then the first conductive material layer is patterned by a patterning process to simultaneously form the first group of data lines DL1 , the first group of lead wires W1 and the first group of contact pads P1 .
  • the manufacturing process of the first group of data lines DL1, the first group of lead wires W1 and the first group of contact pads P1 can be simplified.
  • the second group of data lines DL2 among the plurality of data lines D is located on the first conductive layer ECL1
  • Two groups of second contact pads P2 are located in the second conductive layer ECL2 and integrally formed.
  • the second conductive material layer is formed first, and then the second conductive material layer is patterned through a patterning process to simultaneously form the second group of lead wires W2 and the second group of second contact pads P2, thereby simplifying the second group of contact pads P2.
  • the first conductive material layer and the second conductive material layer may include metal materials or alloy materials, such as metal single-layer or multi-layer structures formed by molybdenum, aluminum, titanium, etc., and the first conductive material layer and the second conductive material layer
  • the materials of the material layers may be the same or different.
  • At least part of the contact pads and the first conductive connection line closest to the at least part of the contact pads are respectively arranged in two conductive layers of different layers In this way, it is possible to avoid the formation of a pointed electric field between at least part of the contact pad and the first conductive connection line, thereby preventing electrostatic discharge and conduction, and reducing or even eliminating display defects in the display area.
  • by setting dummy pixels when static electricity is introduced into the display area from the lead wires, the static electricity can be discharged through the dummy pixels first, thereby avoiding the discharge of static electricity at the display pixels.
  • the static charge can be discharged through the second dummy thin film transistor first, thereby further avoiding discharge of static electricity at the display pixel.

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Abstract

一种显示基板及制造方法和显示装置。显示基板(100)包括：显示区(AA)和周边区(PA)；还包括：多个信号线(DL)，配置为向显示区(AA)提供信号；多个接触垫(P)，配置为与多个信号线(DL)电连接；至少两个导电连接线(Z1、Z2)位于多个接触垫(P)远离显示区(AA)的一侧，至少两个导电连接线(Z1、Z2)包括在从显示区(AA)指向周边区(PA)的第一方向(R1)上最靠近多个接触垫(P)的第一导电连接线(Z1)；至少部分多个接触垫(P)位于第一导电层(ECL1)，第一导电连接线(Z1)位于第二导电层(ECL2)，第一导电层(ECL1)和第二导电层(ECL2)设置为不同层。显示基板(100)可避免在至少部分接触垫(P)和第一导电连接线(Z1)之间形成尖端电场，由此阻止静电释放。

Description

显示基板及其制造方法和显示装置 技术领域
本公开实施例涉及一种显示基板及其制造方法和显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)具有体积小、功耗低、无辐射等特点，在当前的平板显示器市场中占据了主导地位。
薄膜晶体管液晶显示器按照显示模式可以分为：扭曲向列(Twisted Nematic，TN)型，平面转换(In Plane Switching，IPS)型和高级超维场开关(Advanced Super Dimension Switch，ADS)型。针对不同应用，ADS技术的改进技术有高透过率I-ADS技术、高开口率H-ADS和高分辨率S-ADS技术等。
发明内容
本公开实施例提供一种显示基板及其制造方法和显示装置。
根据本公开的第一方面，提供一种显示基板，包括：显示区和位于所述显示区至少一侧的周边区，所述显示基板还包括：多个信号线，位于所述显示区中，配置为向所述显示区提供信号；多个接触垫，位于所述周边区中，配置为与所述多个信号线电连接；至少两个导电连接线，位于所述周边区中并且位于所述多个接触垫远离所述显示区的一侧，所述至少两个导电连接线间隔排布，所述至少两个导电连接线包括在从所述显示区指向所述周边区的第一方向上最靠近所述多个接触垫的第一导电连接线；其中，至少部分所述多个接触垫位于第一导电层，所述第一导电连接线位于第二导电层，所述第一导电层和所述第二导电层设置为不同层。
至少一些实施例中，所述多个接触垫包括第一组接触垫和第二组接触垫，所述第一组接触垫与所述第二组接触垫沿所述第一方向错开一定距离并且所 述第二组接触垫比所述第一组接触垫更远离所述第一导电连接线；所述第一组接触垫位于所述第一导电层。
至少一些实施例中，所述第一组接触垫与所述第二组接触垫之间沿所述第一方向错开x个接触垫的位置，其中0.5≤x≤1.5；所述第一组接触垫与所述第二组接触垫在垂直于所述显示基板的方向上与所述至少两个导电连接线均不交叠。
至少一些实施例中，所述周边区包括周边邦定区和位于所述周边邦定区和所述显示区之间的周边过渡区。所述显示基板还包括：多个引线，位于所述周边过渡区中，与所述多个信号线连接；所述多个接触垫位于所述周边邦定区中并且与所述多个引线连接；所述多个信号线包括第一组信号线和第二组信号线，所述多个引线包括第一组引线和第二组引线；所述第一组引线在靠近所述第一组信号线的一侧与所述第一组信号线连接并且在靠近所述第一组接触垫的一侧与所述第一组接触垫连接。所述第一组信号线、所述第一组引线和所述第一组接触垫均位于所述第一导电层。
至少一些实施例中，所述第二组引线在靠近所述第二组信号线的一侧与所述第二组信号线连接并且在靠近所述第二组接触垫的一侧与所述第二组接触垫连接；所述第二组信号线位于所述第一导电层，所述第二组引线和所述第二组接触垫位于所述第二导电层。
至少一些实施例中，所述显示基板还包括：衬底基板；和位于所述衬底基板上的显示像素阵列，所述显示像素阵列位于所述显示区中，所述显示像素阵列包括：显示像素驱动电路、第一显示电极、钝化层和第二显示电极，所述第一显示电极和所述第二显示电极配置为产生电场。所述显示像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括：栅极、源漏电极和层间绝缘层，所述层间绝缘层在垂直于所述衬底基板的方向上位于所述栅极和所述源漏电极之间；所述第一显示电极与所述源漏电极同层设置，所述第一显示电极与所述源漏电极电连接；所述钝化层位于所述第一显示电极的远离所述衬底基板的一侧；所述第二显示电极位于所述钝化层的远离所述第一显示电极的一侧。所述第一导电层和所述第二导电层之一与所述栅极同层设置，所述第一导电层和所述第二导电层中的另一个与所述源漏电极同层设置。
至少一些实施例中，所述源漏电极位于所述栅极的远离所述衬底基板的 一侧；所述第一导电层位于所述第二导电层的远离所述衬底基板的一侧；所述第一导电层与所述源漏电极设置为同层同材料，所述第二导电层与所述栅极设置为同层同材料。
至少一些实施例中，所述钝化层、所述层间绝缘层还延伸到所述周边区，所述层间绝缘层位于所述第二组引线的远离所述衬底基板的一侧，所述第二组信号线位于所述层间绝缘层的远离所述第二组引线的一侧，所述钝化层位于所述第二组信号线和所述层间绝缘层的远离所述衬底基板的一侧。所述周边过渡区还设置有第一过孔、第二过孔和转接导电图案，所述第一过孔贯穿所述钝化层以暴露所述第二组信号线中的至少一个信号线，所述第二过孔贯穿所述钝化层和所述层间绝缘层以暴露所述第二组引线中与所述至少一个信号线对应的至少一个引线，所述转接导电图案覆盖所述第一过孔和所述第二过孔以电连接所述至少一个信号线和所述至少一个引线。
至少一些实施例中，所述至少两个导电连接线还包括：第二导电连接线，位于所述第一导电连接线远离所述多个接触垫的一侧，所述第二导电连接线位于所述第一导电层和所述第二导电层中的至少一层。
至少一些实施例中，所述第一导电连接线和所述第二导电连接线配置为传输外部电路提供的信号。
至少一些实施例中，所述显示基板还包括：衬底基板；位于所述衬底基板上的显示像素阵列，所述显示像素阵列位于所述显示区中；和位于所述衬底基板上的虚拟像素阵列区，所述虚拟像素阵列区包括多个虚拟像素，所述多个虚拟像素沿所述显示像素阵列的至少部分外周排布为至少一排。每个所述虚拟像素配置为与所述多个接触垫之一电连接。
至少一些实施例中，所述虚拟像素包括虚拟像素驱动电路、第一虚拟电极和第二虚拟电极，所述虚拟像素驱动电路包括第一虚拟薄膜晶体管，所述第一虚拟薄膜晶体管包括：第一虚拟栅极和第一虚拟源漏电极；所述第一虚拟电极与所述第一虚拟源漏电极同层设置；所述第二虚拟电极位于所述第一虚拟电极的远离所述衬底基板的一侧并且与所述第一虚拟电极间隔设置；所述第一虚拟电极配置为与所述第一虚拟源漏电极电连接，所述第一虚拟源漏电极配置为与所述多个引线之一电连接。
至少一些实施例中，所述第一虚拟电极包括第一虚拟子电极和第二虚拟 子电极，所述第一虚拟子电极和所述第二虚拟子电极在所述第一方向上间隔设置且彼此绝缘；所述第二虚拟子电极位于所述第一虚拟子电极的靠近所述显示区的一侧。
至少一些实施例中，所述第一虚拟电极和所述第二虚拟电极之一为虚拟像素电极，另一个为虚拟公共电极，所述虚拟像素电极和所述虚拟公共电极在垂直于所述衬底基板的方向上相互交叠；所述虚拟像素电极为板状电极，所述虚拟公共电极为狭缝状电极。
至少一些实施例中，所述虚拟像素阵列区还包括：多个第二虚拟薄膜晶体管，位于所述多个虚拟像素的远离所述显示区的一侧，所述多个第二虚拟薄膜晶体管沿所述虚拟像素阵列的至少部分外周排布为至少一排。每个所述第二虚拟薄膜晶体管包括：第二虚拟栅极和第二虚拟源漏电极，所述第二虚拟源漏电极配置为与所述多个引线之一电连接。
至少一些实施例中，至少部分所述多个接触垫中的每个沿所述第一方向延伸，每个所述导电连接线的至少一部分的延伸方向与所述第一方向相互交叉。
至少一些实施例中，所述第一导电连接线与至少部分所述多个接触垫在所述第一方向上的最小第一间距为大于或等于10微米。
至少一些实施例中，每个所述导电连接线的至少一部分的延伸方向与所述第一方向相互垂直。
至少一些实施例中，所述第一导电连接线与至少部分所述多个接触垫在所述第一方向上的第一间距为大于或等于10微米。
至少一些实施例中，所述第一间距小于所述第一导电连接线的线宽。
至少一些实施例中，所述显示基板还包括设置在所述周边区中的多个输入接触垫，所述多个输入接触垫包括至少两组输入接触垫，所述至少两组输入接触垫包括第一组输入接触垫和第二组输入接触垫，每个所述导电连接线电连接于所述第一组输入接触垫和所述第二组输入接触垫之间。所述第一组输入接触垫配置为接收外部电路提供的外部信号；每个所述导电连接线配置为将所述第一组输入接触垫接收的所述外部信号传输给所述第二组输入接触垫。
根据本公开的第二方面，提供一种显示装置，包括上述显示基板。
至少一些实施例中，所述显示装置还包括驱动芯片，所述显示基板还包括 设置在所述周边区中的多个输入接触垫，其中，所述多个输入接触垫包括至少两组输入接触垫，所述至少两组输入接触垫包括第一组输入接触垫和第二组输入接触垫，每个所述导电连接线电连接于所述第一组输入接触垫和所述第二组输入接触垫之间；其中，所述多个接触垫与所述驱动芯片电连接并且用作所述驱动芯片的输出接触垫，所述驱动芯片向所述多个接触垫提供控制信号。
根据本公开的第三方面，提供一种显示基板的制造方法，包括：形成多个信号线、多个接触垫和至少两个导电连接线，其中，所述多个信号线位于显示基板的显示区中并且配置为向所述显示区提供信号，所述多个接触垫位于显示基板的周边区中并且与所述多个信号线电连接，所述至少两个导电连接线，位于所述周边区中并且位于所述多个接触垫远离所述显示区的一侧，所述至少两个导电连接线间隔排布，所述至少两个导电连接线包括在从所述显示区指向所述周边区的第一方向上最靠近所述多个接触垫的第一导电连接线；其中，至少部分所述多个接触垫位于第一导电层，所述第一导电连接线位于第二导电层，所述第一导电层和所述第二导电层设置为不同层。
至少一些实施例中，所述多个接触垫中的第一组接触垫位于所述第一导电层。
至少一些实施例中所述制造方法还包括：形成多个引线，所述多个引线位于所述周边区的周边过渡区中并且与所述多个信号线电连接，所述多个接触垫与所述多个引线电连接；其中，所述多个信号线中的第一组信号线、所述多个引线中的第一组引线和所述第一组接触垫均位于所述第一导电层且一体成型。
至少一些实施例中，所述多个信号线中的第二组信号线位于所述第一导电层，所述多个引线中的第二组引线和所述多个接触垫中的第二组第二接触垫位于所述第二导电层且一体成型。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开实施例提供的显示基板的结构示意图；
图2为图1的显示基板的区域M的局部放大结构示意图；
图3是沿图2的A1-A1线的截面示意图；
图4是沿图2的A2-A2线的截面示意图；
图5是沿图2的B1-B1线的截面示意图；
图6是沿图2的B2-B2线的截面示意图；
图7是沿图2的I-I线的截面示意图；
图8是沿图2的II-II线的截面示意图；
图9为本公开实施例提供的液晶显示装置的局部截面示意图；
图10为图1的显示基板的区域N的局部放大结构示意图；
图11是沿图10的C-C线的截面示意图；
图12是沿图10的D-D线的截面示意图；
图13是沿图10的E-E线的截面示意图；
图14是沿图10的F-F线的截面示意图；
图15为本公开实施例提供的显示基板的周边邦定区的结构示意图；
图16为本公开实施例提供的显示基板的周边邦定区的简化截面示意图；
图17为本公开实施例提供的显示基板的制造方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接， 而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
显示基板的制造过程中，一些特殊的制作工艺有可能导致产生静电。例如，在液晶显示基板的制造过程中，当对液晶显示基板上的取向层进行摩擦取向时，静电会通过摩擦或者由于电荷相互吸引引起电荷的重新分布而形成。发明人发现，当静电被击穿时，上述摩擦产生的静电有可能从非显示区流入显示区，从而导致显示区中发生显示不良，例如，显示不良的表现可以是亮线(例如X亮线)或亮点的不良现象，而且，随着摩擦布使用次数的增多，这种不良发生率呈逐渐增加趋势，从而严重影响显示装置的显示效果。
例如，本公开的显示基板包括周边区，周边区中设置有多个接触垫，显示区中的各个信号线与多个接触垫电连接，并且通过这些多个接触垫与外部电路电连接。周边区中还设置有多个输入接触垫和导电连接线，一部分输入接触垫与外部电路连接，用于接收外部电路提供的信号。导电连接线电连接于一部分输入接触垫和另一部分输入接触垫之间，用于将一部分输入接触垫上的外部信号传输给另一部分输入接触垫。另一部分输入接触垫将外部信号传输给驱动芯片(驱动芯片邦定在周边区中)，驱动芯片再将外部信号提供给多个接触垫并且通过多个接触垫向显示区传输控制信号。
通常，为了显示装置的窄边框设计，需要减少周边区中接触垫和导电连接线之间的间距，使周边区中的布线更紧凑。然而，当接触垫与这些导电连接线离得过近时，摩擦产生的静电可能会在接触垫与导电连接线之间形成尖端电场，导致静电被释放并传导到接触垫上，进而被输送到显示区的信号线上。这样一来，由于静电对信号线上的信号造成干扰，使显示区出现显示不良现象。
另外，在这些信号线从显示区到周边区的路径中，部分信号线会利用转接孔结构实现换层。发明人还发现，当在周边区产生静电时，静电更容易在具有转接孔的信号线上发生击穿(例如在转接孔处发生击穿)，从而更容易对信号线上传输的信号造成不良影响。
为了解决以上至少一个问题，本公开至少一个实施例提供一种显示基板，包括显示区和位于所述显示区至少一侧的周边区。所述显示基板还包括：多个信号线、多个接触垫和至少两个导电连接线。所述多个信号线位于所述显示区 中并且配置为向所述显示区提供信号。所述多个接触垫位于所述周边区中并且与所述多个信号线电连接。所述至少两个导电连接线位于所述周边区中并且位于所述多个接触垫远离所述显示区的一侧。所述至少两个导电连接线间隔排布。所述至少两个导电连接线包括在从所述显示区指向所述周边区的第一方向上最靠近所述多个接触垫的第一导电连接线。所述至少部分所述多个接触垫位于第一导电层，所述第一导电连接线位于第二导电层，所述第一导电层和所述第二导电层设置为不同层。
在本公开至少一个实施例提供的显示基板中，通过将至少部分接触垫与最靠近该至少部分接触垫的第一导电连接线分别设置在不同层的两个导电层中，可避免在至少部分接触垫和第一导电连接线之间形成尖端电场，由此阻止静电释放和导通，减少甚至消除显示区出现的显示不良现象。
在本公开实施例中，“不同层”指的是两个功能层位于显示基板的不同层级，“同层”指的是两个功能层位于显示基板的同一层级。通常，显示基板包括衬底基板和形成在衬底基板上相互堆叠的多层，每一层代表一个层级。
在本公开实施例中，“部件A配置为与部件B电连接”指的是部件A在一定情况下与部件B电连接，不代表部件A始终与部件B电连接。例如，在一些情况下，部件A与部件B电连接，在另一些情况下，部件A与部件B不电连接。
下面通过几个具体的实施例对本公开进行说明。为了保持本公开实施例以下的说明清楚且简明，可省略已知功能和已知部件的详细说明。当本公开实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中可以由相同的参考标号表示。
在本公开的各个附图中，第一方向R1和第二方向R2平行于衬底基板所在平面，第三方向R3垂直于衬底基板SUB所在平面。本公开实施例中，“多个”指的是两个或两个以上。
图1为本公开实施例提供的显示基板的结构示意图。图2为图1的显示基板的区域M的局部放大结构示意图。
如图1所示，例如，本公开至少一实施例提供的显示基板100包括显示区AA和围绕所述显示区AA的周边区PA。显示区AA用于显示图像，周边区PA为非显示区。
例如，所述周边区PA包括位于显示区AA的一侧(例如图中所示下侧)的周边邦定区PBA和位于所述周边邦定区PBA和所述显示区AA之间的周边过渡区PTA。可以理解的是，在显示区AA的其他侧(例如显示区AA的左侧)上同样可以设置周边邦定区PBA和周边过渡区PTA，为了简化目的，图中已省略。
例如，显示基板100包括衬底基板SUB，显示区AA、周边过渡区PTA和周边邦定区PBA均位于衬底基板SUB上，也就是上述每个区域的正投影均位于衬底基板SUB上。显示区AA包括像素阵列以及为像素阵列提供控制信号、数据信号、电压信号等的扫描线(栅线)、数据线、电源线等。
例如，显示基板100包括多个第一信号线和多个第二信号线，第一信号线例如为沿第一方向R1延伸的数据线DL，第二信号线例如为第二方向R2(例如，与第一方向R1相垂直的方向)延伸的栅线GL。多个数据线DL和多个栅线GL相互交叉以限定多个显示像素区，每个显示像素区中设置有显示像素PX。多个显示像素PX以阵列方式排布以形成显示像素阵列。
本公开实施例中，出于简化目的，图1的数据线DL和栅线GL分别示出为直线，可以理解的是，数据线DL和栅线GL可以为折线或曲线，本公开实施例对此不做限制。
栅线GL和数据线DL可延伸或走线到位于显示区AA至少一侧的周边邦定区PBA。例如，周边过渡区PTA中设置有多个引线W，多个数据线DL与多个引线W一一对应地电连接，由此可以与周边邦定区PBA的驱动芯片(未在图1中示出)电连接。多个栅线GL也可以与另外多个引线(未示出)一一对应地电连接，由此可以与位于显示区AA左侧的周边邦定区的另一驱动芯片(未示出)电连接。本公开实施例以数据线DL和位于显示区AA下侧的周边过渡区PTA中的引线W为例进行说明。
例如，周边邦定区PBA位于周边过渡区PTA的远离显示区AA的一侧。周边邦定区PBA用于通过邦定工艺将外部电路与显示基板100电连接。例如，外部电路可以包括柔性电路板等，用于向多个接触垫P提供外部信号。周边邦定区PBA中设置有多个接触垫P，多个接触垫P位于多个引线W的远离显示区AA的一侧并且与多个引线W一一对应地电连接。引线W的一端部延伸至显示区AA与显示区AA中的数据线DL电连接，引线W的另一端部 延伸至周边邦定区PBA与接触垫P电连接。引线W例如与显示区AA中的数据线DL同层形成，由此可以一体形成，或者形成在不同层，由此需要通过二者之间的绝缘层中的转接孔彼此电连接。
例如，周边邦定区PAB中还设置有两个导电连接线Z，用于传输不同外部信号。两个导电连接线Z位于所述多个接触垫P远离所述显示区AA的一侧，二者间隔排布。例如，两个导电连接线Z包括第一导电连接线Z1和第二导电连接线Z2，其中第一导电连接线Z1在从所述显示区AA指向所述周边区PA的第一方向R1上最靠近所述多个接触垫P。第二导电连接线Z2位于第一导电连接线Z1的远离多个接触垫P的一侧。例如，第一导电连接线Z1用于传输工作电压VDD，第二导电连接线Z2用于接地。优选地，第一导电连接线Z1和第二导电连接线Z2相互绝缘。
本实施例中，图1仅示出了两个导电连接线Z1、Z2，可以理解的是，周边邦定区PAB中还可以设置更多个导电连接线，本公开实施例对此不做限制。
本公开实施例中，出于简化目的，以第一方向R1为竖直方向为例进行说明。可以理解的是，术语“从显示区AA指向周边区PA的第一方向”指的是一个朝向，只要是从显示区朝向周边区的方向都包括在第一方向的范畴内，因此，第一方向R1不一定是竖直方向，还可以是与竖直方向倾斜一定角度的斜向方向，甚至是水平方向等。第二方向R2为与第一方向R1相互垂直的方向。
图3是沿图2的A1-A1线的截面示意图。图4是沿图2的A2-A2线的截面示意图。图5是沿图2的B1-B1线的截面示意图。图6是沿图2的B2-B2线的截面示意图。图7是沿图2的I-I线的截面示意图。图8是沿图2的II-II线的截面示意图。
如图1和图2所示，例如，多个接触垫P包括第一组接触垫P1和第二组接触垫P2。第一组接触垫P1包括多个第一接触垫P1，第二组接触垫P2包括多个第二接触垫P2。多个数据线DL包括第一组数据线DL1和第二组数据线DL2。第一组数据线D1包括多个第一数据线D1，第二组数据线D2包括多个第二数据线D2。多个引线W包括第一组引线W1和第二组引线W2。第一组引线W1包括多个第一引线W1，第二组引线W2包括多个第二引线W2。
例如，所述第一组引线W1在靠近所述第一组数据线DL1的一侧与所述第一组数据线DL1电连接并且在靠近所述第一组接触垫P1的一侧与所述第 一组接触垫P1电连接。所述第二组引线W2在靠近所述第二组数据线DL2的一侧与所述第二组数据线DL2电连接并且在靠近所述第二组接触垫P2的一侧与所述第二组接触垫P2电连接。例如，多个第一引线W1的靠近第一数据线D1的多个第一端部(未标出)与多个第一数据线D1一一对应地电连接，并且多个第一引线W1的靠近第一接触垫D1的多个第二端部(未标出)与多个第一接触垫P1一一对应地电连接。多个第二引线W2的靠近第二数据线D2的多个第一端部(未标出)与多个第二数据线D2一一对应地电连接，并且多个第二引线W2的靠近第二接触垫D1的多个第二端部(未标出)与多个第二接触垫P2一一对应地电连接。
本公开实施例中，第一引线W1的第一端部和第二端部以及第二引线W2的第一端部和第二端部是为了更清楚地描述技术特征，在实际产品中，第一引线W1或第二引线W2上并不具有限定第一、第二端部的明显界限。
如图3和图7所示，例如，显示基板100还包括依次位于衬底基板SUB上的、从显示区AA延伸到周边区PA的第一绝缘层(例如层间绝缘层IL)和第二绝缘层(例如钝化层PVX)，还包括位于周边区PA中的第一导电层ECL1和第二导电层ECL2。第一导电层ECL1在垂直于衬底基板SUB方向上位于层间绝缘层IL和钝化层PVX之间，第二导电层ECL2在垂直于衬底基板SUB方向上衬底基板SUB和层间绝缘层IL之间。
例如，第一组接触垫P1位于第一导电层ECL1，第一导电连接线Z1位于第二导电层ECL2。由于所述第一导电层ECL1与衬底基板SUB之间通过层间绝缘层IL相互间隔且绝缘，第一导电层ECL1与衬底基板SUB不直接接触。第二导电层ECL2与衬底基板SUB直接接触。由于第一导电层ECL1和所述第二导电层ECL2位于不同层,第一组接触垫P1和第一导电连接线Z1也位于不同层。
至少一些实施例中，所述多个接触垫中的至少部分接触垫中的每个沿所述第一方向延伸，每个所述导电连接线的至少一部分的延伸方向与所述第一方向相互交叉。例如，多个接触垫P中的每个沿第一方向R1延伸，第一导电连接线Z1的至少一部分沿第二方向R2延伸。通常，在对显示基板上的取向层执行摩擦工艺时，如果多个接触垫P和第一导电连接线Z1设置为同层时，更容易在多个接触垫P和第一导电连接线Z1之间形成尖端电场，从而发生静 电释放并导通。
本实施例中，通过使至少部分接触垫P(即第一组接触垫P1)和第一导电连接线Z1设置为不同层，可避免在第一组接触垫P1和第一导电连接线Z1之间形成尖端电场。这样一来，即使静电在周边邦定区PBA中产生，也能降低被传输到显示区中的风险，由此减少甚至消除显示区出现的显示不良现象。
如图4所示，例如，所述第一数据线DL1和第一引线W1均位于所述第一导电层ECL1，由此，所述第一数据线DL1、第一引线W1和第一接触垫P1均位于所述第一导电层ECL1，即第一组数据线DL1、第一组引线W1和第一组接触垫P1均位于第一导电层ECL1。
通常，在数据线DL从显示区AA延伸到周边邦定区PBA的过程中，如果采用转接孔设计，静电更容易在转接孔处发生击穿，从而更容易对数据线DL上传输的信号造成不良影响。
本实施例中，通过将第一组接触垫P1、以及与该第一组接触垫P1电连接的第一组数据线DL1、第一组引线W1设置为同层，即均位于第一导电层ECL1，使第一组数据线DL1无需经过转接孔与第一组接触垫P1电连接，降低了静电导入有转接孔的数据线的风险，从而消除转接孔被静电打坏的风险。
至少一些实施例中，第二组接触垫P2以及与该第二组接触垫P2电连接的第二组数据线DL2、第二组引线W2可以位于同一导电层(例如第一导电层ECL1或第二导电层ECL2)，也可以位于两个不同导电层。当位于同一导电层时，可简化制造工艺。当位于不同导电层时，信号线利用转接孔结构进行换层设计，可减小信号线或引线在周边区所占的空间，提高周边区的空间利用率。下面以第二组接触垫P2、第二组数据线DL2、第二组引线W2位于不同层为例进行说明。
例如，如图5所示，第二组接触垫P2位于第二导电层ECL2。如图6所示，与第二组接触垫P2电连接的第二组引线W2位于第二导电层ECL2；与第二组引线W2电连接的第二组数据线DL2位于第一导电层ECL1。也就是，第二组接触垫P2和第二组引线W2设置为与第二组数据线DL2不同层。进一步地，例如，在图6所示的周边过渡区PTA中，第二引线W2通过第一过孔VH1、第二过孔VH2以及位于第一过孔VH1、第二过孔VH2中的转接导电图案DWP与第二数据线D2电连接，由此第二组数据线DL2通过诸如第 一过孔VH1、第二过孔VH2的转接孔实现与第二组接触垫P2的电连接。
通常，为了降低多条引线在周边区中占用的空间，会将多个引线之间的间距设计得较窄。当引线之间的间距过近时，可能有信号串扰的问题。尤其在第一引线W1和第二引线W2均位于同一导电层(例如第一导电层ECL1)的情况下，信号串扰问题会更明显。
本实施例中，通过采用转接孔设计，使第二引线W2位于第二导电层ECL2，由于第一导电层ECL1与第二导电层ECL2相互绝缘，即使第一引线W1和第二引线W2之间的间距比较近，也能避免二者的信号串扰问题。这样，在不影响第一引线W1和第二引线W2传输信号的同时，能进一步减小第一引线W1和第二引线W2之间的间距，提高周边区的空间使用率。
本实施例中，通过贯穿钝化层PVX的第一过孔VH1、贯穿钝化层PVX和层间绝缘层IL的第二过孔VH2以及转接导电图案DWP实现第二数据线DL2的换层仅出于示意性目的，在其他实施例中，还可以采用其他转接孔结构实现第二数据线DL2的换层。例如，可以在层间绝缘层IL中形成过孔，该过孔暴露第二引线W2，然后将层间绝缘层IL上的第二数据线DL2形成为覆盖该过孔以与暴露的第二引线W2电连接，因此，本公开实施例对换层结构不做限制。
如图3所示，例如，在钝化层PVX的远离衬底基板SUB的一侧还设置有第一导电图案EDP1。该钝化层PVX覆盖第一接触垫P1的边缘并且设置有第一接触孔CH1。第一导电图案EDP1通过第一接触孔CH1与第一接触垫P1电连接。这样，第一接触垫P1可通过第一导电图案EDP1与外部电路电连接，由此实现信号传输。
如图5所示，例如，在钝化层PVX的远离衬底基板SUB的一侧还设置有第二导电图案EDP2。由钝化层PVX和层间绝缘层IL构成的绝缘层叠层覆盖第二接触垫P2的边缘并且设置有第二接触孔CH2。第二导电图案EDP2通过第二接触孔CH2与第二接触垫P2电连接。这样，第二接触垫P2可通过第二导电图案EDP2与外部电路电连接，由此实现信号传输。
本实施例中，接触垫的边缘包括沿接触垫的外周延伸的边缘。
如图1所示，例如，所述第一组接触垫P1与所述第二组接触垫P2在垂直于所述显示基板的方向上与两个导电连接线Z1、Z2不交叠，并且每一组接 触垫与两个导电连接线Z1、Z2均相互绝缘。此处，“垂直于所述显示基板的方向”指的是垂直于显示基板所在平面的方向，也可以理解为垂直于衬底基板SUB所在平面的方向。换言之，所述第一组接触垫P1与所述第二组接触垫P2在衬底基板SUB上的正投影与两个导电连接线Z1、Z2在衬底基板SUB上的正投影之间不交叠。
例如，第一组接触垫P1与所述第二组接触垫P2均沿所述第一方向R1延伸，并且二者之间错开一定距离，使得第二组接触垫P2比第一组接触垫P1更远离第一导电连接线Z1。术语“错开”指的是第一组接触垫P1中第一接触垫P1的中心点和第二组接触垫P2中的第二接触垫P2的中心点在第二方向R2上不设置在同一直线上。
本实施例中，第二组接触垫P2电连接于具有转接孔结构的第二组数据线DL2，通过将第二组接触垫P2设置为比第一组接触垫P1更远离第一导电连接线Z1，可降低摩擦静电导入到第二组接触垫P2的风险，避免静电破坏第二组数据线DL2上的转接孔结构。
需要说明的是，术语“错开”并不是对第一组接触垫P1在第一方向R1上的长度和第二组接触垫P2在第一方向R1上的长度限定，也不一定是错开一个接触垫的长度。只要第一接触垫P1的中心点和第二接触垫P2的中心点在第二方向R2上不设置在同一直线上即可。例如，如图2所示，沿图2所示的从左向右的第二方向R2观察，第一组接触垫P1和第二组接触垫P2之间不交叠。可以理解的是，在其他实施例中，第一组接触垫P1和第二组接触垫P2之间沿第二方向R2也可以交叠，本公开对此不做限制。
本公开实施例中，第一接触垫P1在第一方向R1上的长度和第二接触垫P2在第一方向R1上的长度可以相同，也可以不同。如图2所示，例如，第一接触垫P1的长度等于第二接触垫P2的长度，并且第一接触垫P1与第二接触垫P2之间沿所述第一方向R1错开至少1个接触垫的位置。在此情况下，不仅可简化制造工艺，还可以避免静电导入到第二接触垫P2中。
图2所示的第一接触垫P1和第二接触垫P2之间的相对位置仅为示意性的，可以理解的是，在其他实施例中，所述第一接触垫P1与所述第二接触垫P2之间沿所述第一方向R1可以错开x个接触垫(第一接触垫P1或第二接触垫P2)的位置，其中0.5≤x≤1.5。
本公开实施例中，第一接触垫P1的数量和第二接触垫P2的数量可以相同，也可以不同；多个第一接触垫P1可以等间距或不等间距设置；多个第二接触垫P2可以等间距或不等间距设置，本公开实施例对此不做限制。
本公开实施例中，出于示意性目的，图2中的第一接触垫P1和第二接触垫P2在第二方向R2上交替设置，也就是，每相邻两个第二接触垫P2之间设置有一个第一接触垫P1。可以理解的是，在其他实施例中，每相邻两个第二接触垫P2之间还可以设置两个、三个或更多个第一接触垫P1；或者，每相邻两个第一接触垫P1之间可以设置两个、三个或更多个第二接触垫P2，本公开对此不做限制。
另外，在本公开其他实施例中，还可以将仅一部分第一接触垫P1和第二接触垫P2设置为交替形式，或者将仅一部分第二接触垫P2和第一接触垫P1设置为交替形式，同样可以实现本发明目的。
如图8所示，例如，第二导电连接线Z2包括位于第一导电层ECL1中的第一导电部Z2C1和位于第二导电层ECL2中的第二导电部Z2C2。第一导电部Z2C1和第二导电部Z2C2在垂直于衬底基板SUB的方向上交叠。
本公开实施例中，在对第一导电连接线和第二导电连接线的阻抗要求相同的情况下，第一导电连接线Z1由于仅设置在一个导电层中，在沿着垂直于第一接触垫P1延伸方向(例如第二方向R2)延伸时，具有较大的线宽，而第二导电连接线Z2由于设置在两个导电层中，在沿着垂直于第一接触垫P1延伸方向(第二方向R2)延伸时，可以具有较小的线宽。本实施例中，通过将第二导电连接线Z2设置为位于第一导电层ECL1和第二导电层ECL2中，可以在保证传输信号不被干扰的情况下，降低第二导电连接线Z2在周边邦定区中所占用的空间。
本公开实施例中，第一导电连接线Z1和第二导电连接线Z2的线宽仅为示意性的，本领域技术人员可以根据实际需要进行设计，本公开实施例对此不做限制。
另外，可以理解的是，本实施例中的第二导电连接线Z2的设置方式仅为示意性的，在其他实施例中，第二导电连接线Z2还可以仅位于第一导电层ECL1或仅位于第二导电层ECL2中，本公开实施例对此不做限制。
如图1和2所示，例如，第一组接触垫P1和第二组接触垫P2沿所述第 一方向R1延伸。至少部分第一导电连接线Z1和至少部分第二导电连接线Z2沿第二方向R2延伸。因此，第一组接触垫P1和第二组接触垫P2的延伸方向与至少部分第一导电连接线Z1和至少部分第二导电连接线Z2的延伸方向之间的夹角等于90度。可以理解的是，上述夹角也可以不是90度，例如大于0度且小于90度，只要至少部分第一导电连接线Z1和至少部分第二导电连接线Z2的延伸方向与第一组接触垫P1和第二组接触垫P2的延伸方向相互交叉即可，本公开对此不做限制。
至少一些实施例中，通过增加第一导电连接线Z1和第二导电连接线Z2与多个接触垫P之间的间距，可进一步避免在多个接触垫P和导电连接线之间形成尖端电场，由此避免静电导入到接触垫P中。
例如，如图2所示，所述第一导电连接线Z1与第一组接触垫P1在所述第一方向R1上的第一间距L1为大于或等于10微米，可选地，例如大于或等于10微米且小于或等于400微米。在一个示例中，第一间距L1可以为10微米、20微米、30微米、40微米、50微米、60微米、70微米、80微米、90微米或100微米等。所述第二导电连接线Z2与第一组接触垫P1在所述第一方向R1上的第二间距L2大于第一间距L1。通过将第二导电连接线Z2设置为比第一导电连接线Z1更远离第一组接触垫P1，可避免第二导电连接线Z2和第一组接触垫P1之间形成尖端电场，进而降低第二导电连接线Z2上的静电通过第一组接触垫P1进入显示区的可能。
例如，第一间距L1小于第一导电连接线Z1的线宽。第一间距L1小于第一导电连接线Z1的线宽，有利于显示面板实现窄边框。
本实施例中的第一间距L1和第二间距L2以第一导电连接线Z1的延伸方向与第一组接触垫P1的延伸方向相互垂直为例进行说明。可以理解的是，当第一导电连接线Z1的延伸方向与第一组接触垫P1的延伸方向不垂直时，所述第一导电连接线Z1与第一组接触垫P1在所述第一方向R1上具有最小的第一间距L1。该最小的第一间距L1例如为大于或等于10微米，可选地，例如大于或等于10微米且小于或等于400微米。在一个示例中，该最小的第一间距可以为10微米、20微米、30微米、40微米、50微米、60微米、70微米、80微米、90微米或100微米等。例如，所述最小的第一间距L1小于所述第一导电连接线Z1的线宽。
本公开实施例中，衬底基板SUB可以为玻璃板、石英板、金属板或树脂类板件等。例如，衬底基板的材料可以包括有机材料，例如该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料，衬底基板SUB可以为柔性基板或非柔性基板，本公开的实施例对此不作限制。
本公开实施例中，第一绝缘层和第二绝缘层的材料可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对第一绝缘层的材料不做具体限定。
本公开实施例中，引线的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构。第一导电层和第二导电层的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构。
图9为本公开实施例提供的液晶显示装置的局部截面示意图。
如图9所示，例如，该液晶显示装置包括液晶显示面板，该液晶显示面板包括在第三方向R3上相对设置的阵列基板200和对向基板300，以及填充在阵列基板200和对向基板300之间的液晶层LC。阵列基板200和彩膜基板300经对盒(cell-assembly)工艺通过封框胶(未示出)形成封闭的液晶盒，液晶层LC密封在液晶盒内。
例如，阵列基板200包括衬底基板SUB和形成在衬底基板SUB上的在显示像素PX，该显示像素PX包括显示像素驱动电路、像素电极PE(即第一显示电极)、钝化层PVX、公共电极CE(即第二显示电极)和第一取向层PI1。
例如，所述显示像素驱动电路包括薄膜晶体管TFT和存储电容(未示出)等，本公开的实施例对于显示像素驱动电路不做限制。薄膜晶体管TFT可以为顶栅型或底栅型，本公开实施例以底栅型TFT为例进行说明。
例如，所述薄膜晶体管TFT包括：栅极GE、源漏电极SE/DE、有源层AT和层间绝缘层IL。栅极GE与栅线GL同层设置，源漏电极SE/DE与数据线DL同层设置。所述层间绝缘层IL在第三方向R3上位于所述栅极GE和所述源漏电极SE/DE之间，例如位于栅极GE和有源层AT之间。源漏电极SE/DE位于有源层AT的远离栅极GE的一侧并且覆盖有源层AT。可选地， 可以在源漏电极SE/DE的远离衬底基板SUB的一侧设置刻蚀阻挡层，以防止刻蚀工艺对源漏电极SE/DE的损伤。
例如，像素电极PE位于层间绝缘层的远离衬底基板的一侧，并且与所述源漏电极SE/DE同层设置。数据线DL与薄膜晶体管TFT的源极SE电连接，像素电极PE与漏极DE电连接，从而将数据线DL中的数据线信号加载到像素电极PE上。所述钝化层PVX位于像素电极PE的远离所述衬底基板SUB的一侧，公共电极CE位于所述钝化层PVX的远离所述像素电极PE的一侧，由此，像素电极PE和公共电极CE通过钝化层PVX相互绝缘。
当在像素电极PE和公共电极CE之间施加电压时(例如像素电极PE施加数据线电压VData，公共电极CE施加公共电压Vcom)，二者之间形成横向电场，该横向电场作用于液晶层LC中的液晶分子上，使得液晶分子发生一定偏转。
例如，像素电极PE为板状电极，公共电极CE为狭缝状电极，包括多个狭缝状电极。可以理解的是，也可以将像素电极PE设为狭缝状电极，公共电极CE设为板状电极，本公开实施例对此不做限制。
例如，像素电极PE和公共电极CE例如由透明导电材料形成，该透明导电材料包括但不限于透明导电氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)等。
如图9所示，例如，对向基板300包括对向衬底基板SUB’和设置在对向衬底基板SUB’上的彩色滤光层CF、黑矩阵层BM和第二取向层PI2。
例如，彩色滤光层CF可与黑矩阵层BM同层设置，用于将透过液晶层LC的光转变为具有与彩色滤光层CF的颜色对应颜色的光，从而实现彩色显示。彩色滤光层CF包括按阵列布置的滤色单元(例如RGB滤色单元)。彩色滤光单元的材料包括感光树脂。此外，在黑矩阵BM和彩色滤光层CF上还覆盖有平坦化层OC，以将对向基板300的表面平坦化。
例如，黑矩阵层BM用于防止显示像素PX之间的串扰或漏光。例如，薄膜晶体管TFT沿第三方向R3在衬底基板SUB上的正投影落入黑矩阵层BM沿第三方向R3在衬底基板SUB上的正投影中。需要说明的是，彩色滤光层CF也可与黑矩阵层BM不同层设置，本公开实施例对此不做限制。当在阵列基板200上形成有黑矩阵层和彩色滤光层时，则在对向基板300上可不再形 成黑矩阵层和彩色滤光层。黑矩阵层BM的材料包括具有遮光性能的颜料以防止像素之间的漏光。例如，黑矩阵层BM的材料可包括碳(C)或铬(Cr)。
例如，第一取向层PI1和第二取向层PI2在第三方向R3上相对设置，用于对液晶层LC中的液晶分子进行取向。第一取向层PI1位于阵列基板200的公共电极CE的靠近液晶层LC的一侧。第二取向层PI2位于彩膜基板300的平坦化层OC的靠近液晶层的一侧。第一取向层PI1和第二取向层PI2的材料例如为聚酰亚胺。
例如，为了保持均一的液晶盒厚度，在阵列基板200和彩膜基板300之间设置有多个柱状隔垫物SP。柱状隔垫物SP例如由形状记忆高分子材料形成。当隔垫物SP的刚性较大时，能对彩膜基板300起到很好的支撑作用，防止彩膜基板300在外力的作用下发生形变。
本实施例中，液晶显示面板还包括设置在阵列基板200的远离对向基板300一侧的背光模块(未示出)，该背光模块在液晶显示面板的非显示侧，用于为显示提供光源。该背光模块可以为侧面照射型或直下型，所使用的光源可以为冷阴极荧光灯、发光二极管(LED)等，本发明的实施例不限于此。在此实施例中，液晶显示面板可以为透射型或半透半反型。例如，液晶显示面板可以为反射型，由此不需要为该液晶显示面板另外设置背光模块。
图9所示的液晶显示基板可以适用于高级超维场开关(Advanced Super Dimension Switch，ADS)模式的液晶面板或者其变型。
本公开实施例中，图3至图8中所示的位于周边区PA中的衬底基板SUB、层间绝缘层IL和钝化层PVX可以理解为从图9所示的位于显示区AA中的衬底基板SUB、层间绝缘层IL和钝化层PVX延伸到周边区PA中。因此，本公开实施例中，图3至图8中各个功能层的层级结构可参考图9的层级结构进行描述。
如图3至图6、图8、图9所示，例如，位于周边区PA中的所述第一导电层ECL1与显示区AA中的源漏电极SE/DE同层设置，也就是第一导电层ECL1与源漏电极SE/DE均位于层间绝缘层IL上。这样，在制备过程中，可以在形成源漏电极SE/DE的同时形成位于第一导电层ECL1的第一组接触垫P1、第一组数据线DL1、第二组数据线DL2和第一组引线W1，由此简化制造工艺。进一步地，例如，第二导电连接线Z2的第二导电部Z2C2也可以在 形成源漏电极SE/DE的同时形成，由此简化第二导电连接线Z2的制造工艺。
如图5至图8、图9所示，例如，位于周边区PA中的第二导电层ECL2可以与显示区AA中的栅极GE同层设置，也就是第二导电层ECL2与栅极GE均位于衬底基板SUB上。这样，在制备过程中，可以在形成栅极GE的同时形成位于第二导电层ECL1的第二组接触垫P2和第二组引线W2，由此简化制造工艺。进一步地，例如，第一导电连接线Z1和第二导电连接线Z2的第一导电部Z2C1也可以在形成栅极GE的同时形成，由此简化导电连接线Z1和Z2的制造工艺。
例如，如图9所述，所述源漏电极SE/DE位于所述栅极GE的远离衬底基板SUB的一侧。如图3至图8所示，所述第一导电层ECL1位于所述第二导电层ECL2的远离所述衬底基板SUB的一侧。所述第一导电层ECL1与所述源漏电极SE/DE设置为同层同材料，所述第二导电层ECL2与所述栅极GE设置为同层同材料。
在本公开的实施例中，“同层同材料”为两个功能层(例如第二导电层ECL2与所述栅极GE)在显示基板的层级结构中同层且同材料形成，这样，在制备过程中，两个功能层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构，例如可以在先形成该材料层后，由该材料层经过构图工艺形成。
例如，为了简化制造工艺，图3的第一导电图案EDP1、图5的第二导电图案EDP2和图6的转接导电图案DWP可以与图9的公共电极CE同层同材料，以减少工艺步骤。
图10为图1的显示基板的区域N的局部放大结构示意图。
如图1和图10所示，显示基板100还包括位于显示区AA中且靠近周边区PA例如周边过渡区PTA一侧的虚拟像素阵列区DPA。如图10所示，在虚拟像素阵列区中，相邻两条栅线GL与多个第一数据线DL1和多个第二数据线DL2相互交叉形成多个虚拟像素区，每个虚拟像素区中设置有虚拟像素DP。例如，多个虚拟像素DP以阵列方式排布以形成虚拟像素阵列。
本公开实施例中，虚拟像素DP可以具有与显示像素PX相同或不同的结构。当虚拟像素DP和显示像素PX的结构相同时，更有利于虚拟像素DP模拟显示像素PX的工作状态，从而更有利于静电从虚拟像素DP处释放，即在 虚拟像素DP处发生击穿。在一个具体实施例中，例如，虚拟像素DP具有与图9所示的显示像素PX的结构。
本实施例中，每个所述虚拟像素DP与引线W电连接，这样当有静电从引线W导入显示区时，可先通过虚拟像素DP释放静电荷，由此避免在显示像素PX处释放静电。
例如，所述多个虚拟像素DP沿所述显示像素阵列的至少部分外周排布为至少一排。发明人发现，显示区AA中显示不良(例如，亮点不良)的位置通常是在显示像素阵列中最靠近周边区PA的那排显示像素中。两个带不同静电电平的物体之间通过直接接触会使两物体的静电电荷发生位移，当静电电场达到一定能量，两个的物体被击穿而产生放电，这就是静电释放的过程。本实施例中，通过在沿所述显示像素阵列的至少部分外周排布为至少一排虚拟像素DP，可使虚拟像素DP模拟显示像素PX的工作状态，静电电荷更容易在距离产生静电的接触垫更近的虚拟像素DP处释放，虚拟像素DP中的第一虚拟薄膜晶体管被击穿，从而可以保护显示区中的显示像素PX，由此避免发生显示不良现象。
例如，如图1所示，沿多个显示像素PX构成的显示像素阵列的下侧的外周设置有一行虚拟像素DP，多个虚拟像素DP沿第二方向R2排布。可以理解的是，为了提高静电释放的几率，虚拟像素DP也可以设置为多行，这样在静电从引线W导入显示区时，可通过两个或更多个虚拟像素DP释放静电荷。因此，本公开实施例对虚拟像素DP的数量和行数不做具体限制。
出于示意性目的，图1仅示出了沿显示像素阵列下侧的外周设置的一行虚拟像素DP，可以理解的是，还可以沿显示像素阵列左侧、右侧和上侧的外周设置一行或多行虚拟像素DP。例如，一个示例中，还可以沿显示像素阵列左侧的外周设置一列虚拟像素设置，这样，能有效释放从显示区AA左侧的另一周边邦定区中进入显示区的静电。
图11是沿图10的C-C线的截面示意图。图12是沿图10的D-D线的截面示意图。图13是沿图10的E-E线的截面示意图。
如图11至图13所示，例如，每个虚拟像素DP包括形成在衬底基板SUB上的虚拟像素驱动电路、虚拟像素电极PE1(即第一虚拟电极)、钝化层PVX、虚拟公共电极CE1(即第二虚拟电极)。
例如，所述虚拟像素驱动电路包括第一虚拟薄膜晶体管D-TFT1，第一虚拟薄膜晶体管D-TFT1具有与图9所示的薄膜晶体管TFT的完全相同的结构。例如当薄膜晶体管TFT为底栅型TFT时，第一虚拟薄膜晶体管D-TFT1同样为底栅型TFT。
本公开实施例中，第一虚拟薄膜晶体管D-TFT1可以具有与显示像素PX中的薄膜晶体管TFT具有相同或不同的结构。当第一虚拟薄膜晶体管D-TFT1与显示像素PX中的薄膜晶体管TFT的结构相同时，更有利于第一虚拟薄膜晶体管D-TFT1模拟显示像素PX中的薄膜晶体管TFT的工作状态，从而使第一虚拟薄膜晶体管D-TFT1更容易被击穿，从而更有利于静电从第一虚拟像素DP处释放。在一个具体实施例中，例如，第一虚拟薄膜晶体管D-TFT1具有与图9所示的薄膜晶体管TFT的结构。
本公开实施例中，通过使第一虚拟薄膜晶体管D-TFT1具有与薄膜晶体管TFT相同的结构，第一虚拟薄膜晶体管D-TFT1可以完全模拟显示像素PX的构造，这样更有利于在第一虚拟薄膜晶体管D-TFT1处释放，从而避免因静电导入显示区的显示像素PX中引发的显示不良现象。
例如，如图11和图12所示，所述第一虚拟薄膜晶体管D-TFT1包括：第一虚拟栅极GE1、第一虚拟有源层AT1、第一虚拟源漏电极SE1/DE1和层间绝缘层IL。第一虚拟栅极GE1与栅线GL同层设置，第一虚拟源漏电极SE1/DE1与第一数据线DL1同层设置。所述层间绝缘层IL在第三方向R3上位于所述第一虚拟栅极GE1和所述第一虚拟源漏电极SE1/DE1之间，例如位于第一虚拟栅极GE1和第一虚拟有源层AT1之间。第一虚拟源漏电极SE1/DE1位于第一虚拟有源层AT1的远离第一虚拟栅极GE1的一侧。
例如，如图11至图13所示，虚拟像素电极PE1位于层间绝缘层IL的远离衬底基板SUB的一侧，并且与所述第一虚拟源漏电极SE1/DE1和第一数据线DL1同层设置。如图10所示，第一数据线DL1与第一虚拟薄膜晶体管D-TFT的第一虚拟源极SE1电连接，虚拟像素电极PE1与第一虚拟漏极DE1电连接，从而将第一数据线DL1中的数据线信号加载到虚拟像素电极PE1上。
考虑静电导入第一组接触垫P1后，需要找地方释放。由于虚拟像素电极PE1通过第一虚拟漏极DE1与第一数据线DL1电连接，当静电经第一组接触垫P1导入第一组第一引线W1上时，由于静电使第一虚拟源电极SE1和第一 虚拟漏电极DE1之间导通，静电可从虚拟像素电极PE1处得到释放，由此避免静电进入显示区AA的显示像素PX中。之后，当需要给第一数据线DL1提供控制信号时，控制信号可正常经第一组接触垫P1输入到第一组第一引线W1以及第一数据线DL1中。
所述钝化层PVX位于虚拟像素电极PE1的远离所述衬底基板SUB的一侧，虚拟公共电极CE1位于所述钝化层PVX的远离所述虚拟像素电极PE1的一侧，由此，虚拟像素电极PE1和虚拟公共电极CE1通过钝化层PVX相互绝缘。
本实施例中，虚拟像素DP可以发光，也可以不发光。例如，虚拟像素电极PE1和虚拟公共电极CE1在垂直于所述衬底基板SUB的方向上相互交叠，当在虚拟像素电极PE1和虚拟公共电极CE1之间施加电压时，二者之间形成横向电场，该横向电场作用于液晶层LC中的液晶分子上，使得液晶分子发生一定偏转。当经过液晶层LC的光射入到对向基板300时，可以将图9中的黑矩阵层BM配置为遮挡住虚拟像素DP，以使虚拟像素DP的光线被黑矩阵层BM遮挡，由此实现虚拟像素DP不发光，从而避免虚拟像素DP对相邻的显示像素PX的发光造成干扰。
例如，虚拟像素电极PE1为板状电极，虚拟公共电极CE1为狭缝状电极，包括多个狭缝状电极。优选地，如图10和图12所示，所述虚拟像素电极PE1包括板状的第一虚拟子电极PE11和板状的第二虚拟子电极PE12，所述第一虚拟子电极PE11和所述第二虚拟子电极PE12在所述第一方向R1上间隔设置且彼此绝缘。所述第二虚拟子电极PE12位于所述第一虚拟子电极PE11的靠近所述显示区AA的一侧。第一虚拟子电极与第一虚拟漏极DE1电连接，所述第二虚拟子电极PE12不与任何导电结构电连接。
本公开实施例中，通过将虚拟像素电极分成彼此独立的第一虚拟子电极PE11和第二虚拟子电极PE12，在第一虚拟子电极PE11释放静电的情况下，由于更靠近显示区AA的第二虚拟子电极PE12与第一虚拟子电极PE11相互绝缘，当第一虚拟子电极PE11释放静电时，该静电很难传导到第二虚拟子电极PE12上，因此更难传导到显示像素PX上，由此使第二虚拟子电极PE12对显示像素PX起到保护作用。
可以理解的是，也可以将虚拟像素电极PE1设为狭缝状电极，虚拟公共 电极CE1设为板状电极，本公开实施例对此不做限制。
例如，虚拟像素电极PE1可以与像素电极PE设置为同层同材料，虚拟公共电极CE1可以与公共电极CE设置为同层同材料。第一虚拟源漏电极SE1/DE1可以与所述源漏电极SE/DE设置为同层同材料。第一虚拟栅极GE1可以与所述栅极GE设置为同层同材料。第一虚拟有源层AT1可以与有源层AT设置为同层同材料。这样一来，可在形成显示像素PX的同时形成虚拟像素DP，从而简化制造工艺，减少工艺步骤。
图14是沿图10的F-F线的截面示意图。
如图10和图14所示，例如，所述多个虚拟像素阵列区DPA还包括多个第二虚拟薄膜晶体管D-TFT2。如图10所示，显示基板100还包括两条辅助栅线AGL，两条辅助栅线AGL与栅线GL相互平行。相邻两条辅助栅线AGL与多个第一数据线DL1和多个第二数据线DL2相互交叉形成多个虚拟薄膜晶体管区，每个虚拟薄膜晶体管区中设置有第二虚拟薄膜晶体管D-TFT2。例如，多个第二虚拟薄膜晶体管D-TFT2以阵列方式排布。
本公开实施例中，第二虚拟薄膜晶体管D-TFT2可以具有与显示像素PX中的薄膜晶体管TFT具有相同或不同的结构。当第二虚拟薄膜晶体管D-TFT2与显示像素PX中的薄膜晶体管TFT的结构相同时，第二虚拟薄膜晶体管D-TFT2可模拟显示像素PX中的薄膜晶体管TFT的工作状态，从而更有利于静电从第二虚拟薄膜晶体管D-TFT2处释放。在一个具体实施例中，第二虚拟薄膜晶体管D-TFT2可以具有与显示像素PX的薄膜晶体管TFT相同的结构，例如，具有与图9所示的TFT的结构。
本实施例中，每个第二虚拟薄膜晶体管D-TFT2与引线W电连接，这样当接触垫上产生的静电从引线W导入显示区时，由于第二虚拟薄膜晶体管D-TFT2比虚拟像素DP距离产生静电的接触垫更近，可先通过第二虚拟薄膜晶体管D-TFT2释放全部或大部分静电荷，使第二虚拟薄膜晶体管D-TFT2被击穿。如果还有少量静电荷，则还可以通过虚拟像素DP释放。
本实施例中，通过设置第二虚拟薄膜晶体管D-TFT2，使静电荷可以在第二虚拟薄膜晶体管D-TFT2和虚拟像素DP的两个位置上得到释放，从而形成了对显示区形成双重保障由此进一步避免了因在显示像素PX处释放静电造成的显示不良。
例如，多个第二虚拟薄膜晶体管D-TFT2位于所述多个虚拟像素DP的远离所述显示区AA的一侧。所述多个第二虚拟薄膜晶体管D-TFT2沿所述虚拟像素阵列的至少部分外周排布为至少一排。例如，如图10所示，沿多个虚拟显示像素DP构成的虚拟像素阵列的下侧的外周设置有两行第二虚拟薄膜晶体管D-TFT2，由此可提高静电释放的几率。因此，本公开实施例对第二虚拟薄膜晶体管D-TFT2的数量和行数不做具体限制。
本公开实施例中，无论虚拟像素DP设置在沿显示像素阵列哪一侧，例如上侧、下侧、左侧和右侧，均可以在虚拟像素DP的远离显示区AA的一侧设置第二虚拟薄膜晶体管D-TFT2，并且使第二虚拟薄膜晶体管D-TFT2与虚拟像素DP连接到同一信号线，这样当静电从与该信号线连接的引线上导入时，更有利于静电在第二虚拟薄膜晶体管D-TFT2处释放。
例如，如图14所示，每个所述第二虚拟薄膜晶体管D-TFT2包括第二虚拟栅极GE2、第二虚拟有源层AT2、第二虚拟源漏电极SE2/DE2。例如，第二虚拟栅极GE2与辅助栅线AGL设置为同层同材料且彼此电连接。辅助栅线AGL配置为提供栅信号给第二虚拟栅极GE2。第二虚拟源极SE2与第一数据线DL1电连接。
例如，第二虚拟源漏电极SE2/DE2可以与第一虚拟源漏电极SE1/DE1设置为同层同材料。第二虚拟栅极GE2可以与第一虚拟栅极GE1设置为同层同材料。第二虚拟有源层AT2可以与第一虚拟有源层AT1设置为同层同材料。这样一来，可在形成第一虚拟薄膜晶体管D-TFT1的同时形成第二虚拟薄膜晶体管D-TFT2，从而简化制造工艺，减少工艺步骤。
图15为本公开实施例提供的显示基板的周边邦定区的结构示意图。
如图15所示，例如，所述显示基板100上还设置有位于周边邦定区PBA中多个输入接触垫，驱动芯片IC邦定在该周边邦定区PBA中。
例如，所述多个输入接触垫包括至少两组输入接触垫，所述至少两组输入接触垫包括第一组输入接触垫INP1和第二组输入接触垫INP2。第一组输入接触垫INP1配置为接收外部电路(例如柔性电路板FPC)提供的外部信号，外部信号包括但不限于电源电压、公共电压、接地等。第一导电连接线Z1和第二导电连接线Z2电连接在所述第一组输入接触垫INP1和所述第二组输入接触垫INP2之间并且配置为将所述第一组输入接触垫INP1接收的所述外部 信号传输给所述第二组输入接触垫INP2。所述第二组输入接触垫INP2配置为将所述外部信号传输给驱动芯片IC。所述多个接触垫P与所述驱动芯片IC电连接并且用作所述驱动芯片IC的输出接触垫，所述驱动芯片IC向多个接触垫P提供控制信号，进而通过多个接触垫P向所述显示区AA中的各个信号线提供控制信号。本实施例中，通过在第一组输入接触垫INP1和第二组输入接触垫INP2之间设置诸如第一导电连接线Z1或第二导电连接线Z2的导电连接线，有利于在周边区不同位置上的接触垫之间实现信号传输并且保证信号传输中的稳定性。
例如，所述第二组输入接触垫INP2包括设置在所述周边邦定区PBA的同一侧边缘上且间隔设置的多个第一输入接触垫CP1和多个第二输入接触垫CP2。所述第一组输入接触垫INP1包括多个第三输入接触垫CP3。
例如，第一导电连接线Z1包括第一连接部Z101，第一连接部Z101电连接于第三输入接触垫CP3和第一输入接触垫CP1之间，用于将外部信号(例如电源电压信号)从第三输入接触垫CP3传输到第一输入接触垫CP1。
例如，可选地，第一导电连接线Z1还包括第二连接部Z102，第二连接部Z102电连接第一输入接触垫CP1和第二输入接触垫CP2，用于将第一输入接触垫CP1上的电源电压信号传输到第二输入接触垫CP2。本实施例中，通过设置第二连接部Z102，用于在第一输入接触垫CP1和第二输入接触垫CP2之间实现信号传输同时保持两个第一输入接触垫CP1上的信号一致。
例如，可选地，第一导电连接线Z1还包括第三连接部Z103，其电连接于两个第一输入接触垫CP1之间，用于在两个第一输入接触垫CP1之间实现信号传输。本实施例中，通过在两个第一输入接触垫CP1之间设置第三连接部Z103，可以保证两个第一输入接触垫CP1上信号的稳定性和一致性。此外，本实施例中，通过将第三连接部Z103和第一连接部Z101(以及第二连接部Z102)分别设置在多个第一输入接触垫CP1的沿第一方向R1的相对两侧上，可提高显示基板上的空间利用率。
例如，第二导电连接线Z2用于传输与第一导电连接线Z1不同的外部信号，例如传输接地信号。第二导电连接线Z2包括第一连接部Z201。第一连接部Z201电连接于第三输入接触垫CP3和第一输入接触垫CP1之间，用于将接地信号从第三输入接触垫CP3传输到第一输入接触垫CP1。
例如，可选地，第二导电连接线Z2还包括第二连接部Z202，第二连接部Z202电连接于所述第一输入接触垫CP1和所述第二输入接触垫CP2之间，用于将接地信号从第一输入接触垫CP1传输到第二输入接触垫CP2。本实施例中，通过设置第二连接部Z202，可在第一输入接触垫CP1和第二输入接触垫CP2之间实现信号传输同时保持第一输入接触垫CP1和第二输入接触垫CP2上的信号一致。
例如，可选地，第二导电连接线Z2还包括第三连接部Z203，其电连接于第一输入接触垫CP1和第二输入接触垫CP2之间(例如图中所示三个第一输入接触垫CP1和两个第二输入接触垫CP2)，用于这些输入接触垫之间实现信号传输，以保证在这些输入接触垫上信号的稳定性和一致性。本实施例中，通过将第三连接部Z203和第一连接部Z201(以及第二连接部Z202)分别设置在多个第一输入接触垫CP1的沿第一方向R1的相对两侧上，可提高显示基板上的空间利用率。
可以理解的是，图中所示的通过第三连接部Z203连接的第一输入接触垫CP1和第二输入接触垫CP2的数量仅为示例性的，本公开实施例对此不做限定。
本公开实施例中，通过设置第三连接部Z103和第三连接部Z203，还可以在保证不增加显示基板的下边框的宽度的情况下，实现信号传输的稳定性。
可以理解的是，由于所述第二组输入接触垫INP2、第一组接触垫P1、第二接触垫P2都需要和驱动芯片IC邦定，为减小边框尺寸，第一组接触垫P1、第二接触垫P2与第一导电连接线Z1和第二导电连接线Z2之间的距离较近，本公开实施例的设计可以避免由于连接线与接触垫之间距离过近而造成的静电引发显示不良。
本公开实施例中，第一导电连接线Z1和第二导电连接线Z2在周边区中的走线方式与多个输入接触垫的布局相关。图15所示的第一导电连接线Z1和第二导电连接线Z2的走线方式仅为示意性的，本领域技术人员可以根据实际需要，设计出第一导电连接线Z1和第二导电连接线Z2的其他走线方式，本公开实施例对此不做限制。
图16为本公开实施例提供的显示基板的周边邦定区的简化截面示意图。
如图16所示，例如，所述显示基板包括显示侧，所述周边邦定区PBA包 括位于所述显示侧的第一表面SF1和与显示侧相反的第二表面SF2。
结合图15和图16，多个接触垫P、多个输入接触垫INP、第一导电连接线Z1、第二导电连接线Z2和所述驱动芯片IC均位于所述第一表面SF1。为了简化目的，图16仅示出了驱动芯片IC。
图17为本公开实施例提供的显示基板的制造方法的流程图。例如，本公开至少一个实施例还提供一种图1所示的显示基板100的制造方法，包括：
S100：形成多个数据线D、多个接触垫P和至少两个导电连接线Z1、Z2。
例如，所述多个数据线D位于显示基板100的显示区AA中并且配置为向所述显示区AA提供信号，所述多个接触垫P位于显示基板的周边区PA中并且与所述多个数据线D电连接，所述至少两个导电连接线Z1、Z2，位于所述周边区PA中并且位于所述多个接触垫P远离所述显示区AA的一侧，所述至少两个导电连接线Z1、Z2间隔排布且彼此绝缘。
例如，多个接触垫P中的第一组接触垫P1位于所述第一导电层ECL1，所述第一导电连接线Z1位于第二导电层ECL2，所述第一导电层ECL1和所述第二导电层ECL2设置为不同层。
在本公开至少一个实施例提供的显示基板的制造方法中，通过将第一组接触垫P1与最靠近该第一组接触垫P1的第一导电连接线Z1分别设置在不同层的两个导电层中，可避免在第一组接触垫P1和第一导电连接线Z1之间形成尖端电场，由此阻止静电释放和导通，减少甚至消除显示区出现的显示不良现象。
例如，上述制造方法还可包括：
S200：形成多个引线W，所述多个引线W位于所述周边区PA的周边过渡区PTA中，每个引线W的一端与所述数据线D电连接，另一端与接触垫P电连接。
例如，所述多个数据线D中的第一组数据线DL1、所述多个引线W中的第一组引线W1和所述第一组接触垫P1均位于所述第一导电层ECL2且一体成型。
在一个示例中，先形成第一导电材料层，然后通过构图工艺图案化第一导电材料层，以同时形成第一组数据线DL1、第一组引线W1和第一组接触垫P1。通过上述制造方法，可简化第一组数据线DL1、第一组引线W1和第一 组接触垫P1的制造工艺。
例如，所述多个数据线D中的第二组数据线DL2位于所述第一导电层ECL1，所述多个引线W中的第二组引线W2和所述多个接触垫P中的第二组第二接触垫P2位于所述第二导电层ECL2中且一体成型。
在一个示例中，先形成第二导电材料层，然后通过构图工艺图案化第二导电材料层，以同时形成第二组引线W2和第二组第二接触垫P2，由此可简化第二组引线W2和第二组第二接触垫P2的制造工艺。
例如，第一导电材料层和第二导电材料层可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，并且，第一导电材料层和第二导电材料层的材料可以相同，也可以不相同。
在本公开至少一个实施例提供的显示基板及其制造方法和显示装置中，通过将至少部分接触垫与最靠近该至少部分接触垫的第一导电连接线分别设置在不同层的两个导电层中，可避免在至少部分接触垫和第一导电连接线之间形成尖端电场，由此阻止静电释放和导通，减少甚至消除显示区出现显示不良现象。至少一些实施例中，通过设置虚拟像素，当有静电从引线导入显示区时，可先通过虚拟像素释放静电荷，由此避免在显示像素处释放静电。至少一些实施例中，通过设置第二虚拟薄膜晶体管，当有静电从引线导入显示区时，可先通过第二虚拟薄膜晶体管释放静电荷，由此进一步避免在显示像素处释放静电。
本文中，有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (27)

  1. 一种显示基板，包括：显示区和位于所述显示区至少一侧的周边区，所述显示基板还包括：
    多个信号线，位于所述显示区中，配置为向所述显示区提供信号；
    多个接触垫，位于所述周边区中，配置为与所述多个信号线电连接；
    至少两个导电连接线，位于所述周边区中并且位于所述多个接触垫远离所述显示区的一侧，所述至少两个导电连接线间隔排布，所述至少两个导电连接线包括在从所述显示区指向所述周边区的第一方向上最靠近所述多个接触垫的第一导电连接线；
    其中，至少部分所述多个接触垫位于第一导电层，所述第一导电连接线位于第二导电层，所述第一导电层和所述第二导电层设置为不同层。
  2. 根据权利要求1所述的显示基板，
    其中，所述多个接触垫包括第一组接触垫和第二组接触垫，所述第一组接触垫与所述第二组接触垫沿所述第一方向错开一定距离并且所述第二组接触垫比所述第一组接触垫更远离所述第一导电连接线；
    其中，所述第一组接触垫位于所述第一导电层。
  3. 根据权利要求2所述的显示基板，其中，所述第一组接触垫与所述第二组接触垫之间沿所述第一方向错开x个接触垫的位置，其中0.5≤x≤1.5；所述第一组接触垫与所述第二组接触垫在垂直于所述显示基板的方向上与所述至少两个导电连接线均不交叠。
  4. 根据权利要求1至3任一项所述的显示基板，
    其中，所述周边区包括周边邦定区和位于所述周边邦定区和所述显示区之间的周边过渡区；
    其中，所述显示基板还包括：
    多个引线，位于所述周边过渡区中，与所述多个信号线连接；
    所述多个接触垫位于所述周边邦定区中并且与所述多个引线连接；所述多个信号线包括第一组信号线和第二组信号线，所述多个引线包括第一组引线和第二组引线；所述第一组引线在靠近所述第一组信号线的一侧与所述第一组信号线连接并且在靠近所述第一组接触垫的一侧与所述第一组接触垫连 接；
    其中，所述第一组信号线、所述第一组引线和所述第一组接触垫均位于所述第一导电层。
  5. 根据权利要求4所述的显示基板，其中，
    所述第二组引线在靠近所述第二组信号线的一侧与所述第二组信号线连接并且在靠近所述第二组接触垫的一侧与所述第二组接触垫连接；
    所述第二组信号线位于所述第一导电层，所述第二组引线和所述第二组接触垫位于所述第二导电层。
  6. 根据权利要求5所述的显示基板，还包括：
    衬底基板；和
    位于所述衬底基板上的显示像素阵列，所述显示像素阵列位于所述显示区中，所述显示像素阵列包括：显示像素驱动电路、第一显示电极、钝化层和第二显示电极，所述第一显示电极和所述第二显示电极配置为产生电场；
    其中，所述显示像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括：栅极、源漏电极和层间绝缘层，所述层间绝缘层在垂直于所述衬底基板的方向上位于所述栅极和所述源漏电极之间；
    所述第一显示电极与所述源漏电极同层设置，所述第一显示电极与所述源漏电极电连接；
    所述钝化层位于所述第一显示电极的远离所述衬底基板的一侧；
    所述第二显示电极位于所述钝化层的远离所述第一显示电极的一侧；
    其中，所述第一导电层和所述第二导电层之一与所述栅极同层设置，所述第一导电层和所述第二导电层中的另一个与所述源漏电极同层设置。
  7. 根据权利要求6所述的显示基板，其中，
    所述源漏电极位于所述栅极的远离所述衬底基板的一侧；
    所述第一导电层位于所述第二导电层的远离所述衬底基板的一侧；
    所述第一导电层与所述源漏电极设置为同层同材料，所述第二导电层与所述栅极设置为同层同材料。
  8. 根据权利要求6所述的显示基板，
    其中，所述钝化层、所述层间绝缘层还延伸到所述周边区，
    所述层间绝缘层位于所述第二组引线的远离所述衬底基板的一侧，
    所述第二组信号线位于所述层间绝缘层的远离所述第二组引线的一侧，
    所述钝化层位于所述第二组信号线和所述层间绝缘层的远离所述衬底基板的一侧；
    其中，所述周边过渡区还设置有第一过孔、第二过孔和转接导电图案，
    所述第一过孔贯穿所述钝化层以暴露所述第二组信号线中的至少一个信号线，
    所述第二过孔贯穿所述钝化层和所述层间绝缘层以暴露所述第二组引线中与所述至少一个信号线对应的至少一个引线，
    所述转接导电图案覆盖所述第一过孔和所述第二过孔以电连接所述至少一个信号线和所述至少一个引线。
  9. 根据权利要求1至8任一项所述的显示基板，
    其中，所述至少两个导电连接线还包括：
    第二导电连接线，位于所述第一导电连接线远离所述多个接触垫的一侧，所述第二导电连接线位于所述第一导电层和所述第二导电层中的至少一层。
  10. 根据权利要求9所述的显示基板，其中，所述第一导电连接线和所述第二导电连接线配置为传输外部电路提供的信号。
  11. 根据权利要求1至10任一项所述的显示基板，还包括：
    衬底基板；
    位于所述衬底基板上的显示像素阵列，所述显示像素阵列位于所述显示区中；和
    位于所述衬底基板上的虚拟像素阵列区，所述虚拟像素阵列区包括多个虚拟像素，所述多个虚拟像素沿所述显示像素阵列的至少部分外周排布为至少一排；
    其中，每个所述虚拟像素配置为与所述多个接触垫之一电连接。
  12. 根据权利要求11所述的显示基板，其中：
    所述虚拟像素包括虚拟像素驱动电路、第一虚拟电极和第二虚拟电极，
    所述虚拟像素驱动电路包括第一虚拟薄膜晶体管，所述第一虚拟薄膜晶体管包括：第一虚拟栅极和第一虚拟源漏电极；
    所述第一虚拟电极与所述第一虚拟源漏电极同层设置；
    所述第二虚拟电极位于所述第一虚拟电极的远离所述衬底基板的一侧并 且与所述第一虚拟电极间隔设置；
    其中，所述第一虚拟电极配置为与所述第一虚拟源漏电极电连接，所述第一虚拟源漏电极配置为与所述多个引线之一电连接。
  13. 根据权利要求12所述的显示基板，其中，
    所述第一虚拟电极包括第一虚拟子电极和第二虚拟子电极，所述第一虚拟子电极和所述第二虚拟子电极在所述第一方向上间隔设置且彼此绝缘；
    所述第二虚拟子电极位于所述第一虚拟子电极的靠近所述显示区的一侧。
  14. 根据权利要求13所述的显示基板，其中，
    所述第一虚拟电极和所述第二虚拟电极之一为虚拟像素电极，另一个为虚拟公共电极，所述虚拟像素电极和所述虚拟公共电极在垂直于所述衬底基板的方向上相互交叠；
    所述虚拟像素电极为板状电极，所述虚拟公共电极为狭缝状电极。
  15. 根据权利要求11所述的显示基板，其中，所述虚拟像素阵列区还包括：
    多个第二虚拟薄膜晶体管，位于所述多个虚拟像素的远离所述显示区的一侧，
    其中，所述多个第二虚拟薄膜晶体管沿所述虚拟像素阵列的至少部分外周排布为至少一排；
    其中，每个所述第二虚拟薄膜晶体管包括：第二虚拟栅极和第二虚拟源漏电极，所述第二虚拟源漏电极配置为与所述多个引线之一电连接。
  16. 根据权利要求1至15任一项所述的显示基板，其中，至少部分所述多个接触垫中的每个沿所述第一方向延伸，每个所述导电连接线的至少一部分的延伸方向与所述第一方向相互交叉。
  17. 根据权利要求16所述的显示基板，其中，所述第一导电连接线与至少部分所述多个接触垫在所述第一方向上的最小第一间距为大于或等于10微米。
  18. 根据权利要求16所述的显示基板，其中，每个所述导电连接线的至少一部分的延伸方向与所述第一方向相互垂直。
  19. 根据权利要求18所述的显示基板，其中，所述第一导电连接线与至少部分所述多个接触垫在所述第一方向上的第一间距为大于或等于10微米。
  20. 根据权利要求19所述的显示基板，其中，所述第一间距小于所述第一导电连接线的线宽。
  21. 根据权利要求1至20任一项所述的显示基板，还包括设置在所述周边区中的多个输入接触垫，
    其中，所述多个输入接触垫包括至少两组输入接触垫，所述至少两组输入接触垫包括第一组输入接触垫和第二组输入接触垫，每个所述导电连接线电连接于所述第一组输入接触垫和所述第二组输入接触垫之间；
    所述第一组输入接触垫配置为接收外部电路提供的外部信号；每个所述导电连接线配置为将所述第一组输入接触垫接收的所述外部信号传输给所述第二组输入接触垫。
  22. 一种显示装置，包括权利要求1至21任一项所述的显示基板。
  23. 根据权利要求22所述的显示装置，还包括驱动芯片，所述显示基板还包括设置在所述周边区中的多个输入接触垫，
    其中，所述多个输入接触垫包括至少两组输入接触垫，所述至少两组输入接触垫包括第一组输入接触垫和第二组输入接触垫，每个所述导电连接线电连接于所述第一组输入接触垫和所述第二组输入接触垫之间；
    其中，所述多个接触垫与所述驱动芯片电连接并且用作所述驱动芯片的输出接触垫，所述驱动芯片向所述多个接触垫提供控制信号。
  24. 一种显示基板的制造方法，包括：
    形成多个信号线、多个接触垫和至少两个导电连接线，
    其中，所述多个信号线位于所述显示基板的显示区中并且配置为向所述显示区提供信号，所述多个接触垫位于所述显示基板的周边区中并且与所述多个信号线电连接，所述至少两个导电连接线，位于所述周边区中并且位于所述多个接触垫远离所述显示区的一侧，所述至少两个导电连接线间隔排布，所述至少两个导电连接线包括在从所述显示区指向所述周边区的第一方向上最靠近所述多个接触垫的第一导电连接线；
    其中，至少部分所述多个接触垫位于第一导电层，所述第一导电连接线位于第二导电层，所述第一导电层和所述第二导电层设置为不同层。
  25. 根据权利要求24所述的制造方法，其中，所述多个接触垫中的第一组接触垫位于所述第一导电层。
  26. 根据权利要求25所述的制造方法，还包括：
    形成多个引线，所述多个引线位于所述周边区的周边过渡区中并且与所述多个信号线电连接，所述多个接触垫与所述多个引线电连接；
    其中，所述多个信号线中的第一组信号线、所述多个引线中的第一组引线和所述第一组接触垫均位于所述第一导电层且一体成型。
  27. 根据权利要求26所述的制造方法，其中，所述多个信号线中的第二组信号线位于所述第一导电层，所述多个引线中的第二组引线和所述多个接触垫中的第二组第二接触垫位于所述第二导电层且一体成型。
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