WO2023068127A1 - High-frequency switch - Google Patents

High-frequency switch Download PDF

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Publication number
WO2023068127A1
WO2023068127A1 PCT/JP2022/038005 JP2022038005W WO2023068127A1 WO 2023068127 A1 WO2023068127 A1 WO 2023068127A1 JP 2022038005 W JP2022038005 W JP 2022038005W WO 2023068127 A1 WO2023068127 A1 WO 2023068127A1
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WIPO (PCT)
Prior art keywords
wiring
fet
frequency switch
drain
source
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PCT/JP2022/038005
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French (fr)
Japanese (ja)
Inventor
健 岸本
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株式会社村田製作所
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Publication of WO2023068127A1 publication Critical patent/WO2023068127A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present invention relates to high frequency switches.
  • Patent Document 1 describes a high-frequency switch arranged in a transmission path of high-frequency signals.
  • the off-capacitance of the high-frequency switch may cause the high-frequency signal to leak from the input terminal to the output terminal when the switch is turned off.
  • an object of the present invention is to provide a high-frequency switch that easily ensures isolation between an input terminal and an output terminal when the switch is turned off and reduces insertion loss when the switch is turned on.
  • a high-frequency switch includes an input terminal, an output terminal, a first FET, a second FET, a third FET, a first wiring, and a second wiring, wherein the first wiring is an input terminal.
  • the second wiring is connected between the output terminal and the source of the second FET, the source of the first FET and the drain of the second FET are connected, and the drain of the third FET is connected between the terminal and the drain of the first FET.
  • the source of the third FET is connected to the ground, and at least part of the first wiring and at least part of the second wiring are arranged so as to be magnetically coupled.
  • the direction of signal flow from the input terminal to the drain of the first FET in at least part of the first wiring and the direction of signal flow from the source of the second FET to the output terminal in at least part of the second wiring are substantially the same.
  • the first wiring and the second wiring are formed such that
  • the present invention it is possible to ensure isolation between the input terminal and the output terminal when the switch is turned off and to reduce the insertion loss when the switch is turned on.
  • FIG. 1 is a circuit configuration diagram showing an example of a high frequency switch according to an embodiment.
  • FIG. 2A is a cross-sectional view showing an example of first wiring and second wiring.
  • FIG. 2B is a cross-sectional view showing an example of the first wiring and the second wiring;
  • FIG. 3A is a diagram schematically showing the high-frequency switch when switched off.
  • FIG. 3B is an equivalent circuit diagram of the high-frequency switch when switched off.
  • FIG. 4 is a graph showing isolation characteristics of the high-frequency switch when the switch is turned off in the embodiment and the comparative example.
  • FIG. 5A is a diagram schematically showing the high-frequency switch when switched on.
  • FIG. 5B is an equivalent circuit diagram of the high-frequency switch when switched on.
  • FIG. 5A is a diagram schematically showing the high-frequency switch when switched on.
  • FIG. 5B is an equivalent circuit diagram of the high-frequency switch when switched on.
  • FIG. 5A is a diagram schematically showing the high-frequency switch when
  • FIG. 6A is a graph showing return loss characteristics of high-frequency switches when switched on in the embodiment and the comparative example.
  • FIG. 6B is a Smith chart showing the impedance characteristics of the high-frequency switch when switched on in the embodiment and the comparative example.
  • FIG. 6C is a graph showing pass characteristics of high-frequency switches when switched on in the embodiment and the comparative example.
  • FIG. 7A is a diagram showing an application example of the high frequency switch according to the embodiment.
  • FIG. 7B is a diagram showing an application example of the high frequency switch according to the embodiment.
  • connection means not only direct connection but also via other elements (for example, capacitors, inductors, or semiconductor elements such as diodes or transistors). A case of being electrically connected is also included.
  • connection between A and B means connected between A and B to both A and B, either directly or through another element.
  • FIG. 1 is a circuit configuration diagram showing an example of a high frequency switch 1 according to an embodiment.
  • the high-frequency switch 1 is a switch that switches between conduction and non-conduction between the input terminal t1 and the output terminal t2.
  • switch-on a state in which the input terminal t1 and the output terminal t2 of the high-frequency switch 1 are electrically connected
  • switch-off a state in which the input terminal t1 and the output terminal t2 are not electrically connected
  • the high-frequency switch 1 includes an input terminal t1, an output terminal t2, a first FET 30, a second FET 40, a third FET 50, a first wiring 10, and a second wiring 20.
  • the high-frequency switch 1 may also include control terminals t3 and t4 and resistors 60, 70 and 80. FIG.
  • the input terminal t1 is a terminal to which a signal (for example, a high frequency signal) is input
  • the output terminal t2 is a terminal to which the signal is output.
  • a signal input to the input terminal t1 is output from the output terminal t2 when the high frequency switch 1 is switched on.
  • Control terminals t3 and t4 are terminals for controlling the first FET 30, the second FET 40 and the third FET . By inputting a control signal (for example, a signal of a predetermined voltage value) to the control terminals t3 and t4, conduction and non-conduction of the first FET 30, the second FET 40 and the third FET 50 can be controlled.
  • the first wiring 10 is connected between the input terminal t1 and the drain of the first FET30.
  • the second wiring 20 is connected between the output terminal t2 and the source of the second FET40.
  • the first wiring 10 and the second wiring 20 are, for example, wiring patterns provided on a substrate.
  • the first FET 30 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • the first FET 30 has a gate connected to the control terminal t3 via the resistor 60, a drain connected to the input terminal t1 via the first wiring 10, and a source connected to the drains of the second FET 40 and the third FET 50.
  • a resistor 60 is a gate resistor of the first FET 30 .
  • the second FET 40 is, for example, a MOSFET.
  • the second FET 40 has a gate connected to the control terminal t3 via the resistor 70, a drain connected to the source of the first FET 30 and the drain of the third FET 50, and a source connected to the output terminal t2 via the second wiring 20.
  • a resistor 70 is the gate resistor of the second FET 40 .
  • the third FET 50 is connected between a path connecting the source of the first FET 30 and the drain of the second FET 40 and the ground.
  • the third FET 50 is, for example, a MOSFET.
  • the third FET 50 has a gate connected to the control terminal t4 via the resistor 80, a drain connected to the source of the first FET 30 and the drain of the second FET 40, and a source connected to the ground.
  • the first FET 30, the second FET 40 and the third FET 50 may be N-type or P-type.
  • At least part of the first wiring 10 and at least part of the second wiring 20 are arranged so as to be summatively coupled.
  • at least part of the first wiring 10 and at least part of the second wiring 20 are arranged so as to be magnetically coupled, and the signal from the input terminal t1 in at least part of the first wiring 10 to the drain of the first FET 30 is and the direction of signal flow from the source of the second FET 40 to the output terminal t2 in at least a part of the second wiring 20 are substantially the same. be done.
  • first wiring 10 and the second wiring 20 extend over the entire length of the first wiring 10 and the second wiring 20 (that is, the wiring from the input terminal t1 to the drain of the first FET 30 and the wiring from the output terminal t2 to the source of the second FET 40). may be arranged so as to be summatively combinable.
  • the first wiring 10 and the second wiring 20 are arranged over the entire length of the first wiring 10 and the second wiring 20 so as to be magnetically coupled, and the first wiring 10 and the second wiring 20 are arranged over the entire length of the first wiring 10 and the second wiring 20.
  • the direction of the signal flowing through the second wiring 20 from the source of the second FET 40 to the output terminal t2 are substantially the same.
  • first wiring 10 and the second wiring 20 may be formed.
  • the first wiring 10 and the second wiring 20 may be arranged so as to be partially summatively coupled.
  • the first wiring 10 and the second wiring 20 are partially arranged so as to be magnetically coupled, and from the input terminal t1 flowing through the first wiring 10 to the drain of the first FET 30 in the portion where the magnetic coupling is possible, and the direction of the signal flowing through the second wiring 20 from the source of the second FET 40 to the output terminal t2 are substantially the same. good.
  • the first wiring 10 may be all of the wiring from the input terminal t1 to the drain of the first FET 30. and may be part of it.
  • the second wiring 20 is simply referred to as the second wiring 20, but the second wiring 20 described below may be the entire wiring from the output terminal t2 to the source of the second FET 40. , may be part of it.
  • first wiring 10 and the second wiring 20 are arranged so as to be additively coupled, in other words, the first wiring 10 and the second wiring 20 are arranged so as to be magnetically coupled, and the first wiring 10 2A and 2B, the case where the first wiring 10 and the second wiring 20 are formed so that the direction of the signal flowing through the second wiring 20 is substantially the same as the direction of the signal flowing through the second wiring 20 will be described. do.
  • FIG. 2A and 2B are cross-sectional views showing examples of the first wiring 10 and the second wiring 20.
  • FIG. 2A and 2B are cross-sectional views showing examples of the first wiring 10 and the second wiring 20.
  • the high frequency switch 1 includes a substrate 5, and the first wiring 10 and the second wiring 20 are formed on the substrate 5.
  • the first wiring 10 and the second wiring 20 may be formed in the same layer of the substrate 5 as shown in FIG. 2A.
  • the first wiring 10 and the second wiring 20 are arranged substantially parallel along the direction in which each wiring extends.
  • the signal flows to the second wiring 20
  • the signal also flows from the front side of the paper surface to the back side of the paper surface.
  • a signal flows from the back side of the paper to the front side of the paper for the first wiring 10
  • the signal also flows from the back side of the paper to the front side of the paper for the second wiring 20 .
  • the first wiring 10 and the second wiring 20 are formed such that the direction of the signal flowing through the first wiring 10 and the direction of the signal flowing through the second wiring 20 are substantially the same.
  • the first wiring 10 and the second wiring 20 do not have to be arranged completely parallel to each other. If the angle between the first wiring 10 and the second wiring 20 is 30° or less, the first wiring 10 and the second wiring 20 may be arranged substantially parallel along the direction in which each wiring extends. That is, if the angle formed by the extending direction of the first wiring 10 and the extending direction of the second wiring 20 is 30° or less when the substrate 5 is viewed from above, the direction of the signal flowing through the first wiring 10 and the The first wiring 10 and the second wiring 20 may be formed such that the directions of the signals flowing through the two wirings 20 are substantially the same.
  • the first wiring 10 and the second wiring 20 may be formed in different layers of the substrate 5, as shown in FIG. 2B.
  • the substrate 5 may have multiple dielectric layers and the first wiring 10 and the second wiring 20 may be formed in different dielectric layers within the substrate 5 .
  • the first wiring 10 and the second wiring 20 may be formed on the front and back surfaces of the substrate 5 . Forming the first wiring 10 and the second wiring 20 on the front and back surfaces of the substrate 5 is also an example of forming the first wiring 10 and the second wiring 20 on different layers of the substrate 5 .
  • the first wiring 10 and the second wiring 20 are formed in different layers of the substrate 5, when the substrate 5 is viewed from above, the first wiring 10 and the second wiring 20 overlap along the direction in which each wiring extends.
  • the signal when a signal flows from the near side of the paper to the far side of the paper for the first wiring 10, the signal also flows from the near side of the paper to the far side of the paper for the second wiring 20 as well.
  • the signal when a signal flows from the back side of the paper to the front side of the paper for the first wiring 10 , the signal also flows from the back side of the paper to the front side of the paper for the second wiring 20 .
  • the first wiring 10 and the second wiring 20 are formed such that the direction of the signal flowing through the first wiring 10 and the direction of the signal flowing through the second wiring 20 are substantially the same.
  • the first wiring 10 and the second wiring 20 may not completely overlap along the direction in which each wiring extends.
  • the first wiring 10 and the second wiring 20 may overlap each other along the direction in which the wirings extend, provided that the angle between the wirings is 30° or less. In other words, if the angle formed by the first wiring 10 and the second wiring 20 is 30° or less when the substrate 5 is viewed from above, the direction of the signal flowing through the first wiring 10 and the signal flowing through the second wiring 20 are different.
  • the first wiring 10 and the second wiring 20 may be formed so as to be substantially the same direction as the direction of .
  • the state in which the first wiring 10 and the second wiring 20 are arranged so as to be magnetically coupled is, for example, a gap between the first wiring 10 and the second wiring 20 (left-right gap in FIG. 2A, 2B, the vertical gap) is three times or less the width of the first wiring 10 or the second wiring 20 .
  • first wiring 10 and the second wiring 20 are arranged so as to be magnetically coupled.
  • the first wiring 10 and the second wiring 20 are formed so that the direction of the signal from the source of the 2FET 40 to the output terminal t2 is substantially the same. It is described as being combinably arranged.
  • FIG. 3A the isolation between the input terminal t1 and the output terminal t2 when the high-frequency switch 1 is turned off will be described with reference to FIGS. 3A to 4.
  • FIG. 3A the isolation between the input terminal t1 and the output terminal t2 when the high-frequency switch 1 is turned off will be described with reference to FIGS. 3A to 4.
  • FIG. 3A is a diagram schematically showing the high-frequency switch 1 when switched off.
  • FIG. 3B is an equivalent circuit diagram of the high-frequency switch 1 when switched off.
  • the first FET 30 and the second FET 40 are controlled to be non-conductive, and the third FET 50 is controlled to be conductive.
  • the first wiring 10 has an inductance component L1 and the second wiring 20 has an inductance component L2.
  • the path to which the third FET 50 is connected (the path connecting the source of the first FET 30 and the drain of the second FET 40 and the path connecting the ground) has an inductance component L4.
  • the high-frequency switch 1 is turned off, the first FET 30 has an off-capacitance C1, the second FET 40 has an off-capacitance C2, and the third FET 50 has an on-resistance R3.
  • a positive mutual inductance (+M) is generated in the first wiring 10 and the second wiring 20 .
  • the inductance values of the first wiring 10 and the second wiring 20 are "L”
  • the inductance values of the first wiring 10 and the second wiring 20 where positive mutual inductance is generated are "L+M”, respectively.
  • a negative mutual inductance (-M) is generated in the path to which the third FET 50 is connected. This negative mutual inductance is illustrated as an inductance component L3.
  • FIG. 4 is a graph showing the isolation characteristics of the high-frequency switch (specifically, the isolation characteristics between the input terminal t1 and the output terminal t2) when the switch is turned off in the embodiment and the comparative example.
  • a solid line indicates the isolation characteristic in the embodiment, and a dashed line indicates the isolation characteristic in the comparative example.
  • the first FET 30, the second FET 40 and the third FET 50 are connected in the same manner as in the embodiment, but the first wiring 10 and the second wiring 20 are not arranged so as to be additively coupled.
  • the off-capacitance C1 of the first FET 30 and the off-capacitance C2 of the second FET 40 exist, so the high-frequency signal can leak from the input terminal t1 side to the output terminal t2 side.
  • the path connecting the source of the first FET 30 and the drain of the second FET 40 is connected to the ground via the third FET 50, even if the signal from the input terminal t1 leaks through the first FET 30, the leaked signal It is also considered that the current flows to the ground and that isolation between the input terminal t1 and the output terminal t2 can be ensured.
  • the path to which the third FET 50 is connected has wiring inductance (inductance component L4) in addition to the on-resistance R3 of the third FET 50.
  • the impedance of the path does not decrease at high frequencies. to degrade.
  • the isolation at 7 GHz is as small as 28.309 dB.
  • wiring inductance (inductance component L4) also exists in the path to which the third FET 50 is connected.
  • the first wiring 10 and the second wiring 20 are arranged so as to be additively coupled, negative mutual inductance occurs in the path to which the third FET 50 is connected. Therefore, the inductance value of the path becomes small, the impedance of the path can be lowered even at high frequencies, and the isolation can be improved.
  • the isolation at 7 GHz is as large as 35.281 dB.
  • FIG. 5A is a diagram schematically showing the high-frequency switch 1 when switched on.
  • FIG. 5B is an equivalent circuit diagram of the high-frequency switch 1 when switched on.
  • the first FET 30 and the second FET 40 are controlled to be conductive, and the third FET 50 is controlled to be non-conductive.
  • the first FET 30 has an on-resistance R1
  • the second FET 40 has an on-resistance R2
  • the third FET 50 has an off-capacitance C3.
  • first wiring 10 and the second wiring 20 are arranged so as to be additively coupled, a positive mutual inductance (+M) is generated in the first wiring 10 and the second wiring 20 . Further, since the first wiring 10 and the second wiring 20 are arranged so as to be additively coupled, a negative mutual inductance (-M) is generated in the path to which the third FET 50 is connected.
  • FIG. 6A is a graph showing return loss characteristics of the high-frequency switch when switched on in the embodiment and the comparative example.
  • a solid line indicates return loss characteristics in the embodiment, and a dashed line indicates return loss characteristics in the comparative example.
  • FIG. 6B is a Smith chart showing the impedance characteristics of the high-frequency switch when switched on in the embodiment and the comparative example.
  • a solid line indicates the impedance characteristic in the embodiment, and a dashed line indicates the impedance characteristic in the comparative example.
  • FIG. 6C is a graph showing pass characteristics of the high-frequency switch when switched on in the embodiment and the comparative example.
  • a solid line indicates the pass characteristic in the embodiment, and a dashed line indicates the pass characteristic in the comparative example.
  • the first FET 30, the second FET 40, and the third FET 50 are connected in the same manner as in the embodiment, but the first wiring 10 and the second wiring 20 are arranged so as to be additively coupled.
  • the input/output impedance of the high-frequency switch 1 may exhibit capacitiveness, but the first wiring 10 and the second wiring 20 have an inductance component. Therefore, in some cases, input/output impedance mismatch can be eliminated. However, in some cases, the inconsistency cannot be sufficiently resolved. For example, the mismatch may sometimes be eliminated by lengthening the lengths of the first wiring 10 and the second wiring 20. In that case, the resistance components of the first wiring 10 and the second wiring 20 becomes large, and the high-frequency switch 1 becomes large.
  • the comparative example As shown in FIG. 6B, the mismatch is not eliminated and the input/output impedance of the high frequency switch exhibits capacitiveness. Therefore, as shown in FIG. 6A, the return loss is worse in the comparative example than in the embodiment. As a result, as shown in FIG. 6C, the comparative example has a large insertion loss of 0.319 dB at 7 GHz.
  • the lengths of the first wiring 10 and the second wiring 20 are the same as in the comparative example, but the mismatch is eliminated as shown in FIG. 6B.
  • the first wiring 10 and the second wiring 20 are arranged so as to be additively coupled.
  • Positive mutual inductance is generated in the first wiring 10 and the second wiring 20 by arranging the first wiring 10 and the second wiring 20 so as to be summatively coupled. Therefore, in the embodiment, although the lengths of the first wiring 10 and the second wiring 20 are the same as in the comparative example, the mismatch is eliminated by generating positive mutual inductance. Accordingly, as shown in FIG. 6A, it can be seen that the return loss is improved in the embodiment as compared with the comparative example. As a result, as shown in FIG. 6C, the embodiment has a low insertion loss of 0.194 dB at 7 GHz.
  • an SPnT (Single Pole n Throw) switch as shown in FIG. 7A or an mPnT switch as shown in FIG. 7B may be realized (m and n are integer of 2 or more).
  • FIG. 7A and 7B are diagrams showing application examples of the high-frequency switch 1 according to the embodiment.
  • the SP3T switch may be realized by connecting the input terminal t1 sides of the three high frequency switches 1 in common.
  • the output terminal t2 side may be connected in common.
  • the output terminal t2 side of the three high frequency switches 1 and the input terminal t1 side of the three high frequency switches 1 are commonly connected to realize a 3P3T switch. good too.
  • the high-frequency switch 1 includes the input terminal t1, the output terminal t2, the first FET 30, the second FET 40, the third FET 50, the first wiring 10, and the second wiring 20.
  • the first wiring 10 is connected between the input terminal t1 and the drain of the first FET 30, the second wiring 20 is connected between the output terminal t2 and the source of the second FET 40, and the source of the first FET 30 and the drain of the second FET 40 are connected.
  • the drain of the third FET 50 is connected to the source of the first FET 30 and the drain of the second FET 40, and the source of the third FET 50 is connected to the ground.
  • At least part of the first wiring 10 and at least part of the second wiring 20 are arranged so as to be magnetically coupled, and the direction of signal flow from the input terminal t1 in at least part of the first wiring 10 to the drain of the first FET 30
  • the first wiring 10 and the second wiring 20 are formed such that the direction of signal flow from the source of the second FET 40 to the output terminal t2 in at least a part of the second wiring 20 is substantially the same.
  • At least part of the first wiring 10 and at least part of the second wiring 20 are arranged so as to be magnetically coupled, and a signal flows from the input terminal t1 of at least part of the first wiring 10 to the drain of the first FET 30. Since the first wiring 10 and the second wiring 20 are formed such that the direction of signal flow from the source of the second FET 40 to the output terminal t2 in at least a part of the second wiring 20 is substantially the same as the direction of signal flow, A positive mutual inductance is generated between the first wiring 10 and the second wiring 20 . When the high-frequency switch 1 is turned on, the input/output impedance mismatch of the high-frequency switch 1 may occur due to the off-capacitance C3 of the third FET 50.
  • the mismatch may sometimes be eliminated by lengthening the lengths of the first wiring 10 and the second wiring 20 to increase the inductance components of the first wiring 10 and the second wiring 20; In this case, the resistance components of the first wiring 10 and the second wiring 20 are increased, and the high-frequency switch 1 is increased in size.
  • the insertion loss of the high-frequency switch 1 is reduced when the high-frequency switch 1 is switched on, while suppressing an increase in the resistance components of the first wiring 10 and the second wiring 20 and an increase in the size of the high-frequency switch 1. be able to.
  • At least a portion of the first wiring 10 and at least a portion of the second wiring 20 are arranged so as to be magnetically coupled. and the direction of signal flow from the source of the second FET 40 to the output terminal t2 in at least a part of the second wiring 20 are substantially the same. Therefore, a negative mutual inductance occurs in the path to which the third FET 50 is connected (the path connecting the source of the first FET 30 and the drain of the second FET 40 and the path connecting the ground). As a result, the inductance value (in other words, the impedance value) of the path is reduced, and when the high-frequency switch 1 is switched off, the path connecting the first FET 30 and the second FET 40 is connected to the ground through a path with a small impedance value. becomes. Therefore, even if a signal from the input terminal t1 leaks through the first FET 30, the leaked signal can easily flow to the ground, and isolation between the input terminal t1 and the output terminal t2 can be ensured.
  • the high-frequency switch 1 may further include a substrate 5 , and at least a portion of the first wiring 10 and at least a portion of the second wiring 20 may be formed on the same layer of the substrate 5 .
  • At least a portion of the first wiring 10 and at least a portion of the second wiring 20 can be arranged so as to be magnetically coupled.
  • the high-frequency switch 1 further includes a substrate 5, and at least a portion of the first wiring 10 and at least a portion of the second wiring 20 are formed in different layers of the substrate 5.
  • the substrate 5 is viewed from above, At least part of the first wiring 10 and at least part of the second wiring 20 may overlap.
  • the first wiring 10 and at least a portion of the second wiring 20 can be arranged so as to be magnetically coupled.
  • the high-frequency switch 1 includes an input terminal t1, an output terminal t2, a first FET 30, a second FET 40, a third FET 50, a first wiring 10, and a second wiring 20.
  • the first wiring 10 is connected between the input terminal t1 and the drain of the first FET 30, the second wiring 20 is connected between the output terminal t2 and the source of the second FET 40, and the source of the first FET 30 and the drain of the second FET 40 are connected.
  • the drain of the third FET 50 is connected to the source of the first FET 30 and the drain of the second FET 40, and the source of the third FET 50 is connected to the ground.
  • At least part of the first wiring 10 and at least part of the second wiring 20 are arranged so as to be additively coupled.
  • the mismatch can be eliminated by lengthening the lengths of the first wiring 10 and the second wiring 20 to increase the inductance components of the first wiring 10 and the second wiring 20, but in that case , the resistance components of the first wiring 10 and the second wiring 20 are increased, and the high-frequency switch 1 is increased in size.
  • the insertion loss of the high-frequency switch 1 is reduced when the high-frequency switch 1 is switched on, while suppressing an increase in the resistance components of the first wiring 10 and the second wiring 20 and an increase in the size of the high-frequency switch 1. be able to.
  • the path to which the third FET 50 is connected (the source of the first FET 30 and the drain of the second FET 40) and ground)
  • a negative mutual inductance occurs.
  • the inductance value in other words, the impedance value
  • the path connecting the first FET 30 and the second FET 40 is connected to the ground through a path with a small impedance value. becomes. Therefore, even if a signal from the input terminal t1 leaks through the first FET 30, the leaked signal can easily flow to the ground, and isolation between the input terminal t1 and the output terminal t2 can be ensured.
  • the present invention is not limited to the above embodiments. Another embodiment realized by combining arbitrary constituent elements in the above embodiment, and a modification obtained by applying various modifications to the above embodiment within the scope of the present invention that a person skilled in the art can think of
  • the present invention also includes various devices incorporating the high-frequency switch 1 according to the present invention.
  • the present invention can be widely used as a high-frequency switch for communication equipment such as mobile phones.

Abstract

In a high-frequency switch (1): first wiring (10) is connected between an input terminal (t1) and a drain of a first FET (30); second wiring (20) is connected between an output terminal (t2) and a source of a second FET (40); a source of the first FET (30) and a drain of the second FET (40) are connected; a drain of a third FET (50) is connected to the source of the first FET (30) and the drain of the second FET (40); a source of the third FET (50) is connected to ground; at least a portion of the first wiring (10) and at least a portion of the second wiring (20) are disposed to allow magnetic field coupling between the same; and the first wiring (10) and the second wiring (20) are formed such that an orientation in which a signal flows in the at least a portion of the first wiring (10) and an orientation in which a signal flows in the at least a portion of the second wiring (20) are substantially the same orientation.

Description

高周波スイッチhigh frequency switch
　本発明は、高周波スイッチに関する。 The present invention relates to high frequency switches.
　特許文献１には、高周波信号の伝送経路に配置された高周波スイッチが記載されている。 Patent Document 1 describes a high-frequency switch arranged in a transmission path of high-frequency signals.
国際公開第２０１６／０３０９４２号WO2016/030942
　高周波信号の伝送経路に高周波スイッチが配置される場合、スイッチオフ時には、高周波スイッチのオフ容量によって高周波信号が入力端子から出力端子へ漏洩し得る。スイッチオフ時の入力端子と出力端子との間のアイソレーションを確保して高周波信号の漏洩を抑制するために、高周波スイッチを多段接続することが考えられるが、スイッチオン時には、高周波スイッチのオン抵抗による挿入損失が発生するため、高周波スイッチを多段接続するほど挿入損失が大きくなる。このように、スイッチオフ時の入力端子と出力端子との間のアイソレーションの確保およびスイッチオン時の挿入損失の低減を両立することが困難となっている。 When a high-frequency switch is placed in the high-frequency signal transmission path, the off-capacitance of the high-frequency switch may cause the high-frequency signal to leak from the input terminal to the output terminal when the switch is turned off. In order to secure the isolation between the input terminal and the output terminal when the switch is off and suppress the leakage of high frequency signals, it is possible to connect high frequency switches in multiple stages, but when the switch is on, the on resistance of the high frequency switch Therefore, the more high-frequency switches are connected in multiple stages, the greater the insertion loss. Thus, it is difficult to ensure the isolation between the input terminal and the output terminal when the switch is turned off and to reduce the insertion loss when the switch is turned on.
　そこで、本発明は、スイッチオフ時の入力端子と出力端子との間のアイソレーションの確保およびスイッチオン時の挿入損失の低減を両立しやすい高周波スイッチを提供することを目的とする。 Therefore, an object of the present invention is to provide a high-frequency switch that easily ensures isolation between an input terminal and an output terminal when the switch is turned off and reduces insertion loss when the switch is turned on.
　本発明の一態様に係る高周波スイッチは、入力端子と、出力端子と、第１ＦＥＴと、第２ＦＥＴと、第３ＦＥＴと、第１配線と、第２配線と、を備え、第１配線は、入力端子と第１ＦＥＴのドレインとの間に接続され、第２配線は、出力端子と第２ＦＥＴのソースとの間に接続され、第１ＦＥＴのソースと第２ＦＥＴのドレインとが接続され、第３ＦＥＴのドレインは、第１ＦＥＴのソースおよび第２ＦＥＴのドレインと接続され、第３ＦＥＴのソースは、グランドに接続され、第１配線の少なくとも一部と第２配線の少なくとも一部とは、磁界結合可能に配置され、第１配線の少なくとも一部における入力端子から第１ＦＥＴのドレインへの信号の流れる向きと、第２配線の少なくとも一部における第２ＦＥＴのソースから出力端子への信号の流れる向きとが略同じ向きとなるように、第１配線および第２配線は形成される。 A high-frequency switch according to an aspect of the present invention includes an input terminal, an output terminal, a first FET, a second FET, a third FET, a first wiring, and a second wiring, wherein the first wiring is an input terminal. The second wiring is connected between the output terminal and the source of the second FET, the source of the first FET and the drain of the second FET are connected, and the drain of the third FET is connected between the terminal and the drain of the first FET. is connected to the source of the first FET and the drain of the second FET, the source of the third FET is connected to the ground, and at least part of the first wiring and at least part of the second wiring are arranged so as to be magnetically coupled. , the direction of signal flow from the input terminal to the drain of the first FET in at least part of the first wiring and the direction of signal flow from the source of the second FET to the output terminal in at least part of the second wiring are substantially the same. The first wiring and the second wiring are formed such that
　本発明によれば、スイッチオフ時の入力端子と出力端子との間のアイソレーションの確保およびスイッチオン時の挿入損失の低減を両立できる。 According to the present invention, it is possible to ensure isolation between the input terminal and the output terminal when the switch is turned off and to reduce the insertion loss when the switch is turned on.
図１は、実施の形態に係る高周波スイッチの一例を示す回路構成図である。FIG. 1 is a circuit configuration diagram showing an example of a high frequency switch according to an embodiment. 図２Ａは、第１配線および第２配線の一例を示す断面図である。FIG. 2A is a cross-sectional view showing an example of first wiring and second wiring. 図２Ｂは、第１配線および第２配線の一例を示す断面図である。FIG. 2B is a cross-sectional view showing an example of the first wiring and the second wiring; 図３Ａは、スイッチオフ時の高周波スイッチを模式的に示す図である。FIG. 3A is a diagram schematically showing the high-frequency switch when switched off. 図３Ｂは、スイッチオフ時の高周波スイッチの等価回路図である。FIG. 3B is an equivalent circuit diagram of the high-frequency switch when switched off. 図４は、実施の形態および比較例におけるスイッチオフ時の高周波スイッチのアイソレーション特性を示すグラフである。FIG. 4 is a graph showing isolation characteristics of the high-frequency switch when the switch is turned off in the embodiment and the comparative example. 図５Ａは、スイッチオン時の高周波スイッチを模式的に示す図である。FIG. 5A is a diagram schematically showing the high-frequency switch when switched on. 図５Ｂは、スイッチオン時の高周波スイッチの等価回路図である。FIG. 5B is an equivalent circuit diagram of the high-frequency switch when switched on. 図６Ａは、実施の形態および比較例におけるスイッチオン時の高周波スイッチのリターンロス特性を示すグラフである。FIG. 6A is a graph showing return loss characteristics of high-frequency switches when switched on in the embodiment and the comparative example. 図６Ｂは、実施の形態および比較例におけるスイッチオン時の高周波スイッチのインピーダンス特性を示すスミスチャートである。FIG. 6B is a Smith chart showing the impedance characteristics of the high-frequency switch when switched on in the embodiment and the comparative example. 図６Ｃは、実施の形態および比較例におけるスイッチオン時の高周波スイッチの通過特性を示すグラフである。FIG. 6C is a graph showing pass characteristics of high-frequency switches when switched on in the embodiment and the comparative example. 図７Ａは、実施の形態に係る高周波スイッチの適用例を示す図である。FIG. 7A is a diagram showing an application example of the high frequency switch according to the embodiment. 図７Ｂは、実施の形態に係る高周波スイッチの適用例を示す図である。FIG. 7B is a diagram showing an application example of the high frequency switch according to the embodiment.
　以下、本発明の実施の形態について、図面を用いて詳細に説明する。なお、以下で説明する実施の形態は、いずれも包括的または具体的な例を示すものである。以下の実施の形態で示される数値、形状、材料、構成要素、構成要素の配置および接続形態などは、一例であり、本発明を限定する主旨ではない。以下の実施の形態における構成要素のうち、独立請求項に記載されていない構成要素については、任意の構成要素として説明される。また、図面に示される構成要素の大きさ、または大きさの比は、必ずしも厳密ではない。また、各図において、実質的に同一の構成に対しては同一の符号を付しており、重複する説明は省略または簡略化する場合がある。また、以下の実施の形態において、「接続される」とは、直接接続される場合だけでなく、他の素子（例えば、キャパシタ、インダクタ、または、ダイオードもしくはトランジスタ等の半導体素子など）を介して電気的に接続される場合も含まれる。例えば、「ＡとＢとの間に接続される」とは、ＡおよびＢの間でＡおよびＢの両方に、直接または他の素子を介して接続されることを意味する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It should be noted that the embodiments described below are all comprehensive or specific examples. Numerical values, shapes, materials, constituent elements, arrangement of constituent elements, connection forms, and the like shown in the following embodiments are examples, and are not intended to limit the present invention. Among the constituent elements in the following embodiments, constituent elements not described in independent claims will be described as optional constituent elements. Also, the sizes, or size ratios, of components shown in the drawings are not necessarily exact. Moreover, in each figure, the same code|symbol is attached|subjected with respect to substantially the same structure, and the overlapping description may be abbreviate|omitted or simplified. In addition, in the following embodiments, "connected" means not only direct connection but also via other elements (for example, capacitors, inductors, or semiconductor elements such as diodes or transistors). A case of being electrically connected is also included. For example, "connected between A and B" means connected between A and B to both A and B, either directly or through another element.
　（実施の形態）
　実施の形態について、図１から図７Ｂを用いて説明する。 (Embodiment)
An embodiment will be described with reference to FIGS. 1 to 7B.
　図１は、実施の形態に係る高周波スイッチ１の一例を示す回路構成図である。 FIG. 1 is a circuit configuration diagram showing an example of a high frequency switch 1 according to an embodiment.
　高周波スイッチ１は、入力端子ｔ１と出力端子ｔ２との導通および非導通を切り替えるスイッチである。以下では、高周波スイッチ１によって、入力端子ｔ１と出力端子ｔ２とが導通している状態をスイッチオン時と記載し、入力端子ｔ１と出力端子ｔ２とが非導通となっている状態をスイッチオフ時と記載する。 The high-frequency switch 1 is a switch that switches between conduction and non-conduction between the input terminal t1 and the output terminal t2. Hereinafter, a state in which the input terminal t1 and the output terminal t2 of the high-frequency switch 1 are electrically connected is referred to as switch-on, and a state in which the input terminal t1 and the output terminal t2 are not electrically connected is referred to as switch-off. and described.
　高周波スイッチ１は、入力端子ｔ１と、出力端子ｔ２と、第１ＦＥＴ３０と、第２ＦＥＴ４０と、第３ＦＥＴ５０と、第１配線１０と、第２配線２０と、を備える。また、高周波スイッチ１は、制御端子ｔ３およびｔ４と、抵抗６０、７０および８０と、を備えていてもよい。 The high-frequency switch 1 includes an input terminal t1, an output terminal t2, a first FET 30, a second FET 40, a third FET 50, a first wiring 10, and a second wiring 20. The high-frequency switch 1 may also include control terminals t3 and t4 and resistors 60, 70 and 80. FIG.
　入力端子ｔ１は、信号（例えば高周波信号）が入力される端子であり、出力端子ｔ２は、信号が出力される端子である。入力端子ｔ１に入力された信号は、高周波スイッチ１のスイッチオン時に出力端子ｔ２から出力される。制御端子ｔ３およびｔ４は、第１ＦＥＴ３０、第２ＦＥＴ４０および第３ＦＥＴ５０を制御するための端子である。制御端子ｔ３およびｔ４に制御信号（例えば所定の電圧値の信号）が入力されることで、第１ＦＥＴ３０、第２ＦＥＴ４０および第３ＦＥＴ５０の導通および非導通を制御することができる。 The input terminal t1 is a terminal to which a signal (for example, a high frequency signal) is input, and the output terminal t2 is a terminal to which the signal is output. A signal input to the input terminal t1 is output from the output terminal t2 when the high frequency switch 1 is switched on. Control terminals t3 and t4 are terminals for controlling the first FET 30, the second FET 40 and the third FET . By inputting a control signal (for example, a signal of a predetermined voltage value) to the control terminals t3 and t4, conduction and non-conduction of the first FET 30, the second FET 40 and the third FET 50 can be controlled.
　第１配線１０は、入力端子ｔ１と第１ＦＥＴ３０のドレインとの間に接続される。第２配線２０は、出力端子ｔ２と第２ＦＥＴ４０のソースとの間に接続される。第１配線１０および第２配線２０は、例えば、基板に設けられた配線パターンである。 The first wiring 10 is connected between the input terminal t1 and the drain of the first FET30. The second wiring 20 is connected between the output terminal t2 and the source of the second FET40. The first wiring 10 and the second wiring 20 are, for example, wiring patterns provided on a substrate.
　第１ＦＥＴ３０は、例えば、ＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）である。例えば、第１ＦＥＴ３０は、ゲートが抵抗６０を介して制御端子ｔ３に接続され、ドレインが第１配線１０を介して入力端子ｔ１に接続され、ソースが第２ＦＥＴ４０のドレインおよび第３ＦＥＴ５０のドレインに接続される。抵抗６０は、第１ＦＥＴ３０のゲート抵抗である。 The first FET 30 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). For example, the first FET 30 has a gate connected to the control terminal t3 via the resistor 60, a drain connected to the input terminal t1 via the first wiring 10, and a source connected to the drains of the second FET 40 and the third FET 50. be. A resistor 60 is a gate resistor of the first FET 30 .
　第２ＦＥＴ４０は、例えば、ＭＯＳＦＥＴである。例えば、第２ＦＥＴ４０は、ゲートが抵抗７０を介して制御端子ｔ３に接続され、ドレインが第１ＦＥＴ３０のソースおよび第３ＦＥＴ５０のドレインに接続され、ソースが第２配線２０を介して出力端子ｔ２に接続される。抵抗７０は、第２ＦＥＴ４０のゲート抵抗である。第１ＦＥＴ３０のソースと第２ＦＥＴ４０のドレインとが接続されることで、第１ＦＥＴ３０と第２ＦＥＴ４０とは、直列接続されている。 The second FET 40 is, for example, a MOSFET. For example, the second FET 40 has a gate connected to the control terminal t3 via the resistor 70, a drain connected to the source of the first FET 30 and the drain of the third FET 50, and a source connected to the output terminal t2 via the second wiring 20. be. A resistor 70 is the gate resistor of the second FET 40 . By connecting the source of the first FET 30 and the drain of the second FET 40, the first FET 30 and the second FET 40 are connected in series.
　第３ＦＥＴ５０は、第１ＦＥＴ３０のソースと第２ＦＥＴ４０のドレインとを結ぶ経路とグランドとの間に接続される。第３ＦＥＴ５０は、例えば、ＭＯＳＦＥＴである。例えば、第３ＦＥＴ５０は、ゲートが抵抗８０を介して制御端子ｔ４に接続され、ドレインが第１ＦＥＴ３０のソースおよび第２ＦＥＴ４０のドレインに接続され、ソースがグランドに接続される。 The third FET 50 is connected between a path connecting the source of the first FET 30 and the drain of the second FET 40 and the ground. The third FET 50 is, for example, a MOSFET. For example, the third FET 50 has a gate connected to the control terminal t4 via the resistor 80, a drain connected to the source of the first FET 30 and the drain of the second FET 40, and a source connected to the ground.
　第１ＦＥＴ３０、第２ＦＥＴ４０および第３ＦＥＴ５０は、Ｎ型であってもよいし、Ｐ型であってもよい。 The first FET 30, the second FET 40 and the third FET 50 may be N-type or P-type.
　高周波スイッチ１のスイッチオン時には、第１ＦＥＴ３０および第２ＦＥＴ４０を導通とするための制御信号が制御端子ｔ３に入力され、第３ＦＥＴ５０を非導通とするための制御信号が制御端子ｔ４に入力される。これにより、入力端子ｔ１に入力された信号を出力端子ｔ２から出力することができる。高周波スイッチ１のスイッチオフ時には、第１ＦＥＴ３０および第２ＦＥＴ４０を非導通とするための制御信号が制御端子ｔ３に入力され、第３ＦＥＴ５０を導通とするための制御信号が制御端子ｔ４に入力される。これにより、入力端子ｔ１に入力された信号を出力端子ｔ２から出力されにくくすることができる。 When the high-frequency switch 1 is switched on, a control signal for making the first FET 30 and the second FET 40 conductive is input to the control terminal t3, and a control signal for making the third FET 50 non-conductive is input to the control terminal t4. As a result, the signal input to the input terminal t1 can be output from the output terminal t2. When the high-frequency switch 1 is switched off, a control signal for making the first FET 30 and the second FET 40 non-conductive is input to the control terminal t3, and a control signal for making the third FET 50 conductive is input to the control terminal t4. This makes it difficult for the signal input to the input terminal t1 to be output from the output terminal t2.
　第１配線１０の少なくとも一部と第２配線２０の少なくとも一部とは、和動結合可能に配置される。言い換えると、第１配線１０の少なくとも一部と第２配線２０の少なくとも一部とは、磁界結合可能に配置され、第１配線１０の少なくとも一部における入力端子ｔ１から第１ＦＥＴ３０のドレインへの信号の流れる向きと、第２配線２０の少なくとも一部における第２ＦＥＴ４０のソースから出力端子ｔ２への信号の流れる向きとは、略同じ向きとなるように、第１配線１０および第２配線２０は形成される。なお、第１配線１０および第２配線２０の全長（すなわち入力端子ｔ１から第１ＦＥＴ３０のドレインまでの配線および出力端子ｔ２から第２ＦＥＴ４０のソースまでの配線）にわたって第１配線１０と第２配線２０とが和動結合可能に配置されていてもよい。言い換えると、第１配線１０および第２配線２０の全長にわたって第１配線１０と第２配線２０とが磁界結合可能に配置され、第１配線１０および第２配線２０の全長にわたって、第１配線１０を流れる入力端子ｔ１から第１ＦＥＴ３０のドレインへの信号の向きと、第２配線２０を流れる第２ＦＥＴ４０のソースから出力端子ｔ２への信号の向きとが、略同じ向きとなるように第１配線１０および第２配線２０が形成されていてもよい。あるいは、第１配線１０と第２配線２０とが部分的に和動結合可能に配置されていてもよい。言い換えると、第１配線１０と第２配線２０とが部分的に磁界結合可能に配置され、磁界結合可能に配置されている部分における、第１配線１０を流れる入力端子ｔ１から第１ＦＥＴ３０のドレインへの信号の向きと、第２配線２０を流れる第２ＦＥＴ４０のソースから出力端子ｔ２への信号の向きとが、略同じ向きとなるように第１配線１０および第２配線２０が形成されていてもよい。 At least part of the first wiring 10 and at least part of the second wiring 20 are arranged so as to be summatively coupled. In other words, at least part of the first wiring 10 and at least part of the second wiring 20 are arranged so as to be magnetically coupled, and the signal from the input terminal t1 in at least part of the first wiring 10 to the drain of the first FET 30 is and the direction of signal flow from the source of the second FET 40 to the output terminal t2 in at least a part of the second wiring 20 are substantially the same. be done. Note that the first wiring 10 and the second wiring 20 extend over the entire length of the first wiring 10 and the second wiring 20 (that is, the wiring from the input terminal t1 to the drain of the first FET 30 and the wiring from the output terminal t2 to the source of the second FET 40). may be arranged so as to be summatively combinable. In other words, the first wiring 10 and the second wiring 20 are arranged over the entire length of the first wiring 10 and the second wiring 20 so as to be magnetically coupled, and the first wiring 10 and the second wiring 20 are arranged over the entire length of the first wiring 10 and the second wiring 20. , and the direction of the signal flowing through the second wiring 20 from the source of the second FET 40 to the output terminal t2 are substantially the same. and a second wiring 20 may be formed. Alternatively, the first wiring 10 and the second wiring 20 may be arranged so as to be partially summatively coupled. In other words, the first wiring 10 and the second wiring 20 are partially arranged so as to be magnetically coupled, and from the input terminal t1 flowing through the first wiring 10 to the drain of the first FET 30 in the portion where the magnetic coupling is possible, and the direction of the signal flowing through the second wiring 20 from the source of the second FET 40 to the output terminal t2 are substantially the same. good.
　以下では、第１配線１０の少なくとも一部を単に第１配線１０とも記載するが、以下に記載する第１配線１０は、入力端子ｔ１から第１ＦＥＴ３０のドレインまでの配線の全てであってもよいし、その一部であってもよい。また、第２配線２０の少なくとも一部を単に第２配線２０とも記載するが、以下に記載する第２配線２０は、出力端子ｔ２から第２ＦＥＴ４０のソースまでの配線の全てであってもよいし、その一部であってもよい。 Although at least part of the first wiring 10 is also simply referred to as the first wiring 10 below, the first wiring 10 described below may be all of the wiring from the input terminal t1 to the drain of the first FET 30. and may be part of it. Also, at least part of the second wiring 20 is simply referred to as the second wiring 20, but the second wiring 20 described below may be the entire wiring from the output terminal t2 to the source of the second FET 40. , may be part of it.
　ここで、第１配線１０と第２配線２０とが和動結合可能に配置される場合、言い換えると、第１配線１０と第２配線２０とが、磁界結合可能に配置され、第１配線１０を流れる信号の向きと、第２配線２０を流れる信号の向きとが略同じ向きとなるように第１配線１０および第２配線２０が形成される場合について、図２Ａおよび図２Ｂを用いて説明する。 Here, when the first wiring 10 and the second wiring 20 are arranged so as to be additively coupled, in other words, the first wiring 10 and the second wiring 20 are arranged so as to be magnetically coupled, and the first wiring 10 2A and 2B, the case where the first wiring 10 and the second wiring 20 are formed so that the direction of the signal flowing through the second wiring 20 is substantially the same as the direction of the signal flowing through the second wiring 20 will be described. do.
　図２Ａおよび図２Ｂは、第１配線１０および第２配線２０の一例を示す断面図である。 2A and 2B are cross-sectional views showing examples of the first wiring 10 and the second wiring 20. FIG.
　例えば、高周波スイッチ１は、基板５を備え、第１配線１０および第２配線２０は、基板５に形成される。 For example, the high frequency switch 1 includes a substrate 5, and the first wiring 10 and the second wiring 20 are formed on the substrate 5.
　例えば、図２Ａに示されるように、第１配線１０および第２配線２０は、基板５の同じ層に形成されてもよい。例えば、基板５を平面視したときに、第１配線１０と第２配線２０とは各配線が延びる方向に沿って略平行に配置されており、第１配線１０について紙面手前側から紙面奥側へ信号が流れる場合、第２配線２０についても紙面手前側から紙面奥側へ信号が流れる。また、第１配線１０について紙面奥側から紙面手前側へ信号が流れる場合、第２配線２０についても紙面奥側から紙面手前側へ信号が流れる。このように、第１配線１０を流れる信号の向きと、第２配線２０を流れる信号の向きとが略同じ向きとなるように、第１配線１０および第２配線２０が形成される。なお、基板５を平面視したときに、第１配線１０と第２配線２０とは完全に平行に配置されていなくてもよく、第１配線１０の延びる方向と第２配線２０の延びる方向とのなす角が３０°以下であれば、第１配線１０と第２配線２０とは各配線が延びる方向に沿って略平行に配置されているとしてもよい。つまり、基板５を平面視したときに、第１配線１０の延びる方向と第２配線２０の延びる方向とのなす角が３０°以下であれば、第１配線１０を流れる信号の向きと、第２配線２０を流れる信号の向きとが略同じ向きとなるように、第１配線１０および第２配線２０が形成されているとしてもよい。 For example, the first wiring 10 and the second wiring 20 may be formed in the same layer of the substrate 5 as shown in FIG. 2A. For example, when the substrate 5 is viewed from above, the first wiring 10 and the second wiring 20 are arranged substantially parallel along the direction in which each wiring extends. When the signal flows to the second wiring 20, the signal also flows from the front side of the paper surface to the back side of the paper surface. When a signal flows from the back side of the paper to the front side of the paper for the first wiring 10 , the signal also flows from the back side of the paper to the front side of the paper for the second wiring 20 . Thus, the first wiring 10 and the second wiring 20 are formed such that the direction of the signal flowing through the first wiring 10 and the direction of the signal flowing through the second wiring 20 are substantially the same. Note that when the substrate 5 is viewed in plan, the first wiring 10 and the second wiring 20 do not have to be arranged completely parallel to each other. If the angle between the first wiring 10 and the second wiring 20 is 30° or less, the first wiring 10 and the second wiring 20 may be arranged substantially parallel along the direction in which each wiring extends. That is, if the angle formed by the extending direction of the first wiring 10 and the extending direction of the second wiring 20 is 30° or less when the substrate 5 is viewed from above, the direction of the signal flowing through the first wiring 10 and the The first wiring 10 and the second wiring 20 may be formed such that the directions of the signals flowing through the two wirings 20 are substantially the same.
　また、例えば、図２Ｂに示されるように、第１配線１０および第２配線２０は、基板５の異なる層に形成されてもよい。例えば、基板５は複数の誘電体層を有し、第１配線１０および第２配線２０は、基板５内の異なる誘電体層に形成されてもよい。あるいは、第１配線１０および第２配線２０は、基板５の表面および裏面に形成されてもよい。なお、第１配線１０および第２配線２０が基板５の表面および裏面に形成されることも、第１配線１０および第２配線２０が基板５の異なる層に形成されることの一例とする。 Also, for example, the first wiring 10 and the second wiring 20 may be formed in different layers of the substrate 5, as shown in FIG. 2B. For example, the substrate 5 may have multiple dielectric layers and the first wiring 10 and the second wiring 20 may be formed in different dielectric layers within the substrate 5 . Alternatively, the first wiring 10 and the second wiring 20 may be formed on the front and back surfaces of the substrate 5 . Forming the first wiring 10 and the second wiring 20 on the front and back surfaces of the substrate 5 is also an example of forming the first wiring 10 and the second wiring 20 on different layers of the substrate 5 .
　第１配線１０および第２配線２０が基板５の異なる層に形成される場合に、基板５を平面視したとき、第１配線１０と第２配線２０とは各配線が延びる方向に沿って重複しており、第１配線１０について紙面手前側から紙面奥側へ信号が流れる場合、第２配線２０についても紙面手前側から紙面奥側へ信号が流れる。また、第１配線１０について紙面奥側から紙面手前側へ信号が流れる場合、第２配線２０についても紙面奥側から紙面手前側へ信号が流れる。このように、第１配線１０を流れる信号の向きと、第２配線２０を流れる信号の向きとが略同じ向きとなるように、第１配線１０および第２配線２０が形成される。なお、基板５を平面視したときに、第１配線１０と第２配線２０とは各配線が延びる方向に沿って完全に重複していなくてもよく、第１配線１０と第２配線２０とのなす角が３０°以下であれば、第１配線１０と第２配線２０とは各配線が延びる方向に沿って重複しているとしてもよい。つまり、基板５を平面視したときに、第１配線１０と第２配線２０とのなす角が３０°以下であれば、第１配線１０を流れる信号の向きと、第２配線２０を流れる信号の向きとが略同じ向きとなるように、第１配線１０および第２配線２０が形成されているとしてもよい。 When the first wiring 10 and the second wiring 20 are formed in different layers of the substrate 5, when the substrate 5 is viewed from above, the first wiring 10 and the second wiring 20 overlap along the direction in which each wiring extends. Thus, when a signal flows from the near side of the paper to the far side of the paper for the first wiring 10, the signal also flows from the near side of the paper to the far side of the paper for the second wiring 20 as well. When a signal flows from the back side of the paper to the front side of the paper for the first wiring 10 , the signal also flows from the back side of the paper to the front side of the paper for the second wiring 20 . Thus, the first wiring 10 and the second wiring 20 are formed such that the direction of the signal flowing through the first wiring 10 and the direction of the signal flowing through the second wiring 20 are substantially the same. Note that when the substrate 5 is viewed in plan, the first wiring 10 and the second wiring 20 may not completely overlap along the direction in which each wiring extends. The first wiring 10 and the second wiring 20 may overlap each other along the direction in which the wirings extend, provided that the angle between the wirings is 30° or less. In other words, if the angle formed by the first wiring 10 and the second wiring 20 is 30° or less when the substrate 5 is viewed from above, the direction of the signal flowing through the first wiring 10 and the signal flowing through the second wiring 20 are different. , the first wiring 10 and the second wiring 20 may be formed so as to be substantially the same direction as the direction of .
　また、第１配線１０と第２配線２０とが磁界結合可能に配置される状態とは、例えば、第１配線１０と第２配線２０との間のギャップ（図２Ａでは左右方向のギャップ、図２Ｂでは上下方向のギャップ）が、第１配線１０または第２配線２０の幅の３倍以下となっている状態のことである。 Further, the state in which the first wiring 10 and the second wiring 20 are arranged so as to be magnetically coupled is, for example, a gap between the first wiring 10 and the second wiring 20 (left-right gap in FIG. 2A, 2B, the vertical gap) is three times or less the width of the first wiring 10 or the second wiring 20 .
　以下では、第１配線１０と第２配線２０とが、磁界結合可能に配置され、第１配線１０を流れる入力端子ｔ１から第１ＦＥＴ３０のドレインへの信号の向きと、第２配線２０を流れる第２ＦＥＴ４０のソースから出力端子ｔ２への信号の向きとが略同じ向きとなるように第１配線１０および第２配線２０が形成されることを、第１配線１０と第２配線２０とが和動結合可能に配置されると記載する。 Below, the first wiring 10 and the second wiring 20 are arranged so as to be magnetically coupled. The first wiring 10 and the second wiring 20 are formed so that the direction of the signal from the source of the 2FET 40 to the output terminal t2 is substantially the same. It is described as being combinably arranged.
　次に、高周波スイッチ１のスイッチオフ時の入力端子ｔ１と出力端子ｔ２との間のアイソレーションについて、図３Ａから図４を用いて説明する。 Next, the isolation between the input terminal t1 and the output terminal t2 when the high-frequency switch 1 is turned off will be described with reference to FIGS. 3A to 4. FIG.
　図３Ａは、スイッチオフ時の高周波スイッチ１を模式的に示す図である。 FIG. 3A is a diagram schematically showing the high-frequency switch 1 when switched off.
　図３Ｂは、スイッチオフ時の高周波スイッチ１の等価回路図である。 FIG. 3B is an equivalent circuit diagram of the high-frequency switch 1 when switched off.
　図３Ａに示されるように、高周波スイッチ１のスイッチオフ時には、第１ＦＥＴ３０および第２ＦＥＴ４０は非導通となるように制御され、第３ＦＥＴ５０は導通となるように制御される。図３Ｂに示されるように、例えば、第１配線１０はインダクタンス成分Ｌ１を有し、第２配線２０はインダクタンス成分Ｌ２を有する。また、第３ＦＥＴ５０が接続された経路（第１ＦＥＴ３０のソースと第２ＦＥＴ４０のドレインとを結ぶ経路とグランドとを結ぶ経路）は、インダクタンス成分Ｌ４を有する。高周波スイッチ１のスイッチオフ時には、第１ＦＥＴ３０はオフ容量Ｃ１を有し、第２ＦＥＴ４０はオフ容量Ｃ２を有し、第３ＦＥＴ５０はオン抵抗Ｒ３を有する。 As shown in FIG. 3A, when the high-frequency switch 1 is switched off, the first FET 30 and the second FET 40 are controlled to be non-conductive, and the third FET 50 is controlled to be conductive. As shown in FIG. 3B, for example, the first wiring 10 has an inductance component L1 and the second wiring 20 has an inductance component L2. The path to which the third FET 50 is connected (the path connecting the source of the first FET 30 and the drain of the second FET 40 and the path connecting the ground) has an inductance component L4. When the high-frequency switch 1 is turned off, the first FET 30 has an off-capacitance C1, the second FET 40 has an off-capacitance C2, and the third FET 50 has an on-resistance R3.
　第１配線１０と第２配線２０とは和動結合可能に配置されているため、第１配線１０および第２配線２０に正の相互インダクタンス（＋Ｍ）が発生する。例えば、第１配線１０および第２配線２０のインダクタンス値を「Ｌ」とすると、正の相互インダクタンスが発生した第１配線１０および第２配線２０のインダクタンス値は、それぞれ「Ｌ＋Ｍ」となる。また、第１配線１０と第２配線２０とが和動結合可能に配置されていることで、第３ＦＥＴ５０が接続された経路に負の相互インダクタンス（－Ｍ）が発生する。この負の相互インダクタンスをインダクタンス成分Ｌ３として図示している。 Since the first wiring 10 and the second wiring 20 are arranged so as to be additively coupled, a positive mutual inductance (+M) is generated in the first wiring 10 and the second wiring 20 . For example, if the inductance values of the first wiring 10 and the second wiring 20 are "L", the inductance values of the first wiring 10 and the second wiring 20 where positive mutual inductance is generated are "L+M", respectively. Further, since the first wiring 10 and the second wiring 20 are arranged so as to be additively coupled, a negative mutual inductance (-M) is generated in the path to which the third FET 50 is connected. This negative mutual inductance is illustrated as an inductance component L3.
　図４は、実施の形態および比較例におけるスイッチオフ時の高周波スイッチのアイソレーション特性（具体的には入力端子ｔ１と出力端子ｔ２との間のアイソレーション特性）を示すグラフである。実線は実施の形態におけるアイソレーション特性を示し、破線は比較例におけるアイソレーション特性を示す。比較例では、実施の形態と同じように、第１ＦＥＴ３０、第２ＦＥＴ４０および第３ＦＥＴ５０が接続されているが、第１配線１０と第２配線２０とは和動結合可能に配置されていない。 FIG. 4 is a graph showing the isolation characteristics of the high-frequency switch (specifically, the isolation characteristics between the input terminal t1 and the output terminal t2) when the switch is turned off in the embodiment and the comparative example. A solid line indicates the isolation characteristic in the embodiment, and a dashed line indicates the isolation characteristic in the comparative example. In the comparative example, the first FET 30, the second FET 40 and the third FET 50 are connected in the same manner as in the embodiment, but the first wiring 10 and the second wiring 20 are not arranged so as to be additively coupled.
　比較例における高周波スイッチのスイッチオフ時には、第１ＦＥＴ３０のオフ容量Ｃ１および第２ＦＥＴ４０のオフ容量Ｃ２が存在するため、高周波信号は入力端子ｔ１側から出力端子ｔ２側へ漏洩し得る。このとき、第１ＦＥＴ３０のソースと第２ＦＥＴ４０のドレインとを結ぶ経路は、第３ＦＥＴ５０を介してグランドに接続されているため、入力端子ｔ１からの信号が第１ＦＥＴ３０を漏洩したとしても、漏洩した信号がグランドに流れ、入力端子ｔ１と出力端子ｔ２との間のアイソレーションを確保できるとも考えられる。しかし、第３ＦＥＴ５０が接続された経路には、第３ＦＥＴ５０のオン抵抗Ｒ３に加え、配線インダクタンス（インダクタンス成分Ｌ４）が存在し、比較例では、高周波では当該経路のインピーダンスが下がらないため、アイソレーションは劣化する。比較例では、７ＧＨｚでのアイソレーションが２８．３０９ｄＢと小さくなっている。 When the high-frequency switch in the comparative example is switched off, the off-capacitance C1 of the first FET 30 and the off-capacitance C2 of the second FET 40 exist, so the high-frequency signal can leak from the input terminal t1 side to the output terminal t2 side. At this time, since the path connecting the source of the first FET 30 and the drain of the second FET 40 is connected to the ground via the third FET 50, even if the signal from the input terminal t1 leaks through the first FET 30, the leaked signal It is also considered that the current flows to the ground and that isolation between the input terminal t1 and the output terminal t2 can be ensured. However, the path to which the third FET 50 is connected has wiring inductance (inductance component L4) in addition to the on-resistance R3 of the third FET 50. In the comparative example, the impedance of the path does not decrease at high frequencies. to degrade. In the comparative example, the isolation at 7 GHz is as small as 28.309 dB.
　実施の形態でも、第３ＦＥＴ５０が接続された経路には、第３ＦＥＴ５０のオン抵抗Ｒ３に加え、配線インダクタンス（インダクタンス成分Ｌ４）が存在する。しかし、第１配線１０と第２配線２０とが和動結合可能に配置されているため、第３ＦＥＴ５０が接続された経路に、負の相互インダクタンスが発生する。このため、当該経路のインダクタンス値が小さくなり、高周波でも当該経路のインピーダンスを下げることができ、アイソレーションを改善することができる。実施の形態では、７ＧＨｚでのアイソレーションが３５．２８１ｄＢと大きくなっている。 In the embodiment, in addition to the on-resistance R3 of the third FET 50, wiring inductance (inductance component L4) also exists in the path to which the third FET 50 is connected. However, since the first wiring 10 and the second wiring 20 are arranged so as to be additively coupled, negative mutual inductance occurs in the path to which the third FET 50 is connected. Therefore, the inductance value of the path becomes small, the impedance of the path can be lowered even at high frequencies, and the isolation can be improved. In the embodiment, the isolation at 7 GHz is as large as 35.281 dB.
　このように、第３ＦＥＴ５０が接続された経路に、負の相互インダクタンスが発生することで、当該経路のインダクタンス値（言い換えるとインピーダンス値）が小さくなり、高周波スイッチ１のスイッチオフ時には、第１ＦＥＴ３０と第２ＦＥＴ４０とを結ぶ経路が小さなインピーダンス値の経路を介してグランドと接続されることとなる。このため、入力端子ｔ１からの信号が第１ＦＥＴ３０を漏洩したとしても、漏洩した信号をグランドへ流しやすくなり、入力端子ｔ１と出力端子ｔ２との間のアイソレーションを確保することができる。 In this way, negative mutual inductance is generated in the path to which the third FET 50 is connected, so that the inductance value (in other words, the impedance value) of the path becomes small, and when the high-frequency switch 1 is turned off, the first FET 30 and the first FET 30 The path connecting the 2FET 40 is connected to the ground through a path with a small impedance value. Therefore, even if a signal from the input terminal t1 leaks through the first FET 30, the leaked signal can easily flow to the ground, and isolation between the input terminal t1 and the output terminal t2 can be ensured.
　次に、高周波スイッチ１のスイッチオン時の入力端子ｔ１と出力端子ｔ２との間の挿入損失について、図５Ａから図６Ｃを用いて説明する。 Next, the insertion loss between the input terminal t1 and the output terminal t2 when the high-frequency switch 1 is switched on will be described with reference to FIGS. 5A to 6C.
　図５Ａは、スイッチオン時の高周波スイッチ１を模式的に示す図である。 FIG. 5A is a diagram schematically showing the high-frequency switch 1 when switched on.
　図５Ｂは、スイッチオン時の高周波スイッチ１の等価回路図である。 FIG. 5B is an equivalent circuit diagram of the high-frequency switch 1 when switched on.
　図５Ａに示されるように、高周波スイッチ１のスイッチオン時には、第１ＦＥＴ３０および第２ＦＥＴ４０は導通となるように制御され、第３ＦＥＴ５０は非導通となるように制御される。図５Ｂに示されるように、例えば、第１ＦＥＴ３０はオン抵抗Ｒ１を有し、第２ＦＥＴ４０はオン抵抗Ｒ２を有し、第３ＦＥＴ５０はオフ容量Ｃ３を有する。 As shown in FIG. 5A, when the high-frequency switch 1 is switched on, the first FET 30 and the second FET 40 are controlled to be conductive, and the third FET 50 is controlled to be non-conductive. As shown in FIG. 5B, for example, the first FET 30 has an on-resistance R1, the second FET 40 has an on-resistance R2, and the third FET 50 has an off-capacitance C3.
　第１配線１０と第２配線２０とは和動結合可能に配置されているため、第１配線１０および第２配線２０に正の相互インダクタンス（＋Ｍ）が発生する。また、第１配線１０と第２配線２０とが和動結合可能に配置されていることで、第３ＦＥＴ５０が接続された経路に負の相互インダクタンス（－Ｍ）が発生する。 Since the first wiring 10 and the second wiring 20 are arranged so as to be additively coupled, a positive mutual inductance (+M) is generated in the first wiring 10 and the second wiring 20 . Further, since the first wiring 10 and the second wiring 20 are arranged so as to be additively coupled, a negative mutual inductance (-M) is generated in the path to which the third FET 50 is connected.
　図６Ａは、実施の形態および比較例におけるスイッチオン時の高周波スイッチのリターンロス特性を示すグラフである。実線は実施の形態におけるリターンロス特性を示し、破線は比較例におけるリターンロス特性を示す。 FIG. 6A is a graph showing return loss characteristics of the high-frequency switch when switched on in the embodiment and the comparative example. A solid line indicates return loss characteristics in the embodiment, and a dashed line indicates return loss characteristics in the comparative example.
　図６Ｂは、実施の形態および比較例におけるスイッチオン時の高周波スイッチのインピーダンス特性を示すスミスチャートである。実線は実施の形態におけるインピーダンス特性を示し、破線は比較例におけるインピーダンス特性を示す。 FIG. 6B is a Smith chart showing the impedance characteristics of the high-frequency switch when switched on in the embodiment and the comparative example. A solid line indicates the impedance characteristic in the embodiment, and a dashed line indicates the impedance characteristic in the comparative example.
　図６Ｃは、実施の形態および比較例におけるスイッチオン時の高周波スイッチの通過特性を示すグラフである。実線は実施の形態における通過特性を示し、破線は比較例における通過特性を示す。 FIG. 6C is a graph showing pass characteristics of the high-frequency switch when switched on in the embodiment and the comparative example. A solid line indicates the pass characteristic in the embodiment, and a dashed line indicates the pass characteristic in the comparative example.
　上述したように、比較例では、実施の形態と同じように、第１ＦＥＴ３０、第２ＦＥＴ４０および第３ＦＥＴ５０が接続されているが、第１配線１０と第２配線２０とは和動結合可能に配置されていない。 As described above, in the comparative example, the first FET 30, the second FET 40, and the third FET 50 are connected in the same manner as in the embodiment, but the first wiring 10 and the second wiring 20 are arranged so as to be additively coupled. not
　高周波スイッチ１のスイッチオン時には、第３ＦＥＴ５０のオフ容量Ｃ３が存在するため、高周波スイッチ１の入出力インピーダンスが容量性を示し得るが、第１配線１０および第２配線２０は、インダクタンス成分を有しているため、入出力インピーダンスの不整合を解消することができる場合がある。しかし、不整合を十分に解消できない場合もある。例えば、不整合は、第１配線１０および第２配線２０の長さを長くすることでも解消することができる場合があるが、その場合には、第１配線１０および第２配線２０の抵抗成分が大きくなり、また、高周波スイッチ１が大型化してしまう。 Since the off-capacitance C3 of the third FET 50 exists when the high-frequency switch 1 is switched on, the input/output impedance of the high-frequency switch 1 may exhibit capacitiveness, but the first wiring 10 and the second wiring 20 have an inductance component. Therefore, in some cases, input/output impedance mismatch can be eliminated. However, in some cases, the inconsistency cannot be sufficiently resolved. For example, the mismatch may sometimes be eliminated by lengthening the lengths of the first wiring 10 and the second wiring 20. In that case, the resistance components of the first wiring 10 and the second wiring 20 becomes large, and the high-frequency switch 1 becomes large.
　比較例では、図６Ｂに示されるように、不整合が解消されておらず、高周波スイッチの入出力インピーダンスが容量性を示している。このため、図６Ａに示されるように、比較例では、実施の形態よりもリターンロスが悪くなっていることがわかる。その結果、図６Ｃに示されるように、比較例では、７ＧＨｚでの挿入損失が０．３１９ｄＢと大きなっている。 In the comparative example, as shown in FIG. 6B, the mismatch is not eliminated and the input/output impedance of the high frequency switch exhibits capacitiveness. Therefore, as shown in FIG. 6A, the return loss is worse in the comparative example than in the embodiment. As a result, as shown in FIG. 6C, the comparative example has a large insertion loss of 0.319 dB at 7 GHz.
　一方で、実施の形態では、第１配線１０および第２配線２０の長さは、比較例におけるものと同じ長さであるが、図６Ｂに示されるように、不整合が解消されている。これは、第１配線１０と第２配線２０とが和動結合可能に配置されているためである。第１配線１０と第２配線２０とが和動結合可能に配置されていることで、第１配線１０および第２配線２０に、正の相互インダクタンスが発生する。このため、実施の形態では、第１配線１０および第２配線２０の長さが比較例と同じであるが、正の相互インダクタンスが発生していることによって、不整合が解消されている。これにより、図６Ａに示されるように、実施の形態では、比較例よりもリターンロスが改善していることがわかる。その結果、図６Ｃに示されるように、実施の形態では、７ＧＨｚでの挿入損失が０．１９４ｄＢと小さくなっている。 On the other hand, in the embodiment, the lengths of the first wiring 10 and the second wiring 20 are the same as in the comparative example, but the mismatch is eliminated as shown in FIG. 6B. This is because the first wiring 10 and the second wiring 20 are arranged so as to be additively coupled. Positive mutual inductance is generated in the first wiring 10 and the second wiring 20 by arranging the first wiring 10 and the second wiring 20 so as to be summatively coupled. Therefore, in the embodiment, although the lengths of the first wiring 10 and the second wiring 20 are the same as in the comparative example, the mismatch is eliminated by generating positive mutual inductance. Accordingly, as shown in FIG. 6A, it can be seen that the return loss is improved in the embodiment as compared with the comparative example. As a result, as shown in FIG. 6C, the embodiment has a low insertion loss of 0.194 dB at 7 GHz.
　なお、高周波スイッチ１を複数用いることで、図７Ａに示されるようなＳＰｎＴ（Ｓｉｎｇｌｅ　Ｐｏｌｅ　ｎ　Ｔｈｒｏｗ）のスイッチや、図７Ｂに示されるようなｍＰｎＴのスイッチを実現してもよい（ｍ、ｎは２以上の整数）。 By using a plurality of high-frequency switches 1, an SPnT (Single Pole n Throw) switch as shown in FIG. 7A or an mPnT switch as shown in FIG. 7B may be realized (m and n are integer of 2 or more).
　図７Ａおよび図７Ｂは、実施の形態に係る高周波スイッチ１の適用例を示す図である。 7A and 7B are diagrams showing application examples of the high-frequency switch 1 according to the embodiment.
　例えば、図７Ａに示されるように、３つの高周波スイッチ１の入力端子ｔ１側を共通接続することで、ＳＰ３Ｔのスイッチを実現してもよい。なお、出力端子ｔ２側が共通接続されてもよい。また、例えば、図７Ｂに示されるように、３つの高周波スイッチ１の出力端子ｔ２側と、３つの高周波スイッチ１の入力端子ｔ１側とが共通接続されることで、３Ｐ３Ｔのスイッチを実現してもよい。 For example, as shown in FIG. 7A, the SP3T switch may be realized by connecting the input terminal t1 sides of the three high frequency switches 1 in common. Note that the output terminal t2 side may be connected in common. Further, for example, as shown in FIG. 7B, the output terminal t2 side of the three high frequency switches 1 and the input terminal t1 side of the three high frequency switches 1 are commonly connected to realize a 3P3T switch. good too.
　以上説明したように、高周波スイッチ１は、入力端子ｔ１と、出力端子ｔ２と、第１ＦＥＴ３０と、第２ＦＥＴ４０と、第３ＦＥＴ５０と、第１配線１０と、第２配線２０と、を備える。第１配線１０は、入力端子ｔ１と第１ＦＥＴ３０のドレインとの間に接続され、第２配線２０は、出力端子ｔ２と第２ＦＥＴ４０のソースとの間に接続され、第１ＦＥＴ３０のソースと第２ＦＥＴ４０のドレインとが接続され、第３ＦＥＴ５０のドレインは、第１ＦＥＴ３０のソースおよび第２ＦＥＴ４０のドレインと接続され、第３ＦＥＴ５０のソースは、グランドに接続される。第１配線１０の少なくとも一部と第２配線２０の少なくとも一部とは、磁界結合可能に配置され、第１配線１０の少なくとも一部における入力端子ｔ１から第１ＦＥＴ３０のドレインへの信号の流れる向きと、第２配線２０の少なくとも一部における第２ＦＥＴ４０のソースから出力端子ｔ２への信号の流れる向きとが略同じ向きとなるように、第１配線１０および第２配線２０は形成される。 As described above, the high-frequency switch 1 includes the input terminal t1, the output terminal t2, the first FET 30, the second FET 40, the third FET 50, the first wiring 10, and the second wiring 20. The first wiring 10 is connected between the input terminal t1 and the drain of the first FET 30, the second wiring 20 is connected between the output terminal t2 and the source of the second FET 40, and the source of the first FET 30 and the drain of the second FET 40 are connected. The drain of the third FET 50 is connected to the source of the first FET 30 and the drain of the second FET 40, and the source of the third FET 50 is connected to the ground. At least part of the first wiring 10 and at least part of the second wiring 20 are arranged so as to be magnetically coupled, and the direction of signal flow from the input terminal t1 in at least part of the first wiring 10 to the drain of the first FET 30 The first wiring 10 and the second wiring 20 are formed such that the direction of signal flow from the source of the second FET 40 to the output terminal t2 in at least a part of the second wiring 20 is substantially the same.
　第１配線１０の少なくとも一部と第２配線２０の少なくとも一部とが磁界結合可能に配置されており、第１配線１０の少なくとも一部における入力端子ｔ１から第１ＦＥＴ３０のドレインへの信号の流れる向きと、第２配線２０の少なくとも一部における第２ＦＥＴ４０のソースから出力端子ｔ２への信号の流れる向きとが略同じ向きとなるように第１配線１０および第２配線２０が形成されるため、第１配線１０および第２配線２０に、正の相互インダクタンスが発生する。高周波スイッチ１のスイッチオン時には、第３ＦＥＴ５０のオフ容量Ｃ３による高周波スイッチ１の入出力インピーダンスの不整合が生じ得るが、第１配線１０および第２配線２０に発生する正の相互インダクタンスによって不整合を解消することができ、高周波スイッチ１のスイッチオン時の挿入損失を低減することができる。例えば、不整合は、第１配線１０および第２配線２０の長さを長くして第１配線１０および第２配線２０のインダクタンス成分を大きくすることでも解消することができる場合があるが、その場合には、第１配線１０および第２配線２０の抵抗成分が大きくなり、また、高周波スイッチ１が大型化してしまう。つまり、本発明では、第１配線１０および第２配線２０の抵抗成分が大きくなったり、高周波スイッチ１が大型化したりすることを抑制しつつ、高周波スイッチ１のスイッチオン時の挿入損失を低減することができる。 At least part of the first wiring 10 and at least part of the second wiring 20 are arranged so as to be magnetically coupled, and a signal flows from the input terminal t1 of at least part of the first wiring 10 to the drain of the first FET 30. Since the first wiring 10 and the second wiring 20 are formed such that the direction of signal flow from the source of the second FET 40 to the output terminal t2 in at least a part of the second wiring 20 is substantially the same as the direction of signal flow, A positive mutual inductance is generated between the first wiring 10 and the second wiring 20 . When the high-frequency switch 1 is turned on, the input/output impedance mismatch of the high-frequency switch 1 may occur due to the off-capacitance C3 of the third FET 50. can be eliminated, and the insertion loss when the high-frequency switch 1 is turned on can be reduced. For example, the mismatch may sometimes be eliminated by lengthening the lengths of the first wiring 10 and the second wiring 20 to increase the inductance components of the first wiring 10 and the second wiring 20; In this case, the resistance components of the first wiring 10 and the second wiring 20 are increased, and the high-frequency switch 1 is increased in size. In other words, in the present invention, the insertion loss of the high-frequency switch 1 is reduced when the high-frequency switch 1 is switched on, while suppressing an increase in the resistance components of the first wiring 10 and the second wiring 20 and an increase in the size of the high-frequency switch 1. be able to.
　また、第１配線１０の少なくとも一部と第２配線２０の少なくとも一部とが磁界結合可能に配置されており、第１配線１０の少なくとも一部における入力端子ｔ１から第１ＦＥＴ３０のドレインへの信号の流れる向きと、第２配線２０の少なくとも一部における第２ＦＥＴ４０のソースから出力端子ｔ２への信号の流れる向きとが略同じ向きとなるように第１配線１０および第２配線２０が形成されるため、第３ＦＥＴ５０が接続された経路（第１ＦＥＴ３０のソースと第２ＦＥＴ４０のドレインとを結ぶ経路とグランドとを結ぶ経路）に、負の相互インダクタンスが発生する。これにより、当該経路のインダクタンス値（言い換えるとインピーダンス値）が小さくなり、高周波スイッチ１のスイッチオフ時には、第１ＦＥＴ３０と第２ＦＥＴ４０とを結ぶ経路が小さなインピーダンス値の経路を介してグランドと接続されることとなる。このため、入力端子ｔ１からの信号が第１ＦＥＴ３０を漏洩したとしても、漏洩した信号をグランドへ流しやすくなり、入力端子ｔ１と出力端子ｔ２との間のアイソレーションを確保することができる。 At least a portion of the first wiring 10 and at least a portion of the second wiring 20 are arranged so as to be magnetically coupled. and the direction of signal flow from the source of the second FET 40 to the output terminal t2 in at least a part of the second wiring 20 are substantially the same. Therefore, a negative mutual inductance occurs in the path to which the third FET 50 is connected (the path connecting the source of the first FET 30 and the drain of the second FET 40 and the path connecting the ground). As a result, the inductance value (in other words, the impedance value) of the path is reduced, and when the high-frequency switch 1 is switched off, the path connecting the first FET 30 and the second FET 40 is connected to the ground through a path with a small impedance value. becomes. Therefore, even if a signal from the input terminal t1 leaks through the first FET 30, the leaked signal can easily flow to the ground, and isolation between the input terminal t1 and the output terminal t2 can be ensured.
　以上のように、スイッチオフ時の入力端子ｔ１と出力端子ｔ２との間のアイソレーションの確保およびスイッチオン時の挿入損失の低減を両立できる。 As described above, it is possible to ensure isolation between the input terminal t1 and the output terminal t2 when the switch is turned off and to reduce the insertion loss when the switch is turned on.
　例えば、高周波スイッチ１は、さらに、基板５を備え、第１配線１０の少なくとも一部および第２配線２０の少なくとも一部は、基板５の同じ層に形成されていてもよい。 For example, the high-frequency switch 1 may further include a substrate 5 , and at least a portion of the first wiring 10 and at least a portion of the second wiring 20 may be formed on the same layer of the substrate 5 .
　このように、第１配線１０の少なくとも一部および第２配線２０の少なくとも一部を基板５の同じ層に形成することで、第１配線１０の少なくとも一部と第２配線２０の少なくとも一部とを磁界結合可能に配置することができる。 By forming at least a portion of the first wiring 10 and at least a portion of the second wiring 20 in the same layer of the substrate 5 in this way, at least a portion of the first wiring 10 and at least a portion of the second wiring 20 can be arranged so as to be magnetically coupled.
　例えば、高周波スイッチ１は、さらに、基板５を備え、第１配線１０の少なくとも一部および第２配線２０の少なくとも一部は、基板５の異なる層に形成され、基板５を平面視したとき、第１配線１０の少なくとも一部と第２配線２０の少なくとも一部とは重複していてもよい。 For example, the high-frequency switch 1 further includes a substrate 5, and at least a portion of the first wiring 10 and at least a portion of the second wiring 20 are formed in different layers of the substrate 5. When the substrate 5 is viewed from above, At least part of the first wiring 10 and at least part of the second wiring 20 may overlap.
　このように、第１配線１０の少なくとも一部および第２配線２０の少なくとも一部を基板５の異なる層において、基板５を平面視したときに重複するように形成することで、第１配線１０の少なくとも一部と第２配線２０の少なくとも一部とを磁界結合可能に配置することができる。 Thus, by forming at least a portion of the first wiring 10 and at least a portion of the second wiring 20 in different layers of the substrate 5 so as to overlap when the substrate 5 is viewed from above, the first wiring 10 and at least part of the second wiring 20 can be arranged so as to be magnetically coupled.
　高周波スイッチ１は、入力端子ｔ１と、出力端子ｔ２と、第１ＦＥＴ３０と、第２ＦＥＴ４０と、第３ＦＥＴ５０と、第１配線１０と、第２配線２０と、を備える。第１配線１０は、入力端子ｔ１と第１ＦＥＴ３０のドレインとの間に接続され、第２配線２０は、出力端子ｔ２と第２ＦＥＴ４０のソースとの間に接続され、第１ＦＥＴ３０のソースと第２ＦＥＴ４０のドレインとが接続され、第３ＦＥＴ５０のドレインは、第１ＦＥＴ３０のソースおよび第２ＦＥＴ４０のドレインと接続され、第３ＦＥＴ５０のソースは、グランドに接続される。第１配線１０の少なくとも一部と第２配線２０の少なくとも一部とは、和動結合可能に配置される。 The high-frequency switch 1 includes an input terminal t1, an output terminal t2, a first FET 30, a second FET 40, a third FET 50, a first wiring 10, and a second wiring 20. The first wiring 10 is connected between the input terminal t1 and the drain of the first FET 30, the second wiring 20 is connected between the output terminal t2 and the source of the second FET 40, and the source of the first FET 30 and the drain of the second FET 40 are connected. The drain of the third FET 50 is connected to the source of the first FET 30 and the drain of the second FET 40, and the source of the third FET 50 is connected to the ground. At least part of the first wiring 10 and at least part of the second wiring 20 are arranged so as to be additively coupled.
　第１配線１０の少なくとも一部と第２配線２０の少なくとも一部とが和動結合可能に配置されているため、第１配線１０および第２配線２０に、正の相互インダクタンスが発生する。高周波スイッチ１のスイッチオン時には、第３ＦＥＴ５０のオフ容量Ｃ３による高周波スイッチ１の入出力インピーダンスの不整合が生じ得るが、第１配線１０および第２配線２０に発生する正の相互インダクタンスによって当該不整合を解消することができ、高周波スイッチ１のスイッチオン時の挿入損失を低減することができる。例えば、当該不整合は、第１配線１０および第２配線２０の長さを長くして第１配線１０および第２配線２０のインダクタンス成分を大きくすることでも解消することはできるが、その場合には、第１配線１０および第２配線２０の抵抗成分が大きくなり、また、高周波スイッチ１が大型化してしまう。つまり、本発明では、第１配線１０および第２配線２０の抵抗成分が大きくなったり、高周波スイッチ１が大型化したりすることを抑制しつつ、高周波スイッチ１のスイッチオン時の挿入損失を低減することができる。 Since at least a portion of the first wiring 10 and at least a portion of the second wiring 20 are arranged so as to be coupled dynamically, positive mutual inductance is generated between the first wiring 10 and the second wiring 20 . When the high-frequency switch 1 is switched on, mismatching of the input/output impedance of the high-frequency switch 1 may occur due to the off-capacitance C3 of the third FET 50. can be eliminated, and the insertion loss when the high-frequency switch 1 is turned on can be reduced. For example, the mismatch can be eliminated by lengthening the lengths of the first wiring 10 and the second wiring 20 to increase the inductance components of the first wiring 10 and the second wiring 20, but in that case , the resistance components of the first wiring 10 and the second wiring 20 are increased, and the high-frequency switch 1 is increased in size. In other words, in the present invention, the insertion loss of the high-frequency switch 1 is reduced when the high-frequency switch 1 is switched on, while suppressing an increase in the resistance components of the first wiring 10 and the second wiring 20 and an increase in the size of the high-frequency switch 1. be able to.
　また、第１配線１０の少なくとも一部と第２配線２０の少なくとも一部とが和動結合可能に配置されているため、第３ＦＥＴ５０が接続された経路（第１ＦＥＴ３０のソースと第２ＦＥＴ４０のドレインとを結ぶ経路とグランドとを結ぶ経路）に、負の相互インダクタンスが発生する。これにより、当該経路のインダクタンス値（言い換えるとインピーダンス値）が小さくなり、高周波スイッチ１のスイッチオフ時には、第１ＦＥＴ３０と第２ＦＥＴ４０とを結ぶ経路が小さなインピーダンス値の経路を介してグランドと接続されることとなる。このため、入力端子ｔ１からの信号が第１ＦＥＴ３０を漏洩したとしても、漏洩した信号をグランドへ流しやすくなり、入力端子ｔ１と出力端子ｔ２との間のアイソレーションを確保することができる。 Further, since at least a part of the first wiring 10 and at least a part of the second wiring 20 are arranged so as to be able to be combined dynamically, the path to which the third FET 50 is connected (the source of the first FET 30 and the drain of the second FET 40) and ground), a negative mutual inductance occurs. As a result, the inductance value (in other words, the impedance value) of the path is reduced, and when the high-frequency switch 1 is switched off, the path connecting the first FET 30 and the second FET 40 is connected to the ground through a path with a small impedance value. becomes. Therefore, even if a signal from the input terminal t1 leaks through the first FET 30, the leaked signal can easily flow to the ground, and isolation between the input terminal t1 and the output terminal t2 can be ensured.
　以上のように、スイッチオフ時の入力端子ｔ１と出力端子ｔ２との間のアイソレーションの確保およびスイッチオン時の挿入損失の低減を両立できる。 As described above, it is possible to ensure isolation between the input terminal t1 and the output terminal t2 when the switch is turned off and to reduce the insertion loss when the switch is turned on.
　（その他の実施の形態）
　以上、本発明に係る高周波スイッチ１について、実施の形態を挙げて説明したが、本発明は、上記実施の形態に限定されるものではない。上記実施の形態における任意の構成要素を組み合わせて実現される別の実施の形態や、上記実施の形態に対して本発明の主旨を逸脱しない範囲で当業者が思いつく各種変形を施して得られる変形例や、本発明に係る高周波スイッチ１を内蔵した各種機器も本発明に含まれる。 (Other embodiments)
Although the high frequency switch 1 according to the present invention has been described above with reference to the embodiments, the present invention is not limited to the above embodiments. Another embodiment realized by combining arbitrary constituent elements in the above embodiment, and a modification obtained by applying various modifications to the above embodiment within the scope of the present invention that a person skilled in the art can think of For example, the present invention also includes various devices incorporating the high-frequency switch 1 according to the present invention.
　本発明は、高周波スイッチとして、携帯電話等の通信機器に広く利用できる。 The present invention can be widely used as a high-frequency switch for communication equipment such as mobile phones.
　１　高周波スイッチ
　５　基板
　１０　第１配線
　２０　第２配線
　３０　第１ＦＥＴ
　４０　第２ＦＥＴ
　５０　第３ＦＥＴ
　６０、７０、８０　抵抗
　Ｃ１、Ｃ２、Ｃ３　オフ容量
　Ｌ１、Ｌ２、Ｌ３、Ｌ４　インダクタンス成分
　Ｒ１、Ｒ２、Ｒ３　オン抵抗
　ｔ１　入力端子
　ｔ２　出力端子
　ｔ３、ｔ４　制御端子 1 high-frequency switch 5 substrate 10 first wiring 20 second wiring 30 first FET
40 Second FET
50 Third FET
60, 70, 80 resistance C1, C2, C3 off capacitance L1, L2, L3, L4 inductance component R1, R2, R3 on resistance t1 input terminal t2 output terminal t3, t4 control terminal

Claims (4)

  1. 　入力端子と、
    　出力端子と、
    　第１ＦＥＴと、
    　第２ＦＥＴと、
    　第３ＦＥＴと、
    　第１配線と、
    　第２配線と、を備え、
    　前記第１配線は、前記入力端子と前記第１ＦＥＴのドレインとの間に接続され、
    　前記第２配線は、前記出力端子と前記第２ＦＥＴのソースとの間に接続され、
    　前記第１ＦＥＴのソースと前記第２ＦＥＴのドレインとが接続され、
    　前記第３ＦＥＴのドレインは、前記第１ＦＥＴのソースおよび前記第２ＦＥＴのドレインと接続され、
    　前記第３ＦＥＴのソースは、グランドに接続され、
    　前記第１配線の少なくとも一部と前記第２配線の少なくとも一部とは、磁界結合可能に配置され、
    　前記第１配線の少なくとも一部における前記入力端子から前記第１ＦＥＴのドレインへの信号の流れる向きと、前記第２配線の少なくとも一部における前記第２ＦＥＴのソースから前記出力端子への信号の流れる向きとが略同じ向きとなるように、前記第１配線および前記第２配線は形成される、
    　高周波スイッチ。     an input terminal;
    an output terminal;
    a first FET;
    a second FET;
    a third FET;
    a first wiring;
    a second wiring,
    the first wiring is connected between the input terminal and the drain of the first FET;
    the second wiring is connected between the output terminal and the source of the second FET;
    the source of the first FET and the drain of the second FET are connected;
    the drain of the third FET is connected to the source of the first FET and the drain of the second FET;
    the source of the third FET is connected to ground;
    At least part of the first wiring and at least part of the second wiring are arranged so as to be magnetically coupled,
    A direction of signal flow from the input terminal to the drain of the first FET on at least part of the first wiring, and a direction of signal flow from the source of the second FET to the output terminal on at least part of the second wiring. The first wiring and the second wiring are formed so that the
    high frequency switch.
  2. 　さらに、基板を備え、
    　前記第１配線の少なくとも一部および前記第２配線の少なくとも一部は、前記基板の同じ層に形成される、
    　請求項１に記載の高周波スイッチ。     Further comprising a substrate,
    at least part of the first wiring and at least part of the second wiring are formed in the same layer of the substrate;
    A high frequency switch according to claim 1.
  3. 　さらに、複数の誘電体層を有する基板を備え、
    　前記第１配線の少なくとも一部および前記第２配線の少なくとも一部は、前記基板の異なる層に形成され、
    　前記基板を平面視したとき、前記第１配線の少なくとも一部と前記第２配線の少なくとも一部とは重複している
    　請求項１に記載の高周波スイッチ。     further comprising a substrate having a plurality of dielectric layers;
    at least part of the first wiring and at least part of the second wiring are formed in different layers of the substrate;
    2. The high-frequency switch according to claim 1, wherein at least a portion of the first wiring and at least a portion of the second wiring overlap when the substrate is viewed in plan.
  4. 　入力端子と、
    　出力端子と、
    　第１ＦＥＴと、
    　第２ＦＥＴと、
    　第３ＦＥＴと、
    　第１配線と、
    　第２配線と、を備え、
    　前記第１配線は、前記入力端子と前記第１ＦＥＴのドレインとの間に接続され、
    　前記第２配線は、前記出力端子と前記第２ＦＥＴのソースとの間に接続され、
    　前記第１ＦＥＴのソースと前記第２ＦＥＴのドレインとが接続され、
    　前記第３ＦＥＴのドレインは、前記第１ＦＥＴのソースおよび前記第２ＦＥＴのドレインと接続され、
    　前記第３ＦＥＴのソースは、グランドに接続され、
    　前記第１配線の少なくとも一部と前記第２配線の少なくとも一部とは、和動結合可能に配置される、
    　高周波スイッチ。     an input terminal;
    an output terminal;
    a first FET;
    a second FET;
    a third FET;
    a first wiring;
    a second wiring,
    the first wiring is connected between the input terminal and the drain of the first FET;
    the second wiring is connected between the output terminal and the source of the second FET;
    the source of the first FET and the drain of the second FET are connected;
    the drain of the third FET is connected to the source of the first FET and the drain of the second FET;
    the source of the third FET is connected to ground;
    At least part of the first wiring and at least part of the second wiring are arranged so as to be additively coupled,
    high frequency switch.
PCT/JP2022/038005 2021-10-19 2022-10-12 High-frequency switch WO2023068127A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010258150A (en) * 2009-04-23 2010-11-11 Renesas Electronics Corp Semiconductor device
WO2016030942A1 (en) * 2014-08-25 2016-03-03 ルネサスエレクトロニクス株式会社 Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010258150A (en) * 2009-04-23 2010-11-11 Renesas Electronics Corp Semiconductor device
WO2016030942A1 (en) * 2014-08-25 2016-03-03 ルネサスエレクトロニクス株式会社 Semiconductor device

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