JP2010258150A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of suppressing generation of higher-order harmonic distortion in transmitting. <P>SOLUTION: ON-resistance Ron of a transistor having changed from an OFF state to an ON state can be reduced by increasing an electric potential Vgs1 of the transistor in an OFF state from -Vant to -Vant+1. In other words, the ON-resistance Ron of the transistor having changed from an OFF state to an ON state can be reduced by decreasing the absolute value of the electric potential Vgs1 of the transistor in an OFF state from Vant to Vant-1. As a result, an increase in higher-order harmonic distortion generated from the transistor in an ON state can be suppressed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device including an antenna switch mounted on a mobile communication device or the like.

  Japanese Unexamined Patent Application Publication No. 2008-111131 (Patent Document 1) discloses an antenna switch for reducing high-order harmonic distortion in an antenna switch including an FET (Field Effect Transistor) between an antenna terminal and a plurality of signal terminals. A technique for taking a circuit configuration for increasing the voltage is described. In other words, in order to reduce high-order harmonic distortion, a technique is described in which an off-state FET is turned into a deep off-state.

  Japanese Patent Laid-Open No. 2008-17170 (Patent Document 2) discloses that in a switch circuit composed of a plurality of stages of FETs, at least one threshold voltage of the FET is set to another FET in order to reduce high-order harmonic distortion. A technique for setting a higher value is described.

JP 2008-11131 A JP 2008-17170 A

  In recent mobile phones, not only a voice call function but also various application functions are added. That is, functions other than the voice call function such as viewing of distributed music using a mobile phone, moving image transmission, and data transfer are added to the mobile phone. With such multi-functionality of mobile phones, frequency bands (GSM (Global System for Mobile communications) band, PCS (Personal Communication Services) band, etc.) and modulation systems (GSM, EDGE (Enhanced Data rates for) are being developed around the world. GSM Evolution), WCDMA (Wideband Code Division Multiplex Access), etc.) are supposed to exist. Therefore, the mobile phone needs to support transmission / reception signals corresponding to a plurality of different frequency bands and different modulation schemes. For this reason, in mobile phones, transmission and reception of these transmission / reception signals are shared by one antenna, and the connection to the antenna is switched by an antenna switch.

  For example, in a GSM mobile phone, the power of a transmission signal is usually high, such as exceeding 1 W, and the antenna switch has a high quality of a high-power transmission signal and other frequencies. Performance that reduces the generation of interference waves (high-order harmonic distortion) that adversely affect band communications is required. For this reason, when a field effect transistor (FET) is used as a switching element constituting the antenna switch, the field effect transistor is required to have not only high withstand voltage characteristics but also performance capable of reducing high-order harmonic distortion.

  The antenna switch has a configuration in which, for example, a transmission FET that functions as a switch is connected between the antenna terminal and the transmission terminal, and a reception FET that functions as a switch is connected between the antenna terminal and the reception terminal. Yes. When transmitting a transmission signal from an antenna, the transmission FET is turned on and the reception FET is turned off. On the other hand, when the reception signal is received from the antenna, the transmission FET is turned off and the reception FET is turned on. Therefore, in the antenna switch, there are FETs that are turned on and FETs that are turned off both when the transmission signal is transmitted and when the reception signal is received.

  At this time, high-order harmonic distortion generated from the antenna switch is generated from both the turned-on FET and the turned-off FET. High-order harmonic distortion generated from the FET that is turned off can be reduced by setting the FET that is turned off to a deep off state. In other words, the higher the gate electrode potential (referred to as reverse bias) relative to the source region of the FET that is turned off and the larger the absolute value of the gate electrode potential, the higher the order generated from the FET that is turned off. Harmonic distortion can be reduced. This is because the non-linearity of the capacitance between the gate electrode and the source region (or the drain region) becomes smaller as the reverse bias is increased in the FET that is turned off. On the other hand, the high-order harmonic distortion generated from the FET that is turned on has a positive correlation with the on-resistance having non-linearity, and as the on-resistance increases, the generated higher-order harmonic distortion also increases. Thus, in order to suppress high-order harmonic distortion generated from the antenna switch, both high-order harmonic distortion generated from the FET that is turned off and high-order harmonic distortion generated from the FET that is turned on. It is understood that it is necessary to suppress this.

  Here, as a communication method of the mobile phone, for example, there is a time division multiple access method (TDMA method). The time division multiple access method is a technology that divides a carrier frequency used for transmission into units called time slots and enables a plurality of communications at the same frequency. For example, in the time division multiple access method, there are 8 time slots (576.9 μsec) in one frame (4.615 msec), and multiple communication is possible by assigning transmission mode and reception mode to each time slot. It is what. At this time, the inventor newly found out that there is a difference in the magnitude of high-order harmonic distortion generated from the antenna switch depending on the combination of modes assigned to a plurality of time slots. Specifically, the higher order harmonic distortion that occurs when the time slot immediately after the reception mode is the transmission mode is, for example, the higher order that occurs when the test mode (local mode) in which only the transmission mode exists is present. The present inventor has found that the distortion becomes larger than the harmonic distortion. That is, the present inventor has found that there is a problem that high-order harmonic distortion increases when switching from the reception mode to the transmission mode.

  The objective of this invention is providing the technique which can suppress generation | occurrence | production of the high-order harmonic distortion at the time of transmission.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a typical embodiment includes: (a) an antenna terminal electrically connected to an antenna; (b) a transmission terminal that transmits a transmission signal; and (c) a reception terminal that transmits a reception signal. With. (D) a transmission FET connected between the transmission terminal and the antenna terminal and functioning as a switch; and (e) a reception function connected as a switch between the reception terminal and the antenna terminal. And (f) a control terminal for inputting a control signal for controlling on / off of the transmission FET and the reception FET. At this time, the transmission FET includes (d1) a pair of first source region and first drain region formed separately from each other in the semiconductor substrate, and (d2) the first source region and the first drain region. And a first gate electrode formed on the semiconductor substrate and connected to the control terminal. On the other hand, the receiving FET includes: (e1) a pair of second source region and second drain region formed separately from each other in the semiconductor substrate; and (e2) the second source region and the second drain region. And a second gate electrode formed on the semiconductor substrate and connected to the control terminal. Here, when the transmission signal is transmitted from the antenna, the control signal input from the control terminal is used as a potential of the first gate electrode based on the first source region of the transmission FET. Applying a first potential higher than a threshold voltage to turn on the transmission FET, and as a potential of the second gate electrode with respect to the second source region of the reception FET, a threshold value A second potential lower than the voltage is applied to turn off the receiving FET. On the other hand, when receiving the received signal from the antenna, the control signal input from the control terminal, as a potential of the first gate electrode with respect to the first source region of the transmission FET, A third potential lower than the threshold voltage is applied to turn off the transmission FET, and a threshold voltage is set as the potential of the second gate electrode with respect to the second source region of the reception FET. The receiving FET is turned on by applying a higher fourth potential. At this time, the absolute value of the third potential is smaller than the absolute value of the second potential.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Higher-order harmonic distortion generated from the antenna switch during transmission can be suppressed.

It is a block diagram which shows the structure of the transmission / reception part of a mobile telephone. It is a figure which shows the circuit block structure of RF module in embodiment. It is a figure which shows an example of the mounting structure of RF module in embodiment. It is a figure which shows the other mounting structure of RF module in embodiment. It is sectional drawing which shows the structure of HEMT in embodiment. It is sectional drawing which shows the structure of MOSFET used as a transistor which comprises an antenna switch. It is a figure which shows an example of the circuit which comprises an antenna switch. It is a figure which shows a test mode in a time division multiple access system. It is a figure which shows a normal communication mode in a time division multiple access system. 4 is a graph showing a relationship between a gate electrode potential and a drain current with a source electrode of a transistor as a reference, and a relationship between a gate electrode potential and a gate-source capacitance with respect to the source electrode. 4 is a graph showing a relationship between a gate electrode potential and a drain current with a source electrode of a transistor as a reference, and a relationship between a gate electrode potential and a gate-source capacitance with respect to the source electrode. It is a figure which shows the relationship between the electric potential of the gate electrode on the basis of the source electrode of a transistor, and ON resistance. It is a figure which shows the relationship between the electric potential of the gate electrode on the basis of the source electrode of a transistor, and ON resistance. It is a graph which shows the relationship between the gate voltage applied to the gate electrode of a transistor, and the 2nd harmonic distortion and 3rd harmonic distortion which generate | occur | produce in the transmission mode of GSM high frequency band (DCS / PCS).

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

<Configuration and operation of mobile phone>
FIG. 1 is a block diagram illustrating a configuration of a transmission / reception unit of a mobile phone. As shown in FIG. 1, the mobile phone 1 includes an application processor 2, a memory 3, a baseband unit 4, an RFIC 5, a power amplifier 6, a SAW (Surface Acoustic Wave) filter 7, an antenna switch 8, and an antenna 9. .

  The application processor 2 is composed of, for example, a CPU (Central Processing Unit) and has a function of realizing an application function of the mobile phone 1. Specifically, the application function is realized by reading and decoding an instruction from the memory 3 and performing various operations and controls based on the decoded result. The memory 3 has a function of storing data. For example, the memory 3 is configured to store a program for operating the application processor 2 and processing data in the application processor 2. The memory 3 can be accessed not only by the application processor 2 but also by the baseband unit 4, and can also be used for storing data processed by the baseband unit 4.

  The baseband unit 4 has a CPU as a central control unit, and at the time of transmission, a baseband signal can be generated by digitally processing an audio signal (analog signal) from a user (caller) via the operation unit. It is configured. On the other hand, at the time of reception, an audio signal can be generated from a baseband signal that is a digital signal.

  The RFIC 5 is configured to generate a radio frequency signal by modulating a baseband signal at the time of transmission, and to generate a baseband signal by demodulating the reception signal at the time of reception. The power amplifier 6 is a semiconductor device that newly generates and outputs a high-power signal similar to a weak input signal using power supplied from a power supply. The SAW filter 7 is configured to pass only signals in a predetermined frequency band from the received signal.

  The antenna switch 8 is for separating the reception signal input to the mobile phone 1 and the transmission signal output from the mobile phone 1, and the antenna 9 is for transmitting and receiving radio waves.

  The mobile phone 1 is configured as described above, and the operation thereof will be briefly described below. First, a case where a signal is transmitted will be described. A baseband signal generated by digitally processing an analog signal such as an audio signal in the baseband unit 4 is input to the RFIC 5. In the RFIC 5, the input baseband signal is converted into a radio frequency (RF (Radio Frequency) frequency) signal by a modulation signal source and a mixer. The signal converted into the radio frequency is output from the RFIC 5 to the power amplifier (RF module) 6. A radio frequency signal input to the power amplifier 6 is amplified by the power amplifier 6 and then transmitted from the antenna 9 via the antenna switch 8.

  Next, a case where a signal is received will be described. A radio frequency signal (reception signal) received by the antenna 9 passes through the SAW filter 7 and is then input to the RFIC 5. The RFIC 5 amplifies the input received signal and then performs frequency conversion using a modulation signal source and a mixer. Then, the frequency-converted signal is detected and a baseband signal is extracted. Thereafter, the baseband signal is output from the RFIC 5 to the baseband unit 4. The baseband signal is processed by the baseband unit 4 and an audio signal is output.

<Configuration of RF module>
As described above, when a signal is transmitted from the digital cellular phone, the signal is amplified by the power amplifier 6 and then output from the antenna 9 via the antenna switch 8. For example, the power amplifier 6 and the antenna switch 8 are commercialized as one RF module HPA. Hereinafter, a circuit block configuration of the RF module HPA will be described. FIG. 2 is a diagram showing a circuit block configuration of the RF module HPA in the present embodiment.

  In FIG. 2, the RF module HPA in the present embodiment includes an amplifier circuit PA_L for LowBand (LB), an amplifier circuit PA_H for HighBand (HB), an output matching circuit MN_L for LB, an output matching circuit MN_H for HB, It has a low-pass filter LPF_L for LB, a low-pass filter LPF_H for HB, and an antenna switch ASW.

  The amplifier circuit PA_L is connected to the input terminal TE (TX_L) and configured to amplify the input signal input to the input terminal TE (TX_L). That is, the amplifier circuit PA_L is an amplifier that amplifies an input signal in the GSM low frequency band (824 MHz to 915 MHz), and includes, for example, two amplification stages. In the amplifier circuit PA_L, the GSM low frequency band input signal output from the input terminal TE (TX_L) is first amplified in the first amplification stage. The input signal amplified in the first amplification stage is amplified in the final amplification stage. By this amplifier circuit PA_L, a high power amplified signal similar to a weak input signal can be obtained.

  The amplifier circuit PA_H is connected to the input terminal TE (TX_H) and configured to amplify the input signal input to the input terminal TE (TX_H). That is, the amplifier circuit PA_H is an amplifier that amplifies an input signal in a GSM high frequency band (1710 MHz to 1785 MHz is also referred to as DCS and 1850 MHz to 1910 MHz is also referred to as PCS), and includes, for example, two amplification stages. In the amplifier circuit PA_H, the input signal in the GSM high frequency band (DCS / PCS) output from the input terminal TE (TX_H) is first amplified in the first amplification stage. The input signal amplified in the first amplification stage is amplified in the final amplification stage. By this amplifier circuit PA_H, a high power amplified signal similar to a weak input signal can be obtained.

  As described above, the RF module HPA in the present embodiment is configured to amplify signals in different frequency bands, that is, a GSM low frequency band (GSM) signal and a GSM high frequency band (DCS / PCS) signal. The RF module HPA includes a control circuit CNT that controls an amplifier circuit PA_L that amplifies a GSM low frequency band (GSM) signal and an amplifier circuit PA_H that amplifies a GSM high frequency band (DCS / PCS) signal. is doing. The control circuit CNT applies a bias voltage to the amplifier circuit PA_L and the amplifier circuit PA_H according to the power supply (power supply voltage) and the control signal (power control voltage) input to the RF module HPA, respectively, and controls the amplification degree. It is configured.

  Thus, the control circuit CNT controls the amplification circuit PA_L and the amplification circuit PA_H, but performs feedback control so that the amplification degree of the amplification circuit PA_L and the amplification degree of the amplification circuit PA_H are constant. The configuration of this feedback control will be described.

  In order to implement feedback control, a directional coupler (coupler) (not shown) is provided at the output of the amplifier circuit PA_L that amplifies a GSM low frequency band (GSM) signal. The directional coupler is configured to detect the power of the amplified signal amplified by the amplifier circuit PA_L. Specifically, the directional coupler is formed of a wiring that constitutes the main line and a wiring that constitutes the sub line, and detects the power of the amplified signal traveling on the main line in the sub line by electromagnetic coupling. .

  A detector circuit (not shown) is connected to the directional coupler. The detection circuit is configured to convert electric power detected by the directional coupler into voltage or current and output a detection signal to the control circuit CNT. Thus, the feedback control is realized by the directional coupler and the detection circuit. The control circuit CNT is configured to calculate the difference between the detection signal input from the detection circuit and the control signal (power control voltage) and adjust the bias voltage applied to the amplifier circuit PA_L so that the calculated difference disappears. . In this way, the control circuit CNT controls the amplification degree of the amplifier circuit PA_L to be constant. Similarly, a directional coupler (coupler) (not shown) is provided at the output of the amplifier circuit PA_H that amplifies a signal in the GSM high frequency band (DCS / PCS), and a detection circuit (see FIG. (Not shown) is connected. The detection signal detected by the detection circuit is input to the control circuit CNT.

  Next, the output matching circuit MN_L is configured to input the amplified signal amplified by the amplifier circuit PA_L and to perform impedance matching of the amplified signal. That is, the output matching circuit MN_L has a function of efficiently transmitting the amplified signal amplified by the amplifier circuit PA_L, and includes, for example, passive components such as an inductor, a capacitive element, and a resistive element. Since the amplified signal amplified by the amplifier circuit PA_L is input to the output matching circuit MN_L, the output matching circuit MN_L is an output matching circuit for signals in the GSM low frequency band (GSM).

  The low-pass filter LPF_L is connected to the output matching circuit MN_L and has a function of removing harmonic noise. For example, when an input signal is amplified by the amplifier circuit PA_L, a signal in the GSM low frequency band (GSM) is amplified. At this time, harmonics that are integer multiples of the GSM low frequency band (GSM) are also generated. This harmonic is included in the GSM low frequency band (GSM) signal, but becomes a noise component having a frequency different from that of the amplified signal in the GSM low frequency band (GSM). Therefore, it is necessary to remove harmonic components from the amplified GSM low frequency band (GSM) amplified signal. The low-pass filter LPF_L connected after the output matching circuit MN_L has this function. The low-pass filter LPF_L functions as a selection circuit that passes signals in a specific range of frequency bands from a plurality of frequency band signals. That is, the low-pass filter LPF_L is configured to pass a GSM low frequency band (GSM) amplified signal while attenuating higher harmonics than the GSM low frequency band (GSM) amplified signal. This low-pass filter LPF_L can reduce harmonic noise contained in the amplified signal in the GSM low frequency band (GSM).

  Subsequently, the output matching circuit MN_H and the low-pass filter LPF_H are also connected to the output of the amplifier circuit PA_H that generates an amplified signal in the GSM high frequency band (DCS / PCS). Specifically, the output matching circuit MN_H is configured to input the amplified signal amplified by the amplifier circuit PA_H and perform impedance matching of the amplified signal. In other words, the output matching circuit MN_H has a function of efficiently transmitting the amplified signal amplified by the amplifier circuit PA_H, and includes, for example, passive components such as an inductor, a capacitive element, and a resistive element. Since the amplified signal amplified by the amplifier circuit PA_H is input to the output matching circuit MN_H, the output matching circuit MN_H is an output matching circuit for signals in the GSM high frequency band (DCS / PCS).

  The low-pass filter LPF_H is connected to the output matching circuit MN_H and has a function of removing harmonic noise. For example, when an input signal is amplified by the amplifier circuit PA_H, a signal in the GSM high frequency band (DCS / PCS) is amplified. At this time, harmonics that are integral multiples of the GSM high frequency band (DCS / PCS) are also generated. . This harmonic is included in the signal of the GSM high frequency band (DCS / PCS), but becomes a noise component having a frequency different from that of the amplified signal of the GSM high frequency band (DCS / PCS). Therefore, it is necessary to remove harmonic components from the amplified GSM high frequency band (DCS / PCS) amplified signal. The low-pass filter LPF_H connected after the output matching circuit MN_H has this function. The low-pass filter LPF_H functions as a selection circuit that passes signals in a specific range of frequency bands from a plurality of frequency band signals. That is, the low pass filter LPF_H is configured to pass the amplified signal in the GSM high frequency band (DCS / PCS) and attenuate the higher harmonics than the amplified signal in the GSM high frequency band (DCS / PCS). . The low-pass filter LPF_H can reduce harmonic noise contained in the amplified signal in the GSM high frequency band (DCS / PCS).

  Next, the antenna switch ASW is configured to switch a line connected to the antenna ANT, and the line is switched by the changeover switch. Specifically, the changeover switch constituting the antenna switch ASW switches the output of the low-pass filter LPF_L and the output of the low-pass filter LPF_H, and connects the path (path) switched via the output terminal TE (OUT) to the antenna ANT. It is configured. That is, when the GSM low frequency band (GSM) amplified signal output from the low-pass filter LPF_L is output from the antenna ANT, the output of the low-pass filter LPF_L is connected to the antenna ANT by the changeover switch. On the other hand, when an amplified signal in the GSM high frequency band (DCS / PCS) output from the low-pass filter LPF_H is output from the antenna ANT, the output of the low-pass filter LPF_H is connected to the antenna ANT by a changeover switch. . As described above, the antenna switch ASW is configured to switch between two systems of output (transmission state), and further configured to be able to switch to the reception state. For example, in the reception state, the changeover switch is operated so as to output a reception signal received by the antenna to the reception circuit. Since there are a plurality of receiving lines, a changeover switch is configured so that the receiving circuit can be switched to a plurality of receiving circuits. For example, a reception terminal TE (RX_H) and a reception terminal TE (RX_L) that output a plurality of reception signals are provided, and a reception signal received by the antenna ANT is output to a corresponding reception circuit by switching by the antenna switch ASW. It is configured to be.

  Control of the changeover switch constituting the antenna switch ASW is performed based on a control signal from the control circuit CNT. For example, the amplified signal (RF signal (low frequency band) (GSM)) is output / non-output to the antenna ANT by turning on / off a changeover switch (switching element) formed in the antenna switch ASW. It is controlled. The output / non-output of the reception signal from the antenna to the reception circuit is controlled by turning on / off another switching switch (switching element) formed in the antenna switch ASW. Similarly, output / non-output of the amplified signal (RF signal (high frequency band) (DCS / PCS)) to the antenna ANT is controlled by turning on / off the switch (switching element) in the antenna switch ASW. ing.

<Operation of RF module>
The RF module HPA in the present embodiment is configured as described above, and the operation thereof will be described below. As shown in FIG. 2, the present embodiment is configured to amplify a GSM low frequency band (GSM) signal and a GSM high frequency band (DCS / PCS) signal, but the operation is the same. Therefore, an operation for amplifying a GSM low frequency band (GSM) signal will be described. Note that although the GSM method has been described as the communication method, other communication methods may be used.

  As shown in FIG. 2, when a weak input signal (RF input) is input to the RF module HPA, first, the weak input signal is input to the amplifier circuit PA_L. Subsequently, the power of the input signal input to the amplifier circuit PA_L is amplified by two amplifier stages constituting the amplifier circuit PA_L. At this time, power amplification by the amplifier circuit PA_L is controlled by the control circuit CNT. Specifically, the control circuit CNT applies a bias voltage to the amplifier circuit PA_L based on a power supply (power supply voltage) and a control signal (power control voltage) input to the control circuit CNT. Then, the amplifier circuit PA_L amplifies the input signal based on the bias voltage from the control circuit CNT and outputs the amplified signal. In this way, the amplified signal amplified by the amplifier circuit PA_L is output.

  The amplified signal output from the amplifier circuit PA_L is preferably constant power. However, the power of the amplified signal that is actually output is not always the desired power due to the influence from the outside. Therefore, feedback is applied to the control circuit CNT that controls the amplifier circuit PA_L. The operation of this feedback circuit will be described.

  The power of the amplified signal amplified by the amplifier circuit PA_L is detected by a directional coupler (coupler) (not shown). The electric power detected by the directional coupler is converted into a voltage by a detection circuit (not shown) connected to the directional coupler. A detection signal composed of the voltage converted by the detection circuit is input to the control circuit CNT. On the other hand, a control signal (power control voltage) input from the outside of the RF module HPA is also input to the control circuit CNT. Then, the control circuit CNT calculates the difference between the detection signal converted by the detection circuit and the control signal input from the outside of the RF module HPA. Next, the control circuit CNT controls the bias voltage applied from the control circuit CNT to the amplifier circuit PA_L so that the calculated difference disappears. In this way, the power of the amplified signal amplified by the amplifier circuit PA_L is constant. This operation is the operation of the feedback circuit.

  Subsequently, the amplified signal amplified by the amplifier circuit PA_L is input to the output matching circuit MN_L. Since the output matching circuit MN_L performs impedance matching on the amplified signal, the amplified signal is efficiently output toward the low-pass filter LPF_L without reflection. Subsequently, the high-order harmonic distortion included in the amplified signal is removed from the amplified signal input to the low-pass filter LPF_L by the low-pass filter LPF_L. Thereafter, the amplified signal that has passed through the low-pass filter LPF_L is input to the antenna switch ASW. At this time, the changeover switch constituting the antenna switch ASW is controlled by the switch changeover control signal from the control circuit CNT. In this case, the changeover switch is controlled so that the low-pass filter LPF_L and the antenna ANT are electrically connected. As a result, the amplified signal output from the low-pass filter LPF_L is output to the output terminal TE (OUT) via the ON-state changeover switch, and is transmitted from the output terminal TE (OUT) to the antenna ANT. As described above, the amplified signal amplified by the RF module HPA can be transmitted from the antenna ANT.

  Next, an operation for capturing a reception signal received by the antenna ANT will be described. A reception signal received by the antenna ANT is input to the antenna switch ASW via the output terminal TE (OUT). At that time, the changeover switch is switched by a switch changeover control signal from the control circuit CNT. Specifically, the selector switch included in the antenna switch ASW is switched so as to electrically connect the antenna ANT and a receiving circuit (not shown) provided outside the RF module HPA. Then, the reception signal received by the antenna ANT is input to the reception circuit via the changeover switch constituting the antenna switch ASW. Then, signal processing is performed in the receiving circuit. In this way, the received signal can be received.

<RF module mounting configuration>
Next, the mounting configuration of the RF module HPA will be described. FIG. 3 is a diagram showing an example of a mounting configuration of the RF module HPA in the present embodiment. In FIG. 3, the RF module HPA in the present embodiment includes a semiconductor chip CHP1 (amplifier circuit semiconductor chip, control circuit semiconductor chip), a semiconductor chip CHP2 (antenna switch semiconductor chip), and passive components on a wiring board WB. Has SMD. The semiconductor chip CHP1 and the semiconductor chip CHP2 are electrically connected by wires. Further, the semiconductor chip CHP1 and the passive component SMD, and the semiconductor chip CHP2 and the passive component SMD are also electrically connected by wiring (not shown) formed on the wiring board WB.

  The correspondence relationship between the mounting configuration diagram of the RF module HPA shown in FIG. 3 and the circuit block diagram shown in FIG. 2 will be described below. First, in the semiconductor chip CHP1 shown in FIG. 3, the control circuit CNT, the amplifier circuit PA_L, and the amplifier circuit PA_H shown in FIG. 2 are formed. Specifically, the semiconductor chip CHP1 is composed of a semiconductor substrate mainly made of silicon, and a CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) or an LDMOSFET (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) is formed on the semiconductor substrate. Is formed. A control circuit CNT is constituted by an integrated circuit formed of CMOSFET formed on the semiconductor substrate, and an amplifier circuit PA_L and an amplifier circuit PA_H are formed of integrated circuits formed by LDMOSFET formed on the semiconductor substrate. As described above, in the RF module HPA shown in FIG. 3, since the CMOSFET and the LDMOSFET can be simultaneously formed on the semiconductor substrate mainly made of silicon, the control circuit CNT, the amplifier circuit PA_L, and the amplifier circuit PA_H are integrated into one semiconductor. It can be formed on the chip CHP1.

  Next, the antenna switch ASW shown in FIG. 2 is formed in the semiconductor chip CHP2 shown in FIG. Specifically, the semiconductor chip CHP2 is composed of a compound semiconductor substrate mainly composed of GaAs, and a HEMT (High Electron Mobility Transistor) is formed on the compound semiconductor substrate. The antenna switch ASW is composed of a plurality of HEMTs formed on the compound semiconductor substrate. As described above, in the RF module HPA shown in FIG. 3, the control circuit CNT, the amplifier circuit PA_L, and the amplifier circuit PA_H are formed on the semiconductor chip CHP1 mainly composed of silicon, and the antenna switch ASW is formed on the semiconductor chip CHP2 mainly composed of GaAs. Is formed.

  Subsequently, the passive component SMD illustrated in FIG. 3 is a component that configures the output matching circuit MN_L, the output matching circuit MN_H, the low-pass filter LPF_L, and the low-pass filter LPF_H illustrated in FIG. The passive component SMD is composed of chip components such as a chip resistor, a chip capacitor, and a chip inductor, for example.

  As described above, the RF module HPA in the present embodiment has a mounting configuration as shown in FIG. 3, but is not limited to this, and other mounting configurations are possible. FIG. 4 is a diagram showing another mounting configuration of the RF module HPA in the present embodiment. In FIG. 4, the RF module HPA in the present embodiment includes a semiconductor chip CHP1 (control circuit semiconductor chip), a semiconductor chip CHP2 (antenna switch semiconductor chip), and a semiconductor chip CHP3 (amplifier circuit semiconductor) on the wiring board WB. Chip), a semiconductor chip CHP4 (amplifier circuit semiconductor chip), and a passive component SMD. The semiconductor chip CHP1 and the semiconductor chip CHP2, the semiconductor chip CHP1 and the semiconductor chip CHP3, and the semiconductor chip CHP1 and the semiconductor chip CHP4 are electrically connected by wires. Furthermore, the semiconductor chip CHP1 and the passive component SMD, the semiconductor chip CHP2 and the passive component SMD, the semiconductor chip CHP3 and the passive component SMD, and the semiconductor chip CHP4 and the passive component SMD are also formed on the wiring board WB (not shown). ) Is electrically connected.

  The correspondence relationship between the mounting configuration diagram of the RF module HPA shown in FIG. 4 and the circuit block diagram shown in FIG. 2 will be described below. The semiconductor chip CHP1 is formed from, for example, a semiconductor substrate mainly made of silicon, and a CMOSFET is formed on the semiconductor substrate. A control circuit CNT shown in FIG. 2 is formed in such a semiconductor chip CHP1.

  An antenna switch ASW shown in FIG. 2 is formed in the semiconductor chip CHP2. Specifically, the semiconductor chip CHP2 is composed of a compound semiconductor substrate mainly composed of GaAs, and a HEMT (High Electron Mobility Transistor) (high electron mobility transistor) is formed on the compound semiconductor substrate. The antenna switch ASW is composed of a plurality of HEMTs formed on the compound semiconductor substrate.

  Subsequently, the amplifier circuit PA_L and the amplifier circuit PA_H shown in FIG. 2 are formed in the semiconductor chip CHP3 and the semiconductor chip CHP4. Specifically, the semiconductor chip CHP3 and the semiconductor chip CHP4 are formed from a compound semiconductor substrate mainly composed of GaAs, and an HBT (Heterojunction Bipolar Transistor) is formed on the compound semiconductor substrate. . As described above, in the mounting configuration shown in FIG. 4, the amplifier circuit PA_L and the amplifier circuit PA_H are configured by the HBT formed on the compound semiconductor substrate, and the control circuit CNT is configured by the CMOSFET formed on the silicon substrate. The circuit PA_L (amplifier circuit PA_H) and the control circuit CNT are formed by separate semiconductor chips.

  The passive component SMD shown in FIG. 4 is a component that constitutes the output matching circuit MN_L, the output matching circuit MN_H, the low-pass filter LPF_L, and the low-pass filter LPF_H shown in FIG. The passive component SMD is composed of chip components such as a chip resistor, a chip capacitor, and a chip inductor, for example.

<Device configuration of antenna switch>
As described above, the RF module HPA in the present embodiment has the mounting configuration shown in FIGS. In particular, an antenna switch ASW made of, for example, HEMT is formed in the semiconductor chip CHP2, and the device structure of the HEMT that constitutes the antenna switch ASW will be described.

  FIG. 5 is a cross-sectional view showing the configuration of the HEMT in the present embodiment. In FIG. 5, an epitaxial layer 11 is formed on a semi-insulating substrate 10. The semi-insulating substrate 10 is a substrate composed of a compound semiconductor GaAs substrate as shown below. That is, in a compound semiconductor having a large forbidden band, when a certain type of impurity is added, a deep level is formed inside the forbidden band. The deep level electrons and holes are fixed, and the electron density in the conduction band or the hole density in the valence band becomes very small, becoming closer to an insulator. Such a substrate is called a semi-insulating substrate. In a GaAs substrate, deep levels are formed by adding Cr, In, oxygen or the like, or introducing arsenic excessively, thereby forming a semi-insulating substrate.

  The epitaxial layer 11 formed on the semi-insulating substrate 10 is formed from, for example, a GaAs layer. A buffer layer 12 is formed on the epitaxial layer 11, and an AlGaAs layer 13 is formed on the buffer layer 12. The AlGaAs layer 13 is processed into a mesa shape and element isolation is performed. A gate electrode G is formed on the AlGaAs layer 13. The gate electrode G is formed of, for example, a metal layer having Pt (platinum) as the lowermost layer, and a stacked film in which Pt, Ti (titanium), Pt, and Au (gold) are sequentially stacked from the lower layer is used. As a result, the AlGaAs layer 13 and the gate electrode G (lowermost layer Pt) form a Schottky junction. Further, an n-type GaAs layer 14 is formed so as to sandwich the gate electrode G, and a source electrode SE (ohmic electrode) and a drain electrode DE (ohmic electrode) are formed on the n-type GaAs layer 14. ing. The source electrode SE and the drain electrode DE are configured to make ohmic contact with the n-type GaAs layer 14.

  The above-described high electron mobility transistor (HEMT) is formed by laminating a high-resistance epitaxial layer 11 (GaAs layer) and an AlGaAs layer 13 on a semi-insulating substrate (compound semiconductor substrate) 10 to form a GaAs layer and an AlGaAs layer. A triangular well-type potential formed at the hetero-bond interface with the layer is used. This high electron mobility transistor (HEMT) has a Schottky barrier type gate electrode G by forming a metal film on the surface of the AlGaAs layer 13, and a current flows through the heterojunction plane with the gate electrode G interposed therebetween. Therefore, an ohmic source electrode SE (ohmic electrode) and a drain electrode DE (ohmic electrode) are provided.

  A high electron mobility transistor (HEMT) uses a two-dimensional electron gas formed in this well-type potential as a carrier. Since the width of the well-type potential existing at the heterojunction interface is only as wide as the wavelength of the electrons, and the electrons can only move two-dimensionally along the interface, a large electron mobility can be obtained. is there. Therefore, the high mobility characteristic of the two-dimensional electron gas is excellent in the high frequency characteristic and the high speed characteristic, and the noise is very small. Therefore, it is used for the antenna switch ASW that requires high speed.

  In the present embodiment, an example in which the antenna switch ASW is configured from HEMT has been described. However, the present invention is not limited to this. For example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as a transistor configuring the antenna switch ASW. You can also.

  FIG. 6 is a cross-sectional view showing the structure of a MOSFET used as a transistor constituting the antenna switch ASW. As shown in FIG. 6, a buried insulating layer 21 made of, for example, a silicon oxide film is formed on a semiconductor substrate 20 mainly composed of silicon, and a silicon layer (active layer) 22 is formed on the buried insulating layer 21. ing. That is, in this example, a MOSFET is formed on an SOI (Silicon on Insulator) substrate composed of the semiconductor substrate 20, the buried insulating layer 21, and the silicon layer 22. This MOSFET is formed in an active region partitioned by an element isolation region STI formed in the silicon layer 22. Specifically, the MOSFET has a gate insulating film GOX formed on the silicon layer 22, and has a gate electrode G on the gate insulating film GOX. The gate insulating film GOX is formed from, for example, a silicon oxide film, and the gate electrode G is formed from, for example, a stacked film of a polysilicon film and a silicide film.

  Then, sidewalls SW made of, for example, a silicon oxide film are formed on the sidewalls on both sides of the gate electrode G, and extensions that are impurity diffusion regions are aligned with the gate electrode G in the silicon layer 22 immediately below the sidewall SW. Region EX is formed. A source region S1 and a drain region D1 aligned with the sidewall SW are formed outside the extension region EX. The extension region EX, the source region S1, and the drain region D1 are semiconductor regions into which n-type impurities such as phosphorus and arsenic are introduced, and the amount of impurities introduced into the extension region EX is introduced into the source region S1 and the drain region D1. It is less than the amount of impurities.

  As described above, the MOSFET in the present embodiment is configured, and the interlayer insulating film IL is formed on the MOSFET. Then, plugs PLG that reach the source region S1 and the drain region D1 through the interlayer insulating film IL are formed. A wiring L1 electrically connected to the plug PLG is formed on the interlayer insulating film IL.

  In the present embodiment, the MOSFET is formed on the SOI substrate. However, by forming the MOSFET on the SOI substrate, the elements can be completely separated, and the capacitance of the source region S1 or the drain region D1 can be increased. Can be reduced. For this reason, there is an advantage that an integration density and an operation speed can be improved, a high breakdown voltage and a latch-up free can be realized.

  In this embodiment, an example in which a MOSFET is formed on an SOI substrate has been described. However, for example, the present invention can also be applied to a case where a MOSFET is formed on an SOS (Silicon on Sapphire) substrate instead of the SOI substrate. In addition, a MOSFET formed on a normal semiconductor substrate instead of the SOI substrate can be applied to the antenna switch ASW.

<Circuit configuration of antenna switch>
The present embodiment focuses on the antenna switch ASW mounted on the RF module HPA. Hereinafter, the circuit configuration of the antenna switch ASW will be described. FIG. 7 is a diagram illustrating an example of a circuit constituting the antenna switch ASW. As shown in FIG. 7, the antenna switch ASW has a transmission terminal TX1, a transmission terminal TX2, an antenna terminal TE (ANT), and a reception terminal RX. The transmission terminal TX1 is connected to the output of the GSM low frequency band (GSM) amplifier circuit PA_L (specifically, the output of the low pass filter LPF_L), and the transmission terminal TX2 is connected to the GSM high frequency band (DCS / PCS) amplifier circuit PA_H. It is connected to the output (specifically, the output of the low pass filter LPF_H). The antenna terminal TE (ANT) is connected to the antenna, and the reception terminal RX is connected to the input of the reception circuit.

  A transistor Q1 (first transmission FET) is connected as a switching element between the transmission terminal TX1 and the antenna terminal TE (ANT). The transistor Q1 connected between the transmission terminal TX1 and the antenna terminal TE (ANT) has a source electrode, a drain electrode, and a gate electrode G1. At this time, the source electrode and the drain electrode in the transistor Q1 are equivalent and become ohmic electrodes. In the present specification, the ohmic electrode on the side connected to the antenna terminal TE (ANT) of the transistor Q1 is defined as a source electrode, and the ohmic electrode on the side connected to the transmission terminal TX1 is defined as a drain electrode. The gate electrode G1 is connected to the gate terminal TX1c via the gate resistance Rgg1. The gate resistor Rgg1 is an isolation resistor provided to prevent a transmission signal flowing between the transmission terminal TX1 and the antenna terminal TE (ANT) from leaking to the gate terminal TX1c.

  Subsequently, a transistor Q2 (second transmission FET) is connected as a switching element between the transmission terminal TX2 and the antenna terminal TE (ANT). The transistor Q2 connected between the transmission terminal TX2 and the antenna terminal TE (ANT) has a source electrode, a drain electrode, and a gate electrode G2. At this time, the source electrode and the drain electrode in the transistor Q2 are equivalent and become ohmic electrodes. In the present specification, the ohmic electrode on the side connected to the antenna terminal TE (ANT) of the transistor Q2 is defined as a source electrode, and the ohmic electrode on the side connected to the transmission terminal TX2 is defined as a drain electrode. The gate electrode G2 is connected to the gate terminal TX2c via the gate resistance Rgg2. The gate resistor Rgg2 is an isolation resistor provided to prevent a transmission signal flowing between the transmission terminal TX2 and the antenna terminal TE (ANT) from leaking to the gate terminal TX2c.

  A transistor Q3 (reception FET) is connected as a switching element between the reception terminal RX and the antenna terminal TE (ANT). The transistor Q3 connected between the reception terminal RX and the antenna terminal TE (ANT) has a source electrode, a drain electrode, and a gate electrode G3. At this time, the source electrode and the drain electrode in the transistor Q3 are equivalent and become ohmic electrodes. In the present specification, the ohmic electrode on the side connected to the antenna terminal TE (ANT) of the transistor Q3 is defined as a source electrode, and the ohmic electrode on the side connected to the receiving terminal RX is defined as a drain electrode. The gate electrode G3 is connected to the gate terminal RX1c through the gate resistance Rgg3. The gate resistor Rgg3 is an isolation resistor provided to prevent a transmission signal flowing between the reception terminal RX and the antenna terminal TE (ANT) from leaking to the gate terminal RX1c.

<General circuit operation of antenna switch>
The antenna switch ASW in the present embodiment is configured as described above, and the general operation thereof will be described below. Before describing the operation of the antenna switch ASW, a high electron mobility transistor (HEMT) is assumed as a transistor used in this embodiment. The basic operation of the HEMT will be described using the transistor Q1 shown in FIG. 7 as an example and the cross-sectional structure shown in FIG. The gate electrode G (G1) is in contact with the AlGaAs layer 13 by forming a Schottky junction. If the gate electrode G (G1) has a potential lower than the threshold voltage Vth (generally about −1.0 V) with respect to the source electrode SE (or the drain electrode DE), there is a gap between the source electrode SE and the drain electrode DE. It becomes high impedance and turns off. Conversely, the voltage applied to the gate electrode G (G1) is set higher than the threshold voltage Vth (generally about −1.0 V) with respect to the source electrode SE (or the drain electrode DE). Then, the Schottky barrier between the gate electrode G (G1) and the AlGaAs layer 13 is crushed, and the voltage applied to the gate electrode G (G1) is applied to the source electrode SE and the drain electrode DE. The impedance between the electrodes DE becomes low and the switch is turned on. The on / off control of the transistor Q1 by the potential difference between the gate electrode G (G1) and the source electrode SE (drain electrode DE) can be similarly switched in the MOSFET. Therefore, specifically, a case where a transmission signal is transmitted from an antenna will be described.

  First, the operation of the antenna switch ASW when transmitting a GSM low frequency band (GSM) transmission signal from an antenna will be described with reference to FIG.

  When a positive voltage (˜4V) is applied to the gate electrode G1 of the transistor Q1, the voltage applied to the gate electrode G1 is a threshold voltage Vth (generally −1.0V) with respect to the source electrode (or drain electrode). Transistor Q1 is turned on. That is, in the transistor Q1, since the potential Vgs1 of the gate electrode G1 with respect to the source electrode is equal to or higher than the threshold voltage, the transistor Q1 is turned on. At the same time, a voltage that is lowered by the amount corresponding to the Schottky barrier (down by about 0.5 V) is applied to the source electrode (or drain electrode). Here, when the transistor Q1 is turned on, the source electrode (drain electrode) is applied with a potential that is lower than the voltage applied to the gate electrode G1 by the Schottky barrier, as described above. It is assumed that the same potential as the gate electrode G1 is applied to the source electrode (drain electrode) of the transistor Q1, ignoring the voltage drop for the key barrier. Therefore, the potential Vant of the antenna terminal TE (ANT) that is electrically connected to the source electrode of the transistor Q1 is a positive potential (˜4 V).

  On the other hand, in order to turn off the transistor Q2, 0V is applied to the gate electrode G2 of the transistor Q2. This positive potential (˜4V) is applied to the source electrode and the drain electrode of the transistor Q1 by the positive voltage (˜4V) applied to the gate electrode G1 to turn on the transistor Q1. That is, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q1 becomes a positive potential (˜4 V), and the transistor Q2 electrically connected to the antenna terminal TE (ANT). A positive potential (˜4 V) is also applied to the source electrode. Since the gate electrode G2 of the transistor Q2 is 0 V, the gate electrode G2 has a voltage lower than the threshold voltage Vth with respect to the source electrode (drain electrode). That is, in the transistor Q2, since the potential Vgs2 of the gate electrode G2 with respect to the source electrode is equal to or lower than the threshold voltage, the transistor Q2 is turned off.

  Similarly, 0V is applied to the gate electrode G3 of the transistor Q3. This positive potential (˜4V) is applied to the source electrode and the drain electrode of the transistor Q1 by the positive voltage (˜4V) applied to the gate electrode G1 to turn on the transistor Q1. That is, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q1 becomes a positive potential (˜4 V), and the transistor Q3 electrically connected to the antenna terminal TE (ANT). A positive potential (˜4 V) is also applied to the source electrode. Since the gate electrode G3 of the transistor Q3 is 0 V, the gate electrode G3 has a voltage lower than the threshold voltage Vth with respect to the source electrode (drain electrode). That is, in the transistor Q3, since the potential Vgs3 of the gate electrode G3 with respect to the source electrode is equal to or lower than the threshold voltage, the transistor Q3 is turned off.

  Therefore, the antenna terminal TE (ANT) is electrically connected to the transmission terminal TX1 via the transistor Q1 that is turned on. In this state, the GSM low frequency band (GSM) transmission signal (RF signal) input from the transmission terminal TX1 to the antenna switch ASW is output to the antenna terminal TE (ANT) through the transistor Q1 in the on state. Sent from antenna.

  Next, the operation of the antenna switch ASW when a transmission signal in the GSM high frequency band (DCS / PCS) is transmitted from the antenna will be described with reference to FIG.

  When a positive voltage (˜4V) is applied to the gate electrode G2 of the transistor Q2, the voltage applied to the gate electrode G2 is a threshold voltage Vth (generally −1.0V with respect to the source electrode (or drain electrode)). Transistor Q2 is turned on. That is, in the transistor Q2, since the potential Vgs2 of the gate electrode G2 with respect to the source electrode is equal to or higher than the threshold voltage, the transistor Q2 is turned on. At the same time, a voltage that is lowered by the amount corresponding to the Schottky barrier (down by about 0.5 V) is applied to the source electrode (or drain electrode). Here, when the transistor Q2 is turned on, the source electrode (drain electrode) is applied with a potential that is lower by the Schottky barrier than the voltage applied to the gate electrode G2, as described above. Assume that the same potential as the gate electrode G2 is applied to the source electrode (drain electrode) of the transistor Q2 ignoring the voltage drop for the key barrier. Therefore, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q2 becomes a positive potential (˜4V).

  On the other hand, in order to turn off the transistor Q1, 0V is applied to the gate electrode G1 of the transistor Q1. This positive potential (˜4V) is applied to the source electrode and the drain electrode of the transistor Q2 by the positive voltage (˜4V) applied to the gate electrode G2 to turn on the transistor Q2. That is, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q2 becomes a positive potential (˜4 V), and the transistor Q1 electrically connected to the antenna terminal TE (ANT). A positive potential (˜4 V) is also applied to the source electrode. Since the gate electrode G1 of the transistor Q1 is 0 V, the gate electrode G1 has a voltage lower than the threshold voltage Vth with respect to the source electrode (drain electrode). That is, in the transistor Q1, the potential Vgs1 of the gate electrode G1 with respect to the source electrode is equal to or lower than the threshold voltage, so that the transistor Q1 is turned off.

  Similarly, 0V is applied to the gate electrode G3 of the transistor Q3. This positive potential (˜4V) is applied to the source electrode and the drain electrode of the transistor Q2 by the positive voltage (˜4V) applied to the gate electrode G2 to turn on the transistor Q2. That is, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q2 becomes a positive potential (˜4 V), and the transistor Q3 electrically connected to the antenna terminal TE (ANT). A positive potential (˜4 V) is also applied to the source electrode. Since the gate electrode G3 of the transistor Q3 is 0 V, the gate electrode G3 has a voltage lower than the threshold voltage Vth with respect to the source electrode (drain electrode). That is, in the transistor Q3, since the potential Vgs3 of the gate electrode G3 with respect to the source electrode is equal to or lower than the threshold voltage, the transistor Q3 is turned off.

  Therefore, the antenna terminal TE (ANT) is electrically connected to the transmission terminal TX2 via the transistor Q2 that is turned on. In this state, the GSM high frequency band (DCS / PCS) transmission signal (RF signal) input from the transmission terminal TX2 to the antenna switch ASW is output to the antenna terminal TE (ANT) through the transistor Q2 in the conductive state. Transmitted from the antenna.

  Next, a case where a received signal is received from an antenna will be described. When a positive voltage (˜4V) is applied to the gate electrode G3 of the transistor Q3, the voltage applied to the gate electrode G3 is a threshold voltage Vth (generally −1.0V) with respect to the source electrode (or drain electrode). Transistor Q3 is turned on. That is, in the transistor Q3, since the potential Vgs3 of the gate electrode G3 with respect to the source electrode is equal to or higher than the threshold voltage, the transistor Q3 is turned on. At the same time, a voltage that is lowered by the amount corresponding to the Schottky barrier (down by about 0.5 V) is applied to the source electrode (or drain electrode). Here, when the transistor Q3 is turned on, the source electrode (drain electrode) is applied with a potential that is lower by the Schottky barrier than the voltage applied to the gate electrode G3 as described above. Assume that the same potential as the gate electrode G3 is applied to the source electrode (drain electrode) of the transistor Q3 ignoring the voltage drop of the key barrier. Therefore, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q3 is a positive potential (˜4V).

  On the other hand, in order to turn off the transistor Q1, 0V is applied to the gate electrode G1 of the transistor Q1. This positive potential (˜4V) is applied to the source electrode and the drain electrode of the transistor Q3 by the positive voltage (˜4V) applied to the gate electrode G3 to turn on the transistor Q3. That is, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q3 becomes a positive potential (˜4 V), and the transistor Q1 electrically connected to the antenna terminal TE (ANT). A positive potential (˜4 V) is also applied to the source electrode. Since the gate electrode G1 of the transistor Q1 is 0 V, the gate electrode G1 has a voltage lower than the threshold voltage Vth with respect to the source electrode (drain electrode). That is, in the transistor Q1, the potential Vgs1 of the gate electrode G1 with respect to the source electrode is equal to or lower than the threshold voltage, so that the transistor Q1 is turned off.

  Similarly, 0V is applied to the gate electrode G2 of the transistor Q2. This positive potential (˜4V) is applied to the source electrode and the drain electrode of the transistor Q3 by the positive voltage (˜4V) applied to the gate electrode G3 to turn on the transistor Q3. That is, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q3 becomes a positive potential (˜4 V), and the transistor Q2 electrically connected to the antenna terminal TE (ANT). A positive potential (˜4 V) is also applied to the source electrode. Since the gate electrode G2 of the transistor Q2 is 0 V, the gate electrode G2 has a voltage lower than the threshold voltage Vth with respect to the source electrode (drain electrode). That is, in the transistor Q2, since the potential Vgs2 of the gate electrode G2 with respect to the source electrode is equal to or lower than the threshold voltage, the transistor Q2 is turned off.

  Therefore, the antenna terminal TE (ANT) is electrically connected to the reception terminal RX via the transistor Q3 that is turned on. In this state, the reception signal (RF signal) input from the antenna terminal TE (ANT) to the antenna switch is output to the reception terminal RX through the transistor Q3 in the on state, and then input to the reception circuit.

  As described above, when transmitting a GSM low frequency band (GSM) transmission signal, the transistor Q1 is turned on, and the transistor Q2 and the transistor Q3 are turned off, whereby the transmission signal input from the transmission terminal TX1 is transmitted to the antenna. Transmission is possible from the terminal TE (ANT). Similarly, when transmitting a transmission signal in the GSM high frequency band (DCS / PCS), the transistor Q2 is turned on and the transistors Q1 and Q3 are turned off so that the transmission signal input from the transmission terminal TX2 is transmitted to the antenna. Transmission is possible from the terminal TE (ANT). On the other hand, when receiving a reception signal, the transistor Q1 and the transistor Q2 are turned off and the transistor Q3 is turned on, whereby the reception signal input from the antenna terminal TE (ANT) can be output to the reception circuit.

  Here, a case where a transmission signal is output from the antenna switch is considered. The power of the transmission signal is, for example, large power exceeding 1 W, and it is necessary to suppress high-order harmonic distortion included in this transmission signal. That is, although the transmission signal is transmitted from the antenna, it is desirable that the frequency of the transmission signal includes only a signal in a predetermined frequency band. However, the transmission signal is amplified by, for example, the amplifier circuit PA_L or the amplifier circuit PA_H of the RF module HPA shown in FIG. . Therefore, if the transmission signal output from the amplifier circuit PA_L or the amplifier circuit PA_H is transmitted as it is from the antenna, higher-order harmonic distortion higher than the use band is included, which is a problem in relation to the radio wave law. In other words, the frequency band of the transmission signal is specified in advance, and if a signal in a frequency band outside the specification is generated, it becomes an interference wave of other signals, so that it is necessary to reduce the occurrence of high-order harmonic distortion. Therefore, as shown in FIG. 2, the transmission signal amplified by the amplifier circuit PA_L and the amplifier circuit PA_H is configured to pass through the low-pass filter LPF_L and the low-pass filter LPF_H, and the low-pass filter LPF_L and the low-pass filter LPF_H. Therefore, high-order harmonic distortion included in the transmission signal is removed as much as possible.

  However, the high-order harmonic distortion cannot be completely removed even by the low-pass filter LPF_L or the low-pass filter LPF_H, and the high-order harmonic distortion is also received from the antenna switch ASW that is input after passing through the low-pass filter LPF_L or the low-pass filter LPF_H. Occurs. Therefore, it is necessary to reduce high-order harmonic distortion generated in the antenna switch ASW. Specifically, as shown in FIG. 7, the antenna switch ASW includes, for example, a transistor Q1, a transistor Q2, and a transistor Q3. When transmitting a GSM low frequency band (GSM) transmission signal, the transistor Q1 is turned on, and the transistors Q2 and Q3 are turned off. At this time, high-order harmonic distortion is generated from the transistor Q1 that is turned on, and high-order harmonic distortion is also generated from the transistor Q2 and the transistor Q3 that are turned off.

  First, in both the transistor Q1 that is turned on and the transistors Q2 and Q3 that are turned off, a configuration is adopted that reduces the occurrence of high-order harmonic distortion. For example, the resistor Rd1 is provided between the source electrode and the drain electrode of the transistor Q1. Similarly, a resistor Rd2 is provided between the source electrode and the drain electrode of the transistor Q2, and a resistor Rd3 is provided between the source electrode and the drain electrode of the transistor Q3. The reason for this will be described. For example, consider transistor Q1. The reason why the source electrode and the drain electrode of the transistor Q1 are connected by the resistor Rd1 is to make the source electrode and the drain electrode have the same potential in terms of DC. In other words, if the source electrode and the drain electrode are not at the same potential in terms of DC, nonlinearity between the source electrode and the drain electrode becomes apparent, and when the transmission signal passes due to the manifestation of this nonlinearity, higher order harmonic Distortion occurs. That is, one factor that causes high-order harmonic distortion in the transmission signal is nonlinearity between the source electrode and the drain electrode in the transistor Q1. For this reason, generation | occurrence | production of a high order harmonic distortion can be suppressed by making a source electrode and a drain electrode into the same electric potential like DC with resistance Rd1. For the same reason, the transistor R2 also has a resistor Rd2 between the source electrode and the drain electrode, and the transistor Q3 also has a resistor Rd3 between the source electrode and the drain electrode.

  In FIG. 7, for example, when the source electrode and the drain electrode are connected by the resistor Rd1, it is considered that the source electrode and the drain electrode are conductive even when the transistor Q1 is turned off. Since the resistance Rd1 is sufficiently large to shield the RF signal, the RF signal flows between the source electrode and the drain electrode when the transistor Q1 is off. There is nothing.

<New problem found by the present inventor>
As described above, high-order harmonic distortion generated from the antenna switch ASW becomes a problem. The present inventor has studied high-order harmonic distortion generated from the antenna switch ASW, and as a result, the following is shown. I found a new problem. This problem will be described.

  As a communication system for mobile phones, for example, there is a time division multiple access system (TDMA system). The time division multiple access method is a technology that divides a carrier frequency used for transmission into units called time slots and enables a plurality of communications at the same frequency. For example, in the time division multiple access method, as shown in FIG. 8, there are eight time slots (576.9 μsec) in one frame (4.615 msec), and a transmission mode and a reception mode are assigned to each time slot. Thus, a plurality of communications is possible. FIG. 8 is a diagram illustrating a test mode (local mode) in which a plurality of time slots are used only for the transmission mode. In the test mode shown in FIG. 8, it has been verified that the high-order harmonic distortion generated from the antenna switch ASW is at a level that does not cause a problem. That is, when a plurality of time slots are used only in the transmission mode, the level of high-order harmonic distortion during transmission is low.

  On the other hand, FIG. 9 is a diagram illustrating an example in which communication is actually performed using a mobile phone. FIG. 9 shows a case where the transmission mode exists immediately after the reception mode. This corresponds to the fact that when communicating with an actual mobile phone, first, the base station that can receive and communicate with the radio wave from the base station is confirmed, and then the radio wave is transmitted from the mobile phone to the confirmed base station. It is a thing. That is, in actual mobile phone communication, there is generally a combination in which the transmission mode exists immediately after the reception mode. Compared with the test mode shown in FIG. 8, when the transmission mode exists immediately after the reception mode as shown in FIG. 9, the high-order harmonic distortion generated from the antenna switch ASW increases. The inventor has newly found out. In particular, the present inventor has found that an increase in high-order harmonic distortion becomes significant in a mode in which a transmission signal is transmitted in a GSM low frequency band (GSM) with a large power exceeding 30 dB.

  Therefore, when the present inventor investigated this cause, it was thought that there was a cause of an increase in high-order harmonic distortion in the transition from the reception mode to the transmission mode. That is, in the test mode in which only the transmission mode exists, there is no state that makes a transition from the transmission mode, whereas in the normal communication mode, there exists a state that makes a transition from the reception mode to the transmission mode. Specifically, in the test mode, there is no on / off switching in the antenna switch ASW, whereas in the normal communication mode, there is an on / off switching in the antenna switch ASW. It is speculated that this may be a cause of the increase in distortion. Therefore, the present inventor first examined high-order harmonic distortion generated from the turned-off transistor and high-order harmonic distortion generated from the turned-on transistor in the antenna switch ASW.

<High-order harmonic distortion generated from an off transistor>
The high-order harmonic distortion generated from the transistor that is turned off will be described. FIG. 10 shows the relationship between the gate electrode potential Vgs and the drain current Ids relative to the source electrode of the transistor, and the relationship between the gate electrode potential Vgs and the gate-source capacitance Cgs relative to the source electrode. It is a graph. In FIG. 10, the horizontal axis represents the potential Vgs, and the vertical axis represents the drain current Ids and the gate-source capacitance Cgs. At this time, in FIG. 10, the horizontal axis extends to the left from the origin (0 V). The potential Vgs has a negative value, and the absolute value increases as it proceeds to the left.

  First, looking at the relationship between the potential Vgs and the drain current Ids, the drain current Ids flows when the value of the potential Vgs exceeds the threshold voltage Vth. This state is the on state of the transistor. On the other hand, when the value of the potential Vgs becomes smaller than the threshold voltage Vth, the drain current Ids does not flow. This state is an off state of the transistor. That is, in FIG. 10, when the value of the potential Vgs is larger than the threshold voltage Vth (when the potential Vgs is on the right side of Vth), the transistor is on, and the value of the potential Vgs is When it is lower than the voltage Vth (when the potential Vgs is on the left side of Vth), it indicates an off state of the transistor.

  Next, the relationship between the potential Vgs of the gate electrode with reference to the source electrode of the transistor and the gate-source capacitance will be described. As shown in FIG. 10, when the value of the potential Vgs increases (the absolute value decreases because the potential Vgs is negative), the gate-source capacitance Cgs increases. On the other hand, when the value of the potential Vgs becomes small (because the potential Vgs is negative, the absolute value becomes large), the gate-source capacitance Cgs decreases. This can be explained as follows. For example, the fact that the potential Vgs is smaller than the threshold voltage Vth means that the transistor is turned off. In a transistor that is turned off, a depletion layer between the gate electrode and the source electrode spreads, and as the potential Vgs becomes smaller than the threshold voltage Vth, the transistor is turned off deeper and the depletion layer spreads. This means that as the potential Vgs becomes lower than the threshold voltage Vth, the width of the depletion layer serving as the capacitive insulating film of the gate-source capacitance Cgs increases, and the gate-source capacitance Cgs becomes smaller. It goes down. On the other hand, when the potential Vgs is higher than the threshold voltage Vth, it means that the transistor is turned on. In a transistor that is turned on, the width of the depletion layer decreases and a channel region is formed, so that the gate-source capacitance CGs increases. Therefore, the gate-source capacitance Cgs decreases as the potential Vgs decreases, and the gate-source capacitance Cgs increases as the potential Vgs increases. At this time, the change in the gate-source capacitance Cgs is shown by a curve as shown in FIG. In particular, it can be seen that in the region A in the vicinity of the threshold voltage Vth, the gate-source capacitance Cgs changes abruptly. That is, the change in the gate-source capacitance Cgs in the region A means that the nonlinearity is increased.

  Here, a transistor that is turned off in FIG. 10 is considered. It is assumed that the potential Vgs of the gate electrode with reference to the source electrode of the transistor that is turned off is −Vant ′. Assume that an RF signal is input to the transistor that is turned off. Then, as shown in FIG. 10, the potential Vgs changes with the RF signal superimposed on −Vant ′. For example, the potential Vgs changes with an amplitude (Vin / 2) around −Vant ′. In this case, the gate-source capacitance Cgs also changes as the potential Vgs changes. At this time, as shown in FIG. 10, when the change in the potential Vgs reaches the vicinity of the threshold voltage Vth, the change in the gate-source capacitance Cgs is also performed in the region A where the nonlinear component is large. Therefore, in the transistor that is turned off, the gate-source capacitance Cgs changes due to the input RF signal, and high-order harmonic distortion occurs due to the non-linearity of the changed gate-source capacitance Cgs. . That is, in the transistor that is turned off, high-order harmonic distortion is generated due to the nonlinearity of the gate-source capacitance Cgs.

  Therefore, in order to suppress generation of high-order harmonic distortion from the transistor that is turned off, the following technique is employed. FIG. 11 shows the relationship between the gate electrode potential Vgs and the drain current Ids relative to the source electrode of the transistor, and the relationship between the gate electrode potential Vgs and the gate-source capacitance Cgs relative to the source electrode. It is a graph. In FIG. 11, the horizontal axis indicates the potential Vgs, and the vertical axis indicates the drain current Ids and the gate-source capacitance Cgs. At this time, in FIG. 11, the horizontal axis extends to the left from the origin (0 V). The potential Vgs has a negative value, and the absolute value increases as it proceeds to the left.

  In FIG. 11, a transistor that is turned off is considered. It is assumed that the potential Vgs of the gate electrode with reference to the source electrode of the transistor that is turned off is −Vant. -Vant shown in FIG. 11 is sufficiently smaller than -Vant 'shown in FIG. Assume that an RF signal is input to the transistor that is turned off. Then, as shown in FIG. 11, the potential Vgs is changed by superimposing the RF signal on -Vant. For example, the potential Vgs changes with an amplitude (Vin / 2) around -Vant. In this case, the gate-source capacitance Cgs also changes as the potential Vgs changes. At this time, as shown in FIG. 11, since −Vant is sufficiently smaller than the threshold voltage Vth, the change in the potential Vgs does not reach the vicinity of the threshold voltage Vth. Therefore, the change of the gate-source capacitance Cgs is performed in the region B where the nonlinear component is small. For this reason, in the transistor that is turned off, the gate-source capacitance Cgs is changed by the input RF signal. However, since the non-linearity of the changed gate-source capacitance Cgs is small, high-order harmonic distortion is reduced. Generation can be suppressed. That is, in order to suppress the occurrence of high-order harmonic distortion from the transistor that is turned off, it can be realized by making the potential Vgs of the gate electrode with reference to the source electrode sufficiently lower than the threshold voltage Vth. Recognize.

<High-order harmonic distortion generated from an on transistor>
Next, high-order harmonic distortion generated from a transistor that is turned on will be described. High-order harmonic distortion generated from a transistor that is turned on has a positive correlation with non-linear on-resistance. As the on-resistance increases, higher-order harmonic distortion also increases. Therefore, it can be seen that the on-resistance needs to be reduced in order to suppress high-order harmonic distortion generated from the transistor that is turned on.

  As described above, high-order harmonic distortion from an off transistor can be suppressed by sufficiently reducing the potential Vgs of the gate electrode with respect to the source electrode. However, as a result of studies by the present inventors, it has been found that if the potential Vgs is sufficiently small, the on-resistance when the transistor is turned on increases. That is, if the potential Vgs is sufficiently lowered to suppress high-order harmonic distortion from the off transistor, the on-resistance of the transistor that has transitioned from off to on increases, and the higher order generated from the on transistor. It was found that harmonic distortion increased.

  Specifically, FIG. 12 is a diagram illustrating a relationship between the potential Vgs of the gate electrode with respect to the source electrode of the transistor and the on-resistance. In FIG. 12, the horizontal axis represents the potential Vgs, and the vertical axis represents the on-resistance Ron. At this time, in FIG. 12, the horizontal axis extends to the left from the origin (0 V). The potential Vgs has a negative value, and the absolute value increases as it proceeds to the left. As shown in FIG. 12, it can be seen that the on-resistance Ron increases as the potential Vgs of the off transistor decreases. For example, when the potential Vgs of the transistor that is turned off is −Vant ′, it is turned on when the potential Vgs of the transistor that is turned off is −Vant rather than the on-resistance R1 when the transistor is turned on. In this case, the on-resistance R2 is larger. Accordingly, the lower the potential Vgs of the transistor that is turned off, the larger the on-resistance Ron when it is turned on, and the higher-order harmonic distortion generated from the transistor that is turned on increases.

  It is considered that the lower the potential Vgs of the transistor that is turned off in this way, the higher the on-resistance of the transistor that has turned on is due to the following mechanism. That is, when the transistor is turned off with the potential Vgs lower than the threshold voltage Vth, a trap level (capture level) is generated around the gate electrode of the transistor that is turned off, and holes are trapped in the trap level. (Hole) and electrons are captured. As a result, when a transition is made from off to on, the channel region (region in which carriers can freely move) of the transistor is narrowed, and the on-resistance Ron having nonlinearity increases. According to this mechanism, the lower the potential Vgs, the more trap levels that are generated. As a result, it can be considered that when the transistor transitions from off to on, the channel region (region in which carriers can freely move) of the transistor becomes narrow, and the on-resistance Ron having nonlinearity increases.

  From the above, in order to suppress high-order harmonic distortion generated from an off transistor, it is realized by making the potential Vgs of the gate electrode with reference to the source electrode sufficiently lower than the threshold voltage Vth. it can. However, it can be seen that if the potential Vgs of the transistor that is turned off is sufficiently lowered, the on-resistance Ron of the transistor that has transitioned from off to on increases, and the higher-order harmonic distortion generated from the turned-on transistor increases. . This phenomenon is considered to be the cause of the problem newly found by the present inventors. In other words, in the test mode in which only the transmission mode exists, the transistor that is turned off does not transition to the on state, so the source electrode is used as a reference in order to suppress high-order harmonic distortion that occurs from the transistor that is turned off. Even if the gate electrode potential Vgs is sufficiently lower than the threshold voltage Vth, it is not necessary to consider the effect of high-order harmonic distortion generated from the transistor that is turned on. On the other hand, in the communication mode in which the transmission mode exists immediately after the reception mode, a transistor that is turned off in the reception mode is turned on in the transmission mode, so that there is a transistor that transitions from off to on. In this case, when the potential Vgs of the gate electrode with respect to the source electrode is sufficiently lower than the threshold voltage Vth in order to suppress high-order harmonic distortion generated from the transistor that is turned off, the transistor is turned from off to on. The on-resistance Ron of the transitioning transistor rises, and the higher-order harmonic distortion generated from the turned-on transistor increases. From this, it is considered that the higher-order harmonic distortion generated from the antenna switch ASW is increased in the communication mode in which the transmission mode exists immediately after the reception mode as compared with the test mode. In particular, when the transmission mode existing immediately after the reception mode is a mode for transmitting a GSM low frequency band (GSM) transmission signal, an increase in high-order harmonic distortion is significant. This is a large power with a GSM low frequency band (GSM) power exceeding 30 dB, and in order to suppress the generation of high-order harmonic distortion from an off transistor, the gate electrode with respect to the source electrode is used as a reference. This is because the potential Vgs needs to be considerably lower than the threshold voltage Vth.

<Characteristics of antenna switch in this embodiment>
Therefore, the antenna switch ASW in the present embodiment takes the following countermeasures. Specifically, in the transistor Q1 which is turned on when transmitting a GSM low frequency band (GSM) transmission signal and turned off when transmitting a GSM high frequency band (DCS / PCS) transmission signal and receiving a reception signal. The potential Vgs1 applied to the gate electrode with reference to the source electrode of the transistor Q1 that is turned off is configured to be larger than in the prior art. That is, the feature of this embodiment is that the potential Vgs1 when the transistor Q1 shown in FIG. 7 is off is larger than the potential Vgs2 when the transistor Q2 is off or the potential Vgs3 when the transistor Q3 is off. In other words, since the off-state potential Vgs1 to Vgs3 are negative, the off-state potential Vgs1 of the transistor Q1 is used as the off-state potential Vgs2 of the transistor Q2 or the off-state potential Vgs3 of the transistor Q3. The larger value means that the absolute value of the potential Vgs1 when the transistor Q1 is off is made smaller than the absolute value of the potential Vgs2 when the transistor Q2 is off or the absolute value of the potential Vgs3 when the transistor Q3 is off. Can do. As a result, when shifting from the reception mode to the GSM low frequency band (GSM) transmission mode, the transistor Q1 transitions from the off state to the on state, but the absolute value of the potential Vgs1 when the transistor Q1 is off is reduced. Thus, the on-resistance Ron of the transistor Q1 transitioned from off to on can be reduced. As a result, it is possible to suppress an increase in high-order harmonic distortion generated from the transistor Q1 that is turned on.

  FIG. 13 is a diagram illustrating a relationship between the potential Vgs of the gate electrode with respect to the source electrode of the transistor and the on-resistance. In FIG. 13, the horizontal axis represents the potential Vgs1, and the vertical axis represents the on-resistance Ron. At this time, in FIG. 13, the horizontal axis extends to the left from the origin (0 V). The potential Vgs1 has a negative value, and the absolute value increases as it proceeds to the left. At this time, for example, by increasing the potential Vgs1 when the transistor Q1 is off from −Vant to −Vant + 1, the on-resistance Ron of the transistor Q1 that has transitioned from the off state to the on state can be reduced. In other words, by reducing the absolute value of the potential Vgs1 when the transistor Q1 is off from Vant to Vant-1, the on-resistance Ron of the transistor Q1 that has transitioned from the off state to the on state can be reduced. As a result, it can be seen that an increase in high-order harmonic distortion generated from the turned-on transistor Q1 can be suppressed.

  Here, the reason why the absolute value of the potential Vgs1 when the transistor Q1 is off is reduced by the transistor Q1 and the absolute value of the potential Vgs2 when the transistor Q2 is off and the absolute value of the potential Vgs3 when the transistor Q3 is off is not reduced below. Depending on the reason shown. That is, when there is a transmission mode for transmitting a GSM low frequency band (GSM) transmission signal immediately after the reception mode, it is necessary to suppress an increase in high-order harmonic distortion. At this time, the transistor that transitions from the off state to the on state is the transistor Q1, the transistor Q2 maintains the off state, and the transistor Q3 transitions from the on state to the off state. In other words, in the transistor Q1 that transitions from the off state to the on state, the absolute value of the off-state potential Vgs1 is reduced, so that even when the occurrence of high-order harmonic distortion in the off state is slightly increased, the on-state (GSM low This is because it is necessary to reduce the occurrence of high-order harmonic distortion in a transmission mode in which a transmission signal in the frequency band (GSM) is transmitted. On the other hand, in the transmission mode in which a GSM low frequency band (GSM) transmission signal is transmitted, the transistor Q2 and the transistor Q3 are in an off state. Therefore, in the transmission mode in which a GSM low frequency band (GSM) transmission signal is transmitted, the requirement required for the transistors Q2 and Q3 is to reduce the occurrence of high-order harmonic distortion when turned off. Therefore, in the transistor Q2 and the transistor Q3, in order to suppress the occurrence of high-order harmonic distortion when the transistor Q2 is off, the absolute value of the potential Vgs2 when the transistor Q2 is off and the absolute value of the potential Vgs3 when the transistor Q3 is off are Is not made as small as transistor Q1.

  Next, when the absolute value of the off-state potential Vgs1 is reduced in the transistor Q1, it is considered that the generation of high-order harmonic distortion when the transistor Q1 is off increases. When the transistor Q1 is off, the transmission mode is the transmission mode for transmitting a GSM high frequency band (DCS / PCS) transmission signal.

  FIG. 14 shows the relationship between the gate voltage Vtx1c applied to the gate electrode of the transistor Q1 in the off state and the second harmonic distortion PCS_2HD and the third harmonic distortion PCS_3HD generated in the transmission mode of the GSM high frequency band (DCS / PCS). It is a graph which shows a relationship. At this time, the gate voltage Vtx1c is different from the gate electrode potential Vgs1 with respect to the source electrode, and the gate voltage Vtx1c is a voltage actually applied to the gate electrode. That is, the potential Vgs1 is the potential of the gate electrode with reference to the potential of the source electrode, and the potential Vgs1 represents the gate voltage Vtx1c with respect to the potential of the source electrode. For example, when the potential of the source electrode is Vs, Vtx1c−Vs = Vgs1. Therefore, increasing the value of Vtx1c within a range not exceeding the value of Vs means that the absolute value of the potential Vgs1 is reduced when converted to the potential Vgs1. For example, when the potential Vs of the source electrode is 4V, the potential Vgs1 is −4V when the gate voltage Vtx1c is 0V, and the potential Vgs is −3V when the gate voltage Vtx1c is 1V.

  Therefore, increasing the gate voltage Vtx1c of the transistor Q1 that is turned off corresponds to reducing the absolute value of the potential Vgs1 of the transistor Q1 that is turned off. 14 under this condition, when the gate voltage Vtx1c of the transistor Q1 that is turned off is increased (when the absolute value of the potential Vgs1 of the transistor Q1 that is turned off is reduced), the GSM high frequency band (DCS / It can be seen that second-order harmonic distortion PCS_2HD and third-order harmonic distortion PCS_3HD generated in the transmission mode of (PCS) are increasing. The second harmonic distortion PCS_2HD and the third harmonic distortion PCS_3HD are displayed in decibels. This decibel display indicates how much the magnitude of the higher harmonic distortion attenuates from the power of the input power. Yes. That is, as the decibel display of the higher order harmonic distortion becomes smaller, the attenuation becomes smaller, indicating that the magnitude of the higher order harmonic distortion has increased.

  As can be seen from FIG. 14, when the gate voltage Vtx1c of the transistor Q1 that is turned off exceeds 1V, the higher-order harmonic distortion (second-order harmonic distortion PCS_2HD and third-order harmonic distortion PCS_3HD) increases. Therefore, it can be seen that the gate voltage Vtx1c of the transistor Q1 that is turned off needs to be 1 V or less. In other words, if the absolute value of the potential Vgs1 of the transistor Q1 that is turned off is smaller than (Vs-1), higher-order harmonic distortion that occurs in the transmission mode of the GSM high frequency band (DCS / PCS) may increase. Recognize.

  From the above, from the viewpoint of suppressing high-order harmonic distortion generated in the GSM low frequency band (GSM) transmission mode, it is desirable to reduce the absolute value of the potential Vgs1 of the transistor Q1 that is turned off. If it is too small, the higher-order harmonic distortion generated in the transmission mode of the GSM high frequency band (DCS / PCS) will increase. For this reason, the absolute value of the potential Vgs1 of the transistor Q1 that is turned off is reduced, but by making the absolute value of the potential Vgs1 of the transistor Q1 that is turned off larger than (Vs-1), the GSM low frequency band ( In both the GSM transmission mode and the GSM high frequency band (DCS / PCS) transmission mode, an increase in high-order harmonic distortion can be suppressed.

<Characteristic Operation of Antenna Switch in this Embodiment>
Hereinafter, a characteristic operation of the antenna switch according to the present embodiment will be described. First, a case where a received signal is received from an antenna will be described. When a positive voltage (˜4 V) is applied to the gate electrode G3 of the transistor Q3, the voltage applied to the gate electrode G3 is a threshold voltage Vth (generally −1.0 V with respect to the source electrode (or drain electrode)). Transistor Q3 is turned on. That is, in the transistor Q3, since the potential Vgs3 of the gate electrode G3 with respect to the source electrode is equal to or higher than the threshold voltage, the transistor Q3 is turned on. At the same time, a voltage (about 0.5 V lower) that is lowered by the Schottky barrier is applied to the source electrode (or drain electrode). Here, when the transistor Q3 is turned on, the source electrode (drain electrode) is applied with a potential that is lower than the voltage applied to the gate electrode G3 by a Schottky barrier, as described above. It is assumed that the same potential as the gate electrode G3 is applied to the source electrode (drain electrode) of the transistor Q3 ignoring the voltage drop for the key barrier. Therefore, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q3 is a positive potential (˜4V).

  On the other hand, 1 V is applied to the gate electrode G1 of the transistor Q1 in order to turn off the transistor Q1. This positive potential (˜4V) is applied to the source electrode and the drain electrode of the transistor Q3 by the positive voltage (˜4V) applied to the gate electrode G3 to turn on the transistor Q3. That is, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q3 becomes a positive potential (˜4 V), and the transistor Q1 electrically connected to the antenna terminal TE (ANT). A positive potential (˜4 V) is also applied to the source electrode. Since the gate electrode G1 of the transistor Q1 is 1V, the gate electrode G1 has a voltage lower than the threshold voltage Vth with respect to the source electrode (drain electrode). That is, in the transistor Q1, since the potential Vgs1 (˜−3 V) of the gate electrode G1 with respect to the source electrode is equal to or lower than the threshold voltage, the transistor Q1 is turned off.

  0 V is applied to the gate electrode G2 of the transistor Q2. This positive potential (˜4V) is applied to the source electrode and the drain electrode of the transistor Q3 by the positive voltage (˜4V) applied to the gate electrode G3 to turn on the transistor Q3. That is, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q3 becomes a positive potential (˜4 V), and the transistor Q2 electrically connected to the antenna terminal TE (ANT). A positive potential (˜4 V) is also applied to the source electrode. Since the gate electrode G2 of the transistor Q2 is 0 V, the gate electrode G2 has a voltage lower than the threshold voltage Vth with respect to the source electrode (drain electrode). That is, in the transistor Q2, since the potential Vgs2 (˜−4 V) of the gate electrode G2 with respect to the source electrode is equal to or lower than the threshold voltage, the transistor Q2 is turned off.

  Therefore, the antenna terminal TE (ANT) is electrically connected to the reception terminal RX via the transistor Q3 that is turned on. In this state, a reception signal (AC signal) input from the antenna terminal TE (ANT) to the antenna switch is output to the reception terminal RX through the transistor Q3 in the conductive state, and then input to the reception circuit.

  At this time, the feature of this embodiment is that 1V is applied to the gate electrode G1 of the transistor Q1, thereby setting the potential Vgs1 of the gate electrode G1 with respect to the source electrode to about −3V, thereby turning off the transistor Q1. It is in. On the other hand, by applying 0 V to the gate electrode G2 of the transistor Q2, the potential Vgs2 of the gate electrode G2 with respect to the source electrode is set to about −4 V, and the transistor Q2 is turned off.

  Next, the operation of the antenna switch ASW when transmitting a GSM low frequency band (GSM) transmission signal from an antenna will be described with reference to FIG.

  When a positive voltage (˜4V) is applied to the gate electrode G1 of the transistor Q1, the voltage applied to the gate electrode G1 is a threshold voltage Vth (generally −1.0V) with respect to the source electrode (or drain electrode). Transistor Q1 is turned on. That is, in the transistor Q1, since the potential Vgs1 of the gate electrode G1 with respect to the source electrode is equal to or higher than the threshold voltage, the transistor Q1 is turned on. At the same time, a voltage that is lowered by the amount corresponding to the Schottky barrier (down by about 0.5 V) is applied to the source electrode (or drain electrode). Here, when the transistor Q1 is turned on, the source electrode (drain electrode) is applied with a potential that is lower than the voltage applied to the gate electrode G1 by the Schottky barrier, as described above. It is assumed that the same potential as the gate electrode G1 is applied to the source electrode (drain electrode) of the transistor Q1, ignoring the voltage drop for the key barrier. Therefore, the potential Vant of the antenna terminal TE (ANT) that is electrically connected to the source electrode of the transistor Q1 is a positive potential (˜4 V).

  On the other hand, in order to turn off the transistor Q2, 0V is applied to the gate electrode G2 of the transistor Q2. This positive potential (˜4V) is applied to the source electrode and the drain electrode of the transistor Q1 by the positive voltage (˜4V) applied to the gate electrode G1 to turn on the transistor Q1. That is, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q1 becomes a positive potential (˜4 V), and the transistor Q2 electrically connected to the antenna terminal TE (ANT). A positive potential (˜4 V) is also applied to the source electrode. Since the gate electrode G2 of the transistor Q2 is 0 V, the gate electrode G2 has a voltage lower than the threshold voltage Vth with respect to the source electrode (drain electrode). That is, in the transistor Q2, since the potential Vgs2 (˜−4 V) of the gate electrode G2 with respect to the source electrode is equal to or lower than the threshold voltage, the transistor Q2 is turned off.

  Similarly, 0V is applied to the gate electrode G3 of the transistor Q3. This positive potential (˜4V) is applied to the source electrode and the drain electrode of the transistor Q1 by the positive voltage (˜4V) applied to the gate electrode G1 to turn on the transistor Q1. That is, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q1 becomes a positive potential (˜4 V), and the transistor Q3 electrically connected to the antenna terminal TE (ANT). A positive potential (˜4 V) is also applied to the source electrode. Since the gate electrode G3 of the transistor Q3 is 0 V, the gate electrode G3 has a voltage lower than the threshold voltage Vth with respect to the source electrode (drain electrode). That is, in the transistor Q3, the potential Vgs3 (˜−4 V) of the gate electrode G3 with respect to the source electrode is equal to or lower than the threshold voltage, so that the transistor Q3 is turned off.

  Therefore, the antenna terminal TE (ANT) is electrically connected to the transmission terminal TX1 via the transistor Q1 that is turned on. In this state, the GSM low frequency band (GSM) transmission signal (AC signal) input from the transmission terminal TX1 to the antenna switch ASW is output to the antenna terminal TE (ANT) through the conductive transistor Q1, Sent from antenna.

  At this time, a feature of this embodiment is that by applying 1 V instead of 0 V to the gate electrode G1 of the transistor Q1, the potential Vgs1 of the gate electrode G1 with respect to the source electrode is set to about −3 V, thereby turning off the transistor Q1. There is in being. From this state, a positive voltage (˜4 V) is applied to the gate electrode G1 of the transistor Q1, and the transistor Q1 is turned on. Therefore, the transistor Q1 can reduce the on-resistance Ron of the transistor Q1 that has transitioned from the off-state to the on-state, for example, by increasing the off-state potential Vgs1 of the transistor Q1 from −4V to −3V. In other words, by reducing the absolute value of the potential Vgs1 when the transistor Q1 is off from 4 V to 3 V, the on-resistance Ron of the transistor Q1 that has transitioned from the off state to the on state can be reduced. As a result, it is possible to suppress an increase in high-order harmonic distortion generated from the transistor Q1 that is turned on.

  Finally, the operation of the antenna switch ASW when transmitting a GSM high frequency band (DCS / PCS) transmission signal from an antenna will be described with reference to FIG.

  When a positive voltage (˜4V) is applied to the gate electrode G2 of the transistor Q2, the voltage applied to the gate electrode G2 is a threshold voltage Vth (generally −1.0V with respect to the source electrode (or drain electrode)). Transistor Q2 is turned on. That is, in the transistor Q2, since the potential Vgs2 of the gate electrode G2 with respect to the source electrode is equal to or higher than the threshold voltage, the transistor Q2 is turned on. At the same time, a voltage that is lowered by the amount corresponding to the Schottky barrier (down by about 0.5 V) is applied to the source electrode (or drain electrode). Here, when the transistor Q2 is turned on, the source electrode (drain electrode) is applied with a potential that is lower by the Schottky barrier than the voltage applied to the gate electrode G2, as described above. Assume that the same potential as the gate electrode G2 is applied to the source electrode (drain electrode) of the transistor Q2 ignoring the voltage drop for the key barrier. Therefore, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q2 becomes a positive potential (˜4V).

  On the other hand, 1 V is applied to the gate electrode G1 of the transistor Q1 in order to turn off the transistor Q1. This positive potential (˜4V) is applied to the source electrode and the drain electrode of the transistor Q2 by the positive voltage (˜4V) applied to the gate electrode G2 to turn on the transistor Q2. That is, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q2 becomes a positive potential (˜4 V), and the transistor Q1 electrically connected to the antenna terminal TE (ANT). A positive potential (˜4 V) is also applied to the source electrode. Since the gate electrode G1 of the transistor Q1 is 1V, the gate electrode G1 has a voltage lower than the threshold voltage Vth with respect to the source electrode (drain electrode). That is, in the transistor Q1, since the potential Vgs1 (˜−3 V) of the gate electrode G1 with respect to the source electrode is equal to or lower than the threshold voltage, the transistor Q1 is turned off.

  0V is applied to the gate electrode G3 of the transistor Q3. This positive potential (˜4V) is applied to the source electrode and the drain electrode of the transistor Q2 by the positive voltage (˜4V) applied to the gate electrode G2 to turn on the transistor Q2. That is, the potential Vant of the antenna terminal TE (ANT) electrically connected to the source electrode of the transistor Q2 becomes a positive potential (˜4 V), and the transistor Q3 electrically connected to the antenna terminal TE (ANT). A positive potential (˜4 V) is also applied to the source electrode. Since the gate electrode G3 of the transistor Q3 is 0 V, the gate electrode G3 has a voltage lower than the threshold voltage Vth with respect to the source electrode (drain electrode). That is, in the transistor Q3, the potential Vgs3 (˜−4 V) of the gate electrode G3 with respect to the source electrode is equal to or lower than the threshold voltage, so that the transistor Q3 is turned off.

  Therefore, the antenna terminal TE (ANT) is electrically connected to the transmission terminal TX2 via the transistor Q2 that is turned on. In this state, after the transmission signal (AC signal) of the GSM high frequency band (DCS / PCS) input from the transmission terminal TX2 to the antenna switch ASW is output to the antenna terminal TE (ANT) through the transistor Q2 in the conductive state. Transmitted from the antenna.

  At this time, the feature of this embodiment is that 1V is applied to the gate electrode G1 of the transistor Q1, thereby setting the potential Vgs1 of the gate electrode G1 with respect to the source electrode to about −3V, thereby turning off the transistor Q1. It is in. On the other hand, by applying 0 V to the gate electrode G3 of the transistor Q3, the potential Vgs3 of the gate electrode G3 with respect to the source electrode is set to about −4 V, and the transistor Q3 is turned off. Therefore, when the transistor Q1 is off, the absolute value of the potential Vgs1 (˜−3V) of the transistor Q1 is smaller than the absolute value of the potential Vgs3 (˜−4V) of the transistor Q3 that is off. The higher order harmonic distortion generated from the transistor Q3 is considered to increase more than the higher order harmonic distortion generated from the transistor Q3 that is turned off. However, as shown in FIG. 14, if the potential Vgs1 of the transistor Q1 that is turned off is about −3V (corresponding to the gate voltage Vtx1c = 1V in FIG. 14), an increase in higher-order harmonic distortion is suppressed. You can see that

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

DESCRIPTION OF SYMBOLS 1 Mobile phone 2 Application processor 3 Memory 4 Baseband part 5 RFIC
6 power amplifier 7 SAW filter 8 antenna switch 9 antenna 10 semi-insulating substrate 11 epitaxial layer 12 buffer layer 13 AlGaAs layer 14 n-type GaAs layer 20 semiconductor substrate 21 buried insulating layer 22 silicon layer A region ANT antenna ASW antenna switch B region Cgs Capacitance between gate and source CHP1 to CHP4 Semiconductor chip CNT Control circuit D1 Drain region DE Drain electrode EX Extension region G Gate electrode G1 to G3 Gate electrode GOX Gate insulating film HPA RF module Ids Drain current IL Interlayer insulating film L1 Wiring LPF_H Low pass filter LPF_L Low pass filter MN_H Output matching circuit MN_L Output matching circuit PA_H Amplifying circuit PA_L Amplifying circuit PCS_2HD Second harmonic Distortion PCS_3HD Third harmonic distortion PLG plug Q1 to Q3 Transistors Rd1 to Rd3 Resistance Rgg1 to Rgg3 Gate resistance R1 On resistance R2 On resistance Ron On resistance RX Receive terminal RX1c Gate terminal S1 Source region SE Source electrode SMD Passive component STI Element isolation region SW side wall TE (ANT) antenna terminal TE (OUT) output terminal TE (RX_H) receiving terminal TE (RX_L) receiving terminal TE (TX_H) input terminal TE (TX_L) input terminal TX1 transmitting terminal TX1c gate terminal TX2 transmitting terminal TX2c gate Terminal Vant potential Vgs potential Vgs1 to Vgs3 potential Vth threshold voltage Vtx1c Gate voltage WB Wiring board

Claims (16)

(A) an antenna terminal electrically connected to the antenna;
(B) a transmission terminal to which a transmission signal is transmitted;
(C) a receiving terminal to which a received signal is transmitted;
(D) a transmission FET connected between the transmission terminal and the antenna terminal and functioning as a switch;
(E) a receiving FET connected between the receiving terminal and the antenna terminal and functioning as a switch;
(F) a control terminal for inputting a control signal for controlling on / off of the transmission FET and the reception FET;
The transmission FET is
(D1) a pair of first source region and first drain region formed separately in the semiconductor substrate;
(D2) having a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region and connected to the control terminal;
The receiving FET is
(E1) A pair of second source region and second drain region formed separately from each other in the semiconductor substrate;
(E2) having a second gate electrode formed on the semiconductor substrate between the second source region and the second drain region and connected to the control terminal;
When transmitting the transmission signal from the antenna, the control signal input from the control terminal is used as a threshold of the first gate electrode with respect to the first source region of the transmission FET. A first potential higher than a value voltage is applied to turn on the transmission FET, and a potential of the second gate electrode with respect to the second source region of the reception FET is set to be higher than a threshold voltage. While applying a low second potential to turn off the receiving FET,
When receiving the received signal from the antenna, the control signal input from the control terminal is used as a threshold of the first gate electrode with respect to the first source region of the transmitting FET. A third potential lower than the value voltage is applied to turn off the transmission FET, and a potential of the second gate electrode with respect to the second source region of the reception FET is set to be higher than a threshold voltage. A semiconductor device configured to turn on the receiving FET by applying a high fourth potential,
The semiconductor device according to claim 1, wherein an absolute value of the third potential is smaller than an absolute value of the second potential. The semiconductor device according to claim 1,
The semiconductor device, wherein the first potential and the fourth potential are the same potential. The semiconductor device according to claim 1,
The transmission FET is a high electron mobility transistor in which a Schottky barrier exists between the semiconductor substrate and the first gate electrode,
The semiconductor device according to claim 1, wherein the receiving FET is a high electron mobility transistor having a Schottky barrier between the semiconductor substrate and the second gate electrode. The semiconductor device according to claim 1,
The transmission FET is a MISFET in which a first gate insulating film is formed between the semiconductor substrate and the first gate electrode.
The semiconductor device according to claim 1, wherein the receiving FET is a MISFET in which a second gate insulating film is formed between the semiconductor substrate and the second gate electrode. (A) a wiring board;
(B) an antenna switch semiconductor chip on which an antenna switch is formed;
(C) an amplifier circuit semiconductor chip in which an amplifier circuit for amplifying the power of the transmission signal is formed;
(D) comprising a control circuit semiconductor chip on which a control circuit for controlling the amplifier circuit and the antenna switch is formed;
The antenna switch semiconductor chip is:
(B1) a connected antenna terminal electrically connected to the antenna;
(B2) a transmission terminal to which the transmission signal is transmitted;
(B3) a receiving terminal to which the received signal is transmitted;
(B4) a transmission FET connected between the transmission terminal and the antenna terminal and functioning as a switch;
(B5) a reception FET connected between the reception terminal and the antenna terminal and functioning as a switch;
(B6) including a control terminal to which a control signal for controlling ON / OFF of the transmission FET and ON / OFF of the reception FET is transmitted,
The transmission FET is
(B41) A pair of first source region and first drain region formed separately in the semiconductor substrate;
(B42) a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region and connected to the control terminal;
The receiving FET is
(B51) a pair of second source region and second drain region formed separately from each other in the semiconductor substrate;
(B52) a second gate electrode formed on the semiconductor substrate between the second source region and the second drain region and connected to the control terminal;
When transmitting the transmission signal from the antenna, the control circuit uses a first potential higher than a threshold voltage as a potential of the first gate electrode with respect to the first source region of the transmission FET. And applying the second potential lower than the threshold voltage as the potential of the second gate electrode with reference to the second source region of the receiving FET. While turning off the receiving FET,
When receiving the received signal from the antenna, the control circuit uses a third potential lower than a threshold voltage as the potential of the first gate electrode with respect to the first source region of the transmitting FET. And applying a fourth potential higher than a threshold voltage as the potential of the second gate electrode with reference to the second source region of the receiving FET. A semiconductor device configured to turn on a receiving FET,
The semiconductor device according to claim 1, wherein an absolute value of the third potential is smaller than an absolute value of the second potential. The semiconductor device according to claim 5,
The semiconductor device for an amplifier circuit and the semiconductor chip for a control circuit are constituted by separate semiconductor chips. The semiconductor device according to claim 5,
The semiconductor device for an amplifier circuit and the semiconductor chip for a control circuit are constituted by the same semiconductor chip. The semiconductor device according to claim 5,
The transmission FET is a high electron mobility transistor in which a Schottky barrier exists between the semiconductor substrate and the first gate electrode,
The semiconductor device according to claim 1, wherein the receiving FET is a high electron mobility transistor having a Schottky barrier between the semiconductor substrate and the second gate electrode. (A) a wiring board;
(B) an antenna switch semiconductor chip on which an antenna switch is formed;
(C) a first amplifier circuit that amplifies the power of the first transmission signal in the first frequency band, and a second amplifier circuit that amplifies the power of the second transmission signal in the second frequency band different from the first frequency band. A formed semiconductor chip for an amplifier circuit;
(D) comprising a control circuit semiconductor chip on which a control circuit for controlling the amplifier circuit and the antenna switch is formed;
The antenna switch semiconductor chip is:
(B1) a connected antenna terminal electrically connected to the antenna;
(B2) a first transmission terminal to which the first transmission signal is transmitted;
(B3) a second transmission terminal to which the second transmission signal is transmitted;
(B4) a receiving terminal to which a received signal is transmitted;
(B5) a first transmission FET connected between the first transmission terminal and the antenna terminal and functioning as a switch;
(B6) a second transmission FET connected between the second transmission terminal and the antenna terminal and functioning as a switch;
(B7) a receiving FET connected between the receiving terminal and the antenna terminal and functioning as a switch;
(B8) including a control terminal to which a control signal for controlling on / off of the first transmission FET, on / off of the second transmission FET, and on / off of the reception FET is transmitted. ,
The first transmission FET is
(B51) a pair of first source region and first drain region formed separately in the semiconductor substrate;
(B52) having a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region and connected to the control terminal;
The second transmission FET is
(B61) a pair of second source region and second drain region formed separately in the semiconductor substrate;
(B62) a second gate electrode formed on the semiconductor substrate between the second source region and the second drain region and connected to the control terminal;
The receiving FET is
(B71) A pair of third source region and third drain region formed separately in the semiconductor substrate;
(B72) a third gate electrode formed on the semiconductor substrate between the third source region and the third drain region and connected to the control terminal;
When transmitting the first transmission signal from the antenna, the control circuit is higher than a threshold voltage as the potential of the first gate electrode with respect to the first source region of the first transmission FET. The first potential is applied to turn on the first transmission FET, and the potential of the second gate electrode with respect to the second source region of the second transmission FET is higher than a threshold voltage. A second low potential is applied to turn off the second transmission FET, and the potential of the third gate electrode with respect to the third source region of the reception FET is lower than a threshold voltage. Applying a second potential to turn off the receiving FET;
When transmitting the second transmission signal from the antenna, the control circuit is lower than a threshold voltage as a potential of the first gate electrode with respect to the first source region of the first transmission FET. A third potential is applied to turn off the first transmission FET, and the potential of the second gate electrode with respect to the second source region of the second transmission FET is greater than a threshold voltage. The high first potential is applied to turn on the second transmission FET, and the potential of the third gate electrode with respect to the third source region of the reception FET is lower than a threshold voltage Applying the second potential to turn off the receiving FET;
When receiving the received signal from the antenna, the control circuit uses the first gate electrode potential that is lower than a threshold voltage as a potential of the first gate electrode with respect to the first source region of the first transmission FET. Three potentials are applied to turn off the first transmission FET, and the potential of the second gate electrode with respect to the second source region of the second transmission FET is lower than a threshold voltage The second potential is applied to turn off the second transmission FET, and the potential of the third gate electrode with respect to the third source region of the reception FET is higher than a threshold voltage. A semiconductor device configured to turn on the receiving FET by applying a first potential,
The semiconductor device according to claim 1, wherein an absolute value of the third potential is smaller than an absolute value of the second potential. The semiconductor device according to claim 9,
The power of the first transmission signal in the first frequency band is greater than the power of the second transmission signal in the second frequency band. The semiconductor device according to claim 10,
The semiconductor device according to claim 1, wherein a frequency of the first frequency band is smaller than a frequency of the second frequency band. The semiconductor device according to claim 9,
The control circuit includes a first transmission mode for transmitting the first transmission signal from the antenna, a second transmission mode for transmitting the second transmission signal from the antenna, and a reception mode for receiving the reception signal from the antenna. Are operated by a time division multiple access method. A semiconductor device according to claim 12,
The time division multiple access method implemented by the control circuit includes a case of operating the first transmission mode immediately after operating the reception mode. The semiconductor device according to claim 9,
The semiconductor device for an amplifier circuit and the semiconductor chip for a control circuit are constituted by separate semiconductor chips. The semiconductor device according to claim 9,
The semiconductor device for an amplifier circuit and the semiconductor chip for a control circuit are constituted by the same semiconductor chip. The semiconductor device according to claim 9,
The first transmission FET is a high electron mobility transistor in which a Schottky barrier exists between the semiconductor substrate and the first gate electrode,
The second transmission FET is a high electron mobility transistor in which a Schottky barrier exists between the semiconductor substrate and the second gate electrode,
The semiconductor device according to claim 1, wherein the receiving FET is a high electron mobility transistor having a Schottky barrier between the semiconductor substrate and the third gate electrode.

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