JP2009081474A - Switching element and antenna switch circuit using the same, and high frequency module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching element capable of stabilizing electric potential between gates of multi-gates without increasing insertion loss between them, to provide an antenna switch circuit using the same, and to provide a high frequency module. <P>SOLUTION: The switching element includes two ohmic electrodes 39 and 40 formed on a semiconductor substrate, at least two gate electrodes 41 and 42 arranged between the two ohmic electrodes, and a conductive region 45 arranged with being interposed between adjacent gate electrodes so as to constitute a field effect transistor. One end portion of the conductive region is wider than the portion interposed between adjacent gate electrodes, and the distance between the adjacent gate electrodes is shorter than the width of the wide end portion. Further, resistors 44 and 46 are connected in series between the two ohmic electrodes through the wide portion. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a switching element using a field effect transistor in which conduction and non-conduction are controlled, and more particularly to a switching element suitable for intermittently transmitting a signal with high power, and an antenna switch circuit and a high-frequency module using the switching element.

  In a wireless communication device such as a portable terminal, one antenna is commonly used for transmission and reception, and connection to the antenna is often switched by transmission and reception by an antenna switch. When the mobile terminal or the like is compatible with a plurality of communication methods, the antenna switch is configured to switch the connection between the plurality of transmission circuits and reception circuits and the antenna. The transmission signal output from the transmission circuit is usually high power, such as exceeding 1 W in a cellular phone, and the antenna switch is a high-quality transmission signal with high quality and can be used for communication in other frequency bands. The performance is set so as not to include disturbing waves that have an adverse effect. Therefore, when a switch element using a transistor is used as the antenna switch, the switch element is designed to have a high breakdown voltage and suppress harmonic distortion to a low level.

When a field effect transistor is used for the switch element, the power durability can be improved by using a multi-gate transistor in which a plurality of gates are arranged between two ohmic electrodes (drain electrode and source electrode), or It is generally performed to further improve the power durability by connecting the multiple stages. In a multi-gate transistor, Patent Document 1 discloses an example of a structure in which an n ⁺ electrode formed as an inter-gate region between gate electrodes is connected to an ohmic electrode through a resistor whose resistance value is higher than that of the n ⁺ electrode. An example of a structure having four gate electrodes is shown in FIG. Between the ohmic electrodes 16 and 17, gate electrodes 18 to 20 and n ⁺ electrodes 22 to 24 are arranged, and the n ⁺ electrodes 22 to 24 are connected to the ohmic electrodes 16 and 17 through potential stabilization resistors 25 to 28. Connected.

JP 2000-101032 A

  FIG. 17 shows a general positive power supply driving SPDT (Single Pole Double Throw) switch circuit. The switch circuit has one common terminal 4 and two input / output terminals 2 and 3. When this is used as an antenna switch circuit for switching between transmission and reception circuits, terminal 2 is used as a transmission terminal, terminal 3 is used as a reception terminal, and terminal 4 is used as an antenna terminal. Switching elements 5 and 6 each including a field effect transistor are provided between the terminals 2 and 4 and between the terminals 3 and 4, respectively. Terminals 14 and 15 are control terminals of the switching elements 5 and 6. Capacitors 7, 8, 9 are for high frequency coupling, and resistors 10, 11 are isolation resistors for preventing transmission / reception signals from leaking to terminals 14, 15. The resistors 12 and 13 are bias resistors for causing the control signals input from the terminals 14 and 15 to be equally applied to the switches.

  A large power exceeding 1 W at the maximum is input to the transmission terminal 2 from the transmission circuit. For this reason, a structure in which two stages of dual gate transistors having two gates in each of the switching elements 5 and 6 are cascade-connected is employed.

  During transmission, 0V is applied to the terminal 15 and a positive voltage is applied to the terminal 14. At this time, since a forward voltage is applied between the terminal 14 and the point a, the switching element 5 is in a conductive state, and a reverse voltage is applied between the point a and the terminal 15, so that the switching element 6 is in a non-conductive state. . Thereby, the transmission signal input to the terminal 2 is output to the antenna terminal 4 via the switching element 5. In the switching element 5, the potential difference between the ohmic electrode to which the bias resistor 12 is connected and the gate electrode is stable, but the potential between the gate electrode and the gate electrode is unstable. If the potential at this point is unstable, power durability deteriorates and harmonic distortion tends to increase. At the time of reception, 0V is applied to the terminal 14 and a positive voltage is applied to the terminal 15, so that the switching element 5 is turned off and the switching element 6 is turned on. Thereby, the reception signal input from the antenna terminal 4 is output to the terminal 3 via the switching element 6. Since the received signal is a weak signal, harmonic distortion is not a problem.

As described above, Patent Document 1 discloses a switching element in which n ⁺ electrodes 22 to 24, which are regions between gates, are connected to ohmic electrodes 16 and 17 through potential stabilizing resistors 25 to 28. . However, this switching element has the following problems.

First, as can be seen from FIG. 16, the widths of the n ⁺ electrodes 22 to 24 are wider than the widths of the resistors 25 to 28. Since the resistance width is generally about 3 μm in the standard semiconductor process, the width of the n ⁺ electrodes 22, 23, 24 is 3 μm or more. This means that the on-resistance increases because the distance between the gates cannot be reduced, and the insertion loss increases. Further, since the potential stabilizing resistors 25 to 28 are formed between the gate electrode and the ohmic electrode or between the gate electrodes, the distance between the gate electrodes must be increased. This also increases the on-resistance and increases the insertion loss. In this specification, the width of the gate electrode refers to the size in the longitudinal direction in the vertical direction of the drawing, and the length of the gate electrode refers to the size in the horizontal direction of the drawing in accordance with common practice. However, for the ohmic electrode and the n ⁺ electrode, the width indicates the size in the horizontal direction of the drawing, and the length indicates the size in the longitudinal direction in the vertical direction of the drawing.

  Next, as a method of increasing the gate width in order to increase the allowable power of the switching element, Patent Document 1 discloses a structure in which three switching elements of FIG. 16 are connected in parallel. In this case, since a potential stabilizing resistor is provided for each switching element, the number thereof increases, and the parallel connection structure cannot be reduced in size. Further, as shown in FIG. 18, wirings 201a and 201b for connecting the electrodes 16a and 16b and the electrodes 17a and 17b of the same ohmic electrode to each other are formed. The gate electrode lead lines 200a to 200d and the lead lines 200e to 200h must be crossed. As a result, intersections 202a to 202h that provide interelectrode capacitance are formed. That is, the capacitance between each gate electrode and each ohmic electrode increases. This capacitance causes insertion loss and isolation degradation when the switching element is in the non-passing state.

  An object of the present invention is to provide a switching element capable of stabilizing the potential between the gates of multi-gates without increasing insertion loss, or to provide an antenna switch circuit using the same, or to use the same The object is to provide a high-frequency module.

  In order to achieve the above object, a switching element according to the present invention includes at least two ohmic electrodes formed on a semiconductor substrate and at least disposed between the two ohmic electrodes so as to form a field effect transistor. Two gate electrodes, and a conductive region disposed between adjacent gate electrodes of the at least two gate electrodes, the conductive region being adjacent to the one end at the one end. A wide portion wider than the conductive region sandwiched between the gate electrodes, and a distance between the adjacent gate electrodes is narrower than a width of the wide portion, and the two portions are interposed via the wide portions. A resistor is connected in series between the ohmic electrodes. The distance between the gate electrodes can be set without being affected by the size of the wide portion for connecting the resistor, that is, the size of the connecting portion. Therefore, it is possible to reduce the distance between the gate electrodes so as not to increase the insertion loss, and it is expected to provide a low-loss switching element capable of stabilizing the potential between the gates of the multigate.

  To achieve the above object, an antenna switch circuit of the present invention outputs a first terminal for inputting a transmission signal, a second terminal connected to the antenna, and a reception signal received by the antenna. A third terminal, a first switching element connected between the first terminal and the second terminal, and a second terminal connected between the second terminal and the third terminal. And the second switching element is turned on during transmission and the second switching element is turned off during transmission, and the first switching element is turned on during reception. The second switching element is in a non-conduction state and the second switching element is in a conduction state. Since a low-loss switching element that can stabilize the potential between the gates of multi-gates is used, it is expected to realize an antenna switch circuit that can intermittently transmit a high-power transmission signal and obtain high isolation between transmission and reception. The Therefore, it is expected to realize an antenna switch circuit suitable for use in switching the connection between a plurality of communication circuits and an antenna common to them.

  In order to achieve the above object, a high-frequency module of the present invention includes a first amplifier that amplifies a transmission signal, a second amplifier that amplifies a reception signal received by an antenna, and the first amplifier that outputs during transmission. And the antenna switch circuit for sending the transmission signal to the antenna and sending the reception signal received by the antenna to the second amplifier at the time of reception. Because a high power transmission signal can be interrupted and high isolation can be obtained between transmission and reception, and a suitable antenna switch circuit is used when switching the connection between a plurality of communication circuits and antennas common to them. For example, it is expected to realize a high-frequency module suitable for mounting on a wireless communication device such as a mobile phone that can handle a plurality of communication methods.

  According to the present invention, since the distance between the gate electrodes can be set small so as not to increase the insertion loss, a switching element capable of stabilizing the potential between the gates of the multi-gate without increasing the insertion loss is provided. It becomes feasible.

The top view for demonstrating 1st Embodiment by the switching element which concerns on this invention. The circuit diagram for demonstrating 1st Embodiment by the switching element of this invention. FIG. 6 is a first cross-sectional view for explaining a manufacturing process for the switching element according to the first embodiment. FIG. 6 is a second cross-sectional view for explaining a manufacturing process for the switching element according to the first embodiment. FIG. 6 is a third cross-sectional view for explaining a manufacturing process for the switching element according to the first embodiment. FIG. 6 is a fourth cross-sectional view for explaining a manufacturing process for the switching element according to the first embodiment. The top view for demonstrating 2nd Embodiment by the switching element of this invention. FIG. 7 is a bird's-eye view for explaining a second embodiment of the switching element of the present invention. The top view for demonstrating 3rd Embodiment by the switching element of this invention. The circuit diagram for demonstrating 3rd Embodiment by the switching element of this invention. FIG. 5 is a curve diagram for explaining a change in insertion loss when the width between n ⁺ layers is changed to change the distance between gates. The curve figure which shows the actual measurement result of the 2nd harmonic distortion when electric power is supplied to an n ⁺ layer. The curve figure which shows the actual measurement result of the 3rd harmonic distortion when supplying electric power to a n ⁺ layer. The curve figure which shows the actual measurement result of the 2nd harmonic distortion when not supplying electric power to the n ⁺ layer. The curve figure which shows the actual measurement result of the 3rd harmonic distortion when not supplying electric power to the n ⁺ layer. The measurement circuit diagram using the switching element with electric power feeding to an n ⁺ layer. FIG. 5 is a measurement circuit diagram using a switching element without power feeding in an n ⁺ layer. The curve figure for demonstrating the voltage dependence of ohmic electrode-gate electrode interrogative capacity. The curve figure for demonstrating the voltage dependence of gate electrode-n + layer capacity | capacitance. The circuit block diagram for demonstrating 4th Embodiment by the antenna switch circuit and high frequency module of this invention. The top view for demonstrating the conventional switching element. The circuit diagram for demonstrating a general SPDT switch. The top view for demonstrating the problem of the capacity | capacitance increase in the conventional switching element. Another top view for demonstrating 2nd Embodiment by the switching element of this invention.

  Hereinafter, a switching element according to the present invention, an antenna switch circuit using the same, and a high-frequency module will be described in more detail with reference to some embodiments shown in the drawings.

  1A and 1B show a first embodiment of the present invention. The present embodiment is a dual gate type switching element formed by a high electron mobility transistor (hereinafter referred to as “HEMT: High Electron Mobility Transistor”) which is a field effect transistor. The switching element is used as a main element in an antenna switch circuit provided in a high-frequency module mounted on a mobile communication device such as a mobile phone.

  In the layout shown in FIG. 1A, gate electrodes 41 and 42 having a length of 0.5 μm and a gate electrode distance of 1.5 μm are formed between two ohmic electrodes 39 and 40 having a width of 5 μm. The distances between the ohmic electrode 39 and the gate electrode 41 and between the ohmic electrode 40 and the gate electrode 42 are 1.0 μm, respectively. One end of each of the gate electrodes 41 and 42 is as thick as about 3 to 5 μm in order to connect a wiring or a resistance for bias supply. The other end extends in a different direction outside the ohmic electrode. The element isolation region 43 is formed to include up to this portion.

Between the gate electrodes 41 and 42 in the region sandwiched between the ohmic electrodes 39 and 40, there is an n ⁺ electrode 45 of an n ⁺ layer having a width of 0.5 μm, and the element isolation region 43 outside the ohmic electrodes 39 and 40 and A portion of the n ⁺ electrode 45 surrounded by the gate electrodes 41 and 42 is formed wide. One end of the potential stabilization resistors 44 and 46 is connected to the wide portion, the other end of the potential stabilization resistor 44 is connected to the ohmic electrode 39, and the other end of the potential stabilization resistor 46 is connected to the ohmic electrode 40. . Incidentally, the power supply to ^{n +} electrode 45 is performed by the voltage stabilizing resistors 44 and 46 are connected to the ^{n +} electrode 45, the wide portion of the ^{n +} electrode 45 is a feeding point.

With such a layout, the n ⁺ electrode and the ohmic electrode can be resistance-connected while minimizing the distance between the gates without being affected by the arrangement of the potential stabilization resistors 44 and 46.

Thin film resistance layers are used for the potential stabilization resistors 44 and 46. Although not shown, the thin film resistance layer is connected to the wide portion of the n ⁺ electrode 45 using another wiring layer. Note that the potential stabilization resistors 44 and 46 are not limited thereto, and the same semiconductor layer as the n ⁺ electrode 45 or a part of the semiconductor layer can be used. In that case, the semiconductor layers to be the potential stabilization resistors 44 and 46 are continuously connected from the wide portion of the n ⁺ electrode 45. FIG. 1B shows a circuit diagram of the switching element of this embodiment in which the n ⁺ electrode 45 is connected to the potential stabilization resistors 44 and 46 as described above.

The manufacturing process of the switching element of this embodiment will be described below. First, as shown in FIG. 2, a buffer layer is formed on a semiconductor substrate (hereinafter simply referred to as “substrate”) 29 made of GaAs, which is a compound semiconductor, by, for example, metal organic chemical vapor deposition (MOCVD). 30, the electron supply layer 31, the channel layer 32, the electron supply layer 33, the Schottky layer (electron supply layer) 34, the interlayer film 35, and the n ⁺ layer (n-type cap layer) 36 are epitaxially grown in this order.

  The buffer layer 30 includes a non-doped GaAs layer having a thickness of about 1000 mm, a non-doped AlGaAs (aluminum gallium arsenide) layer having a thickness of about 100 mm, an undoped GaAs layer having a thickness of about 500 mm, and an undoped AlGaAs layer having a thickness of about 3000 mm. It is formed by laminating sequentially from the lower layer.

The electron supply layer 31 is formed of an n ⁺ -type AlGaAs layer having a thickness of about 100 mm, and impurity ions (for example, silicon ions) having an n-type conductivity type (first conductivity type) are 5 × 10 ¹⁷ cm ^−3. It is introduced at a concentration of about.

  The channel layer 32 includes a non-doped AlGaAs layer having a thickness of about 30 mm, a non-doped GaAs layer having a thickness of about 40 mm, a non-doped InGaAs layer having a thickness of about 80 mm, a non-doped GaAs layer having a thickness of about 40 mm, and a thickness of about 30 mm. It is formed by sequentially laminating non-doped AlGaAs layers from the lower layer.

The electron supply layer 33 is formed of an n ⁺ -type AlGaAs layer having a thickness of about 100 mm, and impurity ions (for example, silicon ions) having n-type conductivity are introduced at a concentration of about 3 × 10 ¹⁸ cm ^−3. ing.

The Schottky layer 34 is formed of an n ⁺ -type AlGaAs layer having a thickness of about 590 mm, and impurity ions (for example, silicon ions) having an n-type conductivity are introduced at a concentration of about 2 × 10 ¹⁶ cm ^−3. ing.

The interlayer film 35 is formed of an n ⁺ -type AlGaAs layer having a thickness of about 30 mm, and impurity ions (for example, silicon ions) having n-type conductivity are introduced at a concentration of about 5 × 10 ¹⁸ cm ^−3. Yes.

The n ⁺ layer 36 is formed of an n ⁺ type GaAs layer having a thickness of about 1400 mm, and impurity ions (for example, silicon ions) having an n type conductivity are introduced at a concentration of about 5 × 10 ¹⁸ cm ^−3. ing.

The above epitaxial crystal structure is a strained channel HEMT (hereinafter referred to as “pHEMT: pseudomorphic HEMT”) structure. After performing the above epitaxial growth, element isolation is performed by a mesa etching method, and an ohmic electrode 37 is formed in ohmic contact with the n ⁺ layer 36 at a predetermined position as shown in FIG. The ohmic electrode 37 is a source electrode and a drain electrode of the field effect transistor.

Next, the n ⁺ layer 36 and the interlayer film 35 where the gate electrode is to be formed are removed (FIG. 4). Subsequently, a gate electrode 38 is formed (FIG. 5). The gate electrode 38 has a gate length of 1.0 μm or less, preferably about 0.5 μm. The gate electrode 38 is formed of a metal layer having Pt (platinum) as the lowermost layer. For example, a metal layer in which Pt, Ti (titanium), Pt, and Au (gold) are sequentially stacked from the lower layer is used. The thickness of the lowermost Pt is about 150 mm. This Pt layer reacts with the Schottky layer 34 in the subsequent thermal process, and is buried by about 380 mm to become a buried gate. Note that a gate electrode that is not embedded may be used. In that case, a metal layer in which Ti, Pt, and Au are sequentially stacked from the lower layer is used. In this case, the thickness of the Schottky layer 34 is as thin as about 200 mm.

FIG. 5 shows a cross-sectional structure of a dual gate type device having two gate electrodes 38 between ohmic electrodes 37. Between the two gate electrodes 38, an n ⁺ layer (n-type cap layer) 36 serving as an n ⁺ electrode is disposed. The distance between the n ⁺ layer 36 and the adjacent gate electrode 38 is about 0.5 μm, and the width of the n ⁺ layer 36 is about 0.5 μm. The distance between the gate electrode and the n ⁺ layer and the width of the n ⁺ layer can be arbitrarily designed. However, the distance between the gate electrode and the n ⁺ layer is as close as possible within the range in which the withstand voltage can be maintained during the switch operation. From the viewpoint of the insertion loss, about 0.5 μm is a standard dimension. Further, it is advantageous to make the width of the n ⁺ layer narrower from the viewpoint of reducing insertion loss, and about 0.5 μm is standard from the viewpoint of processing accuracy. It powering the n ⁺ layer extending in the gate width direction is the gist of the present invention, since the n ⁺ layer殆N etc. no current flows, the resistance of the n ⁺ layer need not be lowered as the left. Therefore, when a normal n ⁺ layer having a sheet resistance of about 50Ω / □ is used, a width of about 0.5 μm is sufficient. The same applies to a multi-gate element having three or more gate electrodes between ohmic electrodes. Note that the layer between the gate electrodes is not limited to the n ⁺ layer and can be a wide conductive region. As described above, the material of the conductive region is set on the assumption that almost no current flows in the conductive region.

  The main manufacturing process of the field effect transistor has been described above. Thereafter, a resistance element and a capacitive element are integrated and formed on the substrate 29, a necessary wiring is provided, and finally a passivation film is formed, thereby completing the process of the main surface (element formation surface) of the chip. Finally, the substrate thickness is appropriately reduced to about 100 μm and cut out from the substrate to complete the chip.

  The field effect transistor manufactured by the above manufacturing process is a pHEMT, but the present invention is not limited to this, and can be, for example, a strain relaxation HEMT (hereinafter referred to as “mHEMT: metamorphic HEMT”). A manufacturing process of the switching element when the field effect transistor is mHEMT will be described below.

  In FIG. 2, a layer in which the InAs mixed crystal ratio of the InAlAs layer is continuously or stepwise increased from 0 to a desired value is inserted as the buffer layer 30, and dislocations caused by the crystal lattice constant difference are generated in the buffer layer 30. Be trapped. The extent to which the InAs mixed crystal ratio is increased depends on the composition of the InGaAs channel to be used. Here, the InAs mixed crystal ratio of the InGaAs channel is about 0.4, and the InAs mixed crystal ratio of the buffer layer 30 is also increased to about 0.4. Is done. The electron supply layer 31 is not inserted in this manufacturing process.

  The channel layer 32 is formed by sequentially laminating a non-doped InGaAs layer (InAs mixed crystal ratio of about 0.4) having a thickness of 200 mm and a non-doped InAlAs layer (InAs mixed crystal ratio of about 0.4) having a thickness of 20 mm as a spacer layer. Has been.

The electron supply layer 33 is formed of an n ⁺ -type InAlAs layer (InAs mixed crystal ratio of about 0.4) having a film thickness of about 100 mm, and impurity ions (for example, silicon ions) having an n-type conductivity type are 3 × 10. It is introduced at a concentration of about ¹⁸ cm ⁻³ .

The Schottky layer 34 is formed of an n ⁺ -type InAlAs layer (InAs mixed crystal ratio of about 0.4) having a thickness of about 330 mm, and impurity ions (for example, silicon ions) having an n-type conductivity type are 2 × 10. It is introduced at a concentration of about ¹⁶ cm ⁻³ .

The interlayer film 35 is formed of an n ⁺ -type InP layer having a thickness of about 50 mm, and impurity ions (for example, silicon ions) having n-type conductivity are introduced at a concentration of about 5 × 10 ¹⁸ cm ^−3. Yes.

The n ⁺ layer (n-type cap layer) 36 is formed from an n ⁺ -type InGaAs layer (InAs mixed crystal ratio of about 0.4) having a film thickness of about 1400 mm, and has impurity ions (for example, silicon) having an n-type conductivity type. Ions) are introduced at a concentration of about 5 × 10 ¹⁸ cm ⁻³ .

Next, as in the case of pHEMT, after the ohmic electrode 37 is formed (FIG. 3), the n ⁺ layer 36 and the interlayer film 35 where the gate electrode is formed are removed (FIG. 4). Subsequently, a gate electrode 38 is formed (FIG. 5). For the gate electrode 38, a metal layer (a metal layer in which Pt, Ti, Pt, and Au are sequentially stacked) having Pt as the lowermost layer is used. The thickness of the lowermost Pt is about 50 mm. This Pt layer reacts and is embedded with the Schottky layer 34 in the subsequent thermal process. In mHEMT, a leakage current is suppressed by sufficiently increasing the height of the Schottky barrier of the gate electrode formed on InAlAs, and therefore, a Pt gate that has a large work function and a high Schottky barrier is often used. This Pt gate is also used in this manufacturing process. That is, in the switch circuit using mHEMT, a Pt gate is preferable from the viewpoint of reducing the leakage current of the gate electrode. In addition, the Pt gate having a large work function and a high Schottky barrier is effective for the present invention because the problem of the voltage dependency of the off capacitance, which tends to be a problem with the buried gate using Pt, is avoided.

The distance between the gate electrode 38 and the n ⁺ layer 36 and the width of the n ⁺ layer 36 are set to about 0.5 μm as in the case of the previous manufacturing process.

  The mHEMT formed by this manufacturing process has an electron mobility of 20% or more higher than that of pHEMT. For this reason, the on-resistance Ron of the device is reduced, and the insertion loss in the switch circuit can be reduced. By using a Pt gate, the problem of voltage dependency of off-capacitance that tends to be a problem can be avoided, and harmonic distortion can be suppressed low.

  As described above, in the present embodiment, the case of the switching element by pHEMT and mHEMT using GaAs has been described, but the present invention can be similarly applied to other field-effect transistor switching elements. For example, the present invention is applicable to a field effect transistor switching element using a GaN or InGaN layer as a channel layer.

  FIG. 6 shows a second embodiment of the present invention. The present embodiment is a switching element having a larger gate width than the first embodiment. The manufacturing process is the same as that in the first embodiment.

In FIG. 6, ohmic electrodes 39 and 40 having a width of 5 μm are arranged so as to mesh with each other, and the gate electrodes 41 and 42 having a gate length of 0.5 μm have a gate-to-gate distance of 1.5 μm. And is formed in a meander shape with an n ⁺ layer 45 serving as an n ⁺ electrode interposed therebetween. At this time, the distance between the ohmic electrode 39 and the gate electrode 41 and between the ohmic electrode 40 and the gate electrode 42 is 1 μm, respectively, and the distance between the n ⁺ layer 45 and the gate electrodes 41 and 42 is 0.5 μm, respectively.

  One end of each of the gate electrodes 41 and 42 is as thick as 3 to 5 μm for connection with a wiring or a bias supply resistor. The other end extends to the outside of the ohmic electrode, and the gate electrodes 41 and 42 outside the ohmic electrode extend in a different direction from the gate electrodes 41 and 42 inside the ohmic electrode. The element isolation region 43 is formed to include up to this portion.

Thereby, the width of the n ⁺ electrode 45 can be made thicker than 0.5 μm outside the ohmic electrode. Therefore, the area of the n ⁺ layer 45 surrounded by the gate electrodes 41 and 42 extending in different directions and the element isolation region 43 is large enough to secure an area sufficient to connect the resistors. It will be. The width of the n ⁺ electrode 45 in this portion is usually about 3 μm. The ohmic electrode 39 and the n ⁺ layer 45 are connected by the potential stabilization resistor 44, and the ohmic electrode 40 and the n ⁺ layer 45 are connected by the potential stabilization resistor 46.

In the above structure, the gate electrodes 41 and 42 are sandwiched in three times with the ohmic electrodes 39 and 40, whereby three of the switching elements shown in FIG. 1A are connected in series, and the total gate width Increases threefold. Even if the number of comb teeth of the ohmic electrodes 39 and 40 is increased to further increase the gate width, it is sufficient that there is at least one connection point between the n ⁺ electrode 45 and the potential stabilization resistors 44 and 46. In the conventional example shown in FIG. 18, the number of potential stabilizing resistors increases in proportion to the number of parallel connections, but in the present embodiment, there is no such increase in the number. Therefore, by the above method, it is possible to suppress the increase in the minimum area with respect to the increase in the gate width while suppressing the distance between the gates to the minimum.

  Further, the above structure does not have a crossing portion where the lead-out line of the gate electrode and the interconnection line of the ohmic electrode cross like the conventional structure shown in FIG. Therefore, there is no increase in capacitance between the gate electrode and the ohmic electrode, and an increase in insertion loss and isolation deterioration when the switching element is in the non-passing state due to the increase in capacitance are avoided.

Here, FIG. 7 shows a bird's-eye view of a cross section taken along line AA in FIG. The numbers in the figure correspond to those in FIG. The illustration of the potential stabilizing resistance elements 44 and 46 is omitted. Since the upper surface of the semiconductor is cut outside the element isolation region 43, a slope is formed in the vicinity of the region. By forming the gate electrodes 41 and 42 so as to extend beyond the slope, the region between the gate electrode and the ohmic electrode and the region between the gate electrode and the n ⁺ electrode are separated.

8A and 8B show a third embodiment of the present invention. The present embodiment is a triple gate type element having three gate electrodes. The manufacturing process is basically the same as in the first embodiment, although the gate electrode and n ⁺ layer to be formed are different.

In the example of the layout shown in FIG. 8A, gate electrodes 41, 42, 47 are arranged between ohmic electrodes 39, 40, and n ⁺ layers 45, 48 are arranged between the gate electrodes. In this example, unlike the second embodiment of FIG. 6, the entire ohmic electrode is covered with the blocking isolation region 43. As a result, the meander portion also operates as a field effect transistor, so that the on-resistance can be reduced with the same element area. The gate electrodes 41 and 42 extend in different directions outside the ohmic electrode, and the gate electrode 47 is extended as it is, thereby widening the space between the gate electrodes. Therefore, wide n ⁺ layers 45 and 48 are formed in a region surrounded by the gate electrodes 41, 42 and 47 and the element isolation region 43. By connecting the wide n ⁺ layer 45 and the ohmic electrode 39, the n ⁺ layer 45 and the n ⁺ layer 48, and the n ⁺ layer 48 and the ohmic electrode 40 with a potential stabilizing resistor (not shown), respectively, the ohmic electrode and the gate are connected. The potentials of the electrode, gate electrode, and n ⁺ layer are the same, and the potential of the gate electrode is stabilized. FIG. 8B shows a circuit diagram of the switching element of the present embodiment.

Here, FIG. 9 shows the calculation result of the change in insertion loss when the switching element of the present invention is turned on and the distance between the gates is changed. The switch element used for the calculation has two stages of dual gates. The gate width is fixed at 1 mm, the distance between the ohmic electrode and the gate electrode is 1 μm, and the distance between the gate electrode and the n ⁺ electrode is fixed at 0.5 μm. Only the distance between the gate electrodes changes by changing the n ⁺ electrode width.

In the first, second, and third embodiments, the distance between the gates is 1.5 μm and the n ⁺ electrode width is 0.5 μm. The corresponding insertion loss is about 0.28 dB. When the n ⁺ electrode width is increased to 3 μm, the loss increases to 0.4 dB, and when the n ⁺ electrode width is further increased to 5 μm, the loss increases to 0.5 dB. As a result, it was demonstrated that the on-resistance of the transistor is minimized and the insertion loss is minimized by minimizing the distance between the gate electrodes.

  As described above, according to the present invention, the power durability can be improved without increasing the insertion loss and the element area, and the reduction of harmonic distortion, which is another important effect, will be described below.

10A to 10D, the switching element for supplying power to the n ⁺ electrode of the present invention shown in FIG. 1A and the switching circuit shown in FIG. 1A do not supply power to the n ⁺ electrode, and therefore the potential between the gates is not stable. The measurement results of the dependence of the second harmonic distortion (2HD) and the third harmonic distortion (3HD) on the input power (Pin) when each switching element is connected in parallel to the transmission line in a non-passing state are shown. . The frequency was 1910 MHz. 10A and 10B are second harmonic distortion and third harmonic distortion of the switching element of the present invention, respectively. FIGS. 10C and 10D are second harmonic distortion and third harmonic distortion of a general switching element, respectively. FIG. 11 shows a measurement circuit diagram of harmonic distortion using the switching element of the present invention. The switching element 54 has a dual gate two-stage configuration for supplying power to the n ⁺ electrode. The switching element 54 of the dual gate two-stage configuration of the present invention is connected between the transmission line between the input terminal 49 and the output terminal 50 and the ground. The terminals 51 and 56 are bias supply terminals. The capacitor 53 is used for high frequency coupling, and the resistors 52 and 57 are used for high frequency leakage prevention and DC component coupling. The resistor 55 connected between the ohmic electrodes via the n ⁺ electrode between the gate electrodes is a resistor for evenly biasing each stage.

FIG. 12 shows a measurement circuit diagram of harmonic distortion using a general switching element. The switching element 54 has a dual gate two-stage configuration that does not supply power to the n ⁺ electrode. Unlike the switching element of FIG. 11, the resistor 55 is connected between the ohmic electrodes without passing through the n ⁺ electrode.

  As shown in FIGS. 10A to 10D, the switch of the present invention has low harmonic distortion because of low input power, and low harmonic distortion even at 35 dBm input. In the present invention and the general switching element, the harmonic distortion is improved as the bias is deepened to V1, V2, and V3. However, in the switching element of the present invention, the change of the harmonic distortion with respect to the bias is large. It is confirmed that the degree of improvement is large. The improvement of the harmonic distortion in the non-concurrent state in the switching element will be described with reference to FIGS. 13 and 14.

FIG. 13 shows the dependence of the capacitance between the ohmic electrode and the gate electrode on the voltage between the ohmic electrode and the gate electrode, and FIG. 14 shows the capacitance between the gate electrode and the n ⁺ electrode arranged between the same electrodes. The gate electrode-n ⁺ interelectrode voltage dependency is shown. In both figures, the capacitance decreases with decreasing voltage at a voltage lower than the voltage at which the transistor is turned off. In addition, the change in capacitance increases as the voltage approaches the off voltage. Such voltage dependence exhibited by the off-state capacitance causes harmonic distortion generated from the off-state transistor. In particular, in the case of the Pt buried type gate electrode employed in the present embodiment of the first, second, and third embodiments, the bottom surface of the gate electrode is not completely flat, and thus the voltage dependency of the off capacitance tends to increase. is there. That is, the harmonic distortion of the off-state transistor tends to increase. However, the Pt buried type is advantageous in reducing insertion loss and harmonic distortion in an on-state transistor because the resistance of the parasitic part on the side of the gate is reduced.

In the case of the circuit of FIG. 12, that is, when there is a portion where the potential is unstable without supplying power to the n ⁺ electrode, when the switch-off voltage of Vc is applied to the terminal 51, the gap between the ohmic electrode and the gate electrode is Biased to 13 points b. However, the voltage between the n ⁺ electrode and the gate is biased to a point c in FIG. 14, and becomes a voltage close to the voltage at which the channel is turned off. For this reason, the voltage dependence of the off-capacitance is large, and large harmonic distortion occurs when high-frequency power passes.

In the switching element of the present invention shown in FIG. 11, since power is supplied to the n ⁺ electrode, the gap between the ohmic electrode and the gate electrode is biased to the point b in FIG. 13, and the gap between the gate electrode and the n ⁺ electrode is FIG. Biased to point d. For this reason, since the bias is biased in a region where the voltage dependence of the off capacitance is small, the generation of harmonic distortion can be suppressed. That is, in the element having the Pt buried type gate electrode in which the voltage dependence of the off capacitance is large as in the present embodiment, the low insertion loss and the low distortion in the on state which are the merits of Pt embedding are suppressed while suppressing the generation of harmonics. You can enjoy it. Further, as shown in FIGS. 13 and 14, when the bias is deepened, the bias dependency of the off capacitance is reduced, and the off operation region is widened, so that the harmonic distortion is improved and the power durability is improved.

In this embodiment, the case of a transistor having a Pt buried type gate has been described, but even when a gate without embedding is used, the application of the present invention in which power is supplied to the n ⁺ electrode suppresses an increase in insertion loss and chip area. The same is true in that harmonic distortion can be suppressed. In addition to the suppression of harmonics, the OFF state is less likely to collapse when high power is input, and there is an effect of improving power durability.

Next, a description will be given magnitude relationship between the potential stabilizing resistor connecting the n ⁺ electrode and the ohmic electrode and the resistance of the n ⁺ electrodes. For example, when the total gate width is 2mm, when the sheet resistance of the ^{n +} layer and ^{n +} electrode and 50 [Omega / □, width 0.5 [mu] m, the resistance of the ^{n +} layer of length 2mm is a 200 k [Omega], the feeding point When only one point is formed at one end of the n ⁺ layer, the effective resistance to the field effect transistor is considered to be ½ thereof, and becomes 100 kΩ.

By the way, Patent Document 1 discloses a method of connecting a potential stabilizing resistance larger than the resistance value of the n ⁺ layer between the n ⁺ layer and the ohmic electrode. However, when the n ⁺ layer becomes 100 kΩ, the potential is The stabilization resistor will exceed this value. Resistors exceeding 100 kΩ have an excessively large pattern area and hinder downsizing of the device. On the other hand, the value of the potential stabilization resistor may be such that a sufficiently high resistance can be secured during high-frequency operation of the switching element, and is usually about 10 kΩ. In this case, the effective resistance of the n ⁺ layer is made smaller than 10 kΩ. However, this time, the width of the n ⁺ layer has to be set to 5 μm or more, which increases the insertion loss as a switch. It is also disadvantageous from the viewpoint of increasing the occupied area of the transistor.

Here, the resistance of the n ⁺ layer may decide the upper limit as a resistance which is a value that the voltage drop negligible due to the current flowing through the n ⁺ layer. The current flowing through the n ⁺ layer in the off-state transistor is a gate leakage current. Usually, the doping amount in the semiconductor is designed so that the reverse gate leakage current is about 1 μA / mm or less. Now, let the gate leakage current per unit gate width be Ig, the gate width be Wg, and the resistance of the n ⁺ layer per unit length in the gate width direction be R. Since the length of the n ⁺ layer is almost equal to the gate width, it is assumed here that the length is equal to the gate width. When power is supplied to one end of the n ⁺ layer, the voltage drop Vdrop due to Ig between the gate widths is given by the following equation.

Vdrop = (1/2) · R · Ig · Wg ²
= (R · Wg / 2) · (Ig · Wg)
= Reff / Igtotal
Reff = R · WG / 2 is the effective resistance described above.

Here, when the sheet resistance of the n ⁺ layer is set to 50Ω / □ and the width is set to 0.5 μm, the resistance R per unit length in the gate width direction is 10 kΩ / mm, and when Ig = 1 μA / mm, the gate width At = 2 mm, Vdrop is 0.2V. When Wg = 1 mm, this ¼ is 0.05V. Since the off state of the field effect transistor switch is normally set to a voltage 1V to 2V deeper than Vth, if Vdrop is about 0.05 to 0.2V, the voltage is 1V to 2V deeper than Vth. It is well tolerated. That is, it is shown that the resistance of 10 to 20 kΩ when the length of the n ⁺ layer is 1 to 2 mm may be larger than the usual 10 kΩ of the potential stabilization resistor, and the resistance of the n ⁺ layer is large. However, it is shown that it is preferable to suppress the width to about 0.5 μm. When the voltage drop Vdrop cannot be ignored because the gate width is further increased, the connection of the potential stabilizing resistor between the n ⁺ layer and the ohmic electrode of the present invention is as in the second embodiment shown in FIG. Vdrop can be suppressed to the minimum by providing not only on one of the gate electrodes but also on both of the gate electrodes as shown in FIG.

In the above embodiments, a structure (recess gate structure) in which a pHEMT transistor or an mHEMT transistor is used and n ⁺ layers (cap layers) are arranged on both sides of the gate electrode has been described. However, the present invention is not limited to the case where the cap layer is disposed. When the cap layer is not disposed, power supply between the gate electrodes may be performed with respect to the channel layer provided in the portion between the gate electrodes. The gate-to-gate distance may be designed according to the above-mentioned concept using the sheet resistance of the channel layer in this portion instead of the sheet resistance of the n ⁺ layer.

  FIG. 15 shows a fourth embodiment of the present invention. The present embodiment is an antenna switch circuit using the switching element of the present invention, and a high-frequency module used in a quad-band compatible mobile phone equipped with the antenna switch circuit. In FIG. 15, 76 is an antenna switch circuit, and 58 is a high-frequency module. The quad band refers to a band based on four mobile phone standards (communication systems) such as GSM (Global System for Mobile communications) in Europe, GSM in the United States, PCS (Personal Communication Services), and DCS (Digital Communication System). For convenience, GSM in Europe is GSM1, and GSM in the United States is GSM2. In order to cope with this, the high-frequency module 58 has one common GSM transmission (GSM1 / 2), two reception (GSM1 and GSM2), one common PCS and DCS transmission, one PCS reception, and DCS. Each terminal of reception 1 system is provided. GSM is in the 900 MHz band, and PCS and DCS are in the 1800 MHz band.

  The antenna switch circuit 76 switches between the seven systems and one antenna 75. In the antenna switch circuit 76 shown in FIG. 15, 79 to 86 are switching elements, 96 to 103 are control terminals to which control signals for controlling conduction and non-conduction of the switching elements 79 to 86 are input, and 87 is high frequency coupling. Capacity. Furthermore, 88 is a PCS / DCS transmission terminal (first terminal), 89 is a GSM transmission terminal (first terminal), 90 is an antenna terminal (second terminal), 91 is a ground terminal, and 92 is a GSM1 reception terminal. (Third terminal), 93 is a GSM2 receiving terminal (third terminal), 94 is a PCS receiving terminal (third terminal), and 95 is a DCS receiving terminal (third terminal). The ground terminal 91 is connected to the ground plane of the module 58. The switching elements of the first or second embodiment are used for the switching elements 79 and 80, and the switching element of the third embodiment is used for the switching element 81.

  In the high-frequency module 58 shown in FIG. 15, 104 is a GSM transmission signal input terminal, 105 is a PCS / DCS transmission signal input terminal, 106 is an antenna connection terminal, 107 is a GSM1 reception signal output terminal, and 108 is a GSM2 reception signal. An output terminal 109 is an output terminal for a PCS reception signal, and 110 is an output terminal for a DCS reception signal. Reference numeral 78 denotes a control circuit that generates a control signal to the control terminals 96 to 103. Further, 59 and 61 are power amplifiers (first amplifiers), 60 and 62 are low-pass filters, 77a to 77f are capacitors for high frequency coupling, 65, 68, 71 and 74 are frequency converters, 64, 67, 70, 73 is a low noise amplifier (second amplifier), and 63, 66, 69, 72 are SAW (Surface Acoustic Wave) filters. The transmission-side filters 60 and 62 may be provided inside the power amplifiers 59 and 60 as part of the matching circuit of the power amplifiers 59 and 60.

  At the time of transmission, the GSM transmission signal output from the external GSM transmission circuit is input to the input terminal 104, amplified by the power amplifier 59, the harmonic component is removed by the low-pass filter 60, and is transmitted to the transmission terminal 89 of the switching element 76. Entered. At this time, the control circuit 78 applies a positive voltage to the control terminals 97 and 99, and a zero voltage to the control terminals 96, 98, and 100 to 103, so that the switching elements 80 and 82 are in a conductive state. 81 and 83-86 will be in a non-conduction state. As a result, the amplified GSM transmission signal is transmitted from the antenna 75 connected to the antenna connection terminal 106 via the switching element 80 and the antenna terminal 90.

At this time, in the switching elements 80 and 82, the n ⁺ layer and the ohmic electrode are resistance-connected by the application of the present invention, and the gap between the gate electrodes is set narrow, so that the resistance when conducting is made resistance. Therefore, a low insertion loss is realized. The low insertion loss of the switching element 82 improves the isolation between the antenna terminal 90 of the antenna switch circuit 76 and the receiving terminals 92 to 95.

  Next, the signal output from the external PCS / DCS transmission circuit is input to the input terminal 105, amplified by the power amplifier 61, the harmonic component is removed by the low-pass filter 62, and input to the transmission terminal 88. At this time, the control circuit 78 brings the switching elements 79 and 82 into the conducting state and the switching elements 80, 81, and 83 to 86 into the non-conducting state, and the antenna connected to the antenna terminal 106 via the switching element 79 and the antenna terminal 90. 75.

At this time, in the switching elements 79 and 82, the n ⁺ layer and the ohmic electrode are resistance-connected by applying the present invention, and the gap between the gate electrodes is set narrow, so that the resistance when conducting is made resistance. Therefore, a low insertion loss is realized. As described above, the low insertion loss of the switching element 82 improves the isolation between the antenna terminal 90 and the reception terminals 92 to 95 of the antenna switch circuit 76.

  In particular, of the PCS transmission frequency and the DCS reception frequency, the frequency bands from 1850 MHz to 1875 MHz overlap with each other, so that when a high-power PCS transmission signal leaks to the DCS reception terminal 95, it is isolated from the transmission side. If it is not sufficiently high, the SAW filter 72 may be destroyed. However, since high isolation is realized in the present invention, the SAW filter is not destroyed.

  As an operation at the time of reception, DCS reception will be typically described. A DCS reception signal received by the antenna 75 is input to the antenna terminal 90 via the antenna terminal 106. At this time, the switching elements 79, 80, 82 to 85 are turned off and the switches 81, 86 are turned on by the control circuit 78. As a result, the received signal is spurious out of the band by the SAW 72 and noise is reduced, and then the signal is amplified by the low noise amplification circuit 73, converted to an IF signal or a demodulated signal by the frequency converter 74, and output terminal 110 Is output.

  As described above, according to the present embodiment, it is possible to realize an antenna switch circuit and a high-frequency module that have low insertion loss in transmission / reception operations and can provide high isolation between transmission and reception.

  In this embodiment, increasing the positive voltage applied to the switching element at the time of transmission increases the bias of the non-conducting switching element, thereby improving the power durability and reducing the bias dependency of the capacitance. Therefore, harmonic distortion is also improved. Therefore, the present invention is applied to a communication method adopting digital modulation that requires high linearity such as WCDMA (Wideband Code Division Multiplex Access), EDGE (Enhanced Data rates for GSM Evolution), and wireless LAN (Local Area Network). But it is possible.

  Further, when the mobile phone is compatible with a single band, the switching elements 82 to 86 are omitted in the antenna switch circuit 76, and the transmission / reception circuit in the high frequency module 58 is of course one system.

39, 40 ... Ohmic electrode, 41, 42, 47 ... Gate electrode, 43 ... Element isolation region, 44, 46 ... Resistance for potential stabilization, 45, 48 ... n ⁺ electrode (n ⁺ layer), 58 ... High frequency module, 59 , 61 ... power amplifier, 64, 67, 70, 73 ... low noise amplifier, 60, 62 ... low pass filter, 63, 66, 69, 72 ... SAW filter, 65, 68, 71, 74 ... frequency converter, 76 ... Antenna switch circuit, 78... Control circuit, 79 to 86.

Claims (19)

Like a field effect transistor,
Two ohmic electrodes formed on a semiconductor substrate;
At least two gate electrodes disposed between the two ohmic electrodes;
A conductive region sandwiched between adjacent gate electrodes of the at least two gate electrodes,
The conductive region has, at one end, a wide portion wider than the conductive region sandwiched between the adjacent gate electrodes,
The distance between the adjacent gate electrodes is narrower than the width of the wide portion,
A switching element, wherein a resistor is connected in series between the two ohmic electrodes through the wide portion. In claim 1,
One end of the gate electrode adjacent to the two ohmic electrodes of the at least two gate electrodes extends in a direction away from the sandwiched conductive region. In claim 1,
The switching element, wherein the conductive region includes an n-type cap layer. In claim 1,
A switching element, wherein the field effect transistor is a high electron mobility transistor. In claim 4,
A switching element, wherein the high electron mobility transistor is a strained channel high electron mobility transistor. In claim 4,
The switching element, wherein the high electron mobility transistor is a strain relaxation high electron mobility transistor. In claim 1,
A switching element characterized in that individual resistance values of the resistors connected in series between the two ohmic electrodes through the wide portion are smaller than an effective resistance value of the conductive region. A first terminal for inputting a transmission signal;
A second terminal connected to the antenna;
A third terminal for outputting a received signal received by the antenna;
A first switching element connected between the first terminal and the second terminal;
Comprising a second switching element connected between the second terminal and the third terminal,
During transmission, the first switching element is turned on and the second switching element is turned off. During reception, the first switching element is turned off and the second switching element is turned on. State
Each of the first and second switching elements is
Like a field effect transistor,
Two ohmic electrodes formed on a semiconductor substrate;
At least two gate electrodes disposed between the two ohmic electrodes;
A conductive region sandwiched between adjacent gate electrodes of the at least two gate electrodes,
The conductive region has, at one end, a wide portion wider than the conductive region sandwiched between the adjacent gate electrodes,
The distance between the adjacent gate electrodes is narrower than the width of the wide portion,
An antenna switch circuit, wherein a resistor is connected in series between the two ohmic electrodes through the wide portion. In claim 8,
One end of the gate electrode adjacent to the two ohmic electrodes among the at least two gate electrodes extends in a direction away from the sandwiched conductive region. In claim 8,
The antenna switch circuit, wherein the conductive region includes an n-type cap layer. In claim 8,
An antenna switch circuit, wherein the field effect transistor is a high electron mobility transistor. In claim 8,
An antenna switch circuit characterized in that individual resistance values of the resistors connected in series between the two ohmic electrodes through the wide portion are smaller than an effective resistance value of the conductive region. A first amplifier for amplifying the transmission signal;
A second amplifier for amplifying the received signal received by the antenna;
An antenna switch circuit that transmits the transmission signal output from the first amplifier during transmission to the antenna and transmits the reception signal received by the antenna to the second amplifier during reception;
The antenna switch circuit is
A first terminal for inputting the transmission signal output from the first amplifier;
A second terminal connected to the antenna;
A third terminal for outputting the received signal received by the antenna;
A first switching element connected between the first terminal and the second terminal;
Comprising a second switching element connected between the second terminal and the third terminal,
During transmission, the first switching element is turned on and the second switching element is turned off. During reception, the first switching element is turned off and the second switching element is turned on. State
Each of the first and second switching elements is
Like a field effect transistor,
Two ohmic electrodes formed on a semiconductor substrate;
At least two gate electrodes disposed between the two ohmic electrodes;
A conductive region sandwiched between adjacent gate electrodes of the at least two gate electrodes,
The conductive region has, at one end, a wide portion wider than the conductive region sandwiched between the adjacent gate electrodes,
The distance between the adjacent gate electrodes is narrower than the width of the wide portion,
A high-frequency module, wherein a resistor is connected in series between the two ohmic electrodes through the wide portion. In claim 13,
One end of the gate electrode adjacent to the two ohmic electrodes of the at least two gate electrodes extends in a direction away from the sandwiched conductive region. In claim 13,
The high-frequency module, wherein the conductive region includes an n-type cap layer. In claim 13,
A high-frequency module, wherein the field effect transistor is a high electron mobility transistor. In claim 16,
A high-frequency module, wherein the high electron mobility transistor is a strained channel high electron mobility transistor. In claim 16,
The high-frequency module, wherein the high electron mobility transistor is a strain relaxation high electron mobility transistor. In claim 15,
A high-frequency module, wherein individual resistance values of the resistors connected in series between the two ohmic electrodes through the wide portion are smaller than an effective resistance value of the conductive region.

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