WO2023065955A1 - 通信方法及装置 - Google Patents

通信方法及装置 Download PDF

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Publication number
WO2023065955A1
WO2023065955A1 PCT/CN2022/120645 CN2022120645W WO2023065955A1 WO 2023065955 A1 WO2023065955 A1 WO 2023065955A1 CN 2022120645 W CN2022120645 W CN 2022120645W WO 2023065955 A1 WO2023065955 A1 WO 2023065955A1
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WIPO (PCT)
Prior art keywords
bit sequence
bit
sequence
decoding
value
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PCT/CN2022/120645
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English (en)
French (fr)
Inventor
郑孟帆
顾佳琦
凌聪
马梦瑶
王磊
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华为技术有限公司
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Publication of WO2023065955A1 publication Critical patent/WO2023065955A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present application relates to the communication field, and in particular to a communication method and device.
  • Separate source channel coding is about performing source coding and channel coding separately.
  • the advantage is that the design is simple and the versatility is good.
  • the disadvantage is that the wrong decoding results cannot be accurately judged without making full use of their respective advantages. , reducing system performance.
  • the present application provides a communication method and device, which can accurately determine an erroneous decoding result, and can increase the detection probability of an erroneous decoding result, thereby improving system performance.
  • a communication method includes: performing source coding on the first bit sequence to obtain a second bit sequence, obtaining a fourth bit sequence according to the second bit sequence and the third bit sequence, and performing channel coding on the fourth bit sequence to obtain a fifth bit sequence, send the fifth bit sequence.
  • the length of the first bit sequence is A
  • A is an integer greater than
  • the length of the second bit sequence is B
  • B is an integer greater than 0.
  • the length of the fifth bit sequence is N, and N is an integer greater than 0.
  • the sending end combines the source coding result of the first bit sequence with a part of the bit sequence in the first bit sequence to obtain the input of channel coding, that is, the fourth bit sequence, and for the fourth bit
  • the receiving end can use part of the bit sequence in the first bit sequence for joint decoding.
  • the joint source channel coding scheme (JSCC) the wrong decoding result can be accurately judged, the probability of the wrong decoding result being detected can be increased, and the system performance can be improved.
  • E is equal to C and F is equal to 0
  • the first bit satisfies the first principle
  • the first principle may include: E pieces of information whose first bit is at the front of the natural order of the fourth bit sequence Bits on.
  • the first bit satisfies the second principle
  • the second principle may include: the first bit of the fourth bit sequence and the first position of the sequence to be decoded
  • the source decoding value of one or more bits of the third bit sequence can be obtained, or, the first The bits are located on the last F frozen bits in the natural order of the fourth bit sequence.
  • the above-mentioned third bit sequence is C bits in the first bit sequence, which may include: the third bit sequence is the first C bits in natural order in the first bit sequence.
  • the above-mentioned third bit sequence is located on the first bit of the fourth bit sequence, which may include: the scrambled third bit sequence is located on the first bit of the fourth bit sequence, adding The scrambled third bit sequence is obtained according to the scrambling sequence and the third bit sequence.
  • scrambling the information bits of the fourth bit sequence will not increase the code rate of channel coding, which can improve system performance
  • a communication method includes: receiving a sequence to be decoded, performing channel decoding on the sequence to be decoded to obtain a channel decoding value of the fourth bit sequence, and performing source decoding on the channel decoding value of the second bit sequence to obtain the first The source coded value of the bit sequence.
  • the length of the sequence to be decoded is N, N is an integer greater than 0, the sequence to be decoded is the sequence after channel transmission of the fifth bit sequence, the fifth bit sequence is the channel coding value of the fourth bit sequence, and the to-be-decoded sequence
  • the first position of the code sequence corresponds to the first bit of the fourth bit sequence
  • the third bit sequence is on the first bit of the fourth bit sequence
  • E is an integer greater than or equal to
  • F is an integer greater than or equal to
  • the third bit sequence is the C bits in the first bit sequence
  • the first bit sequence The length is A, A is an integer greater than 0, and C is an integer greater than 0 and less than or equal to A.
  • the second position of the sequence to be decoded corresponds to the B information bits occupied by the second bit sequence in the fourth bit sequence, the second bit sequence is the information source code value of the first bit sequence, and the length of the second bit sequence is B, B is an integer greater than 0.
  • the channel decoding value of the fourth bit sequence includes the channel decoding value of the second bit sequence and the channel decoding value of the third bit sequence, and the length of the fourth bit sequence is N.
  • E is equal to C and F is equal to 0, and the first bit of the fourth bit sequence satisfies the first principle.
  • the first principle may include: the first bit is in the natural sequence of the fourth bit sequence on the first E information bits.
  • performing channel decoding on the sequence to be decoded to obtain the channel decoding value of the fourth bit sequence may include: the channel decoding method is a serial cancellation list (successive cancellation list, SCL) Decoding mode, the number of lists is L, L is an integer greater than 0, the initial value of c u_total is equal to 0, if c u_total is less than C, the following first source channel operation is performed.
  • the channel decoding method is a serial cancellation list (successive cancellation list, SCL) Decoding mode
  • the number of lists is L
  • L is an integer greater than 0
  • the initial value of c u_total is equal to 0, if c u_total is less than C, the following first source channel operation is performed.
  • Channel decoding is performed on the value at bit n-m to the value at bit n of the sequence to be decoded to obtain a first decoding result.
  • the n-mth bit to the nth bit may include at least one position in the first position and/or b positions in the second position, n-m is an integer greater than 0, m is an integer greater than 0, the first decoding result It may include a channel decoding value of b bits of the second bit sequence and/or a channel decoding value of at least one bit of the third bit sequence, where b is an integer greater than 0 and less than or equal to B.
  • c t is an integer greater than 0 and less than or equal to C.
  • c u bits of the third bit sequence determine the nth sequence to be decoded based on l decoding paths From the value on the +1 bit to the value on the Nth bit, continue to perform the first source channel operation, and count c u into c u_total .
  • c u is an integer greater than
  • l is an integer less than or equal to L.
  • c u_total is equal to C and n is less than N, continue to perform channel decoding from the value at bit n+1 to the value at bit N of the sequence to be decoded.
  • the source decoding value of c u bits of the third bit sequence and the channel decoding value of c u bits corresponding to the natural sequence of the third bit sequence are determined based on l
  • the decoding path continues to perform the first source channel operation from the value on the n+1th bit to the Nth bit of the sequence to be decoded, and counts c u into c u_total , which may include: traversing L decoding paths , determine whether the source decoding value of c u bits of the third bit sequence corresponding to the first decoding path and the channel decoding value of c u bits corresponding to the natural sequence of the third bit sequence corresponding to the first decoding path Same, and count c u into c u_total .
  • the first decoding path is one of the L decoding paths. If not, determine to delete the first decoding path, and terminate the operation of the first source channel based on the first decoding path. If they are the same, it is determined that the l decoding paths include the first decoding path.
  • F is equal to C and E is equal to 0, and the first bit satisfies the second principle, which includes: the first bit of the fourth bit sequence corresponds to the first position of the sequence to be decoded , after performing source decoding on the result of channel decoding the previous value of the first position of the sequence to be decoded, the source decoding value of one or more bits of the third bit sequence can be obtained, or, the first bit It is located on the last F frozen bits in the natural order of the fourth bit sequence.
  • the second principle which includes: the first bit of the fourth bit sequence corresponds to the first position of the sequence to be decoded , after performing source decoding on the result of channel decoding the previous value of the first position of the sequence to be decoded, the source decoding value of one or more bits of the third bit sequence can be obtained, or, the first bit It is located on the last F frozen bits in the natural order of the fourth bit sequence.
  • channel decoding is performed on the sequence to be decoded to obtain the channel decoding value of the fourth bit sequence, including: the channel decoding method is the serial cancellation list SCL decoding method, and the number of lists is L, L is an integer greater than 0, the initial value of c t_total is equal to 0, and if c t_total is less than C, the following second source channel operation is performed.
  • Channel decoding is performed on the value at bit n-m to the value at bit n of the sequence to be decoded to obtain a second decoding result.
  • bit n+1 is one of the first positions
  • n-m is an integer greater than
  • m is an integer greater than
  • the second decoding result includes channel decoding values of b bits of the second bit sequence.
  • Source decoding is performed on the channel decoding values of b bits in the second bit sequence to obtain source decoding values of c t bits in the third bit sequence, and c t is included in c t_total .
  • c t is an integer greater than 0 and less than or equal to C
  • the source decoding values of the c t bits of the third bit sequence are sequentially used as the channel decoding values at the c t positions in the first position of the sequence to be decoded code value.
  • c t_total is greater than 0 and less than C, continue to perform the second source channel operation from the value on bit n+1 to the value on bit N of the sequence to be decoded.
  • channel decoding continues from the value at bit n+1 to the value at bit N of the sequence to be decoded.
  • the above-mentioned third bit sequence is C bits in the first bit sequence, which may include: the third bit sequence is the first C bits in natural order in the first bit sequence.
  • a communication method includes: receiving a sequence to be decoded.
  • the qth iterative channel decoding is performed on the sequence to be decoded to obtain the channel decoding value of the fourth bit sequence.
  • the g-th source decoding is performed on the channel decoding value of the second bit sequence to obtain the source decoding value of the first bit sequence.
  • the source decoding value of the first bit sequence is output.
  • q is an integer greater than
  • the channel decoding value of the fourth bit sequence includes the channel decoding value of the second bit sequence and the channel decoding value of the third bit sequence.
  • Q is the maximum number of iterations, and Q is an integer greater than 0.
  • the sequence to be decoded includes the sequence after channel transmission of the fifth bit sequence
  • the fifth bit sequence is the channel coding value of the fourth bit sequence
  • the third bit sequence is on the first bit of the fourth bit sequence
  • the first bit of the fourth bit sequence includes C information bits
  • the third bit sequence is C bits in the first bit sequence
  • the length of the first bit sequence is A, where A is an integer greater than 0, and C is an integer greater than 0 and less than or equal to A.
  • the second position of the sequence to be decoded corresponds to the B information bits occupied by the second bit sequence in the fourth bit sequence, the second bit sequence is the information source code value of the first bit sequence, and the length of the second bit sequence is B, B is an integer greater than 0.
  • the communication method provided by the third aspect may also include: the channel decoding value of the third bit sequence is different from the source decoding value of the third bit sequence and q is less than Q Next, perform q+s iterative channel decoding on the sequence to be decoded, and perform g+t source decoding on the channel decoding value of the second bit sequence in the q+s iterative channel decoding result.
  • s is an integer greater than
  • t is an integer greater than 0.
  • the g-th source decoding is performed on the channel decoding value of the second bit sequence to obtain the source decoding value of the first bit sequence, which may include: When the channel decoding value passes the channel check, perform g-th source decoding on the channel decoding value of the second bit sequence to obtain the source decoding value of the first bit sequence.
  • a communication device in a fourth aspect, includes: a processing module and a transceiver module.
  • the processing module is configured to perform information source coding on the first bit sequence to obtain the second bit sequence.
  • the length of the first bit sequence is A, and A is an integer greater than 0, and the length of the second bit sequence is B, and B is an integer greater than 0.
  • the processing module is further configured to obtain a fourth bit sequence according to the second bit sequence and the third bit sequence.
  • the processing module is further configured to perform channel coding on the fourth bit sequence to obtain a fifth bit sequence.
  • the length of the fifth bit sequence is N, and N is an integer greater than 0.
  • the transceiver module is used to send the fifth bit sequence.
  • E is equal to C and F is equal to 0
  • the first bit satisfies the first principle
  • the first principle may include: E pieces of information whose first bit is at the front of the natural order of the fourth bit sequence Bits on.
  • the first bit satisfies the second principle
  • the second principle may include: the first bit of the fourth bit sequence and the first position of the sequence to be decoded
  • the source decoding value of one or more bits of the third bit sequence can be obtained, or, the first The bits are located on the last F frozen bits in the natural order of the fourth bit sequence.
  • the above-mentioned third bit sequence is C bits in the first bit sequence, which may include: the third bit sequence is the first C bits in natural order in the first bit sequence.
  • the above-mentioned third bit sequence is located on the first bit of the fourth bit sequence, which may include: the scrambled third bit sequence is located on the first bit of the fourth bit sequence, adding The scrambled third bit sequence is obtained according to the scrambling sequence and the third bit sequence.
  • the transceiver module described in the fourth aspect may include a receiving module and a sending module.
  • the receiving module is used for receiving data and/or signaling from the receiving end;
  • the sending module is used for sending data and/or signaling to the receiving end.
  • This application does not specifically limit the specific implementation manner of the transceiver module.
  • the communication device described in the fourth aspect may further include a storage module, where programs or instructions are stored in the storage module.
  • the processing module executes the program or instruction
  • the communication device described in the fourth aspect can execute the method described in the first aspect.
  • the communication device described in the fourth aspect may be the sending end (such as network equipment, or terminal equipment, etc.), or it may be a chip (system) or other components or components that can be set at the sending end. No limit.
  • a communication device in a fifth aspect, includes: a processing module and a transceiver module.
  • the transceiver module is used for receiving the sequence to be decoded.
  • the length of the sequence to be decoded is N, N is an integer greater than 0, the sequence to be decoded is the sequence after channel transmission of the fifth bit sequence, the fifth bit sequence is the channel coding value of the fourth bit sequence, and the to-be-decoded sequence
  • the first position of the code sequence corresponds to the first bit of the fourth bit sequence
  • the third bit sequence is on the first bit of the fourth bit sequence
  • E is an integer greater than or equal to
  • F is an integer greater than or equal to
  • the third bit sequence is the C bits in the first bit sequence
  • the first bit sequence The length is A, A is an integer greater than 0, and C is an integer greater than 0 and less than or equal to A.
  • the second position of the sequence to be decoded corresponds to the B information bits occupied by the second bit sequence in the fourth bit sequence, the second bit sequence is the information source code value of the first bit sequence, and the length of the second bit sequence is B, B is an integer greater than 0.
  • the processing module is configured to perform channel decoding on the sequence to be decoded to obtain a channel decoding value of the fourth bit sequence.
  • the channel decoding value of the fourth bit sequence includes the channel decoding value of the second bit sequence and the channel decoding value of the third bit sequence, and the length of the fourth bit sequence is N.
  • the processing module is further configured to perform source decoding on the channel decoding value of the second bit sequence to obtain the source decoding value of the first bit sequence.
  • E is equal to C and F is equal to 0, and the first bit of the fourth bit sequence satisfies the first principle.
  • the first principle may include: the first bit is in the natural sequence of the fourth bit sequence on the first E information bits.
  • the channel decoding method is the serial cancellation list SCL decoding method
  • the number of lists is L
  • L is an integer greater than 0
  • the initial value of c u_total is equal to 0, if c u_total is less than C
  • the processing module is further configured to perform the following first source channel operation.
  • the processing module is further configured to perform channel decoding on the value at bit n-m to the value at bit n of the sequence to be decoded to obtain a first decoding result.
  • the n-mth bit to the nth bit may include at least one position in the first position and/or b positions in the second position, n-m is an integer greater than 0, m is an integer greater than 0, the first decoding result It may include a channel decoding value of b bits of the second bit sequence and/or a channel decoding value of at least one bit of the third bit sequence, where b is an integer greater than 0 and less than or equal to B.
  • the processing module is further configured to perform source decoding on the channel decoding values corresponding to the b bits of the second bit sequence to obtain source decoding values of the c t bits of the third bit sequence.
  • c t is an integer greater than 0 and less than or equal to C.
  • the processing module is further configured to determine, according to the source decoding values of c u bits of the third bit sequence and the channel decoding values of c u bits corresponding to the natural sequence of the third bit sequence, to determine the treatment based on l decoding paths
  • the value at the n+1th bit to the Nth bit of the decoding sequence continues to perform the first source channel operation, and counts c u into c u_total .
  • c u is an integer greater than
  • l is an integer less than or equal to L.
  • the processing module is further configured to continue channel decoding from the value at bit n+1 to the value at bit N of the sequence to be decoded.
  • the processing module is also used to traverse the L decoding paths, and determine the information source decoding value of the third bit sequence c u bits corresponding to the first decoding path and the first decoding path Whether the channel decoding values of c u bits corresponding to the natural sequence of the third bit sequence are the same, and c u is included in c u_total .
  • the first decoding path is one of the L decoding paths.
  • the processing module is further configured to determine to delete the first decoding path, and terminate the operation of the first source channel based on the first decoding path.
  • the processing module is further configured to determine that the l decoding paths include the first decoding path.
  • F is equal to C and E is equal to 0, and the first bit satisfies the second principle, which includes: the first bit of the fourth bit sequence corresponds to the first position of the sequence to be decoded , after performing source decoding on the result of channel decoding the previous value of the first position of the sequence to be decoded, the source decoding value of one or more bits of the third bit sequence can be obtained, or, the first bit It is located on the last F frozen bits in the natural order of the fourth bit sequence.
  • the second principle which includes: the first bit of the fourth bit sequence corresponds to the first position of the sequence to be decoded , after performing source decoding on the result of channel decoding the previous value of the first position of the sequence to be decoded, the source decoding value of one or more bits of the third bit sequence can be obtained, or, the first bit It is located on the last F frozen bits in the natural order of the fourth bit sequence.
  • the channel decoding method is the serial cancellation list SCL decoding method
  • the number of lists is L
  • L is an integer greater than 0
  • the initial value of c t_total is equal to 0, if c t_total is less than C
  • the processing module is further configured to perform the following second source channel operation.
  • the processing module is further configured to perform channel decoding on the value at bit n-m to the value at bit n of the sequence to be decoded to obtain a second decoding result.
  • bit n+1 is one of the first positions
  • n-m is an integer greater than
  • m is an integer greater than
  • the second decoding result includes channel decoding values of b bits of the second bit sequence.
  • the processing module is also used to perform source decoding on the b-bit channel decoding values of the second bit sequence to obtain the source decoding values of c t bits of the third bit sequence, and count c t into c t_total .
  • c t is an integer greater than 0 and less than or equal to C
  • the source decoding values of the c t bits of the third bit sequence are sequentially used as the channel decoding values at the c t positions in the first position of the sequence to be decoded code value.
  • the processing module is further configured to continue to perform the second source channel operation on the value of the n+1th bit to the Nth bit of the sequence to be decoded.
  • the processing module is further configured to continue channel decoding from the value at bit n+1 to the value at bit N of the sequence to be decoded.
  • the above-mentioned third bit sequence is C bits in the first bit sequence, which may include: the third bit sequence is the first C bits in natural order in the first bit sequence.
  • the transceiver module described in the fifth aspect may include a receiving module and a sending module.
  • the receiving module is used for receiving data and/or signaling from the sending end;
  • the sending module is used for sending data and/or signaling to the sending end.
  • This application does not specifically limit the specific implementation manner of the transceiver module.
  • the communication device described in the fifth aspect may further include a storage module, where programs or instructions are stored in the storage module.
  • the processing module executes the program or instruction
  • the communication device described in the fifth aspect can execute the method described in the second aspect.
  • the communication device described in the fifth aspect may be the receiving end (such as network equipment, or terminal equipment, etc.), or it may be a chip (system) or other components or components that can be set at the receiving end. No limit.
  • a communication device in a sixth aspect, includes: a processing module and a transceiver module.
  • the transceiver module is used for receiving the sequence to be decoded.
  • the sequence to be decoded includes the sequence after channel transmission of the fifth bit sequence, the fifth bit sequence is the channel coding value of the fourth bit sequence, the first position of the sequence to be decoded and the first bit of the fourth bit sequence bit correspondence, the third bit sequence is on the first bit of the fourth bit sequence, the first bit of the fourth bit sequence includes C information bits, and the third bit sequence is C bits in the first bit sequence,
  • the length of the first bit sequence is A, where A is an integer greater than 0, and C is an integer greater than 0 and less than or equal to A.
  • the second position of the sequence to be decoded corresponds to the B information bits occupied by the second bit sequence in the fourth bit sequence, the second bit sequence is the information source code value of the first bit sequence, and the length of the second bit sequence is B, B is an integer greater than 0.
  • the processing module is configured to perform the qth iterative channel decoding on the sequence to be decoded to obtain the channel decoding value of the fourth bit sequence.
  • q is an integer greater than 0, and the channel decoding value of the fourth bit sequence includes the channel decoding value of the second bit sequence and the channel decoding value of the third bit sequence.
  • the processing module is further configured to perform gth source decoding on the channel decoding value of the second bit sequence to obtain the source decoding value of the first bit sequence.
  • g is an integer greater than 0, and the information source decoding value of the first bit sequence includes the information source decoding value of the third bit sequence.
  • the processing module is further configured to output the source decoding value of the first bit sequence when the channel decoding value of the third bit sequence is the same as the source decoding value of the third bit sequence or q is equal to Q.
  • Q is the maximum number of iterations, and Q is an integer greater than 0.
  • the processing module when the channel decoding value of the third bit sequence is different from the source decoding value of the third bit sequence and q is less than Q, the processing module is also used to Perform q+s iterative channel decoding, and perform g+t th source decoding on the channel decoding value of the second bit sequence in the q+s iterative channel decoding result.
  • s is an integer greater than
  • t is an integer greater than 0.
  • the processing module when the channel decoding value of the fourth bit sequence passes the channel check, the processing module is also used to perform the gth source decoding on the channel decoding value of the second bit sequence code to obtain the source decoding value of the first bit sequence.
  • the transceiver module described in the sixth aspect may include a receiving module and a sending module.
  • the receiving module is used for receiving data and/or signaling from the sending end;
  • the sending module is used for sending data and/or signaling to the sending end.
  • This application does not specifically limit the specific implementation manner of the transceiver module.
  • the communication device described in the sixth aspect may further include a storage module, where programs or instructions are stored in the storage module.
  • the processing module executes the program or instruction
  • the communication device described in the sixth aspect can execute the method described in the third aspect.
  • the communication device described in the sixth aspect may be the receiving end (such as network equipment, or terminal equipment, etc.), or it may be a chip (system) or other components or components that can be set at the receiving end. No limit.
  • a communication device in a seventh aspect, includes: a processor, the processor is coupled with a memory, and the memory is used for storing computer programs.
  • the processor is configured to execute the computer program stored in the memory, so that the communication method described in any possible implementation manner of the first aspect to the third aspect is executed.
  • the communication device described in the seventh aspect may further include a transceiver.
  • the transceiver can be a transceiver circuit or an input/output port.
  • the transceiver may be used by the communication means to communicate with other devices.
  • the input port can be used to realize the receiving function involved in the first aspect to the third aspect
  • the output port can be used to realize the sending function involved in the first aspect to the third aspect
  • the communication device described in the seventh aspect may be a sending end or a receiving end, or a chip or a chip system disposed inside the sending end or the receiving end.
  • a communication system in an eighth aspect, includes the communication device according to the fourth aspect and the communication device according to the fifth aspect. Or, the communication system includes the communication device according to the fourth aspect and the communication device according to the sixth aspect.
  • the communication system includes the communication device according to the fourth aspect for realizing the method according to the first aspect, and the communication device according to the fifth aspect for realizing the method according to the second aspect.
  • the communication system includes the communication device according to the fourth aspect for realizing the method according to the first aspect, and the communication device according to the sixth aspect for realizing the method according to the third aspect.
  • a chip system in a ninth aspect, includes a logic circuit and an input/output port.
  • the logic circuit is used to realize the processing function involved in the first aspect to the third aspect
  • the input/output port is used to realize the sending and receiving function involved in the first aspect to the third aspect.
  • the input port can be used to realize the receiving function involved in the first aspect to the third aspect
  • the output port can be used to realize the sending function involved in the first aspect to the third aspect.
  • system-on-a-chip further includes a memory, which is used to store program instructions and data for realizing the functions involved in the first aspect to the third aspect.
  • the system-on-a-chip may consist of chips, or may include chips and other discrete devices.
  • a computer-readable storage medium stores computer programs or instructions; when the computer programs or instructions are run on a computer, any one of the first to third aspects The communication method described in the possible implementation manner is executed.
  • a computer program product including a computer program or instruction, when the computer program or instruction is run on a computer, the communication described in any one of the possible implementations of the first aspect to the third aspect is made method is executed.
  • the sending end combines the source coding result of the first bit sequence with a part of the bit sequence in the first bit sequence to obtain the input of the channel coding, that is, the fourth bit sequence, and for the fourth The bit sequence is channel-coded.
  • the receiving end can use part of the bit sequence in the first bit sequence for joint decoding. This joint source-channel coding scheme can accurately determine the error The decoding result can increase the detection probability of the wrong decoding result, thereby improving the system performance.
  • FIG. 1 is a schematic diagram of the architecture of a communication system provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a signal processing process provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a polar code provided in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a decoding tree provided by an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a communication method provided by an embodiment of the present application.
  • Figure 6a to Figure 6g provide various coding schematic diagrams for the embodiment of the present application.
  • Fig. 7 is a schematic diagram of source coding from variable length to fixed length provided by the embodiment of the present application.
  • FIG. 8 is a schematic diagram of a source coding value provided by an embodiment of the present application.
  • FIG. 9 is a schematic flowchart of another communication method provided by the embodiment of the present application.
  • FIG. 10 is a schematic diagram of a block error rate performance provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of another block error rate performance provided by the embodiment of the present application.
  • FIG. 12 is a schematic diagram of another block error rate performance provided by the embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a communication device provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of another communication device provided by an embodiment of the present application.
  • the technical solution of the embodiment of the present application can be applied to various communication systems, such as wireless fidelity (wireless fidelity, WiFi) system, vehicle to any object (vehicle to everything, V2X) communication system, device-to-device, D2D) communication system, Internet of Vehicles communication system, 4th generation (4G) mobile communication system, such as long term evolution (LTE) system, worldwide interoperability for microwave access (WiMAX) communication system, the fifth generation (5th generation, 5G) mobile communication system, such as the new air interface (new radio, NR) system, and future communication systems, such as the sixth generation (6th generation, 6G) mobile communication system, etc.
  • 4G 4th generation
  • LTE long term evolution
  • WiMAX worldwide interoperability for microwave access
  • 5th generation, 5G mobile communication system
  • future communication systems such as the sixth generation (6th generation, 6G) mobile communication system, etc.
  • the present application presents various aspects, embodiments or features in terms of a system that can include a number of devices, components, modules and the like. It is to be understood and appreciated that the various systems may include additional devices, components, modules, etc. and/or may not include all of the devices, components, modules etc. discussed in connection with the figures. In addition, combinations of these schemes can also be used.
  • the network architecture and business scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute limitations on the technical solutions provided by the embodiments of the present application.
  • the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.
  • FIG. 1 is a schematic structural diagram of a communication system to which the communication method provided in the embodiment of the present application is applicable.
  • the communication system includes terminal equipment and network equipment.
  • the number of terminal devices may be one or more, and the number of network devices may be one or more.
  • the above-mentioned terminal device is a terminal that accesses the above-mentioned communication system and has a wireless transceiver function, or a chip or a chip system that can be set on the terminal.
  • the terminal equipment may also be called user equipment (user equipment, UE), user device, access terminal, subscriber unit, subscriber station, mobile station, mobile station (mobile station, MS), remote station, remote terminal, mobile device, A user terminal, terminal, terminal unit, end station, terminal device, wireless communication device, user agent or user device.
  • the terminal device in the embodiment of the present application may be a mobile phone, a wireless data card, a personal digital assistant (personal digital assistant, PDA) computer, a laptop computer, a tablet computer (Pad), Unmanned aerial vehicles, computers with wireless transceiver functions, machine type communication (machine type communication, MTC) terminals, virtual reality (virtual reality, VR) terminal equipment, augmented reality (augmented reality, AR) terminal equipment, Internet of Things (Internet of Things) things, IoT) terminal equipment, wireless terminals in industrial control, wireless terminals in self driving, wireless terminals in remote medical, wireless terminals in smart grid Terminals, wireless terminals in transportation safety, wireless terminals in smart city, wireless terminals in smart home (such as game consoles, smart TVs, smart speakers, smart refrigerators and fitness equipment etc.), vehicle-mounted terminals, and RSUs with terminal functions.
  • MTC machine type communication
  • VR virtual reality
  • AR augmented reality
  • IoT Internet of Things
  • An access terminal can be a cellular phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA) , a handheld device (handset) with wireless communication function, a computing device or other processing device connected to a wireless modem, a wearable device, and the like.
  • SIP session initiation protocol
  • WLL wireless local loop
  • PDA personal digital assistant
  • Handset handheld device with wireless communication function
  • computing device or other processing device connected to a wireless modem a wearable device, and the like.
  • the terminal device in the embodiment of the present application can be an express terminal in smart logistics (such as a device that can monitor the location of cargo vehicles, a device that can monitor the temperature and humidity of goods, etc.), a wireless terminal in smart agriculture (such as a device that can collect poultry wearable devices related to livestock data, etc.), wireless terminals in smart buildings (such as smart elevators, fire monitoring equipment, and smart meters, etc.), wireless terminals in smart medical care (such as wireless terminals that can monitor the physiological status of people or animals) Wearable devices), wireless terminals in smart transportation (such as smart buses, smart vehicles, shared bicycles, charging pile monitoring equipment, smart traffic lights, and smart monitoring and smart parking equipment, etc.), wireless terminals in smart retail (such as automatic vending Cargo planes, self-checkout machines, and unmanned convenience stores, etc.).
  • smart logistics such as a device that can monitor the location of cargo vehicles, a device that can monitor the temperature and humidity of goods, etc.
  • a wireless terminal in smart agriculture such as a device that can collect poultry wearable devices
  • the terminal device of the present application may be a vehicle-mounted module, a vehicle-mounted module, a vehicle-mounted component, a vehicle-mounted chip, or a vehicle-mounted unit built into a vehicle as one or more components or units. Groups, on-board components, on-board chips, or on-board units can implement the methods provided in this application.
  • the above-mentioned network device is a device located on the network side of the above-mentioned communication system and having a wireless transceiver function or a chip or a chip system that can be provided in the device.
  • the network equipment includes but is not limited to: an access point (access point, AP) in a wireless fidelity (Wi-Fi) system, such as a home gateway, a router, a server, a switch, a bridge, etc., and an evolved node B (evolved Node B, eNB), radio network controller (radio network controller, RNC), node B (Node B, NB), base station controller (base station controller, BSC), base transceiver station (base transceiver station, BTS) , home base station (for example, home evolved NodeB, or home Node B, HNB), baseband unit (baseband unit, BBU), wireless relay node, wireless backhaul node, transmission point (transmission and reception point, TRP or transmission point, TP), etc.
  • the device sending the bit sequence is the sending end
  • the device receiving the bit sequence is the receiver.
  • the sending end can realize functions such as signal generation and transmission, and can be a network device or a terminal device
  • the receiving end can realize functions such as signal acquisition and processing, and can be a network device or a terminal device.
  • the network device sends a bit sequence to the terminal device, the network device is the sending end, and the terminal device is the receiving end; in the downlink communication scenario, the terminal device sends the bit sequence to the network device, and the terminal device is the sending end, and the network device is the receiving end.
  • one terminal device can send a bit sequence to another terminal device, and in this case, the sending end and the receiving end are different terminal devices; one network device can send a bit sequence to another network device A sequence of bits, in which case the sender and receiver are different network devices.
  • the sending end can be used as the receiving end to realize functions such as signal acquisition and processing; the receiving end can be used as the sending end to realize functions such as signal generation and transmission.
  • a physical device can be the sender, or it can be the receiver, or both.
  • FIG. 1 is only a simplified schematic diagram for easy understanding, and the communication system may also include other network devices and/or other terminal devices, which are not shown in FIG. 1 .
  • the information source is sent to the receiving end on the channel after sequentially undergoing source coding, channel coding, rate matching and modulation, and the receiving end receives the sent After the signal sent by the terminal, the destination is obtained through demodulation, rate matching, channel decoding and source decoding in sequence.
  • the method provided in the embodiment of the present application can be specifically applied to the process of joint source-channel coding at the sending end and joint source-channel decoding at the receiving end.
  • the method provided by the embodiment of this application can be specifically executed by an encoder at the sending end and a decoder at the receiving end.
  • the encoder can include a source encoder and a channel encoder
  • the decoder can include a source decoder and a channel decoder. .
  • Polar code is a linear block code, which is a channel coding scheme that can be strictly proved to "reach" the channel capacity. It has the characteristics of high performance and low complexity, and can be used for 5G control channel enhanced mobile broadband. , eMBB) scenario.
  • the coding process of polar code is in, is a Polar code with code length N, is a binary row vector of length N, is the encoding matrix, represents the Kronecker power of F, defined as in,
  • a part of the bits of can be used to carry information, and the bits carrying information can be called information bits or information bits, these information bits constitute a set of information bits, and the index set of information bits can be denoted as A.
  • the other part of bits can be set as a fixed value pre-agreed by the receiving end and the sending end, called fixed bits or frozen bits (frozen bits) or frozen bits. Wherein, the frozen bit can be set to 0, or can be set to any fixed value pre-agreed by the receiving end and the sending end, without limitation.
  • the row vector u passes through the generator matrix, and the encoded Bits can be a vector (X1, X2, X3, X4, X5, X6, X7, X8).
  • the encoded Bits can be a vector (X1, X2, X3, X4, X5, X6, X7, X8).
  • ⁇ u1, u2, u3, u5 ⁇ can be determined as the position of the frozen bit
  • ⁇ u4, u6, u7, u8 ⁇ can be determined as the position of the information bit
  • the length is 4 information vectors to be encoded are mapped to information bit positions.
  • u A is The set of information bits in , its length is denoted as K.
  • G N (A) is a sub-matrix in G N composed of rows corresponding to indexes in the information bit index set A, and G N (A) is a K ⁇ N matrix.
  • the construction process of the Polar code is actually the selection process of the set A, and the accuracy of the selection process determines the performance of the Polar code.
  • Serial cancellation (successive cancellation, SC) decoding is a polar code decoding algorithm.
  • the performance of polar codes using SC decoding is not ideal.
  • Improved algorithms can be obtained based on SC decoding, such as serial offset list decoding, serial offset stack decoding, etc.
  • the improved algorithm based on SC decoding can preserve multiple decoding paths during the decoding process and output
  • the method of decoding the result with the highest probability improves the finite code length performance of the polar code.
  • the finite code length performance of polar codes can be further improved by using cyclic redundancy check (CRC) to assist in screening correct decoding results.
  • CRC cyclic redundancy check
  • the decoding tree may have multiple layers of decoding nodes, and a circle in Fig. 4 represents a decoding node.
  • Arithmetic coding is a lossless data compression method and a method of entropy coding.
  • the difference between arithmetic coding and other entropy coding methods is that other entropy coding methods usually divide the input message into symbols and then encode each symbol, while arithmetic coding directly converts the entire input according to the probability of the source symbol
  • the message encoding of is a decimal n satisfying (0.0 ⁇ n ⁇ 1.0).
  • arithmetic coding can give near-optimal coding results.
  • Compression algorithms that use arithmetic coding usually estimate the probability of the input symbols before encoding. The more accurate this estimate is, the closer the encoding result is to the optimal result.
  • the initial interval of encoding is [0,1).
  • the encoding process first reads the next source symbol, and then determines the next interval based on the value of the symbol.
  • the current coding interval is [a, b)
  • the new interval becomes [a, a+(ba)*p 0 ); if the next symbol is 1, the new interval becomes [ a+(ba)*p 0 ,b).
  • the finally obtained result interval uniquely determines the encoded symbol sequence.
  • Arithmetic coding can handle not only the compression of non-memory sources, but also memory sources.
  • an adaptive interval determination method can be used for encoding, that is, a new encoding interval is determined according to the conditional distribution probability under a specific context, and adaptively updated with different contexts.
  • the decoder can use the same model as the encoder.
  • the communication method provided by the embodiment of the present application will be described in detail below with reference to FIGS. 5-9 .
  • the communication method provided by the embodiment of the present application may be applicable to a scenario where information source redundancy not only has non-uniformity but also memory.
  • FIG. 5 is a schematic flowchart of a communication method provided in an embodiment of the present application.
  • the communication method includes the following steps:
  • the sending end performs source coding on the first bit sequence to obtain a second bit sequence.
  • the length of the first bit sequence is A, and A is an integer greater than 0. This application does not limit the value of A.
  • the length of the second bit sequence is B, and B is an integer greater than 0. This application does not limit the value of B.
  • a in the following may represent the length of the first bit sequence
  • B may represent the length of the second bit sequence, which are described uniformly here and will not be described in detail below.
  • the sending end performs source coding on the first bit sequence to obtain the second bit sequence.
  • the sending end may use arithmetic coding to perform source coding on the first bit sequence to obtain the second bit sequence
  • the receiving end may use arithmetic decoding to perform source decoding
  • the above S501 may include: S501-1 to S501-4.
  • the sending end performs bit-by-bit source coding on the first bit sequence, and obtains a first source coding value of the first bit sequence after performing source coding on the a-th bit of the first bit sequence.
  • a is an integer greater than 0 and less than or equal to A.
  • Fig. 7 is a schematic diagram of source coding from variable length to fixed length provided by the embodiment of the present application. As shown in FIG. 7 , after source coding is performed on the first bit to the 50th bit of the first bit sequence, a first source code value of the first bit sequence is obtained.
  • the first length threshold may be an integer greater than 0.
  • the length of the first length threshold can be 30 bits, if the length of the first source coded value of the first bit sequence is exactly equal to 30, then output the first source coded value of the first bit sequence.
  • the first source coding value may include first length information, and the first length information may indicate that the first source coding value is obtained after source coding a first number of bits in the first bit sequence of.
  • the first length information may indicate how many bits of the first source code value correspond to the first bit sequence.
  • the first source coding value of the first bit sequence is obtained, assuming that the length of the first length threshold is 30 bits, the first The length of the first source coded value of a bit sequence is exactly equal to 30, and the first length information may indicate the first number of 50.
  • the next time source coding is performed from the 51st bit.
  • the first length information may be placed in the first bit in natural order of the first information source coded value.
  • the sending end deletes the second source code value in the first source code value to obtain the third source code value value, pad the end of the third source coded value with zeros, and output the fourth source coded value.
  • the second source coding value is obtained by performing source coding on the a-th bit of the first bit sequence, and the length of the fourth source coding value is equal to the first length threshold.
  • the length of the first source coded value of the first bit sequence is equal to 31, wherein the first source coded value includes the third source coded value and the second source coded value Source coded value.
  • the length of the third source coding value is 29, which is obtained by performing source coding on the first bit to the 49th bit of the first bit sequence; the length of the second source coding value is 2, which is obtained by coding the first bit.
  • the 50th bit of the sequence is obtained by source coding.
  • the second source code value in the first source code value can be deleted to obtain a third source code value with a length of 29.
  • the length of the third source coded value is not equal to the first length threshold 30, and the end of the third source coded value can be padded with zeros so that the length of the third source coded value is 30, and the zero-padded first Three source coded values. The next time the source coding is performed from the 50th bit.
  • the length of the first source coding value is not necessarily exactly equal to the first length threshold, and it is possible that the length of the encoding result obtained after encoding the a-1th bit is smaller than the first length threshold, but for the ath The length of the encoding result obtained after the bit encoding is completed is greater than the first length threshold.
  • the coded bit corresponding to the ath bit in the first source coded value may be deleted, and the end of the deleted first source coded value is zero-filled to the first length threshold.
  • the sending end pads the end of the first source code value with zeros, and outputs The fifth source code value.
  • the length of the fifth source coded value is equal to the first length threshold.
  • both the fourth source code value and the fifth source code value may include corresponding length information to indicate the length of the original source corresponding to the source code value.
  • the end of the first source coded value can be filled with zeros and output, so that each The source coded values of a segment are of the same length.
  • the bits of the length information and the trailing zero padding bits in the source coded value can be called non-uniform bits
  • Non-uniform bits can be mapped to less reliable information bits.
  • the bits of the length information and the zero-padding bits at the end are mapped to the information bits with low reliability, and then channel coding and decoding operations can be performed on the mapped source coded values, which can improve the error rate of decoding. The probability that the code result is detected.
  • the sender can compress information sources of different lengths into multiple sequences of the same length, which can take into account both lossless compression and fixed output lengths, and subsequently can use a fixed code rate for channel coding, and can also use compressed non-uniform bits
  • Auxiliary decoding can improve the decoding success rate.
  • the sending end obtains a fourth bit sequence according to the second bit sequence and the third bit sequence.
  • the third bit sequence may be C bits in the first bit sequence, where C is an integer greater than 0 and less than or equal to A.
  • C bits may be selected from the A bits of the first bit sequence as the third bit sequence.
  • C bit sequences in the third bit sequence may be continuous C bits as shown in Figure 6a, Figure 6b, and Figure 6c, or non-consecutive C bits, and this application does not To limit.
  • the sending end selects part of the bits in the first bit sequence and maps them to the fourth bit sequence, so as to use part of the original source bit sequence to assist in channel decoding, without modifying the source coding result, it can accurately determine whether the decoding result is Accurate, improve the success rate of decoding.
  • the third bit sequence is C bits in the first bit sequence, which may include: the third bit sequence is the first C bits in natural order in the first bit sequence.
  • the first bit sequence includes a 1 , a 2 , a 3 , a 4 , a 5 , a 6 , a 7 , a 8
  • a 1 can represent the first bit in the natural order
  • a 2 It can represent the second bit in the natural order
  • a 3 can represent the third bit in the natural order
  • a 8 can represent the eighth bit in the natural order.
  • the third bit sequence may be the first C bits in natural order in the first bit sequence.
  • selecting the first bit in the natural order of the first bit sequence as the third bit sequence can make it possible to participate in the verification earlier in the decoding process, and can judge whether the decoding result is accurate earlier. If the decoding result exists error, decoding can be stopped earlier.
  • the third bit sequence may be the middle C bits of natural order in the first bit sequence, as shown in Fig. 6b and Fig. 6c.
  • the third bit sequence may be any C bits in the first bit sequence.
  • it may be the last C bits in the natural order in the first bit sequence, which is not limited in the present application.
  • the length of the fourth bit sequence is N, and N is an integer greater than 0.
  • the fourth sequence of bits may include one or more information bits, and one or more freeze bits.
  • the second bit sequence may be on the B information bits of the fourth bit sequence.
  • the second bit sequence can be mapped to B information bits of the fourth bit sequence.
  • the B information bits may be continuous or discontinuous, which is not limited in this application.
  • the third bit sequence may be located on the first bit of the fourth bit sequence.
  • the sending end may place all the bits of the third bit sequence on the information bits of the fourth bit sequence; or place all the bits of the third bit sequence on the frozen bits of the fourth bit sequence; or , placing part of the third bit sequence on the information bits of the fourth bit sequence, and placing the other part on the frozen bits of the fourth bit sequence.
  • the third bit sequence is placed on the E information bits and F frozen bits of the fourth bit sequence.
  • the sending end may place C bits of the third bit sequence on consecutive C bits of the fourth bit sequence. As shown in Figure 6a, it is placed on consecutive C frozen bits. As shown in FIG. 6b or FIG. 6d, it is placed on consecutive C information bits. As shown in FIG. 6e, it is placed on consecutive C1 information bits and C2 freezing bits.
  • mapping the third bit sequence to the frozen bits of the fourth bit sequence does not increase the code rate of channel coding, and can improve system performance.
  • E is equal to C and F is equal to 0
  • the first bit satisfies the first principle
  • the first principle may include: E pieces of information whose first bit is at the front of the natural order of the fourth bit sequence Bits on.
  • the length of the third bit sequence is 10, including c 1 to c 10
  • the length of the second bit sequence is 32, including b 1 to b 32 .
  • the third bit sequence is in the first bit position
  • the second bit sequence is in other information bits of the fourth bit sequence.
  • the arrangement order of the third bit sequence and the second bit sequence can be c 1 c 2 ... c 10 b 1 b 2 . . . b 32 .
  • E is equal to C and F is equal to 0, and the first bit satisfies the first principle, and the first principle may include: E bits of the first bit and B bits of the second bit sequence Alternately.
  • the length of the third bit sequence is 10, including c 1 to c 10
  • the length of the second bit sequence is 32, including b 1 to b 32 .
  • the arrangement order of the third bit sequence and the second bit sequence can be c 1 b 1 c 2 b 2 c 3 b 3 c 4 b 4 c 5 b 5 c 6 b 6 c 7 b 7 c 8 b 8 c 9 b 9 c 10 b 10 b 11 ...b 32 ,b 1 c 1 b 2 c 2 b 3 c 3 b 4 c 4 b 5 c 5 b 6 c 6 b 7 c 7 b 8 c 8 b 9 c 9 b 10 c 10 b 11 ... b 32 , c 1 c 2 b 1 b 2 c 3 c 4 b 3 b 4 ...
  • the embodiment of the present application does not limit how the E bits of the first bit and the B bits of the second bit sequence are alternately arranged. In the case of alternating arrangement in this application, it is defined whether there is an interval between each bit of the third bit sequence and the second bit sequence.
  • the situation that the E bits of the first bit are arranged alternately with the B bits of the second bit sequence can make it possible to judge whether the decoding result of this part is accurate after decoding some bits in the decoding process.
  • whether the decoding result of this part is accurate can be judged earlier, and if there is an error in the decoding result, the decoding can be stopped earlier.
  • E bits of the first bit and B bits of the second bit sequence is also applicable to the case where E is greater than 0 and F is greater than 0.
  • the first bit satisfies the second principle
  • the second principle may include: the first bit of the fourth bit sequence and the first position of the sequence to be decoded
  • the source decoding value of one or more bits of the third bit sequence can be obtained, or, the first The bits are located on the last F frozen bits in the natural order of the fourth bit sequence.
  • the sequence to be decoded is a sequence of the fifth bit sequence transmitted through a channel.
  • the sending end performs channel coding on the fourth bit sequence to obtain the fifth bit sequence, and sends the fifth bit sequence through the channel, and the receiving end receives the sequence to be decoded.
  • the first position of the sequence to be decoded corresponds to the first bit of the fourth bit sequence
  • the third bit sequence is located on the first bit of the fourth bit sequence
  • the bit sequence number of the first position of the sequence to be decoded is the same as that of the fourth bit sequence
  • the bit number of the first bit of the bit sequence is the same.
  • the first bit may be on the last C frozen bits in the natural order of the fourth bit sequence.
  • the C bits of the third bit sequence are in the first bit position (the 38th to the 47th bit) of the fourth bit sequence, and the first bit corresponds to the first position of the sequence to be decoded (bits 38 to 47) satisfy: perform source decoding on the result of channel decoding the previous value of the first position of the sequence to be decoded (for example, the value on the first bit to the value on the 37th bit) After that, the source decoding values of the C bits of the third bit sequence can be obtained.
  • the C bits of the third bit sequence are on the first bit (the 21st to the 25th, and the 38th to the 42nd) of the fourth bit sequence, and the first bit (the 38th to the 42nd) 21st to 25th) corresponding to the first position of the sequence to be decoded (21st to 25th) meet: the bits before the C1 bits of the sequence to be decoded (for example, the value on the 1st bit to The value on the 20th bit) is channel-decoded and source-decoded to obtain the corresponding C1-bit source-decoded value of the third bit sequence.
  • the source decoding values of the corresponding C1 bits of the third bit sequence are used as the channel decoding values at positions of the C1 bits of the sequence to be decoded.
  • the first position (bit 38 to bit 42) of the sequence to be decoded corresponding to the first bit (bit 38 to bit 42) satisfies: continue to After the channel decoding result of the previous bits of C2 bits (for example, the value on the 21st bit to the value on the 37th bit) is subjected to source decoding, the corresponding C2 bits of the third bit sequence can be obtained Source decoding value.
  • the source decoding value for example, the corresponding 4-bit source decoding value of the third bit sequence can be obtained. That is to say, it can be guaranteed that the source decoding value of the corresponding C2 bits of the third bit sequence can be obtained after channel decoding the result of channel decoding the previous values of the C2 positions of the sequence to be decoded, that is, Can.
  • the above-mentioned second principle is also applicable to the case where E is greater than 0 and F is greater than 0.
  • the first bits may include E information bits and F frozen bits, E is greater than 0 and F is greater than 0, and the E information bits satisfy the first principle, that is, the E information bits are in the fourth On the first E information bits of the natural order of the bit sequence (as shown in Figure 6c), or the E bits are arranged alternately with the B bits of the second bit sequence; the F bits satisfy the second principle, that is The first bit of the fourth bit sequence corresponds to the first position of the sequence to be decoded, and the third bit can be obtained after channel decoding the result of channel decoding on the previous value of the first position of the sequence to be decoded.
  • the source decoding value of one or more bits of the sequence (as shown in Figure 6c), or, the F bits are on the F frozen bits after the natural order of the fourth bit sequence (as shown in Figure 6c ).
  • the third bit sequence being on the first bit of the fourth bit sequence may include: the scrambled third bit sequence is on the first bit of the fourth bit sequence.
  • the scrambled third bit sequence may be obtained according to the scrambled sequence and the third bit sequence.
  • the first bit may be the last C information bits in the natural order of the fourth bit sequence.
  • channel decoding can be performed on the information bits at the beginning of the natural order, and scrambling the information bits of the fourth bit sequence will not increase the code rate of channel coding, and can improve system performance.
  • source decoding errors at multiple original source bit positions will affect channel decoding at these bit positions, thereby further increasing the detection probability of erroneous decoding results.
  • the sending end performs channel coding on the fourth bit sequence to obtain a fifth bit sequence.
  • the length of the fifth bit sequence is N, and N is an integer greater than 0.
  • channel coding is performed on the fourth bit sequence to obtain a fifth bit sequence.
  • the fourth bit sequence is determined according to the second bit sequence and the third bit sequence
  • the third bit sequence is one or more bits in the original source bit sequence, directly using part of the original source bit and the original source bit
  • the source coding result of the sequence is channel coded, which can improve the system performance.
  • the sending end may use polar code coding to perform channel coding to obtain the fifth bit sequence
  • the receiving end may use polar code coding to perform channel decoding, which is not limited in this application.
  • the sending end sends the fifth bit sequence.
  • the sending end may send the fifth bit sequence through the channel.
  • the receiving end receives the sequence to be decoded.
  • the length of the sequence to be decoded is N, and N is an integer greater than 0.
  • the length of the sequence to be decoded is N, where N is an integer greater than 0, and the sequence to be decoded is a sequence of the fifth bit sequence transmitted through the channel.
  • the fifth bit sequence is the channel coding value of the fourth bit sequence
  • the first position of the sequence to be decoded corresponds to the first bit of the fourth bit sequence
  • the third bit sequence is at the first position of the fourth bit sequence.
  • the third bit sequence is C bits in the first bit sequence
  • the length of the first bit sequence is A
  • A is an integer greater than
  • C is an integer greater than 0 and less than or equal to A.
  • the second position of the sequence to be decoded corresponds to the B information bits occupied by the second bit sequence in the fourth bit sequence
  • the second bit sequence is the information source code value of the first bit sequence
  • the length of the second bit sequence is B
  • B is an integer greater than 0.
  • E is an integer greater than or equal to 0
  • F is an integer greater than or equal to 0.
  • E is equal to C and F is equal to 0, and the first bit of the fourth bit sequence satisfies the first principle.
  • the first principle may include: the first bit is in the natural sequence of the fourth bit sequence on the first E information bits.
  • the first bit satisfies the second principle
  • the second principle may include: the first bit of the fourth bit sequence and the first position of the sequence to be decoded
  • the source decoding value of one or more bits of the third bit sequence can be obtained, or, the first The bits are located on the last C frozen bits in the natural order of the fourth bit sequence.
  • the receiving end performs channel decoding on the sequence to be decoded to obtain a channel decoding value of the fourth bit sequence.
  • the channel decoding value of the fourth bit sequence may include the channel decoding value of the second bit sequence and the channel decoding value of the third bit sequence.
  • the receiving end may perform channel decoding on the sequence to be decoded in a bit-by-bit decoding manner to obtain a channel decoding value of the fourth bit sequence.
  • the receiving end may use a list, a stack, and other types of decoding structures.
  • the above S506 may include the following steps 1 to 4.
  • the channel decoding mode may be an SCL mode, and the number of lists is L, where L is an integer greater than 0.
  • the initial value of c u_total is equal to 0. If c u_total is less than C, the receiving end may perform the following first source channel operation (including the following steps 1 to 3).
  • step 1 the receiving end performs channel decoding on the value of the n-m bit to the n-th bit of the sequence to be decoded, and obtains a first decoding result.
  • the n-mth to nth bits include at least one position in the first position and/or b positions in the second position, n-m is an integer greater than 0, m is an integer greater than 0, and b is greater than 0 and an integer less than or equal to B.
  • the first decoding result may include channel decoding values of b bits of the second bit sequence and/or channel decoding values of at least one bit of the third bit sequence.
  • the receiving end can perform channel decoding on the value of at least one bit in the first position and the value of at least one bit in the second position, and the first decoding result can include at least one of the second bit sequence The channel decoding value of the bit and the channel decoding value of at least one bit of the third bit sequence.
  • the value of m can be equal to each time the first source channel operation is performed or not equal.
  • the receiving end starts channel decoding from the value of the first bit of the sequence to be decoded.
  • the number of first decoding results may be one or more, for example, it may be L.
  • bits n-m to n may include bits 1 to 28.
  • the 11th to 20th digits may be the first 10 digits in the second position
  • the 28th digit may be the first digit in the first position.
  • Perform channel decoding on the value on the 1st bit to the value on the 28th bit, and the obtained first decoding result includes the channel decoding value of the first 10 bits of the second bit sequence and the first 10 bits of the third bit sequence Bit channel decoding value.
  • bits n-m to n may include bits 1 to 28.
  • the 11th to 20th bits may be the 10 bits in the first position
  • the 28th bit may be the first bit in the second position.
  • Perform channel decoding on the value on the 1st bit to the value on the 28th bit, and the obtained first decoding result includes the channel decoding value of the first 10 bits of the third bit sequence and the first 10 bits of the second bit sequence Bit channel decoding value.
  • the n-mth to nth bits may include the 1st to 28th bits.
  • the 11th to 15th digits may be the first 5 digits in the first position
  • the 16th digit may be the first digit in the second position.
  • Perform channel decoding on the value on the 1st bit to the 16th bit, and the obtained first decoding result includes the channel decoding value of the first 5 bits of the third bit sequence and the first 5 bits of the second bit sequence Bit channel decoding value.
  • the arrangement order of the third bit sequence and the second bit sequence is c 1 b 1 c 2 b 2 c 3 b 3 c 4 b 4 c 5 b 5 c 6 b 6 c 7 b 7 c 8 b 8 c
  • the value on the nth bit to the value on the nth bit can include c 1 b 1
  • the value on the nth bit to the value on the nth bit is channeled
  • the obtained first decoding result includes the channel decoding value of c 1 bits of the third bit sequence and the channel decoding value of b 1 bits of the second bit sequence.
  • the The value on the nth bit to the value on the nth bit may include c 1 c 2 b 1 , perform channel decoding on the value on the nth bit to the nth bit, and the obtained first decoding result includes the third The channel decoding value of c 1 c 2 bits of the bit sequence and the channel decoding value of b 1 bit of the second bit sequence.
  • This application does not enumerate one by one.
  • the receiving end performs the first source channel operation for the second time, and continues to perform step 1 on the sequence to be decoded shown in FIG.
  • the 29th to the 32nd can be the 2nd to the 5th in the first position.
  • Channel decoding is performed on the value at the 29th bit to the value at the 32nd bit, and the obtained first decoding result includes the channel decoding values of the second bit to the fifth bit of the third bit sequence.
  • the receiving end executes the first source channel operation for the second time, and continues to perform step 1 on the sequence to be decoded shown in FIG. 6d, and bits n-m to n may include bits 29 to 37.
  • the 29th to the 37th may be the 2nd to the 10th in the second position.
  • Channel decoding is performed on the value at the 29th bit to the value at the 37th bit, and the obtained first decoding result includes the channel decoding values of the 2nd bit to the 10th bit of the second bit sequence.
  • the receiving end performs the first source channel operation for the second time, and continues to perform step 1 on the sequence to be decoded shown in FIG. 6g, and bits n-m to n may include bits 17 to 20.
  • the 17th to 20th digits may be the 2nd to 4th digits in the second position.
  • Channel decoding is performed on the value on the 17th bit to the value on the 20th bit, and the obtained first decoding result includes channel decoding values of the second bit to the fourth bit of the second bit sequence.
  • channel decoding can be performed on the value from the first bit to the 20th bit of the sequence to be decoded, which is not limited in this application , the above are only examples provided by this application.
  • the above step 1 may be performed by the channel decoder at the receiving end, and the channel decoder may feed back the obtained channel decoding values of the b bits of the second bit sequence to the channel decoder, thereby performing the following Step 2 above.
  • Step 2 The receiving end performs source decoding on the channel decoding values corresponding to the b bits of the second bit sequence to obtain source decoding values of the c t bits of the third bit sequence.
  • c t is an integer greater than 0 and less than or equal to C.
  • source decoding is performed on the channel decoding values of the first 10 bits of the second bit sequence to obtain source decoding values of c t bits of the third bit sequence, for example, c t is equal to 5.
  • the receiving end may not perform step 2, but directly perform step 3 below.
  • the receiving end can source the channel decoding values corresponding to the second bit to the tenth bit of the second bit sequence Decoding, to obtain the information source decoding value of c t bits of the third bit sequence, for example, c t is equal to 9.
  • the receiving end can source the channel decoding values corresponding to the second bit to the fourth bit of the second bit sequence Decoding, to obtain the source decoding value of c t bits of the third bit sequence, for example, c t is equal to 4.
  • the above step 2 may be performed by the source decoder at the receiving end, and the source decoder may feed back the obtained source decoding values of c t bits of the third bit sequence to the channel decoder .
  • Step 3 According to the source decoding value of c u bits of the third bit sequence and the channel decoding value of c u bits corresponding to the natural sequence of the third bit sequence, the receiving end determines the value to be decoded based on l decoding paths The value on the n+1th bit to the Nth bit of the code sequence continues to perform the first source channel operation, and counts c u into c u_total .
  • c u is an integer greater than 0, and l is an integer less than or equal to L.
  • the receiver can decode the information of the first bit according to the source decoding value of the first 5 bits of the third bit sequence (obtained in step 2 by executing the first source channel operation for the first time).
  • step 2 If it is necessary to continue to perform the first source channel operation for the second time in combination with the sequence to be decoded shown in FIG.
  • step 3 shown in FIG. 6b and FIG. 6g is similar to that in FIG. 6b , and will not be repeated here.
  • step 3 may include the following steps 3a to 3c.
  • Step 3a the receiving end traverses L decoding paths, and determines the source decoding values of c u bits of the third bit sequence corresponding to the first decoding path and the natural sequence of the third bit sequence corresponding to the first decoding path Whether the channel decoding values of the corresponding c u bits are the same.
  • the first decoding path may be one of the L decoding paths.
  • c u 2
  • the source decoding value of the 5th bit and the 6th bit of the third bit sequence is compared with the channel decoding value of the 5th bit and the 6th bit of the third bit sequence, If the source decoding value of the fifth bit of the third bit sequence is the same as the channel decoding value of the fifth bit of the third bit sequence, and the source decoding value of the sixth bit of the third bit sequence is the same as the third bit If the channel decoding value of the sixth bit of the sequence is the same, it is determined to be the same; otherwise, it is determined to be different.
  • Step 3b if not the same, the receiving end determines to delete the first decoding path, and terminates the operation of the first source channel based on the first decoding path.
  • Step 3c if they are the same, the receiving end may determine that the 1 decoding path includes the first decoding path.
  • the receiving end can continue to execute the first signal based on the value of the n+1th bit to the Nth bit of the sequence to be decoded based on the first decoding path.
  • Source channel operation
  • Step 4 if c u_total is equal to C and n is less than N, continue to perform channel decoding from the value at bit n+1 to the value at bit N of the sequence to be decoded.
  • the source decoding value of the last bit of the third bit sequence corresponds to the channel decoding value of the last bit of the natural order of the third bit sequence
  • the above step 3 has been performed, and the decoding Perform channel decoding on all bits of the sequence, and continue to perform channel decoding on the values of the remaining positions in the sequence to be decoded to complete the channel decoding.
  • B channel decoding values of the second bit sequence and C channel decoding values of the third bit sequence are obtained.
  • the receiving end obtains the source decoding value of the third bit sequence according to the channel decoding value of the second bit sequence, and combines the source decoding value of the third bit sequence with the source decoding value of the third bit sequence
  • the above S506 may include the following steps 5 to 9.
  • the initial value of c t_total is equal to 0. If c t_total is less than C, the receiving end may perform the following second source channel operation (including the following steps 5 to 6).
  • the channel decoding mode may be an SCL mode, and the number of lists is L, where L is an integer greater than 0.
  • Step 5 The receiving end performs channel decoding on the value at the n-mth bit to the nth bit of the sequence to be decoded to obtain a second decoding result.
  • bit n+1 is one of the first positions, n-m is an integer greater than 0, and m is an integer greater than 0.
  • bits n-m to nth of the sequence to be decoded may include bits 1 to 37.
  • bits n-m to nth of the sequence to be decoded may include bits 1 to 20.
  • bits n-m to nth of the sequence to be decoded may include bits 21 to 37.
  • the second decoding result may include channel decoding values of the b bits of the second bit sequence.
  • the second decoding result may further include a channel decoding value of at least one bit of the third bit sequence.
  • channel decoding is performed on the value at the first bit to the value at the 37th bit to obtain the channel decoding value of the first 20 bits of the second bit sequence.
  • channel decoding is performed on the value at the first bit to the value at the 20th bit to obtain the channel decoding value of the first 10 bits of the second bit sequence.
  • channel decoding is performed on the value on the 21st bit to the value on the 37th bit to obtain the 11th bit of the second bit sequence
  • the above step 5 may be performed by the channel decoder at the receiving end, and the channel decoder may feed back the obtained channel decoding values of the b bits of the second bit sequence to the channel decoder, thereby performing the following Step 6 above.
  • Step 6 The receiver performs source decoding on the channel decoding values of b bits in the second bit sequence to obtain the source decoding values of c t bits in the third bit sequence, and counts c t into c t_total .
  • c t is an integer greater than 0 and less than or equal to C.
  • the source decoding values of the c t bits of the third bit sequence are sequentially used as the channel decoding values of the values at the c t positions in the first position of the sequence to be decoded.
  • the source decoding values of the c t bits of the third bit sequence obtained by performing the second source channel operation each time can be directly used as the c t positions in the first positions of the sequence to be decoded in turn
  • the second source channel operation is performed for the first time, and the source decoding value of the 5 bits of the third bit sequence is obtained in step 6, and it is used as the first bit to the first bit in the first position of the sequence to be decoded Channel-decoded value of the value on 5 bits.
  • the second source channel operation is performed for the first time, and the source decoding value of the 3 bits of the third bit sequence is obtained in step 6, and it is used as the 6th to 8th bits in the first position of the sequence to be decoded
  • the channel-decoded value of the value in bit is used as the 6th to 8th bits in the first position of the sequence to be decoded
  • the receiving end performs source decoding on the channel decoding values of the first 20 bits of the second bit sequence to obtain the source decoding values of 10 bits of the third bit sequence, c t_total equals 10. And the obtained 10-bit source decoding values of the third bit sequence are sequentially used as channel decoding values of the values at the 10 positions in the first position of the sequence to be decoded.
  • the receiving end performs source decoding on the channel decoding values of the first 10 bits of the second bit sequence to obtain the source information of the first bit to the fifth bit of the third bit sequence Decoded value, c t_total is equal to 5. And the obtained source decoding values of the first bit to the fifth bit of the third bit sequence are sequentially used as the 21st to 25th bits of the sequence to be decoded (that is, the first 5 bits in the first position) The channel decoded value of the value above.
  • the above step 6 may be performed by the source decoder at the receiving end, and the source decoder may feed back the obtained source decoding values of c t bits of the third bit sequence to the channel decoder .
  • Step 7 if c t_total is greater than 0 and less than C, the receiving end continues to perform the second source channel operation from the value on bit n+1 to the value on bit N of the sequence to be decoded.
  • step 6 If the c t_total obtained in step 6 is greater than 0 and less than C, the receiving end continues to perform the above steps 5 to 6 for the value of the remaining bits of the sequence to be decoded.
  • c t_total is equal to 5 (refer to the above step 6), and the receiving end continues to decode the value from the 21st bit to the Nth bit of the sequence to be decoded Execute the second source channel operation.
  • the above step 7 may include: if c t_total is greater than 0 and less than C, the receiving end determines the n+1th sequence to be decoded based on the l decoding path according to the path metric values corresponding to the L decoding paths respectively The value on the bit to the value on the Nth bit continues to perform the second source channel operation.
  • the receiving end obtains the source decoding value of the third bit sequence by performing source decoding on the channel decoding value of the second bit sequence, and uses the source decoding value of the third bit sequence as the sequence to be decoded The channel-decoded value of the value in the first position.
  • the channel decoding value of the second bit sequence is wrong, it will cause the source decoding value of the third bit sequence to be wrong, which will lead to decoding when the sequence to be decoded decodes the first position.
  • the errors of the current decoding path will accumulate, which will cause the path metric value corresponding to the current decoding path to change, so that decoding errors can be easily identified and the success rate of decoding can be improved.
  • Step 9 if c t_total is equal to C and n is less than N, the receiving end continues to perform channel decoding from the value at bit n+1 to the value at bit N of the sequence to be decoded.
  • c t_total is equal to 10 (refer to step 6 above), and the receiving end continues to Perform channel decoding.
  • c t_total is equal to 10 (refer to the above step 6), and the receiving end continues to Perform channel decoding.
  • B channel decoding values of the second bit sequence and C channel decoding values of the third bit sequence are obtained.
  • the above step 9 may include: if c t_total is equal to C and n is less than N, the receiving end may determine the nth sequence to be decoded based on the l decoding path according to the path metric values corresponding to the L decoding paths The value on the +1 bit to the value on the Nth bit continue to perform the second source channel operation.
  • the foregoing S506 may include the foregoing steps 1 to 4, and the foregoing steps 5 to 9.
  • the first bit includes E information bits and F freezing bits.
  • E is greater than 0 and F is greater than 0
  • the above steps 1 to 4 and the above steps 5 to 9 can be used in combination.
  • the receiving end can judge whether the decoding result is accurate by comparing the source decoding value of the third bit sequence with the channel decoding value of the third bit sequence, and can compare the source decoding value of the third bit sequence
  • the path metric value corresponding to the decoding path can be used to judge whether the decoding result is accurate, which can increase the probability of the wrong decoding result being detected, thereby improving the system performance.
  • 0 when channel decoding is performed on the value at the third position of the sequence to be decoded, 0 may be assigned directly.
  • the third position corresponds to the ordinary frozen bits of the fourth bit sequence
  • the ordinary frozen bits refer to frozen bits that do not belong to the first bits.
  • the first bit to the tenth bit, and the twenty-first bit to the twenty-seventh bit of the fourth bit sequence may all be referred to as ordinary frozen bits.
  • the receiving end if it performs channel decoding on the value of the last bit of the sequence to be decoded, it can recover the first bit sequence with a length greater than A through the obtained channel decoding value of the second bit sequence If the source decoding value of , then there is an error in the current decoding path, delete the current decoding path.
  • the original length of the first bit is A
  • the source decoding value of the first bit sequence whose length is greater than A is restored through the partial channel decoding value of the second bit sequence.
  • the receiving end may output the channel decoding value of the fourth bit sequence with the highest possibility as the channel decoding.
  • the receiving end performs source decoding on the channel decoding value of the second bit sequence to obtain the source decoding value of the first bit sequence.
  • the channel decoding value of the second bit sequence is obtained from the channel decoding value of the fourth bit sequence, and information source decoding is performed to obtain the information source decoding value of the first bit sequence.
  • the sender Based on the communication method shown in Figure 5, the sender combines the source coding result of the first bit sequence with a part of the bit sequence in the first bit sequence to obtain the input of the channel coding, that is, the fourth bit sequence, for the fourth bit sequence
  • the receiving end can use part of the bit sequence in the first bit sequence for joint decoding in the process of decoding the sequence to be decoded, which can accurately determine the wrong decoding result and improve the error rate. The probability of the code result being detected, thereby improving the system performance.
  • FIG. 9 is a schematic flowchart of another communication method provided in the embodiment of the present application.
  • the communication method includes the following steps:
  • the sending end performs source coding on the first bit sequence to obtain a second bit sequence.
  • the sending end obtains a fourth bit sequence according to the second bit sequence and the third bit sequence.
  • the sending end performs channel coding on the fourth bit sequence to obtain a fifth bit sequence.
  • the sending end sends the fifth bit sequence.
  • S901 to S904 in the communication method shown in FIG. 9 can refer to the examples in FIG. 6b, FIG. 6d, and FIG. 6g in the communication method shown in FIG. example.
  • the receiving end receives the sequence to be decoded.
  • the sequence to be decoded includes the sequence of the fifth bit sequence after channel transmission, the fifth bit sequence is the channel coding value of the fourth bit sequence, the first position of the sequence to be decoded and the first position of the fourth bit sequence One bit corresponds, the third bit sequence is on the first bit of the fourth bit sequence, the first bit of the fourth bit sequence includes C information bits, and the third bit sequence is C information bits in the first bit sequence bits, the length of the first bit sequence is A, A is an integer greater than 0, and C is an integer greater than 0 and less than or equal to A.
  • the second position of the sequence to be decoded corresponds to the B information bits occupied by the second bit sequence in the fourth bit sequence, the second bit sequence is the information source code value of the first bit sequence, and the length of the second bit sequence is B, B is an integer greater than 0.
  • B is an integer greater than 0.
  • the receiving end performs the qth iterative channel decoding on the sequence to be decoded to obtain the channel decoding value of the fourth bit sequence.
  • q is an integer greater than 0.
  • the channel decoding value of the fourth bit sequence may include the channel decoding value of the second bit sequence and the channel decoding value of the third bit sequence.
  • the receiving end performs g-th source decoding on the channel decoding value of the second bit sequence to obtain the source decoding value of the first bit sequence.
  • g is an integer greater than 0. G and q may not be equal.
  • the receiving end may perform source decoding once on the channel decoding value of the second bit sequence after performing multiple iterations of channel decoding on the sequence to be decoded.
  • the information source decoding value of the first bit sequence may include the information source decoding value of the third bit sequence.
  • the third bit sequence is one or more bits in the first bit sequence
  • the information source decoding value of the first bit sequence includes the information source decoding value of all bits of the first bit sequence, thus including the third The source decoding value of the C bits of the bit sequence.
  • the above S907 may include: in the case that the channel decoding value of the fourth bit sequence passes the channel verification, the receiving end performs the gth signal on the channel decoding value of the second bit sequence Source decoding to obtain the source decoding value of the first bit sequence.
  • the gth source decoding is performed on the channel decoding value of the second bit sequence to obtain the first bit The source decoding value of the sequence, so as to obtain the source decoding value of the third bit sequence.
  • the receiving end When the channel decoding value of the third bit sequence is the same as the source decoding value of the third bit sequence or q is equal to Q, the receiving end outputs the source decoding value of the first bit sequence.
  • Q is the maximum number of iterations, and Q is an integer greater than 0.
  • the receiving end can compare the channel decoding value of the third bit sequence with the source decoding value of the third bit sequence, and if they are the same, output the source decoding value of the first bit sequence. Or when the number of channel decoding iterations reaches the maximum number of iterations, the source decoding value of the first bit sequence is output.
  • the communication method shown in FIG. 9 may further include: when the channel decoding value of the third bit sequence is different from the source decoding value of the third bit sequence and q is less than Q , performing q+s iterative channel decoding on the sequence to be decoded, and performing g+t source decoding on the channel decoding value of the second bit sequence in the q+s iterative channel decoding result.
  • s is an integer greater than 0, and t is an integer greater than 0.
  • the receiving end may perform source decoding once on the channel decoding value of the second bit sequence after performing multiple iterations of channel decoding on the sequence to be decoded.
  • the receiving end when the channel decoding value of the third bit sequence is the same as the source decoding value of the third bit sequence and/or q is equal to Q, the receiving end outputs the source decoding result and stops performing channel decoding and source decoding.
  • the receiving end selects the channel decoding value of the second bit sequence from the result of the qth iterative channel decoding of the sequence to be decoded and performs the gth source decoding to obtain the first
  • the source decoding value of the bit sequence until the channel decoding value of the third bit sequence is the same as the source decoding value of the third bit sequence or reaches the maximum number of iterations, output the source decoding of the first bit sequence
  • the value can increase the probability of detecting wrong decoding results, thereby improving system performance.
  • FIG. 10-12 are schematic diagrams of several block error rate performances provided by the embodiments of the present application.
  • FIG. 10 and FIG. 11 are schematic diagrams of block error rate (block error rate, BLER) performance of the communication method shown in FIG. 5 above.
  • FIG. 12 is a schematic diagram of the block error rate performance of the communication method shown in FIG. 9 above.
  • FIG. 10 is a block error rate performance comparison between the communication method shown in FIG. 5 and two separate decoding schemes.
  • the channel coding does not contain cyclic redundancy check (cyclic redundancy check, CRC) bits, and the original information source is used for verification.
  • CRC cyclic redundancy check
  • the channel coding does not use CRC bits, and in the other separate decoding scheme, the channel coding uses 8-bit channel CRC bit. It can be seen that in most signal-to-noise ratio (SNR) ranges, the communication method shown in FIG. 5 can bring a gain of about 0.1-0.2 dB.
  • SNR signal-to-noise ratio
  • Fig. 11 is a block error rate performance comparison between the communication method shown in Fig. 5 and two separate decoding schemes.
  • the channel coding does not contain cyclic redundancy check bits, and the original information source is used for checking.
  • two separate decoding schemes of arithmetic code and polar code are investigated. In one separate decoding scheme, the channel coding does not use CRC bits, and in the other separate decoding scheme, the channel coding uses 8-bit channel CRC bit. It can be seen from Fig. 11 that in most SNR ranges, the decoding performance of the communication method shown in Fig. 5 is better, and the communication method shown in Fig. 5 can bring a gain of about 0.1-0.2 dB.
  • FIG. 12 is a block error rate performance comparison between the communication method shown in FIG. 9 and two separate decoding schemes.
  • the list size of the first-order Markov source and polar code decoding is 32 as an example.
  • the channel coding does not contain CRC bits, and the original information source is used for verification.
  • two separate decoding schemes of arithmetic code and polar code are investigated. In one separate decoding scheme, the channel coding does not use CRC bits, and in the other separate decoding scheme, the channel coding uses 8-bit channel CRC bit. It can be seen from Fig. 12 that the decoding performance of the communication method shown in Fig. 9 is better in most SNR ranges, and the communication method shown in Fig. 9 can bring a gain of about 0.1-0.2 dB.
  • mapping part of the original source bits to the corresponding positions of the polar code channel code to assist decoding as described in Figures 5 to 12 above the design idea of this application can also be extended to other directions. For example, in protocol flow design, a certain These fields are mapped to some bits of channel coding.
  • the mapping here may be the mapping of some fields of the physical layer to some bits of the physical layer, or the mapping of some fields of the upper layer to some bits of the physical layer, which is not limited in this application.
  • the present application can be applied to the data mapping from the (media access control, MAC) layer to the physical layer, and the transport block (transport block, TB) transmitted from the MAC layer to the physical layer can perform, for example, cyclic redundancy check (CRC) encoding, Segmentation and other operations, and then channel coding, this application does not limit these operations.
  • Channel coding can adopt polar code coding.
  • PDU protocol data unit
  • the reserved (reserved, R) field in the sub header (sub header) in the MAC PDU is mapped to the information bits corresponding to the bits involved in the channel coding, and if it is decoded to the corresponding position, the current decoding path is based on The decoding result of the previous bit is inconsistent with the original mapping value of the R field, indicating that the current path decoding error occurs, and this decoding path can be deleted.
  • LCID logical channel identify
  • the value of LCID is basically fixed.
  • CCCH common control channel
  • the LCID value can be mapped to the channel coding information bit, so that during channel decoding, it is possible to determine whether there is a decoding error in the current decoding path by comparing the decoding result of the actual mapped bit with the original mapping value, and determine whether the current decoding needs to be deleted. path.
  • mapping schemes are just examples of the expansion of the application's ideas. In fact, this application is not limited to the above mapping schemes. Other types of fields, such as new fields in subsequent standards, can be used Similar mappings and methods are similar, which will not be described in this application.
  • mapping method can make the current decoding result and the value of the original mapping field cross-checked when decoding the polar code, so that we can delete the wrong path in advance and improve the decoding performance.
  • the communication method provided by the embodiment of the present application is described in detail above with reference to FIG. 5-FIG. 12 .
  • the communication device provided by the embodiment of the present application will be described in detail below with reference to FIG. 13-FIG. 14 .
  • FIG. 13 is a schematic structural diagram of a communication device that can be used to implement the communication method provided by the embodiment of the present application.
  • the communication device 1300 may be a receiving end or a sending end, and may also be a chip applied to the receiving end or the sending end or other components with corresponding functions.
  • a communication device 1300 may include a processor 1301 .
  • the communication device 1300 may further include one or more of a memory 1302 and a transceiver 1303 .
  • the processor 1301 may be coupled with one or more of the memory 1302 and the transceiver 1303, such as through a communication bus, or the processor 1301 may be used alone.
  • the components of the communication device 1300 are specifically introduced below in conjunction with FIG. 13 :
  • the processor 1301 is the control center of the communication device 1300, and may be one processor, or may be a general term for multiple processing elements.
  • the processor 1301 is one or more central processing units (central processing unit, CPU), may also be a specific integrated circuit (application specific integrated circuit, ASIC), or is configured to implement one or more An integrated circuit, for example: one or more microprocessors (digital signal processor, DSP), or, one or more field programmable gate arrays (field programmable gate array, FPGA).
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • An integrated circuit for example: one or more microprocessors (digital signal processor, DSP), or, one or more field programmable gate arrays (field programmable gate array, FPGA).
  • the processor 1301 can execute various functions of the communication device 1300 by running or executing software programs stored in the memory 1302 and calling data stored in the memory 1302 .
  • the processor 1301 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG. 13 .
  • the communication device 1300 may also include multiple processors, for example, the processor 1301 and the processor 1304 shown in FIG. 13 .
  • processors can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU).
  • a processor herein may refer to one or more communication devices, circuits, and/or processing cores for processing data (eg, computer program instructions).
  • the memory 1302 may be a read-only memory (read-only memory, ROM) or other types of static storage communication devices that can store static information and instructions, or a random access memory (random access memory, RAM) that can store information and other types of dynamic storage communication devices for instructions, and can also be electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or Other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disc storage media or other magnetic storage communication devices, or can be used to carry or store desired information in the form of instructions or data structures program code and any other medium that can be accessed by a computer, but not limited to.
  • the memory 1302 may be integrated with the processor 1301, or exist independently, and be coupled with the processor 1301 through an input/output port (not shown in FIG. 13 ) of the communication device 1300, which is not specifically limited in this embodiment of the present application.
  • the input port can be used to realize the receiving function performed by the receiving end or the sending end in any of the above method embodiments
  • the output port can be used to realize the sending function performed by the receiving end or the sending end in any of the above method embodiments. Function.
  • the memory 1302 may be used to store a software program for executing the solution of the present application, and the execution is controlled by the processor 1301 .
  • the processor 1301 may be used to store a software program for executing the solution of the present application, and the execution is controlled by the processor 1301 .
  • the transceiver 1303 is used for communication with other communication devices.
  • the transceiver 1303 may be used to communicate with the sending end.
  • the transceiver 1303 may be used to communicate with the receiving end.
  • the transceiver 1303 may include a receiver and a transmitter (not separately shown in FIG. 13 ). Wherein, the receiver is used to realize the receiving function, and the transmitter is used to realize the sending function.
  • the transceiver 1303 may be integrated with the processor 1301, or may exist independently, and be coupled to the processor 1301 through an input/output port (not shown in FIG. 13 ) of the communication device 1300, which is not specifically limited in this embodiment of the present application. .
  • the structure of the communication device 1300 shown in FIG. 13 does not constitute a limitation to the communication device, and an actual communication device may include more or less components than shown in the figure, or combine certain components, or Different component arrangements.
  • the above-mentioned actions of the receiving end in FIGS. 5-12 can be executed by the processor 1301 in the communication device 1300 shown in FIG. 13 calling the application program code stored in the memory 1302 to instruct the receiving end to execute, which is not limited in this embodiment.
  • the communication device 1300 can execute any one or more possible design methods involved in the sending end in the above method embodiments; when the communication device is the receiving end, the communication device 1300 can execute the above method Any one or more possible design modes involved in the receiving end in the embodiments.
  • FIG. 14 is a schematic structural diagram of another communication device provided by an embodiment of the present application. For ease of illustration, FIG. 14 only shows the main components of the communication device.
  • the communication device 1400 includes a transceiver module 1401 and a processing module 1402 .
  • the communication device 1400 may be the sending end or the receiving end in the foregoing method embodiments.
  • the transceiving module 1401 which may also be referred to as a transceiving unit, is configured to implement the transceiving function performed by the transmitting end or the receiving end in any of the above method embodiments.
  • the transceiver module 1401 may include a receiving module and a sending module (not shown in FIG. 14 ). Wherein, the receiving module is used for receiving data and/or signaling from other devices; the sending module is used for sending data and/or signaling to other devices. This application does not specifically limit the specific implementation manner of the transceiver module.
  • the transceiver module may be composed of a transceiver circuit, a transceiver, a transceiver or a communication interface.
  • the processing module 1402 may be configured to implement the processing function performed by the sending end or the receiving end in any of the above method embodiments.
  • the processing module 1402 may be a processor.
  • the communication device 1400 is presented in the form of dividing various functional modules in an integrated manner.
  • a “module” here may refer to a specific ASIC, a circuit, a processor and a memory executing one or more software or firmware programs, an integrated logic circuit, and/or other devices that can provide the functions described above.
  • the communication device 1400 can take the form of the communication device 1300 shown in FIG. 13 .
  • the processor 1301 in the communication device 1300 shown in FIG. 13 may invoke the computer-executed instructions stored in the memory 1302, so that the communication method in the above method embodiment is executed.
  • the function/implementation process of the transceiver module 1401 and the processing module 1402 in FIG. 14 can be implemented by the processor 1301 in the communication device 1300 shown in FIG. 13 invoking computer-executed instructions stored in the memory 1302.
  • the function/implementation process of the processing module 1402 in FIG. 14 can be realized by the processor 1301 in the communication device 1300 shown in FIG. /The implementation process may be implemented by the transceiver 1303 in the communication device 1300 shown in FIG. 13 .
  • the communication device 1400 provided in this embodiment can execute the above-mentioned communication method, the technical effect it can obtain can refer to the above-mentioned method embodiment, and details are not repeated here.
  • the communication device 1400 shown in FIG. 14 is applicable to the communication system shown in FIG. 1 , and performs the function of the sending end in the communication method shown in FIG. 5 or FIG. 9 .
  • the processing module 1402 is configured to perform information source coding on the first bit sequence to obtain a second bit sequence.
  • the length of the first bit sequence is A
  • A is an integer greater than
  • the length of the second bit sequence is B
  • B is an integer greater than 0.
  • the processing module 1402 is further configured to obtain a fourth bit sequence according to the second bit sequence and the third bit sequence.
  • the processing module 1402 is further configured to perform channel coding on the fourth bit sequence to obtain a fifth bit sequence.
  • the length of the fifth bit sequence is N, and N is an integer greater than 0.
  • the transceiver module 1401 is configured to send the fifth bit sequence.
  • the communication device 1400 may further include a storage module (not shown in FIG. 14 ), where programs or instructions are stored in the storage module.
  • the processing module 1402 executes the program or instruction
  • the communication device 1400 can execute the function of the sending end in the communication method shown in FIG. 5 or FIG. 9 .
  • the communication device 1400 may be a sending end, or a chip (system) or other components or components that may be arranged at the sending end, which is not limited in this application.
  • the communication device 1400 shown in FIG. 14 may be applicable to the communication system shown in FIG. 1 , and perform the function of the receiving end in the communication method shown in FIG. 5 .
  • the transceiver module 1401 is configured to receive the sequence to be decoded.
  • the length of the sequence to be decoded is N, N is an integer greater than 0, the sequence to be decoded is the sequence after channel transmission of the fifth bit sequence, the fifth bit sequence is the channel coding value of the fourth bit sequence, and the to-be-decoded sequence
  • the first position of the code sequence corresponds to the first bit of the fourth bit sequence
  • the third bit sequence is on the first bit of the fourth bit sequence
  • E is an integer greater than or equal to
  • F is an integer greater than or equal to
  • the third bit sequence is the C bits in the first bit sequence
  • the first bit sequence The length is A, A is an integer greater than 0, and C is an integer greater than 0 and less than or equal to A.
  • the second position of the sequence to be decoded corresponds to the B information bits occupied by the second bit sequence in the fourth bit sequence, the second bit sequence is the information source code value of the first bit sequence, and the length of the second bit sequence is B, B is an integer greater than 0.
  • the channel decoding value of the fourth bit sequence includes the channel decoding value of the second bit sequence and the channel decoding value of the third bit sequence, and the length of the fourth bit sequence is N.
  • the processing module 1402 is configured to perform channel decoding on the sequence to be decoded to obtain a channel decoding value of the fourth bit sequence.
  • the channel decoding value of the fourth bit sequence includes the channel decoding value of the second bit sequence and the channel decoding value of the third bit sequence, and the length of the fourth bit sequence is N.
  • the processing module 1402 is further configured to perform source decoding on the channel decoding value of the second bit sequence to obtain the source decoding value of the first bit sequence.
  • the communication device 1400 may further include a storage module (not shown in FIG. 14 ), where programs or instructions are stored in the storage module.
  • the processing module 1402 executes the program or instruction
  • the communication device 1400 can execute the function of the receiving end in the communication method shown in FIG. 5 .
  • the communication device 1400 may be a receiving end, or a chip (system) or other components or components that may be arranged at the receiving end, which is not limited in this application.
  • the communication device 1400 shown in FIG. 14 may be applicable to the communication system shown in FIG. 1 , and perform the function of the receiving end in the communication method shown in FIG. 9 .
  • the transceiver module 1401 is configured to receive the sequence to be decoded.
  • the sequence to be decoded is the sequence after the fifth bit sequence is transmitted through the channel
  • the fifth bit sequence is the channel coding value of the fourth bit sequence
  • the first position of the sequence to be decoded and the first bit of the fourth bit sequence
  • the third bit sequence is on the first bit of the fourth bit sequence
  • the first bit of the fourth bit sequence includes C information bits
  • the third bit sequence is C bits in the first bit sequence
  • the third bit sequence is C bits in the first bit sequence
  • the third bit sequence is C bits in the first bit sequence.
  • the length of a bit sequence is A, A is an integer greater than 0, and C is an integer greater than 0 and less than or equal to A.
  • the second position of the sequence to be decoded corresponds to the B information bits occupied by the second bit sequence in the fourth bit sequence, the second bit sequence is the information source code value of the first bit sequence, and the length of the second bit sequence is B, B is an integer greater than 0.
  • the processing module 1402 is configured to perform the qth iterative channel decoding on the sequence to be decoded to obtain the channel decoding value of the fourth bit sequence.
  • q is an integer greater than 0, and the channel decoding value of the fourth bit sequence includes the channel decoding value of the second bit sequence and the channel decoding value of the third bit sequence.
  • the processing module 1402 is further configured to perform g-th information source decoding on the channel decoding value of the second bit sequence to obtain the information source decoding value of the first bit sequence.
  • g is an integer greater than 0, and the information source decoding value of the first bit sequence includes the information source decoding value of the third bit sequence.
  • the processing module 1402 is further configured to output the source decoding value of the first bit sequence when the channel decoding value of the third bit sequence is the same as the source decoding value of the third bit sequence or q is equal to Q.
  • Q is the maximum number of iterations, and Q is an integer greater than 0.
  • the communication device 1400 may further include a storage module (not shown in FIG. 14 ), where programs or instructions are stored in the storage module.
  • the processing module 1402 executes the program or instruction
  • the communication device 1400 can execute the function of the receiving end in the communication method shown in FIG. 9 .
  • the communication device 1400 may be a receiving end, or a chip (system) or other components or components that may be arranged at the receiving end, which is not limited in this application.
  • An embodiment of the present application provides a communication system.
  • the communication system includes: a sending end and a receiving end.
  • the sending end is used to execute the actions of the sending end in the above method embodiments, and the specific execution method and process may refer to the above method embodiments, which will not be repeated here.
  • the receiving end is used to execute the actions of the receiving end in the foregoing method embodiments.
  • An embodiment of the present application provides a chip system, and the chip system includes a logic circuit and an input/output port.
  • the logic circuit can be used to realize the processing function involved in the communication method provided by the embodiment of the application
  • the input/output port can be used for the sending and receiving function involved in the communication method provided in the embodiment of the application.
  • the input port can be used to realize the receiving function involved in the communication method provided by the embodiment of the present application
  • the output port can be used to realize the sending function involved in the communication method provided in the embodiment of the present application.
  • the processor in the communication device 1300 may be used to perform, for example but not limited to, baseband related processing, and the transceiver in the communication device 1300 may be used to perform, for example but not limited to, radio frequency transceiving.
  • the above-mentioned devices may be respectively arranged on independent chips, or at least partly or all of them may be arranged on the same chip.
  • processors can be further divided into analog baseband processors and digital baseband processors.
  • the analog baseband processor can be integrated with the transceiver on the same chip, and the digital baseband processor can be set on an independent chip.
  • a digital baseband processor can be combined with a variety of application processors (such as but not limited to graphics processors, multimedia processors, etc.) integrated on the same chip.
  • application processors such as but not limited to graphics processors, multimedia processors, etc.
  • Such a chip can be called a system chip (system on chip). Whether each device is independently arranged on different chips or integrated and arranged on one or more chips often depends on the specific needs of product design.
  • the embodiment of the present invention does not limit the specific implementation forms of the foregoing devices.
  • the chip system further includes a memory, where the memory is used to store program instructions and data for implementing functions involved in the communication method provided by the embodiments of the present application.
  • the system-on-a-chip may consist of chips, or may include chips and other discrete devices.
  • the embodiment of the present application provides a computer-readable storage medium, the computer-readable storage medium stores a computer program or instruction, and when the computer program or instruction is run on a computer, the communication method provided in the embodiment of the present application is executed.
  • An embodiment of the present application provides a computer program product, and the computer program product includes: a computer program or an instruction, and when the computer program or instruction is run on a computer, the communication method provided in the embodiment of the present application is executed.
  • the processor in the embodiment of the present application may be a central processing unit (central processing unit, CPU), and the processor may also be other general-purpose processors, digital signal processors (digital signal processor, DSP), dedicated integrated Circuit (application specific integrated circuit, ASIC), off-the-shelf programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.
  • the memory in the embodiments of the present application may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories.
  • the non-volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically programmable Erases programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory can be random access memory (RAM), which acts as external cache memory.
  • RAM random access memory
  • static random access memory static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory Access memory
  • SDRAM synchronous dynamic random access memory
  • double data rate synchronous dynamic random access memory double data rate SDRAM, DDR SDRAM
  • enhanced synchronous dynamic random access memory enhanced SDRAM, ESDRAM
  • serial link DRAM SLDRAM
  • direct memory bus random access memory direct rambus RAM, DR RAM
  • the above-mentioned embodiments may be implemented in whole or in part by software, hardware (such as circuits), firmware, or other arbitrary combinations.
  • the above-described embodiments may be implemented in whole or in part in the form of computer program products.
  • the computer program product comprises one or more computer instructions or computer programs. When the computer instruction or computer program is loaded or executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part.
  • the computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server or data center by wired (such as infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center that includes one or more sets of available media.
  • the available media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media.
  • the semiconductor medium may be a solid state drive.
  • At least one means one or more, and “multiple” means two or more.
  • At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • at least one item (piece) of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .
  • sequence numbers of the above-mentioned processes do not mean the order of execution, and the execution order of the processes should be determined by their functions and internal logic, and should not be used in the embodiments of the present application.
  • the implementation process constitutes any limitation.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

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Abstract

本申请提供一种通信方法及装置，提高错误的译码结果被检出的概率，从而提高系统性能。该方法包括：对第一比特序列进行信源编码，得到第二比特序列，根据第二比特序列和第三比特序列，得到第四比特序列，对第四比特序列进行信道编码，得到第五比特序列，发送第五比特序列。其中，第三比特序列为第一比特序列中的C个比特，第四比特序列包括一个或多个信息比特、和一个或多个冻结比特，第二比特序列处于第四比特序列的B个信息比特位上，第三比特序列处于第四比特序列的第一比特位上，第一比特位包括E个信息比特位和F个冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数。

Description

通信方法及装置
本申请要求于2021年10月21日提交国家知识产权局、申请号为202111228364.1、申请名称为“通信方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种通信方法及装置。
背景技术
分离信源信道编码(separate source channel coding，SSCC)即将信源编码和信道编码分别进行，优点是设计简单、通用性好，缺点是没有充分利用各自的优势不能准确地判断出错误的译码结果，降低了系统性能。
发明内容
本申请提供一种通信方法及装置，能够准确地判断出错误的译码结果，可以提高错误的译码结果被检出的概率，从而提高系统性能。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种通信方法。该通信方法包括：对第一比特序列进行信源编码，得到第二比特序列，根据第二比特序列和第三比特序列，得到第四比特序列，对第四比特序列进行信道编码，得到第五比特序列，发送第五比特序列。其中，第一比特序列的长度为A，A为大于0的整数，第二比特序列的长度为B，B为大于0的整数。第三比特序列为第一比特序列中的C个比特，C为大于0且小于或等于A的整数，第四比特序列的长度为N，N为大于0的整数，第四比特序列包括一个或多个信息比特、和一个或多个冻结比特，第二比特序列处于第四比特序列的B个信息比特位上，第三比特序列处于第四比特序列的第一比特位上，第一比特位包括E个信息比特位和F个冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数。第五比特序列的长度为N，N为大于0的整数。
基于第一方面所示的通信方法，发送端将第一比特序列的信源编码结果和第一比特序列中的部分比特序列结合，获得信道编码的输入，即第四比特序列，对第四比特序列进行信道编码，接收端在对待译码序列进行译码的过程中，可以采用第一比特序列中的部分比特序列进行联合译码，该联合信源信道编码方案(joint source channel coding，JSCC)，可以准确地判断出错误的译码结果，可以提高错误的译码结果被检出的概率，从而提高系统性能。
在一种可能的设计方式中，E等于C且F等于0，第一比特位满足第一原则，第一原则可以包括：第一比特位处于第四比特序列的自然序靠前的E个信息比特位上。如此，可以使接收端在译码过程中更早地判断译码结果是否准确，若译码结果存在错误，可以更早停止译码。
在一种可能的设计方式中，F等于C且E等于0，第一比特位满足第二原则，第二原则可以包括：第四比特序列的第一比特位与待译码序列的第一位置对应，对待译码序列的第一位置的之前的值进行信道译码的结果进行信源译码后，能够获得第三比特序列的一个或多个比特的信源译码值，或者，第一比特位处于第四比特序列的自然序靠后的F个冻结比特位上。如此，可以使在译码过程中，若第二比特序列的信道译码值有错误，使当前译码路径的错误进行积累，从而译码错误很容易被甄别出来，可以提高译码成功率。
在一种可能的设计方式中，上述第三比特序列为第一比特序列中的C个比特，可以包括：第三比特序列为第一比特序列中的自然序靠前的C个比特。如此，选择第一比特序列中的自然序靠前的比特作为第三比特序列，可以使在译码过程中更早参与校验，可以更早地判断译码结果是否准确，若译码结果存在错误，可以更早停止译码，提高系统性能。
在一种可能的设计方式中，上述第三比特序列处于第四比特序列的第一比特位上，可以包括：加扰后的第三比特序列处于第四比特序列的第一比特位上，加扰后的第三比特序列是根据加扰序列和第三比特序列获得的。如此，对第四比特序列的信息比特进行加扰不会增大信道编码的码率，可以提高系统性能
第二方面，提供一种通信方法。该通信方法包括：接收待译码序列，对待译码序列进行信道译码，得到第四比特序列的信道译码值，对第二比特序列的信道译码值进行信源译码，得到第一比特序列的信源译码值。
其中，待译码序列的长度为N，N为大于0的整数，待译码序列为第五比特序列经过信道传输后的序列，第五比特序列为第四比特序列的信道编码值，待译码序列的第一位置与第四比特序列的第一比特位对应，第三比特序列处于第四比特序列的第一比特位上，第四比特序列的第一比特位包括E个信息比特位和F个冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数，第三比特序列为第一比特序列中的C个比特，第一比特序列的长度为A，A为大于0的整数，C为大于0且小于或等于A的整数。待译码序列的第二位置与第四比特序列的中第二比特序列占用的B个信息比特位对应，第二比特序列为第一比特序列的信源编码值，第二比特序列的长度为B，B为大于0的整数。第四比特序列的信道译码值包括第二比特序列的信道译码值和第三比特序列的信道译码值，第四比特序列的长度为N。
在一种可能的设计方式中，E等于C且F等于0，第四比特序列的第一比特位满足第一原则，第一原则可以包括：第一比特位处于第四比特序列的自然序靠前的E个信息比特位上。
在一种可能的设计方式中，上述对待译码序列进行信道译码，得到第四比特序列的信道译码值，可以包括：信道译码的方式为串行抵消列表(successive cancellation list，SCL)译码方式，列表的数量为L，L为大于0的整数，c u_total的初始值等于0，若c u_total小于C，则执行下述第一信源信道操作。
对待译码序列的第n-m位上的值至第n位上的值进行信道译码，得到第一译码结果。其中，第n-m位至第n位可以包括第一位置中的至少一个位置和/或第二位置中的b个位置，n-m为大于0的整数，m为大于0的整数，第一译码结果可以包括第二比特 序列的b个比特的信道译码值和/或第三比特序列的至少一个比特的信道译码值，b为大于0且小于或等于B的整数。
对第二比特序列的b个比特对应的信道译码值进行信源译码，得到第三比特序列的c t个比特的信源译码值。其中，c t为大于0且小于或等于C的整数。
根据第三比特序列的c u个比特的信源译码值与第三比特序列的自然序对应的c u个比特的信道译码值，确定基于l条译码路径对待译码序列的第n+1位上的值至第N位上的值继续执行第一信源信道操作，并将c u计入c u_total。其中，c u为大于0的整数，l为小于或等于L的整数。
若c u_total等于C且n小于N，则对待译码序列的第n+1位上的值至第N位上的值继续进行信道译码。
在一种可能的设计方式中，上述根据第三比特序列的c u个比特的信源译码值与第三比特序列的自然序对应的c u个比特的信道译码值，确定基于l条译码路径对待译码序列的第n+1位上的值至第N位上的值继续执行第一信源信道操作，并将c u计入c u_total，可以包括：遍历L条译码路径，确定第一译码路径对应的第三比特序列c u个比特的信源译码值与第一译码路径对应的第三比特序列的自然序对应的c u个比特的信道译码值是否相同，并将c u计入c u_total。其中，第一译码路径为L条译码路径中的一个。若不相同，则确定删除第一译码路径，终止基于第一译码路径的第一信源信道操作。若相同，则确定l条译码路径包括第一译码路径。
在一种可能的设计方式中，F等于C且E等于0，第一比特位满足第二原则，第二原则包括：第四比特序列的第一比特位与待译码序列的第一位置对应，对待译码序列的第一位置的之前的值进行信道译码的结果进行信源译码后，能够获得第三比特序列的一个或多个比特的信源译码值，或者，第一比特位处于第四比特序列的自然序靠后的F个冻结比特位上。
在一种可能的设计方式中，上述对待译码序列进行信道译码，得到第四比特序列的信道译码值，包括：信道译码的方式为串行抵消列表SCL译码方式，列表的数量为L，L为大于0的整数，c t_total的初始值等于0，若c t_total小于C，则执行下述第二信源信道操作。
对待译码序列的第n-m位上的值至第n位上的值进行信道译码，得到第二译码结果。其中，第n+1位为第一位置中的一个位置，n-m为大于0的整数，m为大于0的整数，第二译码结果包括第二比特序列的b个比特的信道译码值。
对第二比特序列的b个比特的信道译码值进行信源译码，得到第三比特序列的c t个比特的信源译码值，并将c t计入c t_total。其中，c t为大于0且小于或等于C的整数，第三比特序列的c t个比特的信源译码值依次作为待译码序列的第一位置中的c t个位置上的信道译码值。
若c t_total大于0且小于C，对待译码序列的第n+1位上的值至第N位上的值继续执行第二信源信道操作。
若c t_total等于C且n小于N，对待译码序列的第n+1位上的值至第N位上的值继续进行信道译码。
在一种可能的设计方式中，上述第三比特序列为第一比特序列中的C个比特，可 以包括：第三比特序列为第一比特序列中的自然序靠前的C个比特。
此外，第二方面所述的通信方法的技术效果可以参考第一方面所述的通信方法的技术效果，此处不再赘述。
第三方面，提供一种通信方法。该通信方法包括：接收待译码序列。对待译码序列进行第q次迭代信道译码，获得第四比特序列的信道译码值。对第二比特序列的信道译码值进行第g次信源译码，得到第一比特序列的信源译码值。在第三比特序列的信道译码值与第三比特序列的信源译码值相同或q等于Q的情况下，输出第一比特序列的信源译码值。其中，q为大于0的整数，第四比特序列的信道译码值包括第二比特序列的信道译码值和第三比特序列的信道译码值。Q为最大迭代次数，Q为大于0的整数。
其中，待译码序列包括为第五比特序列经过信道传输后的序列，第五比特序列为第四比特序列的信道编码值，待译码序列的第一位置与第四比特序列的第一比特位对应，第三比特序列处于第四比特序列的第一比特位上，第四比特序列的第一比特位包括C个信息比特位，第三比特序列为第一比特序列中的C个比特，第一比特序列的长度为A，A为大于0的整数，C为大于0且小于或等于A的整数。待译码序列的第二位置与第四比特序列的中第二比特序列占用的B个信息比特位对应，第二比特序列为第一比特序列的信源编码值，第二比特序列的长度为B，B为大于0的整数。
在一种可能的设计方式中，第三方面提供的通信方法，还可以包括：在第三比特序列的信道译码值与第三比特序列的信源译码值不相同且q小于Q的情况下，对待译码序列进行第q+s次迭代信道译码，对第q+s次迭代信道译码结果中的第二比特序列的信道译码值进行第g+t次信源译码。其中，s为大于0的整数，t为大于0的整数。
在一种可能的设计方式中，上述对第二比特序列的信道译码值进行第g次信源译码，得到第一比特序列的信源译码值，可以包括：在第四比特序列的信道译码值通过信道校验的情况下，对第二比特序列的信道译码值进行第g次信源译码，得到第一比特序列的信源译码值。
此外，第三方面所述的通信方法的技术效果可以参考第一方面所述的通信方法的技术效果，此处不再赘述。
第四方面，提供一种通信装置。该通信装置包括：处理模块和收发模块。
其中，处理模块，用于对第一比特序列进行信源编码，得到第二比特序列。其中，第一比特序列的长度为A，A为大于0的整数，第二比特序列的长度为B，B为大于0的整数。
处理模块，还用于根据第二比特序列和第三比特序列，得到第四比特序列。其中，第三比特序列为第一比特序列中的C个比特，C为大于0且小于或等于A的整数，第四比特序列的长度为N，N为大于0的整数，第四比特序列包括一个或多个信息比特、和一个或多个冻结比特，第二比特序列处于第四比特序列的B个信息比特位上，第三比特序列处于第四比特序列的第一比特位上，第一比特位包括E个信息比特位和F个冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数。
处理模块，还用于对第四比特序列进行信道编码，得到第五比特序列。其中，第五比特序列的长度为N，N为大于0的整数。
收发模块，用于发送第五比特序列。
在一种可能的设计方式中，E等于C且F等于0，第一比特位满足第一原则，第一原则可以包括：第一比特位处于第四比特序列的自然序靠前的E个信息比特位上。
在一种可能的设计方式中，F等于C且E等于0，第一比特位满足第二原则，第二原则可以包括：第四比特序列的第一比特位与待译码序列的第一位置对应，对待译码序列的第一位置的之前的值进行信道译码的结果进行信源译码后，能够获得第三比特序列的一个或多个比特的信源译码值，或者，第一比特位处于第四比特序列的自然序靠后的F个冻结比特位上。
在一种可能的设计方式中，上述第三比特序列为第一比特序列中的C个比特，可以包括：第三比特序列为第一比特序列中的自然序靠前的C个比特。
在一种可能的设计方式中，上述第三比特序列处于第四比特序列的第一比特位上，可以包括：加扰后的第三比特序列处于第四比特序列的第一比特位上，加扰后的第三比特序列是根据加扰序列和第三比特序列获得的。
需要说明的是，第四方面所述的收发模块可以包括接收模块和发送模块。其中，接收模块用于接收来自接收端的数据和/或信令；发送模块用于向接收端发送数据和/或信令。本申请对于收发模块的具体实现方式，不做具体限定。
可选地，第四方面所述的通信装置还可以包括存储模块，该存储模块存储有程序或指令。当处理模块执行该程序或指令时，使得第四方面所述的通信装置可以执行第一方面所述的方法。
需要说明的是，第四方面所述的通信装置可以是发送端(例如网络设备、或终端设备等)，也可以是可设置于发送端的芯片(系统)或其他部件或组件，本申请对此不做限定。
此外，第四方面所述的通信装置的技术效果可以参考第一方面中任一种可能的实现方式所述的通信方法的技术效果，此处不再赘述。
第五方面，提供一种通信装置。该通信装置包括：处理模块和收发模块。
其中，收发模块，用于接收待译码序列。其中，待译码序列的长度为N，N为大于0的整数，待译码序列为第五比特序列经过信道传输后的序列，第五比特序列为第四比特序列的信道编码值，待译码序列的第一位置与第四比特序列的第一比特位对应，第三比特序列处于第四比特序列的第一比特位上，第四比特序列的第一比特位包括E个信息比特位和F个冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数，第三比特序列为第一比特序列中的C个比特，第一比特序列的长度为A，A为大于0的整数，C为大于0且小于或等于A的整数。待译码序列的第二位置与第四比特序列的中第二比特序列占用的B个信息比特位对应，第二比特序列为第一比特序列的信源编码值，第二比特序列的长度为B，B为大于0的整数。
处理模块，用于对待译码序列进行信道译码，得到第四比特序列的信道译码值。其中，第四比特序列的信道译码值包括第二比特序列的信道译码值和第三比特序列的信道译码值，第四比特序列的长度为N。
处理模块，还用于对第二比特序列的信道译码值进行信源译码，得到第一比特序列的信源译码值。
在一种可能的设计方式中，E等于C且F等于0，第四比特序列的第一比特位满足第一原则，第一原则可以包括：第一比特位处于第四比特序列的自然序靠前的E个信息比特位上。
在一种可能的设计方式中，信道译码的方式为串行抵消列表SCL译码方式，列表的数量为L，L为大于0的整数，c u_total的初始值等于0，若c u_total小于C，则处理模块，还用于执行下述第一信源信道操作。
处理模块，还用于对待译码序列的第n-m位上的值至第n位上的值进行信道译码，得到第一译码结果。其中，第n-m位至第n位可以包括第一位置中的至少一个位置和/或第二位置中的b个位置，n-m为大于0的整数，m为大于0的整数，第一译码结果可以包括第二比特序列的b个比特的信道译码值和/或第三比特序列的至少一个比特的信道译码值，b为大于0且小于或等于B的整数。
处理模块，还用于对第二比特序列的b个比特对应的信道译码值进行信源译码，得到第三比特序列的c t个比特的信源译码值。其中，c t为大于0且小于或等于C的整数。
处理模块，还用于根据第三比特序列的c u个比特的信源译码值与第三比特序列的自然序对应的c u个比特的信道译码值，确定基于l条译码路径对待译码序列的第n+1位上的值至第N位上的值继续执行第一信源信道操作，并将c u计入c u_total。其中，c u为大于0的整数，l为小于或等于L的整数。
若c u_total等于C且n小于N，则处理模块，还用于对待译码序列的第n+1位上的值至第N位上的值继续进行信道译码。
在一种可能的设计方式中，处理模块，还用于遍历L条译码路径，确定第一译码路径对应的第三比特序列c u个比特的信源译码值与第一译码路径对应的第三比特序列的自然序对应的c u个比特的信道译码值是否相同，并将c u计入c u_total。其中，第一译码路径为L条译码路径中的一个。
若不相同，则处理模块，还用于确定删除第一译码路径，终止基于第一译码路径的第一信源信道操作。
若相同，则处理模块，还用于确定l条译码路径包括第一译码路径。
在一种可能的设计方式中，F等于C且E等于0，第一比特位满足第二原则，第二原则包括：第四比特序列的第一比特位与待译码序列的第一位置对应，对待译码序列的第一位置的之前的值进行信道译码的结果进行信源译码后，能够获得第三比特序列的一个或多个比特的信源译码值，或者，第一比特位处于第四比特序列的自然序靠后的F个冻结比特位上。
在一种可能的设计方式中，信道译码的方式为串行抵消列表SCL译码方式，列表的数量为L，L为大于0的整数，c t_total的初始值等于0，若c t_total小于C，则处理模块，还用于执行下述第二信源信道操作。
处理模块，还用于对待译码序列的第n-m位上的值至第n位上的值进行信道译码，得到第二译码结果。其中，第n+1位为第一位置中的一个位置，n-m为大于0的整数，m为大于0的整数，第二译码结果包括第二比特序列的b个比特的信道译码值。
处理模块，还用于对第二比特序列的b个比特的信道译码值进行信源译码，得到 第三比特序列的c t个比特的信源译码值，并将c t计入c t_total。其中，c t为大于0且小于或等于C的整数，第三比特序列的c t个比特的信源译码值依次作为待译码序列的第一位置中的c t个位置上的信道译码值。
若c t_total大于0且小于C，处理模块，还用于对待译码序列的第n+1位上的值至第N位上的值继续执行第二信源信道操作。
若c t_total等于C且n小于N，处理模块，还用于对待译码序列的第n+1位上的值至第N位上的值继续进行信道译码。
在一种可能的设计方式中，上述第三比特序列为第一比特序列中的C个比特，可以包括：第三比特序列为第一比特序列中的自然序靠前的C个比特。
需要说明的是，第五方面所述的收发模块可以包括接收模块和发送模块。其中，接收模块用于接收来自发送端的数据和/或信令；发送模块用于向发送端发送数据和/或信令。本申请对于收发模块的具体实现方式，不做具体限定。
可选地，第五方面所述的通信装置还可以包括存储模块，该存储模块存储有程序或指令。当处理模块执行该程序或指令时，使得第五方面所述的通信装置可以执行第二方面所述的方法。
需要说明的是，第五方面所述的通信装置可以是接收端(例如网络设备、或终端设备等)，也可以是可设置于接收端的芯片(系统)或其他部件或组件，本申请对此不做限定。
此外，第五方面所述的通信装置的技术效果可以参考第二方面中任一种可能的实现方式所述的通信方法的技术效果，此处不再赘述。
第六方面，提供一种通信装置。该通信装置包括：处理模块和收发模块。
其中，收发模块，用于接收待译码序列。其中，待译码序列包括为第五比特序列经过信道传输后的序列，第五比特序列为第四比特序列的信道编码值，待译码序列的第一位置与第四比特序列的第一比特位对应，第三比特序列处于第四比特序列的第一比特位上，第四比特序列的第一比特位包括C个信息比特位，第三比特序列为第一比特序列中的C个比特，第一比特序列的长度为A，A为大于0的整数，C为大于0且小于或等于A的整数。待译码序列的第二位置与第四比特序列的中第二比特序列占用的B个信息比特位对应，第二比特序列为第一比特序列的信源编码值，第二比特序列的长度为B，B为大于0的整数。
处理模块，用于对待译码序列进行第q次迭代信道译码，获得第四比特序列的信道译码值。其中，q为大于0的整数，第四比特序列的信道译码值包括第二比特序列的信道译码值和第三比特序列的信道译码值。
处理模块，还用于对第二比特序列的信道译码值进行第g次信源译码，得到第一比特序列的信源译码值。其中，g为大于0的整数，第一比特序列的信源译码值包括第三比特序列的信源译码值。
处理模块，还用于在第三比特序列的信道译码值与第三比特序列的信源译码值相同或q等于Q的情况下，输出第一比特序列的信源译码值。其中，Q为最大迭代次数，Q为大于0的整数。
在一种可能的设计方式中，在第三比特序列的信道译码值与第三比特序列的信源 译码值不相同且q小于Q的情况下，处理模块，还用于对待译码序列进行第q+s次迭代信道译码，对第q+s次迭代信道译码结果中的第二比特序列的信道译码值进行第g+t次信源译码。其中，s为大于0的整数，t为大于0的整数。
在一种可能的设计方式中，在第四比特序列的信道译码值通过信道校验的情况下，处理模块，还用于对第二比特序列的信道译码值进行第g次信源译码，得到第一比特序列的信源译码值。
需要说明的是，第六方面所述的收发模块可以包括接收模块和发送模块。其中，接收模块用于接收来自发送端的数据和/或信令；发送模块用于向发送端发送数据和/或信令。本申请对于收发模块的具体实现方式，不做具体限定。
可选地，第六方面所述的通信装置还可以包括存储模块，该存储模块存储有程序或指令。当处理模块执行该程序或指令时，使得第六方面所述的通信装置可以执行第三方面所述的方法。
需要说明的是，第六方面所述的通信装置可以是接收端(例如网络设备、或终端设备等)，也可以是可设置于接收端的芯片(系统)或其他部件或组件，本申请对此不做限定。
此外，第六方面所述的通信装置的技术效果可以参考第三方面中任一种可能的实现方式所述的通信方法的技术效果，此处不再赘述。
第七方面，提供一种通信装置。该通信装置包括：处理器，该处理器与存储器耦合，存储器用于存储计算机程序。
处理器用于执行存储器中存储的计算机程序，以使得如第一方面至第三方面中任一种可能的实现方式所述的通信方法被执行。
在一种可能的设计中，第七方面所述的通信装置还可以包括收发器。该收发器可以为收发电路或输入/输出端口。所述收发器可以用于该通信装置与其他设备通信。
需要说明的是，输入端口可用于实现第一方面至第三方面所涉及的接收功能，输出端口可用于实现第一方面至第三方面所涉及的发送功能。
在本申请中，第七方面所述的通信装置可以为发送端、或接收端，或者设置于发送端、或接收端内部的芯片或芯片系统。
此外，第七方面所述的通信装置的技术效果可以参考第一方面至第三方面中任一种实现方式所述的通信方法的技术效果，此处不再赘述。
第八方面，提供一种通信系统。该通信系统包括如第四方面所述的通信装置和如第五方面所述的通信装置。或者，该通信系统包括如第四方面所述的通信装置和如第六方面所述的通信装置。
或者，该通信系统包括如第四方面所述的用于实现如第一方面所述方法的通信装置、如第五方面所述的用于实现如第二方面所述方法的通信装置。或者，该通信系统包括如第四方面所述的用于实现如第一方面所述方法的通信装置、如第六方面所述的用于实现如第三方面所述方法的通信装置。
第九方面，提供了一种芯片系统，该芯片系统包括逻辑电路和输入/输出端口。其中，逻辑电路用于实现第一方面至第三方面所涉及的处理功能，输入/输出端口用于实现第一方面至第三方面所涉及的收发功能。具体地，输入端口可用于实现第一方面至 第三方面所涉及的接收功能，输出端口可用于实现第一方面至第三方面所涉及的发送功能。
在一种可能的设计中，该芯片系统还包括存储器，该存储器用于存储实现第一方面至第三方面所涉及功能的程序指令和数据。
该芯片系统，可以由芯片构成，也可以包含芯片和其他分立器件。
第十方面，提供一种计算机可读存储介质，该计算机可读存储介质存储有计算机程序或指令；当该计算机程序或指令在计算机上运行时，使得第一方面至第三方面中任意一种可能的实现方式所述的通信方法被执行。
第十一方面，提供一种计算机程序产品，包括计算机程序或指令，当该计算机程序或指令在计算机上运行时，使得第一方面至第三方面中任意一种可能的实现方式所述的通信方法被执行。
本申请上述各方面提供的实现方式中，发送端将第一比特序列的信源编码结果和第一比特序列中的部分比特序列结合，获得信道编码的输入，即第四比特序列，对第四比特序列进行信道编码，接收端在对待译码序列进行译码的过程中，可以采用第一比特序列中的部分比特序列进行联合译码，该联合信源信道编码方案，可以准确地判断出错误的译码结果，可以提高错误的译码结果被检出的概率，从而提高系统性能。
附图说明
图1为本申请实施例提供的通信系统的架构示意图；
图2为本申请实施例提供的一种信号处理过程示意图；
图3为本申请实施例提供的一种极化码的构造示意图；
图4为本申请实施例提供的一种译码树的示意图；
图5为本申请实施例提供的一种通信方法的流程示意图；
图6a至图6g为本申请实施例提供多种编码示意图；
图7为本申请实施例提供的一种变长到定长的信源编码示意图；
图8为本申请实施例提供的一种信源编码值的示意图；
图9为本申请实施例提供的另一种通信方法的流程示意图；
图10为本申请实施例提供的一种误块率性能的示意图；
图11为本申请实施例提供的另一种误块率性能的示意图；
图12为本申请实施例提供的又一种误块率性能的示意图；
图13为本申请实施例提供的一种通信装置的结构示意图；
图14为本申请实施例提供的另一种通信装置的结构示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例的技术方案可以应用于各种通信系统，例如无线保真(wireless fidelity，WiFi)系统，车到任意物体(vehicle to everything，V2X)通信系统、设备间(device-to-device，D2D)通信系统、车联网通信系统、第4代(4th generation，4G)移动通信系统，如长期演进(long term evolution，LTE)系统、全球互联微波接入(worldwide interoperability for microwave access，WiMAX)通信系统、第五代(5th generation，5G)移动通信系统，如新空口(new radio，NR)系统，以及未来的通信系 统，如第六代(6th generation，6G)移动通信系统等。
本申请将围绕可包括多个设备、组件、模块等的系统来呈现各个方面、实施例或特征。应当理解和明白的是，各个系统可以包括另外的设备、组件、模块等，并且/或者可以并不包括结合附图讨论的所有设备、组件、模块等。此外，还可以使用这些方案的组合。
另外，在本申请实施例中，“示例地”、“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用示例的一词旨在以具体方式呈现概念。
本申请实施例描述的网络架构以及业务场景是为了更加清楚的说明本申请实施例的技术方案，并不构成对于本申请实施例提供的技术方案的限定，本领域普通技术人员可知，随着网络架构的演变和新业务场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
为便于理解本申请实施例，首先以图1中示出的通信系统为例详细说明适用于本申请实施例的通信系统。示例性地，图1为本申请实施例提供的通信方法所适用的一种通信系统的架构示意图。
如图1所示，该通信系统包括终端设备和网络设备。其中，终端设备的数量可以为一个或多个，网络设备的数量可以为一个或多个。
其中，上述终端设备为接入上述通信系统，且具有无线收发功能的终端或可设置于该终端的芯片或芯片系统。该终端设备也可以称为用户设备(user equipment，UE)、用户装置、接入终端、用户单元、用户站、移动站、移动台(mobile station，MS)、远方站、远程终端、移动设备、用户终端、终端、终端单元、终端站、终端装置、无线通信设备、用户代理或用户装置。
例如，本申请的实施例中的终端设备可以是手机(mobile phone)、无线数据卡、个人数字助理(personal digital assistant，PDA)电脑、膝上型电脑(laptop computer)、平板电脑(Pad)、无人机、带无线收发功能的电脑、机器类型通信(machine type communication，MTC)终端、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、物联网(internet of things，IoT)终端设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端(例如游戏机、智能电视、智能音箱、智能冰箱和健身器材等)、车载终端、具有终端功能的RSU。接入终端可以是蜂窝电话(cellular phone)、无绳电话、会话启动协议(session initiation protocol，SIP)电话、无线本地环路(wireless local loop，WLL)站、个人数字助理(personal digital assistant，PDA)、具有无线通信功能的手持设备(handset)、计算设备或连接到无线调制解调器的其它处理设备、可穿戴设备等。
又例如，本申请实施例中的终端设备可以是智慧物流中的快递终端(例如可监控货物车辆位置的设备、可监控货物温湿度的设备等)、智慧农业中的无线终端(例如可收集禽畜的相关数据的可穿戴设备等)、智慧建筑中的无线终端(例如智慧电梯、消防 监测设备、以及智能电表等)、智能医疗中的无线终端(例如可监测人或动物的生理状态的可穿戴设备)、智能交通中的无线终端(例如智能公交车、智能车辆、共享单车、充电桩监测设备、智能红绿灯、以及智能监控以及智能停车设备等)、智能零售中的无线终端(例如自动售货机、自助结账机、以及无人便利店等)。又例如，本申请的终端设备可以是作为一个或多个部件或者单元而内置于车辆的车载模块、车载模组、车载部件、车载芯片或者车载单元，车辆通过内置的所述车载模块、车载模组、车载部件、车载芯片或者车载单元可以实施本申请提供的方法。
其中，上述网络设备为位于上述通信系统的网络侧，且具有无线收发功能的设备或可设置于该设备的芯片或芯片系统。该网络设备包括但不限于：无线保真(wireless fidelity，Wi-Fi)系统中的接入点(access point，AP)，如家庭网关、路由器、服务器、交换机、网桥等，演进型节点B(evolved Node B，eNB)、无线网络控制器(radio network controller，RNC)、节点B(Node B，NB)、基站控制器(base station controller，BSC)、基站收发台(base transceiver station，BTS)、家庭基站(例如，home evolved NodeB，或home Node B，HNB)、基带单元(baseband unit，BBU)，无线中继节点、无线回传节点、传输点(transmission and reception point，TRP或者transmission point，TP)等，还可以为5G，如，新空口(new radio，NR)系统中的gNB，或，传输点(TRP或TP)，5G系统中的基站的一个或一组(包括多个天线面板)天线面板，或者，还可以为构成gNB或传输点的网络节点，如基带单元(BBU)，或，分布式单元(distributed unit，DU)、具有基站功能的路边单元(road side unit，RSU)等，或者还可以为卫星、或未来各种形式的基站。
需要注意的是，本申请实施例提供的通信系统中，一个设备(包括网络设备或终端设备)向另一个设备(包括网络设备或终端设备)发送比特序列时，发送比特序列的设备是发送端，接收比特序列的设备是接收端。其中，发送端可以实现信号的生成、发送等功能，可以是网络设备或终端设备；接收端可以实现信号的获取、处理等功能，可以是网络设备或终端设备。以图1为例，在上行通信场景中，网络设备向终端设备发送比特序列，网络设备为发送端，终端设备为接收端；在下行通信场景中，终端设备向网络设备发送比特序列，终端设备为发送端，网络设备为接收端。当然，本申请实施例提供的通信系统中，一个终端设备可以向另一个终端设备发送比特序列，在此情况下发送端和接收端为不同的终端设备；一个网络设备可以向另一个网络设备发送比特序列，在此情况下发送端和接收端为不同的网络设备。
在一些可能的情况下，发送端可以作为接收端，实现信号的获取、处理等功能；接收端可以作为发送端，实现信号的生成、发送等功能。换言之，一个物理设备可以是发送端，或者可以是接收端，或者既是发送端又是接收端。
应当指出的是，本申请实施例中的方案还可以应用于其他通信系统中，相应的名称也可以用其他通信系统中的对应功能的名称进行替代。
应理解，图1仅为便于理解而示例的简化示意图，该通信系统中还可以包括其他网络设备，和/或，其他终端设备，图1中未予以画出。
在发送端与接收端的信号处理过程中，如图2所示，在发送端，信源依次经过信源编码、信道编码、速率匹配和调制后在信道上向接收端发送，接收端接收到发送端 发送的信号后，依次通过解调、解速率匹配、信道译码和信源译码获得信宿。本申请实施例提供的方法具体可以应用于发送端的信源信道联合编码、接收端的信源信道联合译码过程中。本申请实施例提供的方法具体可以由发送端的编码器、接收端的译码器执行，编码器可以包括信源编码器和信道编码器，译码器可以包括信源译码器和信道译码器。
为了使得本申请实施例更加清楚，以下对与本申请实施例相关的部分内容以及概念作统一介绍。
第一，极化码(polar codes)：
极化码是一种线性分组码，是一种能够被严格证明“达到”信道容量的信道编码方案，具有高性能、较低复杂度等特点，可用于5G控制信道增强移动宽带(enhanced mobile broadband，eMBB)场景。
极化码的编码过程为
Figure PCTCN2022120645-appb-000001
其中，
Figure PCTCN2022120645-appb-000002
为码长为N的Polar码，
Figure PCTCN2022120645-appb-000003
是一个长度为N的二进制行向量，
Figure PCTCN2022120645-appb-000004
是编码矩阵，
Figure PCTCN2022120645-appb-000005
代表F的克罗内克幂(Kronecker power)，定义为
Figure PCTCN2022120645-appb-000006
其中，
Figure PCTCN2022120645-appb-000007
在极化码的编码过程中，
Figure PCTCN2022120645-appb-000008
的一部分比特可以用来携带信息，携带信息的比特可以称为信息比特或信息位，这些信息比特构成信息比特集合，信息比特的索引集合可以记作A。
Figure PCTCN2022120645-appb-000009
的另外一部分比特可以被设置为接收端和发送端预先约定的固定值，称为固定比特或冻结比特(frozen bits)或冻结位。其中，冻结比特可以被设置为0，也可以被设置为任意由接收端和发送端预先约定的固定值，不予限制。
如图3所示，以行矢量u为(U1，U2，U3，U4，U5，U6，U7，U8)，生成矩阵为8×8的矩阵为例，行矢量u经过生成矩阵，编码后的比特可以为向量(X1，X2，X3，X4，X5，X6，X7，X8)。其中，可以将可靠度较高的极化信道对应的比特位映射信息比特，将可靠度较低的极化信道对应的比特位映射冻结比特。例如，行矢量u的各个比特位中，可以将{u1,u2,u3,u5}确定为冻结比特的位置，将{u4,u6,u7,u8}确定为信息比特的位置，进而将长度为4的待编码的信息向量映射在信息比特的位置。
当冻结比特被设置为0时，极化码的编码过程可以简化为
Figure PCTCN2022120645-appb-000010
其中，u A是
Figure PCTCN2022120645-appb-000011
中的信息比特集合，其长度记作K。G N(A)是G N中由信息比特的索引集合A中的索引对应的行组成的子矩阵，G N(A)是一个K×N的矩阵。Polar码的构造过程实际上是集合A的选取过程，该选取过程的准确性决定Polar码的性能。
串行抵消(successive cancellation，SC)译码(decoding)是一种极化码译码算法。一个码长为N＝2 n的码可以对应一个n层的二叉译码码树，SC译码可以被描述为在译码码树上搜寻正确译码路径的过程。图4示出了图3所示的极化码的译码树。从译码码树的根节点(例如S＝3层的译码节点)开始往下逐一比特译码，直到最底层(例如S＝0层的译码节点)。
在有限码长下，极化码使用SC译码的性能并不理想。基于SC译码可得到改进算法，例如串行抵消列表译码、串行抵消堆栈译码等，基于SC译码的改进算法可通过在译码过程中同时保留多条译码路径并在最终输出概率最大的译码结果的方式，改进极化码的有限码长性能。此外，可通过使用循环冗余检验(cyclic redundancy check，CRC)来辅助筛选正确的译码结果，从而极化码的有限码长性能可以得到进一步提高。
如图4所示，译码树可以有多层译码节点，图4中的一个圆圈代表一个译码节点。图4所示的译码树中包括4层译码节点，S＝3层的译码节点需要经过3层的译码递归运算得到S＝0层的译码节点。
一条译码路径表示的是已译出的译码节点中的比特的一种取值，比如S＝3层的译码节点得到S＝1层的译码节点，若译出的3个比特的取值分别为000、001、010、011、100、101、110、和111，则000为一条译码路径，001为一条译码路径，010为一条译码路径，011为一条译码路径，100为一条译码路径，101为一条译码路径，110为一条译码路径，111为一条译码路径。
第二，算术编码：
算术编码是一种无损数据压缩方法，也是一种熵编码的方法。算术编码和其它熵编码方法的不同之处在于，其他的熵编码方法通常是把输入的消息分割为符号，然后对每个符号进行编码，而算术编码是根据信源符号的概率直接把整个输入的消息编码为一个满足(0.0≤n<1.0)的小数n。在给定符号集和符号概率的情况下，算术编码可以给出接近最优的编码结果。使用算术编码的压缩算法通常先要对输入符号的概率进行估计，然后再编码。这个估计越准，编码结果就越接近最优的结果。
以一个非均匀分布的二元信源为例，假设0出现的概率为p 0，1出现的概率为1p 0。编码的初始区间为[0,1)。编码过程首先读取下一个信源符号，然后根据符号的值确定下一个区间。假设当前编码区间为[a,b)，若下一个符号为0，则新的区间变为[a,a+(b-a)*p 0)；若下一个符号为1，则新的区间变为[a+(b-a)*p 0,b)。当所有的符号都编码完毕，最终得到的结果区间即唯一的确定了已编码的符号序列。任何人使用该区间和使用的模型参数即可以解码重建得到该符号序列。实际上，并不需要传输最后的结果区间，只需要传输该区间中的任一个小数即可。在实用中，可以选择该区间中二进制(或其他进制)表示最短的小数作为编码结果，亦可直接选取区间的起点作为结果。
算术编码不仅能处理非记忆信源的压缩，还可以处理有记忆信源。此时可以采用自适应的区间确定方式进行编码，即根据具体上下文下的条件分布概率确定新的编码区间，随着不同的上下文进行自适应更新。解码器可以使用与编码器相同地模型。
下面将结合图5-图9对本申请实施例提供的通信方法进行具体阐述。本申请实施例提供的通信方法可以适用于信源冗余不仅仅存在非均匀性，还可能存在记忆性的场景。
示例性地，图5为本申请实施例提供的一种通信方法的流程示意图。
如图5所示，该通信方法包括如下步骤：
S501，发送端对第一比特序列进行信源编码，得到第二比特序列。
示例性地，第一比特序列的长度为A，A为大于0的整数。本申请对A的取值不进行限定。
示例性地，第二比特序列的长度为B，B为大于0的整数。本申请对B的取值不进行限定。
需要说明的是，本申请图5-图9提供的通信方法中字母的含义与上述对极化码和算术编码的阐述中字母的含义没有关联关系，以具体记载为准，在没有特殊说明的情 况下，下文中的A可以表示第一比特序列的长度，B可以表示第二比特序列的长度，在此统一说明，以下不再赘述。
示例性地，如图6a、图6b、和图6c所示，发送端对第一比特序列进行信源编码，得到第二比特序列。
在一些实施例中，发送端可以采用算数编码对第一比特序列进行信源编码，得到第二比特序列，接收端可以采用算数译码进行信源译码。
在一种可能的设计方式中，上述S501可以包括：S501-1至S501-4。
S501-1，发送端对第一比特序列进行逐比特信源编码，对第一比特序列的第a个比特进行信源编码后，得到第一比特序列的第一信源编码值。
可选地，a为大于0且小于或等于A的整数。
图7为本申请实施例提供的一种变长到定长的信源编码示意图。如图7所示，对第一比特序列的第1个比特至第50个比特进行信源编码后，得到第一比特序列的第一信源编码值。
S501-2，若第一比特序列的第一信源编码值的长度等于第一长度阈值，则输出第一比特序列的第一信源编码值。
可选地，第一长度阈值可以为大于0的整数。
结合图7，假设第一长度阈值的长度可以为30比特，若第一比特序列的第一信源编码值的长度刚好等于30，则输出第一比特序列的第一信源编码值。
也就是说，对第一比特序列进行逐比特信源编码，若编码结果的长度刚好等于第一长度阈值，则直接输出该编码结果，从第一比特序列的下一个比特开始继续进行信源编码。
一些实施例中，第一信源编码值可以包括第一长度信息，该第一长度信息可以指示第一信源编码值是对第一比特序列中的第一数量的比特进行信源编码后获得的。
也就是说，第一长度信息可以指示第一信源编码值对应第一比特序列的几个比特。
结合图7，对第一比特序列的第1个比特至第50个比特进行信源编码后，得到第一比特序列的第一信源编码值，假设第一长度阈值的长度为30比特，第一比特序列的第一信源编码值的长度刚好等于30，则第一长度信息可以指示第一数量50。下一次从第51个比特开始进行信源编码。
可选地，第一长度信息可以置于第一信源编码值的自然序靠前的比特位。
S501-3，若第一比特序列的第一信源编码值的长度大于第一长度阈值，则发送端将第一信源编码值中的第二信源编码值删除，得到第三信源编码值，将第三信源编码值的末尾补零，输出第四信源编码值。
可选地，第二信源编码值是对第一比特序列的第a个比特进行信源编码得到的，第四信源编码值的长度等于第一长度阈值。
结合图7，假设第一长度阈值的长度为30比特，第一比特序列的第一信源编码值的长度等于31，其中，第一信源编码值包括第三信源编码值和第二信源编码值。第三信源编码值的长度为29，是对第一比特序列的第1个比特至第49个比特进行信源编码获得的；第二信源编码值的长度为2，是对第一比特序列的第50个比特进行信源编码获得的。可以将第一信源编码值中的第二信源编码值删除，得到长度为29的第三信 源编码值。然而，第三信源编码值长度不等于第一长度阈值30，可以将第三信源编码值的末尾补零，使第三信源编码值的长度为30，并输出该补零后的第三信源编码值。下一次从第50个比特开始进行信源编码。
也就是说，第一信源编码值的长度不一定刚好等于第一长度阈值，有可能对第a-1个比特编码完成后得到的编码结果的长度小于第一长度阈值，但对第a个比特编码完成后得到的编码结果的长度大于第一长度阈值。这样情况可以删除第一信源编码值中第a个比特对应的编码比特，将删除后的第一信源编码值的末尾补零至第一长度阈值。
S501-4，若第a个比特为第一比特序列的最后一个比特，且第一信源编码值的长度小于第一长度阈值，则发送端将第一信源编码值的末尾补零，输出第五信源编码值。
可选地，第五信源编码值的长度等于第一长度阈值。
与第一信源编码值类似，第四信源编码值、第五信源编码值均可以包括对应的长度信息，以指示信源编码值对应的原始信源的长度。
也就是说，若对第一比特序列信源编码完成后，得到的第一信源编码值的长度小于第一长度阈值，可以将第一信源编码值的末尾补零后输出，从而使每一段的信源编码值的长度相同。
可选地，信源编码值(例如第一信源编码值、第四信源编码值、第五信源编码值等)中的长度信息的比特和末尾补零比特可以称为非均匀比特，可以将非均匀比特映射至可靠度较低的信息比特位。
结合图8，将长度信息的比特和末尾补零比特映射至可靠度较低的信息比特位，后续可以对映射后的信源编码值进行信道编码、以及译码等操作，可以提高错误的译码结果被检出的概率。
如此，发送端可以将不同长度的信源压缩成多个相同长度的序列，可以兼顾无损压缩和固定输出长度，后续可以采用固定的码率进行信道编码，并且还可以利用压缩后的非均匀比特进行辅助译码，可以提高译码成功率。
S502，发送端根据第二比特序列和第三比特序列，得到第四比特序列。
示例性地，第三比特序列可以为第一比特序列中的C个比特，C为大于0且小于或等于A的整数。
如图6a、图6b、和图6c所示，可以从第一比特序列的A个比特中选择C个比特作为第三比特序列。
需要说明的是，第三比特序列中的C个比特序列可以是如图6a、图6b、和图6c所示的连续的C个比特，也可以是非连续的C个比特，本申请对此不进行限定。
如此，发送端选取第一比特序列中的部分比特映射至第四比特序列，以利用部分原始信源比特序列来辅助进行信道译码，不修改信源编码结果，可以准确地判断译码结果是否准确，提高译码成功率。
在一种可能的设计方式中，第三比特序列为第一比特序列中的C个比特，可以包括：第三比特序列为第一比特序列中的自然序靠前的C个比特。
示例性地，假设第一比特序列包括a 1、a 2、a 3、a 4、a 5、a 6、a 7、a 8，a 1可以表示自然序的位置为第一的比特，a 2可以表示自然序的位置为第二的比特，a 3可以表示自然序的位置为第三的比特，类似地，a 8可以表示自然序的位置为第八的比特。
如图6a所示，第三比特序列可以为第一比特序列中的自然序靠前的C个比特。
如此，选择第一比特序列中的自然序靠前的比特作为第三比特序列，可以使在译码过程中更早参与校验，可以更早地判断译码结果是否准确，若译码结果存在错误，可以更早停止译码。
在一些实施例中，第三比特序列可以为第一比特序列中的自然序的中间C个比特，如图6b、和图6c所示。
需要说明的是，第三比特序列可以为第一比特序列中的任意C个比特。例如可以为第一比特序列中的自然序靠后的C个比特，本申请对此不进行限定。
示例性地，第四比特序列的长度为N，N为大于0的整数。第四比特序列可以包括一个或多个信息比特、和一个或多个冻结比特。
示例性地，第二比特序列可以处于第四比特序列的B个信息比特位上。
如图6a、图6b、和图6c所示，可以将第二比特序列映射至第四比特序列的B个信息比特位上。这B个信息比特位可以是连续的或非连续的，本申请对此不进行限定。
示例性地，第三比特序列可以处于第四比特序列的第一比特位上。其中，第一比特位可以包括E个信息比特位和F个冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数。
也就是说，发送端可以将第三比特序列的全部比特置于第四比特序列的信息比特位上；或者，将第三比特序列的全部比特置于第四比特序列的冻结比特位上；或者，将第三比特序列的一部分比特置于第四比特序列的信息比特位上，另一部分置于第四比特序列的冻结比特位上。
如图6a所示，E＝0且F＝C，将第三比特序列全部置于第四比特序列的C个冻结比特位上。
如图6b所示，E＝C且F＝0，将第三比特序列全部置于第四比特序列的C个信息比特位上。
如图6c所示，E＞0且F＞0，将第三比特序列置于第四比特序列的E个信息比特位和F个冻结比特位上。
需要说明的是，发送端可以将第三比特序列的C个比特置于第四比特序列的连续的C个比特位上。如图6a所示，置于连续的C个冻结比特位上。如图6b或图6d所示，置于连续的C个信息比特位上。如图6e所示，置于连续的C1个信息比特位和C2个冻结比特位上。
或者，可以将第三比特序列的C个比特置于第四比特序列的非连续的C个比特位上。如图6c所示，置于非连续的E个信息比特位和F个冻结比特位上。如图6f所示，置于非连续的C1个冻结比特位和C2个冻结比特位上。如图6g所示，置于非连续的C1个信息比特位和C2个信息比特位上，本申请实施例不一一列举。其中，C1+C2＝C。
如此，将第三比特序列映射到第四比特序列的冻结比特位上，不会增大信道编码的码率，可以提高系统性能。
在一种可能的设计方式中，E等于C且F等于0，第一比特位满足第一原则，第一原则可以包括：第一比特位处于第四比特序列的自然序靠前的E个信息比特位上。
示例性地，假设第三比特序列的长度为10，包括c 1至c 10，第二比特序列的长度 为32，包括b 1至b 32。第三比特序列处于第一比特位，第二比特序列处于第四比特序列的其他信息比特位，例如第三比特序列和第二比特序列的排列次序可以为c 1c 2…c 10b 1b 2…b 32。
结合图6d，c 1c 2…c 10可以处于图6d中所示的第四比特序列的自然序靠前的C(C＝10)个信息比特位上，b 1b 2…b 32可以处于第四比特序列剩余的信息比特位上。
需要说明的是，本申请不对第三比特序列和第二比特序列之间、或者第三比特序列的各个比特之间、或者第二比特序列的各个比特之间是否间隔冻比特位进行限定，图6d仅为一种示例。
如此，可以使在译码过程中更早地判断译码结果是否准确，若译码结果存在错误，可以更早停止译码。或者，在一些实施例中，E等于C且F等于0，第一比特位满足第一原则，第一原则可以包括：第一比特位的E个比特位与第二比特序列的B个比特位交替排列。
示例性地，对于第三比特序列的全部比特处于信息比特位的情况，假设第三比特序列的长度为10，包括c 1至c 10，第二比特序列的长度为32，包括b 1至b 32。第三比特序列和第二比特序列的排列次序可以为c 1b 1c 2b 2c 3b 3c 4b 4c 5b 5c 6b 6c 7b 7c 8b 8c 9b 9c 10b 10b 11…b 32，b 1c 1b 2c 2b 3c 3b 4c 4b 5c 5b 6c 6b 7c 7b 8c 8b 9c 9b 10c 10b 11…b 32，c 1c 2b 1b 2c 3c 4b 3b 4…c 9c 10b 9b 10b 11…b 32，或者b 1b 2b 3c 1c 2c 3…b 7b 8b 9c 7c 8c 9b 10c 10b 11…b 32等。
需要说明的是，本申请实施例不对第一比特位的E个比特位与第二比特序列的B个比特位具体如何交替排列进行限定。本申请交替排列情况下第三比特序列和第二比特序列各个比特之间是否间隔冻比特位进行限定。
如此，第一比特位的E个比特位与第二比特序列的B个比特位交替排列的情况，可以使在译码过程中译出部分比特后，即可判断这部分译码结果是否准确，相比于需要译出全部第三比特序列和/或第二比特序列的方式，可以更早地判断这部分译码结果是否准确，若译码结果存在错误，可以更早停止译码。
可选地，第一比特位的E个比特位与第二比特序列的B个比特位交替排列同样适用于E大于0且F大于0的情况。
在一种可能的设计方式中，F等于C且E等于0，第一比特位满足第二原则，第二原则可以包括：第四比特序列的第一比特位与待译码序列的第一位置对应，对待译码序列的第一位置的之前的值进行信道译码的结果进行信源译码后，能够获得第三比特序列的一个或多个比特的信源译码值，或者，第一比特位处于第四比特序列的自然序靠后的F个冻结比特位上。
可选地，待译码序列为第五比特序列经过信道传输后的序列。
如图6a或图6f所示，发送端对第四比特序列进行信道编码得到第五比特序列，并通过信道发送第五比特序列，接收端接收到待译码序列。待译码序列的第一位置与第四比特序列的第一比特位对应，第三比特序列处于第四比特序列的第一比特位上，待译码序列的第一位置的比特序号与第四比特序列的第一比特位的比特序号相同。
如图6a所示，第一比特位可以处于第四比特序列的自然序靠后的C个冻结比特位上。
如图6a所示，第三比特序列的C个比特处于第四比特序列的第一比特位(第38位至第47位)上，该第一比特位对应的待译码序列的第一位置(第38位至第47位)满足：对待译码序列的第一位置的之前的值(例如第1位上的值至第37位上的值)进行信道译码的结果进行信源译码后，能够获得第三比特序列的C个比特的信源译码值。
如图6f所示，第三比特序列的C个比特处于第四比特序列的第一比特位(第21位至第25位、以及第38位至第42位)上，第一比特位(第21位至第25位)对应的待译码序列的第一位置(第21位至第25位)满足：对待译码序列的C1个比特的之前的比特位(例如第1位上的值至第20位上的值)进行信道译码的结果进行信源译码后，能够获得第三比特序列的对应的C1个比特的信源译码值。将第三比特序列的对应的C1个比特的信源译码值作为待译码序列的C1个比特的位置上的信道译码值。
需要说明的是，对待译码序列的C1个位置的之前的位置上的值进行信道译码的结果进行信源译码后，可以获得大于C1(如图6f所示，C1等于5)个比特的信源译码值，例如可以获得第三比特序列的对应的6个比特的信源译码值。
可选地，如图6f所示，第一比特位(第38位至第42位)对应的待译码序列的第一位置(第38位至第42位)满足：继续对待译码序列的C2个比特的之前的比特位(例如第21位上的值至第37位上的值)进行信道译码的结果进行信源译码后，能够获得第三比特序列的对应的C2个比特的信源译码值。
需要说明的是，对待译码序列的C2个比特的之前的比特位进行信道译码的结果进行信源译码后，可以获得小于C2(如图6f所示，C2等于6)个比特的信源译码值，例如可以获得第三比特序列的对应的4个比特的信源译码值。也就是说，能够保证对待译码序列的C2个位置的之前的值进行信道译码的结果进行信源译码后，能够获得第三比特序列的对应的C2个比特的信源译码值即可。
如此，可以使在译码过程中，若第二比特序列的信道译码值有错误，使当前译码路径的错误进行积累，从而译码错误很容易被甄别出来，可以提高译码成功率。
可选地，上述第二原则同样适用于E大于0且F大于0的情况。
一些实施例中，第一比特位可以包括E个信息比特位和F个冻结比特位，E大于0且F大于0，E个信息比特位满足第一原则，即E个信息比特位处于第四比特序列的自然序靠前的E个信息比特位上(如图6c所示)，或者E个比特位与第二比特序列的B个比特位交替排列；F个比特位满足第二原则，即第四比特序列的第一比特位与待译码序列的第一位置对应，对待译码序列的第一位置的之前的值进行信道译码的结果进行信源译码后，能够获得第三比特序列的一个或多个比特的信源译码值(如图6c所示)，或者，F个比特位处于第四比特序列的自然序靠后的F个冻结比特位上(如图6c所示)。
在一种可能的设计方式中，第三比特序列处于第四比特序列的第一比特位上，可以包括：加扰后的第三比特序列处于第四比特序列的第一比特位上。
可选地，加扰后的第三比特序列可以是根据加扰序列和第三比特序列获得的。
示例性地，该第一比特位可以是处于第四比特序列的自然序靠后的C个信息比特位。
如此，在译码过程中，可以对自然序靠前的信息比特位进行信道译码，对第四比 特序列的信息比特进行加扰不会增大信道编码的码率，可以提高系统性能。另外，多个原始信源比特位置的信源译码错误会影响到这些比特位置的信道译码，从而可以进一步提高错误的译码结果被检出的概率。
S503，发送端对第四比特序列进行信道编码，得到第五比特序列。
其中，第五比特序列的长度为N，N为大于0的整数。
如图6a所示，对第四比特序列进行信道编码得到第五比特序列。
如此，第四比特序列是根据第二比特序列和第三比特序列确定的，第三比特序列为原始信源比特序列中的一个或多个比特，直接利用部分原始信源比特和原始信源比特序列的信源编码结果进行信道编码，可以提高系统性能。
在一些实施例中，发送端可以采用极化码编码进行信道编码，得到第五比特序列，接收端可以采用极化码编码进行信道译码，本申请对此不进行限定。
S504，发送端发送第五比特序列。
如图6a所示，发送端可以通过信道发送第五比特序列。
S505，接收端接收待译码序列。
示例性地，待译码序列的长度为N，N为大于0的整数。
示例性地，待译码序列的长度为N，N为大于0的整数，待译码序列为第五比特序列经过信道传输后的序列。
示例性地，第五比特序列为第四比特序列的信道编码值，待译码序列的第一位置与第四比特序列的第一比特位对应，第三比特序列处于第四比特序列的第一比特位上，第三比特序列为第一比特序列中的C个比特，第一比特序列的长度为A，A为大于0的整数，C为大于0且小于或等于A的整数。待译码序列的第二位置与第四比特序列的中第二比特序列占用的B个信息比特位对应，第二比特序列为第一比特序列的信源编码值，第二比特序列的长度为B，B为大于0的整数。具体可参照上述S501或S502中对应的阐述，此处不再赘述。
例如，第四比特序列的第一比特位包括E个信息比特位和F个冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数，具体可参照上述S502中对应的阐述，此处不再赘述。
在一种可能的设计方式中，E等于C且F等于0，第四比特序列的第一比特位满足第一原则，第一原则可以包括：第一比特位处于第四比特序列的自然序靠前的E个信息比特位上。具体实现方式可参照上述S502中对应的阐述，此处不再赘述。
在一种可能的设计方式中，F等于C且E等于0，第一比特位满足第二原则，第二原则可以包括：第四比特序列的第一比特位与待译码序列的第一位置对应，对待译码序列的第一位置的之前的值进行信道译码的结果进行信源译码后，能够获得第三比特序列的一个或多个比特的信源译码值，或者，第一比特位处于第四比特序列的自然序靠后的C个冻结比特位上。具体实现方式可参照上述S502中对应的阐述，此处不再赘述。
需要说明的是，关于第四比特序列的第一比特位具体实现方式可参照上述S502中对应的阐述，此处不再赘述。
S506，接收端对待译码序列进行信道译码，得到第四比特序列的信道译码值。
示例性地，第四比特序列的信道译码值可以包括第二比特序列的信道译码值和第三比特序列的信道译码值。
可选地，接收端可以采用逐比特译码方式对待译码序列进行信道译码，得到第四比特序列的信道译码值。例如，接收端可使用列表、堆栈等类型的译码结构。
在一种可能的设计方式中，上述S506，可以包括下述步骤1至步骤4。
可选地，信道译码的方式可以为SCL方式，列表的数量为L，L为大于0的整数。
c u_total的初始值等于0，若c u_total小于C，则接收端可以执行下述第一信源信道操作(包括下述步骤1至步骤3)。
步骤1，接收端对待译码序列的第n-m位上的值至第n位上的值进行信道译码，得到第一译码结果。
可选地，第n-m位至第n位包括第一位置中的至少一个位置和/或第二位置中的b个位置，n-m为大于0的整数，m为大于0的整数，b为大于0且小于或等于B的整数。
可选地，第一译码结果可以包括第二比特序列的b个比特的信道译码值和/或第三比特序列的至少一个比特的信道译码值。
也就是说，接收端可以对第一位置中的至少一位上的值和第二位置中的至少一位上的值进行信道译码，第一译码结果可以包括第二比特序列的至少一个比特的信道译码值和第三比特序列的至少一个比特的信道译码值。
一些实施例中，接收端需要通过执行多次第一信源信道操作，完成对待译码序列的信道译码的情况下，每次执行第一信源信道操作的过程中，m的值可以相等或不相等。
示例性地，接收端从待译码序列的第1位上的值开始进行信道译码，第一次执行第一信源信道操作的过程中，可以对待译码序列的第1位上的值至第6位上的值将进行信道译码(m＝5)，第二次执行第一信源信道操作的过程中，可以对待译码序列的第7位上的值至第14位上的值将进行信道译码(m＝7)，不一一赘述。
可选地，第一译码结果的数量可以是一个或多个，例如可以是L个。
结合图6b，假设C＝10，B＝32，第n-m位至第n位可以包括第1位至第28位。其中，第11位至第20位可以为第二位置中的前10位，第28位可以为第一位置中的第1位。对第1位上的值至第28位上的值进行信道译码，得到的第一译码结果包括第二比特序列的前10个比特的信道译码值和第三比特序列的第1个比特的信道译码值。
结合图6d，假设C＝10，B＝32，第n-m位至第n位可以包括第1位至第28位。其中，第11位至第20位可以为第一位置中的10个位，第28位可以为第二位置中的第1位。对第1位上的值至第28位上的值进行信道译码，得到的第一译码结果包括第三比特序列的前10个比特的信道译码值和第二比特序列的第1个比特的信道译码值。
结合图6g，假设C＝10，B＝32，第n-m位至第n位可以包括第1位至第28位。其中，第11位至第15位可以为第一位置中的前5位，第16位可以为第二位置中的第1位。对第1位上的值至第16位上的值进行信道译码，得到的第一译码结果包括第三比特序列的前5个比特的信道译码值和第二比特序列的第1个比特的信道译码值。
示例性地，第三比特序列和第二比特序列的排列次序为 c 1b 1c 2b 2c 3b 3c 4b 4c 5b 5c 6b 6c 7b 7c 8b 8c 9b 9c 10b 10b 11…b 32时，第n-m位上的值至第n位上的值可以包括c 1b 1，对第n-m位上的值至第n位上的值进行信道译码，得到的第一译码结果包括第三比特序列的c 1比特的信道译码值和第二比特序列的b 1比特的信道译码值。
示例性地，第三比特序列和第二比特序列的排列次序为c 1c 2b 1b 2c 3c 4b 3b 4…c 9c 10b 9b 10b 11…b 32时，第n-m位上的值至第n位上的值可以包括c 1c 2b 1，对第n-m位上的值至第n位上的值进行信道译码，得到的第一译码结果包括第三比特序列的c 1c 2比特的信道译码值和第二比特序列的b 1比特的信道译码值。本申请不再一一列举。
接收端第二次执行第一信源信道操作，继续对图6b所示的待译码序列执行步骤1，第n-m位至第n位可以包括第29位至第32位。其中，第29位至第32位可以为第一位置中的第2位至第5位。对第29位上的值至第32位上的值进行信道译码，得到的第一译码结果包括第三比特序列的第2个比特至第5个比特的信道译码值。
接收端第二次执行第一信源信道操作，继续对图6d所示的待译码序列执行步骤1，第n-m位至第n位可以包括第29位至第37位。其中，第29位至第37位可以为第二位置中的第2位至第10位。对第29位上的值至第37位上的值进行信道译码，得到的第一译码结果包括第二比特序列的第2个比特至第10个比特的信道译码值。
接收端第二次执行第一信源信道操作，继续对图6g所示的待译码序列执行步骤1，第n-m位至第n位可以包括第17位至第20位。其中，第17位至第20位可以为第二位置中的第2位至第4位。对第17位上的值至第20位上的值进行信道译码，得到的第一译码结果包括第二比特序列的第2个比特至第4个比特的信道译码值。需要说明的是，在第一次执行第一信源信道操作的过程中，可以对待译码序列的第1位上的值至20位上的值进行信道译码，本申请对此不进行限定，上述仅为本申请提供的示例。
一些实施例中，上述步骤1可以是接收端的信道译码器执行的，信道译码器可以将获得的第二比特序列的b个比特的信道译码值反馈到信道译码器，从而执行下述步骤2。
步骤2，接收端对第二比特序列的b个比特对应的信道译码值进行信源译码，得到第三比特序列的c t个比特的信源译码值。
可选地，c t为大于0且小于或等于C的整数。
结合图6b，对第二比特序列的前10个比特的信道译码值进行信源译码，得到第三比特序列的c t个比特的信源译码值，例如c t等于5。
结合图6d或图6g，对第二比特序列的第1个比特的信道译码值进行信源译码，得到第三比特序列的c t个比特的信源译码值，例如c t等于1。
需要说明的是，本申请不再一一列举，得到第三比特序列的至少一个比特的信源译码值即可。
第二次执行第一信源信道操作时，对于图6b所示的待译码序列，接收端可以不执行步骤2，直接执行下述步骤3。
第二次执行第一信源信道操作时，对于图6d所示的待译码序列，接收端可以对第二比特序列的第2个比特至第10个比特对应的信道译码值进行信源译码，得到第三比特序列的c t个比特的信源译码值，例如c t等于9。
第二次执行第一信源信道操作时，对于图6g所示的待译码序列，接收端可以对第二比特序列的第2个比特至第4个比特对应的信道译码值进行信源译码，得到第三比特序列的c t个比特的信源译码值，例如c t等于4。
一些实施例中，上述步骤2可以是接收端的信源译码器执行的，信源译码器可以将获得的第三比特序列的c t个比特的信源译码值反馈到信道译码器。
步骤3，接收端根据第三比特序列的c u个比特的信源译码值与第三比特序列的自然序对应的c u个比特的信道译码值，确定基于l条译码路径对待译码序列的第n+1位上的值至第N位上的值继续执行第一信源信道操作，并将c u计入c u_total。
可选地，c u为大于0的整数，l为小于或等于L的整数。
如此，可以根据已获得的第三比特序列的至少一个比特的信源译码值与第三比特序列的自然序对应的至少一个比特的信道译码值，判断译码结果是否正确。
结合图6b，接收端可以根据第三比特序列的前5个比特的信源译码值(第一次执行第一信源信道操作在步骤2中得出的)中的第1个比特的信源译码值，以及第三比特序列的第1个比特的信道译码值(第一次执行第一信源信道操作在步骤1中得出的)，确定是否继续执行第一信源信道操作，其中，c u＝1，将1计入c u_total，c u_total＝1。
若需要结合图6b所示的待译码序列继续第二次执行第一信源信道操作，接收端可以根据第三比特序列的第2个比特至第5个比特的信源译码值(第一次执行第一信源信道操作在步骤2中得出的)，以及第三比特序列的第2个比特至第5个比特的信道译码值(第二次执行第一信源信道操作在步骤1中得出的)，确定是否继续执行第一信源信道操作，其中，c u＝4，将4计入上一次执行第一信源信道操作后的c u_total(c u_total＝1)，c u_total＝1+4＝5。
需要说明的是，关于图6b和图6g所示的待译码序列在步骤3中的实现方式与图6b类似，此处不再赘述。
在一些实施例中，步骤3可以包括下述步骤3a至步骤3c。
步骤3a，接收端遍历L条译码路径，确定第一译码路径对应的第三比特序列的c u个比特的信源译码值与第一译码路径对应的第三比特序列的自然序对应的c u个比特的信道译码值是否相同。
可选地，第一译码路径可以为L条译码路径中的一个。
示例性地，c u＝2，第三比特序列第5个比特和第6个比特的信源译码值与第三比特序列第5个比特和第6个比特的信道译码值进行比较，若第三比特序列第5个比特的信源译码值与第三比特序列第5个比特的信道译码值相同，且第三比特序列第6个比特的信源译码值与第三比特序列第6个比特的信道译码值相同，则确定为相同，否则，确定为不相同。
如此，可以准确地判断出第一译码路径的译码结果是否准确。
步骤3b，若不相同，则接收端确定删除第一译码路径，终止基于第一译码路径的第一信源信道操作。
如此，判断出第一译码路径的译码结果的不准确，删减第一译码路径，不再基于第一译码路径对待译码序列的第n+1位上的值至第N位上的值继续执行第一信源信道操作。
步骤3c，若相同，则接收端可以确定l条译码路径包括所述第一译码路径。
如此，判断出第一译码路径的译码结果的准确，接收端可以基于第一译码路径对待译码序列的第n+1位上的值至第N位上的值继续执行第一信源信道操作。
步骤4，若c u_total等于C且n小于N，则对待译码序列的第n+1位上的值至第N位上的值继续进行信道译码。
也就是说，若已根据第三比特序列的最后一个比特的信源译码值与第三比特序列的自然序对应的最后一个比特的信道译码值执行上述步骤3，并且还未对待译码序列的所有比特进行信道译码，继续对待译码序列的剩余位置的值进行信道译码，完成信道译码。从而，得到第二比特序列的B个的信道译码值和第三比特序列的C个的信道译码值。
如此，接收端在信道译码过程中，根据第二比特序列的信道译码值获得第三比特序列的信源译码值，将第三比特序列的信源译码值与第三比特序列的信道译码值进行比较，可以准确地判断译码结果是否准确，从而提高系统性能。
在另一种可能的设计方式中，上述S506，可以包括下述步骤5至步骤9。
c t_total的初始值等于0，若c t_total小于C，则接收端可以执行下述第二信源信道操作(包括下述步骤5至步骤6)。
可选地，信道译码的方式可以为SCL方式，列表的数量为L，L为大于0的整数。
步骤5，接收端对待译码序列的第n-m位上的值至第n位上的值进行信道译码，得到第二译码结果。
可选地，第n+1位为第一位置中的一个位置，n-m为大于0的整数，m为大于0的整数。
例如，假设C＝10，对于图6a所示的待译码序列，待译码序列的第n-m位至第n位可以包括第1位至第37位。
假设C＝10，对于图6f所示的待译码序列，待译码序列的第n-m位至第n位可以包括第1位至第20位。当针对图6f所示的待译码序列第二次执行第二信源信道操作时，待译码序列的第n-m位至第n位可以包括第21位至第37位。
一些实施例中，第二译码结果可以包括第二比特序列的b个比特的信道译码值。
可选地，第二译码结果还可以包括第三比特序列的至少一个比特的信道译码值。
例如，对于图6a所示的待译码序列，对第1位上的值至第37位上的值进行信道译码，得到第二比特序列的前20个比特的信道译码值。
例如，对于图6f所示的待译码序列，对第1位上的值至第20位上的值进行信道译码，得到第二比特序列的前10个比特的信道译码值。
当针对图6f所示的待译码序列第二次执行第二信源信道操作时，对第21位上的值至第37位上的值进行信道译码，得到第二比特序列的第11个比特至第20个比特的信道译码值、和第三比特序列的第1个比特至第5个比特的信道译码值。
一些实施例中，上述步骤5可以是接收端的信道译码器执行的，信道译码器可以将获得的第二比特序列的b个比特的信道译码值反馈到信道译码器，从而执行下述步骤6。
步骤6，接收端对第二比特序列的b个比特的信道译码值进行信源译码，得到第 三比特序列的c t个比特的信源译码值，并将c t计入c t_total。
可选地，c t为大于0且小于或等于C的整数。
可选地，第三比特序列的c t个比特的信源译码值依次作为待译码序列的第一位置中的c t个位置上的值的信道译码值。
也就是说，可以直接将每一次执行第二信源信道操作获得的第三比特序列的c t个比特的信源译码值，依次作为待译码序列的第一位置中的c t个位置上的值的信道译码值。例如第一次执行第二信源信道操作，在步骤6得到第三比特序列的5个比特的信源译码值，则将其作为待译码序列的第一位置中的第1位至第5位上的值的信道译码值。第一次执行第二信源信道操作，在步骤6得到第三比特序列的3个比特的信源译码值，则将其作为待译码序列的第一位置中的第6位至第8位上的值的信道译码值。
结合图6a，假设C＝10，接收端对第二比特序列的前20个比特的信道译码值进行信源译码，得到第三比特序列的10个比特的信源译码值，c t_total等于10。并将得到的第三比特序列的10个比特的信源译码值，依次作为待译码序列的第一位置中的10个位置上的值的信道译码值。
结合图6f，假设C＝10，接收端对第二比特序列的前10个比特的信道译码值进行信源译码，得到第三比特序列的第1个比特至第5个比特的信源译码值，c t_total等于5。并将得到的第三比特序列的第1个比特至第5个比特的信源译码值，依次作为待译码序列的第21位至第25位(即第一位置中的前5位)上的值的信道译码值。
结合图6f，第二次执行第二信源信道操作时，接收端对第二比特序列的第11个比特至第20个比特的信道译码值进行信源译码，得到第三比特序列的第6个比特至第10个比特的信源译码值，将5计入上一次执行第二信源信道操作后的c t_total，c t_total＝5+5＝10。并将得到的第三比特序列的第6个比特至第10个比特的信源译码值，依次作为待译码序列的第38位至第42位(即第一位置中的后5位)上的值的信道译码值。
一些实施例中，上述步骤6可以是接收端的信源译码器执行的，信源译码器可以将获得的第三比特序列的c t个比特的信源译码值反馈到信道译码器。
步骤7，若c t_total大于0且小于C，接收端对待译码序列的第n+1位上的值至第N位上的值继续执行第二信源信道操作。
若步骤6中获得的c t_total大于0且小于C，则接收端继续对待译码序列剩余位上的值执行上述步骤5至步骤6。
例如，结合图6f，第一次执行第二信源信道操作后，c t_total等于5(参照上述步骤6)，接收端对待译码序列的第21位上的值至第N位上的值继续执行第二信源信道操作。
也就是说，若未译出第三比特序列的全部比特的信源译码值，则继续执行步骤5至步骤6。
可选地，上述步骤7可以包括：若c t_total大于0且小于C，接收端根据L条译码路径分别对应的路径度量值，确定基于l条译码路径对待译码序列的第n+1位上的值至第N位上的值继续执行第二信源信道操作。
如此，接收端通过对第二比特序列的信道译码值进行信源译码，得到第三比特序 列的信源译码值，并将第三比特序列的信源译码值作为待译码序列的第一位置上的值的信道译码值。这样，若第二比特序列的信道译码值有错误，会导致第三比特序列的信源译码值有误，进而导致译码时，导致待译码序列对第一位置进行译码时译码有误，这样当前译码路径的错误会进行积累，使得当前译码路径对应的路径度量值变化，从而译码错误很容易被甄别出来，可以提高译码成功率。
步骤9，若c t_total等于C且n小于N，接收端对待译码序列的第n+1位上的值至第N位上的值继续进行信道译码。
例如，结合图6a，第一次执行第二信源信道操作后，c t_total等于10(参照上述步骤6)，接收端对待译码序列的第38位上的值及后续的位置上的值继续进行信道译码。
例如，结合图6f，第二次执行第二信源信道操作后，c t_total等于10(参照上述步骤6)，接收端对待译码序列的第38位上的值及后续的位置上的值继续进行信道译码。
从而，得到第二比特序列的B个的信道译码值和第三比特序列的C个的信道译码值。
可选地，上述步骤9可以包括：若c t_total等于C且n小于N，接收端可以根据L条译码路径分别对应的路径度量值，确定基于l条译码路径对待译码序列的第n+1位上的值至第N位上的值继续执行第二信源信道操作。
在一种可能的设计方式中，上述S506，可以包括上述步骤1至步骤4、以及上述步骤5至步骤9。
示例性地，第一比特位包括E个信息比特位和F个冻结比特位，对于E大于0且F大于0的情况，可以结合使用上述步骤1至步骤4、以及上述步骤5至步骤9。
例如，对于图6c、图6e所示的待译码序列，可以结合使用上述步骤1至步骤4、以及上述步骤5至步骤9进行信道译码，获得第四比特序列的信道译码值，此处不再详细赘述。
如此，接收端可以通过将第三比特序列的信源译码值与第三比特序列的信道译码值进行比较，判断译码结果是否准确，并且可以将第三比特序列的信源译码值作为待译码序列的第一位置上的值的信道译码值，通过译码路径对应的路径度量值，判断译码结果是否准确，可以提高错误的译码结果被检出的概率，从而提高系统性能。
在一些实施例中，对待译码序列的第三位置上的值进行信道译码时，可以直接赋0。
示例性地，第三位置与第四比特序列的普通冻结比特位对应，普通冻结比特位指不属于第一比特位的冻结比特位。
如图6a所示，第四比特序列的第1个比特位至第10个比特位、和第21个比特位至第27个比特位均可以称为普通冻结比特位。
在一些实施例中，若接收端对待译码序列的最后一位上的值进行信道译码前，能够通过已经获得的第二比特序列的信道译码值恢复出长度大于A的第一比特序列的信源译码值，则当前译码路径存在错误，删除当前译码路径。
也就是说，第一比特的原始长度为A，通过第二比特序列的部分信道译码值恢复出长度大于A的第一比特序列的信源译码值，明显译码结果存在错误，停止基于当前译码路径进行信道译码。
可选地，接收端对待译码序列中的全部值进行信道译码完成后，可以将可能性最高的第四比特序列的信道译码值作为信道译码输出。
S507，接收端对第二比特序列的信道译码值进行信源译码，得到第一比特序列的信源译码值。
示例性地，从第四比特序列的信道译码值中获取第二比特序列的信道译码值，并进行信源译码，得到第一比特序列的信源译码值。
对于采用上述S501-1至S501-4所示的方式进行信源编码的情况，在进行信源译码时，在译到非均匀比特(例如长度信息占用的比特或补0的比特)时，若非均匀比特(b i)的值为0，则将该比特对应的译码路径的路径度量值增加一个偏移量，即-logP(b i＝0)；若非均匀比特的值为1，则将该比特对应的译码路径的路径度量值增加一个偏移量，即-logP(b i＝1)。其中，P(b i)是该比特的先验分布概率。然后再进行路径选择，并将它们逆映射到原始的位置。
基于图5所示的通信方法，发送端将第一比特序列的信源编码结果和第一比特序列中的部分比特序列结合，获得信道编码的输入，即第四比特序列，对第四比特序列进行信道编码，接收端在对待译码序列进行译码的过程中，可以采用第一比特序列中的部分比特序列进行联合译码，可以准确地判断出错误的译码结果，可以提高错误的译码结果被检出的概率，从而提高系统性能。
示例性地，图9为本申请实施例提供的另一种通信方法的流程示意图。
如图9所示，该通信方法包括如下步骤：
S901，发送端对第一比特序列进行信源编码，得到第二比特序列。
S902，发送端根据第二比特序列和第三比特序列，得到第四比特序列。
S903，发送端对第四比特序列进行信道编码，得到第五比特序列。
S904，发送端发送第五比特序列。
需要说明的是，上述S901至S904的具体实现方式可分别参照上述S501至S504的实现方式，此处不再赘述。主要区别在于，图5所示的通信方法中，第四比特序列的第一比特位包括E个信息比特位和F个冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数；图9所示的通信方法中，第四比特序列的第一比特位包括C个信息比特位，属于E等于C且F等于0的情况。
例如，图9所示的通信方法中S901至S904的具体实现方式可参照图5所示的通信方法中关于图6b、图6d、图6g的示例、和其他E等于C且F等于0对应的示例。
S905，接收端接收待译码序列。
示例性地，待译码序列包括为第五比特序列经过信道传输后的序列，第五比特序列为第四比特序列的信道编码值，待译码序列的第一位置与第四比特序列的第一比特位对应，第三比特序列处于第四比特序列的第一比特位上，第四比特序列的第一比特位包括C个信息比特位，第三比特序列为第一比特序列中的C个比特，第一比特序列的长度为A，A为大于0的整数，C为大于0且小于或等于A的整数。待译码序列的第二位置与第四比特序列的中第二比特序列占用的B个信息比特位对应，第二比特序列为第一比特序列的信源编码值，第二比特序列的长度为B，B为大于0的整数。具体可参照上述S501或S502中对应的阐述，此处不再赘述。
S906，接收端对待译码序列进行第q次迭代信道译码，获得第四比特序列的信道译码值。
可选地，q为大于0的整数。
示例性地，第四比特序列的信道译码值可以包括第二比特序列的信道译码值和第三比特序列的信道译码值。
S907，接收端对第二比特序列的信道译码值进行第g次信源译码，得到第一比特序列的信源译码值。
可选地，g为大于0的整数。G与q可以不相等。
例如，接收端可以在对待译码序列进行多次迭代信道译码后，对第二比特序列的信道译码值进行1次信源译码。
示例性地，第一比特序列的信源译码值可以包括第三比特序列的信源译码值。
也就是说，第三比特序列为第一比特序列中的一个或多个比特，第一比特序列的信源译码值包括第一比特序列的全部比特的信源译码值，从而包括第三比特序列的C个比特的信源译码值。
在一种可能的设计方式中，上述S907，可以包括：在第四比特序列的信道译码值通过信道校验的情况下，接收端对第二比特序列的信道译码值进行第g次信源译码，得到第一比特序列的信源译码值。
示例性地，若第四比特序列的信道译码值能够通过信道译码器本身的校验机制，则对第二比特序列的信道译码值进行第g次信源译码，得到第一比特序列的信源译码值，从而得到第三比特序列的信源译码值。
S908，接收端在第三比特序列的信道译码值与第三比特序列的信源译码值相同或q等于Q的情况下，输出第一比特序列的信源译码值。
可选地，Q为最大迭代次数，Q为大于0的整数。
也就是说，接收端可以将第三比特序列的信道译码值与第三比特序列的信源译码值进行比较，若相同，则输出第一比特序列的信源译码值。或者信道译码迭代次数达到最大迭代次数的情况下，输出第一比特序列的信源译码值。
在一种可能的设计方式中，图9所示的通信方法还可以包括：在第三比特序列的信道译码值与第三比特序列的信源译码值不相同且q小于Q的情况下，对待译码序列进行第q+s次迭代信道译码，对第q+s次迭代信道译码结果中的第二比特序列的信道译码值进行第g+t次信源译码。
可选地，s为大于0的整数，t为大于0的整数。
例如，接收端可以在对待译码序列进行多次迭代信道译码后，对第二比特序列的信道译码值进行1次信源译码。
也就是说，接收端在第三比特序列的信道译码值与第三比特序列的信源译码值相同和/或q等于Q的情况下，输出信源译码结果，停止进行信道译码和信源译码。
基于图9所示的通信方法，接收端从对待译码序列进行第q次迭代信道译码的结果中，选择第二比特序列的信道译码值进行第g次信源译码，得到第一比特序列的信源译码值，直到第三比特序列的信道译码值与第三比特序列的信源译码值相同或达到最大迭代次数的情况下，输出第一比特序列的信源译码值，可以提高错误的译码结果 被检出的概率，从而提高系统性能。
图10-图12为本申请实施例提供的几种误块率性能的示意图。图10和图11为上述图5所示的通信方法的误块率(block error rate，BLER)性能的示意图。图12为上述图9所示的通信方法的误块率性能的示意图。
图10为图5所示的通信方法、与两种分离译码方案的误块率性能对比。结合图10，以信源长度A＝256、第四比特序列的长度N＝256、信源为P(0)＝0.89的伯努利信源、极化码译码的列表大小为32为例。图5所示的通信方法中，信道编码不含循环冗余校验(cyclic redundancy check，CRC)比特，利用原始信源进行校验。作为对比，考察了两种算术码和极化码分离译码方案，一种分离译码方案中，信道编码不采用CRC比特，另一种分离译码方案中，信道编码采用8位的信道CRC比特。可以看出，在大部分信噪比(signal-to-noise ratio，SNR)范围内，图5所示的通信方法能带来0.1～0.2dB左右的增益。
在某一信噪比下，误块率越低，表示该方法在信噪比下传输可靠度越高。对于某一方法的误块率曲线随信噪比的升高，下降得越快(斜率越高)，说明该方法能随信噪比的升高，更快得达到更高的传输可靠度。从图10中可以看出，在大部分(signal-to-noise ratio，SNR)范围内，图5所示的通信方法的译码性能更好。
图11为图5所示的通信方法、与两种分离译码方案的误块率性能对比。结合图11，以信源长度A＝256、第四比特序列的长度N＝256、信源为具有转移概率矩阵
Figure PCTCN2022120645-appb-000012
的一阶马尔科夫信源、极化码译码的列表大小为32为例。图5所示的通信方法中，信道编码不含循环冗余校验比特，利用原始信源进行校验。作为对比，考察了两种算术码和极化码分离译码方案，一种分离译码方案中，信道编码不采用CRC比特，另一种分离译码方案中，信道编码采用8位的信道CRC比特。从图11中可以看出，在大部分信噪比范围内，图5所示的通信方法的译码性能更好，图5所示的通信方法能带来0.1～0.2dB左右的增益。
图12为图9所示的通信方法、与两种分离译码方案的误块率性能对比。结合图12，以信源压缩的目标长度第一长度阈值K＝256、第四比特序列的长度N＝512、信源为具有转移概率矩阵
Figure PCTCN2022120645-appb-000013
的一阶马尔科夫信源、极化码译码的列表大小为32为例。图9所示的通信方法中，信道编码不含CRC比特，利用原始信源进行校验。作为对比，考察了两种算术码和极化码分离译码方案，一种分离译码方案中，信道编码不采用CRC比特，另一种分离译码方案中，信道编码采用8位的信道CRC比特。从图12中可以看出，在大部分信噪比范围内，图9所示的通信方法的译码性能更好，图9所示的通信方法能带来0.1～0.2dB左右的增益。
除了上述图5至图12所述的将部分原始信源比特映射到polar码信道编码相应位置来辅助译码，本申请的设计思想还可以扩展至其他方向，例如协议流程设计中，可以将某些字段映射到信道编码的部分比特位上。此处的映射可以是物理层某些字段对物理层某些比特位的映射，也可以是上层某些字段对物理层某些比特位的映射，本申请对此不做限制。
例如，本申请可以应用于(media access control，MAC)层到物理层的数据映射，从MAC层传输到物理层的传输块(transport block，TB)，可以进行例如循环冗余校验CRC编码、分段等操作，然后再进行信道编码，本申请对这些操作不做限制。信道编 码可以采用polar码编码。
在此过程中，可以将MAC协议数据单元(protocol data unit，PDU)中的某些字段，映射到物理层polar码编码时的信息比特位或者冻结比特位。
例如，将MAC PDU中的子头部(sub header)里的预留(reserved，R)字段映射到相应参与信道编码比特的信息比特位中，若译码到相应位置时，当前译码路径根据前面比特得到译码结果和R字段原始映射值不一致，说明当前路径译码出现错误，可以删除此条译码路径。
又例如，将MAC PDU中的sub header里的逻辑信道标识(logical channel identify，LCID)字段映射到信道编码信息位，如果信道译码译码到相应位置，求出的译码结果转换为LCID值，LCID值刚好属于LCID的Reversed值，那说明译码出现错误，可以删除此条译码路径。
又例如，在部分场景下，LCID的取值是基本固定的，比如在随机接入场景下，Msg3和Msg4就是属于公共控制信道(common control channel，CCCH)，也就是LCID＝0，该固定的LCID值可以映射到信道编码信息位上，这样信道译码时，可以通过对比实际映射位的译码结果和原始映射值来确定当前译码路径是否出现译码错误，确定是否需要删除当前译码路径。
需要说明的是，上面几种映射方案只是给出了本申请思想扩展的例子，实际上，本申请并不局限于以上几种映射方案，其他类型字段，例如后续标准新增字段，都可以做类似的映射，方法类似，本申请不做赘述。
总的来说，这样的映射方法可以使得在polar码译码时，当前译码结果和原始映射字段的值得以交叉对比检验，使得我们可以提前删除错误路径，提高译码性能。
本申请中，除特殊说明外，各个实施例之间相同或相似的部分可以互相参考。在本申请中各个实施例、以及各实施例中的各个实施方式/实施方法/实现方法中，如果没有特殊说明以及逻辑冲突，不同的实施例之间、以及各实施例中的各个实施方式/实施方法/实现方法之间的术语和/或描述具有一致性、且可以相互引用，不同的实施例、以及各实施例中的各个实施方式/实施方法/实现方法中的技术特征根据其内在的逻辑关系可以组合形成新的实施例、实施方式、实施方法、或实现方法。以下所述的本申请实施方式并不构成对本申请保护范围的限定。
以上结合图5-图12详细说明了本申请实施例提供的通信方法。以下结合图13-图14详细说明本申请实施例提供的通信装置。
图13为可用于执行本申请实施例提供的通信方法的一种通信装置的结构示意图。通信装置1300可以是接收端、或发送端，也可以是应用于接收端、或发送端中的芯片或者其他具有相应功能的部件。如图13所示，通信装置1300可以包括处理器1301。可选地，通信装置1300还可以包括存储器1302和收发器1303中的一个或多个。其中，处理器1301可以与存储器1302和收发器1303中的一个或多个耦合，如可以通过通信总线连接，处理器1301也可以单独使用。
下面结合图13对通信装置1300的各个构成部件进行具体的介绍：
处理器1301是通信装置1300的控制中心，可以是一个处理器，也可以是多个处理元件的统称。例如，处理器1301是一个或多个中央处理器(central processing unit， CPU)，也可以是特定集成电路(application specific integrated circuit，ASIC)，或者是被配置成实施本申请实施例的一个或多个集成电路，例如：一个或多个微处理器(digital signal processor，DSP)，或，一个或者多个现场可编程门阵列(field programmable gate array，FPGA)。
其中，处理器1301可以通过运行或执行存储在存储器1302内的软件程序，以及调用存储在存储器1302内的数据，执行通信装置1300的各种功能。
在具体的实现中，作为一种实施例，处理器1301可以包括一个或多个CPU，例如图13中所示的CPU0和CPU1。
在具体实现中，作为一种实施例，通信装置1300也可以包括多个处理器，例如图13中所示的处理器1301和处理器1304。这些处理器中的每一个可以是一个单核处理器(single-CPU)，也可以是一个多核处理器(multi-CPU)。这里的处理器可以指一个或多个通信设备、电路、和/或用于处理数据(例如计算机程序指令)的处理核。
可选地，存储器1302可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储通信设备，随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储通信设备，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储通信设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。存储器1302可以和处理器1301集成在一起，也可以独立存在，并通过通信装置1300的输入/输出端口(图13中未示出)与处理器1301耦合，本申请实施例对此不作具体限定。
示例性地，输入端口可用于实现上述任一方法实施例中由接收端、或发送端执行的接收功能，输出端口可用于实现上述任一方法实施例中由接收端、或发送端执行的发送功能。
其中，所述存储器1302可用于存储执行本申请方案的软件程序，并由处理器1301来控制执行。上述具体实现方式可以参考下述方法实施例，此处不再赘述。
可选地，收发器1303，用于与其他通信装置之间的通信。例如，通信装置1300为接收端时，收发器1303可以用于与发送端通信。又例如，通信装置1300为发送端时，收发器1303可以用于与接收端通信。
此外，收发器1303可以包括接收器和发送器(图13中未单独示出)。其中，接收器用于实现接收功能，发送器用于实现发送功能。收发器1303可以和处理器1301集成在一起，也可以独立存在，并通过通信装置1300的输入/输出端口(图13中未示出)与处理器1301耦合，本申请实施例对此不作具体限定。
需要说明的是，图13中示出的通信装置1300的结构并不构成对该通信装置的限定，实际的通信装置可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
其中，上述图5-图12中发送端的动作可以由图13所示的通信装置1300中的处理器1301调用存储器1302中存储的应用程序代码以指令发送端执行。
上述图5-图12中接收端的动作可以由图13所示的通信装置1300中的处理器1301调用存储器1302中存储的应用程序代码以指令接收端执行，本实施例对此不作任何限制。
当通信装置为发送端时，通信装置1300可执行上述方法实施例中的发送端所涉及的任一种或多种可能的设计方式；当通信装置为接收端时，通信装置1300可执行上述方法实施例中的接收端所涉及的任一种或多种可能的设计方式。
需要说明的是，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
图14为本申请实施例提供的另一种通信装置的结构示意图。为了便于说明，图14仅示出了该通信装置的主要部件。
该通信装置1400包括收发模块1401、和处理模块1402。该通信装置1400可以是前述方法实施例中的发送端或接收端。收发模块1401，也可以称为收发单元，用以实现上述任一方法实施例中由发送端或接收端执行的收发功能。
需要说明的是，收发模块1401可以包括接收模块和发送模块(图14中未示出)。其中，接收模块用于接收来自其他设备的数据和/或信令；发送模块用于向其他设备发送数据和/或信令。本申请对于收发模块的具体实现方式，不做具体限定。该收发模块可以由收发电路、收发机、收发器或者通信接口构成。
处理模块1402，可以用于实现上述任一方法实施例中由发送端或接收端执行的处理功能。该处理模块1402可以为处理器。
在本实施例中，该通信装置1400以采用集成的方式划分各个功能模块的形式来呈现。这里的“模块”可以指特定ASIC，电路，执行一个或多个软件或固件程序的处理器和存储器，集成逻辑电路，和/或其他可以提供上述功能的器件。在一个简单的实施例中，本领域的技术人员可以想到该通信装置1400可以采用图13所示的通信装置1300的形式。
比如，图13所示的通信装置1300中的处理器1301可以通过调用存储器1302中存储的计算机执行指令，使得上述方法实施例中的通信方法被执行。
具体的，图14中的收发模块1401和处理模块1402的功能/实现过程可以通过图13所示的通信装置1300中的处理器1301调用存储器1302中存储的计算机执行指令来实现。或者，图14中的处理模块1402的功能/实现过程可以通过图13所示的通信装置1300中的处理器1301调用存储器1302中存储的计算机执行指令来实现，图14中的收发模块1401的功能/实现过程可以通过图13中所示的通信装置1300中的收发器1303来实现。
由于本实施例提供的通信装置1400可执行上述通信方法，因此其所能获得的技术效果可参考上述方法实施例，在此不再赘述。
在一种可能的设计方案中，图14所示出的通信装置1400可适用于图1所示出的通信系统中，执行图5或图9所示的通信方法中的发送端的功能。
处理模块1402，用于对第一比特序列进行信源编码，得到第二比特序列。其中，第一比特序列的长度为A，A为大于0的整数，第二比特序列的长度为B，B为大于0的整数。
处理模块1402，还用于根据第二比特序列和第三比特序列，得到第四比特序列。其中，第三比特序列为第一比特序列中的C个比特，C为大于0且小于或等于A的整数，第四比特序列的长度为N，N为大于0的整数，第四比特序列包括一个或多个信息比特、和一个或多个冻结比特，第二比特序列处于第四比特序列的B个信息比特位上，第三比特序列处于第四比特序列的第一比特位上，第一比特位包括E个信息比特位和F个冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数。
处理模块1402，还用于对第四比特序列进行信道编码，得到第五比特序列。其中，第五比特序列的长度为N，N为大于0的整数。
收发模块1401，用于发送第五比特序列。
可选的，通信装置1400还可以包括存储模块(图14中未示出)，该存储模块存储有程序或指令。当处理模块1402执行该程序或指令时，使得通信装置1400可以执行图5或图9所示的通信方法中的发送端的功能。
需要说明的是，通信装置1400可以是发送端，也可以是可设置于发送端的芯片(系统)或其他部件或组件，本申请对此不做限定。
此外，通信装置1400的技术效果可以参考图5或图9所示的通信方法的技术效果，此处不再赘述。
在另一种可能的设计方案中，图14所示出的通信装置1400可适用于图1所示出的通信系统中，执行图5所示的通信方法中的接收端的功能。
其中，收发模块1401，用于接收待译码序列。其中，待译码序列的长度为N，N为大于0的整数，待译码序列为第五比特序列经过信道传输后的序列，第五比特序列为第四比特序列的信道编码值，待译码序列的第一位置与第四比特序列的第一比特位对应，第三比特序列处于第四比特序列的第一比特位上，第四比特序列的第一比特位包括E个信息比特位和F个冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数，第三比特序列为第一比特序列中的C个比特，第一比特序列的长度为A，A为大于0的整数，C为大于0且小于或等于A的整数。待译码序列的第二位置与第四比特序列的中第二比特序列占用的B个信息比特位对应，第二比特序列为第一比特序列的信源编码值，第二比特序列的长度为B，B为大于0的整数。第四比特序列的信道译码值包括第二比特序列的信道译码值和第三比特序列的信道译码值，第四比特序列的长度为N。
处理模块1402，用于对待译码序列进行信道译码，得到第四比特序列的信道译码值。其中，第四比特序列的信道译码值包括第二比特序列的信道译码值和第三比特序列的信道译码值，第四比特序列的长度为N。
处理模块1402，还用于对第二比特序列的信道译码值进行信源译码，得到第一比特序列的信源译码值。
需要说明的是，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
可选的，通信装置1400还可以包括存储模块(图14中未示出)，该存储模块存储有程序或指令。当处理模块1402执行该程序或指令时，使得通信装置1400可以执行图5所示的通信方法中的接收端的功能。
需要说明的是，通信装置1400可以是接收端，也可以是可设置于接收端的芯片(系统)或其他部件或组件，本申请对此不做限定。
此外，通信装置1400的技术效果可以参考图5所示的通信方法的技术效果，此处不再赘述。
在又一种可能的设计方案中，图14所示出的通信装置1400可适用于图1所示出的通信系统中，执行图9所示的通信方法中的接收端的功能。
其中，收发模块1401，用于接收待译码序列。其中，待译码序列为第五比特序列经过信道传输后的序列，第五比特序列为第四比特序列的信道编码值，待译码序列的第一位置与第四比特序列的第一比特位对应，第三比特序列处于第四比特序列的第一比特位上，第四比特序列的第一比特位包括C个信息比特位，第三比特序列为第一比特序列中的C个比特，第一比特序列的长度为A，A为大于0的整数，C为大于0且小于或等于A的整数。待译码序列的第二位置与第四比特序列的中第二比特序列占用的B个信息比特位对应，第二比特序列为第一比特序列的信源编码值，第二比特序列的长度为B，B为大于0的整数。
处理模块1402，用于对待译码序列进行第q次迭代信道译码，获得第四比特序列的信道译码值。其中，q为大于0的整数，第四比特序列的信道译码值包括第二比特序列的信道译码值和第三比特序列的信道译码值。
处理模块1402，还用于对第二比特序列的信道译码值进行第g次信源译码，得到第一比特序列的信源译码值。其中，g为大于0的整数，第一比特序列的信源译码值包括第三比特序列的信源译码值。
处理模块1402，还用于在第三比特序列的信道译码值与第三比特序列的信源译码值相同或q等于Q的情况下，输出第一比特序列的信源译码值。其中，Q为最大迭代次数，Q为大于0的整数。
需要说明的是，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
可选的，通信装置1400还可以包括存储模块(图14中未示出)，该存储模块存储有程序或指令。当处理模块1402执行该程序或指令时，使得通信装置1400可以执行图9所示的通信方法中的接收端的功能。
需要说明的是，通信装置1400可以是接收端，也可以是可设置于接收端的芯片(系统)或其他部件或组件，本申请对此不做限定。
此外，通信装置1400的技术效果可以参考图9所示的通信方法的技术效果，此处不再赘述。
本申请实施例提供一种通信系统。该通信系统包括：发送端和接收端。
其中，发送端用于执行上述方法实施例中发送端的动作，具体执行方法和过程可参照上述方法实施例，此处不再赘述。
接收端用于执行上述方法实施例中接收端的动作，具体执行方法和过程可参照上述方法实施例，此处不再赘述。
本申请实施例提供一种芯片系统，该芯片系统包括逻辑电路和输入/输出端口。其中，逻辑电路可用于实现本申请实施例提供的通信方法所涉及的处理功能，输入/输出 端口可用于本申请实施例提供的通信方法所涉及的收发功能。
示例性地，输入端口可用于实现本申请实施例提供的通信方法所涉及的接收功能，输出端口可用于实现本申请实施例提供的通信方法所涉及的发送功能。
示例性的，通信装置1300中的处理器可用于进行，例如但不限于，基带相关处理，通信装置1300中的收发器可用于进行，例如但不限于，射频收发。上述器件可以分别设置在彼此独立的芯片上，也可以至少部分的或者全部的设置在同一块芯片上。例如，处理器可以进一步划分为模拟基带处理器和数字基带处理器。其中，模拟基带处理器可以与收发器集成在同一块芯片上，数字基带处理器可以设置在独立的芯片上。随着集成电路技术的不断发展，可以在同一块芯片上集成的器件越来越多，例如，数字基带处理器可以与多种应用处理器(例如但不限于图形处理器，多媒体处理器等)集成在同一块芯片之上。这样的芯片可以称为系统芯片(system on chip)。将各个器件独立设置在不同的芯片上，还是整合设置在一个或者多个芯片上，往往取决于产品设计的具体需要。本发明实施例对上述器件的具体实现形式不做限定。
在一种可能的设计中，该芯片系统还包括存储器，该存储器用于存储实现本申请实施例提供的通信方法所涉及功能的程序指令和数据。
该芯片系统，可以由芯片构成，也可以包含芯片和其他分立器件。
本申请实施例提供一种计算机可读存储介质，该计算机可读存储介质存储有计算机程序或指令，当计算机程序或指令在计算机上运行时，使得本申请实施例提供的通信方法被执行。
本申请实施例提供一种计算机程序产品，该计算机程序产品包括：计算机程序或指令，当计算机程序或指令在计算机上运行时，使得本申请实施例提供的通信方法被执行。
应理解，在本申请实施例中的处理器可以是中央处理单元(central processing unit，CPU)，该处理器还可以是其他通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现成可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解，本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的随机存取存储器(random access memory，RAM)可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM) 和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
上述实施例，可以全部或部分地通过软件、硬件(如电路)、固件或其他任意组合来实现。当使用软件实现时，上述实施例可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令或计算机程序。在计算机上加载或执行所述计算机指令或计算机程序时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质。半导体介质可以是固态硬盘。
应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A,B可以是单数或者复数。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系，但也可能表示的是一种“和/或”的关系，具体可参考前后文进行理解。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a,b,或c中的至少一项(个)，可以表示：a,b,c,a-b,a-c,b-c,或a-b-c，其中a,b,c可以是单个，也可以是多个。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显 示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (34)

  1. 一种通信方法，其特征在于，包括：
    对第一比特序列进行信源编码，得到第二比特序列；其中，所述第一比特序列的长度为A，A为大于0的整数，所述第二比特序列的长度为B，B为大于0的整数；
    根据所述第二比特序列和第三比特序列，得到第四比特序列；其中，所述第三比特序列为所述第一比特序列中的C个比特，C为大于0且小于或等于A的整数，所述第四比特序列的长度为N，N为大于0的整数，所述第四比特序列包括一个或多个信息比特、和一个或多个冻结比特，所述第二比特序列处于所述第四比特序列的B个所述信息比特位上，所述第三比特序列处于所述第四比特序列的第一比特位上，所述第一比特位包括E个所述信息比特位和F个所述冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数；
    对所述第四比特序列进行信道编码，得到第五比特序列；其中，所述第五比特序列的长度为N，N为大于0的整数；
    发送所述第五比特序列。
  2. 根据权利要求1所述的通信方法，其特征在于，E等于C且F等于0，所述第一比特位满足第一原则，所述第一原则包括：所述第一比特位处于所述第四比特序列的自然序靠前的E个所述信息比特位上。
  3. 根据权利要求1所述的通信方法，其特征在于，F等于C且E等于0，所述第一比特位满足第二原则，所述第二原则包括：所述第四比特序列的所述第一比特位与待译码序列的第一位置对应，对所述待译码序列的所述第一位置的之前的值进行信道译码的结果进行信源译码后，能够获得所述第三比特序列的一个或多个比特的信源译码值，或者，所述第一比特位处于所述第四比特序列的自然序靠后的F个所述冻结比特位上。
  4. 根据权利要求1-3中任一项所述的通信方法，其特征在于，所述第三比特序列为所述第一比特序列中的C个比特，包括：所述第三比特序列为所述第一比特序列中的自然序靠前的C个比特。
  5. 根据权利要求1-4中任一项所述的通信方法，其特征在于，所述第三比特序列处于所述第四比特序列的第一比特位上，包括：所述加扰后的所述第三比特序列处于所述第四比特序列的所述第一比特位上，所述加扰后的所述第三比特序列是根据加扰序列和所述第三比特序列获得的。
  6. 一种通信方法，其特征在于，包括：
    接收待译码序列；其中，所述待译码序列的长度为N，N为大于0的整数，所述待译码序列为第五比特序列经过信道传输后的序列，所述第五比特序列为第四比特序列的信道编码值，所述待译码序列的第一位置与第四比特序列的第一比特位对应，所述第三比特序列处于所述第四比特序列的第一比特位上，所述第四比特序列的所述第一比特位包括E个所述信息比特位和F个所述冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数，所述第三比特序列为第一比特序列中的C个比特，所述第一比特序列的长度为A，A为大于0的整数，C为大于0且小于或等于A的整数；所述待译码序列的第二位置与所述第四比特序列的中所述第二比特序列占用 的B个信息比特位对应，所述第二比特序列为所述第一比特序列的信源编码值，所述第二比特序列的长度为B，B为大于0的整数；
    对所述待译码序列进行信道译码，得到所述第四比特序列的信道译码值；其中，所述第四比特序列的信道译码值包括所述第二比特序列的信道译码值和所述第三比特序列的信道译码值，所述第四比特序列的长度为N；
    对所述第二比特序列的信道译码值进行信源译码，得到所述第一比特序列的信源译码值。
  7. 根据权利要求6所述的通信方法，其特征在于，E等于C且F等于0，所述第四比特序列的所述第一比特位满足第一原则，所述第一原则包括：所述第一比特位处于所述第四比特序列的自然序靠前的E个所述信息比特位上。
  8. 根据权利要求7所述的通信方法，其特征在于，所述对所述待译码序列进行信道译码，得到所述第四比特序列的信道译码值，包括：
    所述信道译码的方式为串行抵消列表SCL译码方式，所述列表的数量为L，L为大于0的整数，c u_total的初始值等于0，若c u_total小于C，则执行下述第一信源信道操作：
    对所述待译码序列的第n-m位上的值至第n位上的值进行信道译码，得到第一译码结果；其中，所述第n-m位至所述第n位包括所述第一位置中的至少一个位置和/或所述第二位置中的b个位置，n-m为大于0的整数，m为大于0的整数，所述第一译码结果包括所述第二比特序列的b个比特的信道译码值和/或所述第三比特序列的至少一个比特的信道译码值，b为大于0且小于或等于B的整数；
    对所述第二比特序列的b个比特对应的信道译码值进行信源译码，得到所述第三比特序列的c t个比特的信源译码值；其中，c t为大于0且小于或等于C的整数；
    根据所述第三比特序列的c u个比特的信源译码值与所述第三比特序列的自然序对应的c u个比特的信道译码值，确定基于l条译码路径对所述待译码序列的第n+1位上的值至第N位上的值继续执行所述第一信源信道操作，并将c u计入c u_total；其中，c u为大于0的整数，l为小于或等于L的整数；
    若c u_total等于C且n小于N，则对所述待译码序列的第n+1位上的值至第N位上的值继续进行信道译码。
  9. 根据权利要求8所述的通信方法，其特征在于，所述根据所述第三比特序列的c u个比特的信源译码值与所述第三比特序列的自然序对应的c u个比特的信道译码值，确定基于l条译码路径对所述待译码序列的第n+1位上的值至第N位上的值继续执行所述第一信源信道操作，并将c u计入c u_total，包括：
    遍历所述L条译码路径，确定第一译码路径对应的所述第三比特序列c u个比特的信源译码值与所述第一译码路径对应的所述第三比特序列的自然序对应的c u个比特的信道译码值是否相同，并将c u计入c u_total；其中，所述第一译码路径为L条译码路径中的一个；
    若不相同，则确定删除所述第一译码路径，终止基于所述第一译码路径的所述第一信源信道操作；
    若相同，则确定所述l条译码路径包括所述第一译码路径。
  10. 根据权利要求6所述的通信方法，其特征在于，F等于C且E等于0，所述第一比特位满足第二原则，所述第二原则包括：所述第四比特序列的所述第一比特位与所述待译码序列的第一位置对应，对所述待译码序列的所述第一位置的之前的值进行信道译码的结果进行信源译码后，能够获得所述第三比特序列的一个或多个比特的信源译码值，或者，所述第一比特位处于所述第四比特序列的自然序靠后的F个所述冻结比特位上。
  11. 根据权利要求10所述的通信方法，其特征在于，所述对所述待译码序列进行信道译码，得到所述第四比特序列的信道译码值，包括：
    所述信道译码的方式为串行抵消列表SCL译码方式，所述列表的数量为L，L为大于0的整数，c t_total的初始值等于0，若c t_total小于C，则执行下述第二信源信道操作：
    对所述待译码序列的第n-m位上的值至第n位上的值进行信道译码，得到第二译码结果；其中，第n+1位为所述第一位置中的一个位置，n-m为大于0的整数，m为大于0的整数，所述第二译码结果包括所述第二比特序列的b个比特的信道译码值；
    对所述第二比特序列的b个比特的信道译码值进行信源译码，得到所述第三比特序列的c t个比特的信源译码值，并将c t计入c t_total；其中，c t为大于0且小于或等于C的整数，所述第三比特序列的c t个比特的信源译码值依次作为所述待译码序列的所述第一位置中的c t个位置上的信道译码值；
    若c t_total大于0且小于C，对所述待译码序列的所述第n+1位上的值至第N位上的值继续执行所述第二信源信道操作；
    若c t_total等于C且n小于N，对所述待译码序列的第n+1位上的值至第N位上的值继续进行信道译码。
  12. 根据权利要求6-11中任一项所述的通信方法，其特征在于，所述第三比特序列为第一比特序列中的C个比特，包括：所述第三比特序列为所述第一比特序列中的自然序靠前的C个比特。
  13. 一种通信方法，其特征在于，包括：
    接收待译码序列；其中，所述待译码序列包括为第五比特序列经过信道传输后的序列，所述第五比特序列为第四比特序列的信道编码值，所述待译码序列的第一位置与第四比特序列的第一比特位对应，所述第三比特序列处于所述第四比特序列的第一比特位上，所述第四比特序列的所述第一比特位包括C个信息比特位，所述第三比特序列为第一比特序列中的C个比特，所述第一比特序列的长度为A，A为大于0的整数，C为大于0且小于或等于A的整数；所述待译码序列的第二位置与所述第四比特序列的中所述第二比特序列占用的B个信息比特位对应，所述第二比特序列为所述第一比特序列的信源编码值，所述第二比特序列的长度为B，B为大于0的整数；
    对所述待译码序列进行第q次迭代信道译码，获得所述第四比特序列的信道译码值；其中，q为大于0的整数，所述第四比特序列的信道译码值包括所述第二比特序列的信道译码值和所述第三比特序列的信道译码值；
    对所述第二比特序列的信道译码值进行第g次信源译码，得到所述第一比特序列的信源译码值；其中，g为大于0的整数，所述第一比特序列的信源译码值包括所述 第三比特序列的信源译码值；
    在所述第三比特序列的信道译码值与所述第三比特序列的信源译码值相同或q等于Q的情况下，输出所述第一比特序列的信源译码值；其中，Q为最大迭代次数，Q为大于0的整数。
  14. 根据权利要求13所述的通信方法，其特征在于，所述方法还包括：
    在所述第三比特序列的信道译码值与所述第三比特序列的信源译码值不相同且q小于Q的情况下，对所述待译码序列进行第q+s次迭代信道译码，对第q+s次迭代信道译码结果中的所述第二比特序列的信道译码值进行第g+t次信源译码；其中，s为大于0的整数，t为大于0的整数。
  15. 根据权利要求13或14所述的通信方法，其特征在于，所述对所述第二比特序列的信道译码值进行第g次信源译码，得到所述第一比特序列的信源译码值，包括：
    在所述第四比特序列的信道译码值通过信道校验的情况下，对所述第二比特序列的信道译码值进行第g次信源译码，得到所述第一比特序列的信源译码值。
  16. 一种通信装置，其特征在于，包括：处理模块和收发模块；其中，
    所述处理模块，用于对第一比特序列进行信源编码，得到第二比特序列；其中，所述第一比特序列的长度为A，A为大于0的整数，所述第二比特序列的长度为B，B为大于0的整数；
    所述处理模块，还用于根据所述第二比特序列和第三比特序列，得到第四比特序列；其中，所述第三比特序列为所述第一比特序列中的C个比特，C为大于0且小于或等于A的整数，所述第四比特序列的长度为N，N为大于0的整数，所述第四比特序列包括一个或多个信息比特、和一个或多个冻结比特，所述第二比特序列处于所述第四比特序列的B个所述信息比特位上，所述第三比特序列处于所述第四比特序列的第一比特位上，所述第一比特位包括E个所述信息比特位和F个所述冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数；
    所述处理模块，还用于对所述第四比特序列进行信道编码，得到第五比特序列；其中，所述第五比特序列的长度为N，N为大于0的整数；
    所述收发模块，用于发送所述第五比特序列。
  17. 根据权利要求16所述的通信装置，其特征在于，E等于C且F等于0，所述第一比特位满足第一原则，所述第一原则包括：所述第一比特位处于所述第四比特序列的自然序靠前的E个所述信息比特位上。
  18. 根据权利要求16所述的通信装置，其特征在于，F等于C且E等于0，所述第一比特位满足第二原则，所述第二原则包括：所述第四比特序列的所述第一比特位与待译码序列的第一位置对应，对所述待译码序列的所述第一位置的之前的值进行信道译码的结果进行信源译码后，能够获得所述第三比特序列的一个或多个比特的信源译码值，或者，所述第一比特位处于所述第四比特序列的自然序靠后的F个所述冻结比特位上。
  19. 根据权利要求16-18中任一项所述的通信装置，其特征在于，所述第三比特序列为所述第一比特序列中的C个比特，包括：所述第三比特序列为所述第一比特序列中的自然序靠前的C个比特。
  20. 根据权利要求16-19中任一项所述的通信装置，其特征在于，所述第三比特序列处于所述第四比特序列的第一比特位上，包括：所述加扰后的所述第三比特序列处于所述第四比特序列的所述第一比特位上，所述加扰后的所述第三比特序列是根据加扰序列和所述第三比特序列获得的。
  21. 一种通信装置，其特征在于，包括：处理模块和收发模块；其中，
    所述收发模块，用于接收待译码序列；其中，所述待译码序列的长度为N，N为大于0的整数，所述待译码序列为第五比特序列经过信道传输后的序列，所述第五比特序列为第四比特序列的信道编码值，所述待译码序列的第一位置与第四比特序列的第一比特位对应，所述第三比特序列处于所述第四比特序列的第一比特位上，所述第四比特序列的所述第一比特位包括E个所述信息比特位和F个所述冻结比特位，E+F＝C，E为大于或等于0的整数，F为大于或等于0的整数,所述第三比特序列为第一比特序列中的C个比特，所述第一比特序列的长度为A，A为大于0的整数，C为大于0且小于或等于A的整数；所述待译码序列的第二位置与所述第四比特序列的中所述第二比特序列占用的B个信息比特位对应，所述第二比特序列为所述第一比特序列的信源编码值，所述第二比特序列的长度为B，B为大于0的整数；
    所述处理模块，用于对所述待译码序列进行信道译码，得到所述第四比特序列的信道译码值；其中，所述第四比特序列的信道译码值包括所述第二比特序列的信道译码值和所述第三比特序列的信道译码值，所述第四比特序列的长度为N；
    所述处理模块，还用于对所述第二比特序列的信道译码值进行信源译码，得到所述第一比特序列的信源译码值。
  22. 根据权利要求21所述的通信装置，其特征在于，E等于C且F等于0，所述第四比特序列的所述第一比特位满足第一原则，所述第一原则包括：所述第一比特位处于所述第四比特序列的自然序靠前的E个所述信息比特位上。
  23. 根据权利要求22所述的通信装置，其特征在于，所述信道译码的方式为串行抵消列表SCL译码方式，所述列表的数量为L，L为大于0的整数，c u_total的初始值等于0，若c u_total小于C，则所述处理模块，还用于执行下述第一信源信道操作：
    所述处理模块，还用于对所述待译码序列的第n-m位上的值至第n位上的值进行信道译码，得到第一译码结果；其中，所述第n-m位至所述第n位包括所述第一位置中的至少一个位置和/或所述第二位置中的b个位置，n-m为大于0的整数，m为大于0的整数，所述第一译码结果包括所述第二比特序列的b个比特的信道译码值和/或所述第三比特序列的至少一个比特的信道译码值，b为大于0且小于或等于B的整数；
    所述处理模块，还用于对所述第二比特序列的b个比特对应的信道译码值进行信源译码，得到所述第三比特序列的c t个比特的信源译码值；其中，c t为大于0且小于或等于C的整数；
    所述处理模块，还用于根据所述第三比特序列的c u个比特的信源译码值与所述第三比特序列的自然序对应的c u个比特的信道译码值，确定基于l条译码路径对所述待译码序列的第n+1位上的值至第N位上的值继续执行所述第一信源信道操作，并将c u计入c u_total；其中，c u为大于0的整数，l为小于或等于L的整数；
    若c u_total等于C且n小于N，则所述处理模块，还用于对所述待译码序列的第n+1 位上的值至第N位上的值继续进行信道译码。
  24. 根据权利要求23所述的通信装置，其特征在于，
    所述处理模块，还用于遍历所述L条译码路径，确定第一译码路径对应的所述第三比特序列c u个比特的信源译码值与所述第一译码路径对应的所述第三比特序列的自然序对应的c u个比特的信道译码值是否相同，并将c u计入c u_total；其中，所述第一译码路径为L条译码路径中的一个；
    若不相同，则所述处理模块，还用于确定删除所述第一译码路径，终止基于所述第一译码路径的所述第一信源信道操作；
    若相同，则所述处理模块，还用于确定所述l条译码路径包括所述第一译码路径。
  25. 根据权利要求21所述的通信装置，其特征在于，F等于C且E等于0，所述第一比特位满足第二原则，所述第二原则包括：所述第四比特序列的所述第一比特位与所述待译码序列的第一位置对应，对所述待译码序列的所述第一位置的之前的值进行信道译码的结果进行信源译码后，能够获得所述第三比特序列的一个或多个比特的信源译码值，或者，所述第一比特位处于所述第四比特序列的自然序靠后的F个所述冻结比特位上。
  26. 根据权利要求25所述的通信装置，其特征在于，
    所述信道译码的方式为串行抵消列表SCL译码方式，所述列表的数量为L，L为大于0的整数，c t_total的初始值等于0，若c t_total小于C，则所述处理模块，还用于执行下述第二信源信道操作：
    所述处理模块，还用于对所述待译码序列的第n-m位上的值至第n位上的值进行信道译码，得到第二译码结果；其中，第n+1位为所述第一位置中的一个位置，n-m为大于0的整数，m为大于0的整数，所述第二译码结果包括所述第二比特序列的b个比特的信道译码值；
    所述处理模块，还用于对所述第二比特序列的b个比特的信道译码值进行信源译码，得到所述第三比特序列的c t个比特的信源译码值，并将c t计入c t_total；其中，c t为大于0且小于或等于C的整数，所述第三比特序列的c t个比特的信源译码值依次作为所述待译码序列的所述第一位置中的c t个位置上的信道译码值；
    若c t_total大于0且小于C，所述处理模块，还用于对所述待译码序列的所述第n+1位上的值至第N位上的值继续执行所述第二信源信道操作；
    若c t_total等于C且n小于N，所述处理模块，还用于对所述待译码序列的第n+1位上的值至第N位上的值继续进行信道译码。
  27. 根据权利要求21-26中任一项所述的通信装置，其特征在于，所述第三比特序列为第一比特序列中的C个比特，包括：所述第三比特序列为所述第一比特序列中的自然序靠前的C个比特。
  28. 一种通信装置，其特征在于，包括：处理模块和收发模块；其中，
    所述收发模块，用于接收待译码序列；其中，所述待译码序列包括为第五比特序列经过信道传输后的序列，所述第五比特序列为第四比特序列的信道编码值，所述待译码序列的第一位置与第四比特序列的第一比特位对应，所述第三比特序列处于所述第四比特序列的第一比特位上，所述第四比特序列的所述第一比特位包括C个信息比 特位，所述第三比特序列为第一比特序列中的C个比特，所述第一比特序列的长度为A，A为大于0的整数，C为大于0且小于或等于A的整数；所述待译码序列的第二位置与所述第四比特序列的中所述第二比特序列占用的B个信息比特位对应，所述第二比特序列为所述第一比特序列的信源编码值，所述第二比特序列的长度为B，B为大于0的整数；
    所述处理模块，用于对所述待译码序列进行第q次迭代信道译码，获得所述第四比特序列的信道译码值；其中，q为大于0的整数，所述第四比特序列的信道译码值包括所述第二比特序列的信道译码值和所述第三比特序列的信道译码值；
    所述处理模块，还用于对所述第二比特序列的信道译码值进行第g次信源译码，得到所述第一比特序列的信源译码值；其中，g为大于0的整数，所述第一比特序列的信源译码值包括所述第三比特序列的信源译码值；
    所述处理模块，还用于在所述第三比特序列的信道译码值与所述第三比特序列的信源译码值相同或q等于Q的情况下，输出所述第一比特序列的信源译码值；其中，Q为最大迭代次数，Q为大于0的整数。
  29. 根据权利要求28所述的通信装置，其特征在于，
    所述处理模块，还用于在所述第三比特序列的信道译码值与所述第三比特序列的信源译码值不相同且q小于Q的情况下，对所述待译码序列进行第q+s次迭代信道译码，对第q+s次迭代信道译码结果中的所述第二比特序列的信道译码值进行第g+t次信源译码；其中，s为大于0的整数，t为大于0的整数。
  30. 根据权利要求28或29所述的通信装置，其特征在于，
    所述处理模块，还用于在所述第四比特序列的信道译码值通过信道校验的情况下，对所述第二比特序列的信道译码值进行第g次信源译码，得到所述第一比特序列的信源译码值。
  31. 一种通信装置，其特征在于，所述通信装置包括：处理器；所述处理器，用于执行如权利要求1-15中任一项所述的通信方法。
  32. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机程序或指令，当所述计算机程序或指令在计算机上运行时，使得如权利要求1-15中任一项所述的通信方法被执行。
  33. 一种计算机程序产品，其特征在于，所述计算机程序产品包括：计算机程序或指令，当所述计算机程序或指令在计算机上运行时，使得如权利要求1-15中任一项所述的通信方法被执行。
  34. 一种通信系统，其特征在于，包括发送端和接收端，其中所述发送端用于执行如权利要求1-5中任一项所述的通信方法，所述接收端用于执行6-15中任一项所述的通信方法。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103841065A (zh) * 2014-02-17 2014-06-04 清华大学 非正交多用户接入发送及联合接收解调译码系统及方法
WO2018098691A1 (zh) * 2016-11-30 2018-06-07 华为技术有限公司 一种控制信道生成方法、控制信道检测方法及相关设备
WO2018127234A1 (zh) * 2017-01-09 2018-07-12 电信科学技术研究院有限公司 一种极化码编译码方法及装置
CN108494527A (zh) * 2018-03-20 2018-09-04 清华大学 一种基于LoRa的数据发送和接收方法
CN109981226A (zh) * 2019-04-16 2019-07-05 厦门大学 一种联合信源信道编码系统的联合调度译码算法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103841065A (zh) * 2014-02-17 2014-06-04 清华大学 非正交多用户接入发送及联合接收解调译码系统及方法
WO2018098691A1 (zh) * 2016-11-30 2018-06-07 华为技术有限公司 一种控制信道生成方法、控制信道检测方法及相关设备
WO2018127234A1 (zh) * 2017-01-09 2018-07-12 电信科学技术研究院有限公司 一种极化码编译码方法及装置
CN108494527A (zh) * 2018-03-20 2018-09-04 清华大学 一种基于LoRa的数据发送和接收方法
CN109981226A (zh) * 2019-04-16 2019-07-05 厦门大学 一种联合信源信道编码系统的联合调度译码算法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
YIN, WEIWEI ET AL.: "Joint Source-Channel Decoding Based on Iterative Source Model Parameter Update", JOURNAL OF APPLIED SCIENCES, vol. 24, no. 04, 30 July 2006 (2006-07-30), pages 345 - 348, XP009545546 *

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