WO2022111575A1 - 传输数据的方法以及装置 - Google Patents

传输数据的方法以及装置 Download PDF

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Publication number
WO2022111575A1
WO2022111575A1 PCT/CN2021/133082 CN2021133082W WO2022111575A1 WO 2022111575 A1 WO2022111575 A1 WO 2022111575A1 CN 2021133082 W CN2021133082 W CN 2021133082W WO 2022111575 A1 WO2022111575 A1 WO 2022111575A1
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subsequences
column vector
column
vectors
subsequence
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PCT/CN2021/133082
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English (en)
French (fr)
Inventor
卢建民
汪凡
张长
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华为技术有限公司
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Priority to EP21897075.4A priority Critical patent/EP4236577A4/en
Publication of WO2022111575A1 publication Critical patent/WO2022111575A1/zh
Priority to US18/324,560 priority patent/US20230300900A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W74/00—Wireless channel access
    • H04W74/08—Non-scheduled access, e.g. ALOHA
    • H04W74/0833—Random access procedures, e.g. with 4-step access
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/251—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with block coding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/611—Specific encoding aspects, e.g. encoding by means of decoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0065—Serial concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1861—Physical mapping arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/04—Wireless resource allocation
    • H04W72/044—Wireless resource allocation based on the type of the allocated resource

Definitions

  • the present application relates to the field of communications, and in particular, to a method and apparatus for transmitting data.
  • Random access is a very critical technical issue in wireless communication and has a wide range of application scenarios. Such as used in user initial access, and in contention transmission.
  • massive Machine Type of Communication (mMTC) service is a very important service scenario, which can enable a variety of applications with different characteristics.
  • mMTC massive Machine Type of Communication
  • MTC machine type communication
  • the transmitted data packets are mainly small packets.
  • the present application provides a method and device for data transmission, which can improve the problems of low data transmission efficiency and small coding gain due to small data packets.
  • a first aspect provides a method for transmitting data, the method comprising: acquiring a first sequence, where the first sequence includes T first subsequences, where T is a positive integer; and determining T according to the T first subsequences encoding vectors, the number of non-zero elements of at least one encoding vector in the T encoding vectors is greater than or equal to 2, the T first subsequences are in one-to-one correspondence with the T encoding vectors, and the t-th encoding vector in the T encoding vectors has a one-to-one correspondence.
  • the positions of non-zero elements in a coded vector are determined according to the t 1 -th first subsequence, t 1 ⁇ [ 1 , T], where both t 1 and T are positive integers; according to one or more codebooks and the T coding vectors are generated, and T second subsequences are generated, wherein each first subsequence corresponds to a column vector group in the one or more codebooks, and at least one first subsequence in the T first subsequences
  • the column vector group corresponding to the sequence includes at least two column vectors; the T second subsequences are sent.
  • the number of non-zero elements of at least one of the T coding vectors determined according to the T first subsequences is greater than or equal to 2
  • the number of the T second subsequences determined according to the codebook and the coding vectors The column vector group corresponding to the at least one second subsequence includes at least two column vectors, that is, at least one first subsequence is mapped to at least two column vectors in the codebook, which has the technical effect of improving the codeword space.
  • the t 2 th second subsequence is obtained by multiplying the codebook E t2 and the t 2 th encoding vector, where the codebook E t2 is n rows A matrix of M columns, the t 2 coded vector is determined according to the t 2 first subsequence, and the length of the t 2 coded vector is equal to M, where t 2 ⁇ [1,T], t 2 , n and M are both positive integers, and the codebook E t2 is one of one or more codebooks.
  • any two column vectors in the two column vector groups corresponding to any two first subsequences do not overlap each other.
  • a first subsequence is mapped to at least two column vectors corresponding to the codebook, and any two column vectors in the column vector group corresponding to any two first subsequences do not overlap each other, and it is possible to It has the technical effects of increasing redundancy, additionally protecting the first subsequence, increasing coding gain, and improving the reliability of decoding.
  • At least two column vectors in the two column vector groups corresponding to any two first subsequences do not overlap each other.
  • a first subsequence is mapped to at least two column vectors corresponding to the codebook, and at least two column vectors in the column vector group corresponding to any two first subsequences do not overlap each other, and the To increase the information rate carried by each first subsequence, expand the codeword space, and the technical effect of the number of users that can be accommodated.
  • any two column vectors in the column vector group corresponding to the T 1 first subsequences do not overlap each other, and T At least two column vectors in the column vector group corresponding to the two first subsequences do not overlap each other, wherein any one of the T1 sequences to be sent and any one of the T2 sequences to be sent are to be sent.
  • the combination of two different methods can not only strengthen the protection of the important first subsequence and improve the technical effect of reliability, but also increase the transmission rate and increase the transmission rate of more users at the same time.
  • the combination of the two provides functional flexibility for the overall optimization of system performance.
  • a column vector group in the codebook corresponding to each first subsequence in the T first subsequences is one of the c column vector groups.
  • c is the value of M/g rounded up or down
  • g is the number of column vectors in the one column vector group
  • M is the number of columns in the codebook
  • g is greater than or equal to 1 and less than or an integer equal to M.
  • a column vector group in the codebook corresponding to each first subsequence in the T first subsequences is one of the c column vector groups.
  • outer code encoding is performed on the original information sequence to generate the first sequence.
  • a method for transmitting data comprising:
  • T second subsequences where the T second subsequences are generated by one or more codebooks and T encoding vectors, the T encoding vectors are generated according to the T first subsequences, and the T encoding vectors
  • the number of non-zero elements of at least one coding vector is greater than or equal to 2
  • the T first subsequences are in one-to-one correspondence with the T coding vectors
  • the position of t 1 is determined according to the t 1 th first subsequence, t 1 ⁇ [1, T], both t 1 and T are positive integers; the T second subsequences are performed according to the one or more codebooks.
  • each first subsequence corresponds to a column vector group in the one or more codebooks, and at least one of the T first subsequences is the first subsequence
  • the column vector group corresponding to the subsequence includes at least two column vectors.
  • T second subsequences are decoded with inner code according to one or more codebooks to obtain T first subsequences.
  • the column vector group includes at least two column vectors, which has the technical effect of improving the codeword space.
  • a column vector group in the codebook E t2 corresponding to the t 2 first subsequence is determined, wherein , t 2 ⁇ [1,T], t 2 is a positive integer, the codebook E t2 is one of the one or more codebooks; according to the codebook E t2 corresponding to the t 2 first subsequence A set of column vectors that determine the t 2 first subsequence.
  • the t2th second subsequence is detected, and when at least one column vector in a column vector group satisfies a preset condition, it is determined that the one column vector group is A column vector group in the codebook E t2 corresponding to the t2th first subsequence.
  • the t2th second subsequence is detected, and when any column vector in a column vector group satisfies a preset condition, it is determined that the column vector group is A column vector group in the codebook E t2 corresponding to the t2th first subsequence.
  • the combination of two different methods can not only strengthen the protection of the important first subsequence, avoid the undetectable subsequent blocks caused by missed detection, and improve the technical effect of decoding reliability, but also It will increase the transmission rate and have the technical effect of increasing more users to transmit at the same time.
  • the combination of the two provides the greatest functional flexibility for the overall optimization of system performance.
  • any two column vectors in the two column vector groups corresponding to any two first subsequences do not overlap each other.
  • a first subsequence is mapped to at least two column vectors corresponding to the codebook, and any two column vectors in the column vector group corresponding to any two first subsequences do not overlap each other, and it is possible to It has the technical effects of increasing redundancy, additionally protecting the first subsequence, increasing coding gain, and improving the reliability of decoding.
  • At least two column vectors in the two column vector groups corresponding to any two first subsequences do not overlap each other.
  • one first subsequence is mapped to at least two column vectors corresponding to the codebook, and at least two column vectors in the column vector group corresponding to any two first subsequences do not overlap each other, which can be expanded
  • the codeword space increases the information rate carried by each first subsequence and increases the number of users that can be accommodated.
  • the combination of two different methods can not only strengthen the protection of the important first subsequence and improve the technical effect of reliability, but also increase the transmission rate and the number of users that can be accommodated.
  • the combination of the two provides functional flexibility for the overall optimization of system performance.
  • a column vector group in the codebook corresponding to each first subsequence in the T first subsequences is one of the c column vector groups.
  • c is the value of M/g rounded up or down
  • g is the number of column vectors in the one column vector group
  • M is the number of columns in the codebook
  • g is greater than or equal to 1 and less than or an integer equal to M.
  • a column vector group in the codebook corresponding to each first subsequence in the T first subsequences is one of the c column vector groups.
  • outer code decoding is performed on the first sequence to generate an original information sequence.
  • a third aspect provides a communication device
  • the communication device may include modules or units corresponding to one-to-one execution of the methods/operations/steps/actions described in the first aspect
  • the modules or units may be hardware circuits, or
  • software can also be implemented in combination with hardware circuits and software.
  • the device includes:
  • a communication unit configured to acquire a first sequence, where the first sequence includes T first subsequences, where T is a positive integer; a processing unit, configured to determine T coding vectors according to the T first subsequences, the T The number of non-zero elements of at least one coding vector in the coding vector is greater than or equal to 2, the T first subsequences are in one-to-one correspondence with the T coding vectors, and the t 1 th coding vector in the T coding vectors is non-zero.
  • the position of the zero element is determined according to the t 1 th first subsequence, t 1 ⁇ [1, T], and both t 1 and T are positive integers; the processing unit is also used to The T encoding vectors generate T second subsequences, wherein each first subsequence corresponds to a column vector group in the codebook, and a column vector corresponding to at least one first subsequence in the T first subsequences
  • the group includes at least two column vectors; the communication unit is further configured to send the T second subsequences.
  • the processing unit is specifically configured to obtain the t 2 th second subsequence by multiplying the codebook E t2 and the t 2 th coding vector, wherein the The codebook E t2 is a matrix with n rows and M columns, the t 2 coded vector is determined according to the t 2 first subsequence, and the length of the t 2 coded vector is equal to M, where t 2 ⁇ [1, T], t 2 , n and M are all positive integers, and the codebook E t2 is one of the one or more codebooks.
  • any two column vectors in the column vector group corresponding to any two first subsequences do not overlap each other.
  • At least two column vectors in the column vector group corresponding to any two first subsequences do not overlap each other.
  • any two column vectors in the column vector group corresponding to the T 1 first subsequences do not overlap each other
  • T 2 At least two column vectors in the column vector group corresponding to the first subsequence do not overlap each other, wherein any one of the first subsequences of the T 1 first subsequences and any one of the first subsequences of the T 2 first subsequences
  • a column vector group in the codebook corresponding to each first subsequence in the T first subsequences is one of the c column vector groups.
  • c is the value of M/g rounded up or down
  • g is the number of column vectors in the one column vector group
  • M is the number of columns in the codebook
  • g is greater than or equal to 1 and less than or an integer equal to M.
  • a column vector group in the codebook corresponding to each second subsequence in the T second subsequences is one of the c column vector groups.
  • the processing unit before acquiring the first sequence, is further configured to perform outer code encoding on the original information sequence to generate the first sequence.
  • a fourth aspect provides a communication device
  • the communication device may include modules or units corresponding to one-to-one execution of the methods/operations/steps/actions described in the second aspect, the modules or units may be hardware circuits, or However, software can also be implemented in combination with hardware circuits and software.
  • the device includes:
  • a communication unit configured to acquire T second subsequences, wherein the T second subsequences are generated by one or more codebooks and T coding vectors, and the T coding vectors are generated according to the T first subsequences,
  • the number of non-zero elements of at least one of the T coding vectors is greater than or equal to 2, the T first subsequences are in one-to-one correspondence with the T coding vectors, and the t 1 th code in the T coding vectors
  • the position of non-zero elements in the vector is determined according to the first subsequence of t 1 , t 1 ⁇ [1, T], and both t 1 and T are positive integers;
  • a processing unit configured to perform inner code decoding on the T second subsequences according to the one or more codebooks to obtain the T first subsequences, wherein each first subsequence is associated with the one or more One column vector group in the codebook corresponds to, and the column vector group corresponding to at least one first subsequence in the T first subsequences includes at least two column vectors.
  • the processing unit is specifically configured to, by detecting the t2th second subsequence, determine the codebook E t2 corresponding to the t2th first subsequence A column vector group of , where t 2 ⁇ [1,T], t 2 is a positive integer, and the codebook E t2 is one of the one or more codebooks; according to the t 2 first subsequence A column vector group in the corresponding codebook E t2 determines the t 2 first subsequence.
  • the processing unit is further specifically configured to detect the t2th second subsequence, when at least one column vector in a column vector group satisfies a preset condition , and the one column vector group is determined to be a column vector group in the codebook E t2 corresponding to the t 2 th first subsequence.
  • the processing unit is further specifically configured to detect the t2th second subsequence, when any column vector in a column vector group satisfies a preset condition , and the one column vector group is determined to be a column vector group in the codebook E t2 corresponding to the t 2 th first subsequence.
  • any two column vectors in the two column vector groups corresponding to any two first subsequences do not overlap each other.
  • At least two column vectors in the two column vector groups corresponding to any two first subsequences do not overlap each other.
  • a column vector group in the codebook corresponding to each first subsequence in the T first subsequences is one of the c column vector groups.
  • c is the value of M/g rounded up or down
  • g is the number of column vectors in the one column vector group
  • M is the number of columns in the codebook
  • g is greater than or equal to 1 and less than or an integer equal to M.
  • a column vector group in the codebook corresponding to each first subsequence in the T first subsequences is one of the c column vector groups.
  • the processing unit is further specifically configured to perform outer code decoding on the first sequence to obtain the original information sequence.
  • a communication device in a fifth aspect, has the function of implementing the method in the above-mentioned first aspect and any possible implementation manners thereof.
  • This function can be implemented by hardware or by executing corresponding software by hardware.
  • the hardware or software includes one or more units corresponding to the above-mentioned functions.
  • the communication device when part or all of the function is implemented by hardware, includes: an input interface circuit for acquiring the first sequence; a logic circuit for according to one or more codebooks and T encoding vectors to generate T second subsequences.
  • the communication device may be a chip or an integrated circuit.
  • the communication device when part or all of the function is implemented by software, includes: a memory for storing a computer program; a processor for executing the computer program stored in the memory, when the computer program is stored When executed, the communication apparatus may implement the method for transmitting data as in any possible design of the first aspect and the first aspect.
  • the memory may be a physically separate unit, or may be integrated with the processor.
  • the communication device includes only a processor when part or all of the functionality is implemented in software.
  • the memory for storing the program is located outside the communication device, and the processor is connected to the memory through a circuit/wire for reading and running the program stored in the memory to execute the above-mentioned first aspect and any possible implementation of the first aspect The method of transferring data in .
  • a communication device in a sixth aspect, has the function of implementing the method in the second aspect and any possible implementation manners thereof.
  • This function can be implemented by hardware or by executing corresponding software by hardware.
  • the hardware or software includes one or more units corresponding to the above-mentioned functions.
  • the communication device when part or all of the function is implemented by hardware, includes: an input interface circuit for acquiring T second subsequences; a logic circuit for executing the second aspect above The decoding method; the output interface circuit is used to output the original information sequence.
  • the communication device may be a chip or an integrated circuit.
  • the communication device when part or all of the function is implemented by software, the communication device includes: a memory for storing a computer program; a processor for executing the computer program stored in the memory, when the computer program is stored When executed, the communication device can implement the decoding method as described in the second aspect.
  • the memory may be a physically separate unit, or may be integrated with the processor.
  • the communication device includes only a processor when part or all of the functionality is implemented in software.
  • the memory for storing the program is located outside the communication device, and the processor is connected to the memory through a circuit/wire for reading and running the program stored in the memory to execute the decoding method in the second aspect.
  • the communication device may be a chip or an integrated circuit.
  • the present application provides a network device including a transceiver, a processor and a memory.
  • the processor is used to control the transceiver to send and receive signals
  • the memory is used to store a computer program
  • the processor is used to call and run the computer program stored in the memory, so that the method in any possible implementation manner of the first aspect is implemented.
  • the present application provides a terminal device including a transceiver, a processor and a memory.
  • the processor is used to control the transceiver to send and receive signals
  • the memory is used to store a computer program
  • the processor is used to call and run the computer program stored in the memory, so that the method in any possible implementation manner of the second aspect is executed.
  • the present application provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, when the computer-readable storage medium runs on a computer, the first aspect or any possible implementation of the first aspect is method is executed.
  • the present application provides a computer program product, the computer program product includes computer program code, when the computer program code is run on a computer, the method in the above-mentioned first aspect and any possible implementation manner thereof is implement.
  • the present application provides a chip including a processor.
  • the processor is configured to read and execute the computer program stored in the memory, so as to execute the method in the first aspect or any possible implementation manner of the first aspect.
  • the chip further includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive the T first subsequences, and the processor obtains the T first subsequences from the communication interface, determines the T coding vectors, and generates the T first subsequences according to the one or more codebooks and the T coding vectors. Two subsequences; the communication interface outputs the encoded T second subsequences.
  • the communication interface may be an input-output interface.
  • the present application provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, when the computer-readable storage medium runs on a computer, the second aspect or any possible implementation manner of the second aspect is method is executed.
  • the present application provides a computer program product, the computer program product comprising computer program code, when the computer program code is run on a computer, the second aspect or the method in any possible implementation manner of the second aspect is enabled. be executed.
  • the present application provides a chip including a processor.
  • the processor is configured to read and execute the computer program stored in the memory, so as to execute the method in the above-mentioned second aspect or any possible implementation manner of the second aspect.
  • the chip further includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive the T second subsequences, and the processor obtains the T second subsequences from the communication interface, and uses the decoding method described in the second aspect to decode the T second subsequences to obtain The original message sequence; the communication interface outputs the original message sequence.
  • the communication interface may be an input-output interface.
  • the present application provides a communication system, including the network device of the fifth aspect and the terminal device of the sixth aspect.
  • FIG. 1 is an architectural diagram of a wireless communication system 100 .
  • FIG. 2 is a schematic diagram of the overall structure of a passive random access system.
  • FIG. 3 is a schematic diagram of outer code coding based on tree coding.
  • FIG. 4 is a schematic diagram of inner code coding based on passive multi-user sparse regression codes.
  • FIG. 5 is a schematic diagram of an operation of tree code-based outer code decoding
  • FIG. 6 is a schematic diagram of a mapping relationship provided by an embodiment of the present application.
  • FIG. 7 is a schematic flowchart of a method 700 for data transmission provided by an embodiment of the present application.
  • FIG. 8 is a schematic flowchart of a method 800 for data transmission provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an inner code encoding based on a passive multi-user sparse regression code provided by an embodiment of the present application.
  • FIG. 10 is a schematic flowchart of a data transmission method 1000 provided by an embodiment of the present application.
  • FIG. 11 is a schematic block diagram of a communication apparatus 1100 provided by this application.
  • FIG. 12 is a schematic structural diagram of a communication apparatus 1200 provided by the present application.
  • FIG. 13 is a schematic diagram of the internal structure of the processing device 1201 provided by the present application.
  • FIG. 14 is a schematic block diagram of a communication apparatus 1400 provided by this application.
  • FIG. 15 is a schematic structural diagram of a communication apparatus 1500 provided by this application.
  • FIG. 16 is a schematic diagram of the internal structure of the processing device 1502 provided by the present application.
  • FIG. 17 is a schematic structural diagram of a terminal device 1700 provided by this application.
  • FIG. 1 is an architectural diagram of a wireless communication system 100 .
  • the wireless communication system 100 may include at least one network device and one or more terminal devices.
  • a network device (111 as shown in FIG. 1 ) may wirelessly communicate with the one or more terminal devices (122 to 126 as shown in FIG. 1 ).
  • the wireless communication systems involved in this application include but are not limited to long term evolution (long term evolution, LTE) systems, LTE frequency division duplex (frequency division duplex, FDD) systems, LTE time division duplex (time division duplex, TDD) systems ), the three major application scenarios of 5th generation mobile networks (5G), namely enhanced mobile broadband (eMBB), high reliability and low latency communication (ultra reliable low latency communication, URLLC) and Enhance massive machine type communication (eMTC) or future communication systems, etc.
  • 5G enhanced mobile broadband
  • URLLC ultra reliable low latency communication
  • eMTC Enhance massive machine type communication
  • the terminal equipment involved in the embodiments of the present application may refer to a user equipment (user equipment, UE), a terminal (terminal), an access terminal, a subscriber unit, a subscriber station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user Terminal, terminal, wireless communication device, user agent or user equipment.
  • UE user equipment
  • terminal terminal
  • an access terminal a subscriber unit, a subscriber station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user Terminal, terminal, wireless communication device, user agent or user equipment.
  • the terminal device may also be a cellular phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), a wireless communication Functional handheld devices, computing devices or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, terminal devices in 5G networks, terminals in the future evolution of the public land mobile network (PLMN) equipment, virtual reality (VR) terminal equipment, augmented reality (AR) terminal equipment, wireless equipment in industrial control (industrial control), wireless equipment in unmanned driving (self driving), telemedicine ( Wireless devices in remote medical, wireless devices in smart grid, wireless devices in transportation safety, wireless devices in smart city, wireless devices in smart home equipment, etc., which are not limited in this application.
  • PLMN public land mobile network
  • VR virtual reality
  • AR augmented reality
  • Wireless devices in remote medical wireless devices in smart grid, wireless devices in transportation safety, wireless devices in smart city, wireless devices in smart home equipment, etc., which are not limited in this application.
  • the network device involved in this application may be a device for communicating with a terminal device.
  • the network device may be a base station, a device integrated with a base station and a base station controller, or other devices with similar communication functions.
  • the base station mentioned here can be an evolved base station (evolutional nodeB, eNB or eNodeB) in a long term evolution (LTE) system, or it can be a cloud radio access network (CRAN) scenario.
  • LTE long term evolution
  • CRAN cloud radio access network
  • the network device in this embodiment of the present application may include various forms of base stations, such as: a macro base station, a micro base station (also referred to as a small cell), a relay station, an access point, a 5G base station or a future base station, a transmission point (transmitting and receiving point, TRP), transmitting point (transmitting point, TP), mobile switching center and device-to-device (Device-to-Device, D2D), vehicle outreach (vehicle-to-everything, V2X), machine to A device that undertakes the function of a base station in machine-to-machine (M2M) communication, etc., is not limited in this embodiment of the present application.
  • a macro base station such as: a macro base station, a micro base station (also referred to as a small cell), a relay station, an access point, a 5G base station or a future base station, a transmission point (transmitting and receiving point, TRP), transmitting point (transmitting point
  • Wireless technology is used for communication between the network device and the terminal device in FIG. 1 .
  • the network device sends a signal, it is the sending end, and when the network device receives the signal, it is the receiving end.
  • the terminal device sends a signal, it is the transmitter, and when the terminal device receives the signal, it is the receiver.
  • FIG. 2 is a schematic diagram of the overall structure of a passive random access system. As shown in Figure 2, there are multiple terminal equipment access, for a certain terminal equipment i, assuming that the information (original information sequence) that it needs to send at a certain moment is MSG i, then first perform outer code encoding on it, where, The outer code encoding can use tree encoding.
  • FIG. 3 is a schematic diagram of outer code coding based on tree coding.
  • the original information sequence is first divided into T original information subsequences, wherein the number of bits included in each original information subsequence may be different.
  • the index of the original information subsequence starts from 0, that is, the number of the first original information subsequence is 0, and the numbers of the following subsequences increase in turn, then for the original information sequence contained in the n+1th original information subsequence It is denoted as ⁇ (n) and the number of bits is denoted as m n .
  • the outer code bit sequence is based on ⁇ (0) , ⁇ (1) , ..., ⁇ (n-1) , ⁇ (n) is encoded and generated, and the length is l n .
  • the outer code bit sequence may be equivalent to the parity bit sequence of the original information bit sequences of all previous n+1 original information subsequences including the n+1 th original information subsequence.
  • the length of the original information bits included in the former original information subsequence is the same, and the first original information subsequence does not include the outer code bit sequence.
  • FIG. 4 is a schematic diagram of inner code coding based on passive multi-user sparse regression codes.
  • T first sequences encoded by the outer code are obtained.
  • E*W is sent, where E is the codebook and is The independent and identically distributed matrix of n*M includes M column vectors of length n, and W is an M*1 matrix of length M, where W has 1 non-zero element.
  • W represents the bit sequence encoded by the outer code, in which only 1 row is not 0, and the other rows are 0.
  • the position of the row where the 1 is located represents the first sequence encoded by the outer code, which can be regarded as a kind of position modulation.
  • p is the length of the check bit sequence in a first sequence
  • s is a positive integer
  • p is greater than or equal to 0 Integer.
  • the transmitted signal can be regarded as T first sequences, each first sequence occupies n transmission resources, and the bit signal transmitted on the n resources just corresponds to a certain column in the matrix E vector.
  • the receiving end uses an approximate message passing (Approximate message passing, AMP) decoder to recover the bit sequence before the sparse regression code inner code encoding, and then Through the outer code decoder, the respective signals of each user are separated, wherein the outer code decoder can adopt tree decoding.
  • approximate message passing Approximate message passing, AMP
  • FIG. 5 is a schematic diagram of an operation of outer code decoding based on tree codes.
  • Figure 5(a) is stage 0, and node 1 is the root node of the tree structure;
  • Figure 5(b) is stage 1, verifying the parity constraints of all child nodes of the root node, and the second The child node 1 and child node 2 of the behavior shadow are the child nodes that satisfy the parity check constraint;
  • Figure 5(c) is stage 2, and the parity check constraints of all its child nodes are verified against the child node 1 and child node 2 of the second row.
  • the shadowed child nodes in the third row are the child nodes that satisfy the parity check constraint;
  • Figure 5(d) is the stage n-1, which only verifies the parity check constraints of the self-child nodes retained in the n-2 stage.
  • a node is a subsection that satisfies the n-1 stage parity check constraint, wherein the path indicated by the dotted line is an effective path decoded by the tree decoder.
  • the complete reception of a user's information is achieved through outer code and tree decoding search.
  • the order of tree search determines that nodes near the root have higher importance.
  • the outer code sequence at the front is short, for example, the first sequence often does not contain check bits. Therefore, if an earlier sequence is missed or falsely detected, the entire sequence may be unrecoverable.
  • the number of sequences is small due to the use of position modulation.
  • FIG. 6 is a schematic diagram of a mapping relationship involved in an embodiment of the present application.
  • the element set ⁇ x, y, z ⁇ , x, y, and z are respectively mapped to specific positions, and different elements can be mapped to the same position.
  • the main idea is that the same position can be mapped by multiple elements, and each element is mapped to multiple positions.
  • checking whether an element exists check all the positions that the element needs to be mapped to. When all the positions mapped by the element are recorded, it is judged that the element may exist, otherwise it is judged that it does not exist.
  • the first sequence represents the sequence of the original information sequence encoded by the outer code
  • the second sequence represents the sequence of the first sequence encoded by the inner code
  • FIG. 7 is a schematic flowchart of a method 700 for data transmission provided by an embodiment of the present application. Method 700 may be performed by a sender.
  • the outer code encoder After acquiring the original information sequence, the outer code encoder performs tree encoding on the original information sequence to obtain the first sequence.
  • the first sequence includes T first subsequences, and T is a positive integer.
  • S720 Perform inner code encoding on the first sequence to obtain a second sequence, and send the second sequence.
  • T first subsequences are encoded to obtain T second subsequences, and the T second subsequences are sent, wherein the T second subsequences constitute the second sequence.
  • the inner code encoder uses the method proposed in the embodiment of the present application to perform inner code encoding on the first sequence based on passive multi-user sparse regression codes, to obtain the second sequence. sequence.
  • S730 Acquire the second sequence, and perform inner code decoding on the second sequence.
  • the first sequence may be obtained by decoding the second sequence by using an Approximate Message Passing (AMP) decoder.
  • AMP Approximate Message Passing
  • the outer code decoder obtains the first sequence, and performs outer code decoding on the first sequence to obtain the original information sequence.
  • outer-code decoding is performed using a tree-code-based outer-code decoder.
  • the outer code decoder can restore the original information sequence of any terminal equipment.
  • the AMP decoder may decode multiple sequences originating from multiple users for multiple second subsequences. For multiple second subsequences, how to determine that each second subsequence originates from the same terminal device is crucial, and this function will be implemented by the outer code decoder.
  • the outer code sequence added to each first sequence is related to the information of all previous first subsequences, which can be regarded as a check sequence. Therefore, each first subsequence can be determined in this way. It belongs to the same original information sequence as a certain first sub-sequence before, so as to obtain the original information sequences of independent multiple terminal devices.
  • FIG. 8 is a schematic flowchart of a method 800 for data transmission provided by an embodiment of the present application. As shown in Figure 8, the specific process is as follows:
  • the inner code encoder obtains a first sequence encoded by the outer code encoder, where the first sequence includes T first subsequences, where T is a positive integer.
  • the inner code encoder determines T coding vectors according to the above-mentioned T first subsequences.
  • the number of non-zero elements of at least one of the T coding vectors is greater than or equal to 2
  • the T first subsequences are in one-to-one correspondence with the T coding vectors
  • the t 1st coding vector in the T coding vectors The position of the non-zero element is determined according to the t 1 th subsequence to be encoded, t 1 ⁇ [1, T], and both t 1 and T are positive integers.
  • the inner code encoder generates T second subsequences according to one or more codebooks and T encoding vectors.
  • the inner code encoder After generating T second subsequences, the inner code encoder sends T second subsequences to the inner code decoder.
  • FIG. 9 is a schematic diagram of an inner code encoding based on a passive multi-user sparse regression code provided by an embodiment of the present application.
  • a codebook E*coding vector W is sent, where the codebook E is an independent and identically distributed matrix with n rows and M columns.
  • the length of the vector W is equal to M, of which there are a n That is, there are a n non-zero elements, and a n is greater than or equal to 2.
  • W represents the first sequence encoded by the outer code, in which only the row of an is not 0 , and the other rows are all 0.
  • the position of the row where the an is located represents the first sequence after encoding by the outer code, which can be regarded as a kind of position modulation.
  • the transmitted signal can be regarded as T second subsequences.
  • Each second subsequence occupies n transmission resources, and the bit signals transmitted on the n resources just correspond to a certain column vector group in the matrix E, wherein a column vector group includes at least two column vectors, n, M, T All are positive integers.
  • one codebook may correspond to one coding vector, or may correspond to multiple coding vectors, which is not limited in this application.
  • T coding vectors are determined according to the T first subsequences, wherein the T first subsequences are in one-to-one correspondence with the T coding vectors, and the number of non-zero elements of at least one coding vector in the T coding vectors is greater than or equal to 2, the position of the non-zero element in the t1th coding vector is determined according to the t1th first subsequence, and the length of each coding vector is equal to M, where the t1th coding vector is the same as the t1th coding vector.
  • the first subsequence corresponds to t 1 ⁇ [1, T], where both t 1 and T are positive integers.
  • the number of non-zero elements may be the same or different, which is not limited in this application.
  • T second subsequences are generated according to the one or more codebooks and the T code vectors.
  • the t2th second subsequence is obtained by multiplying the codebook E t2 and the t2th encoding vector, and the t2th encoding vector is determined according to the t2th first subsequence, wherein,
  • the codebook E t2 is a matrix with n rows and M columns, t 2 ⁇ [1, T], and the codebook E t2 is one of one or more codebooks.
  • the inner code encoder After obtaining the T first subsequences, the inner code encoder encodes the T first subsequences, that is, generates T second subsequences according to one or more codebooks and T encoding vectors.
  • mapping relationship is that any two column vectors in the column vector group in the codebook corresponding to any two first subsequences do not overlap each other.
  • mapping relationship For a specific description of the mapping relationship, reference may be made to the description in S1002 below.
  • mapping relationship is that at least two column vectors in the two column vector groups that satisfy the mapping relationship with any two first subsequences do not overlap each other.
  • mapping relationship For a specific description of the mapping relationship, reference may be made to the description in S1002 below.
  • the mapping relationship is that any two column vectors in the column vector group in the codebook corresponding to each of the first k first subsequences do not overlap each other, and further , each first subsequence is mapped to a column vector group in the c column vector groups, and only has a mapping relationship with the first subsequence, and has no mapping relationship with other first subsequences; the k+1th to the Tthth At least two column vectors in a column vector group corresponding to each first subsequence in a subsequence do not overlap each other.
  • mapping relationship For a specific description of the mapping relationship, reference may be made to the description in S1002 below.
  • FIG. 10 is a schematic flowchart of a data transmission method 1000 provided by an embodiment of the present application. As shown in Figure 10, the specific steps are described as follows:
  • the inner code decoder first obtains T second subsequences, wherein the T second subsequences are generated by one or more codebooks and T coding vectors, and the T coding vectors are based on the T first subsequences.
  • the number of non-zero elements of at least one of the T coding vectors is greater than or equal to 2
  • the T first subsequences correspond to the T coding vectors one-to-one
  • the position of the non-zero elements in the t 1st coding vector is Determined according to the t 1 th first subsequence, the length of each coding vector in the T coding vectors is equal to M, and t 1 ⁇ [1, T], where M, t 1 and T are all positive integers;
  • S1002 Perform inner code decoding on the T second subsequences according to one or more codebooks to obtain T first subsequences.
  • the inner code decoder will decode the T second subsequences.
  • the inner code decoding is performed on the T second subsequences according to one or more codebooks to obtain the first sequence, that is, the T first subsequences.
  • each first subsequence corresponds to one column vector group in the codebook, and the column vector group corresponding to at least one first subsequence in the T first subsequences includes at least two column vectors.
  • a column vector group in the codebook E t2 corresponding to the t2th first subsequence is determined, and then according to the code corresponding to the t2th first subsequence A column vector group in this E t2 , determining the t 2 th first subsequence, where t 2 ⁇ [1, T], t 2 is a positive integer, and codebook E t2 is the one or more codebooks one of the.
  • the measurement iteration obtains a numerical value about the confidence of the existence of certain column vectors.
  • AMP approximate message passing
  • GAMP generalized approximate message passing
  • the t2th second subsequence is detected, and the AMP algorithm or the GAMP algorithm and other similar algorithms are used to determine which column vector in which column vector group in the codebook E t2 satisfies the preset condition, and determine which column vector satisfies the preset condition.
  • the column vector group to which the column vector belongs is a column vector group in the codebook E t2 corresponding to the t 2 th first subsequence.
  • the preset condition may be that the reliability value of the column vector in the column vector group is greater than the preset threshold, or it may be considered that the column vector with the highest reliability is the column vector that satisfies the preset condition, which is not discussed in this application. Do limit.
  • the second sequence can be regarded as an approximate weighted superposition of some column vectors in the codebook, so the received second sequence can be one-to-one with all the column vectors in the codebook Do correlation detection, and obtain the correlation value corresponding to each column vector, or the normalized correlation value, as a numerical measure of the credibility of whether a column vector exists.
  • the numerical measurement result of the reliability of the column vector is greater than the preset threshold, it can be considered that the column vector in the column vector group is a column vector that satisfies the preset condition.
  • the T first subsequences are determined according to the mapping relationship between the column vector groups that meet the preset conditions in the one or more codebooks and the T first subsequences.
  • the mapping relationship is that any two column vectors in the column vector group in the codebook corresponding to any two first subsequences do not overlap each other. Further, each first subsequence satisfies a mapping relationship with one column vector group in the c column vector groups in the codebook, and any column vector group in the c column vector groups includes at least two column vectors, and c is positive. Integer. It should be understood that the c column vectors in the codebook mean that the c column vector groups are composed of column vectors in the codebook.
  • mapping method of at least two column vectors of a column vector group in the codebook to the first subsequence can be consistent with the encoding end and the decoding end according to the standard pre-definition, or through signaling transmission. Consensus can also be achieved through other methods, which is not limited in this application.
  • a first subsequence and one column vector group in the c column vector groups satisfy a mapping relationship, wherein any two column vectors in the two column vector groups corresponding to any two first subsequences do not overlap each other. For example, suppose that the column vector group that satisfies the mapping relationship with the t1th first subsequence is the t1th column vector group, and the column vector group that satisfies the mapping relationship with the t2th first subsequence is the t2th column vector group If the values of the first subsequence t1 and the first subsequence t2 are different, then the column vector of the t1th column vector group and the column vector of the t2th column vector group are both Non-overlapping and non-overlapping column vectors belong to different groups of column vectors.
  • the obtained c is equal to 4.
  • a first subsequence is two bits, and in the first subsequence of two bits, different values of the first subsequence represent different ways of mapping column vector groups.
  • the number of column vector groups satisfying the mapping relationship between a first subsequence and the codebook is 4, wherein, there are 2 column vectors in each column vector group.
  • the relationship between a first subsequence and a column vector that satisfies the mapping condition in the codebook can be as shown in Table 1:
  • the first subsequence exists by detecting that at least one column vector in a column vector group of the c column vector groups satisfying a mapping relationship with a first subsequence satisfies a preset condition.
  • a mapping relationship with a first subsequence satisfies a preset condition.
  • Table 1 when it is detected that the column vector whose column vector sequence number is 1 or 2 satisfies the preset condition, it can be determined that the value of the first subsequence is 00. Thereby, the accuracy of decoding can be improved, and missed detection can be avoided.
  • the mapping relationship is that at least two column vectors in the two column vector groups that satisfy the mapping relationship with any two first subsequences do not overlap each other. Further, each first subsequence satisfies a mapping relationship with one column vector group in the c column vector groups in the codebook, and any column vector group in the c column vector groups includes at least two column vectors, and c is positive. Integer. It should be understood that the c column vectors in the codebook mean that the c column vector groups are composed of column vectors in the codebook.
  • mapping method of at least two column vectors of a column vector group in the codebook to the first subsequence can be consistent with the encoding end and the decoding end according to the standard pre-definition, or through signaling transmission. Consensus can also be achieved through other methods, which is not limited in this application.
  • a first subsequence satisfies a mapping relationship with one column vector group in the c column vector groups, and the mapping relationship includes at least two column vectors in the two column vector groups in the codebook where any two first subsequences satisfy the mapping relationship do not overlap each other.
  • c 2 k
  • k is log 2 p rounded up or down
  • log 2 p ⁇ s, s is the length of a first sequence
  • b is the number of non-zero elements in the encoding vector
  • b and s are both positive integers.
  • the number of column vector groups satisfying the mapping relationship between a first subsequence and the codebook is 4, wherein, there are 2 column vectors in each column vector group.
  • the relationship between a first subsequence and a column vector that satisfies the mapping condition in the codebook can be as shown in Table 2:
  • the mechanism for determining the existence of the first subsequence can be determined.
  • Table 2 it is necessary to simultaneously detect that the column vectors whose sequence numbers are 1 and 3 satisfy the preset condition, so that the value of the first subsequence can be determined as 001. Therefore, the bit information rate carried by each first subsequence can be increased, the codeword space can be increased, and more users can transmit simultaneously.
  • the mapping relationship is that any two column vectors in the column vector group in the codebook corresponding to each of the first k first subsequences do not overlap each other, and further , each first subsequence is mapped to a column vector group in the c column vector groups, and only has a mapping relationship with the first subsequence, and has no mapping relationship with other first subsequences; the k+1th to the Tthth At least two column vectors in a column vector group corresponding to each first subsequence in a subsequence do not overlap each other.
  • One first subsequence in the first k first subsequences of group mapping, c 1 f(M 1 /g), f(M 1 /g) is rounding up or rounding down M 1 /g
  • g is the number of column vectors in a column vector group in the codebook satisfying the mapping relationship, where g ⁇ (0, M 1 ], g is an integer; the first subsequence from k+1 to T satisfies the mapping At least two column vectors in the column vector group of the c 2 column vector groups
  • a first subsequence includes an information bit sequence and a check bit sequence, wherein the length of the information bit sequence is h, the length of the check bit sequence is f, h is a positive integer, and f is an integer greater than or equal to 0.
  • mapping method of the first subsequence to at least two column vectors of a column vector group in the codebook can be consistent with the encoding end and the decoding end according to the standard pre-definition, or be maintained through signaling transmission. Consensus can also be achieved through other methods, which is not limited in this application.
  • Mechanisms For example, in Table 3, for the first first subsequence, it can be determined that the value of the first subsequence is 1 only when the column vector whose sequence number is 3 or 4 is detected; for the second subsequence For the first subsequence, it is necessary to simultaneously detect the column vectors whose sequence numbers are 6 and 7, so that the value of the first subsequence can be determined as 011.
  • the bit information rate carried by each first subsequence can be increased, the codeword space can be increased, more users can be supported for simultaneous transmission, and the flexibility of the system can be enhanced.
  • the data transmission method provided by the present application has been described in detail above with reference to FIG. 1 to FIG. 10 .
  • the receiving end or called the decoding end
  • the second sequence is received from the sending end (or called the encoding end).
  • the present application provides a method for data transmission, so that the receiving end can perform decoding in units of T second subsequences instead of decoding in units of bits, and a large number of simulation results show that the decoding performance is obtained. uplifted. For example, the decoding delay is reduced, and the bit error rate is reduced.
  • the following describes the communication apparatus, encoding apparatus, network equipment and terminal equipment provided by the present application with reference to FIG. 11 to FIG. 17 .
  • FIG. 11 is a schematic block diagram of a communication apparatus 1100 provided by the present application. As shown in FIG. 11 , the apparatus 1100 includes a processing unit 1110 and a communication unit 1120 .
  • the processing unit 1110 is configured to determine T coding vectors according to the T first subsequences; and generate T second subsequences according to one or more codebooks and the T coding vectors.
  • the communication unit 1120 is configured to acquire the T first subsequences and send the T second subsequences generated by the processing unit 1110 .
  • FIG. 12 is a schematic structural diagram of a communication apparatus 1200 provided by the present application.
  • the communication device 1200 is used to realize the function of encoding, and the communication device 1200 includes:
  • the processing device 1201 is configured to determine T coding vectors according to the T first subsequences; and generate T second subsequences according to one or more codebooks and the T coding vectors.
  • the transceiver 1202 is configured to acquire the first sequence and send the T second subsequences.
  • the transceiver is connected to the antenna 1203 .
  • the processing device 1201 may be a processor, a chip or an integrated circuit.
  • the present application further provides a processing apparatus 1201, which is used to implement the data transmission method of the above method embodiment.
  • a processing apparatus 1201 which is used to implement the data transmission method of the above method embodiment.
  • Part or all of the processes of the data transmission method 800 in this embodiment of the present application may be implemented by hardware, or may also be implemented by software.
  • the above-mentioned processing device 1201 may be a processor.
  • FIG. 13 is a schematic diagram of the internal structure of the processing device 1201 .
  • the processing device 1201 includes:
  • Input interface circuit 1211 for acquiring T first subsequences
  • the logic circuit 1212 is configured to determine T coding vectors according to the T first subsequences; and generate T second subsequences according to one or more codebooks and the T coding vectors.
  • the output interface circuit 1213 is used for outputting the T second subsequences.
  • the above-mentioned logic circuit 1212 may be used to execute the data transmission methods described in the various embodiments of the present application. For the detailed process, refer to the descriptions in the above method embodiments, which will not be repeated here.
  • part or all of the processes of the method 800 for data transmission provided in this application can also be implemented by software.
  • the processing device 1201 may be a processor, and the processor is configured to execute the computer program stored in the memory.
  • the processor executes the data transmission method in the above method embodiment.
  • the memory may be a physically separate unit.
  • the memory can also be integrated with the processor, which is not limited in this application.
  • the processing device 1201 may only include a processor.
  • the processor is connected to the memory through circuits/wires for reading and executing computer programs stored in the memory.
  • the processing device 1201 further includes a memory.
  • the chip may further include an input interface and an output interface.
  • the input interface is used to receive a first sequence of inputs.
  • the output interface is used to output the T second subsequences.
  • the present application further provides a communication device 1400 .
  • the communication device 1400 is used to perform the method 1000 described above.
  • FIG. 14 is a schematic block diagram of a communication apparatus 1400 provided by the present application.
  • the communication device 1400 includes a communication unit 1401 and a processing unit 1402 .
  • the communication unit 1401 is configured to receive T second subsequences from the transmitting end, where T is a positive integer.
  • the processing unit 1402 is configured to perform inner code decoding on the T second subsequences according to one or more codebooks to obtain T first subsequences.
  • the above-mentioned communication apparatus 1400 may be used to execute the data transmission methods in the various embodiments of the present application.
  • FIG. 15 is a schematic structural diagram of a communication apparatus 1500 provided by the present application.
  • the communication device 1500 is used for realizing the function of decoding, and the decoding device 1500 includes:
  • a transceiver 1501, configured to receive T second subsequences from the transmitter
  • the processing device 1502 is configured to perform inner code decoding on the T second subsequences according to one or more codebooks to obtain T first subsequences.
  • the transceiver 1501 is connected to the antenna 1503 .
  • the processing device 1502 may be a processor, a chip or an integrated circuit.
  • the present application also provides a processing device 1502 for implementing the above decoding method.
  • Part or all of the processes of the decoding method in the embodiments of the present application may be implemented by hardware, or may also be implemented by software.
  • the above-mentioned processing device 1502 may be a processor.
  • the above-mentioned processing apparatus 1502 may also be as shown in FIG. 16 .
  • FIG. 16 is a schematic diagram of the internal structure of the processing device 1502 .
  • the processing device 1502 includes: an input interface circuit 1521 , a logic circuit 1522 and an input interface circuit 1523 .
  • Input interface circuit 1521 for acquiring T second subsequences
  • a logic circuit 1522 configured to perform inner code decoding on the T second subsequences according to one or more codebooks to obtain the T first subsequences;
  • the logic circuit 1522 is further configured to perform outer code decoding on the T first subsequences to obtain the original information sequence;
  • the output interface circuit 1523 is used for outputting the original information sequence.
  • the processing device 1502 may be a processor, and the processor is configured to execute the computer program stored in the memory, and when the computer program is executed, the processor executes the above decoding method.
  • the memory may be a physically separate unit.
  • the memory can also be integrated with the processor, which is not limited in this application.
  • the processing device 1502 only includes a processor.
  • the processor is connected to the memory through circuits/wires for reading and executing computer programs stored in the memory.
  • the processing device 1502 further includes a memory.
  • the chip may further include an input interface and an output interface.
  • the input interface is used to receive the input bit sequence to be decoded.
  • the output interface is used to output the decoding result.
  • the data transmission method provided in this application may be executed by the sending end.
  • the network device 111 when the network device 111 sends a signal, the network device 111 is the sending end.
  • the terminal device When any one of the terminal devices 121 to 126 sends a signal, the terminal device is the sending end. Therefore, the present application further provides a network device and a terminal device below, and the network device and the terminal device have the function of implementing the above data transmission method.
  • FIG. 17 is a schematic structural diagram of a terminal device 1700 provided by the present application.
  • the terminal device 1700 includes: one or more processors 1710 , one or more memories 1720 , and one or more transceivers 1730 .
  • the processor 1710 is used to control the transceiver 1730 to send and receive signals
  • the memory 1720 is used to store a computer program
  • the processor 1710 is used to call and run the computer program from the memory 1720 to execute the corresponding flow of the data transmission method 700 provided in this application .
  • details are not repeated here.
  • the present application provides a computer-readable storage medium, where computer instructions are stored in the computer-readable storage medium, and when the computer instructions are executed on the computer, the computer is made to execute the corresponding data transmission method 700 of the embodiments of the present application. operations and/or processes.
  • the present application also provides a computer program product, the computer program product includes computer program code, when the computer program code runs on a computer, the computer program code enables the computer to perform corresponding operations and/or processes of the data transmission method of the embodiments of the present application.
  • the present application also provides a chip including a processor.
  • the processor is configured to read and execute the computer program stored in the memory, so as to perform corresponding operations and/or processes of the data transmission method provided by the present application.
  • the chip further includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive the bit sequence to be encoded, and the processor obtains the information bit sequence from the communication interface, and uses the data transmission method of the embodiment of the present application to perform data processing on the information bit sequence; the communication interface outputs the encoded bit sequence .
  • the communication interface may be an input-output interface.
  • the present application provides a computer-readable storage medium, where computer instructions are stored in the computer-readable storage medium, and when the computer instructions are executed on a computer, the computer can perform corresponding operations and/or corresponding operations of the data transmission method of the embodiments of the present application. process.
  • the present application also provides a computer program product, the computer program product includes computer program code, when the computer program code is run on a computer, the computer program code enables the computer to perform corresponding operations and/or processes of the data transmission method of the embodiments of the present application.
  • the present application also provides a chip including a processor.
  • the processor is configured to read and execute the computer program stored in the memory, so as to execute corresponding operations and/or processes of the data transmission method provided by the application.
  • the chip further includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive the T second subsequences, and the processor obtains the T second subsequences from the communication interface, and adopts the method 1000 for transmitting data in this embodiment of the present application to perform a pairing of the T second subsequences according to one or more codebooks.
  • the second subsequence is subjected to inner code decoding to obtain T first subsequences.
  • the communication interface may be an input-output interface.
  • each step of the above-mentioned method can be completed by a hardware integrated logic circuit in a processor or an instruction in the form of software.
  • the steps of the foregoing method embodiments may be directly embodied as executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.
  • the software modules may be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media mature in the art.
  • the storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware.
  • the chip described in the embodiments of the present application may be a field-programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central A processor (central processor unit, CPU), a network processor (Network Processor, NP), a digital signal processing circuit (digital signal processor, DSP), or a microcontroller (micro controller unit, MCU, programmable controller ( programmable logic device, PLD) or other integrated chips.
  • FPGA field-programmable gate array
  • ASIC application specific integrated circuit
  • SoC system on chip
  • CPU central processor unit, CPU
  • NP Network Processor
  • NP digital signal processing circuit
  • DSP digital signal processor
  • microcontroller microcontroller unit, MCU, programmable controller ( programmable logic device, PLD) or other integrated chips.
  • the processor in the embodiment of the present application may be an integrated circuit chip, which has signal processing capability.
  • each step of the above method embodiments may be completed by a hardware integrated logic circuit in a processor or an instruction in the form of software.
  • a processor may be a general purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components.
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the steps of the methods disclosed in the embodiments of the present application may be directly embodied as executed by a hardware coding processor, or executed by a combination of hardware and software modules in the coding processor.
  • the software modules may be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media mature in the art.
  • the storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware.
  • the memory in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically programmable Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be random access memory (RAM), which acts as an external cache.
  • RAM random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous DRAM
  • SDRAM double data rate synchronous dynamic random access memory
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronous link dynamic random access memory
  • direct rambus RAM direct rambus RAM
  • the apparatus embodiments described above in this application are only illustrative.
  • the division of the units is only a logical function division, and there may be other division manners in actual implementation.
  • multiple units or components may be combined or integrated into another system, or some features may be omitted, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present application.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable storage medium.
  • the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.

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Abstract

本申请提供了一种传输数据的方法及装置，该方法包括：获取第一序列，所述第一序列包括T个第一子序列；根据所述T个第一子序列，确定T个编码向量；根据一个或多个码本和所述T个编码向量，生成T个第二子序列，其中，每个第一子序列与所述一个或多个码本中的一个列向量组对应，所述T个第一子序列中至少一个第一子序列对应的所述列向量组包括至少两个列向量；发送所述T个第二子序列。本申请提供的方案可以改善因为数据包较小，导致数据传输效率低，编码增益小的问题，起到提升码字空间的技术效果。

Description

传输数据的方法以及装置
本申请要求于2020年11月30日提交中国国家知识产权局、申请号为202011380672.1、申请名称为“传输数据的方法以及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种传输数据的方法和装置。
背景技术
随机接入在无线通信中是非常关键的技术问题，有广泛的应用场景。如用在用户初始接入上，以及在竞争传输中。在无线通信中，大规模机器通信(massive Machine Type of Communication,mMTC)业务是非常重要的业务场景，可以使能多种特征不同的应用。在很多mMTC业务中，存在大量有可能进行通信的机器类型终端，但是一个机器类通信(machine type communication，MTC)终端可能仅需要在个别时刻传输，而同时需要进行传输的MTC终端数量比较少。此外，传输的数据包以小包为主。在这类场景中，如果按照4G(4th Generation)等通信系统中通常采用的，随机接入-请求-授权-传输的流程，因为数据包很小，数据传输的效率将会非常低，传输的时延也将增大。较为高效的做法是采用免授权随机接入方案，在初始竞争的随机接入阶段即完成数据传输。小包数据对传统方案的影响还体现在编码码长较短时，编码增益明显减小，距离香农的理论界间距离较大。
为了解决这些问题，近些年学术界进行了许多理论研究。目前较好的一类方案是基于无源随机接入的数据传输。这种方案将数据调制、编码与竞争随机接入进行联合优化设计，取得了较好的理论性能。基于稀疏回归码(Sparse regression code,SPARC)内码与树码(Tree code)级联的无源随机接入是其中一种方案。然而，这类方案因为其特殊的设计，存在靠前序列如果漏检或者误检，可能造成整个序列无法恢复。此外，对于激活率过低的场景，这种方案的信息传输速率相对较低，码字的数量较少。而且该方案中，支持的最大同时激活数目也存在限制，对于激活率很高的场景也不适用。
发明内容
本申请提供一种数据传输的方法和装置，能够改善因为数据包较小，导致数据传输效率低，编码增益小的问题。
第一方面，提供了一种传输数据的方法，该方法包括：获取第一序列，该第一序列包括T个第一子序列，T为正整数；根据该T个第一子序列，确定T个编码向量，该T个编码向量中至少一个编码向量的非零元素的数量大于或者等于2，该T个第一子序列与该T个编码向量一一对应，T个编码向量中的第t 1个编码向量中非零元素的位置是根据第t 1个第一子序列确定的，t 1∈[1,T]，t 1和T均为正整数；根据一个或多个码本和该T个编码 向量，生成T个第二子序列，其中，每个第一子序列与该一个或多个码本中的一个列向量组对应，该T个第一子序列中至少一个第一子序列对应的该列向量组包括至少两个列向量；发送该T个第二子序列。
在本技术方案中，根据T个第一子序列确定的T个编码向量中至少一个编码向量的非零元素的数量大于或者等于2，根据码本和编码向量确定的T个第二子序列中至少一个第二子序列对应的列向量组包括至少两个列向量，也就是，至少一个第一子序列映射为码本中的至少两个列向量，起到了提升码字空间的技术效果。
结合第一方面，在第一方面的某些实现方式中，通过码本E t2与第t 2个编码向量相乘得到第t 2个第二子序列，其中，该码本E t2为n行M列的矩阵，该第t 2个编码向量根据第t 2个第一子序列确定，该第t 2个编码向量的长度等于M，其中，t 2∈[1,T]，t 2、n和M均为正整数，码本E t2为一个或多个码本中的一个。
结合第一方面，在第一方面的某些实现方式中，任意两个第一子序列对应的两个列向量组中的任意两个列向量互不重叠。
在本技术方案中，将一个第一子序列映射到码本对应的至少两个列向量，并且任意两个第一子序列对应的该列向量组中的任意两个列向量互不重叠，可以起到增加冗余，对第一子序列进行额外保护，增大编码增益，以及提升译码的可靠性的技术效果。
结合第一方面，在第一方面的某些实现方式中，任意两个第一子序列对应的两个列向量组中的至少两个列向量互不重叠。
在本技术方案中，将一个第一子序列映射到码本对应的至少两个列向量，并且任意两个第一子序列对应的列向量组中的至少两个列向量互不重叠，可以起到增加每个第一子序列承载的信息速率，扩大码字空间，以及可容纳的用户数的技术效果。
结合第一方面，在第一方面的某些实现方式中，该T个第一子序列中，T 1个第一子序列对应的该列向量组中的任意两个列向量互不重叠，T 2个第一子序列对应的该列向量组中的至少两个列向量互不重叠，其中，该T 1个待发送序列中任意一个待发送序列与该T 2个待发送序列中任意一个待发送序列为不同的序列，T＝T 1+T 2。
在本技术方案中，通过两种不同的方式的结合，不仅可以对重要的第一子序列起到加强保护，提升可靠性的技术效果，还会增加传输速率，增加更多的用户同时传输的技术效果，二者的结合为整体优化系统性能提供了功能上的灵活性。
结合第一方面，在第一方面的某些实现方式中，该T个第一子序列中的每个第一子序列对应的该码本中的一个列向量组为c个列向量组中的一个，其中，c为M/g向上取整或者向下取整的值，g为该一个列向量组中列向量的数量，M为该码本的列数，g为大于或等于1且小于或等于M的整数。
结合第一方面，在第一方面的某些实现方式中，该T个第一子序列中的每个第一子序列对应的该码本中的一个列向量组为c个列向量组中的一个，其中，c＝2 k，k为log 2p向上取整或者向下取整的值，p等于
Figure PCTCN2021133082-appb-000001
b为该一个列向量组中列向量的数量，M为该码本的列数，其中，b为大于或等于1且小于或等于M的整数。
结合第一方面，在第一方面的某些实现方式中，对原始信息序列进行外码编码，生成该第一序列。
第二方面，提供了一种传输数据的方法，该方法包括：
获取T个第二子序列，其中，该T个第二子序列由一个或多个码本与T个编码向量生成，该T个编码向量根据T个第一子序列生成，该T个编码向量中至少一个编码向量的非零元素的数量大于或者等于2，该T个第一子序列与该T个编码向量一一对应，该T个编码向量中的第t 1个编码向量中非零元素的位置是根据第t 1个第一子序列确定的，t 1∈[1,T]，t 1与T均为正整数；根据该一个或多个码本对该T个第二子序列进行内码译码，获得该T个第一子序列，其中，每个第一子序列与该一个或多个码本中的一个列向量组对应，该T个第一子序列中至少一个第一子序列对应的该列向量组包括至少两个列向量。
在本技术方案中，根据一个或多个码本对T个第二子序列进行内码译码，得到T个第一子序列，T个第一子序列中至少一个第一子序列对应的该列向量组包括至少两个列向量，起到了提升码字空间的技术效果。
结合第二方面，在第二方面的某些实现方式中，通过检测第t 2个第二子序列，确定第t 2个第一子序列对应的码本E t2中的一个列向量组，其中，t 2∈[1,T]，t 2为正整数，该码本E t2为该一个或多个码本中的一个；根据该第t 2个第一子序列对应的码本E t2中的一个列向量组，确定该第t 2个第一子序列。
结合第二方面，在第二方面的某些实现方式中，检测该第t 2个第二子序列，当一个列向量组中的至少一个列向量满足预设条件，确定该一个列向量组为第t 2个第一子序列对应的码本E t2中的一个列向量组。
在本技术方案中，该列向量组中的至少一个列向量满足预设条件时，可以确定该向量组存在，可以起到提高译码可靠性的技术效果。
结合第二方面，在第二方面的某些实现方式中，检测该第t 2个第二子序列，当一个列向量组中的任意一个列向量满足预设条件，确定该一个列向量组为第t 2个第一子序列对应的码本E t2中的一个列向量组。
在本技术方案中，该列向量组中的一个列向量满足预设条件时，可以确定该列向量存在，由此，可以起到提升增加更多的用户同时传输的技术效果。
结合第二方面，在第二方面的某些实现方式中，检测该T个第二子序列，当T 1个列向量组中的至少一个列向量满足预设条件，T 2个列向量组中的任意一个列向量满足预设条件，确定该列向量组为该T个第一子序列对应的码本中的列向量组，其中，T＝T 1+T 2。
在本技术方案中，通过两种不同的方式的结合，不仅可以对重要的第一子序列起到加强保护，避免漏检造成后续块的无法检测，提升了译码可靠性的技术效果，还会增加传输速率，起到增加更多的用户同时传输的技术效果，二者的结合为整体优化系统性能提供了最大的功能上的灵活性。
结合第二方面，在第二方面的某些实现方式中，任意两个第一子序列对应的两个列向量组中的任意两个列向量互不重叠。
在本技术方案中，将一个第一子序列映射到码本对应的至少两个列向量，并且任意两个第一子序列对应的该列向量组中的任意两个列向量互不重叠，可以起到增加冗余，对第一子序列进行额外保护，增大编码增益，以及提升译码的可靠性的技术效果。
结合第二方面，在第二方面的某些实现方式中，任意两个第一子序列对应的两个列向量组中的至少两个列向量互不重叠。
在本技术方案中，将一个第一子序列映射到码本对应的至少两个列向量，并且任意两 个第一子序列对应的列向量组中的至少两个列向量互不重叠，可以扩大码字空间，增加每个第一子序列承载的信息速率，增加可容纳的用户数。
结合第二方面，在第二方面的某些实现方式中，该T个第一序列中，T 1个第一子序列对应的该列向量组中的任意两个列向量互不重叠，T 2个第一子序列对应的该列向量组中的至少两个列向量互不重叠，其中，该T 1个第一子序列中任意一个第一子序列与该T 2个第一子序列中任意一个第一子序列为不同的序列，T＝T 1+T 2。
在本技术方案中，通过两种不同的方式的结合，不仅可以对重要的第一子序列起到加强保护，提升可靠性的技术效果，还会起到增加传输速率，增加可容纳的用户数的技术效果，二者的结合为整体优化系统性能提供了功能上的灵活性。
结合第二方面，在第二方面的某些实现方式中，该T个第一子序列中的每个第一子序列对应的该码本中的一个列向量组为c个列向量组中的一个，其中，c为M/g向上取整或者向下取整的值，g为该一个列向量组中列向量的数量，M为该码本的列数，g为大于或等于1且小于或等于M的整数。
结合第二方面，在第二方面的某些实现方式中，该T个第一子序列中的每个第一子序列对应的该码本中的一个列向量组为c个列向量组中的一个，其中，c＝2 k，k为log 2p向上取整或者向下取整的值，p等于
Figure PCTCN2021133082-appb-000002
b为该一个列向量组中列向量的数量，M为该码本的列数，其中，b为大于或等于1且小于或等于M的整数。
结合第二方面，在第二方面的某些实现方式中，对该第一序列进行外码译码，生成原始信息序列。
第三方面，提供了一种通信装置，该通信装置可以包括执行第一方面中所描述的方法/操作/步骤/动作所一一对应的模块或单元，该模块或单元可以是硬件电路，也可是软件，也可以是硬件电路结合软件实现。一种可能的实现中，该装置包括：
通信单元，用于获取第一序列，该第一序列包括T个第一子序列，T为正整数；处理单元，用于根据该T个第一子序列，确定T个编码向量，该T个编码向量中至少一个编码向量的非零元素的数量大于或者等于2，该T个第一子序列与该T个编码向量一一对应，该T个编码向量中的第t 1个编码向量中非零元素的位置是根据第t 1个第一子序列确定的，t 1∈[1,T]，t 1和T均为正整数；该处理单元，还用于根据一个或多个码本和该T个编码向量，生成T个第二子序列，其中，每个第一子序列与码本中的一个列向量组对应，T个第一子序列中至少一个第一子序列对应的列向量组包括至少两个列向量；该通信单元，还用于发送该T个第二子序列。
由上述通信装置带来的有益效果，可以参考第一方面的具体描述，为了简洁，此处不再赘述。
结合第三方面，在第三方面的某些实现方式中，该处理单元具体用于，通过码本E t2与第t 2个编码向量相乘得到第t 2个第二子序列，其中，该码本E t2为n行M列的矩阵，该第t 2个编码向量根据第t 2个第一子序列确定，该第t 2个编码向量的长度等于M，其中，t 2∈[1,T]，t 2、n和M均为正整数，该码本E t2为该一个或多个码本中的一个。
结合第三方面，在第三方面的某些实现方式中，任意两个第一子序列对应的该列向量组中的任意两个列向量互不重叠。
结合第三方面，在第三方面的某些实现方式中，任意两个第一子序列对应的该列向量 组中的至少两个列向量互不重叠。
结合第三方面，在第三方面的某些实现方式中，T个第一子序列中，T 1个第一子序列对应的列向量组中的任意两个列向量互不重叠，T 2个第一子序列对应的列向量组中的至少两个列向量互不重叠，其中，T 1个第一子序列中任意一个第一子序列与T 2个第一子序列中任意一个第一子序列为不同的序列，T＝T 1+T 2。
结合第三方面，在第三方面的某些实现方式中，该T个第一子序列中的每个第一子序列对应的该码本中的一个列向量组为c个列向量组中的一个，其中，c为M/g向上取整或者向下取整的值，g为该一个列向量组中列向量的数量，M为该码本的列数，g为大于或等于1且小于或等于M的整数。
结合第三方面，在第三方面的某些实现方式中，该T个第二子序列中的每个第二子序列对应的该码本中的一个列向量组为c个列向量组中的一个，其中，c＝2 k，k为log 2p向上取整或者向下取整的值，p等于
Figure PCTCN2021133082-appb-000003
b为该一个列向量组中列向量的数量，M为该码本的列数，其中，b为大于或等于1且小于或等于M的整数。
结合第三方面，在第三方面的某些实现方式中，在该获取第一序列之前，该处理单元还用于，对原始信息序列进行外码编码，生成该第一序列。
第四方面，提供了一种通信装置，该通信装置可以包括执行第二方面中所描述的方法/操作/步骤/动作所一一对应的模块或单元，该模块或单元可以是硬件电路，也可是软件，也可以是硬件电路结合软件实现。一种可能的实现中该装置包括：
通信单元，用于获取T个第二子序列，其中，该T个第二子序列由一个或多个码本与T个编码向量生成，该T个编码向量根据T个第一子序列生成，该T个编码向量中至少一个编码向量的非零元素的数量大于或者等于2，该T个第一子序列与该T个编码向量一一对应，该T个编码向量中的第t 1个编码向量中非零元素的位置是根据第t 1个第一子序列确定的，t 1∈[1,T]，t 1与T均为正整数；
处理单元，用于根据该一个或多个码本对该T个第二子序列进行内码译码，获得该T个第一子序列，其中，每个第一子序列与该一个或多个码本中的一个列向量组对应，该T个第一子序列中至少一个第一子序列对应的该列向量组包括至少两个列向量。
由上述通信装置带来的有益效果，可以参考第二方面的具体描述，为了简洁，此处不再赘述。
结合第四方面，在第四方面的某些实现方式中，该处理单元具体用于，通过检测第t 2个第二子序列，确定第t 2个第一子序列对应的码本E t2中的一个列向量组，其中，t 2∈[1,T]，t 2为正整数，该码本E t2为该一个或多个码本中的一个；根据该第t 2个第一子序列对应的码本E t2中的一个列向量组，确定该第t 2个第一子序列。
结合第四方面，在第四方面的某些实现方式中，该处理单元还具体用于，检测该第t 2个第二子序列，当一个列向量组中的至少一个列向量满足预设条件，确定该一个列向量组为第t 2个第一子序列对应的码本E t2中的一个列向量组。
结合第四方面，在第四方面的某些实现方式中，该处理单元还具体用于，检测该第t 2个第二子序列，当一个列向量组中的任意一个列向量满足预设条件，确定该一个列向量组为第t 2个第一子序列对应的码本E t2中的一个列向量组。
结合第四方面，在第四方面的某些实现方式中，该处理单元还具体用于，检测该T个 第二子序列，当T 1个列向量组中的至少一个列向量满足预设条件，T 2个列向量组中的任意一个列向量满足预设条件，确定该列向量组为该T个第一子序列对应的码本中的列向量组，其中，T＝T 1+T 2。
结合第四方面，在第四方面的某些实现方式中，任意两个第一子序列对应的两个列向量组中的任意两个列向量互不重叠。
结合第四方面，在第四方面的某些实现方式中，任意两个第一子序列对应的两个列向量组中的至少两个列向量互不重叠。
结合第四方面，在第四方面的某些实现方式中，该T个第一序列中，T 1个第一子序列对应的该列向量组中的任意两个列向量互不重叠，T 2个第一子序列对应的该列向量组中的至少两个列向量互不重叠，其中，该T 1个第一子序列中任意一个第一子序列与该T 2个第一子序列中任意一个第一子序列为不同的序列，T＝T 1+T 2。
结合第四方面，在第四方面的某些实现方式中，该T个第一子序列中的每个第一子序列对应的该码本中的一个列向量组为c个列向量组中的一个，其中，c为M/g向上取整或者向下取整的值，g为该一个列向量组中列向量的数量，M为该码本的列数，g为大于或等于1且小于或等于M的整数。
结合第四方面，在第四方面的某些实现方式中，该T个第一子序列中的每个第一子序列对应的该码本中的一个列向量组为c个列向量组中的一个，其中，c＝2 k，k为log 2p向上取整或者向下取整的值，p等于
Figure PCTCN2021133082-appb-000004
b为该一个列向量组中列向量的数量，M为该码本的列数，其中，b为大于或等于1且小于或等于M的整数。
结合第四方面，在第四方面的某些实现方式中，该处理单元还具体用于，对该第一序列进行外码译码，获得原始信息序列。
第五方面，提供了一种通信装置，该通信装置具有实现上述第一方面及其任意可能的实现方式中的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的单元。
在一种可能的设计中，当该功能的部分或全部通过硬件实现时，该通信装置包括：输入接口电路，用于获取第一序列；逻辑电路，用于根据一个或多个码本和T个编码向量，生成T个第二子序列。
在具体实现时，该通信装置可以是芯片或者集成电路。
在一种可能的设计中，当该功能的部分或全部通过软件实现时，该通信装置包括：存储器，用于存储计算机程序；处理器，用于执行存储器中存储的计算机程序，当该计算机程序被执行时，该通信装置可以实现如上述第一方面和第一方面的任一种可能的设计中该的传输数据的方法。
可选的，存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一种可能的设计中，当该功能的部分或全部通过软件实现时，该通信装置包括仅包括处理器。用于存储程序的存储器位于通信装置之外，处理器通过电路/电线与存储器连接，用于读取并运行存储器中存储的程序，以执行上述第一方面和第一方面的任意可能的实现方式中的传输数据的方法。
第六方面，提供了一种通信装置，该通信装置具有实现上述第二方面及其任意可能的实现方式中的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实 现。该硬件或软件包括一个或多个与上述功能相对应的单元。
在一种可能的设计中，当该功能的部分或全部通过硬件实现时，该通信装置包括：输入接口电路，用于获取T个第二子序列；逻辑电路，用于执行上述第二方面中的译码方法；输出接口电路，用于输出原始信息序列。
可选的，该通信装置可以是芯片或者集成电路。
在一种可能的设计中，当该功能的部分或全部通过软件实现时，该通信装置包括：存储器，用于存储计算机程序；处理器，用于执行存储器中存储的计算机程序，当该计算机程序被执行时，该通信装置可以实现如上述第二方面该的译码方法。
可选的，存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一种可能的设计中，当该功能的部分或全部通过软件实现时，该通信装置包括仅包括处理器。用于存储程序的存储器位于通信装置之外，处理器通过电路/电线与存储器连接，用于读取并运行存储器中存储的程序，以执行上述第二方面中该的译码方法。
在具体实现时，该通信装置可以为芯片或集成电路。
第七方面，本申请提供一种网络设备，包括收发器、处理器和存储器。处理器用于控制收发器收发信号，存储器用于存储计算机程序，处理器用于调用并运行存储器中存储的计算机程序，使得第一方面任意可能的实现方式中的方法。
第八方面，本申请提供一种终端设备，包括收发器、处理器和存储器。处理器用于控制收发器收发信号，存储器用于存储计算机程序，处理器用于调用并运行存储器中存储的计算机程序，使得第二方面任意可能的实现方式中的方法被执行。
第九方面，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机上运行时，使得第一方面或第一方面的任意可能的实现方式中的方法被执行。
第十方面，本申请提供一种计算机程序产品，该计算机程序产品包括计算机程序代码，当计算机程序代码在计算机上运行时，使得上述第一方面及其任意一种可能的实现方式中的方法被执行。
第十一方面，本申请提供一种芯片，包括处理器。处理器用于读取并执行存储器中存储的计算机程序，以执行上述第一方面或第一方面任意可能的实现方式中的方法。可选地，该芯片还包括存储器，该存储器与该处理器通过电路或电线与存储器连接。进一步可选地，该芯片还包括通信接口，处理器与该通信接口连接。通信接口用于接收T个第一子序列，处理器从通信接口获取该T个第一子序列，确定T个编码向量，并根据一个或多个码本和T个编码向量，生成T个第二子序列；通信接口输出编码后的T个第二子序列。该通信接口可以是输入输出接口。
第十二方面，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机上运行时，使得第二方面或第二方面的任意可能的实现方式中的方法被执行。
第十三方面，本申请提供一种计算机程序产品，该计算机程序产品包括计算机程序代码，当计算机程序代码在计算机上运行时，使得上述第二方面或第二方面任意可能的实现方式中的方法被执行。
第十四方面，本申请提供一种芯片，包括处理器。处理器用于读取并执行存储器中存 储的计算机程序，以执行上述第二方面或第二方面任意可能的实现方式中的方法。
可选地，该芯片还包括存储器，该存储器与该处理器通过电路或电线与存储器连接。进一步可选地，该芯片还包括通信接口，处理器与该通信接口连接。通信接口用于接收T个第二子序列，处理器从通信接口获取该T个第二子序列，并采用第二方面描述的译码方法，对该T个第二子序列进行译码，得到原始信息序列；通信接口输出原始信息序列。该通信接口可以是输入输出接口。
第十五方面，本申请提供一种通信系统，包括第五方面的网络设备和第六方面的终端设备。
附图说明
图1为无线通信系统100的一种架构图。
图2为无源随机接入系统整体结构的一种示意图。
图3为基于树编码的外码编码的一种示意图。
图4为基于无源多用户稀疏回归码的内码编码的一种示意图。
图5为基于树码的外码译码的一种操作示意图
图6为本申请实施例提供的映射关系的一种示意图。
图7为本申请实施例提供的数据传输的方法700的一种示意性流程图。
图8为本申请实施例提供的数据传输的方法800的一种示意性流程图。
图9是本申请实施例提供的基于无源多用户稀疏回归码的内码编码的一种示意图。
图10是本申请实施例提供的数据传输的方法1000的一种示意性流程图。
图11为本申请提供的通信装置1100的示意性框图。
图12为本申请提供的通信装置1200的示意性结构图。
图13为本申请提供的处理装置1201的内部结构示意图。
图14为本申请提供的通信装置1400的示意性框图。
图15为本申请提供的通信装置1500的示意性结构图。
图16为本申请提供的处理装置1502的内部结构示意图。
图17为本申请提供的终端设备1700的示意性结构图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
参见图1，图1是无线通信系统100的一种架构图。如图1所示，无线通信系统100可以包括至少一个网络设备、一个或者多个终端设备。网络设备(如图1中所示的111)可以与该一个或多个终端设备(如图1中所示的122至126)进行无线通信。在一个系统中存在大量的终端设备，但是同时激活向网络设备传输数据的终端设备数量较少。
本申请中涉及的无线通信系统，包括但不限于长期演进(long term evolution，LTE)系统、LTE的频分双工(frequency division duplex，FDD)系统、LTE的时分双工(time division duplex，TDD)、第五代移动通信技术(5th generation mobile networks,5G)的三大应用场景，即增强移动带宽(enhance mobile broadband，eMBB)，高可靠性低延迟通信(ultra reliable low latency communication，URLLC)和增强海量机器连接通信(massive machine type  communication，eMTC)或者未来的的通信系统等。
本申请实施例涉及的终端设备可以指用户设备(user equipment，UE)、终端(terminal)、接入终端、用户单元、用户站、移动站、移动台、远方站、远程终端、移动设备、用户终端、终端、无线通信设备、用户代理或用户装置。终端设备还可以是蜂窝电话、无绳电话、会话启动协议(session initiation protocol，SIP)电话、无线本地环路(wireless local loop，WLL)站、个人数字处理(personal digital assistant，PDA)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、车载设备、可穿戴设备，5G网络中的终端设备、未来演进的公用陆地移动通信网络(public land mobile network，PLMN)中的终端设备、虚拟现实(Virtual Reality，VR)终端设备、增强现实(Augmented Reality，AR)终端设备、工业控制(industrial control)中的无线设备、无人驾驶(self driving)中的无线设备、远程医疗(remote medical)中的无线设备、智能电网(smart grid)中的无线设备、运输安全(transportation safety)中的无线设备、智慧城市(smart city)中的无线设备、智慧家庭(smart home)中的无线设备等，本申请对此不作限定。
本申请涉及的网络设备可以是用于与终端设备通信的设备。该网络设备可以是基站，也可以是基站与基站控制器集成后的设备，还可以是具有类似通信功能的其它设备。这里所说的基站可以是长期演进(long term evolution,LTE)系统中的演进型基站(evolutional nodeB，eNB或eNodeB)，还可以是云无线接入网络(cloud radio access network，CRAN)场景下的无线控制器。可选的，本申请实施例中的网络设备可以包括各种形式的基站，例如：宏基站、微基站(也称为小站)、中继站、接入点、5G基站或未来的基站、传输点(transmitting and receiving point，TRP)、发射点(transmitting point，TP)、移动交换中心以及设备到设备(Device-to-Device，D2D)、车辆外联(vehicle-to-everything，V2X)、机器到机器(machine-to-machine，M2M)通信中承担基站功能的设备等等，本申请实施例不作限定。
图1中的网络设备与终端设备之间采用无线技术进行通信。当网络设备发送信号时，其为发送端，当网络设备接收信号时，其为接收端。同理，当终端设备发送信号时，其为发送端，当终端设备接收信号时，其为接收端。
图2是无源随机接入系统整体结构的一种示意图。如图2所示，存在多个终端设备接入，对于某一个终端设备i，假设其在某时刻需要发送的信息(原始信息序列)为MSG i，则首先对其进行外码编码，其中，外码编码可采用树编码。
图3是基于树编码的外码编码的一种示意图。如图3所示，首先将原始信息序列分成T个原始信息子序列，其中，每个原始信息子序列所包含的比特数目可以不同。假设原始信息子序列的索引从0开始，即，第一个原始信息子序列的编号为0，后面的子序列的编号依次增加，则对第n+1个原始信息子序列包含的原始信息序列记为ω (n)，比特数目记为m n。对每个原始信息子序列增加外码比特序列，如对第n+1个原始信息子序列增加外码比特序列，该外码比特序列是根据ω (0)，ω (1)，…，ω (n-1)，ω (n)进行编码生成的，长度为l n。某种程度上，该外码比特序列可以等同于包括第n+1个原始信息子序列在内的此前所有n+1个原始信息子序列的原始信息比特序列的校验比特序列。根据研究，为获得良好性能，需要使前面的原始信息子序列包括的原始信息比特较长，外码比特序列的长度较短，后面的则相反。一般情况下，往往使每个原始信息子序列增加外码比特序列后，包含的原始信 息比特长度加上外码比特序列长度相同，以及第一个原始信息子序列中不包含外码比特序列。
树编码之后的序列再进行内码编码，即，经过稀疏回归码(Sparse Regression Code,SPARC)编码，然后将得到的信号直接进行发送。图4是基于无源多用户稀疏回归码的内码编码的一种示意图。如图4所示，获得外码编码后的T个第一序列，对于T个第一序列中的每一个第一序列，经过内码编码后，发送E*W，其中E为码本，是n*M的独立同分布矩阵，包括M个长度为码长n的列向量，W是长度为M的M*1的矩阵，其中W有1个非0元素。换言之，W表征外码编码后的比特序列，其中只有1行不为0，其他行均为0，此1所在行的位置表征外码编码后的第一序列，可以看为一种位置调制。可知，有log 2M＝s+p，s为一个第一序列中信息比特序列的长度，p为一个第一序列中校验比特序列的长度，s为正整数，p为大于或者等于0的整数。最终，经过外码和内码调制后，发射信号可以看做T个第一序列，每个第一序列占用n个传输资源，n个资源上传输的比特信号正好对应矩阵E中的某一个列向量。
终端i的信号与其他同时刻发送的终端设备的信号经过信道叠加后，接收端利用近似消息传递(Approximate message passing,AMP)译码器，恢复出稀疏回归码内码编码前的比特序列，再通过外码译码器，分离出每个用户各自的信号，其中，外码译码器可以采用树状译码。
图5是基于树码的外码译码的一种操作示意图。如图5所示，图5(a)为阶段0，节点1为该树状结构的根节点；图5(b)为阶段1，验证根节点的所有子节点的奇偶校验约束，第二行为阴影的子节点1与子节点2为满足奇偶校验约束的子节点；图5(c)为阶段2，针对第二行的子节点1和子节点2验证其所有子节点的奇偶校验约束，第三行为阴影的子节点为满足奇偶校验约束的子节点；图5(d)为阶段n-1，仅验证n-2阶段保留下来的自子节点的奇偶校验约束，阴影的子节点为满足n-1阶段奇偶校验约束的子节，其中，虚线指示的路径为被树译码器译码的有效路径。
对于一个用户信息的完整接收，是通过外码和树状译码搜索来实现的，树搜索的顺序决定了靠近根的节点具有更高的重要性。而且，为了获得良好性能，靠前的外码序列较短，例如第一个序列往往不含有校验比特。因此，如果靠前的某个序列漏检或者误检，可能造成整个序列的无法恢复。此外，对于激活率过低的场景，介于采用位置调制，序列的数量较少。而且该方案中，支持的最大同时激活数目也存在限制，对于激活率很高的场景也不适用。
为了解决上述缺点，本申请实施例提出了一种数据传输的方法。图6为本申请实施例涉及的映射关系的一种示意图。如图6所示，元素集合{x,y,z}中，x、y、z分别映射至具体的位置中，不同元素可以映射至同一位置。其主要思想是通过同一个位置可以被多个元素映射，每个元素映射到多个位置。检查某个元素是否存在时，对该元素需要映射到的所有位置进行检查，当该元素映射的所有位置均有记录时，则判断该元素为可能存在，否则判断为不存在。然而，因为存在多个元素映射到同一位置的情况，可能会使得某个元素其实不存在，但其映射的各个位置均有记录。在本申请的技术方案中，通过利用外码的结构特点，可以较为有效的解决上述问题。
下面将结合附图详细说明本申请提供的实施例。
应理解，在本申请实施例中，为了不失一般性，第一序列表示原始信息序列经过外码编码后的序列，第二序列表示第一序列经过内码编码后的序列。
图7是本申请实施例提供的数据传输的方法700的一种示意性流程图。方法700可以由发送端执行。
S710，对原始信息序列进行外码编码。
示例地，外码编码器获取原始信息序列之后，对原始信息序列进行树编码，得到第一序列。其中，第一序列包括T个第一子序列，T为正整数。
S720，对第一序列进行内码编码，得到第二序列，并发送该第二序列。
具体地，对T个第一子序列进行编码得到T个第二子序列，并发送该T个第二子序列，其中，T个第二子序列组成第二序列。
示例地，内码编码器在获取外码编码器输出的第一序列后，采用本申请实施例提出的方法对该第一序列进行基于无源多用户稀疏回归码的内码编码，得到第二序列。
S730，获取第二序列，并对第二序列进行内码译码。
示例地，获取第二序列之后，对第二序列进行内码译码，获得第一序列。可选地，可以通过使用近似消息传递(Approximate Message Passing,AMP)译码器对第二序列进行译码，获得第一序列。
S740，对第一序列进行外码译码。
示例地，外码译码器获得第一序列，对该第一序列进行外码译码，获得原始信息序列。可选地，使用基于树码的外码译码器进行外码译码。
外码译码器可以恢复任一终端设备的原始信息序列。根据上述描述可知，AMP译码器对于多个第二子序列，可能会译码出源于多个用户的多个序列。对于多个第二子序列，如何确定每一个第二子序列是来源于同一个终端设备是至关重要的，这个功能将由外码译码器实现。当外码编码时，每一个第一序列增加的外码序列与此前所有第一子序列的信息均相关，可以看作校验序列，因此，可以通过这种方式，确定每一个第一子序列和之前的某一第一子序列属于同一原始信息序列，从而得出独立的多个终端设备的原始信息序列。
下面对步骤720做详细的描述。图8是本申请实施例提供的数据传输的方法800的一种示意性流程图。如图8所示，具体流程如下所述：
S801、获取第一序列。
示例地，内码编码器获取经外码编码器编码后的第一序列，该第一序列包括T个第一子序列，T为正整数。
S802、根据T个第一子序列，确定T个编码向量。
示例地，内码编码器根据上述T个第一子序列，确定T个编码向量。其中，T个编码向量中至少一个编码向量的非零元素的数量大于或者等于2，T个第一子序列与T个编码向量一一对应，T个编码向量中的第t 1个编码向量中非零元素的位置是根据第t 1个待编码子序列确定的，t 1∈[1,T]，t 1和T均为正整数。
S803、根据一个或多个码本和T个编码向量，生成T个第二子序列。
示例地，内码编码器会根据一个或多个码本与T个编码向量，生成T个第二子序列。
S804、发送T个第二子序列。
示例地，内码编码器在生成T个第二子序列之后，会向内码译码器发送T个第二子序 列。
举例来说，图9是本申请实施例提供的基于无源多用户稀疏回归码的内码编码的一种示意图。如图9所示，对于外码编码后的每一个第一子序列，经过内码编码后，发送码本E*编码向量W，其中码本E为n行M列的独立同分布矩阵，编码向量W的长度等于M，其中有a n个
Figure PCTCN2021133082-appb-000005
即，有a n个非0元素，a n大于或等于2。换言之，W表征外码编码后的第一序列，其中只有a n行不为0，其他行均为0，此a n所在行的位置表征外码编码后该第一序列，可以看为一种位置调制。最终，经过外码和内码调制后，发射信号可以看做T个第二子序列。每个第二子序列占用n个传输资源，n个资源上传输的比特信号正好对应矩阵E中的某一个列向量组，其中，一个列向量组包括至少两个列向量，n、M、T均为正整数。
可选地，一个码本可以对应一个编码向量，也可以对应多个编码向量，本申请在此不做限制。
首先，根据T个第一子序列，确定T个编码向量，其中，T个第一子序列与T个编码向量一一对应，T个编码向量中至少一个编码向量的非零元素的数量大于或者等于2，第t 1个编码向量中非零元素的位置是根据第t 1个第一子序列确定的，每个编码向量的长度等于M，其中，第t 1个编码向量与第t 1个第一子序列对应，t 1∈[1,T]，t 1与T均为正整数。对于不同的第一子序列，在具体实现的过程中，非零元素的数量可以相同，也可以不同，本申请在此不做限制。
其次，根据一个或多个码本和T个编码向量，生成T个第二子序列。
一种可能的实现中，通过码本E t2与第t 2个编码向量相乘得到第t 2个第二子序列，第t 2个编码向量根据第t 2个第一子序列确定，其中，码本E t2为n行M列的矩阵，t 2∈[1,T]，码本E t2为一个或多个码本中的一个。
内码编码器在获得T个第一子序列后，会对该T个第一子序列进行编码，即，根据一个或多个码本和T个编码向量，生成T个第二子序列。
T个第一子序列与码本存在映射关系，介绍如下：
在可能实现的一种方式中，该映射关系为任意两个第一子序列对应的码本中的列向量组中任意两个列向量互不重叠。具体的关于映射关系的描述，可以参考下述S1002中的描述。
在可能实现的另一种方式中，该映射关系为与任意两个第一子序列满足映射关系的两个列向量组中至少两个列向量互不重叠。具体的关于映射关系的描述，可以参考下述S1002中的描述。
在可能实现的另一种方式中，该映射关系为前k个第一子序列中的每个第一子序列对应的码本中的列向量组中任意两个列向量互不重叠，进一步地，每个第一子序列映射到c个列向量组中的列向量组，仅与该第一子序列存在映射关系，与其他第一子序列无映射关系；第k+1至第T个第一子序列中的每个第一子序列对应的一个列向量组中的至少两个列向量互不重叠。具体的关于映射关系的描述，可以参考下述S1002中的描述。
下面对步骤730做详细的描述。图10是本申请实施例提供的数据传输的方法1000的一种示意性流程图。如图10所示，具体的步骤如下描述：
S1001，获取T个第二子序列。
示例地，内码译码器首先获取T个第二子序列，其中，T个第二子序列由一个或多个码本与T个编码向量生成，T个编码向量根据T个第一子序列生成，T个编码向量中至少一个编码向量的非零元素的数量大于或者等于2，T个第一子序列与T个编码向量一一对应，第t 1个编码向量中非零元素的位置是根据第t 1个第一子序列确定的，T个编码向量中的每个编码向量的长度等于M，t 1∈[1,T]，M、t 1与T均为正整数；
S1002，根据一个或多个码本对T个第二子序列进行内码译码，获得T个第一子序列。
示例地，内码译码器在获得T个第二子序列后，会对该T个第二子序列进行译码。
具体地，根据一个或多个码本对T个第二子序列进行内码译码，获得第一序列，即，T个第一子序列。其中，每个第一子序列与码本中的一个列向量组对应，T个第一子序列中至少一个第一子序列对应的列向量组包括至少两个列向量。
举例来说，通过检测第t 2个第二子序列，确定第t 2个第一子序列对应的码本E t2中的一个列向量组，再根据第t 2个第一子序列对应的码本E t2中的一个列向量组，确定第t 2个第一子序列，其中，t 2∈[1,T]，t 2为正整数，码本E t2为所述一个或多个码本中的一个。
在可能实现的一种方式中，通过近似消息传递(AMP)算法或者广义近似消息传递(GAMP)算法等类似相关算法，衡量迭代得到关于衡量某些列向量是否存在的可信度的数值。当这些数值衡量的结果超过预设阈值时，可以认为该列向量达到预设条件；或者对这些数值衡量的结果进行排序，确定存在可信度最高的列向量为达到预设条件的列向量。
具体地，检测第t 2个第二子序列，通过AMP算法或GAMP算法等类似算法，判断码本E t2中哪个列向量组的中的哪个列向量满足预设条件，确定满足预设条件的列向量所属的列向量组为第t 2个第一子序列对应的码本E t2中的一个列向量组。其中，该预设条件可以为该列向量组中的列向量的可信度数值大于预设阈值，也可以认为可信度最高的列向量为满足预设条件的列向量，本申请在此不做限定。
在可能实现的另一种方式中，可以将第二序列看作是码本中某些列向量的近似加权叠加，故而可以将接收到的第二序列，与码本中的所有列向量一一做相关性检测，得出每一个列向量对应的相关值，或者归一化后的相关值，作为某个列向量是否存在的可信度的数值衡量。当该列向量的可信度的数值衡量结果大于预设阈值时，即可认为该列向量组中的列向量为满足预设条件的列向量。
接着，通过一个或多个码本中的满足预设条件的列向量组与T个第一子序列的映射关系，确定T个第一子序列。
T个第一子序列与码本存在三种映射关系，具体介绍如下：
在可能实现的一种方式中，该映射关系为任意两个第一子序列对应的码本中的列向量组中任意两个列向量互不重叠。进一步地，每个第一子序列与码本中的c个列向量组中的一个列向量组满足映射关系，c个列向量组中的任一列向量组包括至少两个列向量，c为正整数。应理解，码本中的c个列向量是指该c个列向量组由码本中的列向量组成。
需要指出的是，码本中的一个列向量组的至少两个列向量到第一子序列的映射方式，编码端与译码端可以根据标准预先定义保持一致，或者通过信令传输的方式保持一致，也可以通过其他方法使得达成一致，本申请在此不做限制。
一个第一子序列与c个列向量组中的一个列向量组满足映射关系，其中，任意两个第一子序列对应的两个列向量组中的任意两个列向量互不重叠。举例来说，假设与第t 1个第 一子序列满足映射关系的列向量组为第t 1个列向量组，与第t 2个第一子序列满足映射关系的列向量组为第t 2个列向量组，第t 1个第一子序列与第t 2个第一子序列的取值不同，则第t 1个列向量组的列向量和第t 2个列向量组中列向量均互不重叠，且互不重叠的列向量属于不同组列向量组。
一种可能的实现中，码本中的c个列向量组中的一个列向量组映射一个第一子序列，c＝f(M/g)，f(M/g)为对M/g的值进行向上取整或者向下取整，g为一个列向量组中列向量的数量，其中，g∈[1,M]，g为正整数。进一步地，每个第一子序列映射到该c个列向量组中的一个列向量组，仅与该一个第一子序列存在映射关系，与其他第一子序列无映射关系。
举例来说，取M为9，c个列向量组中的一个列向量组中列向量的数量g为2，进行M/g的向下取整的操作，得到的c等于4。一个第一子序列为两个比特，在两个比特的第一子序列中，不同的第一子序列取值代表不同的映射列向量组的方式。此时，一个第一子序列与码本中满足映射关系的列向量组的数量为4个，其中，每个列向量组中的列向量有2个。举例来说，一个第一子序列与码本中满足映射条件的列向量的关系可以如表1所示：
表1
Figure PCTCN2021133082-appb-000006
同时，检测与一个第一子序列满足映射关系的c个列向量组中的一个列向量组中至少一个列向量满足预设条件，即可认定该第一子序列存在。例如，在表1中，当检测出列向量序号为1或2的列向量满足预设条件，即可确定第一子序列的取值为00。由此，可以提高译码的准确性，避免造成漏检。
在可能实现的另一种方式中，该映射关系为与任意两个第一子序列满足映射关系的两个列向量组中至少两个列向量互不重叠。进一步地，每个第一子序列与码本中的c个列向量组中的一个列向量组满足映射关系，c个列向量组中的任一列向量组包括至少两个列向量，c为正整数。应理解，码本中的c个列向量是指该c个列向量组由码本中的列向量组成。
需要指出的是，码本中的一个列向量组的至少两个列向量到第一子序列的映射方式，编码端与译码端可以根据标准预先定义保持一致，或者通过信令传输的方式保持一致，也可以通过其他方法使得达成一致，本申请在此不做限制。
一个第一子序列与c个列向量组中的一个列向量组满足映射关系，映射关系包括任意两个第一子序列满足映射关系的码本中的两个列向量组中至少两个列向量互不重叠。
一种可能的实现中，c＝2 k，k为log 2p向上取整或者向下取整的值，并且，log 2p≥s，
Figure PCTCN2021133082-appb-000007
s为一个第一序列的长度，b为编码向量中非零元素的数量，b∈[1,M]，b和s均 为正整数。
可选地，一个第一序列包括信息比特序列与校验比特序列，其中，信息比特序列的长度为h，校验比特序列的长度为f，s＝f+h，h为正整数，f为大于或者等于0的整数。
举例来说，取M为5，编码向量中非零元素的数量b为2，
Figure PCTCN2021133082-appb-000008
k对log 2p进行向下取整，得：k＝log 210＝3，所以，一个第一子序列与码本中满足映射关系的列向量组的数量为2 3＝8个。在一个2比特的第一子序列中，不同的第一子序列取值代表不同的映射列向量组的方式。此时，一个第一子序列与码本中满足映射关系的列向量组的数量为4个，其中，每个列向量组中的列向量有2个。具体地，一个第一子序列与码本中满足映射条件的列向量的关系可以如表2所示：
表2
Figure PCTCN2021133082-appb-000009
同时，检测与一个第一子序列满足映射关系的c个列向量组中的一个列向量组中所有列向量满足预设条件，即可认定该第一子序列存在的机制。例如，在表2中，需要同时检测出列向量序号为1和3的列向量满足预设条件，才能确定第一子序列的取值为001。由此，可以增加每个第一子序列承载的比特信息速率，提升码字空间，增加更多的用户同时传输。
在可能实现的另一种方式中，该映射关系为前k个第一子序列中的每个第一子序列对应的码本中的列向量组中任意两个列向量互不重叠，进一步地，每个第一子序列映射到c个列向量组中的列向量组，仅与该第一子序列存在映射关系，与其他第一子序列无映射关系；第k+1至第T个第一子序列中的每个第一子序列对应的一个列向量组中的至少两个列 向量互不重叠。
例如，T个第一子序列中，每个第一子序列与码本中的，属于c个列向量组的一个列向量组满足映射关系，其中，M＝M 1+M 2，前k个第一子序列中任意两个第一子序列满足映射关系的码本中的，属于c 1个列向量组中的列向量组中任意两个列向量互不重叠，码本中的一个列向量组映射前k个第一子序列中的一个第一子序列，c 1＝f(M 1/g)，f(M 1/g)为对M 1/g进行向上取整或者向下取整，g为满足映射关系的码本中的一个列向量组中列向量的数量，其中，g∈(0,M 1]，g为整数；第k+1至第T个第一子序列满足映射关系的c 2个列向量组中的列向量组中至少两个列向量互不重叠，c 2＝2 k，k为log 2p向上取整或者向下取整的值，并且，log 2p≥s，
Figure PCTCN2021133082-appb-000010
s＝f+h，s为一个第一序列的长度，b为编码向量中非零元素的数量，b∈[0,M 2]，k、b和s均为正整数，c 1、c 2为大于或者等于0的整数，且c＝c 1+c 2。
其中，一个第一子序列包括信息比特序列与校验比特序列，其中，信息比特序列的长度为h，校验比特序列的长度为f，h为正整数，f为大于或者等于0的整数。
具体地，取T为2，M 1为4，M 2为5，g为2，b为2，对M/g进行向下取整，对log 2p进行向下取整，得：M＝9，c 1＝2，c 2＝8，k为3。具体地，T个第一子序列与码本中满足映射条件的列向量的关系可以如表3所示：
表3
Figure PCTCN2021133082-appb-000011
需要指出的是，第一子序列到码本中的一个列向量组的至少两个列向量的映射方式，编码端与译码端可以根据标准预先定义保持一致，或者通过信令传输的方式保持一致，也可以通过其他方法使得达成一致，本申请在此不做限制。
同时，检测出前k个第一子序列满足映射关系的码本中的，属于c 1个列向量组中的一个列向量组中的至少一个列向量满足预设条件，以及第k+1至第T个第一子序列满足映射关系的码本中的，属于c 2个列向量组中的一个列向量组中所有列向量满足预设条件，认定该T个第一子序列存在。即，前k个第一子序列中的任一第一子序列在其映射的码本中所有列向量中的至少一个列向量存在时，认定该第一子序列存在，由此，可以提高译码的准确性，避免造成漏检；第k+1至第T个第一子序列中的任一第一子序列在其映射的码本中所有列向量存在时，认定该第一子序列存在的机制。例如，在表3中，对于第一个第一子序列，只需检测出列向量序号为3或4的列向量时，即可确定该第一子序列的取值为1；对于第二个第一子序列，需要同时检测出列向量序号为6、7的列向量，才能确定该第一子序列的取值为011。由此，可以增加每个第一子序列承载的比特信息速率，增加码字空间，支持更多的用户同时传输，增强了系统的灵活性。
以上结合图1至图10，对本申请提供的数据传输的方法作了详细说明。对于接收端(或者称为译码端)从发送端(或者称为编码端)接收到第二序列。应理解，本申请提供一种数据传输的方法，使得接收端能够以T个第二子序列为单位进行译码，而不是以比特为单位进行译码，并且，大量仿真结果表明译码性能得到了提升。例如，译码时延降低，误码率降低。
下面结合图11至图17，说明本申请提供的通信装置、编码装置、网络设备和终端设备。
参见图11，图11是本申请提供的通信装置1100的示意性框图。如图11所示，装置1100包括处理单元1110和通信单元1120。
处理单元1110，用于根据T个第一子序列，确定T个编码向量；根据一个或多个码本和T个编码向量，生成T个第二子序列。
通信单元1120，用于获取T个第一子序列，并发送处理单元1110生成的T个第二子序列。
上述通信装置1100可以用于执行本申请各实施例中的数据传输方法。详细流程参见上文方法实施例中的描述，此处不再赘述。参见图12，图12为本申请提供的通信装置1200的示意性结构图。通信装置1200用于实现编码的功能，该通信装置1200包括：
处理装置1201，用于根据T个第一子序列，确定T个编码向量；根据一个或多个码本和T个编码向量，生成T个第二子序列。
收发器1202，用于获取第一序列，并发送该T个第二子序列。
可选地，收发器与天线1203相连接。
在具体实现时，处理装置1201可以处理器、芯片或者集成电路。
本申请还提供了一种处理装置1201，用于实现上述方法实施例的数据传输方法。本申请实施例的数据传输方法800的部分或全部流程可以通过硬件来实现，或者也可以通过软件来实现。当通过硬件实现时，上述处理装置1201可以为处理器。
可选地，当本申请的数据传输方法800的全部或部分流程通过硬件实现时，上述处理装置1201还可以如图13所示。参见图13，图13为处理装置1201的内部结构示意图。该处理装置1201包括：
输入接口电路1211，用于获取T个第一子序列；
逻辑电路1212，用于根据T个第一子序列，确定T个编码向量；根据一个或多个码本和T个编码向量，生成T个第二子序列。
输出接口电路1213，用于输出T个第二子序列。
上述逻辑电路1212可以用于执行本申请各实施例中所述的数据传输方法。详细流程参见上文方法实施例中的描述，此处不再赘述。
可选地，本申请提供的数据传输的方法800的部分或全部流程也可以通过软件来实现。此种情况下，处理装置1201可以为处理器，处理器用于执行存储器中存储的计算机程序，当所述计算机程序被执行时，处理器执行上述方法实施例中的数据传输方法。
这里，存储器可以是物理上独立的单元。或者，存储器也可以与处理器集成在一起，本申请不作限定。
在另一种可选的实施例中，处理装置1201可以只包括处理器。处理器通过电路/电线与存储器连接，用于读取并执行存储器中存储的计算机程序。可选地，处理装置1201还包括存储器。
可选地，处理装置1201为芯片时，所述芯片还可以包括输入接口和输出接口。输入接口用于接收输入的第一序列。输出接口用于输出T个第二子序列。
基于本申请提供的数据传输方法1000，本申请还提供一种通信装置1400。通信装置1400用于执行上述方法1000。
参见图14，图14是本申请提供的通信装置1400的示意性框图。通信装置1400包括通信单元1401和处理单元1402。
通信单元1401，用于从发送端接收T个第二子序列，T为正整数。
处理单元1402，用于根据一个或多个码本对T个第二子序列进行内码译码，获得T个第一子序列。
上述通信装置1400可以用于执行本申请各实施例中的数据传输方法。详细流程参见上文方法实施例中的描述，此处不再赘述。
参见图15，图15为本申请提供的通信装置1500的示意性结构图。通信装置1500用于实现译码的功能，该译码装置1500包括：
收发器1501，用于从发送端接收T个第二子序列；
处理装置1502，用于根据一个或多个码本对T个第二子序列进行内码译码，获得T第一子序列。
可选地，收发器1501与天线1503相连接。
在具体实现时，处理装置1502可以处理器、芯片或者集成电路。
本申请还提供了一种处理装置1502，用于实现上述译码方法。本申请实施例的译码方法的部分或全部流程可以通过硬件来实现，或者也可以通过软件来实现。
可选地，当通过硬件实现时，上述处理装置1502可以为处理器。
可选地，当本申请实施例的译码的方法的全部或部分流程通过硬件实现时，上述处理装置1502还可以如图16所示。
参见图16，图16为处理装置1502的内部结构示意图。该处理装置1502包括：输入接口电路1521，逻辑电路1522和输入接口电路1523。
输入接口电路1521，用于获取T个第二子序列；
逻辑电路1522，用于根据一个或多个码本对T个第二子序列进行内码译码，获得T个第一子序列；
在可能实现的一种方式中，逻辑电路1522还用于对T个第一子序列进行外码译码，获得原始信息序列；
输出接口电路1523，用于输出原始信息序列。
可选地，处理装置1502可以为处理器，处理器用于执行存储器中存储的计算机程序，当所述计算机程序被执行时，处理器执行上述译码方法。
这里，存储器可以是物理上独立的单元。或者，存储器也可以与处理器集成在一起，本申请不作限定。
在另一种可选的实施例中，处理装置1502只包括处理器。处理器通过电路/电线与存储器连接，用于读取并执行存储器中存储的计算机程序。可选地，处理装置1502还包括存储器。
可选地，处理装置1502为芯片时，所述芯片还可以包括输入接口和输出接口。输入接口用于接收输入的待译码的比特序列。输出接口用于输出译码结果。
应理解，本申请提供的数据传输的方法可以由发送端执行。例如图1所示的无线通信系统，当网络设备111发送信号时，网络设备111为发送端。当终端设备121至126中任一个终端设备发送信号时，终端设备为发送端。由此，下面本申请再提供一种网络设备和终端设备，该网络设备和终端设备具有实现上述数据传输的方法的功能。
参见图17，图17是本申请提供的终端设备1700的示意性结构图。如图17所示，如图17所示，终端设备1700包括：一个或多个处理器1710，一个或多个存储器1720，一个或多个收发器1730。处理器1710用于控制收发器1730收发信号，存储器1720用于存储计算机程序，处理器1710用于从存储器1720中调用并运行该计算机程序，以执行本申请提供的数据传输的方法700的相应流程。为了简洁，此处不再赘述。
此外，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机指令，当该计算机指令在计算机上运行时，使得计算机执行本申请实施例的数据传输的方法700的相应操作和/或流程。
本申请还提供一种计算机程序产品，该计算机程序产品包括计算机程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行本申请实施例的数据传输的方法的相应操作和/或流程。
本申请还提供一种芯片，包括处理器。处理器用于读取并执行存储器中存储的计算机程序，以执行本申请提供的数据传输的方法的相应操作和/或流程。
可选地，该芯片还包括存储器，该存储器与该处理器通过电路或电线与存储器连接。进一步可选地，该芯片还包括通信接口，处理器与该通信接口连接。通信接口用于接收待编码的比特序列，处理器从通信接口获取该信息比特序列，并采用本申请实施例的数据传输方法，对该信息比特序列进行数据处理；通信接口输出编码后的比特序列。该通信接口可以是输入输出接口。
本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机指令，当该计算机指令在计算机上运行时，使得计算机执行本申请实施例的数据传输方法的相应操作和/或流程。
本申请还提供一种计算机程序产品，该计算机程序产品包括计算机程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行本申请实施例的数据传输方法的相应操作和/或流程。
本申请还提供一种芯片，包括处理器。处理器用于读取并执行存储器中存储的计算机程序，以执行申请提供的数据传输方法的相应操作和/或流程。
可选地，该芯片还包括存储器，该存储器与该处理器通过电路或电线与存储器连接。进一步可选地，该芯片还包括通信接口，处理器与该通信接口连接。通信接口用于接收T个第二子序列，处理器从通信接口获取该T个第二子序列，并采用本申请实施例中的传输数据的方法1000，根据一个或多个码本对T个第二子序列进行内码译码，获得T个第一子序列。该通信接口可以是输入输出接口。在实现过程中，上述方法的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。上述方法实施例的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
本申请实施例中所述的芯片，可以是现场可编程门阵列(field-programmable gate array，FPGA)、专用集成芯片(application specific integrated circuit，ASIC)、系统芯片(system on chip，SoC)、中央处理器(central processor unit，CPU)、网络处理器(Network Processor，NP)、数字信号处理电路(digital signal processor，DSP)，还可以是微控制器(micro controller unit，MCU、可编程控制器(programmable logic device，PLD)或其它集成芯片。
本申请实施例中的处理器可以是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法实施例的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。处理器可以是通用处理器、DSP、ASIC、FPGA或其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。本申请实施例公开的方法的步骤可以直接体现为硬件编码处理器执行完成，或者用编码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和 直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。应注意，本文描述的系统和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现，具体取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。例如，多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (45)

  1. 一种传输数据的方法，其特征在于，包括：
    获取第一序列，所述第一序列包括T个第一子序列，T为正整数；
    根据所述T个第一子序列，确定T个编码向量，所述T个编码向量中至少一个编码向量的非零元素的数量大于或者等于2，所述T个第一子序列与所述T个编码向量一一对应，所述T个编码向量中的第t 1个编码向量中非零元素的位置是根据第t 1个第一子序列确定的，t 1∈[1,T]，t 1和T均为正整数；
    根据一个或多个码本和所述T个编码向量，生成T个第二子序列，其中，每个第一子序列与所述一个或多个码本中的一个列向量组对应，所述T个第一子序列中至少一个第一子序列对应的所述列向量组包括至少两个列向量；
    发送所述T个第二子序列。
  2. 根据权利要求1所述的方法，其特征在于，所述根据一个或多个码本和所述T个编码向量，生成T个第二子序列，包括：
    通过码本E t2与第t 2个编码向量相乘得到第t 2个第二子序列，其中，所述码本E t2为n行M列的矩阵，所述第t 2个编码向量根据第t 2个第一子序列确定，所述第t 2个编码向量的长度等于M，其中，t 2∈[1,T]，t 2、n和M均为正整数，所述码本E t2为所述一个或多个码本中的一个。
  3. 根据权利要求1或2所述的方法，其特征在于，任意两个第一子序列对应的两个列向量组中的任意两个列向量互不重叠。
  4. 根据权利要求1或2所述的方法，其特征在于，任意两个第一子序列对应的两个列向量组中的至少两个列向量互不重叠。
  5. 根据权利要求1或2所述的方法，其特征在于，所述T个第一子序列中，T 1个第一子序列对应的所述列向量组中的任意两个列向量互不重叠，T 2个第一子序列对应的所述列向量组中的至少两个列向量互不重叠，其中，所述T 1个待发送序列中任意一个待发送序列与所述T 2个待发送序列中任意一个待发送序列为不同的序列，T＝T 1+T 2。
  6. 根据权利要求1至5中任一项所述的方法，其特征在于，所述T个第一子序列中的每个第一子序列对应的所述码本中的一个列向量组为c个列向量组中的一个，其中，c为M/g向上取整或者向下取整的值，g为所述一个列向量组中列向量的数量，M为所述码本的列数，g为大于或等于1且小于或等于M的整数。
  7. 根据权利要求1至5中任一项所述的方法，其特征在于，所述T个第一子序列中的每个第一子序列对应的所述码本中的一个列向量组为c个列向量组中的一个，其中，c＝2 k，k为log 2p向上取整或者向下取整的值，p等于
    Figure PCTCN2021133082-appb-100001
    b为所述一个列向量组中列向量的数量，M为所述码本的列数，其中，b为大于或等于1且小于或等于M的整数。
  8. 根据权利要求1至7中任一项所述的方法，其特征在于，在所述获取第一序列之前，所述方法还包括：
    对原始信息序列进行外码编码，生成所述第一序列。
  9. 一种传输数据的方法，其特征在于，包括：
    获取T个第二子序列，其中，所述T个第二子序列由一个或多个码本与T个编码向量生成，所述T个编码向量根据T个第一子序列生成，所述T个编码向量中至少一个编码向量的非零元素的数量大于或者等于2，所述T个第一子序列与所述T个编码向量一一对应，所述T个编码向量中的第t 1个编码向量中非零元素的位置是根据第t 1个第一子序列确定的，t 1∈[1,T]，t 1与T均为正整数；
    根据所述一个或多个码本对所述T个第二子序列进行内码译码，获得所述T个第一子序列，其中，每个第一子序列与所述一个或多个码本中的一个列向量组对应，所述T个第一子序列中至少一个第一子序列对应的所述列向量组包括至少两个列向量。
  10. 根据权利要求9所述的方法，其特征在于，所述根据所述一个或多个码本对所述T个第二子序列进行内码译码，包括：
    通过检测第t 2个第二子序列，确定第t 2个第一子序列对应的码本E t2中的一个列向量组，其中，t 2∈[1,T]，t 2为正整数，所述码本E t2为所述一个或多个码本中的一个；
    根据所述第t 2个第一子序列对应的码本E t2中的一个列向量组，确定所述第t 2个第一子序列。
  11. 根据权利要求10所述的方法，其特征在于，所述通过检测第t 2个第二子序列，确定第t 2个第一子序列对应的码本E t2中的一个列向量组，包括：
    检测所述第t 2个第二子序列，当一个列向量组中的至少一个列向量满足预设条件，确定所述一个列向量组为第t 2个第一子序列对应的码本E t2中的一个列向量组。
  12. 根据权利要求10所述的方法，其特征在于，所述通过检测第t 2个第二子序列，确定第t 2个第一子序列对应的码本E t2中的一个列向量组，包括：
    检测所述第t 2个第二子序列，当一个列向量组中的任意一个列向量满足预设条件，确定所述一个列向量组为第t 2个第一子序列对应的码本E t2中的一个列向量组。
  13. 根据权利要求10所述的方法，其特征在于，所述方法包括：
    检测所述T个第二子序列，当T 1个列向量组中的至少一个列向量满足预设条件，T 2个列向量组中的任意一个列向量满足预设条件，确定所述列向量组为所述T个第一子序列对应的码本中的列向量组，其中，T＝T 1+T 2。
  14. 根据权利要求9至13中任一项所述的方法，其特征在于，任意两个第一子序列对应的两个列向量组中的任意两个列向量互不重叠。
  15. 根据权利要求9至13中任一项所述的方法，其特征在于，任意两个第一子序列对应的两个列向量组中的至少两个列向量互不重叠。
  16. 根据权利要求9至13中任一项所述的方法，其特征在于，所述T个第一序列中，T 1个第一子序列对应的所述列向量组中的任意两个列向量互不重叠，T 2个第一子序列对应的所述列向量组中的至少两个列向量互不重叠，其中，所述T 1个第一子序列中任意一个第一子序列与所述T 2个第一子序列中任意一个第一子序列为不同的序列，T＝T 1+T 2。
  17. 根据权利要求9至16中任一项所述的方法，其特征在于，所述T个第一子序列中的每个第一子序列对应的所述码本中的一个列向量组为c个列向量组中的一个，其中，c为M/g向上取整或者向下取整的值，g为所述一个列向量组中列向量的数量，M为所述码本的列数，g为大于或等于1且小于或等于M的整数。
  18. 根据权利要求9至16中任一项所述的方法，其特征在于，所述T个第一子序列 中的每个第一子序列对应的所述码本中的一个列向量组为c个列向量组中的一个，其中，c＝2 k，k为log 2p向上取整或者向下取整的值，p等于
    Figure PCTCN2021133082-appb-100002
    b为所述一个列向量组中列向量的数量，M为所述码本的列数，其中，b为大于或等于1且小于或等于M的整数。
  19. 根据权利要求9至18中任意项所述的方法，其特征在于，所述方法还包括：
    对所述T个第一子序列进行外码译码，生成原始信息序列。
  20. 一种通信装置，其特征在于，包括：
    通信单元，用于获取第一序列，所述第一序列包括T个第一子序列，T为正整数；
    处理单元，用于根据所述T个第一子序列，确定T个编码向量，所述T个编码向量中至少一个编码向量的非零元素的数量大于或者等于2，所述T个第一子序列与所述T个编码向量一一对应，所述T个编码向量中的第t 1个编码向量中非零元素的位置是根据第t 1个第一子序列确定的，t 1∈[1,T]，t 1和T均为正整数；
    所述处理单元，还用于根据一个或多个码本和所述T个编码向量，生成T个第二子序列，其中，每个第一子序列与所述码本中的一个列向量组对应，所述T个第一子序列中至少一个第一子序列对应的所述列向量组包括至少两个列向量；
    所述通信单元，还用于发送所述T个第二子序列。
  21. 根据权利要求20所述的装置，其特征在于，所述处理单元具体用于：
    通过码本E t2与第t 2个编码向量相乘得到第t 2个第二子序列，其中，所述码本E t2为n行M列的矩阵，所述第t 2个编码向量根据第t 2个第一子序列确定，所述第t2个编码向量的长度等于M，其中，t 2∈[1,T]，t 2、n和M均为正整数，所述码本E t2为所述一个或多个码本中的一个。
  22. 根据权利要求20或21所述的装置，其特征在于，任意两个第一子序列对应的两个列向量组中的任意两个列向量互不重叠。
  23. 根据权利要求20或21所述的装置，其特征在于，任意两个第一子序列对应的两个列向量组中的至少两个列向量互不重叠。
  24. 根据权利要求20或21所述的装置，其特征在于，所述T个第一子序列中，T 1个第一子序列对应的所述列向量组中的任意两个列向量互不重叠，T 2个第一子序列对应的所述列向量组中的至少两个列向量互不重叠，其中，所述T 1个第一子序列中任意一个第一子序列与所述T 2个第一子序列中任意一个第一子序列为不同的序列，T＝T 1+T 2。
  25. 根据权利要求20至24中任一项所述的装置，其特征在于，所述T个第一子序列中的每个第一子序列对应的所述码本中的一个列向量组为c个列向量组中的一个，其中，c为M/g向上取整或者向下取整的值，g为所述一个列向量组中列向量的数量，M为所述码本的列数，g为大于或等于1且小于或等于M的整数。
  26. 根据权利要求20至24中任一项所述的装置，其特征在于，所述T个第一子序列中的每个第一子序列对应的所述码本中的一个列向量组为c个列向量组中的一个，其中，c＝2 k，k为log 2p向上取整或者向下取整的值，p等于
    Figure PCTCN2021133082-appb-100003
    b为所述一个列向量组中列向量的数量，M为所述码本的列数，其中，b为大于或等于1且小于或等于M的整数。
  27. 根据权利要求20至26中任一项所述的装置，其特征在于，在所述获取第一序列之前，所述处理器还用于：
    对原始信息序列进行外码编码，生成所述第一序列。
  28. 一种通信装置，其特征在于，包括：
    通信单元，用于获取T个第二子序列，其中，所述T个第二子序列由一个或多个码本与T个编码向量生成，所述T个编码向量根据T个第一子序列生成，所述T个编码向量中至少一个编码向量的非零元素的数量大于或者等于2，所述T个第一子序列与所述T个编码向量一一对应，所述T个编码向量中的第t 1个编码向量中非零元素的位置是根据第t 1个第一子序列确定的，t 1∈[1,T]，t 1与T均为正整数；
    处理单元，用于根据所述一个或多个码本对所述T个第二子序列进行内码译码，获得第一序列，其中，每个第一子序列与所述一个或多个码本中的一个列向量组对应，所述T个第一子序列中至少一个第一子序列对应的所述列向量组包括至少两个列向量。
  29. 根据权利要求28所述的装置，其特征在于，所述处理单元具体用于：
    通过检测第t 2个第二子序列，确定第t 2个第一子序列对应的码本E t2中的一个列向量组，其中，t 2∈[1,T]，t 2为正整数，所述码本E t2为所述一个或多个码本中的一个；
    根据所述第t 2个第一子序列对应的码本E t2中的一个列向量组，确定第t 2个第一子序列。
  30. 根据权利要求29所述的装置，其特征在于，所述处理单元还具体用于：
    检测所述第t 2个第二子序列，当一个列向量组中的至少一个列向量满足预设条件，确定所述一个列向量组为第t 2个第一子序列对应的码本E t2中的一个列向量组。
  31. 根据权利要求29所述的装置，其特征在于，所述处理单元还具体用于：
    检测所述第t 2个第二子序列，当一个列向量组中的任意一个列向量满足预设条件，确定所述一个列向量组为第t 2个第一子序列对应的码本E t2中的一个列向量组。
  32. 根据权利要求29所述的装置，其特征在于，所述处理单元还具体用于：
    检测所述T个第二子序列，当T 1个列向量组中的至少一个列向量满足预设条件，T 2个列向量组中的任意一个列向量满足预设条件，确定所述列向量组为所述T个第一子序列对应的码本中的列向量组，其中，T＝T 1+T 2。
  33. 根据权利要求28至32中任一项所述的装置，其特征在于，任意两个第一子序列对应的两个列向量组中的任意两个列向量互不重叠。
  34. 根据权利要求28至32中任一项所述的装置，其特征在于，任意两个第一子序列对应的两个列向量组中的至少两个列向量互不重叠。
  35. 根据权利要求28至32中任一项所述的装置，其特征在于，所述T个第一序列中，T 1个第一子序列对应的所述列向量组中的任意两个列向量互不重叠，T 2个第一子序列对应的所述列向量组中的至少两个列向量互不重叠，其中，所述T 1个第一子序列中任意一个第一子序列与所述T 2个第一子序列中任意一个第一子序列为不同的序列，T＝T 1+T 2。
  36. 根据权利要求28至35中任一项所述的装置，其特征在于，所述T个第一子序列中的每个第一子序列对应的所述码本中的一个列向量组为c个列向量组中的一个，其中，c为M/g向上取整或者向下取整的值，g为所述一个列向量组中列向量的数量，M为所述码本的列数，g为大于或等于1且小于或等于M的整数。
  37. 根据权利要求28至35中任一项所述的装置，其特征在于，所述T个第一子序列中的每个第一子序列对应的所述码本中的一个列向量组为c个列向量组中的一个，其中，c＝2 k，k为log 2p向上取整或者向下取整的值，p等于
    Figure PCTCN2021133082-appb-100004
    b为所述一个列向量组中列 向量的数量，M为所述码本的列数，其中，b为大于或等于1且小于或等于M的整数。
  38. 根据权利要求28至35中任一项所述的通信装置，其特征在于，所述处理单元还具体用于：
    对所述第一序列进行外码译码，获得原始信息序列。
  39. 一种通信的装置，其特征在于，包括：处理器，用于执行存储器中存储的计算机指令，使得所述用于通信装置执行如权利要求1至8中任一项所述的方法或如权利要求9至19中任一项所述的方法。
  40. 根据权利要求39所述的装置，还包括所述存储器和通信接口中的一种或多种，所述通信接口用于收发信号。
  41. 根据权利要求40所述的装置，所述通信接口为输入输出接口。
  42. 一种计算机可读存储介质，其特征在于，其上存储有计算机程序，所述计算机程序被通信装置计算机执行时，使得
    如权利要求1至8中任一项所述的方法被执行，或者，
    如权利要求9至19中任一项所述的方法被执行。
  43. 一种计算机程序产品，其特征在于，其包括计算机程序或指令，所述计算机程序或指令被通信装置计算机执行时，使得
    如权利要求1至8中任一项所述的方法被执行，或者
    如权利要求9至19中任一项所述的方法被执行。
  44. 一种计算机程序，当其在计算机上运行时，使得如权利要求1至8中任一项所述的方法被执行，或者如权利要求9至19中任一项所述的方法被执行。
  45. 一种通信系统，包括权利要求20至27中任一项所述的装置和权利要求28至38中任一项所述的装置。
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FENGLER ALEXANDER; JUNG PETER; CAIRE GIUSEPPE: "SPARCs and AMP for Unsourced Random Access", 2019 IEEE INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY (ISIT), 7 July 2019 (2019-07-07), pages 2843 - 2847, XP033620485, DOI: 10.1109/ISIT.2019.8849802 *
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