WO2023065378A1 - 一种阵列基板及其制备方法、显示面板 - Google Patents

一种阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2023065378A1
WO2023065378A1 PCT/CN2021/126434 CN2021126434W WO2023065378A1 WO 2023065378 A1 WO2023065378 A1 WO 2023065378A1 CN 2021126434 W CN2021126434 W CN 2021126434W WO 2023065378 A1 WO2023065378 A1 WO 2023065378A1
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Prior art keywords
common electrode
electrode layer
layer
base substrate
metal unit
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PCT/CN2021/126434
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English (en)
French (fr)
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张羿
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/614,337 priority Critical patent/US20240030230A1/en
Publication of WO2023065378A1 publication Critical patent/WO2023065378A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display panel.
  • display devices using the HFS display mode generally use the entire surface of indium tin oxide (ITO) as the common (COM) electrode. line to reduce the resistance of the common electrode.
  • ITO indium tin oxide
  • Cu traces and common electrodes are generally prepared on the flat layer (PFA). Due to poor contact between Cu traces and PFA, it is impossible to directly prepare Cu traces on PFA; ITO has good contact with PFA and is not easy to fall off. Therefore, the common electrode is generally prepared on the PFA first, and then the Cu wiring is prepared on the common electrode.
  • Cu traces are generally prepared by physical vapor deposition (PVD) process, Cu is generally carried out at 100°C, and PVD forms a film, Cu atoms have a bombardment effect on ITO, which makes the temperature of ITO rise, which leads to crystallization of ITO . After ITO is crystallized, it cannot be etched with oxalic acid, and it is also difficult to etch with nitric acid. The risk of ITO residue after etching is high.
  • PVD physical vapor deposition
  • the annealing treatment of the common electrode will lead to Cu oxidation, so generally the annealing treatment cannot be performed on the common electrode, and thus the resistance of the common electrode cannot be reduced, resulting in a relatively large resistance of the common electrode.
  • the object of the present invention is to provide an array substrate and its preparation method and display panel, which can solve the problems in the prior art that the ITO under the Cu is prone to crystallization, resulting in ITO etching residue; the common electrode cannot be annealed, resulting in common The resistance of the electrode is large and so on.
  • the present invention provides an array substrate, which includes: a base substrate; a thin film transistor layer disposed on the base substrate; a flat layer disposed on the thin film transistor layer away from the base substrate On the surface of one side; the first common electrode layer is arranged on the surface of the flat layer away from the base substrate; the metal unit is arranged on the first common electrode layer away from the base substrate and a second common electrode layer covering the surface of the metal unit and the first common electrode layer on a side away from the base substrate.
  • the thickness of the first common electrode layer is smaller than the thickness of the second common electrode layer.
  • the thickness of the first common electrode layer ranges from 50 ⁇ to 100 ⁇ ; the thickness of the second common electrode layer ranges from 400 ⁇ to 700 ⁇ .
  • the metal unit has a thickness ranging from 1000 angstroms to 3000 angstroms.
  • first common electrode layer, the metal unit and the second common electrode layer are connected in parallel.
  • the metal unit is arranged corresponding to the source of the thin film transistor layer.
  • the present invention also provides a method for preparing an array substrate, which includes the following steps: providing a base substrate; preparing a thin film transistor layer on the base substrate; Prepare a flat layer on the surface of one side of the base substrate; prepare a first common electrode layer on the surface of the flat layer away from the side of the base substrate; prepare the first common electrode layer away from the substrate preparing a metal unit on the surface of one side of the substrate; and preparing a second common electrode layer on the surface of the side of the metal unit and the first common electrode away from the base substrate.
  • the preparation method of the array substrate further includes the following steps: annealing the first common electrode layer and the second common electrode layer by using an annealing process, so that the first common electrode layer and the The second common electrode layer is crystallized.
  • the temperature range of the annealing process is 180°C-230°C, and the time range of the annealing process is 30 minutes-90 minutes.
  • the present invention also provides a display panel, which includes the array substrate described in the present invention.
  • the present invention reduces the thickness of the first common electrode layer below the metal unit, further reduces the crystallization thickness of the first common electrode layer, reduces the etching difficulty of the first common electrode layer, and further reduces the risk of the first common electrode layer remaining.
  • the second common electrode layer is used to cover the metal unit to avoid oxidation of the metal unit during annealing treatment, and then the resistance of the first common electrode layer and the second common electrode layer can be reduced through annealing treatment.
  • FIG. 1 is a schematic structural view of an array substrate according to Embodiment 1 of the present invention.
  • Fig. 3 is a structural schematic diagram of the present invention after sequentially preparing a thin film transistor layer, a first passivation layer, and a flat layer on a base substrate;
  • Fig. 4 is a schematic structural diagram after preparing the first common electrode layer and the metal unit on the basis of Fig. 3;
  • FIG. 5 is a schematic structural view of preparing a second common electrode layer on the basis of FIG. 4 and etching the first common electrode layer and the second common electrode layer;
  • FIG. 6 is a schematic structural diagram of an array substrate according to Embodiment 2 of the present invention.
  • Substrate substrate 2. Thin film transistor layer;
  • the present invention provides a display panel, which includes an array substrate 100 .
  • the array substrate 100 includes: a base substrate 1, a thin film transistor layer 2, a first passivation layer 3, a flat layer 4, a first common electrode layer 5, a metal unit 6, a second common electrode layer 7, and a second passivation layer 8 and the pixel electrode layer 9 .
  • the base substrate 1 is made of glass, so that the base substrate 1 can effectively protect the array substrate 100 .
  • the base substrate 1 may be made of other materials, and this application does not limit the material of the base substrate 1 .
  • the TFT layer 2 includes: a gate layer 21 , a gate insulating layer 22 , an active layer 23 , a source 24 and a drain 25 .
  • the gate layer 21 is disposed on the base substrate 1 .
  • the material of the gate layer 21 includes one or more of Cu, Mo, Al, IZO, ITO, Ni, MoTiNi, NiCr, and CuNb.
  • the gate insulating layer 22 covers the surface of the gate layer 21 away from the base substrate 1 , and extends to cover the base substrate 1 . It is mainly to prevent the short circuit phenomenon caused by the contact between the gate layer 21 and the active layer 23 .
  • the gate insulating layer 22 includes one or more of SiOx, SiNx and Al 2 O 3 .
  • the active layer 23 is disposed on the surface of the gate insulating layer 22 away from the base substrate 1 , and is disposed corresponding to the gate layer 21 .
  • the active layer 23 can be an oxide semiconductor or other types of semiconductors, such as IGZO, IGTO, IGO, IZO, and AIZO.
  • the source electrode 24 and the drain electrode 25 are arranged at intervals on the surface of the active layer 23 away from the base substrate 1 .
  • the source 24 and the drain 25 are electrically connected to the active layer 23 respectively.
  • the materials of the source electrode 24 and the drain electrode 25 include one or more of Cu, Mo, Al, IZO, ITO, Ni, MoTiNi, NiCr, and CuNb.
  • the first passivation layer 3 covers the source electrode 24 and the drain electrode 25 , and extends to cover the active layer 23 and the gate insulating layer 22 .
  • the first passivation layer 3 includes one or more of SiOx, SiNx and Al 2 O 3 .
  • the first passivation layer 3 is mainly used to block water vapor, hydrogen oxygen, etc. from diffusing to the channel of the thin film transistor layer 2 , so as to ensure the device electrical properties and stability of the thin film transistor layer 2 .
  • the flat layer 4 is disposed on the surface of the first passivation layer 3 away from the base substrate 1 .
  • the material of the flat layer 4 is PFA.
  • the flat layer 4 mainly provides a flat surface for the film layer above the flat layer 4 .
  • the planar layer 4 can also prevent coupling between the first common electrode layer 5 on the planar layer 4 and the source 24 and drain 25 below the planar layer.
  • the first common electrode layer 5 is disposed on the surface of the planar layer 4 away from the base substrate 1 .
  • the material of the first common electrode layer 5 is ITO.
  • the first common electrode layer 5 may also be formed by using other transparent conductive oxides, such as TCO conductive glass (FTO for short).
  • the thickness of the first common electrode layer 5 ranges from 50 angstroms to 100 angstroms. In this embodiment, the thickness of the first common electrode layer 5 is 75 angstroms.
  • the metal unit 6 is disposed on the surface of the first common electrode layer 5 away from the base substrate 1 .
  • the thickness of the metal unit 6 ranges from 1000 angstroms to 3000 angstroms. Due to the low price and low resistance of Cu, the material of the metal unit 6 in this embodiment is Cu.
  • the material of the metal unit 6 in other embodiments may also be Al, Ag and other metals.
  • the second common electrode layer 7 covers the surface of the metal unit 6 and the first common electrode layer 5 away from the substrate 1 .
  • the material of the second common electrode layer 7 is ITO.
  • the second common electrode layer 7 may also be formed by using other transparent conductive oxides, such as TCO conductive glass (FTO for short).
  • the thickness of the second common electrode layer 7 ranges from 400 angstroms to 700 angstroms.
  • using the second common electrode layer 7 to cover the metal unit 6 prevents the metal unit 6 from being oxidized during the annealing process, and the resistance of the first common electrode layer 5 and the second common electrode layer 7 can be reduced through the annealing process.
  • the first common electrode layer 5, the metal unit 6 and the second common electrode layer 7 are in contact with each other, the first common electrode layer 5, the metal unit 6 and the second common electrode layer 7 These three conductors are equivalent to being connected in parallel.
  • the first common electrode layer 5, the metal unit 6, and the second common electrode layer 7 are connected in parallel, so that the overall resistance after parallel connection can be lower than the resistance of the first common electrode layer 5, the resistance of the metal unit 6 and the second common electrode layer 7. The resistance.
  • the second passivation layer 8 covers the surface of the second common electrode layer 7 away from the base substrate 1 .
  • the second passivation layer 8 includes one or more of SiOx, SiNx and Al 2 O 3 .
  • the second passivation layer 8 can be used not only to prevent conduction and short circuit between the pixel electrode 9 and the second common electrode layer 7 , but also to isolate water vapor.
  • the present invention also provides a method for preparing an array substrate 100, which includes the following steps: S1, providing a base substrate 1; S2, preparing a thin film transistor layer 2 on the base substrate 1 ; S3, preparing a first passivation layer 3 on the surface of the thin film transistor layer 2 away from the base substrate 1; S4, preparing a flat layer on the surface of the first passivation layer 3 away from the base substrate 1 4; S5, prepare the first common electrode layer 5 on the surface of the flat layer 4 away from the base substrate 1; S6, prepare the metal unit on the surface of the first common electrode layer 5 away from the base substrate 1 6; S7, prepare the second common electrode layer 7 on the surface of the metal unit 6 and the first common electrode 5 away from the base substrate 1; S8, use an array substrate 100, which includes the following steps: S1, providing a base substrate 1; S2, preparing a thin film transistor layer 2 on the base substrate 1 ; S3, preparing a first passivation layer 3 on the surface of the thin film transistor layer 2 away from the base substrate 1;
  • the temperature range of the annealing process in S8 is 180°C-230°C, and the time range of the annealing process is 30 minutes-90 minutes.
  • the main purpose is to crystallize the first common electrode layer 5 and the second common electrode layer 7 , thereby reducing the resistance of the first common electrode layer 5 and the second common electrode layer 7 .
  • Embodiment 2 includes all the technical features of Embodiment 1.
  • the difference between Embodiment 2 and Embodiment 1 is that the metal unit 6 in Embodiment 2 is arranged correspondingly to the source 24 of the TFT layer 2 .
  • the width of the metal unit 6 is equal to or smaller than the width of the source 24 .
  • the width of the metal unit 6 is smaller than the width of the source 24 . Therefore, the black matrix (BM) can shield the metal unit 6 at the same time when shielding the source 24 , without separately increasing the area of the BM and occupying an additional opening area, thereby increasing the aperture ratio.
  • BM black matrix

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  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明涉及一种阵列基板及其制备方法、显示面板。本发明的阵列基板包括：衬底基板、薄膜晶体管层、平坦层、第一公共电极层、金属单元以及第二公共电极层。本发明减薄金属单元下方的第一公共电极层的厚度，进而减薄第一公共电极层的结晶厚度，降低第一公共电极层的蚀刻难度，进而降低第一公共电极层残留的风险。

Description

一种阵列基板及其制备方法、显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及其制备方法、显示面板。
 背景技术
目前，采用HFS显示模式的显示装置一般利用整面性的氧化铟锡（ITO）做公共（COM）电极，由于公共电极的电阻较大，因此高阶显示装置一般需要在公共电极上制备Cu走线以降低公共电极的电阻。目前，Cu走线和公共电极一般制备于平坦层（PFA）上，由于Cu走线与PFA的接触不佳，无法直接在PFA上制备Cu走线；ITO与PFA的接触良好，不易发生脱落，因此一般先在PFA上制备公共电极，然后在公共电极上制备Cu走线。
 技术问题
由于Cu走线一般采用物理气相沉积（PVD）工艺制备，Cu一般是在100℃的条件下进行，且PVD成膜，Cu原子对ITO有轰击作用，使得ITO温度升高，从而导致ITO发生结晶。ITO结晶之后，无法用草酸蚀刻，用硝硫酸也难以蚀刻，蚀刻后出现ITO残留的风险较高。
而且，由于Cu走线直接暴露于公共电极表面，而公共电极进行退火处理会导致Cu氧化，因此一般无法对公共电极进行退火处理，进而无法降低公共电极的电阻，导致公共电极的电阻较大。
 技术解决方案
本发明的目的是提供一种阵列基板及其制备方法、显示面板，其能够解决现有技术中存在的Cu下方的ITO易发生结晶，导致ITO发生蚀刻残留；公共电极无法进行退火处理，导致公共电极的电阻较大等问题。
为了解决上述问题，本发明提供了一种阵列基板，其包括：衬底基板；薄膜晶体管层，设置于所述衬底基板上；平坦层，设置于所述薄膜晶体管层远离所述衬底基板的一侧的表面上；第一公共电极层，设置于所述平坦层远离所述衬底基板的一侧的表面上；金属单元，设置于所述第一公共电极层远离所述衬底基板的一侧的表面上；以及第二公共电极层，覆盖于所述金属单元及所述第一公共电极层远离所述衬底基板的一侧的表面上。
进一步的，所述第一公共电极层的厚度小于所述第二公共电极层的厚度。
进一步的，所述第一公共电极层的厚度范围为50埃米-100埃米；所述第二公共电极层的厚度范围为400埃米-700埃米。
进一步的，所述金属单元的厚度范围为1000埃米-3000埃米。
进一步的，所述第一公共电极层、所述金属单元及所述第二公共电极层相互并联。
进一步的，所述金属单元与所述薄膜晶体管层的源极对应设置。
为了解决上述问题，本发明还提供了一种阵列基板的制备方法，其包括以下步骤：提供一衬底基板；在所述衬底基板上制备薄膜晶体管层；在所述薄膜晶体管层远离所述衬底基板的一侧的表面上制备平坦层；在所述平坦层远离所述衬底基板的一侧的表面上制备第一公共电极层；在所述第一公共电极层远离所述衬底基板的一侧的表面上制备金属单元；以及在所述金属单元及所述第一公共电极远离所述衬底基板的一侧的表面上制备第二公共电极层。
进一步的，所述的阵列基板的制备方法还包括以下步骤：采用退火工艺对所述第一公共电极层及所述第二公共电极层进行退火处理，使得所述第一公共电极层及所述第二公共电极层结晶。
进一步的，所述退火工艺的温度范围为180℃-230℃，所述退火工艺的时间范围为30分钟-90分钟。
为了解决上述问题，本发明还提供了一种显示面板，其包括本发明所述的阵列基板。
 有益效果
本发明减薄金属单元下方的第一公共电极层的厚度，进而减薄第一公共电极层的结晶厚度，降低第一公共电极层的蚀刻难度，进而降低第一公共电极层残留的风险。利用第二公共电极层覆盖于金属单元上，避免退火处理时氧化金属单元，进而可以通过退火处理降低第一公共电极层及第二公共电极层的电阻。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明的实施例1的阵列基板的结构示意图；
图2是本发明的阵列基板的制备步骤图；
图3是本发明在衬底基板上依次制备薄膜晶体管层、第一钝化层、平坦层后的结构示意图；
图4是在图3的基础上制备第一公共电极层及金属单元后的结构示意图；
图5是图4的基础上制备第二公共电极层，并对第一公共电极层和第二公共电极层进行蚀刻后的结构示意图；
图6是本发明的实施例2的阵列基板的结构示意图。
附图标记说明：
100、阵列基板；
1、衬底基板；                     2、薄膜晶体管层；
3、第一钝化层；                   4、平坦层；
5、第一公共电极层；               6、金属单元；
7、第二公共电极层；               8、第二钝化层；
9、像素电极层；
21、栅极层；                      22、栅极绝缘层；
23、有源层；                      24、源极；
25、漏极。
 本发明的实施方式
以下结合说明书附图详细说明本发明的优选实施例，以向本领域中的技术人员完整介绍本发明的技术内容，以举例证明本发明可以实施，使得本发明公开的技术内容更加清楚，使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例，下文实施例的说明并非用来限制本发明的范围。
本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，本文所使用的方向用语是用来解释和说明本发明，而不是用来限定本发明的保护范围。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。此外，为了便于理解和描述，附图所示的每一组件的尺寸和厚度是任意示出的，本发明并没有限定每个组件的尺寸和厚度。
实施例1
如图1所示，本发明提供了一种显示面板，其包括阵列基板100。阵列基板100包括：衬底基板1、薄膜晶体管层2、第一钝化层3、平坦层4、第一公共电极层5、金属单元6、第二公共电极层7、第二钝化层8以及像素电极层9。
本实施例中，衬底基板1的材质为玻璃，由此衬底基板1可以有效保护阵列基板100。其他实施例中，衬底基板1可以采用其他材质制备形成，本申请对衬底基板1的材质不做限定。
如图1所示，薄膜晶体管层2包括：栅极层21、栅极绝缘层22、有源层23、源极24以及漏极25。
如图1所示，栅极层21设置于衬底基板1上。栅极层21的材质包括Cu、Mo、Al、IZO、ITO、Ni、MoTiNi、NiCr、CuNb中的一种或多种。
如图1所示，栅极绝缘层22覆盖于栅极层21远离衬底基板1的一侧的表面上，且延伸覆盖于衬底基板1上。其主要是防止栅极层21与有源层23之间接触产生短路现象。栅极绝缘层22包括SiOx、SiNx及Al 2O 3中的一种或多种。
如图1所示，有源层23设置于栅极绝缘层22远离衬底基板1的一侧的表面上，且与栅极层21对应设置。有源层23可以为氧化物半导体或其他类型半导体，如IGZO、IGTO、IGO、IZO及AIZO等。
如图1所示，源极24及漏极25相互间隔设置于有源层23远离衬底基板1的一侧的表面上。源极24及漏极25分别电连接至有源层23。源极24及漏极25的材质均包括Cu、Mo、Al、IZO、ITO、Ni、MoTiNi、NiCr、CuNb中的一种或多种。
如图1所示，第一钝化层3覆盖于源极24及漏极25上，且延伸覆盖于有源层23及栅极绝缘层22上。第一钝化层3包括SiOx、SiNx及Al 2O 3中的一种或多种。第一钝化层3主要用于阻挡水汽、氢氧等向薄膜晶体管层2的沟道扩散，从而确保薄膜晶体管层2的器件电性和稳定性。
如图1所示，平坦层4设置于第一钝化层3远离衬底基板1的一侧的表面上。本实施例中，平坦层4的材质为PFA。平坦层4主要为平坦层4上方的膜层提供平整的表面。平坦层4还可以防止平坦层4上的第一公共电极层5与平坦层下的源极24及漏极25之间发生耦合现象。
如图1所示，第一公共电极层5设置于平坦层4远离衬底基板1的一侧的表面上。本实施例中，第一公共电极层5的材质为ITO。在其他实施例中，第一公共电极层5也可以采用其他透明导电氧化物制备形成，例如TCO导电玻璃（简称FTO）。
其中，第一公共电极层5的厚度范围为50埃米-100埃米。本实施例中，第一公共电极层5的厚度为75埃米。通过减薄第一公共电极层5的厚度，进而减薄第一公共电极层5的结晶厚度，降低第一公共电极层5的蚀刻难度，进而降低第一公共电极层5残留的风险。
如图1所示，金属单元6设置于第一公共电极层5远离衬底基板1的一侧的表面上。金属单元6的厚度范围为1000埃米-3000埃米。由于Cu的价格低，电阻小，因此本实施例中的金属单元6的材质为Cu。其他实施例中的金属单元6的材质也可以是Al、Ag等金属。
如图1所示，第二公共电极层7覆盖于金属单元6及第一公共电极层5远离衬底基板1的一侧的表面上。本实施例中，第二公共电极层7的材质为ITO。在其他实施例中，第二公共电极层7也可以采用其他透明导电氧化物制备形成，例如TCO导电玻璃（简称FTO）。第二公共电极层7的厚度范围为400埃米-700埃米。
综上，利用第二公共电极层7覆盖与金属单元6上，避免退火处理时氧化金属单元6，进而可以通过退火处理降低第一公共电极层5及第二公共电极层7的电阻。
如图1所示，由于电流是横向传导，且第一公共电极层5、金属单元6及第二公共电极层7相互接触，因而第一公共电极层5、金属单元6及第二公共电极层7这三个导体相当于是并联的。第一公共电极层5、金属单元6及第二公共电极层7相互并联，进而可以使得并联之后的整体电阻小于第一公共电极层5的电阻、金属单元6的电阻及第二公共电极层7的电阻。
如图1所示，第二钝化层8覆盖于第二公共电极层7远离衬底基板1的一侧的表面上。第二钝化层8包括SiOx、SiNx及Al 2O 3中的一种或多种。第二钝化层8既可以用于防止像素电极9和第二公共电极层7之间导通发生短路现象，还可以隔绝水汽。
如图1所示，像素电极9设置于第二钝化层8远离衬底基板1的一侧的表面上。像素电极9电连接至薄膜晶体管层2的漏极25。如图2-图5所示，本发明还提供了一种阵列基板100的制备方法，其包括以下步骤：S1，提供一衬底基板1；S2，在衬底基板1上制备薄膜晶体管层2；S3，在薄膜晶体管层2远离衬底基板1的一侧的表面上制备第一钝化层3；S4，在第一钝化层3远离衬底基板1的一侧的表面上制备平坦层4；S5，在平坦层4远离衬底基板1的一侧的表面上制备第一公共电极层5；S6，在第一公共电极层5远离衬底基板1的一侧的表面上制备金属单元6；S7，在金属单元6及第一公共电极5远离衬底基板1的一侧的表面上制备第二公共电极层7；S8，采用退火工艺对第一公共电极层5及第二公共电极层7进行退火处理；S9，在第二公共电极层7远离衬底基板1的一侧的表面上制备第二钝化层8；以及S10，在第二钝化层8远离衬底基板1的一侧的表面上制备像素电极9。
其中，S8中退火工艺的温度范围为180℃-230℃，退火工艺的时间范围为30分钟-90分钟。主要是使得第一公共电极层5及第二公共电极层7结晶，进而降低第一公共电极层5及第二公共电极层7的电阻。
实施例2
如图6所示，实施例2包括了实施例1的全部技术特征，实施例2与实施例1的区别在于：实施例2中的金属单元6与薄膜晶体管层2的源极24对应设置。金属单元6的宽度等于或小于源极24的宽度。本实施例中，金属单元6的宽度小于源极24的宽度。由此，黑色矩阵（BM）在遮挡源极24时可以同时遮蔽金属单元6，不需要单独增加BM面积，不用额外占用开口面积，进而提升开口率。
以上对本申请所提供的一种阵列基板及其制备方法、显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (15)

  1. 一种阵列基板，包括：
    衬底基板；
    薄膜晶体管层，设置于所述衬底基板上；
    平坦层，设置于所述薄膜晶体管层远离所述衬底基板的一侧的表面上；
    第一公共电极层，设置于所述平坦层远离所述衬底基板的一侧的表面上；
    金属单元，设置于所述第一公共电极层远离所述衬底基板的一侧的表面上；以及
    第二公共电极层，覆盖于所述金属单元及所述第一公共电极层远离所述衬底基板的一侧的表面上。
  2. 根据权利要求1所述的阵列基板，所述第一公共电极层的厚度小于所述第二公共电极层的厚度。
  3. 根据权利要求2所述的阵列基板，所述第一公共电极层的厚度范围为50埃米-100埃米；所述第二公共电极层的厚度范围为400埃米-700埃米。
  4. 根据权利要求1所述的阵列基板，所述金属单元的厚度范围为1000埃米-3000埃米。
  5. 根据权利要求1所述的阵列基板，所述第一公共电极层、所述金属单元及所述第二公共电极层相互并联。
  6. 根据权利要求1所述的阵列基板，所述金属单元与所述薄膜晶体管层的源极对应设置。
  7. 一种阵列基板的制备方法，包括以下步骤：
    提供一衬底基板；
    在所述衬底基板上制备薄膜晶体管层；
    在所述薄膜晶体管层远离所述衬底基板的一侧的表面上制备平坦层；
    在所述平坦层远离所述衬底基板的一侧的表面上制备第一公共电极层；
    在所述第一公共电极层远离所述衬底基板的一侧的表面上制备金属单元；以及
    在所述金属单元及所述第一公共电极远离所述衬底基板的一侧的表面上制备第二公共电极层。
  8. 根据权利要求7所述的阵列基板的制备方法，还包括以下步骤：
    采用退火工艺对所述第一公共电极层及所述第二公共电极层进行退火处理，使得所述第一公共电极层及所述第二公共电极层结晶。
  9. 根据权利要求8所述的阵列基板的制备方法，所述退火工艺的温度范围为180℃-230℃，所述退火工艺的时间范围为30分钟-90分钟。
  10. 一种显示面板，包括阵列基板，所述阵列基板包括：
    衬底基板；
    薄膜晶体管层，设置于所述衬底基板上；
    平坦层，设置于所述薄膜晶体管层远离所述衬底基板的一侧的表面上；
    第一公共电极层，设置于所述平坦层远离所述衬底基板的一侧的表面上；
    金属单元，设置于所述第一公共电极层远离所述衬底基板的一侧的表面上；以及
    第二公共电极层，覆盖于所述金属单元及所述第一公共电极层远离所述衬底基板的一侧的表面上。
  11. 根据权利要求10所述的显示面板，所述第一公共电极层的厚度小于所述第二公共电极层的厚度。
  12. 根据权利要求11所述的显示面板，所述第一公共电极层的厚度范围为50埃米-100埃米；所述第二公共电极层的厚度范围为400埃米-700埃米。
  13. 根据权利要求10所述的显示面板，所述金属单元的厚度范围为1000埃米-3000埃米。
  14. 根据权利要求10所述的显示面板，所述第一公共电极层、所述金属单元及所述第二公共电极层相互并联。
  15. 根据权利要求10所述的显示面板，所述金属单元与所述薄膜晶体管层的源极对应设置。
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