WO2023050662A1 - Circuit d'égalisation de retour de décision pam4 auto-adaptatif - Google Patents

Circuit d'égalisation de retour de décision pam4 auto-adaptatif Download PDF

Info

Publication number
WO2023050662A1
WO2023050662A1 PCT/CN2022/074065 CN2022074065W WO2023050662A1 WO 2023050662 A1 WO2023050662 A1 WO 2023050662A1 CN 2022074065 W CN2022074065 W CN 2022074065W WO 2023050662 A1 WO2023050662 A1 WO 2023050662A1
Authority
WO
WIPO (PCT)
Prior art keywords
decision
adaptive
input
unit
delay unit
Prior art date
Application number
PCT/CN2022/074065
Other languages
English (en)
Chinese (zh)
Inventor
展永政
Original Assignee
苏州浪潮智能科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州浪潮智能科技有限公司 filed Critical 苏州浪潮智能科技有限公司
Publication of WO2023050662A1 publication Critical patent/WO2023050662A1/fr
Priority to US18/232,935 priority Critical patent/US11881971B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03248—Arrangements for operating in conjunction with other apparatus
    • H04L25/03254—Operation with other circuitry for removing intersymbol interference
    • H04L25/03267—Operation with other circuitry for removing intersymbol interference with decision feedback equalisers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H04L25/03063—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure using fractionally spaced delay lines or combinations of fractionally and integrally spaced taps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H04B10/516—Details of coding or modulation
    • H04B10/54—Intensity modulation
    • H04B10/541—Digital intensity or amplitude modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03248—Arrangements for operating in conjunction with other apparatus
    • H04L25/03286—Arrangements for operating in conjunction with other apparatus with channel-decoding circuitry
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H04L25/03885—Line equalisers; line build-out devices adaptive

Definitions

  • the application relates to the technical field of chiplet high-speed interface chip design, in particular to an adaptive PAM4 decision feedback equalization circuit.
  • PAM4 4-level Pulse Amplitude Modulation, four-level pulse amplitude modulation
  • PAM4 4-level Pulse Amplitude Modulation, four-level pulse amplitude modulation
  • the end of Moore's Law will increase the demand and use of SerDes chiplets to meet the chip power and performance requirements of applications such as high-performance computing processors, high-performance AI computing, and IoT/wireless edge.
  • the equalization technology can effectively compensate the high-frequency attenuation signal caused by the chiplet interconnection channel, especially in the transmission channel with serious tailing, the equalizer at the receiving end is particularly important.
  • the traditional PAM4 DFE circuit structure includes 3 decision devices, 3 delay units and 1 thermometer decoder.
  • the traditional PAM4 DFE has a simple structure, low circuit complexity, and low power consumption, but it can only perform 1-tap coefficient compensation, which will greatly deteriorate the transmission quality and bit error performance of the link, and is not suitable for transmission channel occasions with severe tailing .
  • the circuit structure does not have an adaptive function, nor can it automatically track and compensate for changes in channel characteristics, and the traditional circuit is greatly limited in application.
  • An embodiment of the present application provides an adaptive PAM4 decision feedback equalization circuit.
  • the circuit includes: a decision feedback equalization main circuit and an adaptive circuit, wherein the main circuit includes an adder, a first decision unit, a second decision unit, a third decision unit, a first delay unit group, a second delay unit group, and a second delay unit group.
  • each delay unit group is composed of i delay units connected in series, the input signal is connected to the input of the adder, and the output of the adder is respectively connected to the first decision
  • the input connection of the second decision device, the third decision device, the output of the first decision device, the second decision device, and the third decision device are respectively connected with the first delay unit group, the second delay unit group, and the third delay unit group.
  • the input of the time unit group is connected, the output of the first delay unit group, the second delay unit group, and the third delay unit group are respectively connected to the input of the decoder, and the input of each delay unit is connected to a tap coefficient
  • the input connection of the unit, the output of the 3i tap coefficient units are connected to the input of the DSP coefficient table, the output of the DSP coefficient table is connected to the input of the adder, and the input signal and the feedback signal of the DSP coefficient table are synthesized after the adder.
  • the input signal is adaptive circuit, the output of the adaptive circuit is connected with the DSP coefficient table to adjust the tap coefficients in the DSP coefficient table, wherein i is an integer greater than 1.
  • the first decision unit and the first delay unit group form the first decision path
  • the second decision unit and the second delay unit group form the second decision path
  • the third decision unit and the third delay unit group form the second decision path.
  • the unit group constitutes the third decision path
  • the three tap coefficient units corresponding to the three delay units at the same position in the first decision path, the second decision path, and the third decision path use the same tap coefficient.
  • the DSP coefficient table is used to store the tap coefficients, and realize the multiplication and addition functions of the decision signal and the tap coefficients.
  • V x V in -V fed of the synthesized signal x
  • V fed ⁇ V t,i * ci + ⁇ V m,i * ci + ⁇ V b,i * ci
  • V in is the level of the input signal in
  • V t,i is the level of the decision signal corresponding to the i-th delay unit in the first decision path
  • V m,i is the level of the i-th delay unit in the second decision path
  • V b,i is the level of the decision signal corresponding to the i-th delay unit in the third decision path
  • c i is the tap coefficient corresponding to the i-th tap.
  • the tap coefficients are obtained by using a look-up table method, and are controlled by the amplitude of the synthesized signal.
  • the adaptive circuit includes an eye pattern monitoring module and an adaptive module
  • the adaptive module includes a comparison unit, a delay unit, and a coefficient regulation unit, wherein the synthetic signal x is connected to the input of the eye pattern monitoring module, and the eye pattern monitoring
  • the output of the module is respectively connected to the input of the comparison unit and the input of the delay unit, the other input of the comparison unit is connected to the reference value D ref , the output of the comparison unit and the output of the delay unit are respectively connected to the input of the coefficient control unit, and the coefficient control unit
  • the output is connected to the DSP coefficient table.
  • the eye diagram monitoring module uses a zero-crossing circuit and a center sampling circuit to respectively detect the time length between adjacent zero-crossing points and the level difference of intermediate samples, and output D q .
  • the comparison unit realizes the calculation of the difference ⁇ between the current period D q and the reference value D ref .
  • the sign of the difference ⁇ represents the coefficient adjustment direction of the coefficient regulation unit, and the absolute value of the difference ⁇ and D q jointly determine the size of the adjustment step.
  • the adaptive adjustment is realized based on eye diagram monitoring and an adaptive algorithm, wherein the adaptive algorithm adopts the least mean square algorithm LMS,
  • n is the current adopting time
  • T is the sampling period
  • e(n) is the error signal
  • x(n) is the equalization signal
  • ⁇ is the time constant
  • FIG. 1 is a schematic structural diagram of a traditional PAM4 decision feedback equalization circuit
  • FIG. 2 is a schematic diagram of the overall architecture of an adaptive PAM4 decision feedback equalization circuit provided by the present application according to one or more embodiments;
  • Fig. 3 is a schematic diagram of an adaptive circuit architecture provided by the present application according to one or more embodiments.
  • FIG. 1 shows a schematic structural diagram of a traditional PAM4 decision feedback equalization (Decision Feedback Equalization, DFE) circuit.
  • DFE Decision Feedback Equalization
  • the traditional PAM4 DFE circuit structure includes 3 decision devices, 3 delay units and 1 thermometer decoder.
  • V in is the level of the input signal in
  • V t , V m and V b are the three decision levels of the decision device
  • T represents the delay unit, and is delayed by one symbol period
  • D0 and D1 are the decoding Two bits in the output signal out of the device.
  • V t is 2/3, which is used to judge the PAM4 signal level "1" and "1/3”
  • V m is 0, which is used to judge the PAM4 signal level "1/3” and “-1/3”
  • V b is -2/3, which is used to judge the PAM4 signal level "-1/3" and "-1";
  • the input signal V in is compared with 3 levels to obtain a set of 3-bit decision output signals; for example: when the level of the input signal V in is higher than V t , the top, middle, and bottom decision devices all output "1"
  • the signal constitutes a 3-bit "111" output signal.
  • the 3-bit judgment output signal is decoded according to the thermometer code rules, and a 2-bit NRZ (Non-Return-to-Zero, non-return-to-zero binary signal) signal is output.
  • the traditional PAM4 DFE has a simple structure, low circuit complexity, and low power consumption, but it can only perform 1-tap coefficient compensation, which is not suitable for transmission channel occasions with severe tailing. Automatically track and compensate for changes in channel characteristics.
  • the present invention designs a high-speed adaptive PAM4 DFE circuit in a chiplet interconnection interface based on eye pattern monitoring and DSP technology.
  • each decision device multiple delay units form multiple feedback paths. Every time a clock cycle passes, the data passes through the delay unit once. When there are i taps in total, it takes i cycles before the output signal V t,1 of the decision device can be transmitted to V t,i ;
  • the feedback paths corresponding to the delay units at the same position form a set of feedback paths, for example: V t,1 , V m,1 and V b,1 form a set of feedback paths.
  • group, the group of feedback paths adopts the same tap coefficient;
  • the tap coefficient in the feedback path is obtained by using the look-up table method, and is controlled by the amplitude of the transmission signal, so as to realize the multiplication function and superposition function of the transmission signal and the coefficient;
  • the adaptive circuit receives the compensated signal x, and uses the zero-crossing circuit and the center sampling circuit to respectively detect the eye width and eye height or calculate the weighted sum of the two.
  • the DFE main circuit uses multiple delay units to form multiple feedback paths to realize multiple tap coefficient compensation. It is necessary to select the tap coefficients in the DSP through the transmission signals in each feedback path. Eye pattern monitoring updates the tap coefficients through the eye height/eye width or the weighted sum of the two, and it is necessary to judge the difference between the eye height/eye width and the ideal value in this period. Until the eye height/eye width or the weighted sum of the two monitored by the eye diagram is within a certain range, the difference calculated in the adaptive algorithm will be within a very small range, the tap coefficient will also tend to be stable, and the equalization effect will reach the maximum.
  • an adaptive PAM4 decision feedback equalization (DFE) circuit including a decision feedback equalization main circuit and an adaptive circuit, wherein the main circuit includes an adder, a first decision unit, a second decision unit, a second decision unit, and a second decision unit.
  • DFE adaptive PAM4 decision feedback equalization
  • each delay unit group is composed of i delay units connected in series , the input signal is connected to the input of the adder, the output of the adder is respectively connected to the input of the first decision unit, the second decision unit, and the third decision unit, and the output of the first decision unit, the second decision unit, and the third decision unit respectively connected with the input of the first delay unit group, the second delay unit group and the third delay unit group, and the outputs of the first delay unit group, the second delay unit group and the third delay unit group are respectively connected with
  • the input of the decoder is connected, the input of each delay unit is connected to the input of a tap coefficient unit, the output of 3i tap coefficient units is connected to the input of the DSP coefficient table, and the output of the DSP coefficient table is connected to the input of the adder , input signal and DSP coefficient table feedback signal input adaptive circuit after the synthetic signal of adder,
  • the DFE main circuit module includes modules such as an adder, 3 decision devices, 3*i delay units, a thermometer decoder, and a DSP coefficient table.
  • the adder realizes the weighting of the input signal and the feedback compensation signal
  • the decision device realizes the level judgment of the input signal
  • thermometer decoder realizes the decoding function of 3b-2b
  • the DSP coefficient table stores tap coefficients and realizes multiplication and addition functions of decision signals and coefficients.
  • the first decider and the first delay unit group form the first decision path
  • the second decider and the second delay unit group form the second decision path
  • the third decider and the third delay unit The group constitutes a third decision path
  • the three tap coefficient units corresponding to the three delay units at the same position in the first decision path, the second decision path, and the third decision path use the same tap coefficient.
  • the V t decision and i delay units T form the V t decision path; the V m decision and i delay units T form the V m decision path; the V b decision and i delay units T form the V b decision path .
  • [V t,1 , V m,1 and V b,1 ] adopt the same tap coefficient, and so on, [V t,i , V m,i and V b,i ] adopt the same tap coefficient.
  • the DSP coefficient table is used to store the tap coefficients, and realize the multiplication and addition functions of the decision signal and the tap coefficients.
  • the DSP coefficient table stores tap coefficients and implements the multiplication and addition functions of decision signals and coefficients.
  • V x V in -V fed of the synthesized signal x
  • V fed ⁇ V t,i * ci + ⁇ V m,i * ci + ⁇ V b,i * ci
  • V in is the level of the input signal in
  • V t,i is the level of the decision signal corresponding to the i-th delay unit in the first decision path
  • V m,i is the i-th delay in the second decision path
  • V b,i is the level of the decision signal corresponding to the i-th delay unit in the third decision path
  • c i is the tap coefficient corresponding to the i-th tap.
  • 1 and 0 represent the post-judgment levels
  • the selected tap coefficients are c 1 and -c 1 .
  • V fed ⁇ V t,i * ci + ⁇ V m,i * ci + ⁇ V b,i * ci .
  • V in is 0.3, greater than 0, and less than 2/3
  • V fed is fed back to V in for the next cycle again.
  • the tap coefficients are obtained using a look-up table method, and are controlled by the amplitude of the synthesized signal.
  • V x has been judged by three decision devices. If V x is higher than the decision level, the decision device will output a high level "1", if it is lower than the decision level, the decision device will output a low level "0", forming a 3-bit Initial data [V t,1 , V m,1 , V b,1 ]. After each clock cycle, the data is continuously sampled and transmitted. After j clock cycles (j ⁇ i), the output data of the jth delay unit is [V t,j ,V m,j ,V b,j ] .
  • the DSP coefficient table continuously updates the coefficients according to the adaptive circuit, and the feedback compensation signal V fed is also continuously updated accordingly.
  • the adaptive circuit includes an eye pattern monitoring module and an adaptive module
  • the adaptive module includes a comparison unit, a delay unit, and a coefficient regulation unit, wherein the synthetic signal x is connected to the input of the eye pattern monitoring module, and the eye pattern monitoring module
  • the output of the comparison unit is respectively connected to the input of the comparison unit and the input of the delay unit, the other input of the comparison unit is connected to the reference value D ref , the output of the comparison unit and the output of the delay unit are respectively connected to the input of the coefficient regulation unit, and the output of the coefficient regulation unit Link with DSP coefficient table.
  • the eye diagram monitoring module uses a zero-crossing circuit and a center sampling circuit to respectively detect the time length between adjacent zero-crossing points and the level difference of intermediate samples, and output D q .
  • the comparison unit realizes the calculation of the difference ⁇ between the current period D q and the reference value D ref .
  • the sign of the difference ⁇ represents the coefficient adjustment direction of the coefficient regulation unit, and the absolute value of the difference ⁇ and D q jointly determine the size of the adjustment step.
  • the adaptive circuit includes an eye diagram monitoring module and an adaptive module, wherein the adaptive module is composed of a comparison unit, a delay unit, and a coefficient regulation unit.
  • the eye pattern monitoring module uses a zero-crossing circuit and a center sampling circuit to detect the time length between adjacent zero-crossing points and the level difference of the intermediate sampling, that is, the eye width and eye height, and outputs D q .
  • the comparison unit in the adaptive algorithm module is used to realize the calculation of the difference ⁇ between the current period and the ideal value D ref .
  • the comparison unit is implemented with a comparator.
  • the sign of the difference ⁇ represents the coefficient adjustment direction of the coefficient control module, and the absolute value and D q together determine the size of the adjustment step. After adjustment, the coefficient value in the DSP coefficient table is continuously updated.
  • This scheme can not only automatically track channel changes in real time, but also use DSP technology to achieve multi-tap compensation and low power consumption.
  • the adaptive adjustment is realized based on eye diagram monitoring and an adaptive algorithm, wherein the adaptive algorithm adopts the least mean square algorithm LMS,
  • n is the current adopting time
  • T is the sampling period
  • e(n) is the error signal
  • x(n) is the equalization signal
  • ⁇ is the time constant
  • the coefficient control unit can be implemented by an integrator, which outputs tap coefficients.
  • the eye diagram monitoring implements sampling and evaluation of the horizontal opening and vertical opening of the eye diagram to obtain D q .
  • D ref the ideal vertical opening of each eye is 2/3.
  • D q is to monitor the eye diagram of the signal x.
  • the tap coefficient output by the coefficient control unit is fed back to the DSP coefficient table.
  • a high-speed adaptive multi-tap PAM4 DFE is designed based on CMOS technology and DSP technology.
  • DSP technology replaces the multiplier and adder in the DFE feedback loop, and also saves the design of the front-end circuit ADC, effectively reducing power consumption and avoiding the influence of ADC quantization noise on the signal.
  • the eye diagram monitoring and self-adaptive algorithm realize the automatic update of coefficients, which broadens the application scenarios of DFE and is fully applicable to various chiplet interfaces such as C2C and D2D.
  • This application scheme combines DSP technology and adaptive algorithm to realize high-speed adaptive multi-tap PAM4 DFE in the chiplet interconnection interface, which greatly reduces power consumption.
  • the coefficient update is realized by using the look-up table method and eye diagram monitoring technology, which obviously expands the application scenarios and improves the high reliability of the transmitted signal.
  • Each module in the adaptive PAM4 decision feedback equalization (DFE) circuit can be fully or partially realized by software, hardware and a combination thereof.
  • the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, and can also be stored in the memory of the computer device in the form of software, so that the processor can invoke and execute the corresponding operations of the above-mentioned modules.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

La présente demande concerne un circuit d'égalisation de retour de décision PAM4 auto-adaptatif, comprenant un circuit principal d'égalisation de retour de décision et un circuit auto-adaptatif. Le circuit principal comprend un additionneur, un premier dispositif de décision, un deuxième dispositif de décision, un troisième dispositif de décision, un premier groupe d'unités de retard, un deuxième groupe d'unités de retard, un troisième groupe d'unités de retard, un décodeur et une table de coefficients DSP ; le circuit auto-adaptatif comprend un module de surveillance du motif oculaire et un module auto-adaptatif ; et le module auto-adaptatif comprend une unité de comparaison, une unité de retard et une unité de régulation et de commande de coefficient.
PCT/CN2022/074065 2021-09-30 2022-01-26 Circuit d'égalisation de retour de décision pam4 auto-adaptatif WO2023050662A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/232,935 US11881971B2 (en) 2021-09-30 2023-08-11 Adaptive PAM4 decision feedback equalization circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111158691.4 2021-09-30
CN202111158691.4A CN113595949B (zh) 2021-09-30 2021-09-30 自适应pam4判决反馈均衡电路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/232,935 Continuation US11881971B2 (en) 2021-09-30 2023-08-11 Adaptive PAM4 decision feedback equalization circuit

Publications (1)

Publication Number Publication Date
WO2023050662A1 true WO2023050662A1 (fr) 2023-04-06

Family

ID=78242775

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/074065 WO2023050662A1 (fr) 2021-09-30 2022-01-26 Circuit d'égalisation de retour de décision pam4 auto-adaptatif

Country Status (3)

Country Link
US (1) US11881971B2 (fr)
CN (1) CN113595949B (fr)
WO (1) WO2023050662A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113595949B (zh) 2021-09-30 2021-12-21 苏州浪潮智能科技有限公司 自适应pam4判决反馈均衡电路
CN116232816B (zh) * 2023-05-08 2023-08-04 山东云海国创云计算装备产业创新中心有限公司 信号处理方法、信号传输装置及互联接口
CN117290898B (zh) * 2023-10-18 2024-05-03 中诚华隆计算机技术有限公司 一种用于Chiplet芯片系统的安全保护方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150256363A1 (en) * 2014-03-04 2015-09-10 Lsi Corporation Integrated PAM4/NRZ N-Way Parallel Digital Unrolled Decision Feedback Equalizer (DFE)
CN107534629A (zh) * 2015-04-10 2018-01-02 华为技术有限公司 判决反馈均衡装置、方法及光传输系统
CN111294297A (zh) * 2018-12-06 2020-06-16 默升科技集团有限公司 温度计编码的展开的dfe选择元件
CN112825514A (zh) * 2019-11-21 2021-05-21 默升科技集团有限公司 用于SerDes的多功能电平探测器
CN113595949A (zh) * 2021-09-30 2021-11-02 苏州浪潮智能科技有限公司 自适应pam4判决反馈均衡电路

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6233273B1 (en) * 1999-06-29 2001-05-15 Intersil Americas Inc. Rake receiver with embedded decision feedback equalizer
TWI220611B (en) * 2002-10-04 2004-08-21 Realtek Semiconductor Corp Channel estimation device of Ethernet network and method thereof
US7613238B2 (en) * 2005-09-13 2009-11-03 Mediatek Inc. Apparatus and method for decision error compensation in an adaptive equalizer
US7649932B2 (en) * 2005-11-30 2010-01-19 Microtune (Texas), L.P. Segmented equalizer
US7471008B2 (en) * 2006-03-10 2008-12-30 Deere & Company Method and system for controlling a rotational speed of a rotor of a turbogenerator
CN100562076C (zh) * 2006-06-29 2009-11-18 上海高清数字科技产业有限公司 时域自适应均衡器及其包含的判决反馈滤波器
CN101106386B (zh) * 2006-07-14 2012-01-04 上海高清数字科技产业有限公司 时域自适应均衡器
US7792187B2 (en) * 2007-08-31 2010-09-07 International Business Machines Corporation Multi-tap decision feedback equalizer (DFE) architecture eliminating critical timing path for higher-speed operation
US8873615B2 (en) * 2012-09-19 2014-10-28 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and controller for equalizing a received serial data stream
US9584345B1 (en) * 2015-12-09 2017-02-28 International Business Machines Corporation High data rate multilevel clock recovery system
US10205525B1 (en) * 2017-11-30 2019-02-12 International Business Machines Corporation PAM-4 transmitter precoder for 1+0.5D PR channels
CN110830400B (zh) * 2018-08-13 2022-08-02 上海澜至半导体有限公司 判决反馈均衡处理装置和方法
CN109831257B (zh) * 2019-02-13 2020-08-11 深圳市傲科光电子有限公司 一种pam-n cdr电路及其控制方法
CN112737570B (zh) * 2020-12-15 2022-10-28 中国科学技术大学 一种基于软件锁相环的pam4信号时钟数据恢复方法
CN112910565B (zh) * 2021-01-22 2021-10-26 天津大学 一种应用于高速光互连的pam4信号的接收解调电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150256363A1 (en) * 2014-03-04 2015-09-10 Lsi Corporation Integrated PAM4/NRZ N-Way Parallel Digital Unrolled Decision Feedback Equalizer (DFE)
CN107534629A (zh) * 2015-04-10 2018-01-02 华为技术有限公司 判决反馈均衡装置、方法及光传输系统
CN111294297A (zh) * 2018-12-06 2020-06-16 默升科技集团有限公司 温度计编码的展开的dfe选择元件
CN112825514A (zh) * 2019-11-21 2021-05-21 默升科技集团有限公司 用于SerDes的多功能电平探测器
CN113595949A (zh) * 2021-09-30 2021-11-02 苏州浪潮智能科技有限公司 自适应pam4判决反馈均衡电路

Also Published As

Publication number Publication date
CN113595949B (zh) 2021-12-21
US20230396467A1 (en) 2023-12-07
US11881971B2 (en) 2024-01-23
CN113595949A (zh) 2021-11-02

Similar Documents

Publication Publication Date Title
WO2023050662A1 (fr) Circuit d'égalisation de retour de décision pam4 auto-adaptatif
US11165613B2 (en) High-speed signaling systems with adaptable pre-emphasis and equalization
Roshan-Zamir et al. A 56-Gb/s PAM4 receiver with low-overhead techniques for threshold and edge-based DFE FIR-and IIR-tap adaptation in 65-nm CMOS
US11271783B2 (en) Decision feedback equalization embedded in a slicer
US7924912B1 (en) Method and apparatus for a unified signaling decision feedback equalizer
US20170070370A1 (en) Unequalized clock data recovery for serial i/o receiver
US8121186B2 (en) Systems and methods for speculative signal equalization
US11991025B2 (en) Transceiver parameter determination
WO2005086441A1 (fr) Egaliseur de forçage a zero de bord de bit
CN112787963B (zh) 自适应判决反馈均衡的信号处理方法、装置及系统
Lu et al. BER-optimal analog-to-digital converters for communication links
US11005567B2 (en) Efficient multi-mode DFE
CN116827735A (zh) 一种用于以太网判决反馈结构切换双模式的系数更新方法
US11973622B2 (en) Adaptive non-speculative DFE with extended time constraint for PAM-4 receiver
CN108111446B (zh) 一种接收机均衡模块和均衡方法
CN1665225A (zh) 用于以太网物理层的判决反馈均衡器
Azadet et al. DSP implementation issues in 1000BASE-T Gigabit Ethernet
Chang et al. Eye diagram estimation and equalizer design method for PAM4
Lai et al. An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline Receiver
Wang et al. Soft Decision Adjusted Modulus Algorithm for Blind Equalization
Kang et al. A 42Gb/s PAM-8 Transmitter with Feed-Forward Tomlinson-Harashima Precoding in 28nm CMOS
WO2023098483A1 (fr) Procédé et appareil de réception de signal, et dispositif électronique et support de stockage
US20230421349A1 (en) Feedforward jitter correction
Hu et al. An Adaptive Equalizer for 56 Gb/s Duo-Binary SerDes
Li et al. A 5 Gbps serial link pre-emphasis transmitter with a novel-designed register based multiplexer

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22874065

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE