WO2023050273A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2023050273A1
WO2023050273A1 PCT/CN2021/122094 CN2021122094W WO2023050273A1 WO 2023050273 A1 WO2023050273 A1 WO 2023050273A1 CN 2021122094 W CN2021122094 W CN 2021122094W WO 2023050273 A1 WO2023050273 A1 WO 2023050273A1
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WIPO (PCT)
Prior art keywords
transistor
base substrate
orthographic projection
active
conductive layer
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PCT/CN2021/122094
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English (en)
French (fr)
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WO2023050273A9 (zh
Inventor
王彬艳
黄耀
刘聪
王予
王本莲
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/122094 priority Critical patent/WO2023050273A1/zh
Priority to CN202180002780.1A priority patent/CN116724681A/zh
Priority to US17/800,847 priority patent/US20240224678A1/en
Priority to JP2023550287A priority patent/JP2024532989A/ja
Priority to EP21958851.4A priority patent/EP4303931A4/en
Publication of WO2023050273A1 publication Critical patent/WO2023050273A1/zh
Publication of WO2023050273A9 publication Critical patent/WO2023050273A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • the display panel provides a power terminal to the pixel driving circuit through a power line.
  • the voltage drop of the power line itself, there is a voltage difference between the power terminals at different positions of the display panel, resulting in uneven display of the display panel.
  • a display panel includes a plurality of pixel driving circuits distributed in an array along a first direction and a second direction, the first direction intersects the second direction,
  • the pixel driving circuit includes a driving transistor and a capacitor, the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the power line.
  • the display panel further includes: a base substrate, a second conductive layer, and a fifth conductive layer, the second conductive layer is located on one side of the base substrate, and the second conductive layer includes: a plurality of second conductive parts, A plurality of the second conductive parts are provided in one-to-one correspondence with the plurality of pixel drive circuits, and the second conductive parts are used to form the second electrodes of the capacitors in the corresponding pixel drive circuits. At least two adjacent second conductive parts distributed in the first direction are sequentially connected to form a conductive line.
  • the fifth conductive layer is located on the side of the second conductive layer away from the base substrate, and the fifth conductive layer includes: a plurality of the power lines, and a plurality of the power lines are on the base substrate
  • the orthographic projections of are distributed along the first direction at intervals and extend along the second direction, and at least one conductive line is connected to a plurality of the power lines.
  • the second conductive layer further includes: a plurality of first connecting parts, a plurality of first connecting parts, the first connecting parts are connected to between the two second conductive parts.
  • the display panel further includes: a first active layer and a light shielding layer.
  • the first active layer is located between the base substrate and the second conductive layer, and the first active layer includes: a plurality of third active portions, which are provided in one-to-one correspondence with a plurality of the pixel driving circuits , the third active portion is used to form a channel region of the driving transistor in the pixel driving circuit corresponding thereto.
  • the light-shielding layer is located between the base substrate and the first active layer, and the light-shielding layer includes: a plurality of light-shielding parts and a plurality of second connecting parts, which are arranged in one-to-one correspondence with a plurality of the pixel driving circuits,
  • the orthographic projection of the light shielding part on the base substrate covers the orthographic projection of the third active part in the corresponding pixel driving circuit on the base substrate;
  • the second connecting part is connected to Between two adjacent light-shielding parts in the first direction, and the size of the orthographic projection of the second connection part on the base substrate in the second direction is smaller than that of the light-shielding part in the second direction
  • the size of the orthographic projection on the base substrate in the second direction wherein, between two adjacent pixel drive circuits of the same group, the second connecting portion on the base substrate
  • the orthographic projection and the orthographic projection of the first connecting portion on the base substrate are at least partially coincident.
  • the display panel includes a plurality of repeating units distributed along the first direction and the second direction, each of the repeating units includes two of the pixel driving circuits, and the two of the repeating units
  • the pixel driving circuit includes a first pixel driving circuit and a second pixel driving circuit distributed along the first direction, and the first pixel driving circuit and the second pixel driving circuit are mirror-symmetrically arranged.
  • the plurality of first connection parts include: a first sub-connection part, the first sub-connection part is connected between two second conductive parts in the repeating units adjacent in the first direction, so The size of the orthographic projection of the first sub-connection part on the base substrate in the second direction is smaller than the size of the orthographic projection of the second conductive part on the base substrate in the second direction size.
  • the orthographic projection of the first sub-connection part on the base substrate is located at the position where the second connection part is Orthographic projection on the substrate substrate.
  • the pixel driving circuit further includes a first transistor and a second transistor, the first pole of the first transistor is connected to the gate of the driving transistor, and the second pole is connected to the first initial transistor.
  • signal line the first pole of the second transistor is connected to the gate of the driving transistor, the second pole is connected to the second pole of the driving transistor
  • the display panel further includes: a second active layer, a second active layer The active layer is located between the second conductive layer and the fifth conductive layer, the second active layer includes: a first active part and a second active part, and the first active part is used to form the The channel region of the first transistor; the second active part is connected with the first active part for forming the channel region of the second transistor.
  • the power line includes a second extension; the orthographic projection of the second extension on the base substrate covers the orthographic projection of the first active part on the base substrate, the second active portion An orthographic projection of the source portion on the substrate substrate.
  • the power cord further includes: a first extension part and a third extension part, and the second extension part is connected between the first extension part and the third extension part ;
  • the size of the orthographic projection of the second extension on the base substrate in the first direction is larger than the size of the orthographic projection of the first extension on the base substrate in the first direction
  • the size of the orthographic projection of the second extension on the base substrate in the first direction is larger than the size of the orthographic projection of the third extension on the base substrate in the first direction
  • the dimension of the orthographic projection of the second extension on the base substrate in the first direction is L1
  • the orthographic projection of the second extension on the base substrate is in the The dimension in the second direction is L2, wherein L1/L2 is less than or equal to 1/2.
  • a notch or a hollow structure is formed on the second extension part.
  • the pixel driving circuit further includes a fourth transistor, the first pole of the fourth transistor is connected to the data line, the second pole is connected to the first pole of the driving transistor, and the display
  • the panel further includes: a first active layer, a first conductive layer, and a third conductive layer, the first active layer is located between the base substrate and the second conductive layer, and the first active layer includes a first Four active parts, the fourth active part is used to form the channel region of the fourth transistor; the first conductive layer is located between the first active layer and the second conductive layer, and the first conductive layer is located between the first active layer and the second conductive layer.
  • a conductive layer includes a second grid line, the orthographic projection of the second grid line on the base substrate covers the orthographic projection of the fourth active portion on the base substrate, and along the first direction, the partial structure of the second gate line is used to form the gate of the fourth transistor; the third conductive layer is located between the second active layer and the fifth conductive layer, and the third conductive layer Including a first reset signal line, the orthographic projection of the first reset signal line on the base substrate covers the orthographic projection of the first active part on the base substrate, the first reset signal line A part of the structure is used to form the gate of the first transistor; the gap is formed on the side of the second extension portion facing the fourth active portion, and the gap is formed on the base substrate The orthographic projection is located between the orthographic projection of the second gate line on the base substrate and the orthographic projection of the first reset signal line on the base substrate.
  • the plurality of first connecting parts further include: a second sub-connecting part, the second sub-connecting part is connected to two of the second conductive parts in the same repeating unit. between departments.
  • the pixel driving circuit further includes a fifth transistor, the first pole of the fifth transistor is connected to the power line, and the second pole is connected to the first pole of the driving transistor.
  • the first active layer includes: a fifth active part and an eighth active part, the fifth active part is used to form the channel region of the fifth transistor; the eighth active part is connected to the fifth active part The active part is away from the side of the third active part.
  • the display panel further includes: a first conductive layer and a fourth conductive layer, the first conductive layer is located between the first active layer and the second conductive layer, and the first conductive layer includes: an enable signal line, the orthographic projection of the enabling signal line on the substrate extends along the first direction and covers the orthographic projection of the fifth active portion on the substrate, the enabling The partial structure of the signal line is used to form the gate of the fifth transistor; the fourth conductive layer is located between the second conductive layer and the fifth conductive layer, and the fourth conductive layer includes: a first bridge portion , the first bridge part is respectively connected to the eighth active part in the first pixel driving circuit, the eighth active part in the second pixel driving circuit, the first pixel driving circuit and the first pixel driving circuit through via holes.
  • the second sub-connection part between the second pixel driving circuits, and the first bridge part is connected to the power line through a via hole.
  • a hollow portion is formed on the first bridging portion.
  • the orthographic projection of the hollow portion on the base substrate at least partially coincides with the orthographic projection of the enabling signal line on the base substrate.
  • the second direction is a column direction
  • one power supply line is provided corresponding to each column of the pixel driving circuit
  • the power lines in the pixel driving circuit are respectively connected to the first bridge parts through via holes.
  • the first bridging portion includes: a first via hole contact portion, a second via hole contact portion, a third via hole contact portion, a fourth via hole contact portion, and a fifth via hole contact portion.
  • the first via hole contact portion passes through The second via hole is connected to the second sub-connection part; the second via hole contact part is arranged opposite to the first via hole contact part in the second direction, and is connected to the first pixel driving circuit through the via hole.
  • the eighth active part; the third via hole contact part is arranged opposite to the first via hole contact part in the second direction, and is connected to the eighth active part in the second pixel driving circuit through a via hole ;
  • the fourth via hole contact portion is connected between the first via hole contact portion and the second via hole contact portion, and is connected to the power line in the first pixel driving circuit through a via hole;
  • the fifth via hole The contact portion is connected between the first via hole contact portion and the third via hole contact portion, and is connected to the power line in the second pixel driving circuit through the via hole, and the fifth via hole contact portion is connected to the second pixel driving circuit through a via hole.
  • the fourth via hole contact portion is oppositely arranged in the first direction; wherein, the first via hole contact portion, the second via hole contact portion, the third via hole contact portion, the fourth via hole contact portion, The fifth via contact portion surrounds the hollow portion.
  • the first active layer further includes: a plurality of ninth active parts, and the plurality of ninth active parts are arranged in one-to-one correspondence with a plurality of the repeating units, and in the same repetition In the unit, the ninth active part is connected between the eighth active part in the first pixel driving circuit and the eighth active part in the second pixel driving circuit.
  • the first bridge portion is mirror-symmetric to a mirror-symmetric plane of the first pixel driving circuit and the second pixel driving circuit.
  • the pixel driving circuit further includes a fourth transistor, a sixth transistor, and a seventh transistor, the first pole of the fourth transistor is connected to the data line, and the second pole is connected to the driving transistor.
  • the first pole of the sixth transistor is connected to the second pole of the driving transistor, the first pole of the seventh transistor is connected to the second pole of the sixth transistor, and the second pole is connected to the second initial signal line.
  • the display panel further includes: a first active layer and a first conductive layer.
  • the first active layer is located between the base substrate and the second conductive layer, and the first active layer includes: a third active part, a fourth active part, a sixth active part, a seventh active part Active part, the third active part is used to form the channel region of the driving transistor; the fourth active part is connected to one side of the third active part, and is used to form the channel of the fourth transistor region; the sixth active part is connected to the side of the third active part away from the fourth active part, and is used to form the channel region of the sixth transistor; the seventh active part is connected to the The side of the sixth active part away from the third active part is used to form the channel region of the seventh transistor; the first conductive layer is located between the first active layer and the second conductive layer between.
  • the first conductive layer includes: a second gate line, an enable signal line, a second reset signal line, and a first conductive part, and the orthographic projection of the second gate line on the base substrate extends along the first direction and cover the orthographic projection of the fourth active portion on the substrate, the partial structure of the second gate line is used to form the gate of the fourth transistor;
  • the enable signal line is on the substrate
  • the orthographic projection on the substrate extends along the first direction and covers the orthographic projection of the sixth active portion on the base substrate, and part of the structure of the enabling signal line is used to form the sixth transistor gate;
  • the orthographic projection of the second reset signal line on the base substrate extends along the first direction and covers the orthographic projection of the seventh active portion on the base substrate, the second reset
  • the partial structure of the signal line is used to form the gate of the seventh transistor;
  • the orthographic projection of the first conductive part on the base substrate covers the orthographic projection of the third active part on the base substrate,
  • the first conductive part is used to form the gate of
  • the orthographic projection of the first conductive part on the substrate is located at the orthographic projection of the second gate line on the substrate and the enabling signal line is at the between the orthographic projections on the base substrate; the orthographic projection of the second reset signal line on the base substrate is located far from the orthographic projection of the enabling signal line on the base substrate One side of the orthographic projection of a conductive part on the base substrate.
  • the first direction is a row direction
  • the second gate line in the current row of pixel driving circuits is multiplexed as the second reset signal line in the previous row of pixel driving circuits.
  • the pixel driving circuit further includes a first transistor and a second transistor, the first pole of the first transistor is connected to the gate of the driving transistor, and the second pole is connected to the first initial transistor.
  • a signal line, the first pole of the second transistor is connected to the gate of the driving transistor, and the second pole is connected to the second pole of the driving transistor.
  • the display panel further includes: a second active layer, a third conductive layer, the second active layer is located between the second conductive layer and the fifth conductive layer, and the second active layer includes: the first An active part and a second active part, the first active part is used to form the channel region of the first transistor; the second active part is connected to the first active part and is used to form the second active part the channel region of the transistor.
  • the third conductive layer is located between the second active layer and the fifth conductive layer, the third conductive layer includes: a first reset signal line, a first gate line, and the first reset signal line is on the substrate
  • the orthographic projection on the base substrate covers the orthographic projection of the first active part on the base substrate, and the partial structure of the first reset signal line is used to form the top gate of the first transistor; the first gate
  • the orthographic projection of the line on the substrate covers the orthographic projection of the second active portion on the substrate, and part of the structure of the first gate line is used to form the top gate of the second transistor .
  • the orthographic projection of the first gate line on the base substrate is located at the orthographic projection of the first conductive portion on the base substrate and the second gate line is at the Between the orthographic projections on the base substrate, the orthographic projection of the first reset signal line on the base substrate is located far from the orthographic projection of the second gate line on the base substrate One side of the orthographic projection of a conductive part on the base substrate.
  • the second conductive layer further includes: the first initial signal line, the third reset signal line, and the third gate line, and the first initial signal line is on the substrate
  • the orthographic projection on the substrate is located on the side where the orthographic projection of the first reset signal line on the base substrate is away from the orthographic projection of the first conductive portion on the base substrate; the third reset signal line passes through The via hole is connected to the first reset signal line, the orthographic projection on the base substrate covers the orthographic projection of the first active part on the base substrate, and the partial structure of the third reset signal line used to form the bottom gate of the first transistor; the orthographic projection of the third gate line on the base substrate covers the orthographic projection of the second active part on the base substrate, and the third gate line A partial structure of lines is used to form the bottom gate of the second transistor.
  • the pixel driving circuit further includes a fifth transistor, the first pole of the fifth transistor is connected to the power line, the second pole is connected to the first pole of the driving transistor, and the gate
  • the first and second transistors are N-type transistors; the driving transistors, fourth transistors, fifth transistors, sixth transistors, and seventh transistors are P-type transistors.
  • the pixel driving circuit further includes a sixth transistor and a seventh transistor, the first pole of the sixth transistor is connected to the second pole of the driving transistor, and the seventh transistor The first pole is connected to the second pole of the sixth transistor, and the second pole is connected to the second initial signal line; the fourth conductive layer further includes the second initial signal line.
  • all the second conductive parts distributed in the first direction are connected in sequence to form the conductive lines, and each of the conductive lines is connected to each of the power lines.
  • a display device wherein the display device includes the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit in the related art
  • FIG. 2 is a timing diagram of each node in a driving method of the pixel driving circuit shown in FIG. 1;
  • FIG. 3 is a structural layout of an exemplary embodiment of a display panel of the present disclosure
  • Fig. 4 is the structural layout of the second conductive layer in Fig. 3;
  • FIG. 5 is a structural layout of the fifth conductive layer in FIG. 3;
  • FIG. 6 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 7 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 8 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 9 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • Fig. 10 is a structural layout of the light-shielding layer in Fig. 9;
  • FIG. 11 is a structural layout of the first active layer in FIG. 9;
  • FIG. 12 is a structural layout of the first conductive layer in FIG. 9;
  • FIG. 13 is a structural layout of the second conductive layer in FIG. 9;
  • FIG. 14 is a structural layout of the second active layer in FIG. 9;
  • FIG. 15 is a structural layout of the third conductive layer in FIG. 9;
  • FIG. 16 is a structural layout of the fourth conductive layer in FIG. 9;
  • FIG. 17 is a structural layout of the fifth conductive layer in FIG. 9;
  • FIG. 18 is a structural layout of the light-shielding layer and the first active layer in FIG. 9;
  • FIG. 19 is a structural layout of the light-shielding layer, the first active layer, and the first conductive layer in FIG. 9;
  • FIG. 20 is a structural layout of the light-shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG. 9;
  • FIG. 21 is a structural layout of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG. 9;
  • FIG. 22 is a structural layout of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG. 9;
  • FIG. 23 is a structural layout of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG. 9;
  • FIG. 24 is a partial cross-sectional view of the display panel of the present disclosure cut along the dotted line AA in FIG. 9;
  • FIG. 25 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 26 is a structural layout of the fourth conductive layer in FIG. 25;
  • FIG. 27 is a structural layout of the fifth conductive layer in FIG. 25;
  • FIG. 28 is a structural layout of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG. 25;
  • Fig. 29 is a diagram of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in another exemplary embodiment of the display panel of the present disclosure. Structural layout;
  • FIG. 30 is a structural layout of a light-shielding layer in another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 31 is a structural layout of a light-shielding layer in another exemplary embodiment of a display panel of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first pole of the fourth transistor T4 is connected to the data signal terminal Da
  • the second pole is connected to the first pole of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2
  • the first pole of the fifth transistor T5 is connected to the A power supply terminal VDD
  • the second pole is connected to the first pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM
  • the gate of the driving transistor T3 is connected to the node N
  • the first pole of the second transistor T2 is connected to the node N
  • the second pole is connected to the node N.
  • the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor T3, and the second pole is connected to the first pole of the seventh transistor T7.
  • the pixel driving circuit may be connected to a light emitting unit OLED for driving the light emitting unit OLED to emit light, and the light emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power supply terminal VSS.
  • the first transistor T1 and the second transistor T2 may be N-type transistors, for example, the first transistor T1 and the second transistor T2 may be N-type metal oxide transistors, and the N-type metal oxide transistors have a small leakage current, Therefore, the light-emitting phase can be avoided, and the node N leaks electricity through the first transistor T1 and the second transistor T2.
  • the drive transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, for example, the drive transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be P-type low-temperature polysilicon transistors.
  • P-type low-temperature polysilicon transistors have high carrier mobility, which is conducive to realizing high resolution, high response speed, high pixel density, high Aperture ratio display panel.
  • the first initial signal terminal and the second initial signal terminal may output the same or different voltage signals according to actual conditions.
  • FIG. 2 it is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 1 .
  • G1 represents the timing of the first gate driving signal terminal G1
  • G2 represents the timing of the second gate driving signal terminal G2
  • Re1 represents the timing of the first reset signal terminal Re1
  • Re2 represents the timing of the second reset signal terminal Re2
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a first reset phase t1, a compensation phase t2, a second reset phase t3, and a light emitting phase t4.
  • the first reset phase t1 the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N.
  • the compensation stage t2 the first gate drive signal terminal G1 outputs a high-level signal, the second gate drive signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da Output the driving signal to write the voltage Vdata+Vth (that is, the sum of the voltage Vdata and Vth) to the node N, where Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3.
  • the second reset The signal terminal Re2 outputs a low level signal
  • the seventh transistor T7 is turned on
  • the second initial signal terminal Vinit2 inputs an initial signal to the second pole of the sixth transistor T6.
  • Light-emitting stage t4 the enable signal terminal EM outputs a low-level signal
  • the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the drive transistor output current formula is as follows:
  • the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
  • the power line used to provide the first power terminal itself has a voltage drop, which leads to a voltage difference at the first power terminal at different positions of the display panel, thereby causing uneven display on the display panel.
  • this exemplary embodiment provides a display panel, wherein the display panel may include a plurality of pixel driving circuits distributed in an array along a first direction and a second direction, and the first direction and the second direction Intersecting, for example, the first direction may be a row direction, and the second direction may be a column direction.
  • the structure of the pixel driving circuit in the display panel can be shown in FIG. 1 .
  • the display panel may further include: a base substrate, a second conductive layer, and a fifth conductive layer, as shown in FIGS.
  • the structural layout of the second conductive layer in FIG. 3 , and FIG. 5 is the structural layout of the fifth conductive layer in FIG. 3 .
  • the second conductive layer can be located on one side of the base substrate, and the second conductive layer can include: a plurality of second conductive parts 22, and a plurality of second conductive parts 22 can be connected with a plurality of the pixel driving circuits.
  • the second conductive part 22 can be used to form the second electrode of the capacitor in the corresponding pixel driving circuit, and the plurality of second electrodes distributed in the first direction X
  • the conductive parts are connected to form a conductive line 2;
  • the fifth conductive layer may be located on the side of the second conductive layer away from the base substrate, and the fifth conductive layer may include: a plurality of the power supply lines VDD, a plurality of Orthographic projections of the power supply lines VDD on the base substrate are spaced along the first direction X and extend along the second direction Y, and each conductive line 2 may be connected to each power supply line VDD.
  • a plurality of power lines VDD and a plurality of conductive lines 2 can form a grid structure, and the power lines of the grid structure have relatively small resistance, so that the display panel can improve display uniformity of the display panel.
  • the second conductive layer may further include a plurality of first connecting portions 21, and the first connecting portions 21 are connected to the second conductive portions 22 adjacent in the first direction. between.
  • a plurality of second conductive parts 22 distributed at intervals in the first direction X may be connected by a first connection part to form a conductive line 2 .
  • the first connection portion 21 may also be located on other conductive layers.
  • the power line VDD and the conductive line 2 can be connected through a via hole.
  • the display panel can also include a fourth conductive layer, which can be located between the second conductive layer and the fifth conductive layer. Between the conductive layers, the fourth conductive layer may include a plurality of first bridging portions 41 .
  • the first bridge portion 41 can be connected to the first connecting portion 21 through the via hole H
  • the power line VDD can be connected to the first bridge portion 41 through the via hole H, so that the power line VDD can be connected to the conductive line 2 .
  • the black squares in this exemplary embodiment represent via holes, and this exemplary embodiment only marks the positions of some via holes.
  • the power line VDD may also be directly connected to the second conductive portion through a via hole.
  • each conductive line 2 may be connected to each power line VDD. It should be understood that, in other exemplary embodiments, the conductive line 2 may also be connected to only a part of the power line VDD.
  • FIG. 6 it is a structural layout of another exemplary embodiment of the display panel of the present disclosure, wherein the first row of conductive lines 2 is connected to the second to fourth column power lines VDD, and the second row of conductive lines 2 Connected to the first to third column power lines VDD, the display panel can also reduce the voltage drop of the power lines.
  • all the second conductive portions 22 distributed at intervals in the first direction X in the display panel are sequentially connected to form the conductive lines 2 .
  • the conductive wire 2 may also be formed by connecting only some conductive parts 22 .
  • FIG. 7 it is a structural layout of another exemplary embodiment of the display panel of the present disclosure, wherein every adjacent two conductive parts 22 are connected in the first direction X to form a conductive line 2 , the display panel The voltage drop on the power line can also be reduced.
  • FIG. 8 it is a structural layout of another exemplary embodiment of the display panel of the present disclosure.
  • each plurality of second conductive parts 22 forms a conductive line 2
  • the display panel may include a plurality of conductive lines 2 distributed along rows and columns, wherein the conductive lines 2 in adjacent rows and adjacent columns are alternately distributed in the row direction, that is, The orthographic projections of two conductive wires 2 located in adjacent rows and adjacent columns on the base substrate partially intersect in areas covered by movement in the column direction.
  • the staggered conductive lines 2 can be connected to at least two power lines VDD.
  • the display panel can also reduce the voltage drop of the power line.
  • the display panel of the present disclosure may also include pixel driving circuits with other structures. As long as the capacitance of the pixel driving circuit is connected to the power line, the corresponding display panel may adopt the above structure to reduce the voltage drop of the power line itself.
  • the orthographic projection of a structure on the substrate extends along a certain direction. It can be understood that the entire orthographic projection of the structure on the substrate extends along this direction, that is, the The orthographic projection of the structure on the substrate can extend straight or bent along this direction.
  • Different structural parts in the same structural film layer for example, the second conductive layer, the fifth conductive layer
  • the structural layer A is located on the side of the structural layer B away from the base substrate. It can be understood that the structural layer A is formed on the side of the structural layer B away from the base substrate.
  • part of the structure of the structural layer A may also be located at the same physical height of the structural layer B or lower than the physical height of the structural layer B, wherein the base substrate is the height reference.
  • This exemplary embodiment also provides another display panel, which may include a base substrate, a light-shielding layer, a first active layer, a first conductive layer, a second conductive layer, and a second active layer that are sequentially stacked. , a third conductive layer, a fourth conductive layer, and a fifth conductive layer, wherein an insulating layer may be provided between the above layers.
  • FIGS. 9-23 FIG. 9 is a structural layout of another exemplary embodiment of a display panel of the present disclosure, FIG. 10 is a structural layout of a light-shielding layer in FIG. 9 , and FIG. 11 is a first active layer in FIG.
  • Figure 12 is the structural layout of the first conductive layer in Figure 9
  • Figure 13 is the structural layout of the second conductive layer in Figure 9
  • Figure 14 is the structural layout of the second active layer in Figure 9
  • Figure 15 is The structural layout of the third conductive layer in FIG. 9,
  • FIG. 16 is the structural layout of the fourth conductive layer in FIG. 9,
  • FIG. 17 is the structural layout of the fifth conductive layer in FIG. 9, and
  • the structural layout of the active layer is the structural layout of the light-shielding layer, the first active layer, and the first conductive layer in Figure 9, and Figure 20 is the light-shielding layer, the first active layer, the first conductive layer,
  • the structural layout of the second conductive layer Figure 21 is the structural layout of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in Figure 9,
  • Figure 22 is the light-shielding layer in Figure 9 , the structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer
  • FIG. 23 shows the light shielding layer, the first active layer, and the first conductive layer in FIG.
  • the display panel may include a plurality of pixel driving circuits shown in FIG. 1 .
  • the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in the first direction X, the first pixel driving circuit P1 and the second pixel driving circuit P2 Mirror symmetrical settings are possible.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit
  • the display panel may include a plurality of repeating units arranged in an array in the first direction X and the second direction Y.
  • the first direction X and the second direction Y may intersect, for example, the first direction may be a row direction, and the second direction may be a column direction.
  • the light-shielding layer may include a plurality of light-shielding portions 61 distributed in the first direction X, and a second connecting portion 62 connected between the light-shielding portions 61 .
  • the light-shielding layer may be a conductive structure, for example, the light-shielding layer may be a light-shielding metal layer.
  • the first active layer may include a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion. 77 , the eighth active part 78 , and the ninth active part 79 .
  • the third active portion 73 can be used to form the channel region of the driving transistor T3;
  • the fourth active portion 74 can be used to form the channel region of the fourth transistor T4;
  • the fifth active portion 75 can be used to form the channel region of the fourth transistor T4.
  • the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 76 can be used to form the channel region of the seventh transistor T7;
  • the part 78 is connected to the side of the fifth active part 75 away from the third active part 73, and the ninth active part 79 is connected to the eighth active part 78 in the first pixel driving circuit P1 and the second pixel driving circuit P2. between the eighth active parts 78 .
  • the eighth active part 78 can be used to form the first pole of the fifth transistor.
  • the eighth active part in two adjacent pixel driving circuits is connected through the ninth active part 79, so that The voltage difference of the first power supply terminals in the adjacent pixel driving circuits can be reduced.
  • the orthographic projection of the light-shielding portion 61 on the base substrate can cover the orthographic projection of the third active portion 73 on the base substrate, and the light-shielding portion 61 can reduce the influence of light on the characteristics of the driving transistor.
  • the first active layer may be formed of polysilicon material.
  • the driving transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 and the seventh transistor T7 may be P-type low temperature polysilicon thin film transistors.
  • the first conductive layer may include: a first conductive portion 11 , a second gate line G2 , an enable signal line EM, and a second reset signal line Re2 .
  • the second gate line G2 can be used to provide the second gate drive signal terminal in FIG. 1; the enable signal line EM can be used to provide the enable signal terminal in FIG. 1; the second reset signal line Re2 can be used to provide the signal terminal in FIG. In the second reset signal terminal.
  • the orthographic projection of the second gate line G2 on the substrate, the orthographic projection of the enable signal line EM on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate can all extend along the first direction X .
  • the orthographic projection of the second gate line G2 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate, and part of the structure of the second gate line G2 is used to form the gate of the fourth transistor.
  • the orthographic projection of the enable signal line EM on the base substrate covers the orthographic projection of the fifth active portion 75 on the base substrate and the orthographic projection of the sixth active portion 76 on the base substrate, so that the orthographic projection of the enable signal line EM Part of the structure can be used to form the gates of the fifth transistor T5 and the sixth transistor T6 respectively.
  • the orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projection of the seventh active portion 77 on the substrate, and part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. pole.
  • the orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 73 on the substrate, and the first conductive portion 11 can be used to form the gate of the drive transistor T3 and the first electrode of the capacitor .
  • the first direction X may be a row direction. As shown in FIG. 19 , the second gate line G2 in the pixel driving circuit of this row can be multiplexed as the second reset signal line Re2 in the pixel driving circuit of the previous row.
  • the light-shielding layer can be connected to a stable power supply terminal.
  • the light-shielding layer can be connected to the first power supply terminal, the first initial signal terminal, the second initial signal terminal, etc. in FIG. voltage, thereby reducing the voltage fluctuation of the gate of the driving transistor T3 during the light-emitting phase.
  • the display panel can use the first conductive layer as a mask to conduct conductorization treatment on the first active layer, that is, the region of the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area not covered by The area covered by the first conductive layer forms a conductor structure.
  • the second conductive layer may include: a first initial signal line Vinit1 , a third reset signal line 2Re1 , a third gate line 2G1 , and a plurality of second conductive portions 22 .
  • the first initial signal line Vinit1 is used to provide the first initial signal terminal in FIG. 1
  • the third reset signal line 2Re1 can be used to provide the first reset signal terminal in FIG. 1
  • the third gate line 2G1 can be used to provide The first gate drive signal terminal in Figure 1.
  • the orthographic projection of the first initial signal line Vinit1 on the substrate, the orthographic projection of the third reset signal line 2Re1 on the substrate, and the orthographic projection of the third gate line 2G1 on the substrate can all be along the first direction X extend.
  • the second conductive layer may also include a plurality of first connection parts, and the plurality of first connection parts may include: a second sub-connection part connected between two second conductive parts 22 in the same repeating unit 212 .
  • the first sub-connection portion 211 connected between two second conductive portions 22 in adjacent repeating units.
  • the orthographic projection of the first sub-connection portion 211 on the substrate can be the same as the orthographic projection of the second connection portion 62 on the substrate.
  • the orthographic projection of the second sub-connecting portion 212 on the base substrate may at least partially coincide with the orthographic projection of the second connecting portion 62 on the base substrate. This arrangement can reduce the light-shielding influence of the first connection portion on the display panel, and improve the transmittance of the display panel.
  • the size of the orthographic projection of the first sub-connecting portion 211 on the base substrate in the second direction Y may be smaller than the size of the orthographic projection of the second conductive portion 22 on the base substrate in the second direction Y
  • the first The orthographic projection of the sub-connecting portion 211 on the base substrate may be located on the orthographic projection of the second connecting portion 62 on the base substrate, and this setting can greatly improve the transmittance of the display panel.
  • the size of the orthographic projection of the second sub-connecting portion 212 on the base substrate in the second direction Y is equal to the size of the orthographic projection of the second conductive portion 22 on the base substrate in the second direction Y.
  • the size of the orthographic projection of the second sub-connecting portion 212 on the base substrate in the second direction Y may also be smaller than the orthographic projection of the second conductive portion 22 on the base substrate.
  • the dimension projected in the second direction Y may not be provided between two second conductive portions 22 in adjacent repeating units, that is, the two second conductive portions 22 in adjacent repeating units are in the first direction. X upper interval setting.
  • the second active layer can include an active portion 81, and the active portion 81 can include a first active portion 811 and a second active portion 812, and the first active portion 811 can be used for forming the channel region of the first transistor; the second active portion 812 may be used for forming the channel region of the second transistor T2.
  • the second active layer may be formed of InGaZnO, and correspondingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors.
  • the orthographic projection of the third gate line 2G1 on the substrate may cover the orthographic projection of the second active portion 812 on the substrate, and part of the structure of the third gate line 2G1 may be used to form the bottom gate of the second transistor.
  • the orthographic projection of the third reset signal line 2Re1 on the substrate can cover the orthographic projection of the first active portion 811 on the substrate, and the partial structure of the third reset signal line 2Re1 can be used to form the bottom of the first transistor T1. grid.
  • the third conductive layer may include a first reset signal line 3Re1 and a first gate line 3G1 .
  • Both the orthographic projection of the first reset signal line 3Re1 on the base substrate and the orthographic projection of the first gate line 3G1 on the base substrate may extend along the first direction X.
  • the first reset signal line 3Re1 can be used to provide the first reset signal terminal in FIG. 1
  • the orthographic projection of the first reset signal line 3Re1 on the substrate can cover the orthographic projection of the first active portion 811 on the substrate.
  • Part of the structure of the first reset signal line 3Re1 can be used to form the top gate of the first transistor T1, and at the same time, the first reset signal line 3Re1 can be connected to the third reset signal terminal 2Re1 through a via hole located at the edge routing area of the display panel.
  • the first gate line 3G1 can be used to provide the first gate driving signal terminal in FIG. 1 , and the orthographic projection of the first gate line 3G1 on the substrate can cover the orthographic projection of the second active portion 812 on the substrate.
  • Part of the structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2, and at the same time, the first gate line 3G1 can be connected to the third gate line 2G1 through a via hole located in the wiring area along the edge of the display panel. As shown in FIGS.
  • the orthographic projection of the first conductive part 11 on the base substrate may be located between the orthographic projection of the first gate line 3G1 on the base substrate and Between the orthographic projection of the enable signal line EM on the base substrate; the orthographic projection of the first reset signal line 3Re1 on the base substrate may be located on the first gate line 3G1 on the base substrate The orthographic projection of is away from the side of the orthographic projection of the first conductive portion 11 on the base substrate.
  • the orthographic projection of the second gate line G2 on the base substrate may be located between the orthographic projection of the first gate line 3G1 on the base substrate and the orthographic projection of the first reset signal line 3Re1 on the base substrate.
  • the orthographic projection of the second reset signal line Re2 on the base substrate may be located away from the orthographic projection of the enable signal line EM on the base substrate away from the first conductive portion 11 on the base substrate. side of the orthographic projection.
  • the display panel can use the third conductive layer as a mask to conduct conductorization treatment on the second active layer, that is, the region of the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area not covered by The area covered by the third conductive layer forms a conductor structure.
  • the fourth conductive layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, and a sixth bridge portion. 46.
  • the first bridge part 41 can be connected to the second sub-connection part 212 through two via holes, and respectively connected to the eighth active part 78 in the first pixel driving circuit P1 and the active part 78 in the second pixel driving circuit P2 through the via holes.
  • the eighth active part 78 is used to connect the first electrode of the fifth transistor and the second electrode of the capacitor C.
  • the first bridge portion 41 may be mirror-symmetrical to the mirror-symmetric plane of the first pixel driving circuit P1 and the second pixel driving circuit P2 .
  • the second bridge part 42 can connect the first active layer between the sixth active part 76 and the seventh active part 77 through a via hole, so as to connect the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7.
  • the second bridge portion 42 can be used to connect the first electrodes of the light emitting units in the display panel.
  • the third bridging part 43 can respectively connect the first active layer between the sixth active part 76 and the third active part 73, the second active part 812 on the side away from the first active part 811 through via holes.
  • the second active layer is used to connect the second pole of the second transistor T2, the first pole of the sixth transistor T6, and the second pole of the driving transistor T3.
  • the fourth bridge portion 44 can be respectively connected to the second active layer between the first active portion 811 and the second active portion 812 and the first conductive portion 11 through via holes, so as to connect the first electrode of the second transistor T2 and the first electrode of the second transistor T2. Drives the gate of the transistor. As shown in FIG. 13 , an opening 221 is formed on the second conductive portion 22 , and the orthographic projection of the via hole connected between the first conductive portion 11 and the fourth bridging portion 44 on the base substrate is located at the opening 221 on the base substrate.
  • the fifth bridge portion 45 can be connected to the second active layer on the side away from the second active portion 812 of the first active portion 811 and the first initial signal line Vinit1 respectively through via holes, so as to connect the second pole of the first transistor and the first initial signal line Vinit1.
  • the sixth bridge portion 46 may be connected to the first active layer of the fourth active portion 74 on a side away from the third active portion 73 through a via hole, so as to be connected to the first electrode of the fourth transistor.
  • the second initial signal line Vinit2 can be used to provide the second initial signal terminal in FIG.
  • the source layer is connected to the second pole of the seventh transistor and the second initial signal terminal.
  • the fifth conductive layer may include a plurality of power supply lines VDD, a plurality of data lines Da, and a seventh bridge portion 57 .
  • the orthographic projection of the power line VDD on the base substrate and the orthographic projection of the data line Da on the base substrate can both extend along the second direction Y.
  • the power line VDD can be used to provide the first power terminal in FIG. 1
  • the data line Da can be used to provide the data signal terminal in FIG. 1 .
  • each column of pixel driving circuits can be provided with a corresponding power line
  • the power line VDD in the first pixel driving circuit P1 can be connected to the first bridge part 41 through a via hole
  • the power line VDD in the second pixel driving circuit P2 VDD can be connected to the same first bridge portion 41 through a via hole, thereby connecting the first pole of the fifth transistor and the first power supply terminal.
  • the data line Da can be connected to the sixth bridge portion 46 through a via hole, so as to connect the first electrode of the fourth transistor and the data signal terminal.
  • the data line Da is only partially shown, and it can be understood that the orthographic projection of the data line Da on the base substrate extends along the second direction Y.
  • the seventh bridge portion 57 can be connected to the second bridge portion 42 through a via hole to connect to the first electrode of the seventh transistor, and the seventh bridge portion 57 can be used to connect to the first electrode of the light emitting unit. It should be understood that, in other exemplary embodiments, multiple columns of pixel driving circuits may also be provided with one power line correspondingly. As shown in FIG.
  • the power line VDD may include a first extension VDD1, a second extension VDD2, and a third extension VDD3, and the second extension VDD2 is connected between the first extension VDD1 and the third extension VDD3,
  • the size of the orthographic projection of the second extension VDD2 on the base substrate in the first direction X may be larger than the size of the orthographic projection of the first extension VDD1 on the base substrate in the first direction X.
  • the size of the orthographic projection of the second extension VDD2 on the base substrate in the first direction X may be larger than the orthographic projection of the third extension VDD3 on the base substrate Dimensions in the first direction X.
  • the orthographic projection of the second extension portion VDD2 on the base substrate can cover the orthographic projection of the first active portion 811 on the base substrate and the orthographic projection of the second active portion 812 on the base substrate.
  • the second extension portion VDD2 The influence of light on the characteristics of the first transistor T1 and the second transistor T2 can be reduced.
  • the black square drawn on the side of the fourth conductive layer away from the base substrate indicates that the fourth conductive layer is connected to the via holes of other levels on the side facing the base substrate;
  • the black square on the side of the fifth conductive layer facing away from the base substrate indicates that the fifth conductive layer is connected to via holes at other levels on the side facing the base substrate.
  • the black square only indicates the position of the via hole, and different via holes represented by black squares at different positions may penetrate through different insulating layers.
  • the via hole connected between the first bridging portion 41 and the second sub-connecting portion 212 may pass through the insulating layer between the second conductive layer and the fourth conductive layer;
  • the via hole between the source parts 78 may pass through the insulating layer between the first active layer and the fourth conductive layer; it is connected to the second active layer on the side of the second active part 812 away from the first active part 811
  • the via hole between the third bridge portion 43 can penetrate the insulating layer between the fourth conductive layer and the second active layer; the via hole connected between the fourth bridge portion 44 and the first conductive portion 11 can penetrate the first conductive layer.
  • the insulating layer between the fourth conductive layer and the first conductive layer; the via hole connected between the power line VDD and the first bridging portion 41 may penetrate through the insulating layer between the fourth conductive layer and the fifth conductive layer.
  • the drawing method and meaning of the via holes in the figure are the same as those in this exemplary embodiment.
  • FIG. 24 is a partial cross-sectional view of the display panel taken along the dotted line AA in FIG. 9 .
  • the display panel may further include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, a Two dielectric layers 97, a passivation layer 98, and a flat layer 99, wherein, the base substrate 90, the light shielding layer, the first insulating layer 91, the first active layer, the second insulating layer 92, the first conductive layer, the third Insulating layer 93, second conductive layer, fourth insulating layer 94, second active layer, fifth insulating layer 95, third conductive layer, first dielectric layer 96, second dielectric layer 97, fourth conductive layer , the passivation layer 98 , the flat layer 99 , and the fifth conductive layer are stacked in sequence.
  • the first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be a single-layer structure or a multi-layer structure, and the first insulating layer 91, the second insulating layer 92.
  • the material of the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 96, the second dielectric layer Layer 97, passivation layer 98 can be silicon nitride layer;
  • the material of planar layer 99 can be organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate Ethylene glycol ester (PEN), silicon-glass bonding structure (SOG) and other materials.
  • the base substrate 90 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence, and the barrier layer may be an inorganic material.
  • the material of the first conductive layer, the second conductive layer, and the third conductive layer may be one or an alloy of molybdenum, aluminum, copper, titanium, niobium, or a molybdenum/titanium alloy or laminated layers.
  • the material of the fourth conductive layer and the fifth conductive layer may include metal materials, such as molybdenum, aluminum, copper, titanium, niobium or one of them or alloys, or molybdenum/titanium alloys or laminated layers, etc., or may be titanium/aluminum / titanium stack.
  • only a flat layer may be provided between the fourth conductive layer and the fifth conductive layer in the display panel without a passivation layer.
  • the display panel may include a plurality of pixel driving circuits shown in FIG. 1 , and the plurality of pixel driving circuits are included in the first direction X
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 are adjacently distributed, and the first pixel driving circuit P1 and the second pixel driving circuit P2 can be arranged mirror-symmetrically.
  • the display panel may also include a base substrate, a light-shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a Five conductive layers.
  • the layout structure of the light-shielding layer in the display panel shown in FIG. 25 is the same as that of the light-shielding layer in the display panel shown in FIG.
  • the light-shielding layer may be a conductive structure, for example, the light-shielding layer may be a light-shielding metal layer.
  • the layout structure of the first active layer in the display panel shown in FIG. 25 is the same as that of the first active layer in the display panel shown in FIG. 74 , fifth active portion 75 , sixth active portion 76 , seventh active portion 77 , eighth active portion 78 , and ninth active portion 79 .
  • the layout structure of the first conductive layer in the display panel shown in FIG. 25 is the same as that of the first conductive layer in the display panel shown in FIG. Enable signal line EM, second reset signal line Re2.
  • the layout structure of the second conductive layer in the display panel shown in FIG. 25 is the same as that of the second conductive layer in the display panel shown in FIG. 9 , and the second conductive layer may also include: the first initial signal line Vinit1, the third reset signal line 2Re1 , a third gate line 2G1 , and a plurality of second conductive portions 22 .
  • the layout structure of the second active layer in the display panel shown in FIG. 25 is the same as that of the second active layer in the display panel shown in FIG. An active part 811 and a second active part 812 .
  • the layout structure of the third conductive layer in the display panel shown in FIG. 25 is the same as that in the display panel shown in FIG. 9 , and the third conductive layer may also include a first reset signal line 3Re1 and a first gate line 3G1 .
  • Figure 26 is the structural layout of the fourth conductive layer in Figure 25
  • Figure 27 is the structural layout of the fifth conductive layer in Figure 25
  • Figure 28 is the light shielding layer and the first active layer in Figure 25 , the structural layout of the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer.
  • the fourth conductive layer may also include a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, and a sixth bridging portion.
  • the first bridge portion 41 in FIG. 26 has a different layout structure from the first bridge portion 41 in FIG. 16 .
  • the first bridging portion 41 may be formed with a hollow portion 410 , and the area where the hollow portion 410 is located may at least partially form a light-transmitting area of the display panel.
  • the light-transmitting area of the display panel can be understood as the area that is not covered by any structure with light-shielding effect, that is, the area that is not covered by the light-shielding layer, the first conductive layer, the first active layer, the second conductive layer, and the second active layer. , the area covered by the third conductive layer, the fourth conductive layer, and the fifth conductive layer.
  • This setting can improve the transmittance of the display panel.
  • the orthographic projection of the hollow part 410 on the base substrate can also at least partially overlap with the orthographic projection of the enabling signal line EM on the base substrate.
  • the parasitic capacitance of the EM increases the charging speed of the enable signal line, thereby improving the response speed of the fifth transistor T5 and the sixth transistor T6.
  • the first bridging portion 41 may include: a first via hole contact portion 411, a second via hole contact portion 412, a third via hole contact portion 413, a fourth via hole contact portion 414, The fifth via contact part 415 .
  • the first via hole contact portion 411 can be connected to the second sub-connection portion 212 through a via hole; the second via hole contact portion 412 is disposed opposite to the first via hole contact portion 411 in the second direction Y, and The eighth active portion 78 in the first pixel driving circuit P1 is connected through a via hole; the third via hole contact portion 413 is disposed opposite to the first via hole contact portion 411 in the second direction Y, and The eighth active portion 78 in the second pixel driving circuit P2 is connected through a via hole; the fourth via hole contact portion 414 is connected between the first via hole contact portion 411 and the second via hole contact portion 412 and connected to the power line VDD in the first pixel driving circuit P1 through a via hole; the fifth via hole contact portion 415 is connected between the first via hole contact portion 411 and the third via hole contact portion 413 and connected to the power line VDD in the second pixel driving circuit P2 through a via hole, the fifth via hole contact portion 415 and the fourth via hole contact portion 414 are arranged opposite to
  • first via hole contact portion 411, the second via hole contact portion 412, the third via hole contact portion 413, the fourth via hole contact portion 414, and the fifth via hole contact portion 415 may surround the hollow portion. 410.
  • structure A and structure B are arranged opposite to each other in the first direction X, it can be understood that the orthographic projection of structure A on the substrate and the orthographic projection of structure B on the substrate are arranged at intervals from the first direction X , and the area covered by the orthographic projection of structure A on the substrate moving infinitely in the first direction X and the area covered by the orthographic projection of structure B on the substrate moving infinitely in the first direction X are at least partially coincident .
  • structure A and structure B are arranged opposite to each other in the second direction Y.
  • the orthographic projection of structure A on the substrate and the orthographic projection of structure B on the substrate are in the second direction Y. set at intervals, and the area covered by the orthographic projection of structure A on the substrate moving infinitely in the second direction Y is at least at least the area covered by the orthographic projection of structure B on the substrate moving infinitely in the second direction Y partially overlapped.
  • the orthographic projection of the first via contact portion 411 on the substrate, the orthographic projection of the second via contact portion 412 on the substrate, the third via contact may be located between the orthographic projection of the fourth via contact portion 414 on the base substrate and the orthographic projection of the fifth via contact portion 415 on the base substrate; in the second direction On Y, the orthographic projection of the fourth via contact portion 414 on the substrate and the orthographic projection of the fifth via contact portion 415 on the substrate may be located at the orthogonal projection of the first via contact portion 411 on the substrate.
  • the orthographic projection on the base substrate may be located between the orthographic projection of the first via contact portion 411 on the base substrate and the orthographic projection of the third via contact portion 413 on the base substrate.
  • the hollow part 410 can be a closed opening or a non-closed opening. In this exemplary embodiment, the hollow part 410 can be a non-closed opening. As shown in FIG. 26 , the second via contact part 412 and the third via contact part There may be a certain gap between 413. It should be understood that in other exemplary embodiments, the second via contact portion 412 and the third via contact portion 413 may also be directly connected to form the hollow portion 410 that closes the opening. .
  • the fifth conductive layer may also include a power line VDD, a data line Da, and a seventh bridge portion 57 .
  • the fifth conductive layer shown in FIG. 27 is different from the fifth conductive layer shown in FIG. 17 in that the power line VDD in FIG. 27 has a different layout structure from the power line VDD in FIG. 17 .
  • a notch VDD0 is formed on the second extension part VDD2, and at least part of the area where the notch VDD0 is located can form the light-transmitting area of the display panel. The transmittance of the display panel can be improved.
  • the notch VDD0 may be formed on the side of the second extension portion VDD2 facing the fourth active portion 74, and the orthographic projection of the notch VDD0 on the base substrate may be located at the second gate line Between the orthographic projection of G2 on the base substrate and the orthographic projection of the first reset signal line Vinit1 on the base substrate. It should be understood that, in other exemplary embodiments, the gap VDD0 may also be formed at other positions of the second extension portion VDD2. In addition, the display panel can also improve the transmittance of the display panel by forming a hollow structure on the second extension portion VDD2.
  • the power line VDD may form a grid structure with the second conductive portion horizontally connected in the first direction X, so that the power line on the display panel has a smaller self-resistance.
  • this exemplary embodiment can also properly reduce the width of the power line VDD to increase the transmittance of the display panel.
  • the present exemplary embodiment may appropriately reduce the size of the second extension VDD2 in the first direction X.
  • the size of the orthographic projection of the second extension VDD2 on the base substrate in the first direction X is L1
  • the dimension in the second direction Y is L2, wherein L1/L2 may be less than or equal to 1/2, for example, L1/L2 may be 1/2, 1/3/, 1/4, etc.
  • the partial cross-sectional view along the dotted line AA in FIG. 25 may be the same as the cross-sectional view shown in FIG. 24 .
  • FIG. 29 it is a light-shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a second conductive layer in another exemplary embodiment of the display panel of the present disclosure.
  • Two into one, and the two-in-one via hole can be mirror-symmetrical to the mirror symmetry plane of the first pixel driving circuit and the second pixel driving circuit; the first bridge part 41 is respectively connected to the eighth active part and the two via holes of the eighth active part in the second pixel driving circuit can be combined into one, and the combined via hole can connect the ninth active part 79 to connect the second active part 79 in the first pixel driving circuit.
  • the eighth active part and the eighth active part in the second pixel driving circuit, and the combined via hole may be mirror symmetrical to the mirror symmetric plane of the first pixel driving circuit and the second pixel driving circuit.
  • FIG. 30 it is a structural layout of a light-shielding layer in another exemplary embodiment of a display panel of the present disclosure.
  • the orthographic projection of the second connecting portion 62 connected between two adjacent light shielding portions 61 in the first direction X on the base substrate may have a size L1 in the second direction Y, and the light shielding portion 61
  • the size of the orthographic projection on the base substrate in the second direction Y may be L2, L1 may be greater than or equal to 80%*L2 and less than or equal to L2, for example, L1 may be equal to 80%*L2, 90%*L2, L2, etc. This setting reduces the pressure drop across the opacity.
  • FIG. 31 it is a structural layout of a light-shielding layer in another exemplary embodiment of a display panel of the present disclosure.
  • the difference between FIG. 31 and FIG. 30 is that the second connecting portion 62 is formed with a hollow portion 621 , wherein there may be one or more hollow portions 621 .
  • This setting can reduce the influence of the light-shielding layer on the transmittance of the display panel.
  • the scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto, for example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width of each signal line and The spacing can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figure, and the figures described in this disclosure are only structural schematic diagrams.
  • This exemplary embodiment also provides a display device, which includes the above-mentioned display panel.
  • the display device may be a display device such as a mobile phone, a tablet computer, or a television.

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Abstract

一种显示面板和显示装置，显示面板包括沿第一方向(X)和第二方向(Y)阵列分布的多个像素驱动电路，第一方向(X)和第二方向(Y)相交，像素驱动电路包括驱动晶体管(T3)、电容(C)，电容(C)的第一电极连接驱动晶体管(T3)的栅极，第二电极连接电源线(VDD)，显示面板还包括：衬底基板(90)、第二导电层、第五导电层。第二导电层位于衬底基板(90)的一侧，第二导电层包括：多个第二导电部(22)，多个第二导电部(22)与多个像素驱动电路一一对应设置，第二导电部(22)用于形成对应的像素驱动电路中电容(C)的第二电极，在第一方向(X)上分布的至少两个相邻的第二导电部(22)连接以形成导电线(2)；第五导电层位于第二导电层背离衬底基板(90)的一侧，第五导电层包括：多条电源线(VDD)，多条电源线(VDD)在衬底基板上的正投影沿第一方向(X)间隔分布且沿第二方向(Y)延伸，至少一条导电线(2)连接多条电源线(VDD)。显示面板提高了显示均一性。

Description

显示面板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板和显示装置。
背景技术
相关技术中，显示面板通过电源线向像素驱动电路提供电源端，然而，由于电源线自身存在压降，从而导致显示面板不同位置上的电源端存在电压差，进而导致显示面板显示不均匀。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括沿第一方向和第二方向阵列分布的多个像素驱动电路，所述第一方向和所述第二方向相交，所述像素驱动电路包括驱动晶体管、电容，所述电容的第一电极连接所述驱动晶体管的栅极，第二电极连接电源线。所述显示面板还包括：衬底基板、第二导电层、第五导电层，第二导电层位于所述衬底基板的一侧，所述第二导电层包括：多个第二导电部，多个所述第二导电部与多个所述像素驱动电路一一对应设置，所述第二导电部用于形成与其对应的所述像素驱动电路中所述电容的第二电极，在所述第一方向上分布的至少两个相邻的所述第二导电部依次连接以形成导电线。第五导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第五导电层包括：多条所述电源线，多条所述电源线在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，至少一条所述导电线连接多条所述电源线。
本公开一种示例性实施例中，所述第二导电层还包括：多个第一连接部，多个第一连接部，所述第一连接部连接于在所述第一方向上相邻的两所述第二导电部之间。所述显示面板还包括：第一有源层、遮光层。第一有源层位于所述衬底基板和所述第二导电层之间，所述第一有源层包括：多个第三有源部，与多个所述像素驱动电路一一对应设置，所述第三有源部用于形成与其对应的所述像素驱动电路中所述驱动晶体管的沟道区。遮光层位于所述衬底基板和所述第一有源层之间，所述遮光层包括：多个遮光部、多个第二连接部，与多个所述像素驱动电路一一对应设置，所述遮光部在所述衬底基板上的正投影覆盖与其对应的所述像素驱动电路中所述第三有源部在所述 衬底基板上的正投影；所述第二连接部连接于在所述第一方向上相邻的两所述遮光部之间，且所述第二连接部在所述衬底基板上的正投影在所述第二方向上的尺寸小于所述遮光部在所述衬底基板上的正投影在所述第二方向上的尺寸；其中，在同一组相邻的两所述像素驱动电路之间，所述第二连接部在所述衬底基板上的正投影和所述第一连接部在所述衬底基板上的正投影至少部分重合。
本公开一种示例性实施例中，所述显示面板包括沿所述第一方向和第二方向分布的多个重复单元，每个所述重复单元包括两个所述像素驱动电路，两个所述像素驱动电路包括沿所述第一方向分布的第一像素驱动电路和第二像素驱动电路，所述第一像素驱动电路和所述第二像素驱动电路镜像对称设置。多个所述第一连接部中包括：第一子连接部，第一子连接部连接于在所述第一方向上相邻的所述重复单元中两所述第二导电部之间，所述第一子连接部在所述衬底基板上的正投影在所述第二方向上的尺寸小于所述第二导电部在所述衬底基板上的正投影在所述第二方向上的尺寸。
本公开一种示例性实施例中，在同一组相邻的两所述像素驱动电路之间，所述第一子连接部在所述衬底基板上的正投影位于所述第二连接部在所述衬底基板上的正投影上。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管、第二晶体管，所述第一晶体管的第一极连接所述驱动晶体管的栅极，第二极连接第一初始信号线，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极，所述显示面板还包括：第二有源层，第二有源层位于所述第二导电层和所述第五导电层之间，所述第二有源层包括：第一有源部、第二有源部，第一有源部用于形成所述第一晶体管的沟道区；第二有源部与所述第一有源部连接，用于形成所述第二晶体管的沟道区。所述电源线包括第二延伸部；所述第二延伸部在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影、所述第二有源部在所述衬底基板上的正投影。
本公开一种示例性实施例中，所述电源线还包括：第一延伸部、第三延伸部，所述第二延伸部连接于所述第一延伸部和所述第三延伸部之间；所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸大于第一延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸，且所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第三延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸；所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸为L1， 所述第二延伸部在所述衬底基板上的正投影在所述第二方向上的尺寸为L2，其中，L1/L2小于等于1/2。
本公开一种示例性实施例中，所述第二延伸部上形成有缺口或者镂空结构。
本公开一种示例性实施例中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极，所述显示面板还包括：第一有源层、第一导电层、第三导电层，第一有源层位于所述衬底基板和所述第二导电层之间，所述第一有源层包括第四有源部，所述第四有源部用于形成所述第四晶体管的沟道区；第一导电层位于所述第一有源层和所述第二导电层之间，所述第一导电层包括第二栅线，所述第二栅线在所述衬底基板上的正投影覆盖所述第四有源部在所述衬底基板上的正投影，且沿所述第一方向延伸，所述第二栅线的部分结构用于形成所述第四晶体管的栅极；第三导电层位于所述第二有源层和第五导电层之间，所述第三导电层包括第一复位信号线，所述第一复位信号线在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极；所述缺口形成于所述第二延伸部面向所述第四有源部的侧边，且所述缺口在所述衬底基板上的正投影位于所述第二栅线在所述衬底基板上的正投影和所述第一复位信号线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，多个所述第一连接部中还包括：第二子连接部，所述第二子连接部连接于同一所述重复单元中的两所述第二导电部之间。所述像素驱动电路还包括第五晶体管，所述第五晶体管的第一极连接所述电源线，第二极连接所述驱动晶体管的第一极。所述第一有源层包括：第五有源部、第八有源部，第五有源部用于形成所述第五晶体管的沟道区；第八有源部连接于所述第五有源部远离所述第三有源部的一侧。所述显示面板还包括：第一导电层、第四导电层，第一导电层位于所述第一有源层和所述第二导电层之间，所述第一导电层包括：使能信号线，所述使能信号线在所述衬底基板上的正投影沿所述第一方向延伸，且覆盖所述第五有源部在所述衬底基板上的正投影，所述使能信号线的部分结构用于形成所述第五晶体管的栅极；第四导电层位于所述第二导电层和所述第五导电层之间，所述第四导电层包括：第一桥接部，所述第一桥接部分别通过过孔连接所述第一像素驱动电路中的第八有源部、所述第二像素驱动电路中的第八有源部、所述第一像素驱动电路和所述第二像素驱动电路之间的第二子连接部，且所述第一桥接部通过过孔连接所述电源线。
本公开一种示例性实施例中，所述第一桥接部上形成有镂空部。
本公开一种示例性实施例中，所述镂空部在所述衬底基板上的正投影与所述使能信号线在所述衬底基板上的正投影至少部分重合。
本公开一种示例性实施例中，所述第二方向为列方向，每列所述像素驱动电路对应设置一条所述电源线，所述第一像素驱动电路中的电源线和所述第二像素驱动电路中的电源线分别通过过孔连接所述第一桥接部。所述第一桥接部包括：第一过孔接触部、第二过孔接触部、第三过孔接触部、第四过孔接触部、第五过孔接触部，第一过孔接触部通过过孔连接所述第二子连接部；第二过孔接触部与所述第一过孔接触部在所述第二方向上相对设置，且通过过孔连接所述第一像素驱动电路中的第八有源部；第三过孔接触部与所述第一过孔接触部在所述第二方向上相对设置，且通过过孔连接所述第二像素驱动电路中的第八有源部；第四过孔接触部连接于所述第一过孔接触部和所述第二过孔接触部之间，且通过过孔连接所述第一像素驱动电路中的电源线；第五过孔接触部连接于所述第一过孔接触部和所述第三过孔接触部之间，且通过过孔连接所述第二像素驱动电路中的电源线，所述第五过孔接触部与所述第四过孔接触部在所述第一方向上相对设置；其中，所述第一过孔接触部、第二过孔接触部、第三过孔接触部、第四过孔接触部、第五过孔接触部环绕形成所述镂空部。
本公开一种示例性实施例中，所述第一有源层还包括：多个第九有源部，多个第九有源部与多个所述重复单元一一对应设置，在同一重复单元中，所述第九有源部连接于所述第一像素驱动电路中的第八有源部和所述第二像素驱动电路中的第八有源部之间。
本公开一种示例性实施例中，所述第一桥接部以所述第一像素驱动电路和所述第二像素驱动电路的镜像对称面镜像对称。
本公开一种示例性实施例中，所述像素驱动电路还包括第四晶体管、第六晶体管、第七晶体管，所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第七晶体管的第一极连接所述第六晶体管的第二极，第二极连接第二初始信号线。所述显示面板还包括：第一有源层、第一导电层。第一有源层位于所述衬底基板和所述第二导电层之间，所述第一有源层包括：第三有源部、第四有源部、第六有源部、第七有源部，第三有源部用于形成所述驱动晶体管的沟道区；第四有源部连接于所述第三有源部的一侧，用于形成所述第四晶体管的沟道区；第六有源部连接于所述第三有源部远离所述第四有源部的一侧，用于形成所述第六晶体管的沟道区；第七有源部连接于所述第六有 源部远离所述第三有源部的一侧，用于形成所述第七晶体管的沟道区；第一导电层位于所述第一有源层和所述第二导电层之间。所述第一导电层包括：第二栅线、使能信号线、第二复位信号线、第一导电部，第二栅线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第四有源部在所述衬底基板上的正投影，所述第二栅线的部分结构用于形成所述第四晶体管的栅极；使能信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第六有源部在所述衬底基板上的正投影，所述使能信号线的部分结构用于形成所述第六晶体管的栅极；第二复位信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第七有源部在所述衬底基板上的正投影，所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极；第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极和所述电容的第二电极。其中，在同一像素驱动电路中，所述第一导电部在所述衬底基板上的正投影位于所述第二栅线在所述衬底基板上的正投影和所述使能信号线在所述衬底基板上的正投影之间；所述第二复位信号线在所述衬底基板上的正投影位于所述使能信号线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧。
本公开一种示例性实施例中，所述第一方向为行方向，本行像素驱动电路中的第二栅线复用为上一行像素驱动电路中的第二复位信号线。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管、第二晶体管，所述第一晶体管的第一极连接所述驱动晶体管的栅极，第二极连接第一初始信号线，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极。所述显示面板还包括：第二有源层、第三导电层，第二有源层位于所述第二导电层和所述第五导电层之间，所述第二有源层包括：第一有源部、第二有源部，第一有源部用于形成所述第一晶体管的沟道区；第二有源部连接所述第一有源部，用于形成所述第二晶体管的沟道区。第三导电层位于所述第二有源层和所述第五导电层之间，所述第三导电层包括：第一复位信号线、第一栅线，第一复位信号线在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的顶栅；第一栅线在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第一栅线的部分结构用于形成所述第二晶体管的顶栅。在同一所述像素驱动电路中，所述第一栅线在所述衬底基板上的正投影位于所述第一导电部在所述衬底基板上的正投影和所述第二栅线在所述衬 底基板上的正投影之间，所述第一复位信号线在所述衬底基板上的正投影位于所述第二栅线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧。
本公开一种示例性实施例中，所述第二导电层还包括：所述第一初始信号线、第三复位信号线、第三栅线，所述第一初始信号线在所述衬底基板上的正投影位于所述第一复位信号线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧；第三复位信号线通过过孔连接所述第一复位信号线，在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第三复位信号线的部分结构用于形成所述第一晶体管的底栅；第三栅线在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第三栅线的部分结构用于形成所述第二晶体管的底栅。
本公开一种示例性实施例中，所述像素驱动电路还包括第五晶体管，所述第五晶体管的第一极连接所述电源线，第二极连接所述驱动晶体管的第一极，栅极连接所述使能信号线；所述第一晶体管、第二晶体管为N型晶体管；所述驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管为P型晶体管。
本公开一种示例性实施例中，所述像素驱动电路还包括第六晶体管、第七晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第七晶体管的第一极连接所述第六晶体管的第二极，第二极连接第二初始信号线；所述第四导电层还包括所述第二初始信号线。
本公开一种示例性实施例中，在所述第一方向上分布的所有所述第二导电部依次连接以形成所述导电线，每条所述导电线连接每条所述电源线。
根据本公开的一个方面，提供一种显示装置，其中，该显示装置包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以 根据这些附图获得其他的附图。
图1为相关技术中像素驱动电路的电路结构示意图；
图2为图1所示的像素驱动电路一种驱动方法中各节点的时序图；
图3为本公开显示面板一种示例性实施例中的结构版图；
图4为图3中第二导电层的结构版图；
图5为图3中第五导电层的结构版图；
图6为本公开显示面板另一种示例性实施例的结构版图；
图7为本公开显示面板另一种示例性实施例的结构版图；
图8为本公开显示面板另一种示例性实施例的结构版图；
图9为本公开显示面板另一种示例性实施例中的结构版图；
图10为图9中遮光层的结构版图；
图11为图9中第一有源层的结构版图；
图12为图9中第一导电层的结构版图；
图13为图9中第二导电层的结构版图；
图14为图9中第二有源层的结构版图；
图15为图9中第三导电层的结构版图；
图16为图9中第四导电层的结构版图；
图17为图9中第五导电层的结构版图；
图18为图9中遮光层、第一有源层的结构版图；
图19为图9中遮光层、第一有源层、第一导电层的结构版图；
图20为图9中遮光层、第一有源层、第一导电层、第二导电层的结构版图；
图21为图9中遮光层、第一有源层、第一导电层、第二导电层、第二有源层的结构版图；
图22为图9中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层的结构版图；
图23为图9中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图；
图24为本公开显示面板的沿图9中的虚线AA剖开的部分剖视图；
图25为本公开显示面板又一种示例性实施例的结构版图；
图26为图25中第四导电层的结构版图；
图27为图25中第五导电层的结构版图；
图28为图25中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图；
图29为本公开显示面板另一种示例性实施例中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图；
图30为本公开显示面板另一种示例性实施例中遮光层的结构版图；
图31为本公开显示面板另一种示例性实施例中遮光层的结构版图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为相关技术中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：驱动晶体管T3、第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第一极，栅极连接第二栅极驱动信号端G2；第五晶体管T5的第一极连接第一电源端VDD，第二极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；驱动晶体管T3的栅极连接节点N；第二晶体管T2的第一极连接节点N，第二极连接驱动晶体管T3的第二极，栅极连接第一栅极驱动信号端G1；第六晶体管T6的第一极连接驱动晶体管T3的第二极，第二极连接第七晶体管T7的第一极，栅极连接使能信号端EM，第七晶体管T7的第二极连接第二初始信号端Vinit2，栅极连接第二复位信号端Re2；第一晶体管T1的第一极连接节点N，第二极连接第一初始信号端Vinit1，栅极连接第一复位信号端Re1；电容C的第一电极连接节点N，第二电极连接第一电源端VDD。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，第一晶体管T1和第二晶体管T2可以为N型晶体管，例如，第一晶体管T1和第二晶体管T2可以为N型金属氧化物晶体管，N 型金属氧化物晶体管具有较小的漏电流，从而可以避免发光阶段，节点N通过第一晶体管T1和第二晶体管T2漏电。同时，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型晶体管，例如，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型低温多晶体硅晶体管，P型低温多晶体硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。第一初始信号端和第二初始信号端可以根据实际情况输出相同或不同电压信号。
如图2所示，为图1中像素驱动电路一种驱动方法中各节点的时序图。其中，G1表示第一栅极驱动信号端G1的时序，G2表示第二栅极驱动信号端G2的时序，Re1表示第一复位信号端Re1的时序，Re2表示第二复位信号端Re2的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括第一复位阶段t1、补偿阶段t2，第二复位阶段t3、发光阶段t4。在第一复位阶段t1：第一复位信号端Re1输出高电平信号，第一晶体管T1导通，第一初始信号端Vinit1向节点N输入初始信号。在补偿阶段t2：第一栅极驱动信号端G1输出高电平信号，第二栅极驱动信号端G2输出低电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端Da输出驱动信号以向节点N写入电压Vdata+Vth(即电压Vdata与Vth之和)，其中Vdata为驱动信号的电压，Vth为驱动晶体管T3的阈值电压，在第二复位阶段t3，第二复位信号端Re2输出低电平信号，第七晶体管T7导通，第二初始信号端Vinit2向第六晶体管T6的第二极输入初始信号。发光阶段t4：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下发光。
驱动晶体管输出电流公式如下：
I＝(μWCox/2L)(Vgs-Vth) 2
其中，I为驱动晶体管输出电流；μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。
根据上述驱动晶体管输出电流公式，将本公开像素驱动电路中驱动晶体管的栅极电压Vdata+Vth和源极电压Vdd带入上述公式可以得到：本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
然而，在显示面板中，用于提供第一电源端的电源线自身存在压降，从而导致显示面板不同位置上的第一电源端存在压差，进而导致显示面板显示不均匀。
基于此，本示例性实施例提供一种显示面板，其中，所述显示面板可以包括沿第一方向和第二方向阵列分布的多个像素驱动电路，所述第一方向和所述第二方向相交，例如，第一方向可以为行方向，第二方向可以列方向。该显示面板中像素驱动电路的结构可以如图1所示。该显示面板还可以包括：衬底基板、第二导电层、第五导电层，如图3-5所示，图3为本公开显示面板一种示例性实施例中的结构版图，图4为图3中第二导电层的结构版图，图5为图3中第五导电层的结构版图。第二导电层可以位于所述衬底基板的一侧，所述第二导电层可以包括：多个第二导电部22，多个所述第二导电部22可以与多个所述像素驱动电路一一对应设置，所述第二导电部22可以用于形成与其对应的所述像素驱动电路中所述电容的第二电极，且在所述第一方向X上分布的多个所述第二导电部连接以形成导电线2；第五导电层可以位于所述第二导电层背离所述衬底基板的一侧，所述第五导电层可以包括：多条所述电源线VDD，多条所述电源线VDD在所述衬底基板上的正投影沿所述第一方向X间隔分布且沿所述第二方向Y延伸，每条导电线2可以与每条电源线VDD连接。
本示例性实施例中，多条电源线VDD和多条导电线2可以形成网格结构，网格结构的电源线具有较小的电阻，从而该显示面板可以提高显示面板的显示均一度。
本示例性实施例中，如图3、4所示，第二导电层还可以包括多个第一连接部21，第一连接部21连接于在第一方向上相邻的第二导电部22之间。在第一方向X上间隔分布的多个第二导电部22可以通过第一连接部连接以形成导电线2。应该理解的是，在其他示例性实施例中，第一连接部21也可以位于其他导电层。
本示例性实施例中，电源线VDD与导电线2可以通过过孔连接，如图3所示，该显示面板还可以包括第四导电层，第四导电层可以位于第二导电层和第五导电层之间，第四导电层可以包括多个第一桥接部41。其中，第一桥接部41可以通过过孔H连接第一连接部21，电源线VDD可以通过过孔H连接第一桥接部41，从而可以实现电源线VDD连接导电线2。需要说明的是，本示例性实施例中的黑色方块表示过孔，本示例性实施例仅对部分过孔的位置进行了标注。此外，在其他示例性实施例中，电源线VDD还可以通过过孔与第二导电部直接连接。
本示例性实施例中，每条导电线2可以与每条电源线VDD连接。应该理解的是，在其他示例性实施例中，导电线2还可以仅与部分电源线VDD连接。例如，如图6 所示，为本公开显示面板另一种示例性实施例的结构版图，其中，第一行导电线2与第二到第四列电源线VDD连接，第二行导电线2与第一到第三列电源线VDD连接，该显示面板同样可以降低电源线的压降。
本示例性实施例中，显示面板中在第一方向X上间隔分布的所有第二导电部22依次连接以形成导电线2。应该理解的是，在其他示例性实施例中，导电线2也可以仅由部分导电部22连接形成。例如，如图7所示，为本公开显示面板另一种示例性实施例的结构版图，其中，在第一方向X上每相邻两个导电部22连接以形成导电线2，该显示面板同样可以降低电源线的压降。再例如，如图8所示，为本公开显示面板另一种示例性实施例的结构版图。其中，每多个第二导电部22形成导电线2，该显示面板可以包括沿行列分布的多条导电线2，其中，相邻行且相邻列的导电线2在行方向上交错分布，即位于相邻行相邻列的两导电线2在衬底基板上的正投影在列方向移动所覆盖的区域部分相交。交错设置的导电线2可以共同连接至少两条电源线VDD。该显示面板同样可以降低电源线的压降。
本公开的显示面板还可以包括其他结构的像素驱动电路，只要该像素驱动电路的电容连接电源线，相应的显示面板均可以采用上述结构以降低电源线自身的压降。
需要说明的是，本示例性实施例中，一结构在衬底基板上的正投影沿某一方向延伸，可以理解为，该结构在衬底基板上的正投影整体沿该方向延伸，即该结构在衬底基板上的正投影可以沿该方向直线延伸或弯折延伸。同一结构膜层(例如，第二导电层、第五导电层)中的不同结构部可以通过一次构图工艺形成。结构层A位于结构层B背离衬底基板的一侧，可以理解为，结构层A在结构层B背离衬底基板的一侧形成。当结构层B为图案化结构时，结构层A的部分结构也可以位于结构层B的同一物理高度或低于结构层B的物理高度，其中，衬底基板为高度基准。
本示例性实施例还提供另一种显示面板，该显示面板可以包括依次层叠设置的衬底基板、遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层，其中上述层级之间可以设置有绝缘层。如图9-23所示，图9为本公开显示面板另一种示例性实施例中的结构版图，图10为图9中遮光层的结构版图，图11为图9中第一有源层的结构版图，图12为图9中第一导电层的结构版图，图13为图9中第二导电层的结构版图，图14为图9中第二有源层的结构版图，图15为图9中第三导电层的结构版图，图16为图9中第四导电层的结构版图，图17为图9中第五导电层的结构版图，图18为图9中遮光层、第一有源层的结构版图，图19 为图9中遮光层、第一有源层、第一导电层的结构版图，图20为图9中遮光层、第一有源层、第一导电层、第二导电层的结构版图，图21为图9中遮光层、第一有源层、第一导电层、第二导电层、第二有源层的结构版图，图22为图9中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层的结构版图，图23为图9中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图。该显示面板可以包括多个图1所示的像素驱动电路。如图9所示，多个像素驱动电路中可以包括在第一方向X上相邻分布第一像素驱动电路P1和第二像素驱动电路P2，第一像素驱动电路P1和第二像素驱动电路P2可以镜像对称设置。其中，第一像素驱动电路P1和第二像素驱动电路P2可以形成一重复单元，该显示面板可以包括在第一方向X和第二方向Y上阵列分布的多个重复单元。其中，第一方向X和第二方向Y可以相交，例如，第一方向可以为行方向，第二方向可以为列方向。
如图9、10、18所示，遮光层可以包括在第一方向X上分布的多个遮光部61、以及连接于遮光部61之间的第二连接部62。遮光层可以为导体结构，例如，遮光层可以为遮光金属层。
如图9、11、19所示，第一有源层可以包括第三有源部73、第四有源部74、第五有源部75、第六有源部76、第七有源部77、第八有源部78、第九有源部79。其中，第三有源部73可以用于形成驱动晶体管T3的沟道区；第四有源部74可以用于形成第四晶体管T4的沟道区；第五有源部75可以用于形成第五晶体管T5的沟道区；第六有源部76可以用于形成第六晶体管T6的沟道区；第七有源部77可以用于形成第七晶体管T7的沟道区；第八有源部78连接于第五有源部75远离第三有源部73的一侧，第九有源部79连接于第一像素驱动电路P1中第八有源部78和第二像素驱动电路P2中第八有源部78之间。其中，第八有源部78可以用于形成第五晶体管的第一极，本示例性实施例中，通过第九有源部79连接相邻两像素驱动电路中的第八有源部，从而可以降低该相邻像素驱动电路中第一电源端的电压差。如图18所示，遮光部61在衬底基板上的正投影可以覆盖第三有源部73在衬底基板上的正投影，遮光部61可以降低光照对驱动晶体管特性的影响。第一有源层可以由多晶硅材料形成，相应的，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图9、12、19所示，第一导电层可以包括：第一导电部11、第二栅线G2、使能信号线EM、第二复位信号线Re2。第二栅线G2可以用于提供图1中第二栅极驱动 信号端；使能信号线EM可以用于提供图1中的使能信号端；第二复位信号线Re2可以用于提供图1中的第二复位信号端。第二栅线G2在衬底基板上的正投影、使能信号线EM在衬底基板上的正投影、第二复位信号线Re2在衬底基板上的正投影均可以沿第一方向X延伸。其中，第二栅线G2在衬底基板上的正投影覆盖第四有源部74在衬底基板上的正投影，第二栅线G2的部分结构用于形成第四晶体管的栅极。使能信号线EM在衬底基板上的正投影覆盖第五有源部75在衬底基板上的正投影、第六有源部76在衬底基板上的正投影，使能信号线EM的部分结构可以分别用于形成第五晶体管T5、第六晶体管T6的栅极。第二复位信号线Re2在衬底基板上的正投影可以覆盖第七有源部77在衬底基板上的正投影，第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极。第一导电部11在衬底基板上的正投影覆盖第三有源部73在衬底基板上的正投影，第一导电部11可以用于形成驱动晶体管T3的栅极和电容的第一电极。第一方向X可以为行方向，如图19所示，本行像素驱动电路中的第二栅线G2可以复用为上一行像素驱动电路中的第二复位信号线Re2。该设置可以提高像素驱动电路的集成度，降低像素驱动电路的布图面积。遮光层可以连接一稳定电源端，例如，遮光层可以连接图1中的第一电源端、第一初始信号端、第二初始信号端等，遮光部61可以对第一导电部11起到稳压作用，从而降低驱动晶体管T3栅极在发光阶段的电压波动。此外，该显示面板可以利用第一导电层为掩膜对第一有源层进行导体化处理，即第一有源层中被第一导电层覆盖的区域可以形成晶体管的沟道区，未被第一导电层覆盖的区域形成导体结构。
如图9、13、20所示，第二导电层可以包括：第一初始信号线Vinit1、第三复位信号线2Re1、第三栅线2G1、多个第二导电部22。其中，第一初始信号线Vinit1用于提供图1中的第一初始信号端，第三复位信号线2Re1可以用于提供图1中的第一复位信号端，第三栅线2G1可以用于提供图1中的第一栅极驱动信号端。第一初始信号线Vinit1在衬底基板上的正投影、第三复位信号线2Re1在衬底基板上的正投影、第三栅线2G1在衬底基板上的正投影均可以沿第一方向X延伸。如图13所示，第二导电层还可以包括多个第一连接部，多个第一连接部中可以包括：连接于同一重复单元中两第二导电部22之间的第二子连接部212、连接于相邻重复单元中两第二导电部22之间的第一子连接部211。如图20所示，在同一组相邻的两所述像素驱动电路之间，第一子连接部211在衬底基板上的正投影可以与第二连接部62在衬底基板上的正投影至少部分重合，第二子连接部212在衬底基板上的正投影可以与第二连接部62在衬底 基板上的正投影至少部分重合。该设置可以降低第一连接部对显示面板的遮光影响，提供显示面板的透过率。其中，第一子连接部211在衬底基板上的正投影在第二方向Y上的尺寸可以小于第二导电部22在衬底基板上的正投影在第二方向Y上的尺寸，第一子连接部211在衬底基板上的正投影可以位于第二连接部62在衬底基板上的正投影上，该设置可以极大的提高显示面板的透过率。本示例性实施例中，第二子连接部212在衬底基板上的正投影在第二方向Y上的尺寸等于第二导电部22在衬底基板上的正投影在第二方向Y上的尺寸，以降低第二导电部22所形成的行方向延伸的导电条的自身电阻。应该理解的是，在其他示例性实施例中，第二子连接部212在衬底基板上的正投影在第二方向Y上的尺寸也可以小于第二导电部22在衬底基板上的正投影在第二方向Y上的尺寸。此外，在其他示例性实施例中，相邻重复单元中两第二导电部22之间也可以不设置第一子连接部211，即相邻重复单元中两第二导电部22在第一方向X上间隔设置。
如图9、14、21所示，第二有源层可以包括有源部81，有源部81可以包括第一有源部811、第二有源部812，第一有源部811可以用于形成第一晶体管的沟道区；第二有源部812可以用于形成第二晶体管T2的沟道区。其中，第二有源层可以由氧化铟镓锌形成，相应的，第一晶体管T1、第二晶体管T2可以为N型的金属氧化物薄膜晶体管。第三栅线2G1在衬底基板上的正投影可以覆盖第二有源部812在衬底基板上的正投影，第三栅线2G1的部分结构可以用于形成第二晶体管的底栅。第三复位信号线2Re1在衬底基板上的正投影可以覆盖第一有源部811在衬底基板上的正投影，第三复位信号线2Re1的部分结构可以用于形成第一晶体管T1的底栅。
如图9、15、22所示，第三导电层可以包括第一复位信号线3Re1、第一栅线3G1。第一复位信号线3Re1在衬底基板上的正投影、第一栅线3G1在衬底基板上的正投影均可以沿第一方向X延伸。第一复位信号线3Re1可以用于提供图1中的第一复位信号端，第一复位信号线3Re1在衬底基板上的正投影可以覆盖第一有源部811在衬底基板上的正投影，第一复位信号线3Re1的部分结构可以用于形成第一晶体管T1的顶栅，同时，第一复位信号线3Re1可以通过位于显示面板边沿走线区的过孔连接第三复位信号端2Re1。第一栅线3G1可以用于提供图1中的第一栅极驱动信号端，第一栅线3G1在衬底基板上的正投影可以覆盖第二有源部812在衬底基板上的正投影，第一栅线3G1的部分结构可以用于形成第二晶体管T2的顶栅，同时，第一栅线3G1可以通过位于显示面板边沿走线区的过孔连接第三栅线2G1。如图9、22所示，在同一像素驱动电 路中，第一导电部11在所述衬底基板上的正投影可以位于所述第一栅线3G1在所述衬底基板上的正投影和所述使能信号线EM在所述衬底基板上的正投影之间；第一复位信号线3Re1在所述衬底基板上的正投影可以位于第一栅线3G1在所述衬底基板上的正投影远离所述第一导电部11在所述衬底基板上的正投影的一侧。第二栅线G2在衬底基板上的正投影可以位于第一栅线3G1在所述衬底基板上的正投影和第一复位信号线3Re1在所述衬底基板上的正投影之间。第二复位信号线Re2在所述衬底基板上的正投影可以位于所述使能信号线EM在所述衬底基板上的正投影远离所述第一导电部11在所述衬底基板上的正投影的一侧。此外，该显示面板可以利用第三导电层为掩膜对第二有源层进行导体化处理，即第二有源层中被第三导电层覆盖的区域可以形成晶体管的沟道区，未被第三导电层覆盖的区域形成导体结构。
如图9、16、23所示，第四导电层可以包括第一桥接部41、第二桥接部42、第三桥接部43、第四桥接部44、第五桥接部45、第六桥接部46、第二初始信号线Vinit2。其中，第一桥接部41可以通过两个过孔连接第二子连接部212，且通过过孔分别连接第一像素驱动电路P1中的第八有源部78和第二像素驱动电路P2中的第八有源部78，以连接第五晶体管的第一极和电容C的第二电极。第一桥接部41可以以第一像素驱动电路P1和第二像素驱动电路P2的镜像对称面镜像对称。第二桥接部42可以通过过孔连接第六有源部76和第七有源部77之间的第一有源层，以连接第六晶体管T6的第二极和第七晶体管T7的第一极，第二桥接部42可以用于连接显示面板中发光单元的第一电极。第三桥接部43可以分别通过过孔连接第六有源部76和第三有源部73之间的第一有源层、第二有源部812远离第一有源部811一侧的第二有源层，以连接第二晶体管T2的第二极、第六晶体管T6的第一极、驱动晶体管T3的第二极。第四桥接部44可以分别通过过孔连接第一有源部811和第二有源部812之间的第二有源层、第一导电部11，以连接第二晶体管T2的第一极和驱动晶体管的栅极。如图13所示，第二导电部22上形成有开口221，连接于第一导电部11和第四桥接部44之间的过孔在衬底基板上的正投影位于开口221在衬底基板上的正投影以内，以使该过孔内的导电结构与第二导电部22相互绝缘。第五桥接部45可以分别通过过孔连接第一有源部811远离第二有源部812一侧的第二有源层、第一初始信号线Vinit1，以连接第一晶体管的第二极和第一初始信号端。第六桥接部46可以通过过孔连接第四有源部74远离第三有源部73一侧的第一有源层，以连接第四晶体管的第一极。第二初始信号线Vinit2可以用于提供图1中的第二初始信号端，第二初始信号线Vinit2可以通过过孔连接第 七有源部77远离第六有源部76一侧的第一有源层，以连接第七晶体管的第二极和第二初始信号端。
如图9、17所示，第五导电层可以包括多条电源线VDD、多条数据线Da、第七桥接部57。其中，电源线VDD在衬底基板上的正投影、数据线Da在衬底基板上的正投影均可以沿第二方向Y延伸。电源线VDD可以用于提供图1中的第一电源端，数据线Da可以用于提供图1中的数据信号端。如图9所示，每列像素驱动电路可以对应设置一条电源线，第一像素驱动电路P1中的电源线VDD可以通过过孔连接第一桥接部41，第二像素驱动电路P2中的电源线VDD可以通过过孔连接同一第一桥接部41，从而连接第五晶体管的第一极和第一电源端。数据线Da可以通过过孔连接第六桥接部46，以连接第四晶体管的第一极和数据信号端。其中，数据线Da仅示出了部分，可以理解，数据线Da在衬底基板上的正投影是沿第二方向Y延伸的。第七桥接部57可以通过过孔连接第二桥接部42，以连接第七晶体管的第一极，第七桥接部57可以用于连接发光单元的第一电极。应该理解的是，在其他示例性实施例中，多列像素驱动电路也可以对应设置一条电源线。如图17所示，电源线VDD可以包括第一延伸部VDD1、第二延伸部VDD2、第三延伸部VDD3，第二延伸部VDD2连接于第一延伸部VDD1和第三延伸部VDD3之间，第二延伸部VDD2在所述衬底基板上的正投影在所述第一方向X上的尺寸可以大于第一延伸部VDD1在所述衬底基板上的正投影在所述第一方向X上的尺寸，且所述第二延伸部VDD2在所述衬底基板上的正投影在所述第一方向X上的尺寸可以大于所述第三延伸部VDD3在所述衬底基板上的正投影在所述第一方向X上的尺寸。第二延伸部VDD2在衬底基板上的正投影可以覆盖第一有源部811在衬底基板上的正投影、第二有源部812在衬底基板上的正投影，第二延伸部VDD2可以降低光照对第一晶体管T1、第二晶体管T2的特性影响。
需要说明的是，如图9、23所示，画于第四导电层背离衬底基板一侧的黑色方块表示第四导电层连接面向衬底基板一侧的其他层级的过孔；画于第五导电层背离衬底基板一侧的黑色方块表示第五导电层连接面向衬底基板一侧的其他层级的过孔。该黑色方块仅表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层上。例如，连接于第一桥接部41和第二子连接部212之间的过孔可以贯穿位于第二导电层和第四导电层之间的绝缘层；连接于第一桥接部41和第八有源部78之间的过孔可以贯穿位于第一有源层和第四导电层之间的绝缘层；连接于第二有源部812远离第一有源部811一侧的第二有源层和第三桥接部43之间的过孔可以贯穿第四导电层和 第二有源层之间的绝缘层；连接于第四桥接部44和第一导电部11之间的过孔可以贯穿第四导电层和第一导电层之间的绝缘层；连接于电源线VDD和第一桥接部41之间的过孔可以贯穿第四导电层和第五导电层之间的绝缘层。此外，在以下实施例中，图中过孔的画法和表示的含义与本示例性实施例相同。
图24为显示面板的沿图9中虚线AA剖开的部分剖视图。如图24所示，该显示面板还可以包括第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95、第一介电层96、第二介电层97、钝化层98、平坦层99，其中，衬底基板90、遮光层、第一绝缘层91、第一有源层、第二绝缘层92、第一导电层、第三绝缘层93、第二导电层、第四绝缘层94、第二有源层、第五绝缘层95、第三导电层、第一介电层96、第二介电层97、第四导电层、钝化层98、平坦层99、第五导电层依次层叠设置。第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95可以为单层结构或多层结构，且第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95的材料可以为氮化硅，氧化硅，氮氧化硅中的至少一种；第一介电层96、第二介电层97、钝化层98可以为氮化硅层；平坦层99的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料。衬底基板90可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一导电层、第二导电层、第三导电层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第四导电层、第五导电层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。此外，在其他示例性实施例中，该显示面板中的第四导电层和第五导电层之间还可以仅设置平坦层，不设置钝化层。
如图25所示，为本公开显示面板另一种示例性实施例的结构版图，该显示面板可以包括多个图1所示的像素驱动电路，多个像素驱动电路包括在第一方向X上相邻分布第一像素驱动电路P1和第二像素驱动电路P2，第一像素驱动电路P1和第二像素驱动电路P2可以镜像对称设置。该显示面板同样可以包括依次层叠设置的衬底基板、遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层。
图25所示显示面板中的遮光层与图9所示显示面板中的遮光层版图结构相同，遮光层可以包括在第一方向X上分布的两个遮光部61、以及连接于遮光部61之间的第 二连接部62。遮光层可以为导体结构，例如，遮光层可以为遮光金属层。
图25所示显示面板中的第一有源层与图9所示显示面板中的第一有源层版图结构相同，第一有源层同样可以包括第三有源部73、第四有源部74、第五有源部75、第六有源部76、第七有源部77、第八有源部78、第九有源部79。
图25所示显示面板中的第一导电层与图9所示显示面板中的第一导电层版图结构相同，第一导电层同样可以包括：第一导电部11、第二栅线G2、使能信号线EM、第二复位信号线Re2。
图25所示显示面板中的第二导电层与图9所示显示面板中的第二导电层版图结构相同，第二导电层同样可以包括：第一初始信号线Vinit1、第三复位信号线2Re1、第三栅线2G1、多个第二导电部22。
图25所示显示面板中的第二有源层与图9所示显示面板中的第二有源层版图结构相同，第二有源层可以包括有源部81，有源部81可以包括第一有源部811、第二有源部812。
图25所示显示面板中的第三导电层与图9所示显示面板中的第三导电层版图结构相同，第三导电层同样可以包括第一复位信号线3Re1、第一栅线3G1。
图25所示显示面板与图9所示显示面板仅区别在于第四导电层和第五导电层的结构版图不同。如图26-28所示，图26为图25中第四导电层的结构版图，图27为图25中第五导电层的结构版图，图28为图25中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图。
如图25、26、28所示，第四导电层同样可以包括第一桥接部41、第二桥接部42、第三桥接部43、第四桥接部44、第五桥接部45、第六桥接部46、第二初始信号线Vinit2。其中，图26中的第一桥接部41与图16中第一桥接部41具有不同的版图结构。如图26所示，第一桥接部41可以形成有镂空部410，镂空部410所在区域至少部分可以形成显示面板的透光区。显示面板的透光区可以理解为，没有被任何具有遮光作用的结构覆盖的区域，即没有被在遮光层、第一导电层、第一有源层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层覆盖的区域。该设置可以提高显示面板的透过率。如图25、26、28所示，镂空部410在衬底基板上的正投影还可以与使能信号线EM在衬底基板上的正投影至少部分重合，该设置还可以降低使能信号线EM的寄生电容，提高使能信号线的充电速度，从而提高第五晶体管T5和第六晶体管T6的响应速度。
如图25、26、28所示，第一桥接部41可以包括：第一过孔接触部411、第二过孔接触部412、第三过孔接触部413、第四过孔接触部414、第五过孔接触部415。第一过孔接触部411可以通过过孔连接所述第二子连接部212；第二过孔接触部412与所述第一过孔接触部411在所述第二方向Y上相对设置，且通过过孔连接所述第一像素驱动电路P1中的第八有源部78；第三过孔接触部413与所述第一过孔接触部411在所述第二方向Y上相对设置，且通过过孔连接所述第二像素驱动电路P2中的第八有源部78；第四过孔接触部414连接于所述第一过孔接触部411和所述第二过孔接触部412之间，且通过过孔连接所述第一像素驱动电路P1中的电源线VDD；第五过孔接触部415连接于所述第一过孔接触部411和所述第三过孔接触部413之间，且通过过孔连接所述第二像素驱动电路P2中的电源线VDD，所述第五过孔接触部415与所述第四过孔接触部414在所述第一方向X上相对设置。其中，所述第一过孔接触部411、第二过孔接触部412、第三过孔接触部413、第四过孔接触部414、第五过孔接触部415可以环绕形成所述镂空部410。其中，结构A与结构B在第一方向X上相对设置，可以理解为，结构A在衬底基板上的正投影与结构B在衬底基板上的正投影在与第一方向X上间隔设置，且结构A在衬底基板上的正投影在第一方向X上无限移动所覆盖的区域与结构B在衬底基板上的正投影在第一方向X上无限移动所覆盖的区域至少部分重合。同理，结构A与结构B在第二方向Y上相对设置，可以理解为，结构A在衬底基板上的正投影与结构部B在衬底基板上的正投影在与第二方向Y上间隔设置，且结构A在衬底基板上的正投影在第二方向Y上无限移动所覆盖的区域与结构B在衬底基板上的正投影在第二方向Y上无限移动所覆盖的区域至少部分重合。
如图26所示，在第一方向X上，第一过孔接触部411在衬底基板上的正投影、第二过孔接触部412在衬底基板上的正投影、第三过孔接触部413在衬底基板上的正投影可以位于第四过孔接触部414在衬底基板上的正投影和第五过孔接触部415在衬底基板上的正投影之间；在第二方向Y上，第四过孔接触部414在衬底基板上的正投影、第五过孔接触部415在衬底基板上的正投影可以位于第一过孔接触部411在衬底基板上的正投影和第二过孔接触部412在衬底基板上的正投影之间；在第二方向Y上，第四过孔接触部414在衬底基板上的正投影、第五过孔接触部415在衬底基板上的正投影可以位于第一过孔接触部411在衬底基板上的正投影和第三过孔接触部413在衬底基板上的正投影之间。镂空部410可以为闭合开口也可以为非闭环开口，本示例性实施例中，镂空部410可以为非闭合开口，如图26所示，第二过孔接触部412和第三 过孔接触部413之间可以具有一定的间隙，应该理解的是，在其他示例性实施例中，第二过孔接触部412和第三过孔接触部413也可以直接连接，以形成闭合开口的镂空部410。
如图25、27所示，第五导电层同样可以包括电源线VDD、数据线Da、第七桥接部57。其中，图27所示第五导电层与图17所示第五导电层不同在于图27中的电源线VDD与图17中电源线VDD具有不同的版图结构。如图25、27所示，图25所示的显示面板中，所述第二延伸部VDD2上形成有缺口VDD0，缺口VDD0所在区域的至少部分可以形成所述显示面板的透光区域，该设置可以提高显示面板的透过率。其中，缺口VDD0可以形成于所述第二延伸部VDD2面向所述第四有源部74的侧边，且所述缺口VDD0在所述衬底基板上的正投影可以位于所述第二栅线G2在所述衬底基板上的正投影和所述第一复位信号线Vinit1在所述衬底基板上的正投影之间。应该理解的是，在其他示例性实施例中，缺口VDD0还可以形成于第二延伸部VDD2的其他位置。此外，该显示面板还可以通过在第二延伸部VDD2上形成镂空结构，以提高显示面板的透过率。本示例性实施例中，电源线VDD可以和在第一方向X横连的第二导电部形成网格结构，从而该显示面板上的电源线具有较小的自身电阻。在此基础上，本示例性实施例还可以适当减小电源线VDD的宽度以增加显示面板的透过率。例如，本示例性实施例可以适当减小第二延伸部VDD2在第一方向X上的尺寸。本示例性实施例中，第二延伸部VDD2在所述衬底基板上的正投影在所述第一方向X上的尺寸为L1，第二延伸部VDD2在所述衬底基板上的正投影在所述第二方向Y上的尺寸为L2，其中，L1/L2可以小于等于1/2，例如，L1/L2可以为1/2、1/3/、1/4等。
如图25所示，图25中沿虚线AA的部分剖视图可以与图24所示的剖视图相同。
如图29所示，为本公开显示面板另一种示例性实施例中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图。图29所示显示面板与图28所示显示面板不同的是，第一桥接部41上的镂空部410可以闭环图形；第一桥接部41连接第二子连接部212的两个过孔可以合二为一，且该合二为一的过孔可以以第一像素驱动电路和第二像素驱动电路的镜像对称面镜像对称；第一桥接部41分别连接第一像素驱动电路中第八有源部和第二像素驱动电路中第八有源部的两个过孔可以合二为一，该合二为一的过孔可以通过连接第九有源部79以连接第一像素驱动电路中第八有源部和第二像素驱动电路中第八有源部，且该合二为一的过孔可以以第一像素驱动电路和第二像素驱动电路的镜像对称面镜像对称。
如图30所示，为本公开显示面板另一种示例性实施例中遮光层的结构版图。在同一重复单元中，连接于第一方向X上相邻的两遮光部61之间的第二连接部62在衬底基板上的正投影在第二方向Y的尺寸可以为L1，遮光部61在衬底基板上正投影在第二方向Y上的尺寸可以为L2，L1可以大于等于80％*L2且小于等于L2，例如，L1可以等于80％*L2、90％*L2、L2等。该设置可以降低遮光层的压降。
如图31所示，为本公开显示面板另一种示例性实施例中遮光层的结构版图。图31与图30不同的是，第二连接部62上形成有镂空部621，其中，镂空部621可以为一个或多个。该设置可以降低遮光层对显示面板透过率的影响。
此外，需要说明的是，本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图。
本示例性实施例还提供一种显示装置，其中，包括上述的显示面板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (22)

  1. 一种显示面板，其中，所述显示面板包括沿第一方向和第二方向阵列分布的多个像素驱动电路，所述第一方向和所述第二方向相交，所述像素驱动电路包括驱动晶体管、电容，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接电源线，所述显示面板还包括：
    衬底基板；
    第二导电层，位于所述衬底基板的一侧，所述第二导电层包括：
    多个第二导电部，多个所述第二导电部与多个所述像素驱动电路一一对应设置，所述第二导电部用于形成与其对应的所述像素驱动电路中所述电容的第二电极，在所述第一方向上分布的至少两个相邻的所述第二导电部连接以形成导电线；
    第五导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第五导电层包括：
    多条所述电源线，多条所述电源线在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，至少一条所述导电线与多条所述电源线电连。
  2. 根据权利要求1所述的显示面板，其中，所述第二导电层还包括：
    多个第一连接部，所述第一连接部连接于在所述第一方向上相邻的两所述第二导电部之间，以形成所述导电线；
    所述显示面板还包括：
    第一有源层，位于所述衬底基板和所述第二导电层之间，所述第一有源层包括：
    多个第三有源部，与多个所述像素驱动电路一一对应设置，所述第三有源部用于形成与其对应的所述像素驱动电路中所述驱动晶体管的沟道区；
    遮光层，位于所述衬底基板和所述第一有源层之间，所述遮光层包括：
    多个遮光部，与多个所述像素驱动电路一一对应设置，所述遮光部在所述衬底基板上的正投影覆盖与其对应的所述像素驱动电路中所述第三有源部在所述衬底基板上的正投影；
    多个第二连接部，所述第二连接部连接于在所述第一方向上相邻的两所述遮光部之间，且所述第二连接部在所述衬底基板上的正投影在所述第二方向上的尺寸小于所述遮光部在所述衬底基板上的正投影在所述第二方向上的尺寸；
    其中，在同一组相邻的两所述像素驱动电路之间，所述第二连接部在所述衬底基板上的正投影和所述第一连接部在所述衬底基板上的正投影至少部分重合。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板包括沿所述第一方向和第二方向分布的多个重复单元，每个所述重复单元包括两个所述像素驱动电路，两个所述像素驱动电路包括沿所述第一方向分布的第一像素驱动电路和第二像素驱动电路，所述第一像素驱动电路和所述第二像素驱动电路镜像对称设置；
    多个所述第一连接部中包括：
    第一子连接部，连接于在所述第一方向上相邻的所述重复单元中两所述第二导电部之间，所述第一子连接部在所述衬底基板上的正投影在所述第二方向上的尺寸小于所述第二导电部在所述衬底基板上的正投影在所述第二方向上的尺寸。
  4. 根据权利要求3所述的显示面板，其中，在同一组相邻的两所述像素驱动电路之间，所述第一子连接部在所述衬底基板上的正投影位于所述第二连接部在所述衬底基板上的正投影上。
  5. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括第一晶体管、第二晶体管，所述第一晶体管的第一极连接所述驱动晶体管的栅极，所述第一晶体管的第二极连接第一初始信号线，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极，所述显示面板还包括：
    第二有源层，位于所述第二导电层和所述第五导电层之间，所述第二有源层包括：
    第一有源部，用于形成所述第一晶体管的沟道区；
    第二有源部，与所述第一有源部连接，用于形成所述第二晶体管的沟道区；
    所述电源线包括第二延伸部；
    所述第二延伸部在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影、所述第二有源部在所述衬底基板上的正投影。
  6. 根据权利要求5所述的显示面板，其中，所述电源线还包括：第一延伸部、第三延伸部，所述第二延伸部连接于所述第一延伸部和所述第三延伸部之间；
    所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸大于第一延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸，且所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第三延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸；
    所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸为L1，所述第二延伸部在所述衬底基板上的正投影在所述第二方向上的尺寸为L2，其中，L1/L2小于等于1/2。
  7. 根据权利要求5所述的显示面板，其中，所述第二延伸部上形成有缺口或者镂空结构。
  8. 根据权利要求7所述的显示面板，其中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极，所述显示面板还包括：
    第一有源层，位于所述衬底基板和所述第二导电层之间，所述第一有源层包括第四有源部，所述第四有源部用于形成所述第四晶体管的沟道区；
    第一导电层，位于所述第一有源层和所述第二导电层之间，所述第一导电层包括第二栅线，所述第二栅线在所述衬底基板上的正投影覆盖所述第四有源部在所述衬底基板上的正投影，且沿所述第一方向延伸，所述第二栅线的部分结构用于形成所述第四晶体管的栅极；
    第三导电层，位于所述第二有源层和第五导电层之间，所述第三导电层包括第一复位信号线，所述第一复位信号线在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极；
    所述缺口形成于所述第二延伸部面向所述第四有源部的侧边，且所述缺口在所述衬底基板上的正投影位于所述第二栅线在所述衬底基板上的正投影和所述第一复位信号线在所述衬底基板上的正投影之间。
  9. 根据权利要求3所述的显示面板，其中，多个所述第一连接部中还包括：
    第二子连接部，所述第二子连接部连接于同一所述重复单元中的两所述第二导电部之间；
    所述像素驱动电路还包括第五晶体管，所述第五晶体管的第一极连接所述电源线，所述第五晶体管的第二极连接所述驱动晶体管的第一极；
    所述第一有源层包括：
    第五有源部，用于形成所述第五晶体管的沟道区；
    第八有源部，连接于所述第五有源部远离所述第三有源部的一侧；
    所述显示面板还包括：
    第一导电层，位于所述第一有源层和所述第二导电层之间，所述第一导电层包括：
    使能信号线，所述使能信号线在所述衬底基板上的正投影沿所述第一方向延伸，且覆盖所述第五有源部在所述衬底基板上的正投影，所述使能信号线的部分结构用于 形成所述第五晶体管的栅极；
    第四导电层，位于所述第二导电层和所述第五导电层之间，所述第四导电层包括：
    第一桥接部，所述第一桥接部分别通过过孔连接所述第一像素驱动电路中的第八有源部、所述第二像素驱动电路中的第八有源部、所述第一像素驱动电路和所述第二像素驱动电路之间的第二子连接部，且所述第一桥接部通过过孔连接所述电源线。
  10. 根据权利要求9所述的显示面板，其中，所述第一桥接部上形成有镂空部。
  11. 根据权利要求10所述的显示面板，其中，所述镂空部在所述衬底基板上的正投影与所述使能信号线在所述衬底基板上的正投影至少部分重合。
  12. 根据权利要求10所述的显示面板，其中，所述第二方向为列方向，每列所述像素驱动电路对应设置一条所述电源线，所述第一像素驱动电路中的电源线和所述第二像素驱动电路中的电源线分别通过过孔连接所述第一桥接部；
    所述第一桥接部包括：
    第一过孔接触部，通过过孔连接所述第二子连接部；
    第二过孔接触部，与所述第一过孔接触部在所述第二方向上相对设置，且通过过孔连接所述第一像素驱动电路中的第八有源部；
    第三过孔接触部，与所述第一过孔接触部在所述第二方向上相对设置，且通过过孔连接所述第二像素驱动电路中的第八有源部；
    第四过孔接触部，连接于所述第一过孔接触部和所述第二过孔接触部之间，且通过过孔连接所述第一像素驱动电路中的电源线；
    第五过孔接触部，连接于所述第一过孔接触部和所述第三过孔接触部之间，且通过过孔连接所述第二像素驱动电路中的电源线，所述第五过孔接触部与所述第四过孔接触部在所述第一方向上相对设置；
    其中，所述第一过孔接触部、第二过孔接触部、第三过孔接触部、第四过孔接触部、第五过孔接触部环绕形成所述镂空部。
  13. 根据权利要求9所述的显示面板，其中，所述第一有源层还包括：
    多个第九有源部，与多个所述重复单元一一对应设置，在同一重复单元中，所述第九有源部连接于所述第一像素驱动电路中的第八有源部和所述第二像素驱动电路中的第八有源部之间。
  14. 根据权利要求9所述的显示面板，其中，所述第一桥接部以所述第一像素驱动电路和所述第二像素驱动电路的镜像对称面镜像对称。
  15. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括第四晶体管、第六晶体管、第七晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第七晶体管的第一极连接所述第六晶体管的第二极，所述第七晶体管的第二极连接第二初始信号线；
    所述显示面板还包括：
    第一有源层，位于所述衬底基板和所述第二导电层之间，所述第一有源层包括：
    第三有源部，用于形成所述驱动晶体管的沟道区；
    第四有源部，连接于所述第三有源部的一侧，用于形成所述第四晶体管的沟道区；
    第六有源部，连接于所述第三有源部远离所述第四有源部的一侧，用于形成所述第六晶体管的沟道区；
    第七有源部，连接于所述第六有源部远离所述第三有源部的一侧，用于形成所述第七晶体管的沟道区；
    第一导电层，位于所述第一有源层和所述第二导电层之间，所述第一导电层包括：
    第二栅线，在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第四有源部在所述衬底基板上的正投影，所述第二栅线的部分结构用于形成所述第四晶体管的栅极；
    使能信号线，在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第六有源部在所述衬底基板上的正投影，所述使能信号线的部分结构用于形成所述第六晶体管的栅极；
    第二复位信号线，在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第七有源部在所述衬底基板上的正投影，所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极；
    第一导电部，在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极和所述电容的第二电极；
    其中，在同一所述像素驱动电路中，所述第一导电部在所述衬底基板上的正投影位于所述第二栅线在所述衬底基板上的正投影和所述使能信号线在所述衬底基板上的正投影之间；
    所述第二复位信号线在所述衬底基板上的正投影位于所述使能信号线在所述衬 底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧。
  16. 根据权利要求15所述的显示面板，其中，所述第一方向为行方向，本行像素驱动电路中的第二栅线复用为上一行像素驱动电路中的第二复位信号线。
  17. 根据权利要求15所述的显示面板，其中，所述像素驱动电路还包括第一晶体管、第二晶体管，所述第一晶体管的第一极连接所述驱动晶体管的栅极，所述第一晶体管的第二极连接第一初始信号线，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极，所述显示面板还包括：
    第二有源层，位于所述第二导电层和所述第五导电层之间，所述第二有源层包括：
    第一有源部，用于形成所述第一晶体管的沟道区；
    第二有源部，连接所述第一有源部，用于形成所述第二晶体管的沟道区；
    第三导电层，位于所述第二有源层和所述第五导电层之间，所述第三导电层包括：
    第一复位信号线，在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的顶栅；
    第一栅线，在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第一栅线的部分结构用于形成所述第二晶体管的顶栅；
    在同一所述像素驱动电路中，所述第一栅线在所述衬底基板上的正投影位于所述第一导电部在所述衬底基板上的正投影和所述第二栅线在所述衬底基板上的正投影之间，所述第一复位信号线在所述衬底基板上的正投影位于所述第二栅线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧。
  18. 根据权利要求17所述的显示面板，其中，所述第二导电层还包括：
    所述第一初始信号线，在所述衬底基板上的正投影位于所述第一复位信号线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧；
    第三复位信号线，通过过孔连接所述第一复位信号线，在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第三复位信号线的部分结构用于形成所述第一晶体管的底栅；
    第三栅线，在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第三栅线的部分结构用于形成所述第二晶体管的底栅。
  19. 根据权利要求17所述的显示面板，其中，所述像素驱动电路还包括第五晶体管，所述第五晶体管的第一极连接所述电源线，所述第五晶体管的第二极连接所述 驱动晶体管的第一极，栅极连接所述使能信号线；
    所述第一晶体管、第二晶体管为N型晶体管；所述驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管为P型晶体管。
  20. 根据权利要求9所述的显示面板，其中，所述像素驱动电路还包括第六晶体管、第七晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第七晶体管的第一极连接所述第六晶体管的第二极，所述第七晶体管的第二极连接第二初始信号线；
    所述第四导电层还包括所述第二初始信号线。
  21. 根据权利要求1所述的显示面板，其中，在所述第一方向上分布的所有所述第二导电部依次连接以形成所述导电线，每条所述导电线连接每条所述电源线。
  22. 一种显示装置，其中，包括权利要求1-21任一项所述的显示面板。
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