WO2023047228A1 - 電子装置および表示システム - Google Patents
電子装置および表示システム Download PDFInfo
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- WO2023047228A1 WO2023047228A1 PCT/IB2022/058439 IB2022058439W WO2023047228A1 WO 2023047228 A1 WO2023047228 A1 WO 2023047228A1 IB 2022058439 W IB2022058439 W IB 2022058439W WO 2023047228 A1 WO2023047228 A1 WO 2023047228A1
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- circuit
- transistor
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- insulator
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- This specification describes an electronic device, a display system including the electronic device, and a semiconductor device included in the electronic device.
- one aspect of the present invention is not limited to the above technical field.
- Technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input/output devices, and driving methods thereof. , or methods for producing them, can be mentioned as an example.
- a wrist-mounted electronic device may have a configuration including a display, various sensors, a CPU for controlling the various sensors, a memory for storing data, and the like (see, for example, Patent Document 1). .
- SoC System on Chip
- GPU Graphics Processing Unit
- An object of one embodiment of the present invention is to provide a novel electronic device, display system, and the like.
- one embodiment of the present invention is to provide an electronic device, a display system, or the like having a novel configuration in which an increase in heat generation and power consumption can be suppressed in an electronic device including a semiconductor device whose performance is improved by SoC. Make it one of the issues.
- an object of one embodiment of the present invention is to provide an electronic device or the like and a display system with a novel structure in which the number of data transfers in a CPU can be reduced.
- one embodiment of the present invention provides an electronic device, a display system, or the like with a novel configuration that achieves both high performance of a semiconductor device and low power consumption or suppression of heat generation of the semiconductor device.
- One aspect of the present invention is an electronic device including a semiconductor device, wherein the semiconductor device includes a CPU, an accelerator, and a memory device, and the CPU electrically connects a scan flip-flop circuit and a scan flip-flop circuit.
- a backup circuit connected thereto, the backup circuit having a first transistor, the accelerator having an arithmetic circuit and a data holding circuit electrically connected to the arithmetic circuit, the data holding circuit , a second transistor, a memory device having a memory cell having a third transistor, the first to third transistors having a semiconductor layer having a metal oxide in a channel formation region;
- An electronic device is an electronic device.
- One aspect of the present invention is an electronic device including a semiconductor device, wherein the semiconductor device includes a CPU, an accelerator, and a memory device, and the CPU electrically connects a scan flip-flop circuit and a scan flip-flop circuit.
- a backup circuit connected thereto, the backup circuit having a first transistor, the layer provided with the backup circuit being stacked with the layer provided with the scan flip-flop circuit, and the accelerator performing the operation and a data holding circuit electrically connected to the arithmetic circuit, the data holding circuit having a second transistor, and the layer provided with the data holding circuit being stacked with the layer provided with the arithmetic circuit.
- the memory device is an electronic device including a memory cell having a third transistor, and the first to third transistors each including a semiconductor layer including metal oxide in a channel formation region.
- the backup circuit is preferably an electronic device that has a function of holding data held in the scan flip-flop circuit while the supply of power supply voltage is stopped when the CPU is not operating.
- the data holding circuit is preferably an electronic device having a function of holding data held in the data holding circuit while the supply of power supply voltage is stopped when the accelerator is not in operation.
- the scan flip-flop circuit and the arithmetic circuit are preferably electronic devices each including a transistor having a semiconductor layer containing silicon in a channel formation region.
- the memory device is preferably an electronic device in which a peripheral circuit that controls memory cells is provided, and a layer provided with the peripheral circuit is stacked with a layer provided with the memory cell.
- the arithmetic circuit is preferably a semiconductor device that performs sum-of-products operation.
- the semiconductor device preferably contains In, Ga, and Zn as the metal oxide.
- One aspect of the present invention includes a first electronic device and a second electronic device, wherein the first electronic device includes a first display section, first wireless communication means, and a first a sensor, the second electronic device has a second display, a second wireless communication means, and a second sensor; the first wireless communication means; A first electronic device and a second electronic device are connected by interlocking a wireless communication means, and based on any one or more information input to the first sensor and the second sensor 2, based on the function of displaying one or more of augmented reality, virtual reality, alternative reality, or mixed reality on the second display unit, and information input to the first sensor, the second and a function of manipulating an image on a display unit.
- the first electronic device is preferably a display system, which is the electronic device of one aspect of the present invention.
- One aspect of the present invention can provide a novel electronic device, display system, and the like.
- one embodiment of the present invention can provide an electronic device, a display system, or the like with a novel configuration in which an increase in heat generation and power consumption can be suppressed in an electronic device including a semiconductor device whose performance is improved by SoC. can.
- one embodiment of the present invention can provide an electronic device, a display system, or the like with a novel structure in which the number of data transfers in a CPU can be reduced.
- one embodiment of the present invention provides an electronic device, a display system, or the like with a novel configuration that achieves both high performance of a semiconductor device and low power consumption or suppression of heat generation of the semiconductor device. can do.
- one embodiment of the present invention can provide an electronic device, a display system, or the like with a novel configuration that is highly convenient.
- FIGS. 1A and 1B are diagrams for explaining a configuration example of an electronic device.
- 2A and 2B are diagrams for explaining a configuration example of an electronic device.
- FIG. 3 is a diagram illustrating a configuration example of an electronic device.
- 4A and 4B are diagrams for explaining a configuration example of an electronic device.
- FIG. 5 is a diagram illustrating a configuration example of an electronic device.
- 6A and 6B are diagrams for explaining a configuration example of an electronic device.
- 7A and 7B are diagrams for explaining a configuration example of an electronic device.
- 8A and 8B are diagrams for explaining a configuration example of an electronic device.
- 9A and 9B are diagrams for explaining a configuration example of an electronic device.
- 10A and 10B are diagrams for explaining a configuration example of an electronic device.
- FIG. 11A to 11F are diagrams illustrating configuration examples of electronic devices.
- FIG. 12 is a diagram illustrating a configuration example of an electronic device.
- 13A and 13B are diagrams for explaining a configuration example of an electronic device.
- 14A to 14C are diagrams illustrating configuration examples of electronic devices.
- 15A and 15B are diagrams for explaining a configuration example of an electronic device.
- FIG. 16 is a diagram illustrating a configuration example of an electronic device.
- 17A to 17C are diagrams illustrating configuration examples of electronic devices.
- FIG. 18 is a diagram illustrating a configuration example of an electronic device.
- 19A and 19B are diagrams for explaining a configuration example of an electronic device.
- 20A and 20B are diagrams showing configuration examples of a display device and a display system.
- 21A and 21B are diagrams showing configuration examples of a display device and a display system.
- 22A to 22D are diagrams showing examples of images of a display device and a display system.
- FIG. 23 is a diagram illustrating an example of how the display system operates.
- 24A to 24D are diagrams showing examples of images of a display device and a display system.
- FIG. 25 is a diagram illustrating an example of how the display system operates.
- 26A and 26B are diagrams for explaining a configuration example of a display device.
- FIG. 27 is a diagram illustrating a configuration example of a display device.
- FIG. 28 is a diagram illustrating an operation example of the electronic device.
- 29A and 29B are schematic diagrams illustrating a configuration example of an electronic device.
- 30A and 30B are schematic diagrams for explaining a configuration example of an electronic device.
- 31A and 31B are schematic diagrams illustrating configuration examples of electronic devices.
- 32A and 32B are diagrams for explaining a configuration example of a display device.
- 33A and 33B are diagrams for explaining a configuration example of a display device.
- 34A and 34C are diagrams for explaining a configuration example of a display device.
- 35A and 35C are diagrams for explaining a configuration example of a display device.
- 36A and 36B are diagrams illustrating configuration examples of display devices.
- FIG. 37 is a diagram illustrating a configuration example of a display device.
- FIG. 38 is a diagram illustrating a configuration example of a display device.
- FIG. 39 is a diagram illustrating a configuration example of a display device.
- FIG. 37 is a diagram illustrating a configuration example of a display device.
- FIG. 38 is a diagram illustrating a configuration example of a display device.
- FIG. 40 is a diagram illustrating a configuration example of a display device.
- FIG. 41 is a diagram illustrating a configuration example of a display device.
- FIG. 42 is a diagram illustrating a configuration example of a display device.
- FIG. 43 is a diagram illustrating a configuration example of a display device.
- 44A to 44E are diagrams illustrating configuration examples of electronic devices.
- the ordinal numbers “first”, “second”, and “third” are added to avoid confusion of constituent elements. Therefore, the number of components is not limited. Also, the order of the components is not limited. Also, for example, the component referred to as “first” in one of the embodiments of this specification etc. is the component referred to as “second” in another embodiment or the scope of claims It is possible. Further, for example, the component referred to as “first” in one of the embodiments of this specification etc. may be omitted in other embodiments or the scope of claims.
- the power supply potential VDD may be abbreviated as potential VDD, VDD, or the like. This also applies to other components (eg, signals, voltages, circuits, elements, electrodes, wiring, etc.).
- the code is used for identification such as "_1”, “_2”, “[n]", and “[m,n]”. may be described with the sign of .
- the second wiring GL is described as wiring GL[2].
- FIG. 1A is a block diagram illustrating an electronic device according to one embodiment of the present invention.
- the electronic device 100 shown in FIG. 1A includes a semiconductor device 101 as well as a display 102, a main memory 103, a battery 104, and a sensor 105 as an example.
- FIG. 1B shows an example of a perspective view of the electronic device 100 corresponding to the block diagram of the electronic device 100 shown in FIG. 1A.
- the electronic device shown in FIG. 1B is a wristwatch type electronic device, and in addition to the semiconductor device 101, a display 102, a main memory 103, a battery 104, and sensors are contained in a housing 111 to which an operation unit 112 and a band 113 are attached.
- the configuration in which 105 is housed is shown.
- the electronic device 100 shown in FIG. 1B has a function as a so-called smart watch.
- the semiconductor device 101 includes a CPU 10, an accelerator 20, a memory device 30, a DMAC (Direct Memory Access Controller) 41, a power management unit (PMU) 42, a power supply circuit 60, a memory controller 43, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory). ) controller 44, USB (Universal Serial Bus) interface circuit 45, display interface circuit 46, bridge circuit 50, interrupt control circuit 51, interface circuit 52, battery control circuit 53, and ADC (Analog-to-digital converter)/DAC ( (digital-to-analog converter) interface circuit 54 .
- the semiconductor device 101 may include a module (also referred to as a communication module) having a function of communicating with the outside.
- the communication module may be provided with, for example, a high frequency circuit (RF circuit) to transmit and receive RF signals.
- a high-frequency circuit is a circuit that mutually converts an electromagnetic signal and an electric signal in the frequency band specified by the laws and regulations of each country, and uses the electromagnetic signal to wirelessly communicate with other communication devices. Several tens of kHz to several tens of GHz are generally used as a practical frequency band.
- the high-frequency circuit connected to the antenna has a high-frequency circuit section corresponding to a plurality of frequency bands, and the high-frequency circuit section may be configured to have an amplifier (amplifier), a mixer, a filter, a DSP, an RF transceiver, etc. can.
- LTE Long Term Evolution
- 5G 5th generation mobile communication system
- 6th generation Communication standards stipulated by 3GPP (Third Generation Partnership Project) (registered trademark), such as standards corresponding to the next generation mobile communication system (6G), or IEEE (registered trademark) such as Wi-Fi (registered trademark) and Bluetooth (registered trademark)
- 6G next generation mobile communication system
- 6G next generation mobile communication system
- IEEE registered trademark
- Wi-Fi registered trademark
- Bluetooth registered trademark
- the semiconductor device 101 may have another circuit, such as a security circuit.
- the security circuit is a circuit for enhancing confidentiality of signals, such as transmitting and receiving encrypted signals between the semiconductor device 101 and an external circuit.
- the CPU 10 has, for example, a CPU core 11, an L1 cache memory device 12, an L2 cache memory device 13, and a bus interface section 14.
- L1 cache memory device 12 is sometimes referred to as an instruction cache.
- the L2 cache memory device 13 may be called a data cache.
- the CPU core 11 has multiple CPU cores.
- the CPU core has a backup circuit 10M electrically connected to the scan flip-flop circuit.
- the L1 cache memory device 12 has a function of temporarily storing instructions to be executed by the CPU core 11 .
- the L2 cache memory device 13 has a function of temporarily storing data processed by the CPU core 11 or data obtained by the processing.
- the bus interface unit 14 may have a circuit configuration capable of transmitting/receiving signals such as data and addresses to/from a bus for connecting the CPU 10 and other circuits in the semiconductor device 101 .
- the scan flip-flop circuit in the CPU 10 is composed of a circuit having a transistor (Si transistor) having a semiconductor layer containing silicon in the channel forming region, that is, a Si CMOS.
- the backup circuit 10M has a transistor (OS transistor) having a semiconductor layer containing a metal oxide in a channel formation region.
- the backup circuit 10M including the OS transistor can function as an OS memory having a function of holding charge for a long time by turning off the OS transistor.
- the OS transistor Since the bandgap of metal oxide is 2.5 eV or more, the OS transistor has a very small off current.
- the off-state current per 1 ⁇ m of channel width is less than 1 ⁇ 10 ⁇ 20 A, less than 1 ⁇ 10 ⁇ 22 A, or 1 ⁇ 10 A at a voltage between the source and the drain of 3.5 V and at room temperature (25° C.). less than -24 A. That is, the ON/OFF current ratio of the drain current can be set to 20 digits or more and 150 digits or less. Therefore, the OS memory has an extremely small amount of charge leaked from the retention node via the OS transistor. Therefore, since the OS memory can function as a non-volatile memory circuit, power gating of the CPU 10 is possible.
- High-density integrated semiconductor devices may generate heat due to circuit driving.
- the heat generation raises the temperature of the transistor, which may change the characteristics of the transistor, resulting in a change in field-effect mobility, a decrease in operating frequency, or the like.
- the OS transistor has higher heat resistance than the Si transistor, the field-effect mobility is less likely to change due to temperature changes, and the operating frequency is less likely to decrease.
- the OS transistor tends to maintain the characteristic that the drain current increases exponentially with respect to the gate-source voltage even when the temperature rises. Therefore, with the use of the OS transistor, stable operation can be performed in a high temperature environment.
- Metal oxides applied to OS transistors include Zn oxide, Zn—Sn oxide, Ga—Sn oxide, In—Ga oxide, In—Zn oxide, and In—M—Zn oxide (M is , Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf).
- M is , Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf.
- the transistor can have excellent electrical characteristics such as field-effect mobility by adjusting the ratio of the elements, which is preferable.
- oxides containing indium and zinc include aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. , magnesium, etc., or a plurality of kinds thereof may be contained.
- the metal oxide applied to the semiconductor layer is preferably a metal oxide having a crystal part, such as CAAC-OS, CAC-OS, and nc-OS.
- CAAC-OS is an abbreviation for c-axis-aligned crystal oxide semiconductor.
- CAC-OS is an abbreviation for Cloud-Aligned Composite Oxide Semiconductor.
- nc-OS is an abbreviation for nanocrystalline oxide semiconductor.
- CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the a-b plane direction.
- the strain refers to a portion where the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of nanocrystals are connected.
- a CAC-OS has a function of allowing electrons (or holes), which are carriers, to flow, and a function of not allowing electrons, which are carriers, to flow. By separating the function of allowing electrons to flow from the function of not allowing electrons to flow, both functions can be maximized. That is, by using the CAC-OS for the channel formation region of the OS transistor, both high on-current and extremely low off-current can be achieved.
- Metal oxides have a large bandgap, which makes it difficult for electrons to be excited, and the effective mass of holes is large. Therefore, in OS transistors, avalanche decay and the like are less likely to occur than in general Si transistors. . Therefore, it is possible to suppress hot carrier deterioration caused by, for example, avalanche collapse. Since hot carrier deterioration can be suppressed, the OS transistor can be driven with a high drain voltage.
- An OS transistor is a storage transistor that uses electrons as majority carriers. Therefore, the influence of DIBL (Drain-Induced Barrier Lowering), which is one of the short-channel effects, is small compared to an inversion-type transistor (typically, a Si transistor) having a pn junction. That is, the OS transistor has higher resistance to the short channel effect than the Si transistor.
- DIBL Drain-Induced Barrier Lowering
- the OS transistor Since the OS transistor has high resistance to the short-channel effect, the channel length can be reduced without deteriorating the reliability of the OS transistor, so the use of the OS transistor can increase the degree of integration of the circuit.
- the drain electric field increases as the channel length becomes finer, as described above, an avalanche collapse is less likely to occur in an OS transistor than in a Si transistor.
- the OS transistor since the OS transistor has high resistance to the short channel effect, it is possible to make the gate insulating film thicker than the Si transistor. For example, even in a minute transistor with a channel length and a channel width of 50 nm or less, a gate insulating film as thick as about 10 nm can be provided in some cases. By thickening the gate insulating film, the parasitic capacitance can be reduced, so that the operating speed of the circuit can be improved. Also, by thickening the gate insulating film, leakage current through the gate insulating film is reduced, which leads to reduction in static current consumption.
- the CPU 10 can retain data even when the supply of power supply voltage is stopped by having the backup circuit 10M, which is an OS memory. Therefore, power gating of the CPU 10 becomes possible, and a significant reduction in power consumption can be achieved.
- the backup circuit 10M which is an OS memory, can be stacked with a circuit such as a scan flip-flop circuit that is composed of Si transistors that the CPU core 11 has. Therefore, it can be arranged without increasing the circuit area.
- the accelerator 20 has a memory circuit 21, an arithmetic circuit 22, and a control circuit 23.
- the accelerator 20 has a function of executing a program (also called kernel or kernel program) called by the host program.
- the accelerator 20 can perform, for example, parallel processing of matrix calculations in graphics processing, parallel processing of product-sum calculations in neural networks, parallel processing of floating-point calculations in scientific and technical calculations, and the like. Therefore, the performance of the semiconductor device 101 can be improved as compared with the configuration of only the CPU 10 .
- the memory circuit 21 has a plurality of data holding circuits 20M.
- the data holding circuit 20M can have a circuit configuration of NOSRAM.
- NOSRAM registered trademark
- a NOSRAM is a memory whose memory cells are two-transistor (2T) or three-transistor (3T) gain cells and whose access transistors are OS transistors. The current flowing between the source and the drain of the OS transistor in the off state, that is, the leak current is extremely small.
- the NOSRAM can be used as a non-volatile memory by retaining electric charge corresponding to data in the data retention circuit 20M using the characteristic of extremely small leakage current.
- NOSRAM can read data without destroying it (non-destructive reading), it is suitable for parallel processing of sum-of-products operations in neural networks that repeat only data reading operations in large numbers.
- the arithmetic circuit 22 has a function of performing arithmetic processing using digital values. Digital values are less susceptible to noise. Therefore, the accelerator 20 is suitable for performing arithmetic processing that requires highly accurate arithmetic results.
- the arithmetic circuit 22 is preferably composed of a Si CMOS, that is, a transistor (Si transistor) having silicon in a channel formation region. With this structure, the data holding circuit 20M including the OS transistor can be stacked.
- the control circuit 23 is a circuit configuration for controlling each circuit such as a drive circuit within the accelerator 20 .
- the arithmetic circuit 22 may be configured to perform arithmetic processing using analog values.
- the data holding circuit 20M can hold charges according to analog values. With this structure, arithmetic processing using an analog signal output from the data holding circuit 20M including the OS transistor can be performed.
- analog values can be continuously held as data, and can be configured to output to the CPU 10 the calculation results obtained by calculation in the arithmetic circuit. Since the data can be held continuously, the frequency of data transfer for arithmetic processing can be reduced. Moreover, since the amount of arithmetic processing of the CPU 10 can be reduced, the frequency of data transfer between the memory device 30 and the CPU 10 can also be reduced. That is, with the configuration of one embodiment of the present invention, the number of accesses via the bus 40A and the amount of data to be transferred can be reduced.
- the memory device 30 functions as an on-chip memory.
- the on-chip memory is a memory device for storing data or programs to be input/output to/from a circuit included in the semiconductor device 101 , such as the CPU 10 or the accelerator 20 .
- the memory device 30 has a function of storing data or programs to be input/output to/from a circuit of the semiconductor device 101 , such as the CPU 10 or the accelerator 20 .
- the memory device 30 has a memory cell array 31 and a peripheral circuit 32 .
- the memory cell array 31 has memory cells 30M.
- a DOSRAM or NOSRAM is preferable as a storage circuit applicable to the memory cell 30M.
- DOSRAM registered trademark
- DOSRAM is an abbreviation for "Dynamic Oxide Semiconductor RAM” and refers to a RAM having 1T (transistor) 1C (capacitor) type memory cells.
- DOSRAM like NOSRAM, is a memory that utilizes the fact that the off-state current of an OS transistor is low.
- DOSRAM is a DRAM formed using OS transistors, and is a memory that temporarily stores information sent from the outside.
- the memory device 30 can be provided in different stacked layers of the memory cell 30M including the OS transistor and the peripheral circuit 32 including the Si transistor (transistor having silicon in the channel formation region).
- DOSRAM can reduce the overall circuit area.
- the DOSRAM can be divided into small memory cell arrays and arranged efficiently.
- the DOSRAM can have a stacked structure by including OS transistors provided in a plurality of layers.
- the bus 40A is a bus for transmitting and receiving various signals at high speed between the CPU 10, the accelerator 20, the memory device 30, the DMAC 41, the PMU 42, the memory controller 43, the DDR SDRAM controller 44, the USB interface circuit 45, and the display interface circuit 46.
- AMBA Advanced Microcontroller Bus Architecture
- HAB Advanced High-performance Bus
- the DMAC 41 is a direct memory access controller. By having the DMAC 41 , peripheral devices other than the CPU 10 can access the memory device 30 without the CPU 10 .
- the PMU 42 has a circuit configuration for controlling power gating of circuits such as the CPU core 11 of the CPU 10 of the semiconductor device 101 .
- the memory controller 43 has a circuit configuration for writing or reading a program to be executed by the CPU 10 or the accelerator 20 from a program memory outside the semiconductor device 101 .
- the DDR SDRAM controller 44 has a circuit configuration for writing data to or reading data from the main memory 103 such as a DRAM outside the semiconductor device 101 .
- the USB interface circuit 45 has a circuit configuration for transmitting and receiving data to and from a circuit outside the semiconductor device 101 via a USB terminal.
- the USB interface circuit 45 has a circuit configuration for transmitting and receiving signals to and from an external general-purpose device.
- the display interface circuit 46 has a circuit configuration for transmitting and receiving data to and from the display 102 outside the semiconductor device 101 .
- the power supply circuit 60 is a circuit for generating voltage used within the semiconductor device 101 .
- it is a circuit that generates a negative voltage for stabilizing electrical characteristics to be applied to the back gate of an OS transistor.
- the bus 40B is a bus for transmitting and receiving various signals between the interrupt control circuit 51, the interface circuit 52, the battery control circuit 53, and the ADC/DAC interface circuit 54 at low speed.
- AMBA-APB Advanced Peripheral Bus
- Transmission and reception of various signals between the bus 40A and the bus 40B are performed via the bridge circuit 50.
- the interrupt control circuit 51 has a circuit configuration for performing interrupt processing in response to requests received from peripheral devices.
- the interface circuit 52 has a circuit configuration for functioning an interface such as UART (Universal Asynchronous Receiver/Transmitter), I2C (Inter-Integrated Circuit), or SPI (Serial Peripheral Interface).
- UART Universal Asynchronous Receiver/Transmitter
- I2C Inter-Integrated Circuit
- SPI Serial Peripheral Interface
- the battery control circuit 53 has a circuit configuration for transmitting and receiving data relating to charging and discharging of the battery 104 outside the semiconductor device 101 .
- the ADC/DAC interface circuit 54 has a circuit configuration for transmitting and receiving data to and from a sensor 105 that outputs an analog signal, such as a MEMS (Micro Electro Mechanical Systems) device outside the semiconductor device 101 .
- a MEMS Micro Electro Mechanical Systems
- the bus 40B may also be configured to connect other circuits that operate at low speed, such as a timer circuit and a watchdog circuit.
- the electronic device 100 is configured such that electronic equipment such as a display 102, a main memory 103, a battery 104, and a sensor 105 are housed in a limited volume of a housing 111 in addition to the semiconductor device 101.
- the CPU 10 is provided with a backup circuit 10M
- the accelerator 20 is provided with a data holding circuit 20M
- the memory device 30 is provided with a memory cell 30M having an OS transistor.
- it is possible to reduce the frequency of data transfer for arithmetic processing in the accelerator 20 and increase the data capacity of the memory device 30 functioning as an on-chip memory.
- the semiconductor device 101 has a configuration in which a backup circuit 10M is provided in the CPU 10, a configuration in which a data holding circuit 20M is provided in the accelerator 20, and an OS transistor in the memory device 30.
- a backup circuit 10M is provided in the CPU 10
- a data holding circuit 20M is provided in the accelerator 20
- an OS transistor in the memory device 30 By providing the memory cell 30M, it is possible to greatly reduce the sleep power (power during the non-display period) when the electronic device 100 is in the sleep state. can.
- the electronic device 100 it is possible to reduce the number of data transfers between the on-chip memory, the CPU, and the accelerator.
- SoC System on Chip
- power consumption can be reduced, and heat generation can be suppressed by fine-grained power gating.
- Si transistor with a finer transistor structure By using a Si transistor with a finer transistor structure, a semiconductor device with a reduced size or higher performance can be achieved.
- an EL display having a light emitting device can be used.
- the display 102 may have a light receiving device in addition to the light emitting device.
- Display 102 may also be a liquid crystal display having a liquid crystal device.
- Display 102 may also be a ⁇ LED display having micro light emitting diode ( ⁇ LED) devices.
- the substrate constituting the display is attached with a connector such as FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package), or the substrate constituting the display is a COG (Chip On Glass) method.
- a connector such as FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package)
- COG Chip On Glass
- a device in which an IC (integrated circuit) is directly mounted is sometimes called a display module or the like.
- the display 102 may be a display module, or may be configured such that a light-emitting device is directly provided on the semiconductor device 101 to form the display 102 .
- a DRAM can be used as the main memory 103 .
- the main memory 103 can be omitted because the memory device 30 can also serve as the main memory 103 by increasing the memory capacity of the memory device 30, which is an on-chip memory.
- a secondary battery such as a lithium ion battery, a solar battery, or the like can be used.
- sensors such as an imaging device, a gyro sensor, an acceleration sensor, and a touch panel may be provided.
- a sensor or the like may be provided that is in contact with a part of the human body and measures the pulse, surface temperature, blood oxygen concentration, or the like.
- FIG. 2A is a diagram showing an example of arrangement of circuit blocks when the configuration of FIG. 1A is converted to SoC. As in the semiconductor device 101 illustrated in FIG. 2A, each configuration can be arranged by dividing the region on the chip.
- a circuit 10S corresponds to a circuit composed of Si transistors other than the backup circuit 10M in the CPU 10.
- FIG. The circuit 20S corresponds to a circuit composed of Si transistors in the accelerator 20 other than the data holding circuit 20M.
- the circuit 30S corresponds to a circuit composed of Si transistors, which are transistors other than the OS transistors included in the memory cell 30M in the memory device 30.
- FIG. 10S corresponds to a circuit composed of Si transistors other than the backup circuit 10M in the CPU 10.
- the circuit 20S corresponds to a circuit composed of Si transistors in the accelerator 20 other than the data holding circuit 20M.
- the circuit 30S corresponds to a circuit composed of Si transistors, which are transistors other than the OS transistors included in the memory cell 30M in the memory device 30.
- FIG. 2B is a schematic diagram showing a backup circuit 10M (data holding circuit 20M or memory cell 30M) arranged on the circuit 10S (circuit 20S or circuit 30S).
- the backup circuit 10M data holding circuit 20M or memory cell 30M
- the backup circuit 10M has a transistor 201 (OS transistor) having a metal oxide in a semiconductor layer 202 having a channel formation region.
- the circuit 10S includes a transistor 203 (Si transistor) including silicon in the semiconductor layer 204 having a channel formation region. Therefore, the CPU 10, the accelerator 20, and the memory device 30 can be arranged in the same area by integrating each circuit like the semiconductor device 101 shown in FIG. 2A when the SoC is implemented.
- a novel electronic device or the like can be provided according to one aspect of the present invention described above.
- one embodiment of the present invention can provide an electronic device or the like having a novel structure in which an increase in heat generation and power consumption can be suppressed in an electronic device including a semiconductor device whose performance is improved by SoC.
- one embodiment of the present invention can provide an electronic device or the like with a novel structure in which the number of data transfers in a CPU can be reduced.
- one embodiment of the present invention can provide an electronic device or the like with a novel structure that achieves both high performance of a semiconductor device and low power consumption or suppression of heat generation in the semiconductor device. can.
- FIG. 3 shows a configuration example of the CPU 10.
- the CPU 10 includes a CPU core (CPU Core) 11, an L1 (level 1) cache memory device (L1 Cache) 12, an L2 cache memory device (L2 Cache) 13, a bus interface (Bus I/F) 14, a power switch 15A to 15C, and a level shifter (LS) 15D.
- the CPU core 11 has flip-flops 16 .
- the CPU core 11, the L1 cache memory device 12, and the L2 cache memory device 13 are interconnected by the bus interface unit 14.
- the PMU 42 generates a clock signal GCLK1 and various PG (power gating) control signals (PG control signals) in response to externally input interrupt signals (Interrupts) and signals such as the signal SLEEP1 issued by the CPU 10.
- a clock signal GCLK1 and a PG control signal are input to the CPU 10 .
- the PG control signal controls power switches 15A-15C and flip-flop 16.
- the power switches 15A and 15B respectively control the supply of voltages VDDD and VDD1 to the virtual power line V_VDD (hereinafter referred to as V_VDD line).
- the power switch 15C controls supply of voltage VDDH to the level shifter (LS) 15D.
- a voltage VSSS is input to the CPU 10 and the PMU 42 without passing through the power switch.
- a voltage VDDD is input to the PMU 42 without passing through the power switch.
- the voltages VDDD and VDD1 are drive voltages for CMOS circuits.
- Voltage VDD1 is lower than voltage VDDD and is a drive voltage in the sleep state.
- Voltage VDDH is a drive voltage for the OS transistor and is higher than voltage VDDD.
- Each of the L1 cache memory device 12, L2 cache memory device 13 and bus interface unit 14 has at least one power domain capable of power gating.
- a power domain capable of power gating is provided with one or more power switches. These power switches are controlled by PG control signals.
- the flip-flop 16 is used as a register.
- the flip-flop 16 is provided with a backup circuit.
- the flip-flop 16 will be described below.
- FIG. 4A shows a circuit configuration example of the flip-flop 16 (Flip-flop).
- the flip-flop 16 has a scan flip-flop circuit (Scan Flip-flop) 17 and a backup circuit (Backup Circuit) 10M.
- the scan flip-flop circuit 17 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 17A.
- a node D1 is a data input node
- a node Q1 is a data output node
- a node SD is a scan test data input node.
- Node SE is the input node for signal SCE.
- a node CK is an input node for the clock signal GCLK1.
- the clock signal GCLK1 is input to the clock buffer circuit 17A.
- the analog switches of the scan flip-flop circuit 17 are connected to nodes CK1 and CKB1 of the clock buffer circuit 17A.
- a node RT is an input node for a reset signal.
- a signal SCE is a scan enable signal and is generated by the PMU 42 .
- PMU 42 produces signals BK and RC.
- the level shifter 15D level-shifts the signals BK and RC to generate the signals BKH and RCH.
- Signals BK and RC are backup and recovery signals.
- the circuit configuration of the scan flip-flop circuit 17 is not limited to that shown in FIG. 4A.
- a flip-flop prepared in a standard circuit library can be applied.
- the backup circuit 10M has nodes SD_IN, SN11, transistors M11 to M13, and a capacitor C11.
- a node SD_IN is an input node for scan test data and is connected to the node Q1 of the scan flip-flop circuit 17 .
- a node SN11 is a holding node of the backup circuit 10M.
- Capacitor C11 is a holding capacitor for holding the voltage of node SN11.
- the transistor M11 controls the conduction state between the node Q1 and the node SN11.
- Transistor M12 controls conduction between node SN11 and node SD.
- Transistor M13 controls conduction between node SD_IN and node SD.
- the on/off state of the transistors M11 and M13 is controlled by the signal BKH, and the on/off state of the transistor M12 is controlled by the signal RCH.
- the transistors M11 to M13 are OS transistors.
- the transistors M11 to M13 are illustrated as having back gates. Back gates of the transistors M11 to M13 are connected to a power line that supplies the voltage VBG1.
- At least the transistors M11 and M12 are preferably OS transistors.
- the OS transistor has an extremely small off-state current, which makes it possible to suppress a voltage drop at the node SN11, and consumes almost no power to hold data. Therefore, the backup circuit 10M has nonvolatile characteristics. Since data is rewritten by charging/discharging the capacitor C11, the backup circuit 10M has no limitation on the number of rewrites in principle, and can write and read data with low energy.
- the backup circuit 10M can be laminated on the scan flip-flop circuit 17 composed of a silicon CMOS circuit.
- the backup circuit 10M Since the backup circuit 10M has a very small number of elements compared to the scan flip-flop circuit 17, there is no need to change the circuit configuration and layout of the scan flip-flop circuit 17 in order to stack the backup circuit 10M. That is, the backup circuit 10M is a highly versatile backup circuit. Further, since the backup circuit 10M can be provided in the region where the scan flip-flop circuit 17 is formed, the area overhead of the flip-flop 16 can be reduced to zero even if the backup circuit 10M is incorporated. Therefore, power gating of the CPU core 11 becomes possible by providing the backup circuit 10M in the flip-flop 16. FIG. Since the energy required for power gating is small, it is possible to power-gate the CPU core 11 with high efficiency.
- the backup circuit 10M By providing the backup circuit 10M, the parasitic capacitance due to the transistor M11 is added to the node Q1. has no effect on That is, even if the backup circuit 10M is provided, the performance of the flip-flop 16 does not substantially deteriorate.
- a clock gating state, a power gating state, and a sleep state can be set.
- the PMU 42 selects the low power consumption mode of the CPU core 11 based on the interrupt signal, signal SLEEP1, and the like. For example, when transitioning from the normal operating state to the clock gating state, the PMU 42 stops generating the clock signal GCLK1.
- the PMU 42 when transitioning from a normal operating state to a resting state (non-operating state), the PMU 42 performs voltage and/or frequency scaling. For example, when performing voltage scaling, the PMU 42 turns off the power switch 15A and turns on the power switch 15B in order to input the voltage VDD1 to the CPU core 11 .
- the voltage VDD1 is a voltage that does not cause the data of the scan flip-flop circuit 17 to disappear.
- PMU 42 reduces the frequency of clock signal GCLK1.
- Signals PSE0 to PSE2 are control signals for power switches 15A to 15C and are generated by PMU 42 .
- the power switch 15A is on/off. The same applies to the signals PSE1 and PSE2.
- the power switch 15A Before time t1, it is in normal operation.
- the power switch 15A is on, and the CPU core 11 is supplied with the voltage VDDD.
- the scan flip-flop circuit 17 performs normal operation.
- the power switch 15C Since the level shifter 15D does not need to be operated, the power switch 15C is off and the signals SCE, BK and RC are "L”. Since the node SE is "L”, the scan flip-flop circuit 17 stores the data of the node D1.
- the node SN11 of the backup circuit 10M is "L” at time t1.
- the PMU 42 stops the clock signal GCLK1 and changes the signals PSE2 and BK to "H".
- the level shifter 15D becomes active and outputs the "H" signal BKH to the backup circuit 10M.
- the transistor M11 of the backup circuit 10M is turned on, and the data of the node Q1 of the scan flip-flop circuit 17 is written to the node SN11 of the backup circuit 10M. If the node Q1 of the scan flip-flop circuit 17 is "L”, the node SN11 remains “L”, and if the node Q1 is "H”, the node SN11 becomes "H”.
- the PMU 42 sets the signals PSE2 and BK to "L” at time t2, and sets the signal PSE0 to "L” at time t3. At time t3, the state of the CPU core 11 shifts to the power gating state. Note that the signal PSE0 may fall at the same timing as the signal BK falls.
- the PMU 42 changes the signal PSE0 to "H", thereby shifting from the power gating state to the recovery state.
- the PMU 42 changes the signals PSE2, RC and SCE to "H".
- the transistor M12 is turned on, and the charge of the capacitor C11 is distributed between the node SN11 and the node SD. If the node SN11 is "H”, the voltage of the node SD rises. Since the node SE is at "H”, the data of the node SD is written into the input-side latch circuit of the scan flip-flop circuit 17.
- FIG. When clock signal GCLK1 is input to node CK at time t6, data in the input-side latch circuit is written to node Q1. That is, the data of node SN11 is written to node Q1.
- the PMU 42 sets the signals PSE2, SCE, and RC to "L", and the recovery operation ends.
- the backup circuit 10M using OS transistors has low dynamic and static power consumption, so it is very suitable for normally-off computing. Even if the flip-flop 16 is mounted, the deterioration of the performance of the CPU core 11 and the increase of the dynamic power can be hardly caused.
- the CPU core 11 may have a plurality of power domains capable of power gating.
- a plurality of power domains are provided with one or more power switches for controlling voltage input.
- the CPU core 11 may have one or more power domains in which power gating is not performed.
- a power gating control circuit for controlling the flip-flop 16 and power switches 15A to 15C may be provided in a power domain where power gating is not performed.
- the application of the flip-flop 16 is not limited to the CPU 10.
- the flip-flop 16 can be applied to a register provided in a power domain capable of power gating.
- a memory cell 19 shown in FIG. 6A is an example of a circuit diagram of a memory cell applicable to cache memory devices such as the L1 cache memory device 12 and the L2 cache memory device 13 .
- the memory cell 19S shown in FIG. 6A has the same circuit configuration as a standard 6T type SRAM cell.
- a backup circuit 19A shown in FIG. 6A is a circuit for saving data in the memory cell 19S.
- the backup circuit 19A is a circuit for backing up the data of the nodes Q and Qb of the memory cell 19S, and is composed of two 1T1C type cells. Nodes SN1 and SN2 are retention nodes. A gain cell composed of a transistor MW5 and a capacitive element CS5 backs up the data of the node Q. FIG. A gain cell composed of a transistor MW6 and a capacitive element CS6 backs up the data of the node Qb.
- the backup circuit 19A can be laminated on the memory cell 19S. Thereby, the area overhead of the memory cell 19 due to the provision of the backup circuit 19A can be suppressed. Zero area overhead is possible.
- the memory cells 19S are electrically connected to power supply lines V_VDM, V_VSM, word lines WL, and bit line pairs (BL, BLB).
- Power supply lines V_VDM and V_VSM are power supply lines for Vddd and GND, respectively.
- the backup circuit 19A is electrically connected to the wirings OGL and BGL and the power supply line PL3.
- a voltage GND is input to the power line PL3.
- the memory cell 19 operates as an SRAM cell in a normal state. An example operation of the memory cell 19 of FIG. 6A will be described with reference to FIG. 6B. If the memory cell 19 is not accessed for a certain period of time or more, the supply of the voltages Vddd and GND to the power supply lines V_VDM and V_VSM is stopped. The data of the nodes Q and Qb are written to the backup circuit 19A before the supply of the voltage Vddd is stopped. In FIG. 6B, t1, t2, etc. represent times.
- Memory cell 19 Before time t1, it is in a normal operation state (write state or read state). Memory cell 19 operates similarly to a single port SRAM. Here, it is assumed that nodes Q/Qb are "H"/"L” and nodes SN1/SN2 are "L"/"H” at time t1.
- the recovery operation is an operation of recovering the data in the memory cell 19S using the data held by the backup circuit 19A.
- memory cell 19S functions as a sense amplifier for sensing data on node Q/Qb.
- the reset operation of the nodes Q and Qb is performed.
- the voltage of the bit line pair (BL, BLB) is precharged to voltage Vpr2.
- the power supply lines V_VDM line and V_VSM line are precharged to the voltage Vpr2, and the voltages of the nodes Q and Qb are fixed at Vpr2.
- the transistors MW5 and MW6 are turned on.
- the charge of the capacitive element CS5 is distributed to the node Q and the node SN1
- the charge of the capacitive element CS6 is distributed to the node Qb and the node SN2
- a voltage difference is generated between the node Q and the node Qb.
- a memory cell 19_1 shown in FIG. 7A is a modification of the memory cell 19 and has a backup circuit 19B instead of the backup circuit 19A.
- the backup circuit 19B is composed of one 1T1C type memory cell, and has a node SN3, a transistor MW7, and a capacitive element CS7.
- FIG. 7B is a timing chart showing an operation example of the memory cell 19_1.
- Memory cell 19_1 operates similarly to memory cell 19 .
- the description of FIG. 7B incorporates the description of FIG. 6B.
- the backup circuit 19B is configured to back up only the data of the node Q, but the data of the nodes Q and Qb can be restored by the data held in the node SN3. This is because the voltages of the nodes Q and Qb are precharged to Vpr2, and the charge of one capacitive element CS7 can generate a potential difference between the nodes Q and Qb.
- FIG. 8A is a block diagram for explaining the accelerator 20.
- FIG. 8A in addition to the memory circuit 21 having the data holding circuit 20M and the arithmetic circuit 22 described in FIG. Wiring 26 is shown.
- FIG. 8A shows a write bit line driver 23A, a word line driver 23B, a read bit line driver 23C, and a read driver 23D as an example of a configuration functioning as the control circuit 23.
- the control circuit 23 may have a precharge circuit, a sense amplifier, a selector, an input buffer, an arithmetic control circuit, and the like.
- the write bit line driver 23A and word line driver 23B generate, for example, a signal for writing data to the data holding circuit 20M.
- the read bit line driver 23C and the read driver 23D generate, for example, signals for reading data from the data holding circuit 20M.
- the memory circuit 21 having the data holding circuit 20M has a function of storing the data processed by the accelerator 20. Specifically, data input to or output from the arithmetic circuit 22, such as weight data used for parallel processing of sum-of-products operations of a neural network, can be stored.
- the data holding circuit 20M is electrically connected to the arithmetic block 25 of the arithmetic circuit 22 via wiring 26, and has a function of holding a binary or ternary digital value.
- the transistors are OS transistors, and the data holding circuit 20M is preferably an OS memory. Since the accelerator 20 has the data holding circuit 20M, which is an OS memory, it can hold data even when the supply of the power supply voltage is stopped. As a result, power gating of the accelerator 20 becomes possible, and a significant reduction in power consumption can be achieved.
- the data holding circuit 20M made up of OS transistors can be stacked with the arithmetic circuit 22 made up of Si CMOS. Therefore, it can be arranged without increasing the circuit area.
- the data holding circuit 20M and the arithmetic circuit 22 are electrically connected via a wiring 26 provided extending in a direction substantially perpendicular to the surface of the substrate on which the arithmetic circuit 22 is provided. It should be noted that "substantially perpendicular" means a state in which they are arranged at an angle of 85 degrees or more and 95 degrees or less.
- the data holding circuit 20M can have a circuit configuration of NOSRAM.
- a NOSRAM can be used as a non-volatile memory by retaining charges corresponding to data in a memory circuit using the characteristic of extremely small leakage current.
- NOSRAM can read data without destroying it (non-destructive reading), it is suitable for parallel processing of sum-of-products operations in neural networks that repeat only data reading operations in large numbers.
- the plurality of operation blocks 25 of the operation circuit 22 have the function of performing arithmetic processing using digital values. Digital values are less susceptible to noise. Therefore, the accelerator 20 is suitable for performing arithmetic processing that requires highly accurate arithmetic results.
- the arithmetic circuit 22 is preferably composed of a Si CMOS, that is, a transistor (Si transistor) having silicon in a channel formation region. With such a structure, it can be stacked with the OS transistor.
- FIG. 8B illustrates a hierarchical neural network based on the architecture of the Binary Neural Network (BNN)
- BNN Binary Neural Network
- FIG. 8B illustrates a hierarchical neural network based on the BNN architecture.
- FIG. 8B illustrates a fully-connected neural network including a neuron N1, one input layer (I1), three intermediate layers (M1 to M3), and one output layer (O1).
- the number of neurons in the input layer I1 is 786
- the number of neurons in the intermediate layers M1 to M3 is 256
- the number of neurons in the output layer O1 is 10
- the number of connections in each layer is (784 ⁇ 256)+(256 ⁇ 256)+(256).
- x256) + (256 x 10) 334336 in total. That is, since the weight parameters required for neural network calculation are about 330 Kbits in total, the memory capacity can be sufficiently implemented even in a small-scale system.
- the arithmetic block 25 uses the digital value data held in each of the data holding circuits 20M of the memory circuit 21 to perform any one of integer arithmetic, single-precision floating-point arithmetic, double-precision floating-point arithmetic, and the like. have a function.
- the calculation block 25 has a function of repeatedly executing the same processing such as sum-of-products calculation.
- the calculation block 25 is configured such that one calculation block 25 is provided for each read bit line of the data holding circuit 20M, that is, for each column (Column-Parallel Calculation). With this configuration, data for one row (up to all bit lines) of the memory circuit 21 can be processed in parallel. Compared to the sum-of-products operation using the CPU 10, there is no restriction on the size of the data bus between the CPU and memory (32 bits, etc.). It is possible to improve the computational efficiency related to enormous computational processing such as deep neural network learning (deep learning), which is an AI technology, and scientific and technical calculations that perform floating point computations.
- deep neural network learning deep learning
- the data output from the data holding circuit 20M can be read out after completing the calculation, the number of memory accesses (data transfer between the CPU and the memory or calculations in the CPU) can be reduced, and the power generated by the memory access can be reduced. can be reduced. Furthermore, by shortening the physical distance between the arithmetic circuit 22 and the memory circuit 21, for example, by shortening the wiring distance by stacking, parasitic capacitance generated in the signal line can be reduced, so that power consumption can be reduced.
- One aspect of the present invention can reduce the number of data transfers between the CPU 10 and the accelerator 20 .
- a semiconductor device that functions as an accelerator for AI technology which requires a huge amount of calculation and a large number of parameters, has a non-Von Neumann architecture, and consumes extremely little power compared to the Von Neumann architecture, which consumes more power as the processing speed increases. Parallel processing can be done with power.
- FIG. 9A is a diagram illustrating a circuit configuration example applicable to the memory circuit 21.
- write word lines WWL_1 to WWL_M write word lines WWL_1 to WWL_M
- read word lines RWL_1 to RWL_M read word lines
- write bit lines WBL_1 to WBL_N write bit lines
- read bit lines are arranged in the matrix direction of M rows and N columns (M and N are natural numbers of 2 or more). Lines RBL_1 through RBL_N are shown.
- a data holding circuit 20M connected to each word line and bit line is also shown.
- FIG. 9B is a diagram explaining a circuit configuration example applicable to the data holding circuit 20M.
- the data holding circuit 20M has a transistor M1, a transistor M2, a transistor M3, and a capacitor C1.
- One of the source and drain of the transistor M1 is connected to the write bit line WBL.
- a gate of the transistor M1 is connected to the write word line WWL.
- the other of the source and drain of transistor M1 is connected to one electrode of capacitor C1 and the gate of transistor M2.
- One of the source or drain of transistor M2 and the other electrode of capacitor C1 are connected to a wiring that gives a fixed potential, for example, a ground potential.
- the other of the source or drain of transistor M2 is connected to one of the source or drain of transistor M3.
- a gate of the transistor M3 is connected to the read word line RWL.
- the other of the source and drain of the transistor M3 is connected to the read bit line RBL.
- the read bit line RBL is connected to the operation block 25 via the wiring 26 or the like extending in a direction substantially perpendicular to the substrate surface on which the operation circuit 22 is provided, as described above.
- the circuit configuration of the data holding circuit 20M shown in FIG. 9B corresponds to a 3-transistor (3T) gain cell NOSRAM.
- the transistors M1 to M3 are OS transistors.
- the current flowing between the source and the drain of the OS transistor in the off state, that is, the leak current is extremely small.
- a NOSRAM can be used as a non-volatile memory by retaining charges corresponding to data in a memory circuit using the characteristic of extremely small leakage current.
- a memory device 30 shown in FIG. 10A has a memory cell array 31 and peripheral circuits 32 .
- a control circuit 34 , a row circuit 35 , a column circuit 36 and an input/output circuit 37 are provided as the peripheral circuit 32 .
- the memory cell array 31 has memory cells 33, read word lines RWL, write word lines WWL, read bit lines RBL, write bit lines WBL, source lines SL, and wirings BGL.
- the read word line RWL and the write word line WWL may be called the word line RWL and the word line WWL, respectively.
- a read bit line RBL and a write bit line WBL may be called a bit line RBL and a bit line WBL, respectively.
- the control circuit 34 controls the entire memory device 30 and writes and reads data.
- Control circuit 34 processes external command signals (eg, chip enable signal, write enable signal, etc.) to generate control signals for other circuits of peripheral circuit 32 .
- external command signals eg, chip enable signal, write enable signal, etc.
- the row circuit 35 has a function of selecting a row to access.
- row circuitry 35 has a row decoder and a word line driver.
- the column circuit 36 has a function of precharging the bit lines WBL and RBL, a function of writing data to the bit line WBL, a function of amplifying data on the bit line RBL, a function of reading data from the bit line RBL, and the like.
- the input/output circuit 37 has a function of holding write data, a function of holding read data, and the like.
- the configuration of the peripheral circuit 32 is appropriately changed depending on the configuration of the memory cell array 31, read method, write method, and the like.
- FIG. 10B A circuit configuration example of the memory cell 33 is shown in FIG. 10B.
- memory cell 33 is a two-transistor (2T) gain cell.
- the memory cell 33 has transistors MW1 and MR1 and a capacitive element CS1.
- Transistor MW1 is a write transistor and transistor MR1 is a read transistor.
- Back gates of the transistors MW1 and MR1 are electrically connected to the wiring BGL.
- the memory cell 33 Since the OS transistor constitutes the read transistor, the memory cell 33 does not consume power for data retention. Therefore, the memory cell 33 is a low power consumption memory cell capable of holding data for a long period of time, and the memory device 30 can be used as a nonvolatile memory device.
- the OS transistor and the capacitor can be stacked on the Si transistor. Therefore, the memory cell array 31 can be stacked on the peripheral circuit 32, and the degree of integration of the memory cell array 31 can be improved.
- FIGS. 11A to 11F Another configuration example of the memory cell will be described with reference to FIGS. 11A to 11F.
- a memory cell 33A shown in FIG. 11A is a 3T gain cell and has transistors MW2, MR2, MS2, and a capacitive element CS2.
- Transistors MW2, MR2, and MS2 are a write transistor, read transistor, and select transistor, respectively. Back gates of the transistors MW2, MR2, and MS2 are electrically connected to the wiring BGL.
- the memory cell 33A is electrically connected to word lines RWL, WWL, bit lines RBL, WBL, capacitance line CDL, and power supply line PL2.
- a voltage GND low-level side power supply voltage
- Figs. 11B and 11C show other configuration examples of the 2T gain cell.
- the read transistor is composed of an n-channel Si transistor.
- the read transistor is composed of a p-channel Si transistor.
- FIGS. 11B and 11C a configuration in which an OS transistor and a Si transistor are combined as a transistor in a memory cell may be employed.
- Figs. 11D and 11E show other configuration examples of the 3T gain cell.
- the read transistor and the select transistor are composed of n-channel Si transistors.
- the read transistor and the select transistor are composed of p-channel Si transistors.
- voltage Vddd high-level side power supply voltage
- bit lines that also serve as the read bit line RBL and the write bit line WBL may be provided.
- FIG. 11F An example of a 1T1C (capacitance) type memory cell is shown in FIG. 11F.
- a memory cell 33F shown in FIG. 11F is electrically connected to a word line WL, a bit line BL, a capacitor line CDL, and a wiring BGL.
- the memory cell 33F has a transistor MW3 and a capacitive element CS3.
- a back gate of the transistor MW3 is electrically connected to the wiring BGL.
- circuit configuration of the memory cell 30M of the memory device 30 in addition to a circuit configuration composed only of OS transistors, a circuit configuration combined with Si transistors can be used.
- a novel electronic device or the like can be provided according to one aspect of the present invention described above.
- one embodiment of the present invention can provide an electronic device or the like having a novel structure in which an increase in heat generation and power consumption can be suppressed in an electronic device including a semiconductor device whose performance is improved by SoC.
- one embodiment of the present invention can provide an electronic device or the like with a novel structure in which the number of data transfers in a CPU can be reduced.
- one embodiment of the present invention can provide an electronic device or the like with a novel structure that achieves both high performance of a semiconductor device and low power consumption or suppression of heat generation in the semiconductor device. can.
- FIG. 12 is a diagram explaining an example of the operation when part of the computation of the program executed by the CPU 10 is executed by the accelerator 20.
- FIG. 12 is a diagram explaining an example of the operation when part of the computation of the program executed by the CPU 10 is executed by the accelerator 20.
- a host program is executed by the CPU 10 (step S1).
- step S2 When the CPU 10 confirms an instruction to allocate a data area required for calculation using the accelerator 20 in the memory circuit 21 (step S2), the CPU 10 allocates the data area in the memory circuit 21. (step S3).
- the CPU 10 transmits input data from the main memory 103 or the memory device 30 to the memory circuit 21 (step S4).
- the memory circuit 21 receives the input data and stores the input data in the area secured in step S2 (step S5).
- step S6 When the CPU 10 confirms the instruction to start the kernel program (step S6), the accelerator 20 starts executing the kernel program (step S7).
- the CPU 10 may be switched from the operating state to the PG state (step S8). In this case, immediately before the accelerator 20 finishes executing the kernel program, the CPU 10 is switched from the PG state to the operating state (step S9). By keeping the CPU 10 in the PG state during the period from step S8 to step S9, power consumption and heat generation of the semiconductor device 101 as a whole can be suppressed.
- the output data is stored in the memory circuit 21 (step S10).
- the CPU 10 confirms an instruction to transmit the output data stored in the memory circuit 21 to the main memory 103 or the memory device 30 (step S11). It is transmitted to the memory 103 or the memory device 30 and stored in the main memory 103 or the memory device 30 (step S12).
- step S13 When the CPU 10 confirms the instruction to release the data area secured on the memory circuit 21 (step S13), the area secured on the memory circuit 21 is released (step S14).
- step S1 to step S14 By repeating the operations from step S1 to step S14 described above, power consumption and heat generation of the CPU 10 and the accelerator 20 can be suppressed, and part of the calculation of the program executed by the CPU 10 can be executed by the accelerator.
- FIG. 13A shows a semiconductor device 101 having a CPU 10, an accelerator 20, and a memory device 30 connected to a bus 40A, as well as a main memory 103 composed of a DRAM or the like. Also, in FIG. 13A, the data between the memory device 30 and the CPU 10 is illustrated as data D CPU . Also, in FIG. 13A, the data between the memory device 30 and the accelerator 20 is illustrated as data D ACC .
- data can be continuously held in the memory circuit 21 having the data holding circuit 20M of the accelerator 20, and the arithmetic result obtained by the arithmetic circuit 22 can be sent to the CPU 10. It can be configured to output. Therefore, the data DACC from the memory device 30 for arithmetic processing can be reduced. Moreover, since the amount of arithmetic processing of the CPU 10 can be reduced, the data D CPU between the memory device 30 and the CPU 10 can also be reduced. That is, with the configuration of one embodiment of the present invention, the number of accesses via the bus 40A and the amount of data to be transferred can be reduced.
- the backup circuit 10M in the CPU 10, the data holding circuit 20M in the accelerator 20, and the OS transistors of the memory cells 30M in the memory device 30 are stacked with the circuits 10S, 20S, and 30S that can be made of Si CMOS. can be provided. Therefore, it can be arranged without increasing the circuit area.
- the memory device 30 is an OS memory such as DOSRAM or NOSRAM. As shown in FIG. 13B, layers having OS transistors are stacked to form a memory cell 30M. By doing so, the storage capacity per unit area can be increased. In this case, the main memory 103 provided separately from the semiconductor device 101 can be omitted.
- FIG. 14A is a diagram illustrating the relationship between processing performance (OPS: Operations Per Second) and power consumption (W).
- OPS Operations Per Second
- W power consumption
- the vertical axis represents processing capacity
- the horizontal axis represents power consumption.
- 0.1 TOPS/W Transmission Operations Per Second/W
- 1 TOPS/W 1 TOPS/W
- 10 TOPS/W 10 TOPS/W
- 100 TOPS/W are indicated by dashed lines as indices of computational efficiency. .
- a region 710 indicates a region including a conventional general-purpose AI accelerator (Von Neumann type), and a region 712 indicates a region including a semiconductor device of one embodiment of the present invention.
- the area 710 includes, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and an FPGA (Field-Programmable Gate Array).
- power consumption can be reduced by about two orders of magnitude and processing performance can be improved as compared with a conventional general-purpose AI accelerator (Von Neumann type). It can be improved significantly (eg, 1000 times or more). Note that by using the semiconductor device of one embodiment of the present invention, computation efficiency of 100 TOPS/W or higher can be expected.
- a conventional general-purpose AI accelerator Von Neumann type
- FIG. 14B shows an image diagram of power consumption of a semiconductor device with a conventional structure in image recognition
- FIG. 14C shows an image diagram of power consumption of a semiconductor device using the structure of one embodiment of the present invention in image recognition.
- the vertical axis represents power and the horizontal axis represents time.
- power 714 indicates leak power
- power 716 indicates CPU power
- power 718 indicates memory power.
- power 714 indicates leak power
- power 720 indicates CPU power
- power 722 indicates accelerator power. Note that the power 722 also includes power used for an arithmetic circuit and a memory device.
- arrows a, b, and c each represent signals in image recognition. It is assumed that arithmetic processing such as image recognition is started in the semiconductor device when signals of arrow a, arrow b, and arrow c are input.
- leakage power (power 714) is generated with time.
- leakage power (power 714) is generated, but during periods when CPU power (power 720) and accelerator power (power 722) are not used, normally-off driving in which leakage power (power 714) does not occur (period shown in FIG. 14C t1). This makes it possible to significantly reduce power consumption. That is, a semiconductor device with extremely low power consumption can be provided.
- each circuit is integrated into a semiconductor device with extremely low power consumption.
- one embodiment of the present invention may be a modified example of an SoC in which another device is provided in a layer above a circuit including an OS transistor.
- FIG. 15A is a schematic diagram of a semiconductor device 101A in which a layer 391 having a variable resistance device 392, which is another memory device different from the OS memory, is provided above the backup circuit 10M, which is a layer having an OS transistor. .
- a backup circuit 10M having an OS transistor may be provided above a circuit 10S having a CPU core 11 and the like, and a layer 391 having a variable resistance device 392 may be provided thereabove.
- a data holding circuit 20M can be provided in a layer having an OS transistor above a circuit 20S having an arithmetic circuit 22 and the like.
- a memory cell 30M in which memory cells 30M are stacked over a circuit 30S having a peripheral circuit 32 and the like can be arranged.
- a circuit 390 or the like having a Si transistor included in the semiconductor device 101 can be provided.
- variable resistance device 39 for example, flash memory, ferroelectric memory (FeRAM), magnetoresistive memory (MRAM), phase change memory (PRAM), resistance change memory (ReRAM), etc. can be used.
- FeRAM ferroelectric memory
- MRAM magnetoresistive memory
- PRAM phase change memory
- ReRAM resistance change memory
- MRAM magnetoresistive memory
- STT-MRAM Spin Transfer Torque-Magnetoresistive Random Access Memory
- An MTJ element consists of a free layer (also called a recording layer, free layer, or movable layer), a fixed layer (also called a magnetization fixed layer, a pinned layer, or a reference layer), an insulating layer ( Also called a barrier layer, a tunnel insulating film, or a nonmagnetic layer).
- an SoC in which circuits such as a CPU 10, an accelerator 20, and a memory device 30 are tightly coupled has a problem of heat generation. It is suitable because it is small compared to
- parasitic capacitance can be reduced compared to a laminated structure using a through silicon via (TSV) or the like. . Power consumption required for charging and discharging each wiring can be reduced. Therefore, it is possible to improve the arithmetic processing efficiency.
- TSV through silicon via
- FIG. 15B shows a layer 393 having a light emitting device 394, which is another memory device different from the OS memory, above a layer having OS transistors such as the backup circuit 10M, the data retention circuit 20M and the memory cell 30M.
- a light emitting device 394 a light emitting device such as an organic light emitting diode can be used.
- an SoC in which circuits such as a CPU 10, an accelerator 20, and a memory device 30 are tightly coupled has a problem of heat generation. and is small.
- the parasitic capacitance can be reduced compared to a laminated structure using a through silicon via (TSV) or the like. . Power consumption required for charging and discharging each wiring can be reduced. Therefore, it is possible to improve the arithmetic processing efficiency.
- TSV through silicon via
- FIG. 16 A part of the cross-sectional structure of the semiconductor device is shown in FIG.
- a semiconductor device illustrated in FIG. 16 includes a transistor 550 , a transistor 500 , and a capacitor 600 .
- 17A is a cross-sectional view of the transistor 500 in the channel length direction
- FIG. 17B is a cross-sectional view of the transistor 500 in the channel width direction
- FIG. 17C is a cross-sectional view of the transistor 550 in the channel width direction.
- the transistor 500 corresponds to the Si transistor described in the above embodiment
- the transistor 550 corresponds to the OS transistor.
- the transistor 500 is provided above the transistor 550 and the capacitor 600 is provided above the transistors 550 and 500 .
- the transistor 550 is provided over a substrate 311 and has a conductor 316, an insulator 315, a semiconductor region 313 made up of part of the substrate 311, a low resistance region 314a functioning as a source region or a drain region, and a low resistance region 314b. .
- the transistor 550 As shown in FIG. 17C, in the transistor 550, the upper surface and side surfaces in the channel width direction of the semiconductor region 313 are covered with the conductor 316 with the insulator 315 interposed therebetween.
- the transistor 550 Fin-type By making the transistor 550 Fin-type in this way, the effective channel width is increased, so that the on-characteristics of the transistor 550 can be improved. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 550 can be improved.
- the transistor 550 may be either a p-channel type or an n-channel type.
- a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, low-resistance regions 314a and 314b serving as a source region or a drain region, and the like preferably contain a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 550 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.
- HEMT High Electron Mobility Transistor
- the low-resistance region 314a and the low-resistance region 314b are made of an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron in addition to the semiconductor material applied to the semiconductor region 313. contains elements that
- the conductor 316 functioning as a gate electrode is a semiconductor material such as silicon containing an element imparting n-type conductivity such as arsenic or phosphorus or an element imparting p-type conductivity such as boron, a metal material, or an alloy. material, or a conductive material such as a metal oxide material can be used.
- the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, a material such as titanium nitride or tantalum nitride is preferably used for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminated conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.
- the transistor 550 may be formed using an SOI (Silicon Insulator) substrate or the like.
- the SOI substrate is formed by implanting oxygen ions into a mirror-polished wafer and then heating the wafer to a high temperature to form an oxide layer at a certain depth from the surface and eliminate defects in the surface layer.
- a SIMOX (Separation by Implanted Oxygen) substrate or a smart cut method, ELTRAN method (registered trademark: Epitaxial Layer Transfer), etc., in which a semiconductor substrate is cleaved by growing microvoids formed by hydrogen ion implantation through heat treatment.
- an SOI substrate formed by A transistor formed using a single crystal substrate includes a single crystal semiconductor in a channel formation region.
- An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in order to cover the transistor 550 .
- the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. Just do it.
- silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
- silicon oxynitride refers to a material whose composition contains more nitrogen than oxygen.
- aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen
- aluminum oxynitride refers to a material whose composition contains more nitrogen than oxygen. indicates
- the insulator 322 may function as a planarization film that planarizes a step caused by the transistor 550 or the like provided therebelow.
- the top surface of the insulator 322 may be planarized by a chemical mechanical polishing (CMP) method or the like to improve planarity.
- CMP chemical mechanical polishing
- the insulator 324 it is preferable to use a film having a barrier property such that hydrogen, impurities, or the like do not diffuse from the substrate 311, the transistor 550, or the like to the region where the transistor 500 is provided.
- a film having a barrier property against hydrogen for example, silicon nitride formed by a CVD method can be used.
- diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 500 might degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses diffusion of hydrogen between the transistor 500 and the transistor 550 .
- the film that suppresses diffusion of hydrogen is a film from which the amount of desorption of hydrogen is small.
- the desorption amount of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS).
- TDS thermal desorption spectroscopy
- the amount of hydrogen released from the insulator 324 is the amount of hydrogen atoms released per area of the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. , 10 ⁇ 10 15 atoms/cm 2 or less, preferably 5 ⁇ 10 15 atoms/cm 2 or less.
- the insulator 326 preferably has a lower dielectric constant than the insulator 324 .
- the dielectric constant of insulator 326 is preferably less than 4, more preferably less than 3.
- the dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, that of the insulator 324 .
- the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitor 600, a conductor 328 connected to the transistor 500, a conductor 330, or the like.
- the conductors 328 and 330 function as plugs or wirings.
- conductors functioning as plugs or wiring may be given the same reference numerals collectively for a plurality of configurations.
- the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as a wiring and a part of the conductor functions as a plug.
- each plug and wiring As a material for each plug and wiring (conductor 328, conductor 330, etc.), a single layer or a laminate of conductive materials such as metal material, alloy material, metal nitride material, or metal oxide material is used. be able to. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material.
- a wiring layer may be provided over the insulator 326 and the conductor 330 .
- an insulator 350, an insulator 352, and an insulator 354 are stacked in order.
- a conductor 356 is formed over the insulators 350 , 352 , and 354 .
- the conductor 356 functions as a plug or wiring connected to the transistor 550 .
- the conductor 356 can be provided using a material similar to that of the conductors 328 and 330 .
- the conductor 356 preferably contains a conductor having a barrier property against hydrogen.
- a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen.
- tantalum nitride As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. In addition, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 550 can be suppressed while the conductivity of the wiring is maintained. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.
- a wiring layer may be provided over the insulator 354 and the conductor 356 .
- an insulator 360, an insulator 362, and an insulator 364 are stacked in order.
- a conductor 366 is formed over the insulators 360 , 362 , and 364 .
- Conductor 366 functions as a plug or wiring. Note that the conductor 366 can be provided using a material similar to that of the conductors 328 and 330 .
- the conductor 366 preferably contains a conductor having a barrier property against hydrogen.
- a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen.
- a wiring layer may be provided over the insulator 364 and the conductor 366 .
- an insulator 370, an insulator 372, and an insulator 374 are stacked in order.
- a conductor 376 is formed over the insulators 370 , 372 , and 374 .
- Conductor 376 functions as a plug or wiring. Note that the conductor 376 can be provided using a material similar to that of the conductors 328 and 330 .
- the conductor 376 preferably contains a conductor having a barrier property against hydrogen.
- a conductor having a barrier property against hydrogen is formed in the opening of the insulator 370 having a barrier property against hydrogen.
- a wiring layer may be provided over the insulator 374 and the conductor 376 .
- an insulator 380, an insulator 382, and an insulator 384 are stacked in order.
- a conductor 386 is formed over the insulators 380 , 382 , and 384 .
- Conductor 386 functions as a plug or wiring. Note that the conductor 386 can be provided using a material similar to that of the conductors 328 and 330 .
- the insulator 380 for example, an insulator having a barrier property against hydrogen is preferably used like the insulator 324.
- the conductor 386 preferably contains a conductor having a barrier property against hydrogen.
- a conductor having a barrier property against hydrogen is formed in the opening of the insulator 380 having a barrier property against hydrogen.
- the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 are described above. It is not limited to this.
- the number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.
- An insulator 510 , an insulator 512 , an insulator 514 , and an insulator 516 are laminated in this order on the insulator 384 .
- Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably a substance having barrier properties against oxygen, hydrogen, or the like.
- insulators 510 and 514 for example, a film having a barrier property that prevents hydrogen, impurities, or the like from diffusing from the substrate 311, a region where the transistor 550 is provided, or the like to a region where the transistor 500 is provided is used. is preferred. Therefore, a material similar to that of the insulator 324 can be used.
- Silicon nitride formed by a CVD method can be used as an example of a film having a barrier property against hydrogen.
- diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 500 might degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses diffusion of hydrogen between the transistor 500 and the transistor 550 .
- the film that suppresses diffusion of hydrogen is a film from which the amount of desorption of hydrogen is small.
- a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide for the insulators 510 and 514, which are films having a barrier property against hydrogen.
- aluminum oxide has a high shielding effect that prevents both oxygen and impurities such as hydrogen and moisture, which are factors that change the electrical characteristics of transistors, from penetrating through the film. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide forming the transistor 500 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 500 .
- the insulator 512 and the insulator 516 can be made of a material similar to that of the insulator 320 .
- the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.
- the insulator 510, the insulator 512, the insulator 514, and the insulator 516 are embedded with a conductor 518, a conductor forming the transistor 500 (eg, the conductor 503), and the like.
- the conductor 518 functions as a plug or wiring that is connected to the capacitor 600 or the transistor 550 .
- the conductor 518 can be provided using a material similar to that of the conductors 328 and 330 .
- a conductor 518 in a region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water.
- the transistor 550 and the transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.
- a transistor 500 is provided above the insulator 516 .
- transistor 500 includes conductor 503 disposed embedded in insulators 514 and 516 and insulator 520 disposed over insulators 516 and 503 . , insulator 522 over insulator 520, insulator 524 over insulator 522, oxide 530a over insulator 524, and oxide 530a over oxide 530a.
- Conductors 542a and 542b are arranged apart from each other on oxide 530b, and conductors 542a and 542b are arranged on oxide 530b and between conductors 542a and 542b. It has an insulator 580 that overlaps with an opening, an insulator 545 that is arranged on the bottom and side surfaces of the opening, and a conductor 560 that is arranged on the surface where the insulator 545 is formed.
- an insulator 544 is preferably arranged between oxides 530a, 530b, conductors 542a and 542b, and an insulator 580.
- the conductor 560 includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. It is preferable to have Insulator 574 is also preferably disposed over insulator 580, conductor 560, and insulator 545, as shown in FIGS. 17A and 17B.
- oxide 530a and the oxide 530b are sometimes collectively referred to as the oxide 530.
- the transistor 500 shows a structure in which two layers of the oxide 530a and the oxide 530b are stacked in a region where a channel is formed and in the vicinity thereof, the present invention is not limited to this.
- a single layer of the oxide 530b or a stacked structure of three or more layers may be provided.
- the conductor 560 has a two-layer structure in the transistor 500, the present invention is not limited to this.
- the conductor 560 may have a single layer structure or a laminated structure of three or more layers.
- the transistor 500 illustrated in FIGS. 16 and 17A is an example, and the structure is not limited to that, and an appropriate transistor may be used depending on the circuit structure, the driving method, and the like.
- the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as source and drain electrodes, respectively.
- the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b.
- the placement of conductor 560 , conductor 542 a and conductor 542 b is selected in a self-aligned manner with respect to openings in insulator 580 . That is, in the transistor 500, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, so that the area occupied by the transistor 500 can be reduced. As a result, miniaturization and high integration of the semiconductor device can be achieved.
- the conductor 560 is formed in a region between the conductors 542a and 542b in a self-aligning manner, the conductor 560 does not have a region overlapping the conductors 542a or 542b. Accordingly, parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Therefore, the switching speed of the transistor 500 can be improved and high frequency characteristics can be obtained.
- the conductor 560 may function as a first gate (also called top gate) electrode.
- the conductor 503 functions as a second gate (also referred to as a bottom gate) electrode.
- the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560 .
- the threshold voltage of the transistor 500 can be made higher than 0 V and the off current can be reduced. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when no potential is applied.
- the conductor 503 is arranged so as to overlap with the oxide 530 and the conductor 560 .
- a potential is applied to the conductor 560 and the conductor 503
- an electric field generated from the conductor 560 is connected to an electric field generated from the conductor 503, and the channel formation region formed in the oxide 530 is covered. can be done.
- a transistor structure in which a channel formation region is electrically surrounded by an electric field of a pair of gate electrodes is referred to as a surrounded channel (S-channel) structure.
- the surrounded channel (S-channel) configuration means that the side surfaces and the periphery of the oxide 530 in contact with the conductors 542a and 542b functioning as the source and drain electrodes are the same as the channel formation region. It has the characteristic of being a type.
- the side surface and the periphery of the oxide 530 that are in contact with the conductors 542a and 542b are in contact with the insulator 544, they can be i-type like the channel formation region.
- type I can be treated in the same way as high-purity intrinsic, which will be described later.
- the S-channel configuration disclosed herein is different from the Fin configuration and the planar configuration. By adopting the S-channel structure, the transistor can be improved in resistance to the short channel effect, in other words, a transistor in which the short channel effect is less likely to occur.
- the conductor 503 has a structure similar to that of the conductor 518.
- a conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and a conductor 503b is further formed inside.
- the conductor 503 may be provided as a single layer or a laminated structure of three or more layers.
- the conductor 503a it is preferable to use a conductive material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (thus, the above impurities are difficult to permeate).
- a conductive material that has a function of suppressing the diffusion of oxygen eg, at least one of oxygen atoms, oxygen molecules, and the like
- the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of either one or all of the impurities or oxygen.
- the conductor 503a since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 503b from being oxidized and reducing its conductivity.
- the conductor 503b preferably uses a highly conductive material containing tungsten, copper, or aluminum as its main component. Note that although the conductor 503 is illustrated as a laminate of the conductor 503a and the conductor 503b in this embodiment mode, the conductor 503 may have a single-layer structure.
- the insulators 520, 522, and 524 function as second gate insulating films.
- the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the stoichiometric composition.
- the oxygen is easily released from the film by heating.
- the oxygen released by heating is sometimes referred to as "excess oxygen.”
- a region containing excess oxygen also referred to as an “excess oxygen region” is preferably formed in the insulator 524 .
- V OH oxygen vacancies
- the vacancies (hereinafter sometimes referred to as V OH ) function as donors, and electrons, which are carriers, are generated in some cases.
- part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron that is a carrier. Therefore, a transistor including an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics.
- hydrogen in an oxide semiconductor easily moves due to stress such as heat and an electric field; therefore, when a large amount of hydrogen is contained in the oxide semiconductor, the reliability of the transistor might be deteriorated.
- an oxide material from which part of oxygen is released by heating is preferably used as the insulator having the excess oxygen region.
- the oxide that desorbs oxygen by heating means that the desorption amount of oxygen in terms of oxygen atoms is 1.0 ⁇ 10 18 atoms/cm 3 or more, preferably 1, in TDS (Thermal Desorption Spectroscopy) analysis. 0 ⁇ 10 19 atoms/cm 3 or more, more preferably 2.0 ⁇ 10 19 atoms/cm 3 or more, or 3.0 ⁇ 10 20 atoms/cm 3 or more.
- the surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.
- one or more of heat treatment, microwave treatment, and RF treatment may be performed while the insulator having the excess oxygen region and the oxide 530 are in contact with each other.
- water or hydrogen in the oxide 530 can be removed.
- a reaction of breaking the bond of VoH occurs, in other words, a reaction of “V 2 O H ⁇ Vo+H” occurs to dehydrogenate the oxide 530 .
- Part of the hydrogen generated at this time is combined with oxygen to form H 2 O and removed from the oxide 530 or an insulator near the oxide 530 in some cases.
- some of the hydrogen may be gettered by the conductor 542 .
- the microwave treatment for example, it is preferable to use an apparatus having a power supply for generating high-density plasma or an apparatus having a power supply for applying RF to the substrate side.
- a gas containing oxygen and using high-density plasma high-density oxygen radicals can be generated.
- the oxygen radicals generated by the high-density plasma can be generated.
- the microwave treatment may be performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher.
- oxygen and argon are used as gases to be introduced into the apparatus for microwave treatment, and the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is 50% or less, preferably 10% or more and 30%. % or less.
- heat treatment is preferably performed with the surface of the oxide 530 exposed during the manufacturing process of the transistor 500 .
- the heat treatment may be performed at, for example, 100° C. to 450° C., more preferably 350° C. to 400° C.
- the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
- heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxide 530 to reduce oxygen vacancies (V 0 ).
- the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen after the heat treatment is performed in a nitrogen gas or inert gas atmosphere. good.
- heat treatment may be continuously performed in a nitrogen gas or inert gas atmosphere.
- oxygen vacancies in the oxide 530 can be repaired by supplied oxygen, in other words, a reaction of “Vo+O ⁇ null” can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530, so that the hydrogen can be removed as H 2 O (dehydrated). Accordingly, hydrogen remaining in the oxide 530 can be suppressed from being recombined with oxygen vacancies to form VOH .
- the insulator 522 when the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is less permeable).
- oxygen eg, oxygen atoms, oxygen molecules, etc.
- the insulator 522 has a function of suppressing diffusion of oxygen, impurities, and the like, oxygen contained in the oxide 530 does not diffuse to the insulator 520 side, which is preferable. Further, the conductor 503 can be prevented from reacting with oxygen contained in the insulator 524, the oxide 530, or the like.
- Insulator 522 is, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or It is preferable to use an insulator containing a so-called high-k material such as (Ba, Sr)TiO 3 (BST) in a single layer or stacked layers. As transistors are miniaturized and highly integrated, thinning of the gate insulating film may cause problems such as leakage current. By using a high-k material for the insulator functioning as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
- a so-called high-k material such as (Ba, Sr)TiO 3 (BST)
- an insulator containing an oxide of one or both of aluminum and hafnium which is an insulating material that has a function of suppressing the diffusion of impurities and oxygen (the oxygen is less likely to permeate).
- the insulator containing oxides of one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
- the insulator 522 is formed using such a material, the insulator 522 suppresses release of oxygen from the oxide 530 or entry of impurities such as hydrogen from the periphery of the transistor 500 into the oxide 530. act as a layer.
- aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
- these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
- the insulator 520 is preferably thermally stable.
- silicon oxide and silicon oxynitride are preferred because they are thermally stable.
- the insulator 520 having a stacked structure that is thermally stable and has a high relative dielectric constant can be obtained.
- the insulator 520, the insulator 522, and the insulator 524 are illustrated as the second gate insulating film having a stacked-layer structure of three layers.
- the insulating film may have a single layer, two layers, or a laminated structure of four or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may be used.
- the transistor 500 uses a metal oxide functioning as an oxide semiconductor for the oxide 530 including the channel formation region.
- a metal oxide functioning as an oxide semiconductor for the oxide 530 including the channel formation region.
- In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or the like) may be used.
- a metal oxide that functions as an oxide semiconductor may be formed by a sputtering method or by an ALD (Atomic Layer Deposition) method. Note that a metal oxide functioning as an oxide semiconductor will be described in detail in other embodiments.
- the oxide 530 can suppress diffusion of impurities from a component formed below the oxide 530a to the oxide 530b.
- the oxide 530 preferably has a laminated structure of a plurality of oxide layers with different atomic ratios of metal atoms.
- the atomic number ratio of the element M among the constituent elements is greater than the atomic number ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. is preferred.
- the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b.
- the atomic ratio of In to the element M in the metal oxide used for the oxide 530b is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.
- the energy of the conduction band bottom of the oxide 530a be higher than the energy of the conduction band bottom of the oxide 530b.
- the electron affinity of the oxide 530a is preferably smaller than the electron affinity of the oxide 530b.
- the energy level at the bottom of the conduction band changes gently.
- the energy level at the bottom of the conduction band at the junction of the oxide 530a and the oxide 530b continuously changes or continuously joins.
- the oxide 530a and the oxide 530b have a common element (as a main component) other than oxygen, a mixed layer with a low defect level density can be formed.
- the oxide 530b is an In--Ga--Zn oxide
- an In--Ga--Zn oxide, a Ga--Zn oxide, gallium oxide, or the like may be used as the oxide 530a.
- the main route of carriers is the oxide 530b.
- the oxide 530a has the above structure, the defect level density at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.
- a conductor 542a and a conductor 542b functioning as a source electrode and a drain electrode are provided over the oxide 530b.
- Conductors 542a and 542b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. , iridium, strontium, and lanthanum, an alloy containing the above-described metal elements as a component, or an alloy in which the above-described metal elements are combined.
- tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, and the like are used. is preferred.
- tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even after absorbing oxygen.
- a metal nitride film such as tantalum nitride is preferred because of its barrier properties against hydrogen or oxygen.
- the conductor 542a and the conductor 542b are shown as a single-layer structure, but they may be laminated with two or more layers.
- a tantalum nitride film and a tungsten film are preferably stacked.
- a titanium film and an aluminum film may be stacked.
- a two-layer structure in which an aluminum film is stacked over a tungsten film, a two-layer structure in which a copper film is stacked over a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked over a titanium film, a two-layer structure in which a copper film is stacked over a titanium film, A two-layer structure in which copper films are laminated may be used.
- a three-layer structure in which a titanium film or a titanium nitride film is laminated, an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is formed thereon, a molybdenum film or a
- a three-layer structure including a molybdenum nitride film, an aluminum film or a copper film laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film formed thereon.
- a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.
- regions 543a and 543b may be formed as low-resistance regions at and near the interface between the oxide 530 and the conductor 542a (conductor 542b).
- the region 543a functions as one of the source region and the drain region
- the region 543b functions as the other of the source region and the drain region.
- a channel formation region is formed in a region sandwiched between the regions 543a and 543b.
- the oxygen concentration of the region 543a may be reduced.
- a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the component of the oxide 530 is formed in the region 543a (region 543b). In such a case, the carrier density of the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.
- the insulator 544 is provided so as to cover the conductors 542a and 542b and suppress oxidation of the conductors 542a and 542b. At this time, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and be in contact with the insulator 524 .
- a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, or the like is used.
- tungsten titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, or the like
- silicon nitride oxide, silicon nitride, or the like can be used as the insulator 544 .
- an insulator containing one or both oxides of aluminum and hafnium such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate)
- hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is less likely to be crystallized in heat treatment in a later step.
- the conductors 542a and 542b are made of a material having oxidation resistance or a material whose conductivity does not significantly decrease even when oxygen is absorbed, the insulator 544 is not an essential component. It may be appropriately designed depending on the required transistor characteristics.
- the insulator 544 can suppress diffusion of water and impurities such as hydrogen contained in the insulator 580 into the oxide 530b. In addition, oxidation of the conductor 542 due to excess oxygen in the insulator 580 can be suppressed.
- the insulator 545 functions as a first gate insulating film.
- the insulator 545 is preferably formed using an insulator that contains excess oxygen and from which oxygen is released by heating, similarly to the insulator 524 described above.
- silicon oxide with excess oxygen silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and vacancies can be used.
- silicon oxide and silicon oxynitride are preferable because they are stable against heat.
- the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced.
- the thickness of the insulator 545 is preferably 1 nm or more and 20 nm or less.
- a metal oxide may be provided between the insulator 545 and the conductor 560 in order to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530 .
- the metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560 .
- diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. That is, reduction in the amount of excess oxygen supplied to the oxide 530 can be suppressed.
- oxidation of the conductor 560 due to excess oxygen can be suppressed.
- a material that can be used for the insulator 544 may be used.
- the insulator 545 may have a stacked structure similarly to the second gate insulating film. As transistors are miniaturized and highly integrated, thinning of the gate insulating film may cause problems such as leakage current.
- By forming a laminated structure with a material that is relatively stable it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Moreover, it is possible to obtain a laminated structure that is thermally stable and has a high dielectric constant.
- the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 17A and 17B, it may have a single-layer structure or a laminated structure of three or more layers.
- the conductor 560a has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N 2 O, NO, NO 2 ), and copper atoms. Materials are preferably used. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used. Since the conductor 560a has a function of suppressing diffusion of oxygen, oxygen contained in the insulator 545 can suppress oxidation of the conductor 560b and a decrease in conductivity.
- impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N 2 O, NO, NO 2 ), and copper atoms. Materials are preferably used. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used. Since the conductor 560a has
- the conductive material having a function of suppressing diffusion of oxygen tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example.
- an oxide semiconductor that can be used for the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b by a sputtering method, the electric resistance value of the conductor 560a can be lowered to make the conductor 560a a conductor. This can be called an OC (Oxide Conductor) electrode.
- a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 560b.
- the conductor 560b since the conductor 560b also functions as a wiring, a conductor with high conductivity is preferably used.
- a conductive material whose main component is tungsten, copper, or aluminum can be used.
- the conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.
- the insulator 580 is provided over the conductors 542a and 542b with the insulator 544 interposed therebetween.
- Insulator 580 preferably has excess oxygen regions.
- the insulator 580 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or oxide with vacancies. It preferably contains silicon, resin, or the like.
- silicon oxide and silicon oxynitride are preferable because they are thermally stable.
- silicon oxide and silicon oxide having vacancies are preferable because an excess oxygen region can be easily formed in a later step.
- the insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 . Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably low.
- the opening of the insulator 580 is formed so as to overlap a region between the conductors 542a and 542b.
- the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b.
- the conductor 560 can have a shape with a high aspect ratio.
- the conductor 560 since the conductor 560 is embedded in the opening of the insulator 580, the conductor 560 can be formed without collapsing during the process even if the conductor 560 has a high aspect ratio. can be done.
- the insulator 574 is preferably provided in contact with the top surface of the insulator 580 , the top surface of the conductor 560 , and the top surface of the insulator 545 .
- excess oxygen regions can be provided in the insulators 545 and 580 . Accordingly, oxygen can be supplied into the oxide 530 from the excess oxygen region.
- the insulator 574 can be a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like. can be done.
- aluminum oxide has a high barrier property, and even a thin film of 0.5 nm or more and 3.0 nm or less can suppress the diffusion of hydrogen and nitrogen. Therefore, the aluminum oxide film formed by the sputtering method can function not only as an oxygen supply source but also as a barrier film against impurities such as hydrogen.
- An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574 .
- the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.
- conductors 540 a and 540 b are arranged in openings formed in the insulators 581 , 574 , 580 , and 544 .
- the conductor 540a and the conductor 540b are provided to face each other with the conductor 560 interposed therebetween.
- the conductors 540a and 540b have the same structure as the conductors 546 and 548, which will be described later.
- An insulator 582 is provided on the insulator 581 .
- the insulator 582 preferably uses a substance having a barrier property against oxygen, hydrogen, or the like. Therefore, a material similar to that of the insulator 514 can be used for the insulator 582 .
- the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.
- aluminum oxide has a high shielding effect that prevents both oxygen and impurities such as hydrogen and moisture, which are factors that change the electrical characteristics of transistors, from penetrating through the film. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide forming the transistor 500 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 500 .
- An insulator 586 is provided on the insulator 582 .
- a material similar to that of the insulator 320 can be used for the insulator 586 .
- parasitic capacitance generated between wirings can be reduced.
- a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586 .
- the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586 include the conductor 546, the conductor 548, and the like. is embedded.
- the conductors 546 and 548 function as plugs or wirings that connect to the capacitor 600, the transistor 500, or the transistor 550.
- the conductors 546 and 548 can be formed using a material similar to that of the conductors 328 and 330 .
- an opening may be formed so as to surround the transistor 500, and an insulator with a high barrier property against hydrogen or water may be formed to cover the opening.
- an insulator with a high barrier property against hydrogen or water By wrapping the transistor 500 with the above insulator with a high barrier property, entry of moisture and hydrogen from the outside can be prevented.
- the plurality of transistors 500 may be wrapped together with an insulator having a high barrier property against hydrogen or water. Note that in the case where the opening is formed so as to surround the transistor 500, for example, the opening is formed to reach the insulator 522 or the insulator 514, and the above insulator with a high barrier property is provided so as to be in contact with the insulator 522 or the insulator 514.
- the transistor 500 it is preferable to form the transistor 500 because it can also be part of the manufacturing process of the transistor 500 .
- a material similar to that of the insulator 522 or the insulator 514 may be used, for example.
- a capacitor 600 is provided above the transistor 500 .
- a capacitor 600 has a conductor 610 , a conductor 620 , and an insulator 630 .
- a conductor 612 may be provided over the conductor 546 and the conductor 548 .
- the conductor 612 functions as a plug or wiring connected to the transistor 500 .
- Conductor 610 functions as an electrode of capacitor 600 . Note that the conductor 612 and the conductor 610 can be formed at the same time.
- the conductors 612 and 610 are metal films containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or metal nitride films containing any of the above elements as components. (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. Conductive materials such as indium tin oxide can also be applied.
- the conductor 612 and the conductor 610 have a single-layer structure, but are not limited to this structure, and may have a laminated structure of two or more layers. For example, between a conductor with a barrier property and a conductor with high conductivity, a conductor with a barrier property and a conductor with high adhesion to the conductor with high conductivity may be formed.
- a conductor 620 is provided so as to overlap with the conductor 610 with an insulator 630 interposed therebetween.
- the conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten.
- a low-resistance metal material such as Cu (copper) or Al (aluminum) may be used.
- An insulator 640 is provided on the conductor 620 and the insulator 630 .
- the insulator 640 can be provided using a material similar to that of the insulator 320 .
- the insulator 640 may function as a planarizing film that covers the uneven shape thereunder.
- Substrates that can be used for the semiconductor device of one embodiment of the present invention include a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, and a metal substrate (for example, a stainless steel substrate, a substrate having a stainless steel foil, and a tungsten substrate). , a substrate having a tungsten foil), a semiconductor substrate (eg, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, or a compound semiconductor substrate), an SOI (Silicon on Insulator) substrate, and the like. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment mode may be used.
- glass substrates include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, soda lime glass, and the like. In addition, crystallized glass or the like can be used.
- a flexible substrate, a laminated film, paper containing a fibrous material, or a base film can be used as the substrate.
- flexible substrates, laminated films, substrate films, etc. are as follows.
- plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE).
- PET polyethylene terephthalate
- PEN polyethylene naphthalate
- PES polyethersulfone
- PTFE polytetrafluoroethylene
- Another example is a synthetic resin such as acrylic.
- examples include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride.
- examples include polyamide, polyimide, aramid resin, epoxy resin, inorganic deposition film, or paper.
- a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a small-sized transistor with little variation in characteristics, size, shape, or the like, high current capability, and small size can be manufactured.
- a circuit is formed using such transistors, low power consumption of the circuit or high integration of the circuit can be achieved.
- a flexible substrate may be used as the substrate, and transistors, resistors, and/or capacitors may be formed directly over the flexible substrate.
- a release layer may be provided between the substrate and the transistors, resistors, and/or capacitors, and the like. The peeling layer can be used for separating from the substrate and transferring to another substrate after partially or entirely completing the semiconductor device on it. At that time, transistors, resistors, and/or capacitors can be transferred to a substrate having poor heat resistance, a flexible substrate, or the like.
- peeling layer for example, a laminated structure of an inorganic film including a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed over a substrate, a silicon film containing hydrogen, or the like is used. be able to.
- a semiconductor device may be formed over a substrate and then transferred to another substrate.
- substrates on which semiconductor devices are transferred include paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, and the like.
- the transistor 550 illustrated in FIG. 16 is an example, and the structure is not limited to that, and an appropriate transistor may be used depending on the circuit structure, the driving method, and the like.
- the semiconductor device is a unipolar circuit including only OS transistors (meaning a transistor with the same polarity as n-channel transistors only)
- a transistor 550 has a structure similar to that of the transistor 500 as shown in FIG. configuration.
- the backup circuit 10M (the data holding circuit 20M or the memory cell 30M) arranged over the circuit 10S (the circuit 20S or the circuit 30S) described in Embodiment 1.
- a circuit 10S (circuit 20S or circuit 30S) and a backup circuit 10M (data holding circuit 20M or memory cell 30M) are formed using an oxide semiconductor layer in which a channel forming region is formed.
- 530 can be a transistor 550 (OS transistor).
- the circuit 10S (the circuit 20S or the circuit 30S) is composed of Si transistors
- the silicon substrate on which the Si transistors are provided lacks flexibility, so there is a risk of damage due to forces such as bending and twisting.
- the semiconductor device 101 can be freely deformed as follows. Moreover, the possibility that the semiconductor device 101 is destroyed by impact can be reduced. Therefore, an electronic device including the semiconductor device 101 can be an electronic device that is excellent in design and can be less likely to be damaged by an impact.
- ⁇ Display system configuration example> 20A to 20C are diagrams illustrating a configuration example of a display system that is one embodiment of the present invention.
- the display system that is one aspect of the present invention includes the electronic device 100 described in Embodiment 1 and the like, and a head-mounted electronic device 100X (HMD (also referred to as Head Mounted Display)).
- HMD head Mounted Display
- Each of the electronic device 100 and the electronic device 100X has a wireless communication means, and the electronic device 100X has a display region with a higher pixel density (also referred to as definition) than the electronic device 100. , has a function of displaying the screen of the electronic device 100 or a part of the screen on the electronic device 100X using the wireless communication means.
- a display system has multiple electronic devices.
- the plurality of electronic devices exchange data using wireless communication means, and process data such as up-conversion or down-conversion to process a portion of the image data displayed on the screen of one of the electronic devices. can be processed and displayed on the other electronic device.
- process data such as up-conversion or down-conversion to process a portion of the image data displayed on the screen of one of the electronic devices.
- process data such as up-conversion or down-conversion
- the electronic device 100 illustrated in FIG. 20A has a display 102, a housing 111, a communication section 106, a semiconductor device 101, a battery 104, a sensor 105, and a band 113.
- FIG. 20A shows the user's right hand 70R and the user's left hand 70L.
- the electronic device 100X also includes a housing 81, a control unit 71, a display 72, a battery 74, sensors 75A and 75B (sometimes referred to as sensor 75), a communication unit 76, and a mounting unit .
- wireless communication between the electronic device 100 and the electronic device 100X can be performed between the communication unit 106 and the communication unit 76 as shown in FIG. 20A.
- the communication unit 106 has a function of transmitting information to the electronic device 100X according to an operation on the electronic device 100.
- FIG. The communication unit 76 also has a function of transmitting information to the electronic device 100 according to an operation to the electronic device 100X.
- the electronic device 100X shown in FIG. 20A has one or both of a function of displaying augmented reality (AR) content and a function of displaying virtual reality (VR) content.
- AR augmented reality
- VR virtual reality
- the electronic device 100X may have a function of displaying content of alternative reality (SR) or mixed reality (MR). Since the electronic device 100X has a function of displaying content such as AR, VR, SR, and MR, it is possible to enhance the sense of immersion for the user.
- SR alternative reality
- MR mixed reality
- the sensor 75A of the electronic device 100X has a function as a camera section that acquires information on the outside of the electronic device 100X.
- FIG. 20A illustrates how two sensors 75A are arranged outside the housing 81 to acquire information about the user's surroundings.
- a plurality of sensors 75A as a camera unit that acquires information about the user's surroundings in this way, information that cannot be detected by the naked eye can be obtained through the sensors 75A, compared to grasping information about the user's surroundings with the naked eye. can be obtained. Therefore, the amount of information that the user can obtain can be increased.
- the data acquired by the sensor 75A can be output to the display 72 or the display 102 of the electronic device 100.
- the sensor 75B of the electronic device 100X has a function as a camera section that acquires information on the user side of the electronic device 100X.
- FIG. 20A illustrates a state in which two sensors 75A are arranged inside the housing 81 so as to capture images of the user's eyes, and information around the user's eyes is acquired.
- a plurality of sensors 75A as camera units for acquiring information on the eyes of the user in this way, it is possible to perform eye tracking of the user. Therefore, on the display 72, it is possible to perform display according to the line of sight of the user.
- the user can wear the electronic device 100X on the head using the mounting section 82 of the electronic device 100X.
- the shape is illustrated as a temple of spectacles (also referred to as a joint, a temple, etc.), but the shape is not limited to this.
- the mounting portion 82 may be worn by the user, and may be, for example, a helmet-type or band-type shape.
- a distance measuring sensor capable of measuring the distance of an object
- the sensors 75A and 75B are one aspect of the detection section.
- the detection unit for example, an image sensor or a distance image sensor such as a lidar (LIDAR: Light Detection and Ranging) can be used.
- LIDAR Light Detection and Ranging
- the user can operate an image (also called a data object) displayed on the display 72 of the electronic device 100X like an actual object by intuitive gesture operations. For example, it is possible to pinch an image that is displayed as if it is floating on a plate. You can also throw the pinched image like a frisbee to erase the image. You can also move the pinched image up, down, left, or right. Further, by moving the pinched image back and forth, the image can be enlarged or reduced. Also, the pinched image can be turned upside down. At this time, the axis of rotation can be vertical, horizontal, or oblique. Also, by pinching and pulling the edge of the field of view where nothing is displayed, a plate-like image can be drawn out.
- an image also called a data object
- the image can be erased by pushing the plate-like image away from the user.
- the image can be erased by moving the hand left and right after placing the hand on the edge of the plate-shaped image.
- Such an operation of erasing an image may be switched to another image after erasing the image.
- the user may register specific information in the electronic device 100X in advance. For example, the motion of spreading the palm to the motion of connecting the thumb and index finger (the motion of forming a circle with the thumb and index finger) is registered as the first processing information, and based on the first processing information, the second processing is performed. Processing information can be executed.
- the second processing information data that the user wants to execute arbitrarily can be registered as the second processing information, for example, deleting an image, displaying a specific image, displaying a shortcut icon, or the like. can.
- a plurality of detection units may be provided in the electronic device or electronic device in order to perform gesture operations using multiple movements, such as actions using both hands, with high accuracy. preferable. As a result, it is possible to detect the three-dimensional position information of a plurality of objects with higher accuracy, so that input by complicated gesture operations becomes possible.
- the user can operate an image (also called a data object) displayed on the display 72 of the electronic device 100X like an actual object, for example, by gesture operation using both hands. For example, it is possible to pinch two points (for example, top and bottom, left and right, or diagonally) of an image that is displayed as if it were floating on a plate. Also, the image can be enlarged by stretching the image while pinching the image with both hands. Also, the image can be reduced by pinching the image with both hands and shrinking the image. In addition, the image can be erased by pinching the image with both hands or placing hands on both ends of the image and then squeezing the image with both hands.
- an image also called a data object displayed on the display 72 of the electronic device 100X like an actual object, for example, by gesture operation using both hands. For example, it is possible to pinch two points (for example, top and bottom, left and right, or diagonally) of an image that is displayed as if it were floating on a plate.
- the image can be enlarged by stretching the
- the image can be erased by pinching the upper side of the image with both hands and tearing the image left and right. Also, the image can be erased by pinching the image with both hands and bending the image. It is also possible to pinch an image with one hand and perform gesture operations (tap, swipe, pinch-in, pinch-out, etc.) on the image with the other hand. Further, as described above, the user can register in advance a specific action and information on processing associated with the action in the electronic device 100X.
- the electronic device 100 and the electronic device 100X can be network-connected. Accordingly, it is possible to use the electronic device 100 and the electronic device 100X independently as communication tools. For example, an image or part of an image displayed on the electronic device 100X worn by the first user can be displayed on the electronic device 100X worn by the second user. Alternatively, the image or part of the image displayed on the electronic device 100X worn by the first user can be displayed on the electronic device 100 owned by the second user.
- Such a display system allows a plurality of users to share the same image data, thereby enhancing communication.
- a highly convenient display system or an operation method of the display system can be provided.
- processing that can be executed by electronic device 100 and electronic device 100X described in the present embodiment is an example, and various processing is executed according to application software installed in electronic device 100 or electronic device 100X. sell.
- FIGS. 20B, 21A, and 21B Next, an electronic device and a display system of one embodiment of the present invention are described with reference to FIGS. 20B, 21A, and 21B.
- FIG. 20B is a diagram illustrating an electronic device and a display system of one embodiment of the present invention.
- electronic device 100 has at least display 102 and communication unit 106
- electronic device 100X has display 72 and communication unit 76 .
- the electronic device 100 has a display 102, a communication unit 106, a semiconductor device 101, a battery 104, and a sensor 105.
- the electronic device 100X has a display 72, a communication section 76, a control section 71, a battery 74, and a sensor 75.
- the electronic device 100 and the electronic device 100X each have the same function, but the configuration is not limited to this.
- the electronic device 100 and the electronic device 100X may have different functions.
- the electronic device 100 has a camera section 107 (also referred to as a detection section) and a communication section 108 in addition to the configuration shown in FIG. 21A.
- the electronic device 100X has a camera section 77 and a headphone section 78 in addition to the configuration shown in FIG. 21A.
- Camera unit 77 and camera unit 107 may have an imaging unit such as an image sensor.
- a plurality of cameras may be provided so as to be able to deal with a plurality of angles of view such as telephoto and wide angle.
- the communication unit 108 may have a function of performing communication with a function different from that of the communication unit 106 .
- the communication unit 106 has a function of communicating with the communication unit 76, and the communication unit 108 is a third generation mobile communication system (3G), a fourth generation mobile communication system (4G), or a fifth generation mobile communication system. It is only necessary to have a function capable of voice communication using a communication system (5G) or a communication means capable of electronic payment.
- 3G third generation mobile communication system
- 4G fourth generation mobile communication system
- 5G communication system
- 5G communication means capable of electronic payment.
- the display 72 shown in FIGS. 20A, 20B, 21A, and 21B preferably has a higher resolution than the display 102.
- display 102 may have resolutions such as HD (1280 ⁇ 720 pixels), FHD (1920 ⁇ 1080 pixels), and WQHD (2560 ⁇ 1440 pixels).
- the display 72 preferably has a very high resolution such as WQXGA (2560 ⁇ 1600 pixels), 4K2K (3840 ⁇ 2160 pixels), or 8K4K (7680 ⁇ 4320 pixels). In particular, it is preferable to set the resolution to 4K2K, 8K4K, or higher.
- the display 72 preferably has a higher pixel density (definition) than the display 102 .
- the display 102 may have a pixel density of 100 ppi to less than 1000 ppi, preferably 300 ppi to 800 ppi.
- the display 72 can have a pixel density of 1000 ppi to 10000 ppi, preferably 2000 ppi to 6000 ppi, more preferably 3000 ppi to 5000 ppi.
- the screen ratio (aspect ratio) of the display 102 and the display 72 is not particularly limited.
- the display 102 and the display 72 can correspond to various screen ratios such as 1:1 (square), 3:4, 16:9, and 16:10.
- the display 102 is preferably formed on a glass substrate, and the display 72 is preferably formed on a silicon substrate.
- the display 102 By forming the display 102 over a glass substrate, manufacturing costs can be reduced.
- the display 102 when the display 102 is formed on a glass substrate, it may be difficult to increase the pixel density of the display 102 (typically 1000 ppi or more) due to manufacturing equipment. Therefore, in the electronic device and the display system of one embodiment of the present invention, by forming the display 72 over a silicon substrate, the pixel density of the display 72 can be increased (typically, 1000 ppi or more). In other words, the display 72 can supplement and display an image with a definition that the display 102 cannot handle.
- a display system of one aspect of the present invention has two electronic devices with different resolutions or different pixel densities.
- image data displayable by one electronic device into image data suitable for the other electronic device, part or all of the image data may be compressed or decompressed.
- the user By increasing the resolution or definition of the display 72, the user cannot perceive the pixels (such as lines that may occur between the pixels cannot be seen), thereby increasing the sense of immersion, presence, and depth. can feel.
- the electronic device 100 shown in FIG. 20A has a period during which the display does not display, and functions as input/output means (eg, controller) of the electronic device 100X during this period.
- the usage period of the battery 104 included in the electronic device 100 can be extended. That is, the display system which is one embodiment of the present invention can save power.
- the battery 104 for example, a lithium ion secondary battery can be used.
- FIGS. 20A, 20B, 21A, and 21B are described below.
- the display 102 and the display 72 each have a display function.
- the display 102 and the display 72 for example, one or a plurality of devices selected from liquid crystal display devices, light emitting devices including organic EL, and light emitting devices including light emitting diodes such as micro LEDs can be used. Considering productivity and luminous efficiency, it is preferable to use a light-emitting device including an organic EL as the display 102 and the display 72 .
- the communication unit 106 and the communication unit 76 each have a function of communicating wirelessly or by wire. It is preferable that the communication units 106 and 76 have a function of communicating wirelessly, because the number of components such as cables for connection can be omitted.
- Communication means (communication methods) between the communication unit 106 and the communication unit 76 include, for example, the Internet, which is the basis of the World Wide Web (WWW), intranet, extranet, PAN (Personal Area Network), LAN (Local Area Network). ), CAN (Campus Area Network), MAN (Metropolitan Area Network), WAN (Wide Area Network), GAN (Global Area Network), and other computer networks to communicate with each other.
- WWW World Wide Web
- intranet intranet
- extranet extranet
- PAN Personal Area Network
- LAN Local Area Network
- CAN Campus Area Network
- MAN Micropolitan Area Network
- WAN Wide Area Network
- GAN Global Area Network
- LTE Long Term Evolution
- GSM Global System for Mobile Communication: registered trademark
- EDGE Enhanced Data Rates for GSM Evolution
- CDMA2000 Codes 0 Division 0
- W-CDMA registered trademark
- IEEE specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and ZigBee (registered trademark).
- the semiconductor device 101 and the control unit 71 each have a function of controlling the display.
- the semiconductor device 101 and the control unit 71 have, for example, a CPU, a GPU, and a memory.
- Arithmetic circuits such as the CPU and GPU can perform image processing, for example, can perform amp-conversion processing or down-conversion processing of image data. Thereby, image data with low resolution can be up-converted or image data with high resolution can be down-converted in accordance with the resolution of the display, and an image with high display quality can be displayed on the display.
- Battery 104 and battery 74 each have a function of supplying power to the display.
- a primary battery or a secondary battery can be used.
- a lithium ion secondary battery can be used suitably, for example.
- Each of the sensors 105 and 75 has a function of acquiring one or more of the user's visual, auditory, tactile, gustatory, and olfactory information. More specifically, the sensor 105 can detect force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, light, magnetism, temperature, sound, time, electric field, current, voltage, power, radiation, humidity, It has the ability to measure tilt, vibration, odor, and infrared.
- the sensor 75 preferably has a function of measuring electroencephalograms.
- it may have a plurality of electrodes that contact the head and have a mechanism for measuring electroencephalograms from weak currents flowing through the electrodes. Since the sensor 75 has the function of measuring brain waves, the image of the display 102 or part of the image of the display 102 can be displayed on the display 72 as the user thinks. In this case, since the user does not need to use both hands to operate the electronic device, the user can perform input operations and the like without holding anything in both hands (both hands are free).
- FIG. 22A shows the user 130 performing a gesture operation while wearing the glasses-type electronic device 100X.
- the display of the electronic device 100 is turned off, the power consumption of the electronic device 100 can be suppressed.
- the electronic device 100 is worn on the arm of the user 130, the user 130 can operate the display system with both hands free.
- the operation of the display system is information obtained by the sensor 75A on the electronic device 100X side, or information based on the trajectory of the arm movement obtained by applying an acceleration sensor as the sensor 105 provided in the electronic device 100. , can be used.
- FIG. 22B shows an example of the image 140 that appears in the field of view of the user 130 in the room shown in FIG. 22A.
- image information 141 is shown superimposed on an image of the actual indoor scenery such as the floor, walls, and doors.
- image information 141 is part of an image displayed on the display of electronic device 100 .
- the user 130 can also operate the electronic device 100 paired with the electronic device 100X while wearing the electronic device 100X.
- the electronic device 100X recognizes this action as a gesture operation, and changes the position of the image information 141. do.
- the image information 141 can change its position following the movement of the left hand 130L, as shown in FIG. 22B. At this time, not only can the image information 141 be moved left and right, up and down, and back and forth, but also the image information 141 can be rotated according to the movement of the left hand 130L.
- FIG. 22C shows a state in which the user 130 is making a gesture motion, which is different from that shown in FIG. 22A.
- the electronic device 100 with the display turned off is in the same manner as described above.
- FIG. 22D shows the image 140 that appears in the field of view of the user 130 in the room shown in FIG. 22C.
- the image information 141 can be discarded by the user 130 performing the motion of grasping the space where the image information 141 is shown and then performing the motion of throwing the object like throwing a frisbee. At this time, the image information 141 moves away from the user 130 and appears to disappear at a certain point, or is pushed out of the field of view. In this manner, the content image displayed within the field of view can be discarded (closed) by the user's 130 gesture operation.
- the electronic device and display system of one embodiment of the present invention can be operated with new operation methods and operation methods.
- FIG. 23 is a flowchart of a method of operating the display system.
- step S01 the operation is started. At this time, it is assumed that the electronic device 100 is in an activated state (operable state) and the electronic device 100X is in a power-on state.
- step S02 the electronic device 100X is attached.
- the electronic device 100X recognizes that it is attached, and the system starts up.
- step S02 for example, when the electronic device 100X is in the form of goggles, the image of the front camera may be provided to the user, or the image of other content may be displayed.
- step S03 pairing between the electronic device 100 and the electronic device 100X is performed.
- bidirectional data can be exchanged between the electronic device 100 and the electronic device 100X.
- step S04 the first image displayed on the display 102 of the electronic device 100 is displayed on the display of the electronic device 100X. Thereby, the user can see information displayed on the electronic device 100X without looking at the screen of the electronic device 100.
- FIG. 1 the first image displayed on the display 102 of the electronic device 100 is displayed on the display of the electronic device 100X.
- the first image is not displayed as it is, but is displayed on the display of the electronic device 100X so as to have an optimum size. Moreover, it is preferable to display a second image obtained by performing image processing such as up-conversion or down-conversion on the first image on the electronic device 100X.
- step S05 information is transmitted from the electronic device 100X to the electronic device 100.
- the information includes a code indicating that display of the first image is completed.
- step S06 the electronic device 100 turns off the display 102 based on the received information.
- the electronic device 100 keeps the touch sensor of the display 102 active.
- the display 102 of the electronic device 100 functions as input means (touch pad) and the like.
- step S07 the electronic device 100X detects a gesture motion by the user with the detection unit of the electronic device 100X, and acquires gesture information corresponding to the gesture motion.
- step S08 the electronic device 100X executes various processes based on the gesture information. For example, image processing can be performed on image information displayed on the display of the electronic device 100X, and the image information after the image processing can be displayed on the display.
- Step S10 corresponds to, for example, removing the electronic device 100X, turning off the electronic device 100 or the electronic device 100X, or canceling the pairing between the electronic device 100 and the electronic device 100X. .
- FIGS. 24A, 24B, 24C, and 24C are shown in FIGS. 24A, 24B, 24C, and 24C for the operation method that the user can experience and the image that can be presented to the user by the display system of one embodiment of the present invention. Description will be made with reference to FIG. 24D.
- FIG. 24A shows the user 130 performing a gesture operation while wearing the glasses-type electronic device 100X. At this time, since the display of the electronic device 100 is turned off, the power consumption of the electronic device 100 can be suppressed. In addition, since the electronic device 100 is worn on the arm of the user 130, the user 130 can operate the display system with both hands free.
- FIG. 24B shows an example of the image 140 that appears in the field of view of the user 130 in the room shown in FIG. 24A.
- image information 141 is shown superimposed on an image of the actual indoor scenery such as the floor, walls, and doors.
- image information 141 is part of an image displayed on the display of electronic device 100 .
- the user 130 can also operate the electronic device 100 paired with the electronic device 100X while wearing the electronic device 100X.
- the electronic device 100X recognizes this action as a gesture operation, and the image information is displayed.
- the shape of 141 is made changeable.
- the image information 141 is deformed to contract.
- image information 141 can be enlarged.
- the image information 141 can also be moved or rotated by following the movements of the left hand 130L and the right hand 130R.
- the movement of left hand 130L and right hand 130R can use information based on the locus of movement of the left and right arms on which electronic device 100 is worn.
- FIG. 24C shows a state in which the user 130 is making a gesture action, which is different from that shown in FIG. 24A.
- Electronic device 100 with the display turned off is worn on the arm of user 130 in the same manner as described above.
- FIG. 24D shows an image 140 that appears in the field of view of the user 130 in the room shown in FIG. 24C.
- the image information 141 can be discarded by the user 130 performing an action of grasping the space where the image information 141 is shown with the left hand 130L and the right hand 130R and then performing an action of opening left and right.
- the image information 141 is displayed so as to be broken left and right. In this manner, the content image displayed within the field of view can be discarded (closed) by the user's 130 gesture operation.
- the electronic device and the display system of one embodiment of the present invention can be operated with a new operation method.
- FIG. 25 is a flow chart of a method of operating the display system.
- step S11 the operation is started. At this time, it is assumed that the electronic device 100 is in an activated state (operable state) and the electronic device 100X is in a power-on state.
- step S12 the electronic device 100X is attached.
- the electronic device 100X recognizes that it is attached, and the system starts up.
- step S12 for example, when the electronic device 100X is in the form of goggles, the image of the front camera may be provided to the user, or the image of other content may be displayed.
- step S13 pairing between the electronic device 100 and the electronic device 100X is executed.
- bidirectional data can be exchanged between the electronic device 100 and the electronic device 100X.
- step S14 the first image displayed on the display 102 of the electronic device 100 is displayed on the display of the electronic device 100X. Thereby, the user can see information displayed on the electronic device 100X without looking at the screen of the electronic device 100.
- FIG. 1 the first image displayed on the display 102 of the electronic device 100 is displayed on the display of the electronic device 100X.
- the first image is not displayed as it is, but is displayed on the display of the electronic device 100X so as to have an optimum size. Moreover, it is preferable to display a second image obtained by performing image processing such as up-conversion or down-conversion on the first image on the electronic device 100X.
- step S15 information is transmitted from the electronic device 100X to the electronic device 100.
- the information includes a code indicating that display of the first image is completed.
- step S16 the electronic device 100 turns off the display 102 based on the received information.
- the electronic device 100 keeps the touch sensor of the display 102 active.
- the display 102 of the electronic device 100 functions as input means (touch pad) and the like.
- step S17 the electronic device 100X detects gesture motions by the user by means of a plurality of detection units of the electronic device 100X.
- Electronic device 100X acquires gesture information corresponding to the gesture motion based on information (also referred to as input data) output from the plurality of detection units.
- step S18 the electronic device 100X executes various processes based on the gesture information. For example, image processing can be performed on image information displayed on the display of the electronic device 100X, and the image information after the image processing can be displayed on the display.
- Step S19 corresponds to, for example, removing the electronic device 100X, turning off the electronic device 100 or the electronic device 100X, or canceling the pairing between the electronic device 100 and the electronic device 100X. .
- an electronic device with a new configuration or a display system with a new configuration can be provided. Further, with the use of the electronic device and the display system of one embodiment of the present invention, a method for operating an electronic device with a new structure or a method for operating a display system with a new structure can be provided.
- ⁇ Display configuration example> The configuration of the display 72 shown in FIG. 20A will be described with reference to FIGS. 26A, 26B and 27. FIG. Note that the configuration example of the display described below can be applied not only to the display 72 but also to the display 102 .
- 26A and 26B are schematic perspective views of a display (display device 200) applicable to the display 72 illustrated in FIG. 20A.
- the display device 200 has substrates 211 and 212 .
- the display device 200 has a display portion including elements provided between a substrate 211 and a substrate 212 .
- the display section is an area for displaying an image in the display device 200 .
- the display portion is a region in which a plurality of pixels 210 including pixel circuits 251 and light emitting devices 261 connected to the pixel circuits 251 are provided.
- the pixels 210 by arranging the pixels 210 in a matrix of 1920 ⁇ 1080, it is possible to realize a display that can be displayed at a so-called full high-definition (also called “2K resolution”, “2K1K”, or “2K”) resolution.
- full high-definition also called “2K resolution”, “2K1K”, or “2K”
- ultra high definition also called “4K resolution”, “4K2K”, or “4K”.
- the pixels 210 are arranged in a matrix of 7680 ⁇ 4320, it is possible to display at a resolution of so-called Super Hi-Vision (also called “8K resolution”, “8K4K”, or “8K”).
- a display capable of full-color display with a resolution of 16K or even 32K is possible.
- the pixel density (definition) in the display device 200 is preferably 1000 ppi or more and 10000 ppi or less. For example, it may be 2000 ppi or more and 6000 ppi or less, or 3000 ppi or more and 5000 ppi or less.
- the screen ratio (aspect ratio) of the display device 200 is not particularly limited.
- the display device 200 can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
- a display element may be replaced with “device”.
- a display element, a light-emitting element, and a liquid crystal element can be interchanged with, for example, a display device, a light-emitting device, and a liquid crystal device.
- the display device 200 receives various signals and power supply potential from the outside via the terminal section 214, and can perform display.
- a plurality of layers are provided between the substrate 211 and the substrate 212, and each layer is provided with a transistor for circuit operation or a display element for emitting light.
- a pixel circuit having a function of controlling light emission of a display element a driver circuit having a function of controlling the pixel circuit, a functional circuit having a function of controlling the driver circuit, and the like are provided.
- FIG. 26B shows a perspective view schematically showing the structure of each layer provided between the substrate 211 and the substrate 212. As shown in FIG.
- a layer 220 is provided on the substrate 211 .
- Layer 220 has drive circuitry 230 and functional circuitry 240 .
- Layer 220 has transistor 203 with silicon in semiconductor layer 204 with a channel forming region.
- the substrate 211 is, for example, a silicon substrate.
- a silicon substrate is preferable because it has higher thermal conductivity than a glass substrate.
- the transistor 201 can be, for example, a transistor including single crystal silicon in a channel formation region (also referred to as a "c-Si transistor").
- a transistor including single crystal silicon in a channel formation region also referred to as a "c-Si transistor”
- the on current of the transistor can be increased. Therefore, the circuit included in the layer 220 can be driven at high speed, which is preferable.
- the Si transistor can be formed by microfabrication with a channel length of 3 nm to 10 nm, the display device 200 can be provided in which an accelerator such as a CPU, a GPU, an application processor, and the like are provided integrally with the display portion.
- a transistor including polycrystalline silicon in a channel formation region may be used as the transistor provided in the layer 220.
- poly-Si transistor low-temperature polysilicon
- LTPS low-temperature polysilicon
- a transistor including LTPS in a channel formation region is also referred to as an "LTPS transistor.”
- the drive circuit 230 has, for example, a gate driver circuit, a source driver circuit, and the like. In addition, an arithmetic circuit, a memory circuit, a power supply circuit, and the like may be provided. Since the gate driver circuit, the source driver circuit, and other circuits can be arranged so as to overlap the display portion, the display of the display device 200 can be improved compared to the case where these circuits and the display portion are arranged side by side. The width of a non-display region (also referred to as a frame) existing on the outer periphery of the display device 200 can be made extremely narrow, and the size of the display device 200 can be reduced.
- a non-display region also referred to as a frame
- the functional circuit 240 has, for example, the function of an application processor for controlling each circuit in the display device 200 and generating signals for controlling each circuit.
- the functional circuit 240 may also have a circuit for correcting image data, such as an accelerator such as a CPU or GPU.
- the functional circuit 240 also includes an LVDS (Low Voltage Differential Signaling) circuit, a MIPI (Mobile Industry Processor Interface) circuit, and/or a D/A It may have a (Digital to Analog) conversion circuit or the like.
- the functional circuit 240 may also include a circuit for compressing/decompressing image data and/or a power supply circuit. In other words, the functional circuit 240 can be configured to have a part of the function of the control section 71 as well.
- a layer 250 is provided on the layer 220 .
- Layer 250 has pixel circuits 255 that include a plurality of pixel circuits 251 .
- Layer 250 includes transistor 201 including a metal oxide (also referred to as an oxide semiconductor) in semiconductor layer 202 having a channel formation region. Note that the layer 250 can be stacked over the layer 220 .
- a Si transistor may be provided in layer 250 .
- the pixel circuit 251 may include a transistor including single crystal silicon or polycrystal silicon in a channel formation region.
- LTPS may be used as the polycrystalline silicon.
- layer 250 can be formed on another substrate and attached to layer 220 .
- the pixel circuit 251 may be composed of a plurality of types of transistors using different semiconductor materials.
- the transistors may be provided in different layers for each type of transistor.
- the pixel circuit 251 includes a Si transistor and an OS transistor
- the Si transistor and the OS transistor may be overlapped. By overlapping the transistors, the area occupied by the pixel circuit 251 is reduced. Therefore, the definition of the display device 200 can be improved.
- a structure in which an LTPS transistor and an OS transistor are combined is sometimes called an LTPO.
- the OS transistor has the characteristic of having a very low off current. Therefore, it is particularly preferable to use an OS transistor as a transistor provided in the pixel circuit because analog data written to the pixel circuit can be held for a long time.
- a layer 260 is provided on the layer 250 .
- a substrate 212 is provided over the layer 260 .
- the substrate 212 is preferably a light-transmitting substrate or a layer made of a light-transmitting material.
- a layer 260 is provided with a plurality of light emitting devices 261 . Note that the layer 260 can be stacked over the layer 250 .
- an organic electroluminescence element also referred to as an organic EL element
- the light emitting device 261 is not limited to this, and an inorganic EL element made of an inorganic material, for example, may be used.
- the light emitting device 261 may have inorganic compounds such as quantum dots. For example, by using quantum dots in the light-emitting layer, it can function as a light-emitting material.
- the display device 200 of one embodiment of the present invention can have a structure in which a light-emitting device 261, a pixel circuit 251, a driver circuit 230, and a function circuit 240 are stacked; ratio (effective display area ratio) can be extremely high.
- the pixel aperture ratio can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less.
- the pixel circuits 251 can be arranged at an extremely high density, and the definition of pixels can be extremely increased.
- the display portion of the display device 200 (the region where the pixel circuit 251 and the light-emitting device 261 are stacked) has a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, still more preferably 6000 ppi or more. Pixels can be arranged with a resolution of 30000 ppi or less.
- Such a display device 200 has extremely high definition, it can be suitably used for devices for VR such as a head-mounted display, or glasses-type devices for AR. For example, even in the case of a configuration in which the display portion of the display device 200 is viewed through an optical member such as a lens, the display device 200 has an extremely high-definition display portion. A highly immersive display can be performed without being visually recognized.
- the diagonal size of the display portion is 0.1 inch or more and 5.0 inches or less, preferably 0.5 inch or more and 2.0 inches. Below, more preferably, it can be 1 inch or more and 1.7 inches or less. For example, the diagonal size of the display may be 1.5 inches or near 1.5 inches. By setting the diagonal size of the display portion to 2.0 inches or less, preferably around 1.5 inches, it is possible to perform processing in one exposure process of an exposure device (typically a scanner device). , can improve the productivity of the manufacturing process.
- an exposure device typically a scanner device
- the display device 200 can be applied to electronic devices other than wearable electronic devices.
- the diagonal size of the display may exceed 2.0 inches.
- the configuration of the transistors used in the pixel circuit 251 may be selected as appropriate according to the diagonal size of the display portion.
- the diagonal size of the display portion is preferably 0.1 inch or more and 3 inches or less.
- the diagonal size of the display portion is preferably 0.1 inch or more and 30 inches or less, more preferably 1 inch or more and 30 inches or less.
- the diagonal size of the display portion is preferably 0.1 inch or more and 50 inches or less, and more preferably 1 inch or more and 50 inches or less. preferable.
- the diagonal size of the display portion is preferably 0.1 inch or more and 200 inches or less, more preferably 50 inches or more and 100 inches or less.
- a single-crystal Si transistor is much more difficult to increase in size than the size of a single-crystal Si substrate.
- the LTPS transistor uses a laser crystallizer in the manufacturing process, it is difficult to cope with an increase in size (typically, a screen size exceeding 30 inches in diagonal size).
- the OS transistor is free from restrictions on the use of a laser crystallization apparatus or the like in the manufacturing process, or can be manufactured at a relatively low process temperature (typically 450° C. or lower), and thus has a relatively large area. (Typically, it is possible to correspond to a display panel of 50 inches or more and 100 inches or less in diagonal size).
- LTPO can be applied to the diagonal size of the display area (typically, 1 inch or more and 50 inches or less) in the area between the case where the LTPS transistor is used and the case where the OS transistor is used. Become.
- the display device 200 shown in FIG. 27 is a block diagram illustrating a plurality of wirings connecting the pixel circuit 251, the driving circuit 230 and the functional circuit 240, bus wirings in the display device 200, and the like.
- a layer 250 has a plurality of pixel circuits 251 arranged in a matrix.
- the driver circuit 230 and the functional circuit 240 are arranged on the layer 220 .
- the drive circuit 230 has a source driver circuit 231, a digital-analog converter circuit 232, a gate driver circuit 233, and a level shifter 234, for example.
- the functional circuit 240 has, as an example, a storage device 241 , a GPU (AI accelerator) 242 , an EL correction circuit 243 , a timing controller 244 , a CPU 245 , a sensor controller 246 and a power supply circuit 247 .
- Functional circuit 240 has the function of an application processor.
- the circuit included in the drive circuit 230 and the circuit included in the function circuit 240 are each electrically connected to the bus line BSL as an example. .
- the source driver circuit 231 has a function of transmitting image data to the pixel circuit 251 included in the pixel 210 . Therefore, the source driver circuit 231 is electrically connected to the pixel circuit 251 through the wiring SL. Note that a plurality of source driver circuits 231 are preferably provided. By arranging the plurality of source driver circuits 231 for each section of the display portion in which the pixel circuit 251 is provided, it is possible to perform driving with a different driving frequency for each section of the display portion.
- the digital-to-analog conversion circuit 232 has a function of converting image data digitally processed by a GPU, correction circuit, etc. into analog data.
- the image data converted into analog data is amplified by an amplifier circuit such as an operational amplifier and transmitted to the pixel circuit 251 via the source driver circuit 231 .
- the digital-analog conversion circuit 232 may be included in the source driver circuit 231, or the image data may be transmitted in the order of the source driver circuit 231, the digital-analog conversion circuit 232, and the pixel circuit 251.
- the gate driver circuit 233 has a function of selecting a pixel circuit to which image data is to be sent in the pixel circuit 251 . Therefore, the gate driver circuit 233 is electrically connected to the pixel circuit 251 through the wiring GL. Note that it is preferable that a plurality of gate driver circuits 233 are provided corresponding to the source driver circuits 231 . By arranging the plurality of gate driver circuits 233 for each section of the display section in which the pixel circuit 251 is provided, it is possible to perform driving with a different driving frequency for each section of the display section.
- the level shifter 234 has a function of converting signals input to the source driver circuit 231, the digital-to-analog conversion circuit 232, the gate driver circuit 233, etc. to appropriate levels.
- the storage device 241 has a function of storing image data to be displayed on the pixel circuit 251 .
- the storage device 241 can be configured to store image data as digital data or analog data.
- the storage device 241 be a non-volatile memory.
- a NAND memory or the like can be applied as the storage device 241 .
- the storage device 241 is preferably a volatile memory.
- SRAM Static Random Access Memory
- DRAM Dynamic Random Access Memory
- the GPU 242 has, for example, a function of performing processing for outputting image data read from the storage device 241 to the pixel circuit 251 .
- the GPU 242 since the GPU 242 is configured to perform pipeline processing in parallel, image data to be output to the pixel circuit 251 can be processed at high speed.
- GPU 242 may also function as a decoder for restoring encoded images.
- the functional circuit 240 may include a plurality of circuits that can improve the display quality of the display device 200 .
- a correction circuit color toning, dimming
- the functional circuit 240 may be provided with an EL correction circuit.
- the functional circuit 240 includes an EL correction circuit 243 as an example.
- Artificial intelligence may also be used for the image correction described above.
- the current (or voltage applied to the pixel circuit) is monitored and acquired, the displayed image is acquired by an image sensor, etc., and the current (or voltage) and the image are calculated by artificial intelligence (for example, , an artificial neural network, etc.), and the output result may be used to determine whether or not to correct the image.
- artificial intelligence for example, , an artificial neural network, etc.
- artificial intelligence calculations can be applied not only to image correction, but also to up-conversion processing to increase the resolution of image data.
- the GPU 242 in FIG. 27 illustrates blocks for performing various correction calculations (color unevenness correction 242a, up-conversion 242b, etc.).
- Algorithms for up-converting image data include the Nearest neighbor method, Bilinear method, Bicubic method, RAISR (Rapid and Accurate Image Super-Resolution) method, ANR (Anchored Neighborhood Regression) method, A+ method, SuperN (SRCN -Resolution (Convolutional Neural Network) method or the like can be selected.
- the up-conversion process may be configured such that the algorithm used for the up-conversion process is changed for each region determined according to the gaze point. For example, the up-conversion processing of the gaze point and the area near the gaze point is performed with a slow but high-precision algorithm, and the up-conversion processing of areas other than the subject area is performed with a fast but low-accuracy algorithm. Just do it. With this configuration, the time required for up-conversion processing can be shortened. Also, the power consumption required for up-conversion processing can be reduced.
- up-conversion processing not only up-conversion processing, but also down-conversion processing that lowers the resolution of image data may be performed. If the resolution of the image data is higher than the resolution of the display device 200, part of the image data may not be displayed on the display section. In such a case, the entire image data can be displayed on the display unit by performing down-conversion processing.
- the timing controller 244 has a function of controlling the drive frequency for displaying images. For example, when displaying a still image on the display device 200, power consumption of the display device 200 can be reduced by lowering the driving frequency by the timing controller 244. FIG.
- the CPU 245 has a function of performing general-purpose processing such as, for example, operating system execution, data control, various calculations, and program execution.
- the CPU 245 has a role of issuing commands such as, for example, an image data write operation or read operation in the storage device 241, an image data correction operation, and an operation to a sensor, which will be described later.
- the CPU 245 may have a function of transmitting a control signal to at least one of the circuits included in the functional circuit 240 .
- the sensor controller 246 has a function of controlling sensors. Further, in FIG. 27, a wiring SNCL is illustrated as a wiring for electrically connecting to the sensor.
- the sensor can be, for example, a touch sensor that can be provided in the display unit of the display device 200 .
- the sensor may be, for example, an illuminance sensor.
- the power supply circuit 247 has a function of generating a voltage to be supplied to circuits included in the pixel circuit 251, the drive circuit 230, and the function circuit 240.
- the power supply circuit 247 may have a function of selecting a circuit that supplies voltage.
- the power supply circuit 247 can reduce power consumption of the entire display device 200 by stopping voltage supply to the CPU 245, the GPU 242, and the like while a still image is being displayed.
- the display device of one embodiment of the present invention can have a structure in which a display element, a pixel circuit, a driver circuit, and a functional circuit are stacked.
- a driver circuit and a functional circuit which are peripheral circuits, can be arranged so as to overlap with the pixel circuit, and the width of the frame can be extremely narrowed, so that the display device can be miniaturized.
- the display device of one embodiment of the present invention has a structure in which circuits are stacked, the wiring that connects the circuits can be shortened; thus, the display device can be lightweight. .
- the display device of one embodiment of the present invention can have high pixel definition, the display device can have excellent display quality.
- FIG. 28 is a flowchart for explaining an operation example of an electronic device 100X having a display 72 to which the display device 200 is applicable.
- the movement of the electronic device 100X is detected by the sensor 75A or, alternatively, the acceleration sensor, and the first information (information on the movement of the housing 81) is obtained (step E11).
- An image of the user's eye is captured using the sensor 75A or the like to acquire second information (information related to the user's line of sight) (step E12).
- step E13 drawing processing of 360-degree omnidirectional image data is performed based on the first information
- step E13 The schematic diagram shown in FIG. 29A illustrates the user 130 positioned at the center of the 360-degree omnidirectional image data 422 .
- the user can visually recognize an image 424A in a direction 423A displayed on the display device 200 of the electronic device 100X.
- FIG. 29B shows how the user 130 moves the head from the schematic diagram of FIG. 29A and visually recognizes the image 424B in the direction 423B.
- the user 130 can recognize the space represented by the 360-degree omnidirectional image data 422 by changing the image 424A to the image 424B according to the movement of the housing of the electronic device 100X.
- the user 130 moves the housing of the electronic device 100X according to the movement of the head.
- the image obtained from the 360-degree omnidirectional image data 422 according to the movement of the electronic device 100X can be processed with high drawing processing power, so that the user 130 can recognize the virtual space that is in line with the real world space. .
- a plurality of areas corresponding to the gaze point G are determined for the area of the display section of the display device based on the second information (step E14). For example, a first area S1 including the gaze point G is determined, and a second area S2 adjacent to the first area S1 is determined. Also, the outside of the second area is defined as a third area S3.
- step E14 A specific example will be given for step E14.
- the discriminative visual field is a region in which visual functions such as visual acuity and color discrimination are the best, and refers to a region including a fixation point within about 5° of the center of the visual field.
- the effective visual field is the area where specific information can be instantly identified only by eye movement, and the area adjacent to the outside of the discriminative visual field within about 30 degrees horizontally and within about 20 degrees vertically of the center of the visual field (gazing point). Point.
- the stable fixation field is a region where specific information can be identified without difficulty with head movement, and refers to the area adjacent to the outside of the effective visual field within about 90° horizontally and within about 70° vertically of the center of the visual field. .
- the induced visual field is a region in which the existence of a specific object can be recognized, but the discrimination ability is low, and refers to the area adjacent to the stable fixation field within about 100° horizontally and within about 85° vertically of the center of the visual field.
- the auxiliary visual field is an area where the ability to discriminate a specific object is extremely low and the presence of a stimulus can be recognized. refers to the area adjacent to the outside of the .
- the image quality from the discriminative field of view to the effective field of view is important.
- the image quality of the discriminative field of view is important.
- FIG. 30A is a schematic diagram showing how the user 130 observes the image 424 displayed on the display unit of the display device 200 of the electronic device 100X from the front (image display surface).
- the image 424 illustrated in FIG. 30A also corresponds to the display.
- a gaze point G beyond the line of sight 423 of the user 130 is shown.
- first area S1 the area including the discriminative visual field on the image 424
- second area S2 the area including the effective visual field
- a region including the stable fixation field, the guidance field, and/or the auxiliary field of view is defined as a "third region S3".
- the boundaries (contours) of the first area S1 and the second area S2 are indicated by curved lines, but the present invention is not limited to this.
- the boundary (outline) between the first area S1 and the second area S2 may be rectangular or polygonal.
- the shape may be a combination of a straight line and a curved line.
- the display unit of the display device 200 may be divided into two areas, the area including the discriminative visual field and the effective visual field as the first area S1, and the other area as the second area S2. In this case, the third region S3 is not formed.
- FIG. 31A is a top view of an image 424 displayed on the display unit of the display device 200 of the electronic device 100X
- FIG. 31B is a horizontal view of the image 424 displayed on the display unit of the display device 200 of the electronic device 100X. It is the figure seen from.
- the horizontal angle of the first region S1 is indicated as “angle ⁇ x1”
- the horizontal angle of the second region S2 is indicated as “angle ⁇ x2” (see FIG. 31A)
- the vertical angle of the first region S1 is indicated as "angle ⁇ y1”
- the vertical angle of the second region S2 is indicated as "angle ⁇ y2" (see FIG. 31B).
- the area of the first region S1 can be expanded. In this case, part of the effective field of view is included in the first area S1. Further, for example, by setting the angle ⁇ x2 to 45° and the angle ⁇ y2 to 35°, the area of the second region S2 can be increased. In this case, part of the stable fixation field is included in the second region S2.
- each of the angles ⁇ x1 and ⁇ y1 is preferably 5° or more and less than 20°.
- the gaze point G also moves. Therefore, the first area S1 and the second area S2 also move.
- the amount of change in line of sight 423 exceeds a certain amount, it is determined that line of sight 423 is moving. That is, when the amount of change in the point of gaze G exceeds a certain amount, it is determined that the point of gaze G is moving.
- the amount of change in the line of sight 423 is equal to or less than a certain amount, it is determined that the movement of the line of sight 423 has stopped, and the first area S1 to the third area S3 are determined. That is, when the amount of change in the point of gaze G is equal to or less than a certain amount, it is determined that the point of gaze G has stopped moving, and the first area S1 to the third area S3 are determined.
- the driving circuit 230 is controlled according to the plurality of areas (first area S1 to third area S3) (step E15).
- FIG. 32A and 32B show a configuration example of the pixel circuit 251 and a light emitting device 261 connected to the pixel circuit 251.
- FIG. FIG. 32A is a diagram showing the connection of each element
- FIG. 32B is a diagram schematically showing the vertical relationship of a layer 220 including a driver circuit, a layer 250 including a plurality of transistors included in a pixel circuit, and a layer 260 including a light emitting device. be.
- a pixel circuit 251 shown as an example in FIGS. 32A and 32B includes a transistor 452A, a transistor 452B, a transistor 452C, and a capacitor 453.
- the transistors 452A, 452B, and 452C can be OS transistors.
- Each of the OS transistors, the transistor 452A, the transistor 452B, and the transistor 452C, preferably has a back gate electrode. can be configured to provide
- the transistor 452B includes a gate electrode electrically connected to the transistor 452A, a first electrode electrically connected to the light emitting device 261, and a second electrode electrically connected to the wiring ANO.
- the wiring ANO is wiring for applying a potential for supplying current to the light emitting device 261 .
- the transistor 452A has a first terminal electrically connected to the gate electrode of the transistor 452B, a second terminal electrically connected to a wiring SL functioning as a source line, and a wiring GL1 functioning as a gate line. and a gate electrode having a function of controlling a conducting state or a non-conducting state based on the potential.
- the transistor 452C is turned on based on the potentials of the first terminal electrically connected to the wiring V0, the second terminal electrically connected to the light emitting device 261, and the wiring GL2 functioning as a gate line. or a gate electrode having a function of controlling a non-conducting state.
- the wiring V0 is a wiring for applying a reference potential and a wiring for outputting current flowing through the pixel circuit 251 to the driving circuit 230 or the function circuit 240 .
- the capacitor 453 includes a conductive film electrically connected to the gate electrode of the transistor 452B and a conductive film electrically connected to the second electrode of the transistor 452C.
- the light emitting device 261 includes a first electrode electrically connected to the first electrode of the transistor 452B and a second electrode electrically connected to the wiring VCOM.
- a wiring VCOM is a wiring for applying a potential for supplying a current to the light emitting device 261 .
- the intensity of light emitted by the light emitting device 261 can be controlled according to the image signal applied to the gate electrode of the transistor 452B. Variation in the gate-source voltage of the transistor 452B can be suppressed by the reference potential of the wiring V0 applied through the transistor 452C.
- a current value that can be used to set pixel parameters can also be output from the wiring V0.
- the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 452B or the light-emitting device 261 to the outside.
- the current output to the wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to the functional circuit 240 or the like.
- the light-emitting device described in one embodiment of the present invention refers to a self-luminous display element such as an organic EL element (also referred to as an OLED (Organic Light Emitting Diode)).
- the light-emitting device electrically connected to the pixel circuit can be a self-luminous light-emitting device such as LED (Light Emitting Diode), micro LED, QLED (Quantum-dot Light Emitting Diode), semiconductor laser, etc. is.
- the wiring that electrically connects the pixel circuit 251 and the driver circuit 230 can be shortened, so that the wiring resistance of the wiring can be reduced. Therefore, since data can be written at high speed, the display device 200 can be driven at high speed. Accordingly, a sufficient frame period can be ensured even if the number of pixel circuits 251 included in the display device 200 is increased, so that the pixel density of the display device 200 can be increased. Further, by increasing the pixel density of the display device 200, the definition of the image displayed by the display device 200 can be increased. For example, the pixel density of the display device 200 can be 1000 ppi or more, or 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 200 can be a display device for AR or VR, for example, and can be suitably applied to an electronic device, such as an HMD, in which the distance between the display unit and the user is short.
- an electronic device such as an HMD
- FIG. 33A and 33B show perspective views of a display device 200A that is a modification of the display device 200.
- FIG. FIG. 33B is a perspective view for explaining the structure of each layer included in the display device 200A. In order to reduce the repetition of the description, mainly the points different from the display device 200 will be described.
- a pixel circuit group 255 including a plurality of pixel circuits 251 and a driving circuit 230 are overlapped.
- the pixel circuit group 255 is divided into a plurality of sections 259 and the driving circuit 230 is divided into a plurality of sections 239 in the region overlapping the display section 213 .
- a plurality of partitions 239 each have a source driver circuit and a gate driver circuit.
- FIG. 34A shows a configuration example of the pixel circuit group 255 included in the display device 200A.
- FIG. 34B shows a configuration example of the drive circuit 230 included in the display device 200A.
- the partitions 259 and 239 are each arranged in a matrix of m rows and n columns (m and n are integers equal to or greater than 1). In this specification and the like, the partition 259 on the first row and the first column is indicated as partition 259[1,1], and the partition 259 on the mth row and nth column is indicated as partition 259[m,n].
- partition 239 in the first row and first column is indicated as partition 239[1,1]
- partition 239 in the mth row and nth column is indicated as partition 239[m,n].
- 34A and 34B show the case where m is 4 and n is 8. FIG. That is, the pixel circuit group 255 and the driving circuit 230 are each divided into 32 parts.
- Each of the plurality of partitions 259 has a plurality of pixel circuits 251, a plurality of wirings SL, and a plurality of wirings GL.
- one of the plurality of pixel circuits 251 is electrically connected to at least one of the plurality of wirings SL and at least one of the plurality of wirings GL.
- One of the partitions 259 and one of the partitions 239 are overlapped (see FIG. 34C).
- the section 259[i,j] (i is an integer of 1 or more and m or less and j is an integer of 1 or more and n or less) and the section 239[i,j] are overlapped.
- the source driver circuit 231 included in the section 239[i, j] is electrically connected to the wiring SL included in the section 259[i, j].
- the gate driver circuit 233 included in the section 239[i,j] is electrically connected to the wiring GL included in the section 259[i,j].
- the gate driver circuit 233 included in the section 239[i,j] has a function of controlling the plurality of pixel circuits 251 included in the section 259[i,j].
- the pixel circuits 251 included in the partitions 259[i,j] By overlapping the partitions 259[i,j] and the partitions 239[i,j], the pixel circuits 251 included in the partitions 259[i,j], the source driver circuits 231 included in the partitions 239[i,j], and the The connection distance (wiring length) with the gate driver circuit 233 can be extremely shortened. As a result, since wiring resistance and parasitic capacitance are reduced, the time required for charging and discharging is shortened, and high-speed driving can be realized. Also, power consumption can be reduced. In addition, miniaturization and weight reduction can be realized.
- the display device 200A has a configuration in which each section 239 has a source driver circuit 231 and a gate driver circuit 233 . Therefore, it is possible to divide the display unit 213 into each section 259 corresponding to the section 239 and rewrite the image. For example, in the display unit 213, only the image data of the section where the image has changed can be rewritten, and the image data of the section where the image has not changed can be retained, thereby realizing a reduction in power consumption.
- one of the display sections 213 divided into each section 59 is called a sub-display section 219 .
- the display device 200A described with reference to FIGS. 33 and 34 shows the case where the display section 213 is divided into 32 sub-display sections 219 (see FIG. 33A).
- the sub-display portion 219 includes a plurality of pixels 210 shown in FIG. 32 and the like.
- one sub-display portion 219 includes one of the partitions 259 including a plurality of pixel circuits 251 and a plurality of light emitting devices 261 .
- one section 239 has a function of controlling a plurality of pixels 210 included in one sub-display section 219 .
- the display device 200A can arbitrarily set the drive frequency (frame frequency, frame rate, refresh rate, etc.) during image display for each sub-display section 219 by means of the timing controller 244 of the functional circuit 240 .
- Functional circuit 240 has the function of controlling the operation of each of the plurality of partitions 239 and the plurality of partitions 259 . That is, the functional circuit 240 has a function of controlling the driving frequency and operation timing of each of the plurality of sub-display portions 219 arranged in matrix. In addition, functional circuit 240 has a function of adjusting synchronization between the sub-displays.
- the display device in the electronic device of one embodiment of the present invention can reduce power consumption by stacking pixel circuits and driver circuits and varying the driving frequency of each sub-display portion 219 according to the movement of the line of sight. can.
- FIG. 35A shows a display section 213 having sub-display sections 219 of 4 rows and 8 columns. Also, FIG. 35A shows the first area S1 to the third area S3 centering on the gaze point G. As shown in FIG. The display device 200A distributes each of the plurality of sub display portions 219 to either a first section 229A overlapping with the first area S1 or the second area S2 or a second section 229B overlapping with the third area S3. That is, the display device 200A distributes each of the multiple sections 239 to the first section 229A or the second section 229B.
- the first section 229A overlapping the first area S1 and the second area S2 is the sub-display section 219 including the area overlapping the gaze point G
- the second section 229B is located outside the first section 229A
- the function circuit 240 controls the operation of the drive circuits (the source driver circuits 231 and the gate driver circuits 233 ) of each of the plurality of partitions 239 .
- the second section 229B is a section that overlaps with the third region S3 that includes the above-described stable fixation field, guidance field, and auxiliary field of view, and is a section with low discriminating power for the user. Therefore, even if the number of times of rewriting image data per unit time (hereinafter, also referred to as "the number of times of image rewriting”) is smaller in the second section 229B than in the first section 229A during image display, the user's sense of realism is reduced.
- the power consumption of the display device can be reduced.
- lowering the drive frequency also lowers the display quality.
- the display quality during moving image display is degraded.
- by setting the driving frequency of the second section 229B lower than the driving frequency of the first section 229A the power consumption of the section with low visibility to the user is reduced, and A decrease in display quality can be suppressed. According to one embodiment of the present invention, it is possible to achieve both maintenance of display quality and reduction of power consumption.
- the driving frequency of the first section 229A should be 30 Hz or more and 500 Hz or less, preferably 60 Hz or more and 500 Hz or less.
- the drive frequency of the second section 229B is preferably equal to or lower than the drive frequency of the first section 229A, more preferably 1/2 or less of the drive frequency of the first section 229A, and more preferably 1/5 or less of the drive frequency of the first section 229A. .
- the third section 229C is set outside the second section 229B (see FIG. 35C), and the drive frequency of the sub display section 219 included in the third section 229C is set to It may be lower than the second section 229B.
- the drive frequency of the third section 229C is preferably equal to or less than the drive frequency of the second section 229B, more preferably 1/2 or less of the drive frequency of the second section 229B, and more preferably 1/5 or less of the drive frequency of the second section 229B. .
- Power consumption can be further reduced by significantly reducing the number of times the image is rewritten. Also, rewriting of image data may be stopped as necessary. Power consumption can be further reduced by stopping rewriting of image data.
- a transistor with an extremely small off current As the transistor forming the pixel circuit 251 , it is preferable to use a transistor with an extremely small off current as the transistor forming the pixel circuit 251 .
- an OS transistor is suitable for the transistor forming the pixel circuit 251 . Since the OS transistor has extremely low off-state current, image data supplied to the pixel circuit 251 can be retained for a long time. In particular, it is preferable to use an OS transistor for the transistor 452A.
- an image may be displayed that is significantly different in brightness, contrast, color tone, etc. from the previous image.
- there is a difference in the timing of image switching between the first section 229A and the section having a drive frequency lower than that of the first section 229A. is greatly different, and the actual display quality may be impaired.
- the image is rewritten in the sections other than the first section 229A at the same drive frequency as the first section 229A, and then the drive frequencies of the sections other than the first section 229A are changed. should be lowered.
- the sections other than the first section 229A are also rewritten with the same drive frequency as the first section 229A, and it is determined that the amount of change is within the certain amount. If so, the drive frequency of the sections other than the first section 229A may be reduced. Also, when it is determined that the amount of change in the point of gaze G is small, the driving frequency of the sections other than the first section 229A may be further lowered.
- the divisions set in the display unit 213 are not limited to the first division 229A, the second division 229B, and the third division 229C. Four or more sections may be set in the display section 213 . By setting a plurality of sections in the display unit 213 and lowering the driving frequency in stages, it is possible to further reduce substantial deterioration in display quality.
- the above-described up-conversion processing may be performed on the image displayed in the first section 229A.
- the display quality can be improved.
- the above-described up-conversion processing may be performed on the images displayed in the sections other than the first section 229A. By displaying the up-converted image in the sections other than the first section 229A, it is possible to further reduce the substantial decrease in display quality when the driving frequency of the sections other than the first section 229A is lowered. .
- the image displayed in the first section 229A may be upconverted using a high-precision algorithm, and the image displayed in sections other than the first section 229A may be upconverted using a low-precision algorithm. Even in such a case, it is possible to further reduce the substantial deterioration in display quality when the driving frequency of the sections other than the first section 229A is lowered.
- high-speed rewriting can be realized by rewriting image data for each sub-display unit 219 at the same time in all sub-display units 219 . That is, high-speed rewriting can be realized by rewriting image data for each section 239 at the same time for all sections 239 .
- the source driver circuit writes image data to all pixels of one row at the same time while the pixels of one row are selected by the gate driver circuit. For example, if the display section 213 is not divided into the sub-display section 219 and the resolution is 4000 ⁇ 2000, the source driver circuit selects 4000 pixels while the gate driver circuit selects one row of pixels. It is necessary to write image data to pixels. When the frame frequency is 120 Hz, the duration of one frame is approximately 8.3 msec. Therefore, the gate driver needs to select 2000 rows in about 8.3 msec, and the time for selecting one row of gate lines, that is, the time for writing image data per pixel is about 4.17 ⁇ sec. That is, the higher the resolution of the display unit and the higher the frame frequency, the more difficult it becomes to secure sufficient time for rewriting image data.
- the display section 213 is divided into four in the row direction. Therefore, in one sub-display portion 219, the writing time of image data per pixel can be four times longer than when the display portion 213 is not divided. According to one embodiment of the present invention, even when the frame frequency is set to 240 Hz, or even 360 Hz, it is easy to secure time to rewrite image data, so that a display device with high display quality can be realized.
- the display portion 213 is divided into four in the row direction, the length of the wiring SL electrically connecting the source driver circuit and the pixel circuit is reduced to one fourth. become. Therefore, the resistance value and the parasitic capacitance of the wiring SL are each reduced to 1/4, and the time required for writing (rewriting) image data can be shortened.
- the display portion 213 is divided into eight in the column direction. become 1. Therefore, the resistance value and the parasitic capacitance of the wiring GL are each reduced to 1/8, signal deterioration and delay are improved, and it becomes easy to ensure the rewrite time of the image data.
- the display device 200A since it is easy to secure sufficient image data writing time, it is possible to realize high-speed rewriting of the display image. Therefore, a display device with high display quality can be realized. In particular, a display device excellent in displaying moving images can be realized.
- the display device of this embodiment can be a high-definition display panel.
- the display device of one embodiment of the present invention is a display unit of an information terminal (wearable device) such as a wristwatch type and a bracelet type, a device for VR such as a head-mounted display, and a glasses type for AR. It can be used for a display unit of a wearable device that can be worn on the head of the device.
- Display module A perspective view of the display module 980 is shown in FIG. 36A.
- the display module 980 has a display device 200A and an FPC 990 .
- the display panel included in the display module 980 is not limited to the display device 200A, and may be any one of display devices 200B to 200F, which will be described later.
- the display module 980 has substrates 991 and 992 .
- the display module 980 has a display section 981 .
- the display unit 981 is an area for displaying images.
- FIG. 36B shows a perspective view schematically showing the configuration on the substrate 991 side.
- a circuit portion 982 , a pixel circuit portion 983 on the circuit portion 982 , and a pixel portion 984 on the pixel circuit portion 983 are stacked over the substrate 991 .
- a terminal portion 985 for connecting to the FPC 990 is provided on a portion of the substrate 991 that does not overlap with the pixel portion 984 .
- the terminal portion 985 and the circuit portion 982 are electrically connected by a wiring portion 986 composed of a plurality of wirings.
- the pixel section 984 has a plurality of periodically arranged pixels 984a. An enlarged view of one pixel 984a is shown on the right side of FIG. 36B. Pixel 984a has a light emitting device 410R that emits red light, a light emitting device 410G that emits green light, and a light emitting device 410B that emits blue light.
- the pixel circuit section 983 has a plurality of pixel circuits 983a arranged periodically.
- One pixel circuit 983a is a circuit that controls light emission of three light emitting devices included in one pixel 984a.
- One pixel circuit 983a may be provided with three circuits for controlling light emission of one light-emitting device.
- the pixel circuit 983a can have at least one selection transistor, one current control transistor (driving transistor), and a capacitor for each light emitting device. At this time, a gate signal is inputted to the gate of the selection transistor, and a source signal is inputted to the source thereof. This realizes an active matrix display panel.
- the circuit section 982 has a circuit that drives each pixel circuit 983 a of the pixel circuit section 983 .
- a circuit that drives each pixel circuit 983 a of the pixel circuit section 983 For example, it is preferable to have one or both of a gate line driver circuit and a source line driver circuit.
- at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like may be provided.
- the transistor provided in the circuit portion 982 may form part of the pixel circuit 983a.
- the pixel circuit 983a may include a transistor included in the pixel circuit portion 983 and a transistor included in the circuit portion 982 .
- the FPC 990 functions as wiring for supplying a video signal, power supply potential, etc. to the circuit section 982 from the outside. Also, an IC may be mounted on the FPC 990 .
- the aperture ratio (effective display area ratio) of the display portion 981 is extremely high. can be higher.
- the aperture ratio of the display portion 981 can be 40% or more and less than 100%, preferably 50% or more and 95% or less, more preferably 60% or more and 95% or less.
- the pixels 984a can be arranged at extremely high density, and the definition of the display portion 981 can be extremely high.
- pixels 984a may be arranged with a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and still more preferably 6000 ppi or more, and 20000 ppi or less, or 30000 ppi or less. preferable.
- a display module 980 Since such a display module 980 has extremely high definition, it can be suitably used for devices for VR such as head-mounted displays, or glasses-type devices for AR. For example, even in the case of a configuration in which the display portion of the display module 980 is viewed through a lens, the display module 980 has an extremely high-definition display portion 981, so pixels cannot be viewed even if the display portion is enlarged with the lens. , a highly immersive display can be performed. Moreover, the display module 980 is not limited to this, and can be suitably used for electronic equipment having a relatively small display portion. For example, it can be suitably used for a display part of a wearable electronic device such as a wristwatch.
- Display device 200A A display device 200A shown in FIG.
- the substrate 801 corresponds to the substrate 991 in FIGS. 36A and 36B.
- a transistor 810 is a transistor having a channel formation region in the substrate 801 .
- a semiconductor substrate such as a single crystal silicon substrate can be used, for example.
- Transistor 810 includes a portion of substrate 801 , conductive layer 811 , low-resistance region 812 , insulating layer 813 , and insulating layer 814 .
- the conductive layer 811 functions as a gate electrode.
- An insulating layer 813 is located between the substrate 801 and the conductive layer 811 and functions as a gate insulating layer.
- a low-resistance region 812 is a region in which the substrate 801 is doped with impurities and functions as either a source or a drain.
- the insulating layer 814 is provided to cover the side surface of the conductive layer 811 and functions as an insulating layer.
- a device isolation layer 815 is provided between two adjacent transistors 810 so as to be embedded in the substrate 801 .
- An insulating layer 961 is provided to cover the transistor 810 and a capacitor 840 is provided over the insulating layer 961 .
- the capacitor 840 has a conductive layer 941, a conductive layer 945, and an insulating layer 943 positioned therebetween.
- the conductive layer 941 functions as one electrode of the capacitor 840
- the conductive layer 945 functions as the other electrode of the capacitor 840
- the insulating layer 943 functions as the dielectric of the capacitor 840 .
- the conductive layer 941 is provided on the insulating layer 961 and embedded in the insulating layer 954 .
- Conductive layer 941 is electrically connected to one of the source and drain of transistor 810 by plug 971 embedded in insulating layer 961 .
- An insulating layer 943 is provided over the conductive layer 941 .
- the conductive layer 945 is provided in a region overlapping with the conductive layer 941 with the insulating layer 943 provided therebetween.
- An insulating layer 955a is provided to cover the capacitor 840, an insulating layer 955b is provided over the insulating layer 955a, and an insulating layer 955c is provided over the insulating layer 955b.
- An inorganic insulating film can be preferably used for each of the insulating layer 955a, the insulating layer 955b, and the insulating layer 955c.
- a silicon oxide film is preferably used for the insulating layers 955a and 955c
- a silicon nitride film is preferably used for the insulating layer 955b.
- the insulating layer 955b can function as an etching protection film.
- an example in which the insulating layer 955c is partly etched to form a recess is shown; however, the insulating layer 955c does not have to be provided with the recess.
- a light emitting device 410R, a light emitting device 410G, and a light emitting device 410B are provided on the insulating layer 955c.
- the light-emitting device is separately manufactured for each light-emitting color, so there is little change in chromaticity between low-luminance light emission and high-luminance light emission.
- the organic layers 412R, 412G, and 412B are separated from each other, crosstalk between adjacent sub-pixels can be suppressed even in a high-definition display panel. Therefore, a display panel with high definition and high display quality can be realized.
- An insulating layer 425, a resin layer 426, and a layer 428 are provided in regions between adjacent light emitting devices.
- the pixel electrode 411R, the pixel electrode 411G, and the pixel electrode 411B of the light-emitting device are composed of the insulating layer 955a, the insulating layer 955b, and the plug 956 embedded in the insulating layer 955c, the conductive layer 941 embedded in the insulating layer 954, and the pixel electrode 411B. , is electrically connected to one of the source or drain of the transistor 810 by a plug 971 embedded in the insulating layer 961 .
- the height of the upper surface of the insulating layer 955c and the height of the upper surface of the plug 956 match or substantially match.
- Various conductive materials can be used for the plug.
- a protective layer 421 is provided on the light emitting devices 410R, 410G, and 410B.
- a substrate 470 is bonded onto the protective layer 421 with an adhesive layer 471 .
- a display device 200B shown in FIG. 38 has a structure in which a transistor 810A and a transistor 810B each having a channel formed in a semiconductor substrate are stacked.
- the description of the same parts as those of the previously described display panel may be omitted.
- the display device 200B has a structure in which a substrate 801B provided with a transistor 810B, a capacitor 840, and a light-emitting device and a substrate 801A provided with a transistor 810A are bonded together.
- an insulating layer 845 is provided on the lower surface of the substrate 801B, and an insulating layer 846 is provided on the insulating layer 961 provided on the substrate 801A.
- the insulating layers 845 and 846 are insulating layers that function as protective layers and can suppress diffusion of impurities into the substrate 801B and the substrate 801A.
- an inorganic insulating film that can be used for the protective layer 421 or the insulating layer 832 can be used.
- a plug 843 penetrating through the substrate 801B and the insulating layer 845 is provided on the substrate 801B.
- the substrate 801B is provided with a conductive layer 842 below the insulating layer 845 .
- the conductive layer 842 is embedded in the insulating layer 835, and the lower surfaces of the conductive layer 842 and the insulating layer 835 are planarized. Also, the conductive layer 842 is electrically connected to the plug 843 .
- a conductive layer 841 is provided on an insulating layer 846 on the substrate 801A.
- the conductive layer 841 is embedded in the insulating layer 836, and top surfaces of the conductive layer 841 and the insulating layer 836 are planarized.
- the same conductive material is preferably used for the conductive layers 841 and 842 .
- a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above elements as components etc. can be used.
- a Cu—Cu (copper-copper) direct bonding technique (a technique for achieving electrical continuity by connecting Cu (copper) pads) can be applied.
- a display device 200 ⁇ /b>C shown in FIG. 39 has a configuration in which a conductive layer 841 and a conductive layer 842 are bonded via bumps 847 .
- the conductive layers 841 and 842 can be electrically connected.
- the bumps 847 can be formed using a conductive material containing gold (Au), nickel (Ni), indium (In), tin (Sn), or the like, for example. Also, for example, solder may be used as the bumps 847 . Further, an adhesive layer 848 may be provided between the insulating layer 845 and the insulating layer 846 . Further, when the bump 847 is provided, the insulating layer 835 and the insulating layer 836 may be omitted.
- Display device 200D A display device 200D shown in FIG. 40 is mainly different from the display device 200A in that the configuration of transistors is different.
- the transistor 820 is a transistor (OS transistor) in which a metal oxide (also referred to as an oxide semiconductor) is applied to a semiconductor layer in which a channel is formed.
- OS transistor a transistor in which a metal oxide (also referred to as an oxide semiconductor) is applied to a semiconductor layer in which a channel is formed.
- a transistor 820 includes a semiconductor layer 821 , an insulating layer 823 , a conductive layer 824 , a pair of conductive layers 825 , an insulating layer 826 , and a conductive layer 827 .
- the substrate 831 corresponds to the substrate 991 in FIGS. 36A and 36B.
- An insulating layer 832 is provided on the substrate 831 .
- the insulating layer 832 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 831 into the transistor 820 and oxygen from the semiconductor layer 821 toward the insulating layer 832 side.
- a film into which hydrogen or oxygen is less likely to diffuse than a silicon oxide film such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.
- a conductive layer 827 is provided over the insulating layer 832 and an insulating layer 826 is provided to cover the conductive layer 827 .
- the conductive layer 827 functions as a first gate electrode of the transistor 820, and part of the insulating layer 826 functions as a first gate insulating layer.
- An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 826 that is in contact with the semiconductor layer 821 .
- the top surface of the insulating layer 826 is preferably planarized.
- the semiconductor layer 821 is provided on the insulating layer 826 .
- the semiconductor layer 821 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics.
- a pair of conductive layers 825 is provided over and in contact with the semiconductor layer 821 and functions as a source electrode and a drain electrode.
- An insulating layer 828 is provided to cover the top and side surfaces of the pair of conductive layers 825, the side surface of the semiconductor layer 821, and the like, and an insulating layer 964 is provided over the insulating layer 828.
- the insulating layer 828 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 821 from the insulating layer 964 or the like and oxygen from leaving the semiconductor layer 821 .
- an insulating film similar to the insulating layer 832 can be used as the insulating layer 832.
- An opening reaching the semiconductor layer 821 is provided in the insulating layer 828 and the insulating layer 964 .
- An insulating layer 823 in contact with the top surface of the semiconductor layer 821 and a conductive layer 824 are embedded in the opening.
- the conductive layer 824 functions as a second gate electrode, and the insulating layer 823 functions as a second gate insulating layer.
- the top surface of the conductive layer 824, the top surface of the insulating layer 823, and the top surface of the insulating layer 964 are planarized so that their heights are the same or substantially the same, and an insulating layer 829 and an insulating layer 965 are provided to cover them. ing.
- the insulating layers 964 and 965 function as interlayer insulating layers.
- the insulating layer 829 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 820 from the insulating layer 965 or the like.
- As the insulating layer 829 an insulating film similar to the insulating layers 828 and 832 can be used.
- a plug 974 electrically connected to one of the pair of conductive layers 825 is provided so as to be embedded in the insulating layers 965 , 829 and 964 .
- the plug 974 includes a conductive layer 974a covering the side surfaces of the openings of the insulating layers 965, the insulating layers 829, the insulating layers 964, and the insulating layer 828 and part of the top surface of the conductive layer 825, and the conductive layer 974a. It is preferable to have a conductive layer 974b in contact with the top surface. At this time, a conductive material into which hydrogen and oxygen are difficult to diffuse is preferably used for the conductive layer 974a.
- a display device 200E illustrated in FIG. 41 has a structure in which a transistor 820A and a transistor 820B each including an oxide semiconductor as a semiconductor in which a channel is formed are stacked.
- the display device 200D can be used for the structure of the transistor 820A, the transistor 820B, and their peripherals.
- transistors each including an oxide semiconductor are stacked here, the structure is not limited to this.
- a structure in which three or more transistors are stacked may be employed.
- a display device 200F illustrated in FIG. 42 has a structure in which a transistor 810 in which a channel is formed over a substrate 801 and a transistor 820 including a metal oxide in a semiconductor layer in which the channel is formed are stacked.
- An insulating layer 961 is provided to cover the transistor 810 , and a conductive layer 951 is provided over the insulating layer 961 .
- An insulating layer 962 is provided to cover the conductive layer 951 , and the conductive layer 952 is provided over the insulating layer 962 .
- the conductive layers 951 and 952 each function as wirings.
- An insulating layer 963 and an insulating layer 832 are provided to cover the conductive layer 952 , and the transistor 820 is provided over the insulating layer 832 .
- An insulating layer 965 is provided to cover the transistor 820 and a capacitor 840 is provided over the insulating layer 965 . Capacitor 840 and transistor 820 are electrically connected by plug 974 .
- the transistor 820 can be used as a transistor forming a pixel circuit. Further, the transistor 810 can be used as a transistor forming a pixel circuit or a transistor forming a driver circuit (a gate line driver circuit or a source line driver circuit) for driving the pixel circuit. Further, the transistors 810 and 820 can be used as transistors included in various circuits such as an arithmetic circuit and a memory circuit.
- a display device 200G illustrated in FIG. 43 has a structure in which a transistor 820A including a metal oxide in a semiconductor layer in which a channel is formed and a transistor 820B including a metal oxide in a semiconductor layer in which a channel is formed are stacked. .
- transistors having different compositions of constituent elements in the metal oxide of the semiconductor layer can be used. Therefore, a display device using OS transistors with different transistor characteristics can be provided.
- the upper layer transistor 820A can be used as a pixel circuit transistor that drives a light emitting device
- the lower layer transistor 820B can be used as a driver circuit transistor.
- the circuits provided directly under the light-emitting devices can be arranged with higher density, so that the size of the display panel can be reduced compared to the case where the driver circuits are provided around the display region. becomes possible.
- This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.
- Electronic devices using the semiconductor device include display devices such as televisions and monitors, lighting devices, desktop or notebook personal computers, word processors, and recording media such as DVDs (Digital Versatile Discs).
- DVDs Digital Vers
- mobile objects that are propelled by electric motors using power from power storage devices are also included in the category of electronic devices.
- the mobile body include an electric vehicle (EV), a hybrid vehicle (HEV) having both an internal combustion engine and an electric motor, a plug-in hybrid vehicle (PHEV), a tracked vehicle in which the tires and wheels are changed to endless tracks, and an electrically assisted vehicle.
- EV electric vehicle
- HEV hybrid vehicle
- PHEV plug-in hybrid vehicle
- a tracked vehicle in which the tires and wheels are changed to endless tracks and an electrically assisted vehicle.
- motorized bicycles including bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spacecraft.
- Electronic devices are sensors (force, displacement, position, velocity, acceleration, angular velocity, number of revolutions, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared)).
- the electronic device can have various functions. For example, functions to display various information (still images, moving images, text images, etc.) on the display, touch panel functions, functions to display calendars, dates or times, functions to execute various software (programs), wireless communication means, a function of reading a program or data recorded on a recording medium, or the like.
- FIG. 44A shows an example of a band-type information terminal.
- An information terminal 750 includes a housing 751, a semiconductor device 101, a sensor 752, and the like.
- the information terminal 750 may have a secondary battery, a display device, and the like inside.
- the semiconductor device according to one embodiment of the present invention for the information terminal 750, the information terminal 750 can function as an IoT device that is resistant to shock, small in size, and consumes low power.
- FIG. 44B is a diagram showing an example of usage of the information terminal 750 shown in FIG. 44A.
- the information terminal 750 can be used by being wrapped around the user's head or neck.
- a sensor (not shown) is provided inside the band-type information terminal 750 and information obtained from the sensor is processed by a semiconductor device.
- a semiconductor device By adopting such a configuration, it is possible to improve the convenience of the IoT device, which is resistant to impact and excels in miniaturization and low power consumption.
- FIG. 44C is a diagram showing another example of usage of the information terminal 750 shown in FIG. 44A.
- the information terminal 750 can be used by being wrapped around the user's arm.
- a sensor (not shown) is provided inside the band-type information terminal 750, information obtained from the sensor is processed by a semiconductor device, and an antenna 753 or the like provided in the band-type information terminal 750 is used to transmit external information.
- FIGS. 44D and 44E illustrate a dog or cat with an information terminal 750 attached.
- Collar 754 and lead 755 shown in FIGS. 44D and 44E have sensors, semiconductor device 101, etc., similar to information terminal 750 described in FIGS. 44B and 44C.
- the content (may be part of the content) described in one embodiment may be another content (may be part of the content) described in the embodiment, and/or one or more
- the contents described in another embodiment (or part of the contents) can be applied, combined, or replaced.
- electrode or “wiring” in this specification and the like does not functionally limit these components.
- an “electrode” may be used as part of a “wiring” and vice versa.
- electrode or “wiring” includes the case where a plurality of “electrodes” or “wiring” are integrally formed.
- a voltage is a potential difference from a reference potential.
- the reference potential is a ground voltage
- the voltage can be translated into a potential.
- Ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.
- a switch is one that has the function of being in a conducting state (on state) or a non-conducting state (off state) and controlling whether or not to allow current to flow.
- a switch has a function of selecting and switching a path through which current flows.
- the channel length refers to, for example, a region in which a semiconductor (or a portion of the semiconductor in which current flows when the transistor is on) overlaps with a gate in a top view of a transistor, or a channel is formed.
- the channel width refers to, for example, a region where a semiconductor (or a portion of the semiconductor where current flows when the transistor is on) overlaps with a gate electrode, or a region where a channel is formed. is the length of the part where the drain and the drain face each other.
- a and B are connected includes not only direct connection between A and B, but also electrical connection.
- a and B are electrically connected means that when there is an object having some kind of electrical action between A and B, an electric signal can be exchanged between A and B. What to say.
- 10M backup circuit
- 12: L1 cache memory device 13: L2 cache memory device
- 14 bus interface unit
- 20M data holding circuit
- 20: accelerator 21: memory circuit
- 22 arithmetic circuit
- 30M memory cell
- 30: memory device 31: memory cell array
- 45 USB Interface Circuit
- 51: Interrupt Control Circuit 52: Interface Circuit
- 54 DAC Interface Circuit
- 60 Power Supply Circuit
- 100 electronic device, 101: semiconductor device, 102: display, 103: main memory
- 104 battery
- 105: sensor 111: housing
- 112 operation unit
- 113 band
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Abstract
Description
図2Aおよび図2Bは、電子装置の構成例を説明する図である。
図3は、電子装置の構成例を説明する図である。
図4Aおよび図4Bは、電子装置の構成例を説明する図である。
図5は、電子装置の構成例を説明する図である。
図6Aおよび図6Bは、電子装置の構成例を説明する図である。
図7Aおよび図7Bは、電子装置の構成例を説明する図である。
図8Aおよび図8Bは、電子装置の構成例を説明する図である。
図9Aおよび図9Bは、電子装置の構成例を説明する図である。
図10Aおよび図10Bは、電子装置の構成例を説明する図である。
図11A乃至図11Fは、電子装置の構成例を示す図である。
図12は、電子装置の構成例を示す図である。
図13Aおよび図13Bは、電子装置の構成例を説明する図である。
図14A乃至図14Cは、電子装置の構成例を説明する図である。
図15Aおよび図15Bは、電子装置の構成例を説明する図である。
図16は、電子装置の構成例を説明する図である。
図17A乃至図17Cは、電子装置の構成例を説明する図である。
図18は、電子装置の構成例を説明する図である。
図19Aおよび図19Bは、電子装置の構成例を説明する図である。
図20A乃至図20Bは、表示装置、及び表示システムの構成例を示す図である。
図21A、及び図21Bは、表示装置、及び表示システムの構成例を示す図である。
図22A乃至図22Dは、表示装置、及び表示システムの画像の一例を示す図である。
図23は、表示システムの動作方法の一例を示す図である。
図24A乃至図24Dは、表示装置、及び表示システムの画像の一例を示す図である。
図25は、表示システムの動作方法の一例を示す図である。
図26Aおよび図26Bは、表示装置の構成例を説明する図である。
図27は、表示装置の構成例を説明する図である。
図28は、電子装置の動作例を説明する図である。
図29Aおよび図29Bは、電子装置の構成例を説明する模式図である。
図30Aおよび図30Bは、電子装置の構成例を説明する模式図である。
図31Aおよび図31Bは、電子装置の構成例を説明する模式図である。
図32Aおよび図32Bは、表示装置の構成例を説明する図である。
図33Aおよび図33Bは、表示装置の構成例を説明する図である。
図34Aおよび図34Cは、表示装置の構成例を説明する図である。
図35Aおよび図35Cは、表示装置の構成例を説明する図である。
図36A及び図36Bは、表示装置の構成例を示す図である。
図37は、表示装置の構成例を示す図である。
図38は、表示装置の構成例を示す図である。
図39は、表示装置の構成例を示す図である。
図40は、表示装置の構成例を示す図である。
図41は、表示装置の構成例を示す図である。
図42は、表示装置の構成例を示す図である。
図43は、表示装置の構成例を示す図である。
図44A乃至図44Eは、電子装置の構成例を説明する図である。
本発明の一態様である電子装置の構成例について、図1A乃至図11Fを参照して説明する。
図1Aは、本発明の一態様の電子装置を説明するためのブロック図である。図1Aに示す電子装置100は、半導体装置101の他、一例としてディスプレイ102、メインメモリ103、バッテリー104、およびセンサ105を図示している。また図1Bは、図1Aに示す電子装置100のブロック図に対応する電子装置100の斜視図の一例を示す。図1Bに示す電子装置は、腕時計型の電子装置であり、操作部112およびバンド113が取り付けられた筐体111内に、半導体装置101の他、ディスプレイ102、メインメモリ103、バッテリー104、およびセンサ105が納められた構成を図示している。なお、図1Bに示す電子装置100は、いわゆるスマートウォッチとしての機能を有する。
パワーゲーティングが可能なCPUコアを有するCPU10の一例について説明する。
上記CPU10の構成例において、CPUコア11内にバックアップ回路を有する構成例を図示したが、L1キャッシュメモリ装置12およびL2キャッシュメモリ装置13がバックアップ回路を有する構成とすることもできる。図6Aに示すメモリセル19は、L1キャッシュメモリ装置12、L2キャッシュメモリ装置13などのキャッシュメモリ装置に適用可能なメモリセルの回路図の一例である。図6Aに示すメモリセル19Sは、標準的な6T型SRAMセルと同じ回路構成である。図6Aに示すバックアップ回路19Aは、メモリセル19Sのデータを退避するための回路である。
図8Aは、アクセラレータ20を説明するためのブロック図である。図8Aでは、図1Aで説明したデータ保持回路20Mを有するメモリ回路21、演算回路22の他、制御回路23(23A乃至23D)、演算ブロック25、およびメモリ回路21と演算回路22とを接続する配線26を図示している。
ここでは、OSトランジスタを有するメモリセル30Mが設けられるメモリ装置30の構成例について説明する。
本実施の形態では、上記実施の形態1で説明した電子装置100において、CPU10で実行するプログラムの演算の一部をアクセラレータ20で実行する場合の、動作の一例を説明する。なお本実施の形態において、上記実施の形態と同じ符号が付される構成についての繰り返しの説明を省略する場合がある。
本実施の形態では、上記実施の形態1で説明した電子装置100の構成において、CPU10、アクセラレータ20、およびメモリ装置30を密結合させた半導体装置101の構成例および変形例について説明する。
本実施の形態では、上記実施の形態で説明した電子装置が有する半導体装置に適用可能なトランジスタの構成について説明する。一例として、異なる電気特性を有するトランジスタを積層して設ける構成について説明する。当該構成とすることで、半導体装置の設計自由度を高めることができる。また、異なる電気特性を有するトランジスタを積層して設けることで、半導体装置の集積度を高めることができる。
本実施の形態では、本発明の一態様である電子装置と、異なる別の電子装置と、を組み合わせて用いる表示システムについて、図20乃至図25を用いて説明する。
図20A乃至図20Cは、本発明の一態様である表示システムの構成例を説明する図面である。
ディスプレイ102、及びディスプレイ72は、それぞれ表示する機能を有する。ディスプレイ102、及びディスプレイ72としては、例えば、液晶表示デバイス、有機ELを含む発光デバイス、及びマイクロLEDなどの発光ダイオードを含む発光デバイスの中から選ばれる一または複数を用いることができる。生産性、及び発光効率を考慮した場合、ディスプレイ102、及びディスプレイ72としては、有機ELを含む発光デバイスを用いると好適である。
通信部106、及び通信部76は、それぞれ無線または有線で通信する機能を有する。通信部106、及び通信部76は、特に無線で通信する機能を有すると、接続のためのケーブルなどの部品点数を省略できるため好適である。
半導体装置101、及び制御部71は、それぞれディスプレイを制御する機能を有する。半導体装置101、及び制御部71としては、例えばCPU、GPU、およびメモリなどを有する。なお、CPUおよびGPUといった演算回路は、画像処理を行うことができ、例えば、画像データのアンプコンバート処理、またはダウンコンバート処理を行うことができる。これにより、ディスプレイの解像度に合わせて、解像度の小さい画像データをアップコンバートする、または、解像度の大きい画像データをダウンコンバートすることができ、表示品位の高い画像をディスプレイに表示させることができる。
バッテリー104、及びバッテリー74は、それぞれディスプレイに電力を供給する機能を有する。バッテリー104、及びバッテリー74は、例えば、一次電池、または二次電池を用いることができる。なお、当該二次電池としては、例えば、リチウムイオン二次電池を好適に用いることができる。
センサ105、及びセンサ75は、それぞれ、使用者の視覚、聴覚、触覚、味覚、及び嗅覚、のいずれか一または複数の情報を取得する機能を有する。より具体的には、センサ105、は、力、変位、位置、速度、加速度、角速度、回転数、距離、光、磁気、温度、音声、時間、電場、電流、電圧、電力、放射線、湿度、傾度、振動、におい、及び赤外線を測定する機能を有する。
次に、本発明の一態様の電子装置、及び表示システムの画像の一例について、図22A、図22B、図22C、及び図22Dを用いて説明を行う。
以下では、表示システムの動作方法の一例について説明する。図23は、表示システムの動作方法にかかるフローチャートである。
次に、本発明の一態様の表示システムによって、使用者が体験できる操作方法、及び使用者に提示することのできる画像について、上記とは異なる例を、図24A、図24B、図24C、及び図24Dを用いて説明を行う。
以下では、表示システムの動作方法の一例について説明する。図25は、表示システムの動作方法にかかるフローチャートである。
図20Aに図示するディスプレイ72の構成について図26Aおよび図26Bおよび図27を参照して説明する。なお以下で説明するディスプレイの構成例は、ディスプレイ72のみならず、ディスプレイ102にも適用することができる。
表示装置200の動作例について、図面を用いて説明する。図28は、表示装置200を適用可能なディスプレイ72を有する電子装置100Xの動作例を説明するためのフローチャートである。
図32Aおよび図32Bでは、画素回路251の構成例、および画素回路251に接続される発光デバイス261について示す。図32Aは各素子の接続を示す図、図32Bは、駆動回路を備える層220、画素回路が有する複数のトランジスタを備える層250、発光デバイスを備える層260の上下関係を模式的に示す図である。
図33Aおよび図33Bに表示装置200の変形例である表示装置200Aの斜視図を示す。図33Bは表示装置200Aが有する各層の構成を説明するための斜視図である。説明の繰り返しを減らすため、主に表示装置200と異なる点について説明する。
本実施の形態では、本発明の一態様の電子装置のディスプレイに適用できる表示モジュールの構成例について説明する。
図36Aに、表示モジュール980の斜視図を示す。表示モジュール980は、表示装置200Aと、FPC990と、を有する。なお、表示モジュール980が有する表示パネルは表示装置200Aに限られず、後述する表示装置200B乃至表示装置200Fのいずれかであってもよい。
図37Aに示す表示装置200Aは、基板801、発光デバイス410R、410G、410B、容量840、及び、トランジスタ810を有する。
図38に示す表示装置200Bは、それぞれ半導体基板にチャネルが形成されるトランジスタ810Aと、トランジスタ810Bとが積層された構成を有する。なお、以降の表示パネルの説明では、先に説明した表示パネルと同様の部分については説明を省略することがある。
図39に示す表示装置200Cは、導電層841と導電層842を、バンプ847を介して接合する構成を有する。
図40に示す表示装置200Dは、トランジスタの構成が異なる点で、表示装置200Aと主に相違する。
図41に示す表示装置200Eは、それぞれチャネルが形成される半導体に酸化物半導体を有するトランジスタ820Aと、トランジスタ820Bとが積層された構成を有する。
図42に示す表示装置200Fは、基板801にチャネルが形成されるトランジスタ810と、チャネルが形成される半導体層に金属酸化物を含むトランジスタ820とが積層された構成を有する。
図43に示す表示装置200Gは、チャネルが形成される半導体層に金属酸化物を含むトランジスタ820Aと、チャネルが形成される半導体層に金属酸化物を含むトランジスタ820Bと、が積層された構成を有する。当該構成とすることで、半導体層の金属酸化物における構成元素の組成を異ならせたトランジスタを用いることができる。そのため、トランジスタ特性の異なるOSトランジスタを用いた表示装置とすることができる。例えば上層のトランジスタ820Aは、発光デバイスを駆動する画素回路のトランジスタとして用い、下層のトランジスタ820Bは、駆動回路のトランジスタとして用いることができる。
本実施の形態では上述した半導体装置を備えた電子装置の例について図44を用いて説明を行う。
以上の実施の形態、及び実施の形態における各構成の説明について、以下に付記する。
Claims (10)
- 半導体装置を有する電子装置において、
前記半導体装置は、
CPUと、アクセラレータと、メモリ装置と、を有し、
前記CPUは、スキャンフリップフロップ回路と、前記スキャンフリップフロップ回路に電気的に接続されたバックアップ回路と、を有し、
前記バックアップ回路は、第1のトランジスタを有し、
前記アクセラレータは、演算回路と、前記演算回路に電気的に接続されたデータ保持回路を有し、
前記データ保持回路は、第2のトランジスタを有し、
前記メモリ装置は、第3のトランジスタを有するメモリセルを有し、
前記第1のトランジスタ乃至第3のトランジスタは、チャネル形成領域に金属酸化物を有する半導体層を有する、電子装置。 - 半導体装置を有する電子装置において、
前記半導体装置は、
CPUと、アクセラレータと、メモリ装置と、を有し、
前記CPUは、スキャンフリップフロップ回路と、前記スキャンフリップフロップ回路に電気的に接続されたバックアップ回路と、を有し、
前記バックアップ回路は、第1のトランジスタを有し、
前記バックアップ回路が設けられる層は、前記スキャンフリップフロップ回路が設けられる層と積層して設けられ、
前記アクセラレータは、演算回路と、前記演算回路に電気的に接続されたデータ保持回路を有し、
前記データ保持回路は、第2のトランジスタを有し、
前記データ保持回路が設けられる層は、前記演算回路が設けられる層と積層して設けられ、
前記メモリ装置は、第3のトランジスタを有するメモリセルを有し、
前記第1のトランジスタ乃至第3のトランジスタは、チャネル形成領域に金属酸化物を有する半導体層を有する、電子装置。 - 請求項1または2において、
前記バックアップ回路は、前記CPUの非動作時において、前記スキャンフリップフロップ回路に保持されたデータを電源電圧の供給が停止した状態で保持する機能を有する、電子装置。 - 請求項1乃至3のいずれか一において、
前記データ保持回路は、前記アクセラレータの非動作時において、前記データ保持回路に保持されたデータを電源電圧の供給が停止した状態で保持する機能を有する、電子装置。 - 請求項1乃至4のいずれか一において、
前記スキャンフリップフロップ回路および前記演算回路は、チャネル形成領域にシリコンを有する半導体層を有するトランジスタを有する、電子装置。 - 請求項1乃至5のいずれか一において、
前記メモリ装置は、前記メモリセルを制御する周辺回路を有し、
前記周辺回路が設けられる層は、前記メモリセルが設けられる層と積層して設けられる、電子装置。 - 請求項1乃至6のいずれか一において、
前記演算回路は、積和演算を行う回路である、電子装置。 - 請求項1乃至7のいずれか一において、
前記金属酸化物は、Inと、Gaと、Znと、を含む、電子装置。 - 第1の電子装置と、第2の電子装置と、を有し、
前記第1の電子装置は、
第1の表示部と、第1の無線通信手段と、第1のセンサと、を有し、
前記第2の電子装置は、
第2の表示部と、第2の無線通信手段と、第2のセンサと、を有し、
前記第1の無線通信手段と、前記第2の無線通信手段と、を連動させ前記第1の電子装置と、前記第2の電子装置とを、接続し、
前記第1のセンサ、及び前記第2のセンサに入力されるいずれか一または複数の情報をもとに、
前記第2の表示部に拡張現実、仮想現実、代替現実、または複合現実のいずれか一または複数の表示を行う機能と、
前記第1のセンサに入力された情報をもとに、前記第2の表示部の画像を操作する機能と、を有する、表示システム。 - 請求項9において、
前記第1の電子装置は、請求項1乃至8のいずれか一に記載の電子装置である、表示システム。
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