WO2023044773A1

WO2023044773A1 - Semiconductor structure and manufacturing method therefor, radio frequency circuit, and terminal

Info

Publication number: WO2023044773A1
Application number: PCT/CN2021/120384
Authority: WO
Inventors: 简中祥; 徐向明
Original assignee: 华为技术有限公司
Priority date: 2021-09-24
Filing date: 2021-09-24
Publication date: 2023-03-30
Also published as: CN118043973A

Abstract

Embodiments of the present application relate to the technical field of semiconductors, provide a semiconductor structure and a manufacturing method therefor, a radio frequency circuit, and a terminal, and are used for manufacturing a high-performance semiconductor structure. The semiconductor structure comprises a substrate, comprising a collector region; a base region, provided on the substrate, the base region comprising an intrinsic base region and an outer base region, the intrinsic base region and the outer base region having the same material, and the intrinsic base region being in contact with the collector region; an auxiliary layer, provided on the base region, the auxiliary layer having a first opening; an interlayer protection layer, provided on the auxiliary layer, the interlayer protection layer having a second opening, the second opening being located above the first opening, and the interlayer protection layer being exposed out of the auxiliary layer; and an emission region, provided on the interlayer protection layer, and being in contact with the intrinsic base region by means of the first opening and the second opening.

Description

Semiconductor structure and its preparation method, radio frequency circuit, terminal

technical field

The present application relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof, a radio frequency circuit, and a terminal.

Background technique

Due to the demand for high-performance, low-noise and low-cost radio frequency (Radio Frequency, RF) components in modern communications, semiconductor structures with higher and wider frequency bands have played an increasingly important role. Semiconductor structures with good thermal conductivity, good substrate mechanical properties, better linearity, and higher integration will become the trend of future development.

However, how to use a simple process to complete the processing of the semiconductor structure, so as to reduce the process cost, has become a difficult problem at present. At the same time, it is also crucial to reduce power consumption and increase the maximum oscillation frequency of the device.

Contents of the invention

Embodiments of the present application provide a semiconductor structure and a preparation method thereof, a radio frequency circuit, and a terminal, for preparing a high-performance semiconductor structure.

Silicon germanium heterojunction bipolar transistor (SiGeheterojunction bipolar transistor, SiGe HBT) plays an important role in higher and wider frequency band power amplifiers. With better thermal conductivity and good mechanical properties of the substrate, SiGe HBT has better solved the problem of heat dissipation. SiGe HBT also has better linearity and higher integration. Moreover, SiGe HBT is still a silicon-based technology and has good compatibility with complementary metal oxide semiconductor (CMOS) technology. With the gradual popularization of 5G communication, the technology of integrating CMOS and SiGe HBT on the same chip (CMOS+SiGe HBT integrated process, SiGeBiCMOS) is adopted, and the advantages of fast switching speed and high gain of SiGe HBT and CMOS technology are good at building simple low The advantages of power consumption logic gates are integrated on one chip, which will become the trend of future development. The semiconductor structure provided in the embodiment of the present application may be, for example, a SiGe HBT.

In order to prepare a high-performance semiconductor structure, this application adopts the following technical solutions:

According to a first aspect of the embodiments of the present application, a semiconductor structure is provided, including a substrate, a base region, an auxiliary layer, an interlayer protection layer, and an emission region. The substrate includes a collector area; the base area is arranged on the substrate, and the base area includes an intrinsic base area and an extrinsic base area, and the material of the intrinsic base area and the extrinsic base area is the same, for example, the intrinsic base area and the extrinsic base area are integrated molding structure; the intrinsic base area is in contact with the collector area; the auxiliary layer is disposed on the base area; the auxiliary layer has a first opening; the interlayer protection layer is disposed on the auxiliary layer, the interlayer protection layer has a second opening, and the second opening Located above the first opening; the interlayer protection layer exposes the auxiliary layer; the emission region is arranged on the interlayer protection layer and contacts the intrinsic base region through the first opening and the second opening.

In the semiconductor structure provided by the embodiment of the present application, the materials of the intrinsic base region and the extrinsic base region are the same, the contact effect between the two is good, and the resistance of the base region is low. Moreover, the materials of the intrinsic base region and the extrinsic base region are the same, and the two can be formed into an integrated structure at one time. Therefore, the contact area between the intrinsic base region and the extrinsic base region is large, and the resistance of the base region is low. Therefore, compared with the two structures in which the intrinsic base region and the extrinsic base region are made of different materials, the intrinsic base region and the extrinsic base region are made of the same material in the embodiment of the present application, which can be processed integrally, thereby reducing the resistance of the base region and improving the The highest oscillation frequency of the device. By adopting the structure of auxiliary layer, interlayer protection layer and base area covering layer by layer, the manufacturing cost of the corresponding process is reduced and the performance of the chip is guaranteed. Specifically, the auxiliary layer is disposed on the base region, which can protect the base region and avoid damage to the base region, thereby affecting the resistance of the base region. Furthermore, the interlayer protection layer is arranged between the auxiliary layer and the emission area. On the one hand, it can act as a barrier to the auxiliary layer and the emission area, so that there is no need to limit the material of the auxiliary layer; Bottom side for protection.

In a possible implementation manner, the emitter junction formed by the emitter region and the intrinsic base region is a mirror-symmetrical structure, and the symmetry plane of the emitter junction is perpendicular to the substrate. The first opening on the auxiliary layer and the second opening on the interlayer protection layer are used as self-aligned openings to form a mirror-symmetric emitter junction (E-B). Due to process factors, a deviation of several nanometers may occur. However, unlike the asymmetric structure prepared by using a non-self-aligned process, there will be a deviation of tens of nanometers (the minimum may be more than 20 nanometers), resulting in an asymmetrical emitter junction. It can avoid that due to the asymmetry of the emitter junction, the parasitic collector junction capacitance and the base region resistance on both sides of the symmetrical plane of the emitter junction are different, and the effect of equal current sharing on both sides cannot be achieved, resulting in the inability to minimize the total resistance and capacitance. The mirror symmetry of the emitter junction can minimize the base resistance and collector junction capacitance, thereby increasing the highest oscillation frequency of the device.

In a possible implementation manner, the material of the base region includes silicon germanium or silicon germanium carbon alloy. The base region can be prepared by using conventional materials without changing the process and increasing the cost.

In a possible implementation manner, the material of the auxiliary layer includes polysilicon. The polysilicon auxiliary layer can be equivalent to an extrinsic base region, so as to realize the elevation of the extrinsic base region, thereby reducing the resistance of the base region.

In a possible implementation manner, the semiconductor structure further includes an inner wall, and the inner wall is disposed between the auxiliary layer and the emission region. The inner wall is used to isolate the outer base area and the launch area to avoid mutual interference between the two.

In a possible implementation manner, the inner wall includes a single-layer wall, and the inner wall is arranged on the side of the auxiliary layer and extends to the surface of the intrinsic base. The L-shaped inner wall has a wide coverage and a large barrier area, which can improve the isolation effect between the outer base area and the launch area.

In a possible implementation manner, the projection of the outline of the second opening covers the projection of the outline of the first opening. By setting the profile of the second opening to be larger than the profile of the first opening, that is, setting the interlayer protective layer and the auxiliary layer in a stepped shape, the probability of damage to the inner wall can be reduced and the yield of the inner wall can be improved.

In a possible implementation manner, the projection of the outline of the second opening coincides with the projection of the outline of the first opening. By setting the contour of the second opening to coincide with the contour of the first opening, that is to say, setting the interlayer protective layer and the auxiliary layer to be flush, the probability of damage to the inner wall can be reduced, and the good quality of the inner wall can be improved. Rate.

In a possible implementation manner, the semiconductor structure further includes an outer wall; the outer wall wraps the side of the emission region and is used to protect the emission region. The outer wall can protect the emission region during the preparation of the semiconductor structure, and prevent other epitaxial steps from affecting the emission region.

In a possible implementation manner, the semiconductor structure further includes a capping layer; the capping layer is disposed on the emission region for protecting the emission region. The capping layer can protect the emission region during the preparation of the semiconductor structure, preventing other epitaxial steps from affecting the emission region.

In a possible implementation, the semiconductor structure further includes an emitter, a base, and a collector disposed on the substrate; the emitter is in contact with the emitter region, the base is in contact with the outer base region, and the collector is in contact with the collector region .

In a possible implementation, the substrate further includes a shallow trench isolation region, a lead-out region and a buried layer collector region, the lead-out region and the shallow trench isolation region are located above the buried layer collector region, and the shallow trench isolation region Located between the lead-out region and the collector region; the lead-out region and the collector region are respectively in contact with the buried layer collector region; the collector is in contact with the lead-out region contact connection hole and the collector region; the emitter passes through the cap layer and is connected to the emitter The connection hole in contact with the region is in contact with the emitter region; the base is in contact with the outer base region through the connection hole in contact with the outer base region.

In a possible implementation manner, the semiconductor structure further includes a complementary metal-oxide-semiconductor field-effect transistor, and the complementary metal-oxide-semiconductor field-effect transistor is disposed on the substrate. In this way, the semiconductor structure is a CMOS+SiGe HBT device, and CMOS and SiGe HBT can be integrated on the same chip, which can take advantage of both.

A second aspect of the embodiments of the present application provides a semiconductor structure, including a substrate, a base region, and an emitter region. The substrate includes a collector area; the base area is set on the substrate; the base area includes an intrinsic base area and an extrinsic base area, the material of the intrinsic base area and the extrinsic base area is the same, and the intrinsic base area is in contact with the collector area; The region is arranged on the base region and is in contact with the intrinsic base region; the emitter junction formed by the emitter region and the intrinsic base region is a mirror-symmetrical structure, and the symmetry plane of the emitter junction is perpendicular to the substrate.

In the semiconductor structure provided by the embodiment of the present application, the materials of the intrinsic base region and the extrinsic base region are the same, the contact effect between the two is good, and the resistance of the base region is low. Moreover, the materials of the intrinsic base region and the extrinsic base region are the same, and the two can be formed into an integrated structure at one time. The contact area between the intrinsic base area and the extrinsic base area is large, the resistance of the base area is low, and the highest oscillation frequency of the device can be increased. In addition, the emitter junction is a mirror symmetrical structure, which can avoid the asymmetry of the emitter junction, resulting in the difference between the parasitic collector junction capacitance and the base region resistance on both sides of the emitter junction symmetry plane, which cannot share the current equally on both sides, resulting in the total resistance and Capacitance cannot be minimized. The mirror symmetry of the emitter junction can minimize the base resistance and collector junction capacitance, thereby increasing the highest oscillation frequency of the device.

It should be understood that the semiconductor structure of the second aspect may also have other possible implementation manners. For details, reference may be made to the features of the semiconductor structure in various possible implementation manners of the first aspect, which will not be repeated here.

A third aspect of the embodiments of the present application provides a radio frequency circuit, including a transistor circuit including the semiconductor structure of the first aspect or the second aspect.

A fourth aspect of the embodiments of the present application provides a terminal, including a display screen and the radio frequency circuit of the third aspect.

A fifth aspect of the embodiments of the present application provides a method for preparing a semiconductor structure, including: forming a base film on a substrate, the substrate including a collector region; forming a first sacrificial pattern on the base film, the first sacrificial The pattern is located above the collector region and is used to define the window of the emission region; a second sacrificial film is formed on the substrate with the first sacrificial pattern; an interlayer protective film is formed on the second sacrificial film, and the interlayer protective film is formed on the interlayer protective film. The second opening exposes the first pattern of the second sacrificial film, the first pattern covers the first sacrificial pattern; the interlayer protective film covers the second pattern of the second sacrificial film; the material of the interlayer protective film is different from the material of the second sacrificial film ; removing the first pattern and the first sacrificial pattern; forming an emission region, and patterning the base region film to form a base region; the base region includes an intrinsic base region and an extrinsic base region, and the emission region is in contact with the intrinsic base region.

The method for preparing a semiconductor structure provided in the embodiment of the present application uses a base film to directly prepare a base region including an intrinsic base region and an extrinsic base region. The intrinsic base region and the extrinsic base region are integrally formed structures of the same material, and the contact area Large, good contact effect, low base resistance. Moreover, the embodiment of the present application uses a self-aligned structure and a non-selective epitaxial process to prepare the emitter junction (consisting of an intrinsic base region and an emitter region), and the preparation of each film layer in the semiconductor structure can be realized by using conventional techniques. It does not need to adopt a selective epitaxy process with high process difficulty, has low process requirements and low preparation cost. In addition, the embodiment of the present application uses the first sacrificial pattern as the self-alignment structure, and the first sacrificial pattern can be used to realize the self-alignment of the emitter junction (E-B). In this way, the prepared emission junction is a mirror-symmetrical structure, and based on process factors, there may be a deviation of several nanometers. However, unlike the asymmetric structure prepared by using a non-self-aligned process, there will be a deviation of tens of nanometers (the minimum may be more than 20 nanometers), resulting in an asymmetrical emitter junction. The asymmetry of the emitter junction leads to the difference between the parasitic collector junction capacitance and the base region resistance on both sides of the emitter junction midline, which cannot achieve the effect of sharing current on both sides, resulting in the inability to minimize the total resistance and capacitance, while the symmetry on both sides can play a role Minimize the effect of base resistance and collector junction capacitance, thereby increasing the highest oscillation frequency of the device. Moreover, the preparation of each film layer in the embodiment of the present application can be realized by using conventional technology, which requires relatively low process requirements and low preparation cost.

In a possible implementation manner, forming the emission region and patterning the base region film to form the base region includes: forming the emission region film on the substrate; patterning the film layer on the side of the base region film away from the substrate , forming an emission region and exposing the base region film; patterning the base region film to form a base region and define an outer base region pattern. An implementation.

In a possible implementation manner, forming the emission region and patterning the base region film to form the base region includes: forming the emission region film on the substrate; patterning the film layer on the side of the second pattern away from the substrate , forming an emission area, and exposing the second pattern; removing the second pattern, and forming a polysilicon pattern at a corresponding position; patterning the base film and the polysilicon pattern, forming a base area, and defining an outer base area pattern. By replacing the second pattern with a polysilicon pattern, the finally formed polysilicon auxiliary layer can be equivalent to an extrinsic base region, so as to realize the elevation of the extrinsic base region and increase the doping concentration of the extrinsic base region, thereby reducing the resistance of the base region.

In a possible implementation manner, before removing the second pattern and forming the polysilicon pattern at the corresponding position, the method further includes: forming an outer wall around the emission area, the outer wall wraps at least the side of the emission area. Before forming the polysilicon pattern, a layer of outer wall is wrapped around the emission area, which can protect the emission area during the subsequent growth process of the auxiliary polysilicon layer.

In a possible implementation manner, forming the first sacrificial pattern on the base film includes: sequentially forming a first dielectric film and a second dielectric film on the base film, the crystal lattice of the first dielectric film and the base film The degree of mismatch is smaller than the degree of lattice mismatch between the second dielectric film and the base film; the first dielectric film and the second dielectric film are patterned to form a stacked first dielectric pattern and a second dielectric pattern, as the first sacrificial pattern. By setting the first sacrificial pattern to include the first dielectric pattern and the second dielectric pattern arranged in layers, when the first sacrificial pattern is subsequently removed, the second dielectric pattern can be removed first, and at this time the first dielectric pattern can affect the base region film. Protect and then remove the first dielectric pattern. Since the lattice mismatch between the first dielectric pattern and the base film is smaller than the lattice mismatch between the second dielectric pattern and the base film, that is, the gap between the first dielectric pattern and the base film The connection stress is smaller than the connection stress between the second dielectric pattern and the base film. Therefore, making the first dielectric pattern in contact with the base film can reduce damage to the base film when removing the first sacrificial pattern.

In a possible implementation manner, the material of the second dielectric film is the same as that of the second sacrificial film; removing the first pattern and the first sacrificial pattern includes: removing the first pattern and the second dielectric pattern; removing the first dielectric pattern. By making the material of the second dielectric film the same as that of the second sacrificial film, the first pattern and the second dielectric pattern can be removed synchronously, reducing process steps.

In a possible implementation manner, the process of removing the first pattern and the first sacrificial pattern further includes: processing the second opening, so that the projection of the outline of the second opening covers the projection of the outline of the first opening. By arranging the interlayer protective film and the second pattern in a stepped shape, the second pattern located in the lower layer is closer to the window of the emission region. In this way, due to the fact that the second pattern is concave relative to the interlayer protective film (the interlayer protective film on the upper layer is closer to the window of the emission region), the film at the layer where the second pattern is located can be avoided in the process of forming subsequent film layers. Layer formation is too slow, and the film layer at the layer where the interlayer protective film is located is formed too fast, resulting in the surface of the film layer being sealed, but there are air bubbles inside, and the film layer cannot be in good contact with the base film, which affects product performance.

In a possible implementation manner, the process of removing the first pattern and the first sacrificial pattern further includes: processing the second opening so that the projection of the outline of the second opening coincides with the projection of the outline of the first opening . In this way, due to the fact that the second pattern is concave relative to the interlayer protective film (the interlayer protective film on the upper layer is closer to the window of the emission region), the film at the layer where the second pattern is located can be avoided in the process of forming subsequent film layers. Layer formation is too slow, and the film layer at the layer where the interlayer protective film is located is formed too fast, resulting in the surface of the film layer being sealed, but there are air bubbles inside, and the film layer cannot be in good contact with the base film, which affects product performance.

In a possible implementation manner, forming an interlayer protective film on the second sacrificial film includes: forming an interlayer protective film layer on the second sacrificial film, where the interlayer protective film layer covers the first pattern and the second pattern; A second opening is formed on the interlayer protection film layer, and the second opening exposes the first pattern to form an interlayer protection film.

In a possible implementation manner, before forming the emission region, the manufacturing method further includes: forming an inner wall, the inner wall covers the second pattern and the side of the interlayer protective film facing the window of the emission region.

In a possible implementation manner, forming the inner wall includes: forming a third dielectric film on the interlayer protective film, the third dielectric film forming a groove at the window of the emission region; forming a fourth dielectric film on the third dielectric film film; the lattice mismatch between the third dielectric film and the base film is smaller than the lattice mismatch between the fourth dielectric film and the base film; the fourth dielectric film is patterned to form a second wall, and the second wall The body covers the side of the groove; the part of the third dielectric film not covered by the second wall is removed to form the first wall. In this way, when the third dielectric film and the fourth dielectric film are patterned, the connection stress between the third dielectric film and the base film is small, which can reduce the stress on the base region when the third dielectric film is patterned. membrane damage.

In a possible implementation manner, forming the inner wall further includes: removing the second wall. In the case where the inner wall only includes a single-layer wall body, the opening of the emission area window is relatively large, and the finally formed emission area has a large area and low resistance.

In a possible implementation manner, before forming the emission region, the manufacturing method further includes: forming a cap film on the emission region film. The cap film can protect the emitter film during the preparation process.

In a possible implementation manner, the manufacturing method further includes: forming a complementary metal oxide semiconductor field effect transistor on the substrate. CMOS and SiGe HBT can be integrated on the same chip to meet different needs.

Description of drawings

Fig. 1 is the schematic diagram of the preparation process of a kind of SiGe HBT structure provided by related art;

Fig. 2 is a schematic diagram of the preparation process of a semiconductor structure provided in the embodiment of the present application;

3A-3O are schematic diagrams of the preparation process of a semiconductor structure provided in the embodiment of the present application;

4A-4G are schematic diagrams of part of the preparation process of another semiconductor structure provided by the embodiment of the present application;

5A-5H are schematic diagrams of a partial preparation process of another semiconductor structure provided in the embodiment of the present application;

FIG. 5I is a schematic diagram of a semiconductor structure provided by an embodiment of the present application;

FIG. 6 is a schematic diagram of a semiconductor structure of a CMOS+SiGe HBT provided in an embodiment of the present application.

Detailed ways

The following will describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them.

Hereinafter, in the embodiments of the present application, terms such as "first" and "second" are used for convenience of description only, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, a feature defined as "first", "second", etc. may expressly or implicitly include one or more of that feature. In the description of the present application, unless otherwise specified, "plurality" means two or more.

In the embodiment of the present application, "upper", "lower", "left" and "right" are not limited to be defined relative to the schematic placement orientations of the components in the drawings, and it should be understood that these directional terms may be relative concepts , which are used for description and clarification relative to , which may change accordingly according to changes in the orientation in which parts of the drawings are placed in the drawings.

In the embodiment of the present application, unless the context requires otherwise, throughout the description and claims, the term "comprising" is interpreted as an open and inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplarily" or "some examples" are intended to indicate particular features associated with the embodiment or examples , structure, material or characteristic is included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited by the context herein.

In the embodiment of this application, "and/or" is just a kind of relationship describing the relationship between related objects, which means that there may be three kinds of relationships, for example, A and/or B, which can mean that A exists alone, and A and B exist at the same time. B, there are three situations of B alone. In addition, the character "/" in this article generally indicates that the contextual objects are an "or" relationship.

Exemplary embodiments are described in the embodiments of the present application with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

SiGe heterojunction bipolar transistor (SiGe HBT) has better thermal conductivity and good mechanical properties of the substrate, which better solves the heat dissipation problem of semiconductor structures. Moreover, SiGe HBT also has better linearity, higher integration, and good compatibility with complementary metal oxide semiconductor (CMOS) technology. Therefore, it is widely used in the fields of optoelectronics, radio frequency, microwave, etc., especially in high-frequency devices in the above-mentioned fields. For example, some high-frequency analog devices using photoelectric high-speed transmission technology and microwave high-frequency technology, the high-frequency analog devices obtained by using SiGe BiCMOS structure have both the speed block of SiGe HBT structure, high gain, low noise, and low power consumption of CMOS devices. Advantage.

However, how to prepare a high-performance SiGe HBT structure has become a technical problem that is continuously studied by those skilled in the art.

In some embodiments, as shown in FIG. 1 , the inner wall (inner spacer) as a self-aligned double polysilicon self-alignment (double poly selfalign, DPSA) structure, based on a selective epitaxy growth (SEG) process, to form an intrinsic base region.

However, this type of SiGe epitaxy is realized through the SEG process to ensure that the epitaxy grows on the exposed substrate instead of on the dielectric mask, which requires high epitaxy equipment and harsh process conditions.

Moreover, since the connection between the intrinsic base region and the extrinsic base region is also achieved through SEG epitaxy, the filling state of the SEG process and the inability to ensure that the connection between the intrinsic base region and the extrinsic base region is connected in a high doping concentration region, resulting in extrinsic base region There is a lower limit for the connection resistance between the region and the intrinsic base region, which cannot be further reduced, thereby limiting the improvement of high-frequency performance.

Based on this, the embodiment of the present application uses a non-selective epitaxial growth (NSEG) process as a SiGe epitaxial process to prepare a high-performance SiGe HBT structure.

As shown in Figure 2, the fabrication method of the semiconductor structure includes:

S10 , as shown in FIG. 3A , forming a substrate 10 .

Wherein, the embodiment of the present application does not limit the structure and formation method of the substrate 10, as long as the substrate 10 includes a collector region and can lead to a collector electrode (collector electrode, C) of a SiGe HBT.

Exemplarily, as shown in FIG. 3A , the substrate 10 includes a silicon substrate 11, a collector region 12 disposed on the silicon substrate 11, a buried layer collector region 13, a sinker 14, and a shallow trench isolation region 15, The collector region 12 and the lead-out region 14 are located above the buried layer collector region 13 , and a shallow trench isolation region 15 is provided between the collector region 12 and the lead-out region 14 . The lead-out region 14 and the collector region 12 are respectively in contact with the buried layer collector region 13, the collector region 12 is connected to the lead-out region 14 through the buried layer collector region 13, and then the collector is led out through the contact hole.

The formation method of the substrate 10, for example, may be to epitaxially grow a layer of epitaxial layer on the silicon substrate 11; then carry out ion implantation in the epitaxial layer to form the collector region 12, the buried layer collector region 13, and the lead-out region 14, wherein The ion implantation of the buried layer collector region 13 can be implanted before forming the epitaxial layer, and then diffused into the epitaxial layer by high temperature. It can also be obtained by performing ion implantation after forming the epitaxial layer; and then forming the shallow trench isolation region 15 .

S20 , as shown in FIG. 3B , forming a base region film 20 on the substrate 10 .

For example, the base region film 20 may be formed by using an epitaxial growth process. The material of the base film 20 may include SiGe (silicon germanium), SiGeC (silicon germanium carbon) alloy, for example.

S30 , as shown in FIG. 3C , forming a first sacrificial pattern 30 on the base region film 20 , and the first sacrificial pattern 30 is used to define an emission region window.

Wherein, the emission region window can be understood as an area where the emission region is to be formed. The emitter window is located above the collector region 12 , therefore, the first sacrificial pattern 30 is also located above the collector region 12 .

In some embodiments, the method of forming the first sacrificial pattern 30 on the base film 20 includes:

S31 , as shown in FIG. 3C , sequentially forming a first dielectric film 31 and a second dielectric film 32 on the base film 20 .

Wherein, the materials of the first dielectric film 31 and the second dielectric film 32 are different.

In some embodiments, the lattice mismatch between the first dielectric film 31 and the base film 20 is smaller than the lattice mismatch between the second dielectric film 32 and the base film 20 .

For example, the materials of the first dielectric film 31 and the second dielectric film 32 can be silicide, for example.

Exemplarily, the material of the first dielectric film 31 is silicon-containing oxide. For example, the material of the first dielectric film 31 is silicon oxide, silicon oxynitride, or oxygen-rich silicon dioxide.

Exemplarily, the material of the second dielectric film 32 is silicon nitride. For example, the material of the second dielectric film 32 is silicon nitride.

The first dielectric film 31 and the second dielectric film 32 can be formed, for example, by chemical vapor deposition (chemical vapor deposition, CVD) process to form the first dielectric film 31 and the second dielectric film 32 .

S32. As shown in FIG. 3C , pattern the first dielectric film 31 and the second dielectric film 32 to form stacked first dielectric patterns 33 and second dielectric patterns 34 as the first sacrificial patterns 30 .

For example, the first dielectric film 31 and the second dielectric film 32 can be patterned by photolithography and etching processes. Depending on the selected process, the first dielectric film 31 and the second dielectric film 32 can be patterned simultaneously, or the first dielectric film 31 and the second dielectric film 32 can be patterned step by step.

By selecting different materials for the first dielectric film 31 and the second dielectric film 32 , the materials of the first dielectric pattern 33 and the second dielectric pattern 34 formed after patterning are also different. The first sacrificial pattern 30 includes a first dielectric pattern 33 and a second dielectric pattern 34 that are stacked. When the first sacrificial pattern 30 is subsequently removed, the second dielectric pattern 34 can be removed first. At this time, the first dielectric pattern 33 can be used for The base film 20 is protected, and then the first dielectric pattern 33 is removed. Since the lattice mismatch between the first dielectric pattern 33 and the base film 20 is smaller than the lattice mismatch between the second dielectric pattern 34 and the base film 20, that is, the first dielectric pattern 33 and the base film 20 The connection stress between the base film 20 is smaller than the connection stress between the second dielectric pattern 34 and the base film 20 . Therefore, making the first dielectric pattern 33 in contact with the base film 20 can reduce the damage to the base film 20 when the first sacrificial pattern 30 is removed.

Alternatively, as an example, the method for forming the first sacrificial pattern 30 on the base film 20 includes:

A dielectric film is formed on the base film 20 and then patterned to form a first sacrificial pattern 30 . That is to say, the first sacrificial pattern 30 can also be a single-layer structure, and the process is simple.

S40 , as shown in FIG. 3D , forming a second sacrificial film 40 on the substrate 10 formed with the first sacrificial pattern 30 .

A method of forming the second sacrificial film 40 may be, for example, a CVD process may be used to form the second sacrificial film 40 .

The material of the second sacrificial film 40 may be silicide, for example. Exemplarily, the material of the second sacrificial film 40 is silicon oxide, silicon nitride, silicon oxynitride, or oxygen-rich silicon dioxide.

In some embodiments, the first sacrificial pattern 30 is a single film layer, and the material of the second sacrificial film 40 is the same as that of the first sacrificial pattern 30 .

In some other embodiments, the first sacrificial pattern 30 includes a first dielectric pattern 33 and a second dielectric pattern 34 stacked, and the material of the second sacrificial film 40 and the second dielectric pattern 34 (that is, the second dielectric film 32) of the same material.

In this way, when the first sacrificial pattern 30 and the first pattern 41 of the second sacrificial film 40 are subsequently removed, they can be removed simultaneously, reducing process steps.

S50 , as shown in FIG. 3E , forming an interlayer protective film 50 on the second sacrificial film 40 .

Wherein, the second opening 51 included in the interlayer protective film 50 exposes the first pattern 41 of the second sacrificial film 40 , the first pattern 41 covers the first sacrificial pattern 30 , and the interlayer protective film 50 covers the second pattern 41 of the second sacrificial film 40 . Pattern 42.

In some embodiments, forming the interlayer protection film 50 on the second sacrificial film 40 includes:

S51 , as shown in FIG. 3E , an interlayer protective film layer is formed on the second sacrificial film 40 , and the interlayer protective film layer covers the first pattern 41 and the second pattern 42 . That is, the interlayer protective film layer covers the second sacrificial film 40 .

Wherein, the material of the interlayer protective film layer may be a dielectric material, and the material of the interlayer protective film layer is, for example, silicide. Exemplarily, the material of the interlayer protective film layer is silicon oxide, silicon nitride, silicon oxynitride, or oxygen-rich silicon dioxide.

In some embodiments, the material of the interlayer protective film 50 is different from that of the second sacrificial film 40 . To ensure that the first pattern 41 of the second sacrificial film 40 is removed, the interlayer protective film 50 can protect the second pattern 42 of the second sacrificial film 40 .

As a way of forming the interlayer protective film layer, for example, a CVD process may be used to form the interlayer protective film layer.

S52, as shown in FIG. 3E , forming a second opening 51 on the interlayer protection film layer, and the second opening 51 exposes the first pattern 41 to form the interlayer protection film 50 .

For example, chemical mechanical polishing (CMP) can be used to grind the interlayer protection film layer to expose the first pattern 41 . That is, the interlayer protective film 50 is flush with the first pattern 41 .

Of course, the interlayer protection film 50 having the second opening 51 can also be directly formed by controlling the process. The above method is only an illustration, without any limitation.

S60 , as shown in FIG. 3F , removing the first pattern 41 and the first sacrificial pattern 30 .

Regarding the manner of removing the first pattern 41 and the first sacrificial pattern 30 , in some embodiments, the material of the second dielectric pattern 34 is different from that of the second sacrificial film 40 . Removing the first pattern 41 and the first sacrificial pattern 30 includes: removing the first pattern 41 first, and then removing the first sacrificial pattern 30 (removing the second dielectric pattern 34 first, and then removing the first dielectric pattern 33 ).

In other embodiments, the material of the second dielectric pattern 34 (that is, the second dielectric film 32 ) is the same as that of the second sacrificial film 40 . For example, the materials of the second dielectric pattern 34 and the second sacrificial film 40 are both silicon nitride. The material of the first dielectric pattern 33 is silicon oxide.

As shown in FIG. 3F , removing the first pattern 41 and the first sacrificial pattern 30 includes:

S61 , removing the first pattern 41 and the second medium pattern 34 .

S62 , removing the first dielectric pattern 33 .

Wherein, for example, a wet etching process may be used to remove the first pattern 41 and the first sacrificial pattern 30 , and different etching solutions are used for different materials.

As shown in FIG. 3F , after removing the first pattern 41 and the first sacrificial pattern 30 , the window opening of the emission area can be completed, and the subsequent process can be performed through the window opening of the emission area for self-alignment.

In some embodiments, as shown in FIG. 3G , the process of removing the first pattern 41 and the first sacrificial pattern 30 also includes processing the second opening 51 so that the projection of the outline of the second opening 51 covers the first Projection of the contour of the opening 421 . That is, to make the surface of the interlayer protection film 50 facing the emission region window W away from the emission region window W relative to the surface of the second pattern 42 facing the emission region window W. That is to say, the interlayer protective film 50 and the second pattern 42 form a stepped shape.

For example, the material of the first dielectric pattern 33 (that is, the first dielectric film 31 ) is the same as that of the interlayer protection film 50 .

As shown in FIG. 3G, while removing the first dielectric pattern 33, the second opening 51 can be enlarged at the same time by controlling the process (such as the time of wet etching), and the interlayer protective film 50 and the second pattern 42 form a step. shape.

It can be understood that, in this case, the interlayer protective film 50 will also be thinned while removing the first dielectric pattern 33 .

Certainly, after removing the first pattern 41 and the first sacrificial pattern 30, the second opening 51 may be enlarged separately, so that the surface a of the interlayer protective film 50 facing the window W of the emission region is opposite to the second pattern 42 facing the emission region. The surface b of the region window W is remote from the emission region window W.

By arranging the interlayer protection film 50 and the second pattern 42 in a stepped shape, the second pattern 42 on the lower layer is closer to the window W of the emission region. In this way, it can be avoided that the second pattern 42 is recessed relative to the interlayer protective film 50 (the upper interlayer protective film 50 is closer to the window W of the emission region), causing the second pattern 42 to be damaged during the formation of subsequent film layers. The film layer at the layer where the layer is formed is too slow, and the film layer at the layer where the interlayer protective film 50 is located is formed too quickly, causing the surface of the film layer to be sealed, but there are bubbles inside, and the film layer cannot be in good contact with the base film 20, affecting Product performance.

S70 , as shown in FIG. 3H , forming an inner wall 60 .

Wherein, the inner wall 60 covers the side of the second pattern 42 and the interlayer protection film 50 facing the window W of the emission region.

In some embodiments, forming inner wall 60 includes:

S71 , as shown in FIG. 3H , forming a third dielectric film 61 on the interlayer protection film 50 , and the third dielectric film 61 forms a groove U at the window W of the emission region.

Wherein, the material of the third dielectric film 61 may be a dielectric material, and the material of the third dielectric film 61 is, for example, silicide. Exemplarily, the material of the third dielectric film 61 is silicon oxide, silicon nitride, silicon oxynitride, or oxygen-rich silicon dioxide.

The method of forming the third dielectric film 61 may be, for example, a CVD process to form the third dielectric film 61 .

S72 , as shown in FIG. 3H , forming a fourth dielectric film 62 on the third dielectric film 61 .

Wherein, the material of the fourth dielectric film 62 may be a dielectric material, and the material of the fourth dielectric film 62 is, for example, silicide. Exemplarily, the material of the fourth dielectric film 62 is silicon oxide, silicon nitride, silicon oxynitride, or oxygen-rich silicon dioxide.

The method of forming the fourth dielectric film 62 may be, for example, a CVD process to form the fourth dielectric film 62 .

The material of the third dielectric film 61 is different from the material of the fourth dielectric film 62 . In some embodiments, the lattice mismatch between the third dielectric film 61 and the base film 20 is smaller than the lattice mismatch between the fourth dielectric film 62 and the base film 20 .

For example, the material of the third dielectric film 61 is silicon oxide, and the material of the fourth dielectric film 62 is silicon nitride.

S73 , as shown in FIG. 3H , pattern the fourth dielectric film 62 to form a second wall 63 , and the second wall 63 covers the side of the groove U.

For example, a dry etching process may be used to pattern the fourth dielectric film 62 to form the second wall 63 .

S74 , as shown in FIG. 3H , removing the part of the third dielectric film 61 not covered by the second wall body 63 to form the first wall body 64 .

For example, the third dielectric film 61 can be patterned by using dry etching or wet etching process to form the first wall body 64 .

As shown in FIG. 3H , the inner wall 60 of the semiconductor structure includes a first wall 64 and a second wall 63 . Wherein, the first wall body 64 is disposed on the side of the second pattern 42 and extends to the surface of the base film 20 . The inner wall 60 exposes the base film 20 .

In this way, when the third dielectric film 61 and the fourth dielectric film 62 are patterned, the connection stress between the third dielectric film 61 and the base film 20 is small, and the patterning of the third dielectric film 61 can be reduced. damage to the base film 20 during the chemical transformation. Of course, it is also possible to only form the third dielectric film, and then pattern the third dielectric film to form the inner wall 60 . That is to say, the inner wall 60 only includes a single-layer wall.

S80 , as shown in FIG. 3I , forming an emission region film 70 on the substrate 10 formed with the inner wall 60 .

Wherein, the material of the emitter region film 70 can be, for example, doped epitaxial single crystal silicon or polycrystalline silicon, and the emitter region film 70 can also be doped in situ to increase the doping concentration.

For example, the emitter region film 70 may be formed by using an epitaxial growth process. The emitter film 70 covers the interlayer protective film 50 , and the inner wall 60 .

S90 , as shown in FIG. 3J , forming a cap film 80 on the emitter film 70 .

Wherein, the material of the capping film 80 may be a dielectric material, and the material of the capping film 80 is, for example, silicide. Exemplarily, the material of the capping film 80 is silicon oxide, silicon nitride, silicon oxynitride, or oxygen-rich silicon dioxide.

The way of forming the capping film 80 , for example, can adopt CVD process to form the capping film 80 , and the capping film 80 covers the emission region film 70 .

S100 , as shown in FIG. 3K , pattern the film layer on the side of the second pattern 42 away from the substrate 10 to form an emission region 79 and expose the second pattern 42 .

Exemplarily, as shown in FIG. 3J , the film layer located on the side of the second pattern 42 away from the substrate 10 (or understood as the film layer located above the second pattern 42 ) includes an interlayer protective film 50, an emission region film 70 and a capping film 80 . The interlayer protection film 50 , the emitter region film 70 and the capping film 80 are patterned by photolithography and etching processes to form the interlayer protection layer 59 , the emitter region 79 and the capping layer, and expose the second pattern 42 .

Wherein, the patterning of the interlayer protection film 50 , the emission region film 70 and the capping film 80 may be completed in multiple processes, or may be completed in the same process. The specific patterns of the structures remaining after patterning of the interlayer protective film 50 , the emitting region film 70 and the capping film 80 are not limited, and can be reasonably set as required.

In this example, after step S60 is performed, the first pattern 41 and the first sacrificial pattern 30 are removed, and the window opening of the emission region can be completed to expose the window W of the emission region. The emission region film 70 formed in step S80 covers the emission region window W, and self-aligns through the emission region window W, so that the emission region 79 formed in step S100 and the intrinsic base region in the subsequently formed base region 29 constitute an emission region. A mirror-symmetrical structure.

S110 , as shown in FIG. 3L , form an outer wall 9 on the periphery of the emission area 79 , and the outer wall 9 wraps at least a side surface of the emission area 79 .

Wherein, the material of the outer wall 9 may be a dielectric material, and the material of the outer wall 9 is, for example, silicide. Exemplarily, the material of the outer wall 9 is silicon oxide, silicon nitride, silicon oxynitride, or oxygen-rich silicon dioxide.

The outer wall 9 may be formed, for example, by using a CVD process to form a protective film, and then using anisotropic dry etching to etch the protective film to form the outer wall 9 . The outer wall 9 wraps around the periphery of the launch area 79 , and the outer wall 9 at least wraps the sides of the launch area 79 .

In some embodiments, as shown in FIG. 3L , the outer wall 9 wraps the sides of the interlayer protection layer 59 , the emitting region 79 and the capping layer 89 .

By wrapping a layer of outer wall 9 around the emitter region 79, the emitter region 79 can be protected during the subsequent growth process of the auxiliary polysilicon layer.

Of course, step S110 may not be executed, and subsequent steps may be directly executed.

S120 , as shown in FIG. 3M , removing the second pattern 42 and forming a polysilicon pattern 90 at a corresponding position.

For example, the second pattern 42 may be removed through a wet etching process. The polysilicon pattern 90 is formed by a selective epitaxial growth process at the position corresponding to the original second pattern 42 , and the outer wall 9 serves to protect the emission region 79 to ensure that no additional polysilicon layer grows on the side of the emission region.

Wherein, the material of the polysilicon pattern 90 may be, for example, polysilicon or polysilicon silicide.

In some embodiments, in-situ doping can also be performed on the polysilicon pattern 90 .

By replacing the second pattern 42 with the polysilicon pattern 90, the polysilicon pattern 90 can be used as an equivalent extrinsic base region, which is equivalent to increasing the thickness of the extrinsic base region, realizing the elevation of the extrinsic base region and increasing the doping of the extrinsic base region concentration, reducing the resistance of the extrinsic base region. Therefore, the polysilicon pattern 90 can be used as an extrinsic base elevation to effectively reduce the resistance of the extrinsic base.

Of course, step S120 may not be executed, and subsequent steps may be directly executed after step S100 is executed.

S130 , as shown in FIG. 3N , pattern the base region film 20 and the polysilicon pattern 90 to form a base region 29 .

Wherein, the base region 29 includes an intrinsic base region and an extrinsic base region, the intrinsic base region is in contact with the collector region 12, the extrinsic base region is located at the periphery of the intrinsic base region, and the pattern of the extrinsic base region can be defined by performing step S130.

For example, the polysilicon pattern 90 and the base region film 20 may be patterned by photolithography and etching processes, as shown in FIG. 3N , to form the auxiliary layer and the base region 29 . In this case, the auxiliary layer is prepared from the polysilicon pattern 90, and the material of the auxiliary layer is polysilicon. In the embodiment of the present application, the auxiliary layer made of polysilicon is referred to as the first auxiliary layer 99 .

Wherein, the patterning of the polysilicon pattern 90 and the base region film 20 may be completed in multiple processes, or may be completed in the same process. The embodiment of the present application does not limit the specific pattern of the structure remaining after the polysilicon pattern 90 and the base region film 20 are patterned, and it can be reasonably set as required.

It should be noted that the above-mentioned method for preparing the base region 29 is only an illustration, and the embodiment of the present application is not limited to the fact that the intrinsic base region and the extrinsic base region are prepared by integral molding, and the two can also be prepared in steps As a result, the material of the intrinsic base region and the extrinsic base region may be the same.

S140 , performing heat treatment on the semiconductor structure.

Heat treatment (such as annealing) is performed on the structure obtained in FIG. 3N to adjust the doping distribution in the emitter region 79 , the base region 29 and the collector region 12 to improve the activity of dopant ions.

S150, as shown in FIG. 3O, draw the emitter electrode (emitter electrode, E) from the emitter region 79 through the contact hole (contact) 100, draw the base electrode (base electrode, B) from the base region 29 through the contact hole 100, and pass the contact hole 100 draws the collector electrode C from the collector region 12 .

It can be understood that the base B is drawn from the base region 29 , in fact, the base B is drawn from the outer base region in the base region 29 .

Wherein, before step S150 is performed, the capping layer 89 may be patterned to form a via hole to expose the emitter region 79 so as to lead the emitter E from the via hole through the contact hole 100 . Certainly, the step of forming the via hole on the capping layer 89 may also be formed synchronously with other processes in the manufacturing process, which is not limited in this embodiment of the present application.

The semiconductor structure obtained through the above steps S10-S150 is the HBT device. As shown in Figure 3O, the semiconductor structure includes:

The substrate 10 includes a silicon base 11, a collector region 12 disposed on the silicon substrate 11, a buried layer collector region 13, a sinker 14 and a shallow trench isolation region 15, and the collector region 12 and the lead-out region 14 are located Above the buried collector region 13 , a shallow trench isolation region 15 is provided between the collector region 12 and the lead-out region 14 . The collector region 12 is connected to the lead-out region 14 via the buried layer collector region 13 , and then the collector electrode C is led out through the contact hole 100 .

The base region 29 is disposed on the substrate 10; the base region 29 includes an intrinsic base region and an extrinsic base region, and the extrinsic base region is located at the periphery of the intrinsic base region. The material of the intrinsic base region is the same as that of the extrinsic base region; the intrinsic base region is in contact with the collector region 12 and the emitter region 79 . The intrinsic base region and collector region 12 form a collector junction (C-B). The material of the base region 29 can be, for example, SiGe or SiGe:C alloy, and the intrinsic base region and the extrinsic base region in the base region 29 can be formed into an integral structure at one time, for example.

Wherein, the intrinsic base region refers to the part of the base region 29 in contact with the emitter region and the collector region, and the intrinsic base region is used to form an emitter junction with the emitter region and a collector junction with the collector region. The extrinsic base region refers to the peripheral part of the intrinsic base region, and the extrinsic base region is used to realize the interconnection between the intrinsic base region and the base.

The first auxiliary layer 99 is disposed on the base region 29 , and the first auxiliary layer 99 has a first opening exposing the intrinsic base region in the base region 29 .

Wherein, depending on whether step S120 is performed, the materials of the auxiliary layer are different. In the case of performing step S120, the material of the auxiliary layer includes polysilicon. In this case, the first auxiliary layer 99 is connected to the extrinsic base region in the base region 20 , and can be used as an extrinsic base region to raise the extrinsic base region to reduce the resistance of the extrinsic base region.

The interlayer protection layer 59 is disposed on the first auxiliary layer 99, the interlayer protection layer 59 has a second opening, the second opening is located above the first opening, and the second opening exposes the first opening; the interlayer protection layer 59 is far away from the second opening One side (peripheral side) also exposes the first auxiliary layer 99 . The material of the interlayer protective layer 59 may be, for example, silicon oxide.

The projection of the contour of the second opening overlays the projection of the contour of the first opening. That is, the second opening is larger than the first opening. Alternatively, the interlayer protection layer 59 faces the surface a of the first opening, and the first auxiliary layer 99 faces the surface b of the first opening, away from the first opening. That is to say, the interlayer protective layer 59 and the first auxiliary layer 99 form a stepped shape on the side facing the first opening.

The emitter region 79 is disposed on the interlayer protection layer 59 and is in contact with the intrinsic base region in the base region 29 through the first opening and the second opening. The emitter region 79 forms an emitter junction (E-B) with the intrinsic base region. The material of the emitter region 79 can be, for example, doped epitaxial monocrystalline silicon or polycrystalline silicon.

In some embodiments, the emitter junction formed by the emitter region 79 and the intrinsic base region is a mirror-symmetrical structure, and the symmetry plane of the emitter junction is perpendicular to the substrate 10 .

It can be understood that the size deviation within the range of process error (within ±10 nanometers) belongs to the mirror image symmetry in the embodiment of the present application.

The inner wall 60 is disposed between the first auxiliary layer 99 and the emission area 79 .

Wherein, the inner wall 60 includes a first wall 64 and a second wall 63 stacked in a direction toward the first opening, and the materials of the second wall 63 and the first wall 64 are different. The material of the second wall body 63 may be, for example, silicon nitride, and the material of the first wall body 64 may be, for example, silicon oxide.

Based on this, it can be understood that other structures may be filled in the first opening and the second opening. However, the contour of the inner wall 60 in contact with the interlayer protective layer 59 is the contour of the first opening, and the contour of the inner wall 60 in contact with the first auxiliary layer 99 is the contour of the second opening.

The capping layer 89 is disposed on the emitting area 79 to cover the emitting area 79 for protecting the emitting area 79 . The material of the capping layer 89 can be, for example, silicon oxide.

The outer wall 9 wraps the sides of the launch area 79 for protecting the launch area 79 . The material of the outer wall 9 can be, for example, silicon oxide.

The collector electrode C is in contact with the lead-out region 14 , the buried layer collector region 13 and the collector region 12 through the connection hole 100 in contact with the lead-out region 14 . The connection hole 100 may be directly disposed on the surface of the lead-out region 14 , and a metal silicide layer may also be disposed between the connection hole 100 and the lead-out region 14 to realize the contact between the connection hole 100 and the lead-out region 14 .

An emitter electrode (E) is in contact with the emitter region 79 through a connection hole 100 passing through the cap layer 89 and in contact with the emitter region 79 . The connection hole 100 may be directly disposed on the surface of the emission region 79 , and a metal silicide layer may also be disposed between the connection hole 100 and the emission region 79 to realize the contact between the connection hole 100 and the emission region 79 .

A base electrode (B) is in contact with the extrinsic base region in the base region 29 through a connection hole 100 in contact with the extrinsic base region in the base region 29 . The connection hole 100 can be directly disposed on the surface of the base region 29 , and a metal silicide layer can also be disposed between the connection hole 100 and the base region 29 to realize the contact between the connection hole 100 and the outer base region in the base region 29 .

It should be understood that, in the case where the emitting region 79 , the base region 29 and the lead-out region 14 are covered with a dielectric layer, the connection hole 100 must pass through the dielectric layer.

Taking the NPN type HBT device as an example, the emitter E is used to emit electrons, the base B is used to control electrons (the current flowing to the collector C is controlled by the input signal of the base B), and the collector C is used to collect electrons.

It should be noted that the SiGe HBT transistor in the above-mentioned semiconductor structure can be an NPN transistor (the base region 29 is a P region, that is, a P-type semiconductor; the emitter region 79 and the collector region 12 are both N regions, that is, an N-type semiconductor ) or a PNP transistor (the base region 29 is an N region, that is, an N-type semiconductor; the emitter region 79 and the collector region 12 are both P regions, that is, a P-type semiconductor).

In addition, the structure, position, and quantity of the emitter E, base B, and collector C shown in the schematic diagram of the embodiment of the present application are only for illustration. There may be only one emitter E, base B, and collector C each.

Wherein, the material of the film layer in FIG. 3O is only an illustration, without any limitation.

Taking the NPN-type HBT device as an example, the working principle of the SiGe HBT device provided by the embodiment of the present application is described: power is applied to the emitter junction, the emitter junction is forward-biased, and the majority carriers (free electrons) in the emitter region 79 continuously Across the emitter junction into the base region 29, an emitter current is formed. After electrons enter the base region 29, they are densely concentrated near the emitter junction, and gradually form an electron concentration difference. Under the action of the concentration difference, the electron flow is promoted to diffuse in the base region 29 to the collector junction, and is pulled in by the electric field of the collector junction. The collector region 12 forms a collector current. There is also a very small portion of electrons (because the base region 29 is very thin) recombined with the holes in the base region 29, and the ratio of the diffused electron flow to the recombined electron flow determines the amplification capability of the triode. Due to the large reverse voltage applied to the collector junction, the electric field force generated by this reverse voltage will prevent the electrons in the collector region 12 from diffusing to the base region 29, and at the same time pull the electrons diffused to the vicinity of the collector junction into the collector region 12 to form collector main current. In addition, the minority carriers (holes) in the collector region 12 will also drift and flow to the base region 29 to form a reverse saturation current.

According to the method for preparing a semiconductor structure provided in the embodiment of the present application, the intrinsic base region and the extrinsic base region are prepared as an integrated structure, with large contact area, good contact effect, and low resistance of the base region 29 . Compared with the structure in which the intrinsic base region is prepared by a selective epitaxy process, the intrinsic base region and the extrinsic base region are two structures of different materials, and then the intrinsic base region and the extrinsic base region are contacted by controlling the process during preparation, In the embodiment of the present application, the intrinsic base region and the extrinsic base region are an integrated structure with the same material, which can reduce the resistance of the base region 29 . Moreover, the embodiment of the present application uses a self-aligned structure and a non-selective epitaxial process to prepare the emitter junction (consisting of an intrinsic base region and an emitter region), and the preparation of each film layer in the semiconductor structure can be realized by using conventional techniques. It does not need to adopt a selective epitaxy process with high process difficulty, has low process requirements and low preparation cost.

In addition, the embodiment of the present application uses the first sacrificial pattern 30 as a self-alignment structure, the first sacrificial pattern 30 defines the outline of the intrinsic base region, and forms the emission region 79 at the corresponding position of the first sacrificial pattern 30, which can be used to realize Self-alignment of the emitter junction (E-B). In this way, the prepared emission junction has a mirror-symmetrical structure, and even a centrosymmetric structure can be achieved. Due to process factors, there may be a deviation of several nanometers. However, unlike the asymmetric structure prepared by using a non-self-aligned process, there will be a deviation of tens of nanometers (the minimum may be more than 20 nanometers), resulting in an asymmetrical emitter junction. The asymmetry of the emitter junction leads to the difference between the parasitic collector junction capacitance and the base region resistance on both sides of the emitter junction midline, which cannot achieve the effect of sharing current on both sides, resulting in the inability to minimize the total resistance and capacitance, while the symmetry on both sides can play a role Minimize the effect of base resistance and collector junction capacitance, thereby increasing the highest oscillation frequency of the device. Moreover, the preparation of each film layer in the embodiment of the present application can be realized by using conventional technology, which requires relatively low process requirements and low preparation cost.

Furthermore, by adopting a structure in which the auxiliary layer, the interlayer protection layer 59 and the base region 29 are covered layer by layer, the manufacturing cost of the corresponding process is reduced and the performance of the chip is guaranteed. The auxiliary layer is disposed on the base region 29 and can protect the base region 29 to avoid damage to the base region 29 and affect the resistance of the base region. The interlayer protective layer 59 is arranged between the auxiliary layer and the emission region 29. On the one hand, it can play a barrier effect on the auxiliary layer and the emission region 29, so that there is no need to limit the material of the auxiliary layer; on the other hand, it can close the emission region 29 One side of the substrate 10 plays a protective role.

Example two

The difference between Example 2 and Example 1 is that the surface of the interlayer protective film 50 obtained in step S60 facing the emission region window W is flush with the surface of the second pattern facing the emission region window W instead of being stepped.

The method for preparing the semiconductor structure provided in this example is the same as the method for preparing the semiconductor structure provided in Example 1, and the structure obtained by performing step S10-step S50 is shown in FIG. 3A-FIG. 3E.

In step S60, as shown in FIG. 4A , the process of removing the first pattern 41 and the first sacrificial pattern 30 also includes processing the second opening 51 so that the projection of the outline of the second opening 51 is consistent with that of the first opening 421. The projection coincidence of the contours of .

As shown in FIG. 4A, while removing the first dielectric pattern 33, the second opening 51 can be enlarged at the same time by controlling the process (for example, the time of wet etching), so that the projection of the outline of the second opening 51 is consistent with the second opening 51. The projections of the contours of an opening 421 coincide. That is, the second opening 51 is equal to the first opening 421 so that the surface a of the interlayer protection film 50 facing the emission region window W is flush with the surface b of the second pattern facing the emission region window W. Referring to FIG.

The subsequent execution of steps S70-S150 is also the same as in Example 1. In this example, step S110 and step S120 are not executed as an example, and the structure obtained by executing step S70-step S150 (excluding step S110 and step S120) is shown in FIG. 4B-FIG. 4G.

It can be understood that, if step S110 and step S120 are not performed, the auxiliary layer is prepared from the second sacrificial film 40, the material of the auxiliary layer is the same as that of the second sacrificial film 40, and the material of the auxiliary layer is silicide thing. In the embodiment of the present application, the auxiliary layer whose material is silicide is referred to as the second auxiliary layer 98 .

Therefore, when the contact hole 100 leads out the base B from the base region 29 , the second auxiliary layer 98 needs to expose the outer base region in the base region so as to lead out the base B.

For example, as shown in FIG. 4E , when patterning the film layer on the side of the second pattern 42 away from the substrate 10 , the second pattern 42 is also patterned at the same time. That is to say, when forming the emitter region 79 , all the film layers on the side of the base region film 20 away from the substrate 10 are patterned to form the emitter region 79 and expose the base region film 20 . Based on this, when forming the base region 79 , only the base region film 20 needs to be patterned.

The difference between the finally obtained semiconductor structure as shown in FIG. 4G and FIG. 3O lies in that the first opening and the second opening overlap each other. That is to say, the surface a of the interlayer protection layer 59 facing the first opening is flush with the surface b of the second auxiliary layer 98 facing the first opening.

Wherein, the material of the film layer in FIG. 4G is only an illustration, without any limitation.

Example three

The difference between Example 3 and Example 1 and Example 2 is that the inner wall 60 only includes a single-layer wall body, and no longer includes a multi-layer wall body.

Taking the comparison with Example 1 as an example, the preparation method of the semiconductor structure provided in this example is the same as the preparation method of the semiconductor structure provided in Example 1, and the structure obtained by performing steps S10 to S60 is shown in FIGS. 3A-3G .

In step S70 , as shown in FIG. 5A , during the process of forming the inner wall 60 , the finally formed inner wall 60 only includes a single-layer wall.

Exemplarily, after performing steps S71-S74, the preparation method further includes:

S75. Remove the second wall body 63 .

In this way, the finally formed inner wall 60 only includes the first wall 64 .

The subsequent execution of steps S80-S150 is the same as in Example 1. The structure obtained by executing steps S80-S150 is shown in FIG. 5B-FIG. 5H.

The final semiconductor structure shown in FIG. 5H differs from FIG. 3O mainly in that the inner wall 60 only includes a single wall.

Of course, as shown in FIG. 5I , the surface of the interlayer protection layer 59 facing the window W of the emission region and the surface of the first auxiliary layer 99 facing the window W of the emission region may also be flush.

Wherein, the material of the film layer in FIG. 5H and FIG. 5I is only an illustration, without any limitation.

In the case where the inner wall 60 only includes a single-layer wall, the opening of the emission region window W is relatively large, and the finally formed emission region 79 has a large area and low resistance.

Example four

Example 4 differs from Example 1 to Example 3 in that the semiconductor structure further includes a complementary metal oxide semiconductor field-effect transistor (complementary metal oxide semiconductor field-effect transistor, CMOSFET).

The method for preparing a semiconductor structure provided in this example, on the basis of Example 1 to Example 3, further includes:

S160 , forming a CMOSFET on the substrate 10 .

Wherein, the step of forming a CMOSFET on the substrate 10 may be performed before step S10, or may be performed after step S150. As shown in FIG. 6 , the SiGe HBT structure and the CMOSFET structure are isolated by the deep trench isolation region 16 in the substrate 10 .

In addition, the embodiment of the present application does not limit the structure of the CMOSFET, and the CMOSFET in FIG. 6 is only an illustration. CMOSFETs can be NMOS transistors or PMOS transistors.

Wherein, the material of the film layer in FIG. 6 is only an illustration, without any limitation.

The semiconductor structure prepared by the preparation method provided in this example is a CMOS+SiGe HBT device, and CMOS and SiGe HBT can be integrated on the same chip.

After the semiconductor structure prepared by the preparation method provided in the embodiment of the present application is applied to a transistor circuit, the transistor circuit can be directly packaged with a package body to form a packaged device (such as a chip). It can also be packaged together with other chips to form a packaged device. This embodiment of the present application does not limit it.

Based on this, in some embodiments, a transistor circuit including any one of the above-mentioned semiconductor structures can be applied to a radio frequency circuit.

For example, radio frequency circuits can be used in microwave systems, optoelectronic systems, radar, imaging and sensing fields, etc. The radio frequency circuit can be, for example, a power amplifier (power amplifier, PA), a variable gain amplifier (variable gain amplifier, VGA), a low noise amplifier (low noise amplifier, LNA), a transimpedance amplifier (trans-impedance amplifier, TIA), a driver (driver), mixer, clock data recovery (clock data recovery, CDR) circuit, etc.

Certainly, the embodiment of the present application does not limit the scope of application of the above semiconductor structure, for example, it may be applied to any communication device, and the communication device may be a network device or a terminal.

Terminals, such as tablet computers, mobile phones, e-readers, remote controls, personal computers (Personal Computer, PC), notebook computers, personal digital assistants (personal digital assistant, PDA), vehicle equipment, Internet TV, wearable devices, TV etc. For example, the above radio frequency circuit can be applied to a terminal.

In some embodiments, the terminal may further include, for example, a graphics processing unit (graphics processing unit, GPU), a display screen, an application processor, etc., to implement a display function.

Wherein, the display screen is used for displaying images, videos and the like. The display screen includes a display panel. The display panel can be a liquid crystal display panel (liquid crystal display, LCD), an organic light-emitting diode (organic light-emitting diode, OLED) display panel, an active matrix organic light-emitting diode display panel or an active matrix organic light-emitting diode (active matrix display panel). -matrix organic light emitting diode (AMOLED) display panel, flexible light-emitting diode (flex light-emitting diode, FLED) display panel, mini light-emitting diode (mini light-emitting diode, Mini LED) display panel, micro light-emitting diode (micro light-emitting diode) display panel emitting diode (Micro LED) display panel, micro organic light-emitting diode (micro organic light-emitting diode, Micro OLED) display panel, quantum dot light emitting diode (quantum dot light emitting diodes, QLED) display panel, etc.

In another aspect of the present application, there is also provided a non-transitory computer-readable storage medium for use with a computer, the computer having software for creating and making the above-mentioned semiconductor structure, the computer-readable storage medium storing one or A plurality of computer readable data structures, one or more computer readable data structures having control data, such as photomask data, for fabricating the semiconductor structure provided in any one of the illustrations provided above.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A semiconductor structure, characterized in that, comprising:

the substrate, including the collector region;

The base area is arranged on the substrate; the base area includes an intrinsic base area and an extrinsic base area, and the intrinsic base area is made of the same material as the extrinsic base area; the intrinsic base area is the same as the extrinsic base area; Collector contact;

an auxiliary layer disposed on the base region; the auxiliary layer has a first opening;

an interlayer protective layer disposed on the auxiliary layer, the interlayer protective layer has a second opening, the second opening is located above the first opening; the interlayer protective layer exposes the auxiliary layer;

An emission region is disposed on the interlayer protection layer and contacts the intrinsic base region through the first opening and the second opening.
The semiconductor structure according to claim 1, wherein the emitter junction formed by the emitter region and the intrinsic base region is a mirror-symmetrical structure, and a symmetry plane of the emitter junction is perpendicular to the substrate.
The semiconductor structure according to claim 1 or 2, wherein the material of the base region comprises silicon germanium or silicon germanium carbon alloy.
The semiconductor structure according to any one of claims 1-3, wherein the material of the auxiliary layer comprises polysilicon.
The semiconductor structure according to any one of claims 1-4, wherein the semiconductor structure further comprises an inner wall, and the inner wall is disposed between the auxiliary layer and the emission region.
The semiconductor structure according to claim 5, wherein the inner wall comprises a single-layer wall, and the inner wall is disposed on a side of the auxiliary layer and extends to a surface of the base region.
The semiconductor structure according to any one of claims 1-6, wherein the projection of the outline of the second opening covers the projection of the outline of the first opening;

or,

The projection of the contour of the second opening coincides with the projection of the contour of the first opening.
The semiconductor structure according to any one of claims 1-7, wherein the semiconductor structure further comprises an outer wall;

The outer wall wraps the sides of the launch area to protect the launch area.
The semiconductor structure according to any one of claims 1-8, wherein the semiconductor structure further comprises a capping layer;

The capping layer is disposed on the emission area for protecting the emission area.
The semiconductor structure according to any one of claims 1-9, wherein the semiconductor structure further comprises an emitter, a base, and a collector disposed on the substrate;

The emitter is in contact with the emitter region, the base is in contact with the extrinsic base region, and the collector is in contact with the collector region.
The semiconductor structure according to claim 10, wherein the substrate further comprises a shallow trench isolation region, a lead-out region and a buried layer collector region, and the lead-out region and the shallow trench isolation region are located in the buried layer Above the collector region, the shallow trench isolation region is located between the lead-out region and the collector region; the lead-out region and the collector region are respectively in contact with the buried layer collector region;

The collector electrode is in contact with the collector region through a contact connection hole with the lead-out region;

The emitter is in contact with the emission region through a connection hole passing through the capping layer and in contact with the emission region;

The base is in contact with the extrinsic base region through a connection hole in contact with the extrinsic base region.
The semiconductor structure according to any one of claims 1-10, characterized in that the semiconductor structure further comprises a complementary metal-oxide-semiconductor field-effect transistor, and the complementary metal-oxide-semiconductor field-effect transistor is arranged on the substrate superior.
A radio frequency circuit, characterized by comprising a transistor circuit comprising the semiconductor structure according to any one of claims 1-12.
A terminal, characterized by comprising a display screen and the radio frequency circuit according to claim 13.
A method for preparing a semiconductor structure, comprising:

forming a base film on a substrate, the substrate including a collector region;

forming a first sacrificial pattern on the base film; the first sacrificial pattern is located above the collector region and used to define an emission region window;

forming a second sacrificial film on the substrate formed with the first sacrificial pattern;

forming an interlayer protective film on the second sacrificial film; a second opening on the interlayer protective film exposes a first pattern of the second sacrificial film, and the first pattern covers the first sacrificial pattern; The interlayer protection film covers the second pattern of the second sacrificial film;

removing the first pattern and the first sacrificial pattern;

An emission region is formed, and the base region film is patterned to form a base region; the base region includes an intrinsic base region and an extrinsic base region, and the emission region is in contact with the intrinsic base region.
The preparation method according to claim 15, wherein forming an emission region, and patterning the base region film to form a base region comprises:

forming an emitter film on the substrate;

patterning the film layer on the side of the second pattern away from the substrate to form an emission region and expose the second pattern;

removing the second pattern, and forming a polysilicon pattern at a corresponding position;

The base film and the polysilicon pattern are patterned to form a base.
The preparation method according to claim 16, characterized in that, before removing the second pattern and forming the polysilicon pattern at the corresponding position, further comprising:

An outer wall is formed on the periphery of the emission area, and the outer wall wraps at least the side of the emission area.
The preparation method according to any one of claims 15-17, wherein forming a first sacrificial pattern on the base film comprises:

sequentially forming a first dielectric film and a second dielectric film on the base film;

Patterning the first dielectric film and the second dielectric film to form a stacked first dielectric pattern and a second dielectric pattern as the first sacrificial pattern.
The preparation method according to claim 18, wherein the material of the second dielectric film is the same as that of the second sacrificial film;

removing the first pattern and the first sacrificial pattern, comprising:

removing the first pattern and the second dielectric pattern;

The first dielectric pattern is removed.
The preparation method according to any one of claims 15-19, wherein the process of removing the first pattern and the first sacrificial pattern further includes:

processing the second opening such that the projection of the contour of the second opening overlaps the projection of the contour of the first opening;

or,

The second opening is processed such that the projection of the contour of the second opening coincides with the projection of the contour of the first opening.
The preparation method according to any one of claims 15-20, wherein, before forming the emitting region, the preparation method further comprises:

An inner wall covering the second pattern and a side of the interlayer protective film facing the emission area window is formed.
The preparation method according to claim 21, wherein forming the inner wall comprises:

forming a third dielectric film on the interlayer protective film, the third dielectric film forming a groove at the window of the emission region;

A fourth dielectric film is formed on the third dielectric film; the lattice mismatch between the third dielectric film and the base film is smaller than the lattice mismatch between the fourth dielectric film and the base film Spend;

patterning the fourth dielectric film to form a second wall, the second wall covering the side of the groove;

The part of the third dielectric film not covered by the second wall is removed to form the first wall.
The preparation method according to claim 22, characterized in that forming the inner wall further comprises: removing the second wall.
The preparation method according to any one of claims 15-23, wherein the preparation method further comprises:

Complementary metal oxide semiconductor field effect transistors are formed on the substrate.