CN116314305A

CN116314305A - Lateral bipolar junction transistor including stress layer and method

Info

Publication number: CN116314305A
Application number: CN202211447416.9A
Authority: CN
Inventors: J·辛格; A·M·德里克森; A·J·乔瑟夫; A·克诺尔; J·R·霍尔特
Original assignee: GlobalFoundries US Inc
Current assignee: GlobalFoundries US Inc
Priority date: 2021-12-20
Filing date: 2022-11-18
Publication date: 2023-06-23

Abstract

The invention relates to a lateral Bipolar Junction Transistor (BJT) including a stress layer and a method thereof. The semiconductor structure can be easily integrated in advanced silicon-on-insulator (SOI) technology platforms. Moreover, to maintain or enhance performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be adversely affected by the change in orientation of the BJT from vertical to lateral, the semiconductor structure may further include a dielectric stress layer (e.g., a tensile strained layer in the case of an NPN transistor or a compressive strained layer in the case of a PNP transistor) that partially covers the lateral BJT to enhance charge carrier mobility, and the lateral BJT may be configured as a lateral Heterojunction Bipolar Transistor (HBT). The invention also discloses a method for forming the semiconductor structure.

Description

Lateral bipolar junction transistor including stress layer and method

Technical Field

The present invention relates to semiconductor structures, and more particularly to embodiments of semiconductor structures including lateral bipolar junction transistors (bipolar junction transistor; BJTs) and methods of forming the semiconductor structures.

Background

Advantages associated with the fabrication of Complementary Metal Oxide Semiconductor (CMOS) designs using advanced silicon-on-insulator (SOI) processing technology platforms (e.g., fully-depleted silicon-on-insulator (FDSOI) processing technology platforms) include, for example, reduced power, reduced area consumption, reduced cost, high performance, multiple core threshold voltage (Vt) options, and the like. CMOS designs fabricated on such SOI wafers are used in a variety of applications including, but not limited to, internet of Things (IOT) devices, wearable devices, smart phone processors, automotive electronics, and radio frequency integrated circuits (radiofrequency integrated circuit; RFICs), including millimeter wave (mmWave) ICs. These same applications may benefit by including Bipolar Junction Transistors (BJTs) because BJTs tend to have larger drives and are generally considered more suitable for analog functions than field effect transistors (fieldeffect transistor; FETs). However, such BJTs are typically formed as vertical devices (e.g., with a collector in the substrate, a base aligned over the collector, and an emitter aligned over the base), which are not easily integrated in advanced SOI processing technology platforms.

Disclosure of Invention

Embodiments of semiconductor structures are disclosed herein. The semiconductor structure may include a lateral Bipolar Junction Transistor (BJT). The lateral BJT may include a collector, an emitter, and a base laterally between the collector and the emitter. The semiconductor structure may further comprise a first dielectric layer, in particular a dielectric stress layer covering only partially the lateral BJT, with one end thereof being located above the lateral BJT between the collector and the emitter. For example, the first dielectric layer may be over the collector and also extend onto the base such that one end of the first dielectric layer is aligned over the base.

Embodiments of semiconductor structures formed in advanced silicon-on-insulator (SOI) technology platforms are disclosed herein. In these embodiments, the semiconductor structure may include a semiconductor substrate, an insulator layer on the semiconductor substrate, and a semiconductor layer on the insulator layer. The semiconductor structure may include a lateral Bipolar Junction Transistor (BJT), particularly a lateral heterojunction bipolar transistor (heterojunction bipolartransistor; HBT). The lateral HBT may include a base. The base may include a first base region located within the semiconductor layer, a second base region located on the first base region, and a third base region located on the second base region and wider than the second base region. The lateral HBT may also include a collector and an emitter. The base may be laterally located between the collector and the emitter. Furthermore, the collector and the emitter may be made of a first semiconductor material, while at least the second base region may be made of a second semiconductor material different from the first semiconductor material, thereby providing a heterojunction. The semiconductor structure may further comprise a first dielectric layer, in particular a dielectric stress layer covering only partially the lateral BJT, with one end thereof being located above the lateral HBT between the collector and the emitter. For example, the first dielectric layer may be over the collector and also extend onto the base such that one end of the first dielectric layer is aligned over the base.

Also disclosed herein are method embodiments for forming the above semiconductor structures. The method embodiment may include forming a lateral Bipolar Junction Transistor (BJT) including a collector, an emitter, and a base laterally between the collector and the emitter. The method embodiment may further include forming a first dielectric layer, particularly a dielectric stress layer partially covering the lateral BJT, with one end thereof located over the lateral BJT between the collector and the emitter.

Drawings

The invention will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale, and wherein:

FIGS. 1A-1B are layout and cross-sectional views, respectively, showing an embodiment of a disclosed semiconductor structure having a lateral bipolar junction transistor partially covered by a dielectric stressor layer;

figure 2 is a flow chart illustrating an embodiment of a method of forming a semiconductor structure having a lateral bipolar junction transistor partially covered by a dielectric stressor layer;

fig. 3.1 is a cross-sectional view showing a partially completed semiconductor structure formed in accordance with the flow chart of fig. 2;

fig. 3.2 is a cross-sectional view showing a partially completed semiconductor structure formed in accordance with the flow chart of fig. 2;

FIGS. 3.3A and 3.3B are top and cross-sectional views, respectively, showing a partially completed semiconductor structure formed in accordance with the flow chart of FIG. 2;

fig. 3.4 is a cross-sectional view showing a partially completed semiconductor structure formed in accordance with the flowchart of fig. 2;

FIGS. 3.5A and 3.5B are top and cross-sectional views, respectively, showing a partially completed semiconductor structure formed in accordance with the flow chart of FIG. 2;

fig. 3.6A and 3.6B are top and cross-sectional views, respectively, showing a partially completed semiconductor structure formed in accordance with the flow chart of fig. 2;

fig. 3.7 is a cross-sectional view showing a partially completed semiconductor structure formed in accordance with the flowchart of fig. 2;

fig. 3.8 is a cross-sectional view showing a partially completed semiconductor structure formed in accordance with the flowchart of fig. 2;

fig. 3.9 is a cross-sectional view showing a partially completed semiconductor structure formed in accordance with the flowchart of fig. 2;

fig. 3.10 is a cross-sectional view showing a partially completed semiconductor structure formed in accordance with the flow chart of fig. 2;

fig. 3.11 is a cross-sectional view showing a partially completed semiconductor structure formed in accordance with the flowchart of fig. 2;

fig. 3.12 is a cross-sectional view showing a partially completed semiconductor structure formed in accordance with the flowchart of fig. 2;

fig. 3.13 is a cross-sectional view showing a partially completed semiconductor structure formed in accordance with the flowchart of fig. 2; and

Fig. 3.14 is a cross-sectional view showing a partially completed semiconductor structure formed in accordance with the flow chart of fig. 2.

Detailed Description

As described above, advantages associated with fabricating Complementary Metal Oxide Semiconductor (CMOS) designs using advanced silicon-on-insulator (SOI) processing technology platforms, such as fully depleted silicon-on-insulator (FDSOI) processing technology platforms, include, for example, reduced power, reduced area consumption, reduced cost, high performance, multiple core threshold voltage (Vt) options, and the like. CMOS designs fabricated on such SOI wafers are used in a variety of applications including, but not limited to, internet of Things (IOT) devices, wearable devices, smart phone processors, automotive electronics, and Radio Frequency Integrated Circuits (RFICs), including millimeter wave (mmWave) ICs. These same applications may benefit by including Bipolar Junction Transistors (BJTs) because BJTs tend to have larger drives and are generally considered more suitable for analog functions than Field Effect Transistors (FETs). However, such BJTs are typically formed as vertical devices (e.g., having a collector in the substrate, a base aligned over the collector, and an emitter aligned over the base), which are not easily integrated in advanced SOI processing technology platforms.

In view of the foregoing, embodiments of a semiconductor structure having a lateral Bipolar Junction Transistor (BJT) are disclosed herein. The semiconductor structure can be easily integrated in advanced silicon-on-insulator (SOI) technology platforms. Moreover, to maintain or enhance performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta (beta) cut-off frequency) that would otherwise be adversely affected by the orientation of the BJT changing from vertical to lateral, the semiconductor structure may further include a dielectric stress layer (e.g., a tensile strain layer in the case of an NPN-type transistor or a compressive strain layer in the case of a PNP-type transistor) that partially covers the lateral BJT to enhance charge carrier mobility, and optionally the lateral BJT may be configured as a lateral Heterojunction Bipolar Transistor (HBT). Methods of forming the semiconductor structure are also disclosed herein.

Fig. 1A-1B are layout and cross-sectional views, respectively, showing an embodiment of a disclosed semiconductor structure 100 having a lateral Bipolar Junction Transistor (BJT) 150 partially covered by a dielectric stress layer 180. It should be noted that lateral BJT 150 may be a standard BJT in which the collector, emitter, and base are made of the same semiconductor material (e.g., silicon); or Heterojunction Bipolar Transistors (HBTs) in which at least a portion of the base is made of a different semiconductor material than the collector and emitter, such as silicon germanium.

Specifically, the semiconductor structure 100 may be, for example, a semiconductor-on-insulator structure (e.g., a silicon-on-insulator (SOI) structure). That is, the semiconductor structure 100 may include a semiconductor substrate 101. The semiconductor substrate 101 may be a first semiconductor material (e.g., silicon), which is a monocrystalline structure.

Alternatively, the semiconductor substrate 101 may be doped to have a P-type conductivity at a lower conductivity level. Thus, for example, the semiconductor substrate 101 may be a P-silicon substrate.

Alternatively, semiconductor substrate 101 may include buried well 102 (also referred to as a buried dopant implantation region). The buried well 102 may be doped to have P-type conductivity (e.g., become a buried Pwell). Alternatively, the buried well 102 may be doped to have an N-type conductivity (e.g., become a buried Nwell).

The semiconductor structure 100 may also include an insulator layer 103 on a top surface of the semiconductor substrate 101 (e.g., over the buried well 102). Insulator layer 103 may be, for example, a silicon dioxide layer (also referred to herein as a Buried Oxide (BOX) layer) or any other suitable insulator material layer.

Semiconductor structure 100 may further include a semiconductor layer 104 on insulator layer 103. The semiconductor layer 104 may be a monocrystalline structure. The semiconductor layer 104 may be the same semiconductor material as the semiconductor substrate 101. That is, the semiconductor layer 104 may be made of a first semiconductor material (e.g., silicon). Alternatively, the semiconductor layer 104 may be a semiconductor material different from the semiconductor substrate 101. That is, the semiconductor layer 104 may be made of a second semiconductor material (e.g., silicon germanium). The semiconductor layer 104 may be undoped. Alternatively, the semiconductor layer 104 may be doped. The doping of the semiconductor layer 104 may vary depending on whether the lateral BJT 150 is an NPN type transistor or a PNP type transistor. For example, for an NPN transistor, semiconductor layer 150 may be doped to have a P-type conductivity at a lower conductivity (e.g., to be a P-semiconductor layer), while for a PNP transistor, semiconductor layer 104 may be doped to have an N-type conductivity at a lower conductivity level (e.g., to be an N-semiconductor layer).

The semiconductor structure 100 may also include shallow trench isolation (shallow trench isolation; STI) regions 106.STI region 106 may extend substantially vertically through semiconductor layer 104 to insulator layer 103 and may define boundaries of a device region including lateral BJT 150.

As described above, semiconductor structure 100 may further include lateral BJT 150. Those skilled in the art will appreciate that BJTs typically include three terminals: a collector, an emitter, and a base between the collector and the emitter. In a vertical BJT, the collector, base, and emitter are vertically stacked. In a lateral BJT, the base is laterally located between the collector and the emitter. In any case, the base will comprise at least an extrinsic base region having a first type of conductivity, and the collector and emitter will have a second type of conductivity that is different from the first type of conductivity. Thus, an NPN transistor will include at least a P-type extrinsic base, an N-type collector, and an N-type emitter; and the PNP-type transistor will include at least an N-type extrinsic base, a P-type collector, and a P-type emitter. In a standard BJT, the base, collector and emitter are of the same semiconductor material (e.g., silicon). Alternatively, different semiconductor materials may be used. In this case, the BJT is called a Heterojunction Bipolar Transistor (HBT). Those skilled in the art will appreciate that Heterojunction Bipolar Transistors (HBTs) are BJTs in which the collector and emitter are made at least in part of one semiconductor material and the base is made at least in part of a different semiconductor material. Different semiconductor materials are used at the emitter-base junction and at the base-collector junction to form a heterojunction suitable for operating at higher frequencies. Thus, in semiconductor structure 100, lateral BJT 150 may include three terminals: collector 133, emitter 132, and base 131 laterally between collector 133 and emitter 132.

Base 131 may be located over insulator layer 103 and may include, for example, three different stacked regions. The three different stacked regions may include a first base region 131.1, a second base region 131.2 over the first base region, and a third base region 131.3 over the second base region.

The first base region 131.1 may be located within the semiconductor layer 104 and may in particular comprise a first region 125 of the semiconductor layer 104, optionally having a recessed top surface. As described above, the semiconductor layer 104 may be a single crystal structure and may be a first semiconductor material (e.g., silicon) or a second semiconductor material (e.g., silicon germanium). The first region 125 may be undoped or doped. For example, in the case of an NPN transistor, the first region may be a P-region, or in the case of a PNP transistor, the first region may be an N-region.

The second base region 131.2 may be the epitaxial semiconductor layer 112. For a standard BJT, epitaxial semiconductor layer 112 may be a first semiconductor material (e.g., silicon). For HBTs, epitaxial semiconductor layer 112 may be a second semiconductor material (e.g., silicon germanium). In any event, the epitaxial semiconductor layer 112 may be filled with a narrower base opening defined by the space between the first sidewall spacers 108 (e.g., side spacers made of silicon nitride or some other suitable dielectric side spacer material) and aligned over the first region 125 of the semiconductor layer 104. In other words, the second base region 131.2 is laterally located between the first side spacers 108 and aligned over and in contact with the first base region 131.1 as shown. Epitaxial semiconductor layer 112 may be selectively grown from semiconductor layer 104 during processing to render it substantially a monocrystalline structure. Furthermore, epitaxial semiconductor layer 112 may be undoped (i.e., intrinsic) or doped, as described below.

The doping of epitaxial semiconductor layer 112 may vary depending on whether lateral BJT 150 is an NPN type transistor or a PNP type transistor. For example, for an NPN transistor, epitaxial semiconductor layer 112 may be undoped, or alternatively may be doped to have a P-type conductivity at a lower conductivity level, or have a graded P-type profile (e.g., from undoped or low doping near semiconductor layer 104 to higher doping away from semiconductor layer 104). Thus, for example, for an NPN transistor, the second base region 131.2 may be an intrinsic base region (e.g., an i-SiGe base region), or alternatively, a P-base region or a base region having a graded P-type profile from undoped or P-to P or P+. For PNP transistors, however, epitaxial semiconductor layer 112 may be undoped, or alternatively may be doped to have N-type conductivity at a lower conductivity level, or have a graded N-type profile (e.g., from undoped or low doping near semiconductor layer 104 to higher doping away from semiconductor layer 104). Thus, for example, for a PNP type transistor, the second base region 131.2 may be an intrinsic base region (e.g., an i-SiGe base), or alternatively, an N-base region or a base region having an undoped or N-to-N or N+ graded N-type distribution.

It should be noted that the second side spacers 107 (e.g., side spacers made of silicon dioxide or some other suitable dielectric side spacer material) may be disposed laterally adjacent to the first side spacers 108 on opposite sides of the second base region 131.2. The first and second side spacers may have substantially the same height, and in particular, the tops of the first and second side spacers may be substantially coplanar.

The third base region 131.3 may be aligned over the second base region 131.2, may be immediately adjacent to and may be wider than the second base region 131.2 such that it extends laterally over the first side spacers 108 and the second side spacers 107. Base 131 is therefore substantially T-shaped. As shown, the opposite sidewalls of the third base region 131.3 may be substantially vertically aligned with the outer vertical surfaces of the second side spacers 107. The third base region 131.3 may be an epitaxial semiconductor layer 113 composed of a first semiconductor material, e.g. silicon, or alternatively some other suitable base semiconductor material. Epitaxial semiconductor layer 113 may be non-selectively grown during processing to make it a substantially polycrystalline structure (e.g., to make it polycrystalline silicon). The epitaxial semiconductor layer 113 may be doped and the doping will vary depending on whether the lateral BJT150 is an NPN transistor or a PNP transistor. For example, for an NPN transistor, the epitaxial semiconductor layer 113 may be doped to have a P-type conductivity at a higher conductivity level, particularly at a higher conductivity level than the substrate and at a higher conductivity level than the underlying base region, such that the third base region 131.3 is, for example, a p+ extrinsic base region. For PNP transistors, the epitaxial semiconductor layer 113 may be doped to have N-type conductivity at a higher conductivity level, particularly at a higher conductivity level than the underlying base region, so that the third base region 131.3 is, for example, an n+ extrinsic base region.

It should be noted that the third side spacers 115 (e.g., side spacers made of silicon nitride or some other suitable dielectric side spacer material) may be laterally disposed adjacent to opposite sidewalls of the third base region 131.3 and may also cover the outer vertical surfaces of the underlying second side spacers 107.

As described above, the three terminals of lateral BJT 150 may also include collector 133 and emitter 132 on opposite sides of base 131.

In one example structure, the collector 133 and the emitter 132 may be substantially symmetrical. The collector 133 may include a first collector region 133.1 and a second collector region 133.2 located on the first collector region 133.1. The emitter 132 may include a first emitter region 132.1 and a second emitter region 132.2 located on the first emitter region 132.1. The first collector region 133.1 and the first emitter region 132.1 may comprise doped regions 121 in the semiconductor layer 104, optionally having a recessed top surface (not shown) and being located on opposite sides of the first base region 131.1 (i.e., the first base region 131.1 is located laterally between the first collector region 133.1 and the first emitter region 132.1). The second collector region 133.2 and the second emitter region 132.2 may be an epitaxial semiconductor layer 122 composed of a first semiconductor material, such as silicon, and may be doped. The doping of epitaxial semiconductor layer 122 may vary depending on whether lateral BJT 150 is an NPN type transistor or a PNP type transistor. For example, for an NPN transistor, epitaxial semiconductor layer 122 may be doped to have an N-type conductivity at a higher conductivity level. Moreover, the anneal performed during processing may cause portions of the underlying semiconductor layer 104 to also be doped to have N-type conductivity at a higher conductivity level (i.e., see doped region 121). Thus, for example, for an NPN transistor, the first and second collector regions 132.1-32.2 and the first and second emitter regions 133.1-133.2 may be N+ collector and emitter regions. For PNP transistors, the epitaxial semiconductor layer 122 can be doped to have P-type conductivity at a higher conductivity level. Moreover, the anneal performed during processing may cause portions of the underlying semiconductor layer 104 to also be doped to have a P-type conductivity at a higher conductivity level (i.e., see doped region 121). Thus, for example, for a PNP transistor, the first and second collector regions 132.1-132.2 and the first and second emitter regions 133.1-133.2 may be P+ regions.

It should be noted that the above-described configuration of the collector 133 and emitter 132 is provided for illustrative purposes. Alternatively, these regions 132-133 may be asymmetric and/or have some other suitable configuration. In any case, base 131 is laterally located between collector 133 and emitter 132.

Optionally, lateral BJT 150 may further include a metal silicide layer 199 on the uppermost surfaces of base 131, collector 133, and emitter 132. The metal silicide layer 199 may be, for example, cobalt silicide (CoSi), nickel silicide (NiSi), tungsten silicide (WSi), titanium silicide (TiSi), or any other suitable metal silicide material layer.

Semiconductor structure 100 may further include a first dielectric layer 180 that only partially covers lateral BJT 150. The first dielectric layer 180 may be a dielectric stress layer. In some embodiments, the first dielectric layer 180 may be, for example, a silicon nitride layer. The first dielectric layer 180 may be formed to have tensile strain or compressive strain. Specifically, first dielectric layer 180 (i.e., the dielectric stress layer) may have a tensile strain or a compressive strain depending on whether lateral BJT 150 is an NPN type transistor or a PNP type transistor. For example, for an NPN transistor, the first dielectric layer 180 may be a tensile strained layer to enhance electron mobility, while for a PNP transistor, the first dielectric layer 180 may be a compressive strained layer to enhance hole mobility. Such dielectric stress layers apply a corresponding strain to the underlying components of the lateral BJT to enhance performance by enhancing charge carrier mobility.

For example, the first dielectric layer 180 may cover only one side of the lateral BJT150, and one end 189 of the first dielectric layer 180 may be aligned over the lateral BJT150 somewhere between the collector 133 and the emitter 132. In some embodiments, first dielectric layer 180 may completely cover collector 133 and may partially cover base 131 such that one end 189 of first dielectric layer 180 is aligned over base 131 and stress is applied to the collector-base junction, as shown. Alternatively, the first dielectric layer 180 may completely cover the collector region 133 and may also extend completely over the base 131 such that one end 189 of the first dielectric layer 180 is aligned over the third side spacer 115 between the base 131 and the emitter 132. By a first dielectric layer disposed over collector 133 and at least partially over base 131, collector 133 and base 131 will be strained while emitter 132 will remain relaxed.

For example, in the case of an NPN transistor (where first dielectric layer 180 is tensile strained), collector 133 would be a longitudinally stretched and vertically compressed collector, base 131 would be similar to a longitudinally stretched and vertically compressed base, and emitter 132 would be a relaxed emitter. Whereas in the case of a PNP transistor (where the first dielectric layer 180 is compressively strained), the collector 133 will be a longitudinally compressed and vertically stretched collector, the base 131 will be similarly a longitudinally compressed and vertically stretched base, and the emitter 132 will be a relaxed emitter. In embodiments having such asymmetric dielectric stress layers over the collector-base junction, but not over the emitter-base junction, the greatest performance advantages, particularly enhanced charge carrier mobility, have been demonstrated, resulting in faster switching speeds.

It should be understood, however, that the figures are not intended to be limiting and that first dielectric layer 180 may instead cover different portions of the transistor to fine tune the strain applied to different components of lateral BJT 150. For example, first dielectric layer 180 may only completely cover collector 133 and not extend onto base 131 such that one end 189 of first dielectric layer 180 is aligned over third sidewall spacer 115 between base 131 and collector 133. In this case, only the collector will be strained, while the base and emitter will be relaxed. Alternatively, first dielectric layer 180 may only partially cover collector 133 and only partially cover base 131 such that one end of first dielectric layer 180 is aligned over collector 133 and the other end 189 of first dielectric layer 180 is aligned over base 131, or first dielectric layer 180 may only partially cover collector 133 and completely overlie base 131 such that one end of first dielectric layer 180 is aligned over collector 133 and the other end 189 of first dielectric layer 180 is aligned over third side spacer 115 between emitter 132 and base 131. In these cases, the collector and base will be strained to a lesser extent while the emitter is still relaxed. Alternatively, first dielectric layer 180 may be located on emitter 132 and optionally extend onto and/or over base 131 without further extending onto collector 133 (e.g., to strain the emitter and (optionally) the base, while the collector is relaxed), and so on.

The semiconductor structure 100 may also include one or more second dielectric layers 185 on the first dielectric layer and further extending laterally beyond the end 189 of the first dielectric layer and over the relaxed portion of the lateral BJT (e.g., over the collector 133) and over the STI 106. The second dielectric layer may include, for example, one or more conformal dielectric layers (e.g., a conformal silicon nitride etch stop layer) and a capping dielectric layer (e.g., a capping silicon dioxide layer or a capping layer comprised of some other suitable dielectric material) on the conformal dielectric layer. The semiconductor structure 100 may also include an intermediate process (middle of the line; MOL) contact including contacts extending through the dielectric layer to the base, collector, and emitter.

By using the first dielectric layer 180, in particular using a dielectric stress layer for enhancing charge carrier mobility (e.g. a tensile strained layer in case of NPN transistors or a compressive strained layer in case of PNP transistors) to partially cover the lateral BJT, and by optionally configuring the lateral BJT as a lateral HBT (e.g. base comprising SiGe and emitter and collector comprising Si), performance characteristics (e.g. cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta (beta) cut-off frequency) can be improved.

Referring to the flow chart of fig. 2, disclosed herein is also an embodiment of a method of forming a semiconductor-on-insulator structure, such as a silicon-on-insulator (SOI) structure, such as structure 100 described in detail above and shown in fig. 1A-1B, that includes a lateral Bipolar Junction Transistor (BJT), such as a standard BJT or a Heterojunction Bipolar Transistor (HBT), that is partially covered by a first dielectric layer, particularly a dielectric stress layer, to enhance performance.

The method embodiment may begin with an initial semiconductor-on-insulator structure (see process 202 and fig. 3.1). The semiconductor-on-insulator structure may include a semiconductor substrate 101, an insulator layer 103 on a top surface of the semiconductor substrate 101, and a semiconductor layer 104 on the insulator layer 103. The semiconductor substrate 101 and the semiconductor layer 104 may for example be made of the same semiconductor material, in particular a first semiconductor material, e.g. silicon or some other suitable semiconductor substrate material. Alternatively, the semiconductor layer 104 may be made of a second semiconductor material (e.g., silicon germanium or some other suitable semiconductor material instead of silicon) that is different from the first semiconductor material. In any case, the semiconductor substrate 101 and the semiconductor layer 104 may be a single-crystal structure. The semiconductor substrate 101 may be doped to have a P-type conductivity at a lower conductivity level. Thus, for example, the semiconductor substrate 101 may be a P-silicon substrate. Insulator layer 103 may be a silicon dioxide layer (also referred to herein as a Buried Oxide (BOX) layer) or some other suitable insulator material layer.

Optionally, a dopant implantation process may be performed to form a well 102 (also referred to as a dopant implantation region) in the semiconductor substrate, particularly at a top surface of the semiconductor substrate adjacent to the insulator layer 103 (see process 204 and fig. 3.2). It should be noted that the conductivity type of the well 102 may vary depending on whether an NPN type transistor or a PNP type transistor is being formed. For example, for an NPN transistor, a P-type dopant may be implanted adjacent to the top surface of the P-substrate of insulator layer 103 such that well 102 is formed as a Pwell and has a higher P-type conductivity level than the lower portion of the adjacent P-substrate. For a PNP transistor, N-type dopants may be implanted at the top surface of the P-substrate adjacent to the insulator layer 103, so that the well 102 is formed as an Nwell.

Alternatively, if the semiconductor layer 104 is made of a first semiconductor material (e.g., silicon) and the semiconductor layer 104 is optimally made of a second semiconductor material (e.g., silicon germanium), a conversion process may be performed (see process 206 and fig. 3.2). For example, a germanium concentration process may be performed at process 206 to convert a silicon layer located on insulator layer 103 to a silicon germanium layer located on insulator layer 103. Germanium concentration processes are well known in the art, and thus, details of such processes are omitted from this specification to allow the reader to focus on the salient aspects of the disclosed embodiments. The silicon germanium layer thus formed may still be a monocrystalline structure.

Next, a lateral Bipolar Junction Transistor (BJT) may be formed using the semiconductor layer 104 (see process 208). It should be noted that the lateral BJT formed in process 208 may be a standard BJT in which the collector, emitter, and base comprise the same semiconductor material (e.g., silicon), or may be a HBT in which at least a portion of the base comprises a different semiconductor material than the collector and emitter. Further, it should also be noted that in the discussion below regarding the process steps, reference is made to a first type of conductivity and a second type of conductivity, and whether the first type of conductivity and the second type of conductivity are P-type conductivity and N-type conductivity, respectively, or N-type conductivity and P-type conductivity, respectively, depends on whether an NPN-type transistor or a PNP-type transistor is formed in process 208. Specifically, for NPN-type transistors, the first type conductivity refers to P-type conductivity and the second type conductivity refers to N-type conductivity, while for PNP-type transistors, the first type conductivity refers to N-type conductivity and the second type conductivity refers to P-type conductivity.

The formation of the lateral BJT may begin with an optional dopant implantation process to dope the semiconductor layer 104 with a first type conductivity dopant, thereby providing the semiconductor layer 104 with a first type conductivity at a lower conductivity level (see process 210 and fig. 3.2). For example, for an NPN transistor, a P-type dopant may be implanted to provide the semiconductor layer with P-type conductivity at a lower conductivity level (e.g., to provide the semiconductor layer as a P-semiconductor layer), and for a PNP transistor, an N-type dopant may be implanted to provide the semiconductor layer with N-type conductivity at a lower conductivity level (e.g., to provide the semiconductor layer as an N-semiconductor layer).

Shallow Trench Isolation (STI) regions 106 may be formed (see process 212 and fig. 3.3A and 3.3B). STI regions 106 may be formed such that they define boundaries of the device region and extend substantially vertically through semiconductor layer 104 to insulator layer 103. Specifically, at process 212, trenches for STI regions may be formed (e.g., lithographically patterned and etched using conventional STI processing techniques) such that they extend substantially vertically through the semiconductor layer to the insulator layer and such that they define device regions within the semiconductor layer. The trench may be further filled with one or more layers of isolation material (e.g., silicon dioxide, silicon nitride, etc.), and a chemical mechanical polishing (chemical mechanical polishing; CMP) process may be performed to remove any of the isolation material from over the semiconductor layer.

Isolation layer 109 may then be formed over semiconductor layer 104 and adjacent STI regions 106 (see process 214 and fig. 3.4). The isolation layer 109 may be, for example, a silicon dioxide layer formed at process 214 using a conventional oxidation process.

Base opening 110 may then be formed in isolation layer 109 (see process 216 and fig. 3.5A and 3.5B). Specifically, at process 214, conventional photolithographic processing and etching techniques may be performed to form base opening 110 in isolation layer 109. For example, a base opening 110 may be formed to extend vertically through isolation layer 109 to semiconductor layer 104 so as to completely traverse and expose a central portion of the semiconductor layer such that the base opening 110 has a first width (Wbo) and such that portions of the semiconductor layer on either side of the base opening 110 remain covered.

Then, a first sidewall spacer 108 may be formed in the base opening 110. For example, a dielectric spacer material may be conformally deposited to cover the top surface of isolation layer 109 and line base opening 110 (see fig. 3.6A and 3.6B). The dielectric spacer material may be, for example, silicon nitride or some other suitable dielectric spacer material that is different from the isolation material of isolation layer 109 so that it may be selectively etched with respect to isolation material 107. A selective anisotropic sidewall spacer etch process may then be performed to remove the dielectric spacer material from the horizontal surfaces so that it remains intact (i.e., as first sidewall spacer 108) on the vertical surfaces within the base opening. By forming the first sidewall spacers 108 within the base opening 110, the width of the base opening 110 narrows from a first width (Wbo) to a second width (Wfbo) that is narrower than the first width, and exposes the first region of the semiconductor layer. It should be noted that the first width may be at or near the minimum width achievable with conventional photolithographic patterning, and the second width may be less than the minimum width.

Optionally, the first region 125 of the semiconductor layer 104 exposed at the bottom of the base opening may be recessed (see process 218 and fig. 3.7). That is, a selective anisotropic etching process may be performed to recess (i.e., etch back) the top surface of the first region 125 of the semiconductor layer 104 exposed at the bottom of the base opening 110. This selective anisotropic etching process should be performed without completely etching through the semiconductor layer 104 so that at least the lower portion of the first region 125 of the semiconductor layer 104 remains intact and can then be used as a seed layer. The first region 125 (recessed (as shown) or not) of the semiconductor layer 104 aligned under the base opening 110 may correspond to the first base region 131.1 of the base 131 of the lateral BJT being formed (e.g., a standard BJT or HBT).

Then, a second base region 131.2 may be formed in the base opening 110 over the first base region 131.1 (see process 220 and fig. 3.8). Specifically, the epitaxial semiconductor layer 112 may be grown on the top surface of the exposed first region 125 of the semiconductor layer 104 within the narrower base opening 110 (defined by the space between the first side spacers 108). At process 220, epitaxial semiconductor layer 112 may be selectively grown from semiconductor layer 104 to render it substantially a monocrystalline structure. For a standard BJT, the semiconductor layer 104 and the epitaxial semiconductor layer 112 may be a first semiconductor material (e.g., silicon). For HBTs, semiconductor layer 104 may be a first or second semiconductor material (e.g., silicon or silicon germanium), but epitaxial semiconductor layer 112 may be specifically a second semiconductor material (e.g., silicon germanium). In either case, the epitaxial semiconductor layer 112 may be grown at process 220 without any in-situ doping (i.e., leaving it undoped/intrinsic). Alternatively, the epitaxial semiconductor layer 112 may be doped in situ at process 220 to have a first type conductivity at a lower conductivity level or to have a graded dopant profile (e.g., from undoped or low doping adjacent the first base region to higher doping away from the first base region).

Thus, after process 220, for an NPN standard BJT, the second base region 131.2 may be a monocrystalline intrinsic silicon base region (i-Si base), a P-monocrystalline silicon base region, or a monocrystalline silicon base region with a graded dopant profile from undoped or P-adjacent to the first base region to P or p+ away from the first base region. For an NPN HBT, the second base region 131.2 may be a single crystalline intrinsic silicon germanium base region (i-SiGe base), a single crystalline P-silicon germanium base region, or a single crystalline silicon germanium base region having a graded dopant profile from undoped or P-adjacent to the first base region to P or P+ remote from the first base region. For a PNP standard BJT, the second base region 131.2 may be a single crystal intrinsic silicon base region (i-Si base), an N-single crystal silicon base region, or a single crystal silicon base region with a graded dopant profile from undoped or N-adjacent to the first base region to N or N+ away from the first base region. For a PNP HBT, the second base region 131.2 may be a single crystalline intrinsic silicon germanium base region (i-SiGe base), a single crystalline N-silicon germanium base region, or a single crystalline silicon germanium base region with a graded dopant profile from undoped or N-adjacent to the first base region to N or n+ away from the first base region.

Another epitaxial semiconductor layer 113 of the first semiconductor material, e.g. silicon, or some other suitable base semiconductor material, may be grown on the second base region 131.1 and over the isolation layer 109 (see process 222 and fig. 3.9). In process 222, epitaxial semiconductor layer 113 may be non-selectively grown from the second base region and the spacer to render it substantially polycrystalline in structure. At process 222, epitaxial semiconductor layer 113 may be doped in situ to have a first type of conductivity at a higher conductivity level. Thus, for example, for an NPN type standard BJT or HBT, the epitaxial semiconductor layer 113 may be a p+ polycrystalline semiconductor layer (e.g., p+ polycrystalline silicon layer), while for a PNP type standard BJT or HBT, the epitaxial semiconductor layer 113 may be an n+ polycrystalline semiconductor layer (e.g., n+ polycrystalline silicon layer).

A thin cap layer (e.g., thin silicon nitride cap layer 114) may be formed on the epitaxial semiconductor layer 113 (see fig. 3.9).

Subsequently, a base stack may be formed (see process 224 and fig. 3.10). Specifically, a photolithographic patterning and etching process may be performed to define the third base region 131.3 from the portion of the epitaxial semiconductor layer 113 aligned over the second base region 131.2 and further define (from the isolation layer 109) the second side spacers 107 disposed laterally adjacent to the first side spacers 108. Due to the photolithographic patterning and etching process performed at process 224, the formed third base region 131.3 may be aligned over the second base region 131.2, immediately adjacent to and wider than the second base region 131.2, so as to extend laterally over the first side spacers 108 and the formed second side spacers 107. Accordingly, the base 131 is substantially T-shaped and the opposite sidewalls of the third base region 131.3 are substantially vertically aligned with the outer vertical surfaces of the second side spacers 107. Next, third side spacers 115 may be formed on the base stack, in particular adjacent to opposite sidewalls of the third base region 131.3, and also adjacent to outer vertical surfaces of the underlying second side spacers 107 (see fig. 3.10). For example, another dielectric spacer material may be conformally deposited to cover the base stack. The dielectric spacer material used to form the third sidewall spacers may be, for example, silicon nitride or some other suitable dielectric spacer material. A selective anisotropic sidewall spacer etch process may then be performed to remove the dielectric spacer material from the horizontal surfaces of the semiconductor layer 104 on opposite sides of the base stack, especially from the second and third regions 117a-117b, respectively, and leave the dielectric spacer material intact on the vertical surfaces (i.e., as the third sidewall spacers 115).

Optionally, the second and third regions 117a-117b of the semiconductor layer 104 that are exposed during formation of the third side spacers 115 may be recessed (not shown). That is, a selective anisotropic etching process may be performed to recess (i.e., etch back) the top surface of the semiconductor layer 104 in the second and third regions 117a-117b of the semiconductor layer 104. This selective anisotropic etch process should be performed without etching completely through the semiconductor layer 104 so that portions of the semiconductor layer 104 remain intact and may be subsequently used as a seed layer.

Collector 133 and emitter 132 may then be formed on opposite sides of the base stack (see process 226 and fig. 3.11). For example, an additional epitaxial semiconductor layer 122 of a first semiconductor material (e.g., silicon) or some other suitable collector/emitter semiconductor material may be selectively grown from the exposed semiconductor surfaces of the second and third regions 117a-117b of the semiconductor layer 104 to render them substantially monocrystalline in structure. At process 226, the additional epitaxial semiconductor layer 122 may be doped in situ to have a second type of conductivity at a higher conductivity level. Thus, for example, for an NPN transistor, the additional epitaxial semiconductor layer 122 may be an n+ monocrystalline semiconductor layer (e.g., an n+ silicon layer), while for a PNP transistor, the additional epitaxial semiconductor layer 122 may be a p+ monocrystalline semiconductor layer (e.g., a p+ silicon layer). A subsequent annealing process may cause dopants from the additional epitaxial semiconductor layer 122 to diffuse into the second and third regions 117a-117b of the semiconductor layer to form doped regions 121 having a second type conductivity. In this case, the doped regions 121 of the second and third regions 117a-117b of the semiconductor layer 104 form the underlying emitter and collector regions 132.1, 133.1 of the emitter 132 and collector 133, respectively. In addition, the additional epitaxial semiconductor layer 122 grown on the second and third regions 117a-117b of the semiconductor layer 104 forms upper emitter and collector regions 132.2, 133.2 of the emitter 132 and collector 133, respectively. It should be noted that process 226 is but one example process flow that may be used to form emitter 132 and collector 133 on opposite sides of the base stack. Alternatively, any other suitable process flow may be employed to form symmetric or asymmetric emitter/collector regions.

Optionally, the method embodiment may further include selectively removing cap layer 114 from the top of base 131 and forming a metal silicide layer 199 on the uppermost surfaces of base 131, collector 133, and emitter 132 (see process 252 and fig. 3.12). The metal silicide layer 199 may be, for example, cobalt silicide (CoSi), nickel silicide (NiSi), tungsten silicide (WSi), titanium silicide (TiSi), or any other suitable metal silicide material layer. Techniques for forming metal silicide layers are well known in the art and, therefore, are omitted from this description to allow the reader to focus on the salient aspects of the disclosed embodiments.

The method embodiment may further include forming a conformal first dielectric layer 180, particularly a dielectric stress layer, so that it only partially covers the lateral BJT150 (see process 254 and fig. 3.13-3.14). First dielectric layer 180 (i.e., dielectric stress layer) may be, for example, a silicon nitride stress layer that is deposited and further processed as desired to have tensile or compressive strain, depending on whether lateral BJT150 is an NPN type transistor or a PNP type transistor. For example, for an NPN transistor, the first dielectric layer 180 may be deposited and further processed as needed at process 254 to be a tensile strained layer, while for a PNP transistor, the first dielectric layer 180 may be deposited and (optionally) further processed as needed at process 254 to be a compressive strained layer. Various techniques for forming a tensile strained dielectric layer and a compressive strained dielectric layer are well known in the art and may be used in the disclosed methods. However, details of these techniques have been omitted from this description to allow the reader to focus on the salient aspects of the disclosed embodiments.

In any event, first dielectric layer 180 may then be lithographically patterned and etched so that it only partially covers lateral BJT 150 and has one end aligned over the transistor somewhere between the collector and emitter. For example, first dielectric layer 180 may be lithographically patterned and etched such that it covers only one side of lateral BJT 150 and such that one end 189 is aligned over lateral BJT 150 somewhere between collector 133 and emitter 132. In some embodiments, first dielectric layer 180 may be patterned and etched so that it completely covers collector 133, so that it partially covers base 131, and so that it has one end 189 aligned over base 131, as shown. Alternatively, first dielectric layer 180 may be lithographically patterned and etched so as to completely cover collector 133, to extend completely over base 131, and to have one end 189 aligned over third sidewall spacer 115 between base 131 and emitter 132. By the first dielectric layer over the collector 133 and at least partially over the base 131, the collector 133 and the base 131 (and the collector-base junction) will be strained, while the emitter 132 will remain relaxed.

For example, in the case of an NPN transistor (where first dielectric layer 180 is tensile strained), collector 133 would be a longitudinally stretched and vertically compressed collector, base 131 would be similar to a longitudinally stretched and vertically compressed base, and emitter 132 would be a relaxed emitter. Whereas in the case of a PNP transistor (where the first dielectric layer 180 is compressively strained), the collector 133 will be a longitudinally compressed and vertically stretched collector, the base 131 will be similarly a longitudinally compressed and vertically stretched base, and the emitter 132 will be a relaxed emitter. In embodiments having such asymmetric dielectric stress layers over the collector-base junction, but not over the emitter-base junction, the greatest performance advantage, particularly enhanced charge carrier mobility, and thus faster switching speeds, has been presented.

It should be understood that the figures are not intended to be limiting and that the first dielectric layer may alternatively be patterned and etched so as to cover different portions of the lateral BJT to fine tune the strain applied to different components of the lateral BJT 150. For example, first dielectric layer 180 may be patterned and etched so that it only completely covers collector 133 so that it does not extend onto base 131 and so that it has one end 189 aligned over third sidewall spacer 115 between base 131 and collector 133. In this case, only the collector will be strained, while the base and emitter will be relaxed. Alternatively, first dielectric layer 180 may be patterned and etched so that it only partially covers collector 133 and so that it partially or completely covers base 131. In these cases, the collector and base will be strained to a lesser extent while the emitter is still relaxed. Alternatively, first dielectric layer 180 may be patterned and etched so that it overlies emitter 132, and optionally extends onto and/or over base 131, without further extending onto collector 133 (e.g., so that the emitter and (optionally) the base are strained, while the collector is relaxed), and so on.

Moreover, it should be appreciated that the above-described techniques for forming the first dielectric layer 180 that only partially covers the transistor are provided for illustration purposes and are not intended to be limiting. For example, a masking layer may instead be formed over the partially completed structure. The mask layer may be patterned to have an opening exposing a portion of the lateral BJT and to leave another portion of the lateral BJT covered. The first dielectric layer, particularly the dielectric stress layer, may be formed within the trench and the mask layer may be selectively removed.

The method embodiment may further include forming one or more second dielectric layers 185 on the first dielectric layer 180 and further extending laterally beyond the ends 189 of the first dielectric layer 180 to above the portions of the lateral BJT 150 not covered by the first dielectric layer 180 (see process 256). Although not shown, these dielectric layers may include, for example, one or more conformal dielectric layers (e.g., another conformal silicon nitride etch stop layer) and a blanket dielectric layer (e.g., a blanket silicon dioxide layer or a blanket layer composed of some other suitable dielectric material) overlying the conformal dielectric layers. The method embodiment may also include forming an intermediate process (MOL) contact including a contact extending through the dielectric layer to the base, collector, and emitter (see process 258).

It should be understood that in the above structures and methods, semiconductor materials refer to materials whose electrical properties may be altered by doping with impurities. Example semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon germanium carbide, silicon carbide, etc.) and group III-V compound semiconductors (i.e., obtained by combining a group III element such As aluminum (Al), gallium (Ga), indium (In), and a group V element such As nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)), for example, gaN, inP, gaAs, or GaP. Pure semiconductor materials, particularly semiconductor materials that are not doped with impurities for increasing conductivity (i.e., undoped semiconductor materials), are referred to in the art as intrinsic semiconductors. Semiconductor materials doped with impurities for increasing conductivity (i.e., doped semiconductor materials) are known in the art as extrinsic semiconductors and are more conductive than intrinsic semiconductors made from the same substrate. That is, extrinsic silicon will be more conductive than intrinsic silicon; extrinsic silicon germanium will be more conductive than intrinsic silicon germanium; and so on. Moreover, it should be understood that different impurities (i.e., different dopants) may be used to obtain different conductivity types (e.g., P-type conductivity and N-type conductivity), and that the dopants may vary depending on the different semiconductor materials used. For example, silicon-based semiconductor materials (e.g., silicon germanium, etc.) are typically doped with a group III dopant such As boron (B) or indium (In) to obtain P-type conductivity, and silicon-based semiconductor materials are typically doped with a group V dopant such As arsenic (As), phosphorus (P), or antimony (Sb) to obtain N-type conductivity. Gallium nitride (GaN) based semiconductor materials are typically doped with magnesium (Mg) to obtain P-type conductivity and silicon (Si) or oxygen to obtain N-type conductivity. Those skilled in the art will also appreciate that different conductivity levels will depend on the relative concentration levels of dopants in a given semiconductor region.

The method described above may be used in the fabrication of integrated circuit chips. The manufacturer may dispense the resulting integrated circuit chips in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is provided in a single chip package (e.g., a plastic carrier with pins attached to a motherboard or other higher level carrier) or in a multi-chip package (e.g., a ceramic carrier with single or double sided interconnections or embedded interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices, either as part of (a) an intermediate product, such as a motherboard, or as part of (b) an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications, to advanced computer products having a display, a keyboard or other input device, and a central processor.

It is to be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods, and is not intended to be limiting. For example, as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the term "comprising" as used herein indicates the presence of said feature, integer, step, operation, element, and/or component, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Moreover, as used herein, terms such as "right," "left," "vertical," "horizontal," "top," "bottom," "above," "below," "parallel," "vertical," and the like are intended to describe relative positions when they are oriented and displayed in the drawings (unless otherwise indicated), and terms such as "touch," "direct contact," "adjacent," "directly adjacent," "immediately adjacent," and the like are intended to mean that at least one element physically contacts another element (without the other element separating the elements). The term "lateral" as used herein describes the relative position of elements when oriented and shown in the drawings, and particularly indicates that one element is located on a side of another element rather than above or below the other element. For example, one element will be laterally adjacent to another element directly next to the other element, and one element will be laterally surrounding the other element adjacent to and surrounding the outer sidewall of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

The description of the various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, the practical application, or technical improvement in the art known in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure, comprising:

a transistor, comprising: a base; a collector; and an emitter, wherein the base is laterally located between the collector and the emitter; and

and a first dielectric layer partially covering the transistor, wherein one end of the first dielectric layer is positioned above the transistor between the collector and the emitter.

2. The structure of claim 1 wherein the first dielectric layer comprises a stress layer.

3. The structure of claim 1 wherein the first dielectric layer comprises a silicon nitride layer having one of tensile strain and compressive strain.

4. The structure of claim 1 wherein the transistor comprises an NPN heterojunction bipolar transistor and the first dielectric layer comprises a tensile strained layer.

5. The structure of claim 1 wherein the transistor comprises a PNP heterojunction bipolar transistor and the first dielectric layer comprises a compressively strained layer.

6. The structure of claim 1 wherein said first dielectric layer covers said collector and at least partially covers said base.

7. The structure of claim 6 further comprising a second dielectric layer on said first dielectric layer and further extending laterally beyond said end of said first dielectric layer above said emitter.

8. A structure, comprising:

an insulator layer;

a semiconductor layer on the insulator layer;

a transistor, comprising:

a base, comprising: a first base region within the semiconductor layer; a second base region located on the first base region; and a third base region located on the second base region and wider than the second base region;

a collector; and an emitter, wherein the base is laterally located between the collector and the emitter, wherein the collector and the emitter comprise a first semiconductor material, and wherein at least the second base region comprises a second semiconductor material different from the first semiconductor material; and

9. The structure of claim 8 wherein the first dielectric layer comprises a stress layer.

10. The structure of claim 8 wherein the first dielectric layer comprises a silicon nitride layer having one of tensile strain and compressive strain.

11. The structure of claim 10 wherein the transistor comprises an NPN heterojunction bipolar transistor and the first dielectric layer comprises a tensile strained layer.

12. The structure of claim 10 wherein the transistor comprises a PNP heterojunction bipolar transistor and the first dielectric layer comprises a compressively strained layer.

13. The structure of claim 8 wherein said first dielectric layer covers said collector and at least partially covers said base.

14. The structure of claim 13, further comprising a second dielectric layer on the first dielectric layer and further extending laterally beyond the end of the first dielectric layer above the collector.

15. A method, comprising:

Forming a transistor, the transistor comprising: a base; a collector; and an emitter, wherein the base is laterally located between the collector and the emitter; and

a first dielectric layer is formed to partially cover the transistor, wherein one end of the first dielectric layer is located over the transistor between the collector and the emitter.

16. The method of claim 15, wherein,

the forming of the transistor includes forming an NPN heterojunction bipolar transistor, an

Wherein the forming of the first dielectric layer includes forming a tensile strained layer.

17. The method of claim 15, wherein,

the forming of the transistor includes forming a PNP heterojunction bipolar transistor, an

Wherein the forming of the first dielectric layer includes forming a compressively strained layer.

18. The method of claim 15, wherein,

the collector and the emitter are formed to include a first semiconductor material, an

Wherein the base is formed to include: a first base region located in the semiconductor layer; a second base region located on the first base region; and a third base region located on and wider than the second base region, at least the second base region including a second semiconductor material different from the first semiconductor material.

19. The method of claim 15, wherein the first dielectric layer is formed to cover the collector and at least partially cover the base.

20. The method of claim 19, further comprising forming a second dielectric layer on the first dielectric layer and further extending laterally beyond the end of the first dielectric layer above the emitter.