CN116314305A - Lateral bipolar junction transistor including stress layer and method - Google Patents

Abstract

The present invention relates to a lateral bipolar junction transistor including a stress layer and a method, and discloses a semiconductor structure having a lateral bipolar junction transistor (BJT). This semiconductor structure can be easily integrated into advanced silicon-on-insulator (SOI) technology platforms. Also, to maintain or improve performance characteristics such as cutoff frequency (fT)/maximum oscillation frequency (fmax) and beta cutoff frequency that would otherwise be negatively affected by changing the orientation of the BJT from vertical to lateral, the The semiconductor structure may also include a dielectric stress layer (e.g., a tensile strained layer in the case of an NPN transistor, or a compressive strained layer in the case of a PNP transistor) partially covering the lateral BJT to enhance charge carrier mobility. , and the lateral BJT may be configured as a lateral heterojunction bipolar transistor (HBT). The invention also discloses a method of forming the semiconductor structure.

Description

Lateral bipolar junction transistor including stress layer and method

technical field

The present invention relates to semiconductor structures, and more particularly to embodiments of semiconductor structures including lateral bipolar junction transistors (BJTs) and methods of forming the semiconductor structures.

Background technique

Complementary Metal Oxide Semiconductor ( Advantages associated with CMOS) designs include, for example, reduced power, reduced area consumption, reduced cost, high performance, multiple core threshold voltage (Vt) selections, and the like. CMOS fabricated on such SOI wafers are designed for use in a variety of applications, including but not limited to Internet-of-Things (IOT) devices, wearable devices, smartphone processors, automotive electronics, and radio frequency integration Circuit (radiofrequency integrated circuit; RFIC) (including millimeter wave (mmWave) IC). These same applications can benefit from the inclusion of bipolar junction transistors (BJTs) since BJTs tend to have larger drives and are generally considered better suited for analog functions than field effect transistors (FETs). However, such BJTs are typically formed as vertical devices (e.g., with a collector in the substrate, a base aligned over the collector, and an emitter aligned over the base). )), which are not easily integrated in advanced SOI processing technology platforms.

Contents of the invention

Embodiments of semiconductor structures are disclosed herein. The semiconductor structure may include a lateral bipolar junction transistor (BJT). The lateral BJT may include a collector, an emitter, and a base laterally between the collector and the emitter. The semiconductor structure may further comprise a first dielectric layer, in particular a dielectric stress layer only partially covering the lateral BJT, one end of which is located above the lateral BJT between the collector and the emitter. For example, the first dielectric layer may be located over the collector and also extend over the base such that one end of the first dielectric layer is aligned over the base.

Embodiments of semiconductor structures formed in advanced silicon-on-insulator (SOI) technology platforms are disclosed herein. In these embodiments, the semiconductor structure may include a semiconductor substrate, an insulator layer on the semiconductor substrate, and a semiconductor layer on the insulator layer. The semiconductor structure may include a lateral bipolar junction transistor (BJT), especially a lateral heterojunction bipolar transistor (HBT). The lateral HBT may include a base. The base may include a first base region located in the semiconductor layer, a second base region located on the first base region, and a base region located on the second base region and wider than the second base region. of the third base region. The lateral HBT may also include a collector and an emitter. The base may be located laterally between the collector and the emitter. Furthermore, the collector and the emitter may be made of a first semiconductor material, while at least the second base region may be made of a second semiconductor material different from the first semiconductor material, thereby providing a heterojunction. The semiconductor structure may further comprise a first dielectric layer, in particular a dielectric stress layer only partially covering the lateral BJT, one end of which is located above the lateral HBT between the collector and the emitter. For example, the first dielectric layer may be located over the collector and also extend over the base such that one end of the first dielectric layer is aligned over the base.

Embodiments of methods for forming the semiconductor structures described above are also disclosed herein. The method embodiment may include forming a lateral bipolar junction transistor (BJT) including a collector, an emitter, and a base laterally between the collector and the emitter. The method embodiment may further include forming a first dielectric layer, especially a dielectric stress layer partially covering the lateral BJT, one end of which is located above the lateral BJT between the collector and the emitter.

Description of drawings

The present invention will be better understood from the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, and in which:

1A-1B are layout and cross-sectional views, respectively, showing an embodiment of the disclosed semiconductor structure having a lateral bipolar junction transistor partially covered by a dielectric stress layer;

2 is a flowchart showing an embodiment of a method of forming a semiconductor structure having a lateral bipolar junction transistor partially covered by a dielectric stress layer;

Figure 3.1 is a cross-sectional view showing a partially completed semiconductor structure formed according to the flowchart of Figure 2;

Figure 3.2 is a cross-sectional view showing a partially completed semiconductor structure formed according to the flowchart of Figure 2;

3.3A and 3.3B are top and cross-sectional views, respectively, showing a partially completed semiconductor structure formed according to the flowchart of FIG. 2;

3.4 is a cross-sectional view showing a partially completed semiconductor structure formed according to the flowchart of FIG. 2;

3.5A and 3.5B are top and cross-sectional views, respectively, showing a partially completed semiconductor structure formed according to the flowchart of FIG. 2;

3.6A and 3.6B are top and cross-sectional views, respectively, showing a partially completed semiconductor structure formed according to the flowchart of FIG. 2;

3.7 is a cross-sectional view showing a partially completed semiconductor structure formed according to the flowchart of FIG. 2;

3.8 is a cross-sectional view showing a partially completed semiconductor structure formed according to the flowchart of FIG. 2;

Figure 3.9 is a cross-sectional view showing a partially completed semiconductor structure formed according to the flowchart of Figure 2;

Figure 3.10 is a cross-sectional view showing a partially completed semiconductor structure formed according to the flowchart of Figure 2;

Figure 3.11 is a cross-sectional view showing a partially completed semiconductor structure formed according to the flowchart of Figure 2;

Figure 3.12 is a cross-sectional view showing a partially completed semiconductor structure formed according to the flowchart of Figure 2;

Figure 3.13 is a cross-sectional view showing a partially completed semiconductor structure formed according to the flowchart of Figure 2; and

FIG. 3.14 is a cross-sectional view showing a partially completed semiconductor structure formed according to the flowchart of FIG. 2 .

Detailed ways

As noted above, advantages associated with making complementary metal-oxide-semiconductor (CMOS) designs utilizing advanced silicon-on-insulator (SOI) process technology platforms, such as fully depleted silicon-on-insulator (FDSOI) process technology platforms, include, for example, reduced power, Reduced area consumption, reduced cost, high performance, multiple core threshold voltage (Vt) selections, and more. CMOS fabricated on such SOI wafers are designed for use in a variety of applications, including but not limited to Internet-of-Things (IOT) devices, wearable devices, smartphone processors, automotive electronics, and radio frequency integration circuits (RFICs) including millimeter wave (mmWave) ICs. These same applications can benefit from including bipolar junction transistors (BJTs) since BJTs tend to have larger drives and are generally considered better suited for analog functions than field effect transistors (FETs). However, such BJTs are typically formed as vertical devices (e.g., with a collector in the substrate, a base aligned over the collector, and an emitter aligned over the base), which are not easily integrated into advanced SOI processing technology platform.

In view of the foregoing, embodiments of semiconductor structures having lateral bipolar junction transistors (BJTs) are disclosed herein. This semiconductor structure can be easily integrated into advanced silicon-on-insulator (SOI) technology platforms. Also, in order to maintain or improve performance characteristics such as cutoff frequency (fT)/maximum oscillation frequency (fmax) and beta cutoff frequency (which would otherwise be negatively affected by changing the BJT orientation from vertical to lateral ), the semiconductor structure may also include a dielectric stress layer partially covering the lateral BJT to enhance charge carrier mobility (e.g., a tensile strain layer in the case of an NPN transistor, or a tensile strain layer in the case of a PNP transistor compressively strained layer), and optionally, the lateral BJT may be configured as a lateral heterojunction bipolar transistor (HBT). Methods of forming the semiconductor structures are also disclosed herein.

1A-1B are layout and cross-sectional views, respectively, showing an embodiment of a disclosed semiconductor structure 100 having a lateral bipolar junction transistor (BJT) 150 partially covered by a dielectric stress layer 180 . It should be noted that lateral BJT 150 can be a standard BJT, where the collector, emitter, and base are made of the same semiconductor material (eg, silicon), or a heterojunction bipolar transistor (HBT), where , at least a portion of the base is made of a different semiconductor material (eg, silicon germanium) than the collector and emitter.

Specifically, the semiconductor structure 100 may be, for example, a semiconductor-on-insulator structure (eg, a silicon-on-insulator (SOI) structure). That is, the semiconductor structure 100 may include a semiconductor substrate 101 . The semiconductor substrate 101 may be a first semiconductor material (eg, silicon), which is a single crystal structure.

Alternatively, the semiconductor substrate 101 may be doped to have P-type conductivity at a lower conductivity level. Thus, for example, the semiconductor substrate 101 may be a P-silicon substrate.

Optionally, the semiconductor substrate 101 may include a buried well 102 (also referred to as a buried dopant implantation region). Buried well 102 may be doped to have P-type conductivity (eg, to be a buried Pwell). Alternatively, buried well 102 may be doped to have N-type conductivity (eg, as a buried Nwell).

The semiconductor structure 100 may also include an insulator layer 103 on the top surface of the semiconductor substrate 101 (eg, over the buried well 102 ). The insulator layer 103 may be, for example, a layer of silicon dioxide (also referred to herein as a buried oxide (BOX) layer) or any other suitable layer of insulator material.

The semiconductor structure 100 may further include a semiconductor layer 104 on the insulator layer 103 . The semiconductor layer 104 can be a single crystal structure. The semiconductor layer 104 can be the same semiconductor material as the semiconductor substrate 101 . That is, the semiconductor layer 104 may be made of a first semiconductor material (eg, silicon). Alternatively, the semiconductor layer 104 may be a different semiconductor material than the semiconductor substrate 101 . That is, the semiconductor layer 104 may be made of a second semiconductor material (eg, silicon germanium). The semiconductor layer 104 may be undoped. Alternatively, the semiconductor layer 104 may be doped. The doping of the semiconductor layer 104 can vary depending on whether the lateral BJT 150 is an NPN or PNP transistor. For example, for an NPN transistor, the semiconductor layer 150 can be doped to have P-type conductivity at a lower conductivity (e.g., to become a P-semiconductor layer), while for a PNP transistor, the semiconductor layer 104 can be doped to have P-type conductivity at a lower conductivity. Has N-type conductivity at a lower conductivity level (eg, becomes an N-semiconductor layer).

The semiconductor structure 100 may further include a shallow trench isolation (STI) region 106 . STI region 106 may extend substantially vertically through semiconductor layer 104 to insulator layer 103 and may define the boundary of a device region including lateral BJT 150 .

As mentioned above, the semiconductor structure 100 may also include a lateral BJT 150 . Those skilled in the art will appreciate that a BJT typically includes three terminals: a collector, an emitter, and a base between the collector and the emitter. In a vertical BJT, the collector, base, and emitter are stacked vertically. In a lateral BJT, the base is located laterally between the collector and emitter. In any case, the base will include at least an extrinsic base region of a first type of conductivity, and the collector and emitter will have a second type of conductivity different from the first type of conductivity. Therefore, an NPN transistor will at least include a P-type extrinsic base, an N-type collector, and an N-type emitter; and a PNP transistor will at least include an N-type extrinsic base, a P-type collector, and a P-type emitter. In a standard BJT, the same semiconductor material (such as silicon) is used for the base, collector, and emitter. Alternatively, different semiconductor materials may be used. In this case, the BJT is called a heterojunction bipolar transistor (HBT). Those skilled in the art will appreciate that a heterojunction bipolar transistor (HBT) is a BJT in which the collector and emitter are at least partially made of one semiconductor material and the base is at least partially made of a different semiconductor material. become. Different semiconductor materials are used at the emitter-base junction and at the base-collector junction to form heterojunctions suitable for higher frequencies of operation. Thus, in semiconductor structure 100 , lateral BJT 150 may include three terminals: collector 133 , emitter 132 , and base 131 laterally between collector 133 and emitter 132 .

The base 131 may be located above the insulator layer 103 and may include, for example, three different stacked regions. The three different stack regions may include a first base region 131.1, a second base region 131.2 above the first base region, and a third base region 131.3 above the second base region.

The first base region 131.1 may be located within the semiconductor layer 104 and may in particular comprise the first region 125 of the semiconductor layer 104, which optionally has a concave top surface. As mentioned above, the semiconductor layer 104 may be a single crystal structure, and may be a first semiconductor material (eg, silicon) or a second semiconductor material (eg, silicon germanium). The first region 125 may be undoped or doped. For example, in the case of an NPN transistor, the first region may be a P-region, or in the case of a PNP transistor, the first region may be an N-region.

The second base region 131.2 can be the epitaxial semiconductor layer 112 . For a standard BJT, the epitaxial semiconductor layer 112 may be a first semiconductor material (eg, silicon). For HBT, the epitaxial semiconductor layer 112 may be a second semiconductor material (eg, silicon germanium). In any event, the epitaxial semiconductor layer 112 can fill the narrower base opening formed by the first side spacer 108 (e.g., silicon nitride or some other suitable dielectric side spacer material). The space between the formed side spacers) is defined and aligned over the first region 125 of the semiconductor layer 104 . In other words, the second base region 131.2 is located laterally between the first side spacers 108 and is aligned above and in contact with the first base region 131.1, as shown. Epitaxial semiconductor layer 112 may be selectively grown from semiconductor layer 104 during processing so that it is a substantially monocrystalline structure. Also, the epitaxial semiconductor layer 112 may be undoped (ie, intrinsic) or doped, as described below.

The doping of the epitaxial semiconductor layer 112 can vary depending on whether the lateral BJT 150 is an NPN or PNP transistor. For example, for an NPN type transistor, the epitaxial semiconductor layer 112 may be undoped, or alternatively, may be doped to have P-type conductivity at a lower conductivity level, or have a gradient P-type profile (e.g., from a semiconductor layer undoped or low doped near the semiconductor layer 104 to higher doped far away from the semiconductor layer 104). Thus, for example, for an NPN type transistor, the second base region 131.2 may be an intrinsic base region (eg, an i-SiGe base region), or alternatively, a P-base region with undoped or P - Gradient P-type profiled base region to P or P+. However, for a PNP type transistor, the epitaxial semiconductor layer 112 may be undoped, or alternatively, may be doped to have N-type conductivity at a lower conductivity level, or have a gradient N-type profile (e.g., from a semiconductor layer undoped or low doped near the semiconductor layer 104 to higher doped far away from the semiconductor layer 104). Thus, for example, for a PNP type transistor, the second base region 131.2 may be an intrinsic base region (eg, an i-SiGe base), or alternatively, an N-base region with undoped or N- Gradient N-type profiled base region to N or N+.

It should be noted that the second side spacer 107 (eg, a side spacer made of silicon dioxide or some other suitable dielectric side spacer material) may be laterally adjacent to the The first side spacer 108 is provided. The first and second side spacers may have substantially the same height, and in particular, the tops of the first and second side spacers may be substantially coplanar.

The third base region 131.3 may be aligned above the second base region 131.2, may be immediately adjacent to and may be wider than the second base region 131.2, such that it extends laterally above the first side spacer 108 and the second side spacer 107 . Therefore, the base 131 is substantially T-shaped. As shown, the opposite sidewalls of the third base region 131.3 may be substantially vertically aligned with the outer vertical surface of the second side spacer 107 . The third base region 131.3 may be the epitaxial semiconductor layer 113 composed of the first semiconductor material (eg silicon) or alternatively some other suitable base semiconductor material. The epitaxial semiconductor layer 113 may be grown non-selectively during processing to make it a substantially polycrystalline structure (eg, to make it polysilicon). Epitaxial semiconductor layer 113 may be doped, and the doping will vary depending on whether lateral BJT 150 is an NPN or PNP transistor. For example, for an NPN transistor, the epitaxial semiconductor layer 113 can be doped to have P-type conductivity at a higher conductivity level, especially at a higher conductivity level compared to the substrate and at a higher conductivity level than the underlying base region. The conductivity level is such that the third base region 131.3 is, for example, a P+ extrinsic base region. For PNP-type transistors, the epitaxial semiconductor layer 113 can be doped to have N-type conductivity at a higher conductivity level, especially at a higher conductivity level than the underlying base region, so that the third base region 131.3 is, for example, N+ extrinsic base region.

It should be noted that a third side spacer 115 (eg, a side spacer made of silicon nitride or some other suitable dielectric side spacer material) may be disposed laterally adjacent to the opposite sidewall of the third base region 131.3, And it can also cover the outer vertical surface of the lower second side spacer 107 .

As noted above, the three terminals of lateral BJT 150 may also include collector 133 and emitter 132 on opposite sides of base 131 .

In one example structure, the collector 133 and the emitter 132 may be substantially symmetrical. The collector 133 may include a first collector region 133.1 and a second collector region 133.2 on the first collector region 133.1. The emitter 132 may include a first emitter region 132.1 and a second emitter region 132.2 on the first emitter region 132.1. The first collector region 133.1 and the first emitter region 132.1 may include a doped region 121 in the semiconductor layer 104, optionally having a concave top surface (not shown) and positioned opposite the first base region 131.1. side (that is, the first base region 131.1 is laterally located between the first collector region 133.1 and the first emitter region 132.1). The second collector region 133.2 and the second emitter region 132.2 may be the epitaxial semiconductor layer 122 composed of a first semiconductor material, such as silicon, and may be doped. The doping of the epitaxial semiconductor layer 122 may vary depending on whether the lateral BJT 150 is an NPN transistor or a PNP transistor. For example, for an NPN transistor, the epitaxial semiconductor layer 122 may be doped to have N-type conductivity at a higher conductivity level. Also, annealing performed during processing may cause portions of the underlying semiconductor layer 104 to also be doped to have N-type conductivity at a higher conductivity level (ie, see doped region 121 ). Thus, for example, for an NPN type transistor, the first and second collector regions 132.1-32.2 and the first and second emitter regions 133.1-133.2 may be N+ collector and emitter regions. For a PNP transistor, the epitaxial semiconductor layer 122 may be doped to have P-type conductivity at a higher conductivity level. Also, annealing performed during processing may cause portions of the underlying semiconductor layer 104 to also be doped to have P-type conductivity at a higher conductivity level (ie, see doped region 121 ). Thus, for example, for a PNP type transistor, the first and second collector regions 132.1-132.2 and the first and second emitter regions 133.1-133.2 may be P+ regions.

It should be noted that the configuration of the collector 133 and the emitter 132 described above is provided for illustrative purposes. Alternatively, the regions 132-133 may be asymmetrical and/or have some other suitable configuration. In any case, base 131 is located laterally between collector 133 and emitter 132 .

Optionally, the lateral BJT 150 may further include a metal silicide layer 199 on the uppermost surfaces of the base 131 , the collector 133 and the emitter 132 . The metal silicide layer 199 may be, for example, cobalt silicide (CoSi), nickel silicide (NiSi), tungsten silicide (WSi), titanium silicide (TiSi), or any other suitable layer of metal silicide material.

The semiconductor structure 100 may also include a first dielectric layer 180 that only partially covers the lateral BJT 150 . The first dielectric layer 180 may be a dielectric stress layer. In some embodiments, the first dielectric layer 180 may be, for example, a silicon nitride layer. The first dielectric layer 180 may be formed to have tensile strain or compressive strain. Specifically, the first dielectric layer 180 (ie, the dielectric stress layer) may have tensile strain or compressive strain, depending on whether the lateral BJT 150 is an NPN type transistor or a PNP type transistor. For example, for NPN transistors, the first dielectric layer 180 can be a tensile strain layer to enhance electron mobility, and for a PNP transistor, the first dielectric layer 180 can be a compressive strain layer to enhance hole mobility. . Such dielectric stress layers apply corresponding strains to the underlying lateral BJT components to enhance performance by enhancing charge carrier mobility.

For example, first dielectric layer 180 may cover only one side of lateral BJT 150 , and one end 189 of first dielectric layer 180 may be aligned over lateral BJT 150 somewhere between collector 133 and emitter 132 . In some embodiments, the first dielectric layer 180 may completely cover the collector 133 and may partially cover the base 131 such that one end 189 of the first dielectric layer 180 is aligned above the base 131 and stress is applied to Collector-base junction as shown in the figure. Alternatively, the first dielectric layer 180 can completely cover the collector region 133, and can also completely extend above the base electrode 131, so that one end 189 of the first dielectric layer 180 is at the second end between the base electrode 131 and the emitter electrode 132. The three side spacers 115 are aligned above. With the first dielectric layer disposed over collector 133 and at least partially over base 131 , collector 133 and base 131 will be strained while emitter 132 will remain relaxed.

For example, in the case of an NPN type transistor (where the first dielectric layer 180 is tensile strained), the collector 133 would be a longitudinally stretched and vertically compressed collector, and the base 131 would similarly be longitudinally stretched and vertically compressed. A compressed base, while the emitter 132 will be a relaxed emitter. Whereas in the case of a PNP type transistor (where the first dielectric layer 180 is compressively strained), the collector 133 would be a longitudinally compressed and vertically stretched collector, and the base 131 would similarly be longitudinally compressed and vertically stretched base, while the emitter 132 will be the relaxed emitter. The greatest performance advantages, especially enhanced charge carrier mobility, have been shown in embodiments with such an asymmetric dielectric stress layer over the collector-base junction rather than the emitter-base junction, This results in a faster switching speed.

However, it should be understood that these figures are not intended to be limiting, and instead, the first dielectric layer 180 may cover different portions of the transistor to fine-tune the strain applied to different components of the lateral BJT 150 . For example, the first dielectric layer 180 can only completely cover the collector 133 without extending to the base 131, so that the end 189 of the first dielectric layer 180 is on the third side between the base 131 and the collector 133. The top of the spacer wall 115 is aligned. In this case, only the collector will be strained, while the base and emitter will be relaxed. Alternatively, the first dielectric layer 180 may only partially cover the collector 133 and only partially cover the base 131 so that one end of the first dielectric layer 180 is aligned over the collector 133 and the other end of the first dielectric layer 180 189 is aligned over the base 131, alternatively, the first dielectric layer 180 may only partially cover the collector 133 and be completely over the base 131 so that one end of the first dielectric layer 180 is aligned over the collector 133 and the first The other end 189 of the dielectric layer 180 is aligned over the third side spacer 115 between the emitter 132 and the base 131 . In these cases, the collector and base will be strained to a lesser extent, while the emitter remains relaxed. Alternatively, first dielectric layer 180 may be located on emitter 132, and optionally, extend onto and/or over base 131 without further extending onto collector 133 (eg, so that the emitter and ( optionally) the base is strained and the set is relaxed), and so on.

The semiconductor structure 100 may also include one or more second dielectric layers 185 on the first dielectric layer and further extending laterally beyond the end 189 of the first dielectric layer and to the relaxed lateral BJT. partially (eg, over collector 133 ) and on STI 106 . The second dielectric layer may include, for example, one or more conformal dielectric layers (eg, a conformal silicon nitride etch stop layer) and a blanket dielectric layer (eg, a blanket dielectric layer) on the conformal dielectric layer. layer of silicon dioxide or a coating of some other suitable dielectric material). The semiconductor structure 100 may also include middle of the line (MOL) contacts including contacts extending through the dielectric layer to the base, collector and emitter.

By using the first dielectric layer 180, in particular a dielectric stress layer for enhanced charge carrier mobility (e.g. a tensile strain layer in the case of NPN transistors or a compressive strain in the case of PNP transistors) strained layer) partially covers the lateral BJT, and by optionally configuring the lateral BJT as a lateral HBT (e.g., base comprising SiGe and emitter and collector comprising Si), performance characteristics (e.g., cut-off frequency (fT) / maximum oscillation frequency (fmax) and beta (beta) cutoff frequency).

Referring to the flowchart of FIG. 2, an embodiment of a method of forming a semiconductor-on-insulator structure (eg, a silicon-on-insulator (SOI) structure), such as the structure 100 described in detail above and shown in FIGS. 1A-1B , is also disclosed herein, The structure includes a lateral bipolar junction transistor (BJT) (eg, a standard BJT or a heterojunction bipolar transistor (HBT)) partially covered by a first dielectric layer, especially a dielectric stress layer, to enhance performance.

Embodiments of the method may begin with an initial semiconductor-on-insulator structure (see process 202 and FIG. 3.1 ). The semiconductor-on-insulator structure may include a semiconductor substrate 101 , an insulator layer 103 on the top surface of the semiconductor substrate 101 , and a semiconductor layer 104 on the insulator layer 103 . The semiconductor substrate 101 and the semiconductor layer 104 may, for example, be made of the same semiconductor material, especially a first semiconductor material (eg, silicon or some other suitable semiconductor substrate material). Alternatively, the semiconductor layer 104 may be made of a second semiconductor material different from the first semiconductor material (eg, silicon germanium or some other suitable semiconductor material instead of silicon). In any case, the semiconductor substrate 101 and the semiconductor layer 104 may have a single crystal structure. The semiconductor substrate 101 may be doped to have P-type conductivity at a lower conductivity level. Thus, for example, the semiconductor substrate 101 may be a P-silicon substrate. The insulator layer 103 may be a layer of silicon dioxide (also referred to herein as a buried oxide (BOX) layer) or some other suitable layer of insulator material.

Optionally, a dopant implantation process may be performed to form a well 102 (also referred to as a dopant implantation region) in the semiconductor substrate, especially at the top surface of the semiconductor substrate adjacent to the insulator layer 103 (see Process 204 and Figure 3.2). It should be noted that the conductivity type of well 102 may vary depending on whether an NPN type transistor or a PNP type transistor is being formed. For example, for an NPN type transistor, a P-type dopant can be implanted into the top surface of the P-substrate adjacent to the insulator layer 103, so that the formed well 102 is a Pwell and has the same characteristics as the adjacent P-substrate. Lower compared to higher P-type conductivity levels. For PNP transistors, N-type dopants can be implanted on the top surface of the P-substrate adjacent to the insulator layer 103, so that the formed well 102 is a Nwell.

Alternatively, if the semiconductor layer 104 is made of a first semiconductor material (eg, silicon) and the semiconductor layer 104 is preferably made of a second semiconductor material (eg, silicon germanium), a conversion process (see process 206 and Figure 3.2). For example, a germanium enrichment process may be performed in process 206 to convert the silicon layer on the insulator layer 103 into a silicon germanium layer on the insulator layer 103 . Germanium enrichment processes are well known in the art, therefore, details of such processes are omitted from this description to allow the reader to focus on salient aspects of the disclosed embodiments. The silicon germanium layer thus formed can still be a single crystal structure.

Next, a lateral bipolar junction transistor (BJT) may be formed using the semiconductor layer 104 (see process 208 ). It should be noted that the lateral BJT formed in process 208 may be a standard BJT, wherein the collector, emitter, and base comprise the same semiconductor material (eg, silicon), or an HBT, wherein at least a portion of the base comprises A semiconductor material that is different from the collector and emitter. In addition, it should also be noted that in the following discussion about the process steps, the first type conductivity and the second type conductivity are cited, and the first type conductivity and the second type conductivity are P-type conductivity and N-type conductivity, respectively. Type conductivity or N-type conductivity and P-type conductivity, respectively, depends on whether an NPN-type transistor or a PNP-type transistor is formed in process 208 . Specifically, for NPN transistors, the first type of conductivity refers to P-type conductivity and the second type of conductivity refers to N-type conductivity, while for PNP-type transistors, the first type of conductivity refers to N-type conductivity. Type conductivity and the second type conductivity refers to P-type conductivity.

Formation of the lateral BJT may begin with an optional dopant implantation process to dope the semiconductor layer 104 with a first-type conductivity dopant, thereby rendering the semiconductor layer 104 with the first-type conductivity at a lower conductivity level ( See Process 210 and Figure 3.2). For example, for an NPN transistor, a P-type dopant can be implanted so that the semiconductor layer has P-type conductivity at a lower conductivity level (e.g., making the semiconductor layer a P-semiconductor layer), while for a PNP transistor , N-type dopants may be implanted to render the semiconductor layer N-type conductivity at a lower conductivity level (eg, make the semiconductor layer an N-semiconductor layer).

Shallow trench isolation (STI) regions 106 may be formed (see process 212 and Figures 3.3A and 3.3B). STI regions 106 may be formed such that they define the boundaries of device regions and such that they extend substantially vertically through semiconductor layer 104 to insulator layer 103 . Specifically, at process 212, trenches for the STI region may be formed (eg, photolithographically patterned and etched using conventional STI processing techniques) such that they extend substantially vertically through the semiconductor layer to the insulator layer, and such that They define device regions within the semiconductor layer. The trench may be further filled with one or more layers of isolation material (eg, silicon dioxide, silicon nitride, etc.), and a chemical mechanical polishing (CMP) process may be performed to remove Any such insulating material.

Next, isolation layer 109 may be formed over semiconductor layer 104 and adjacent STI region 106 (see process 214 and FIG. 3.4 ). The isolation layer 109 can be, for example, a silicon dioxide layer formed in process 214 using a conventional oxidation process.

Next, a base opening 110 may be formed in the isolation layer 109 (see process 216 and FIGS. 3.5A and 3.5B). Specifically, in process 214 , conventional photolithography processing and etching techniques may be performed to form base opening 110 in isolation layer 109 . For example, the base opening 110 may be formed to extend vertically through the isolation layer 109 to the semiconductor layer 104, thereby completely traversing and exposing a central portion of the semiconductor layer, such that the base opening 110 has a first width (Wbo), and The portion of the semiconductor layer on either side of the base opening 110 remains covered.

Next, first side spacers 108 may be formed within the base opening 110 . For example, a dielectric spacer material can be conformally deposited to cover the top surface of the isolation layer 109 and line the base opening 110 (see FIGS. 3.6A and 3.6B ). The dielectric spacer material may be, for example, silicon nitride or some other suitable dielectric spacer material different from the isolation material of the isolation layer 109 such that it can be selectively etched relative to the isolation material 107 . Next, a selective anisotropic side spacer etch process may be performed to remove the dielectric spacer material from the horizontal surfaces leaving it intact on the vertical surfaces within the base opening (ie, as the first side spacer 108). By forming the first side spacer 108 in the base opening 110, the width of the base opening 110 is narrowed from the first width (Wbo) to a second width (Wfbo) narrower than the first width, and the semiconductor is exposed. The first region of the layer. It should be noted that the first width may be equal to or close to the minimum width achievable using conventional photolithographic patterning, and the second width may be smaller than the minimum width.

Optionally, the first region 125 of the semiconductor layer 104 exposed at the bottom of the base opening may be recessed (see process 218 and FIG. 3.7 ). That is, a selective anisotropic etching process may be performed to recess (ie, etch back) the top surface of the first region 125 of the semiconductor layer 104 exposed at the bottom of the base opening 110 . This selective anisotropic etch process should be performed without etching completely through the semiconductor layer 104 so that at least an underlying portion of the first region 125 of the semiconductor layer 104 remains intact and can subsequently be used as a seed layer. A first region 125 of semiconductor layer 104 (recessed (as shown) or not) aligned under base opening 110 may correspond to base 131 of a lateral BJT (eg, a standard BJT or HBT) being formed. The first base region 131.1.

Next, a second base region 131.2 may be formed in the base opening 110 above the first base region 131.1 (see process 220 and FIG. 3.8). Specifically, epitaxial semiconductor layer 112 may be grown on the top surface of exposed first region 125 of semiconductor layer 104 within narrower base opening 110 (defined by the space between first side spacers 108 ). At process 220, the epitaxial semiconductor layer 112 may be selectively grown from the semiconductor layer 104 to have a substantially monocrystalline structure. For a standard BJT, this semiconductor layer 104 and the epitaxial semiconductor layer 112 may be the first semiconductor material (eg, silicon). For HBT, the semiconductor layer 104 can be a first or second semiconductor material (eg, silicon or silicon germanium), but the epitaxial semiconductor layer 112 can be specifically a second semiconductor material (eg, silicon germanium). In either case, epitaxial semiconductor layer 112 may be grown at process 220 without any in-situ doping (ie, left undoped/intrinsic). Alternatively, the epitaxial semiconductor layer 112 may be doped in situ at process 220 to have the first type conductivity at a lower conductivity level, or to have a gradient dopant profile (eg, from adjacent to the first base undoped or lowly doped pole region to higher doped away from the first base region).

Therefore, after process 220, for an NPN-type standard BJT, the second base region 131.2 can be a monocrystalline intrinsic silicon base region (i-Si base), a P-monocrystalline silicon base region, or a The single crystal silicon base region of the first base region is undoped or has a P- to P or P+ gradient dopant distribution away from the first base region. For an NPN type HBT, the second base region 131.2 can be a single crystal intrinsic silicon germanium base region (i-SiGe base), a single crystal P-silicon germanium base region, or have The undoped or P- to P or P+ graded dopant distribution away from the first base region of the single crystal silicon germanium base region. For a PNP type standard BJT, the second base region 131.2 can be a single crystal intrinsic silicon base region (i-Si base), an N-single crystal silicon base region, or a A monocrystalline silicon base region with a gradient dopant profile of undoped or N- to N or N+ away from the first base region. For a PNP type HBT, the second base region 131.2 can be a single crystal intrinsic silicon germanium base region (i-SiGe base), a single crystal N-silicon germanium base region, or have A single crystal silicon germanium base region with a gradient dopant distribution from undoped or N- to N or N+ away from the first base region.

Another epitaxial semiconductor layer 113 made of the first semiconductor material (eg, silicon) or some other suitable base semiconductor material may be grown on the second base region 131.1 and on the isolation layer 109 (see process 222 and FIG. 3.9). In process 222, the epitaxial semiconductor layer 113 may be non-selectively grown from the second base region and the isolation layer to have a substantially polycrystalline structure. In process 222, the epitaxial semiconductor layer 113 may be in-situ doped to have the first type conductivity at a higher conductivity level. Therefore, for example, for an NPN-type standard BJT or HBT, the epitaxial semiconductor layer 113 can be a P+ polysilicon layer (for example, a P+ polysilicon layer), and for a PNP-type standard BJT or HBT, the epitaxial semiconductor layer 113 can be an N+ polysilicon layer. A crystalline semiconductor layer (eg, N+ polysilicon layer).

A thin cap layer (eg, a thin silicon nitride cap layer 114 ) may be formed on the epitaxial semiconductor layer 113 (see FIG. 3.9 ).

Subsequently, a base stack may be formed (see process 224 and Figure 3.10). Specifically, a photolithographic patterning and etching process may be performed to define the third base region 131.3 from the portion of the epitaxial semiconductor layer 113 aligned over the second base region 131.2, and further define (from the isolation layer 109) the lateral The second side spacer 107 is disposed adjacent to the first side spacer 108 . As a result of the photolithographic patterning and etching process performed in process 224, the third base region 131.3 formed may be aligned over, immediately adjacent to, and wider than, the second base region 131.2, thereby extending laterally. Above the first side spacer 108 and the formed second side spacer 107 . Therefore, the base 131 is substantially T-shaped, and the opposite sidewalls of the third base region 131 . 3 are substantially vertically aligned with the outer vertical surfaces of the second side spacers 107 . Next, a third side spacer 115 may be formed on the base stack, especially adjacent to the opposite sidewall of the third base region 131.3, and also adjacent to the outer vertical surface of the underlying second side spacer 107 (see FIG. 3.10) . For example, another dielectric spacer material can be conformally deposited to cover the base stack. The dielectric spacer material used to form the third side spacer can be, for example, silicon nitride or some other suitable dielectric spacer material. Next, a selective anisotropic side spacer etch process may be performed to remove horizontal surfaces of the semiconductor layer 104 on opposite sides of the base stack, particularly from the second and third regions 117a-117b, respectively. The dielectric spacer material, and keeps the dielectric spacer material intact on the vertical surface (ie, as the third side spacer 115).

Optionally, the second and third regions 117a-117b of the semiconductor layer 104 exposed during the formation of the third side spacer 115 may be recessed (not shown). That is, a selective anisotropic etching process may be performed to recess (ie, etch back) the top surface of the semiconductor layer 104 located in the second and third regions 117 a - 117 b of the semiconductor layer 104 . This selective anisotropic etch process should be performed without etching completely through the semiconductor layer 104 so that portions of the semiconductor layer 104 remain intact and can subsequently be used as a seed layer.

Next, a collector 133 and an emitter 132 may be formed on opposite sides of the base stack (see process 226 and FIG. 3.11 ). For example, additional semiconductors composed of the first semiconductor material (eg, silicon) or some other suitable collector/emitter semiconductor material may be selectively grown from the exposed semiconductor surfaces of the second and third regions 117a-117b of the semiconductor layer 104. The semiconductor layers 122 are epitaxially formed so that they have a substantially monocrystalline structure. At process 226, the additional epitaxial semiconductor layer 122 may be in-situ doped to have a second type of conductivity at a higher conductivity level. Therefore, for example, for an NPN type transistor, the additional epitaxial semiconductor layer 122 can be an N+ single crystal semiconductor layer (for example, an N+ silicon layer), and for a PNP type transistor, the additional epitaxial semiconductor layer 122 can be a P+ single crystal semiconductor layer (for example, P+ silicon layer). The subsequent annealing process can diffuse dopants from the additional epitaxial semiconductor layer 122 into the second and third regions 117 a - 117 b of the semiconductor layer to form the doped region 121 with the second type conductivity. In this case, the doped regions 121 of the second and third regions 117a-117b of the semiconductor layer 104 form the underlying emitter and collector regions 132.1, 133.1 of the emitter 132 and collector 133, respectively. Furthermore, an additional epitaxial semiconductor layer 122 grown on the second and third regions 117a-117b of the semiconductor layer 104 forms upper emitter and collector regions 132.2, 133.2 of the emitter 132 and collector 133, respectively. It should be noted that process 226 is only one example process flow that may be used to form emitter 132 and collector 133 on opposite sides of the base stack. Alternatively, any other suitable process flow may be used to form symmetric or asymmetric emitter/collector regions.

Optionally, the method embodiment may also include selectively removing the capping layer 114 from the top of the base 131, and forming a metal silicide layer 199 on the uppermost surfaces of the base 131, the collector 133, and the emitter 132 ( See Process 252 and Figure 3.12). The metal silicide layer 199 may be, for example, cobalt silicide (CoSi), nickel silicide (NiSi), tungsten silicide (WSi), titanium silicide (TiSi), or any other suitable layer of metal silicide material. Techniques for forming metal suicide layers are well known in the art and, therefore, are omitted from this description to allow the reader to focus on salient aspects of the disclosed embodiments.

This method embodiment may also include forming a conformal first dielectric layer 180 , particularly a dielectric stressor layer, such that it only partially covers the lateral BJT 150 (see process 254 and FIGS. 3.13-3.14 ). The first dielectric layer 180 (i.e., the dielectric stressor layer) can be, for example, a silicon nitride stressor layer that is deposited and further processed as desired to have tensile or compressive strain, depending on whether the lateral BJT 150 is an NPN type transistor or PNP type transistor. For example, for NPN type transistors, the first dielectric layer 180 can be deposited at process 254 and further processed as desired to make it a tensile strained layer, while for PNP type transistors, it can be deposited at process 254 and (optionally) The first dielectric layer 180 is further processed as desired to make it a compressively strained layer. Various techniques for forming tensile and compressive strained dielectric layers are well known in the art and can be used in the disclosed methods. However, the details of these techniques have been omitted from this description to allow the reader to focus on the salient aspects of the disclosed embodiments.

In any case, the first dielectric layer 180 can then be photolithographically patterned and etched so that it only partially covers the lateral BJT 150 and has a slit aligned over the transistor somewhere between the collector and emitter. one end. For example, first dielectric layer 180 may be photolithographically patterned and etched such that it covers only one side of lateral BJT 150 and that one end 189 is aligned over lateral BJT 150 somewhere between collector 133 and emitter 132. . In some embodiments, the first dielectric layer 180 may be patterned and etched such that it completely covers the collector 133, partially covers the base 131, and has an end 189 aligned over the base 131, as As shown in the figure. Alternatively, the first dielectric layer 180 may be photolithographically patterned and etched such that it completely covers the collector 133, extends completely over the base 131, and has a gap between the base 131 and the emitter 132. One end 189 of the third side spacer 115 is aligned above. With the first dielectric layer over collector 133 and at least partially over base 131 , collector 133 and base 131 (and the collector-base junction) will be strained, while emitter 132 will remain relaxed.

For example, in the case of an NPN type transistor (where the first dielectric layer 180 is tensile strained), the collector 133 would be a longitudinally stretched and vertically compressed collector, and the base 131 would similarly be longitudinally stretched and vertically compressed. A compressed base, while the emitter 132 will be a relaxed emitter. Whereas in the case of a PNP type transistor (where the first dielectric layer 180 is compressively strained), the collector 133 would be a longitudinally compressed and vertically stretched collector, and the base 131 would similarly be longitudinally compressed and vertically stretched base, while the emitter 132 will be the relaxed emitter. In embodiments having such an asymmetric dielectric stress layer over the collector-base junction rather than the emitter-base junction, the greatest performance advantages have been exhibited, especially enhanced charge carrier mobility, thereby Has a faster switching speed.

It should be understood that these figures are not intended to be limiting, and instead, the first dielectric layer can be patterned and etched so that it covers different portions of the lateral BJT, thereby fine-tuning the strain applied to different components of the lateral BJT 150 . For example, the first dielectric layer 180 can be patterned and etched so that it only completely covers the collector 133, so that it does not extend onto the base 131, and so that it has a gap between the base 131 and the collector 133. One end 189 aligned above the third side spacer 115 . In this case, only the collector will be strained, while the base and emitter will be relaxed. Alternatively, the first dielectric layer 180 may be patterned and etched so that it only partially covers the collector 133 , and so that it partially or completely covers the base 131 . In these cases, the collector and base will be strained to a lesser extent, while the emitter remains relaxed. Alternatively, first dielectric layer 180 may be patterned and etched such that it lies on emitter 132 and, optionally, extends onto and/or over base 131 without extending further to collector 133. (eg, to strain the emitter and (optionally) base, and relax the collector), and so on.

Also, it should be understood that the techniques described above for forming the first dielectric layer 180 that only partially covers the transistor are provided for purposes of illustration and are not intended to be limiting. For example, a masking layer may instead be formed over the partially completed structure. The masking layer can be patterned with openings exposing a portion of the lateral BJT and leaving another portion of the lateral BJT covered. The first dielectric layer (especially the dielectric stress layer) can be formed in the trench, and the mask layer can be selectively removed.

The method embodiment may also include forming one or more second dielectric layers 185 overlying the first dielectric layer 180 and further extending laterally beyond the end 189 of the first dielectric layer 180 to an area not covered by the first dielectric layer 180. Layer 180 overlies the portion of lateral BJT 150 (see process 256 ). Although not shown, these dielectric layers may include, for example, one or more conformal dielectric layers (e.g., another conformal silicon nitride etch stop layer) and a blanket dielectric layer overlying the conformal dielectric layer ( For example, a layer of silicon dioxide or a coating of some other suitable dielectric material). The method embodiment may also include forming mid-line (MOL) contacts including contacts extending through the dielectric layer to the base, collector, and emitter (see process 258 ).

It should be understood that in the above structures and methods, a semiconductor material refers to a material whose conductivity property can be changed by doping with impurities. Exemplary semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) Ga), indium (In) combined with group V elements such as nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb)) (for example, GaN, InP, GaAs or GaP). Pure semiconductor materials, especially semiconductor materials that are not doped with impurities that increase conductivity (ie, undoped semiconductor materials) are known in the art as intrinsic semiconductors. A semiconductor material doped with impurities to increase conductivity (ie, doped semiconductor material) is known in the art as an extrinsic semiconductor, and will be more conductive than an intrinsic semiconductor made from the same substrate. That is, extrinsic silicon will be more conductive than intrinsic silicon; extrinsic silicon germanium will be more conductive than intrinsic silicon germanium; and so on. Also, it should be understood that different impurities (ie, different dopants) can be used to obtain different conductivity types (eg, P-type conductivity versus N-type conductivity), and that the dopants can vary depending on the type used. depending on the semiconductor material. For example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, etc.) are typically doped with Group III dopants such as boron (B) or indium (In) to obtain P-type conductivity, typically doped with Group V Doping silicon-based semiconductor materials with substances such as arsenic (As), phosphorus (P) or antimony (Sb) to obtain N-type conductivity. Gallium nitride (GaN)-based semiconductor materials are typically doped with magnesium (Mg) to obtain P-type conductivity, and silicon (Si) or oxygen to obtain N-type conductivity. Those skilled in the art will also appreciate that different conductivity levels will depend on the relative concentration levels of dopants in a given semiconductor region.

The method as described above can be used in the manufacture of integrated circuit chips. A fabricator may distribute the resulting integrated circuit chips in raw wafer form (ie, as a single wafer with multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chip is provided in a single-chip package (such as a plastic carrier with pins attached to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier , which have single- or double-sided interconnects or embedded interconnects). In any event, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices, either as part of (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be anything that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

It is to be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. In addition, the term "comprising" used herein indicates the existence of said features, integers, steps, operations, elements and/or components, but does not exclude the existence or addition of one or more other features, integers, steps, operations, elements , components, and/or groups thereof. Moreover, terms such as "right", "left", "vertical", "horizontal", "top", "bottom", "above", "below", "parallel", "perpendicular", etc. as used herein are intended to relative positions when they are oriented and shown in the drawings (unless otherwise indicated), and terms such as "touching", "direct contact", "adjacent", "immediately adjacent", "immediately adjacent" and the like are intended to mean at least An element is in physical contact with another element (with no other element separating the elements). As used herein, the term "transverse" describes the relative position of elements when they are oriented and shown in the drawings, and particularly means that one element is located to the side of another element rather than above or below the other element. For example, an element laterally adjacent to another element will be next to the other element, an element laterally adjacent to another element will be directly next to the other element, and an element laterally around another element will be adjacent to and surround the other element. outer wall. The corresponding structures, materials, acts and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements specifically claimed.

The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen to best explain the principles of the described embodiments, the practical application or technical improvements over technologies known in the marketplace, or to enable a person of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (20)

1. A structure, comprising:

a transistor, comprising: a base; a collector; and an emitter, wherein the base is laterally located between the collector and the emitter; and

and a first dielectric layer partially covering the transistor, wherein one end of the first dielectric layer is positioned above the transistor between the collector and the emitter.

2. The structure of claim 1 wherein the first dielectric layer comprises a stress layer.

3. The structure of claim 1 wherein the first dielectric layer comprises a silicon nitride layer having one of tensile strain and compressive strain.

4. The structure of claim 1 wherein the transistor comprises an NPN heterojunction bipolar transistor and the first dielectric layer comprises a tensile strained layer.

5. The structure of claim 1 wherein the transistor comprises a PNP heterojunction bipolar transistor and the first dielectric layer comprises a compressively strained layer.

6. The structure of claim 1 wherein said first dielectric layer covers said collector and at least partially covers said base.

7. The structure of claim 6 further comprising a second dielectric layer on said first dielectric layer and further extending laterally beyond said end of said first dielectric layer above said emitter.

8. A structure, comprising:

an insulator layer;

a semiconductor layer on the insulator layer;

a transistor, comprising:

a base, comprising: a first base region within the semiconductor layer; a second base region located on the first base region; and a third base region located on the second base region and wider than the second base region;

a collector; and an emitter, wherein the base is laterally located between the collector and the emitter, wherein the collector and the emitter comprise a first semiconductor material, and wherein at least the second base region comprises a second semiconductor material different from the first semiconductor material; and

And a first dielectric layer partially covering the transistor, wherein one end of the first dielectric layer is positioned above the transistor between the collector and the emitter.

9. The structure of claim 8 wherein the first dielectric layer comprises a stress layer.

10. The structure of claim 8 wherein the first dielectric layer comprises a silicon nitride layer having one of tensile strain and compressive strain.

11. The structure of claim 10 wherein the transistor comprises an NPN heterojunction bipolar transistor and the first dielectric layer comprises a tensile strained layer.

12. The structure of claim 10 wherein the transistor comprises a PNP heterojunction bipolar transistor and the first dielectric layer comprises a compressively strained layer.

13. The structure of claim 8 wherein said first dielectric layer covers said collector and at least partially covers said base.

14. The structure of claim 13, further comprising a second dielectric layer on the first dielectric layer and further extending laterally beyond the end of the first dielectric layer above the collector.

15. A method, comprising:

Forming a transistor, the transistor comprising: a base; a collector; and an emitter, wherein the base is laterally located between the collector and the emitter; and

a first dielectric layer is formed to partially cover the transistor, wherein one end of the first dielectric layer is located over the transistor between the collector and the emitter.

16. The method of claim 15, wherein,

the forming of the transistor includes forming an NPN heterojunction bipolar transistor, an

Wherein the forming of the first dielectric layer includes forming a tensile strained layer.

17. The method of claim 15, wherein,

the forming of the transistor includes forming a PNP heterojunction bipolar transistor, an

Wherein the forming of the first dielectric layer includes forming a compressively strained layer.

18. The method of claim 15, wherein,

the collector and the emitter are formed to include a first semiconductor material, an

Wherein the base is formed to include: a first base region located in the semiconductor layer; a second base region located on the first base region; and a third base region located on and wider than the second base region, at least the second base region including a second semiconductor material different from the first semiconductor material.

19. The method of claim 15, wherein the first dielectric layer is formed to cover the collector and at least partially cover the base.

20. The method of claim 19, further comprising forming a second dielectric layer on the first dielectric layer and further extending laterally beyond the end of the first dielectric layer above the emitter.

Images