WO2023044719A1 - 一种指纹识别基板、电子设备和指纹识别方法 - Google Patents

一种指纹识别基板、电子设备和指纹识别方法 Download PDF

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Publication number
WO2023044719A1
WO2023044719A1 PCT/CN2021/120187 CN2021120187W WO2023044719A1 WO 2023044719 A1 WO2023044719 A1 WO 2023044719A1 CN 2021120187 W CN2021120187 W CN 2021120187W WO 2023044719 A1 WO2023044719 A1 WO 2023044719A1
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Prior art keywords
voltage
voltage signal
node
control
signal
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PCT/CN2021/120187
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English (en)
French (fr)
Inventor
董水浪
宁策
袁广才
胡合合
王利忠
姚念琦
薛大鹏
雷利平
许晨
王东方
李正亮
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/913,798 priority Critical patent/US20240212639A1/en
Priority to CN202180002683.2A priority patent/CN116171470A/zh
Priority to PCT/CN2021/120187 priority patent/WO2023044719A1/zh
Publication of WO2023044719A1 publication Critical patent/WO2023044719A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • Embodiments of the present disclosure relate to the field of display technology, and in particular, to a voltage supply unit, a voltage supply method, a display driving module, and a display device.
  • Oxide TFT oxide thin film transistors
  • an embodiment of the present disclosure provides a voltage supply unit, which is applied to a display panel and used to provide a control voltage signal for a driving circuit, and the voltage supply unit includes a step-down circuit and a first level conversion circuit;
  • the step-down circuit is used to receive a first voltage signal, and perform a step-down operation on the first voltage signal to obtain a second voltage signal;
  • the first level conversion circuit is connected to the step-down circuit, and is used for receiving an input control voltage, a third voltage signal and the second voltage signal, and according to the input control voltage, the third voltage signal and the The second voltage signal generates a control voltage signal such that the voltage value of the control voltage signal is less than a predetermined voltage value.
  • the step-down circuit includes a switch unit, a storage unit and a freewheeling unit;
  • the first end of the switch unit is connected to the input node of the step-down circuit, the second end of the switch unit is connected to the first node, and the switch unit is configured to input The signal is transmitted to the storage unit;
  • the storage unit is respectively connected to the first node, the second node and the output node of the step-down circuit, and the storage unit is configured to store the signal from the switch unit and store the signal from the switch unit when the switch unit is turned on. transmitting to the output node, and transmitting the stored signal from the switching unit to the output node when the switching unit is turned off;
  • the freewheeling unit is connected to the first node and the second node, and the freewheeling unit is configured to convert the signal stored in the storage unit into a current when the switch unit is turned off .
  • the switch unit includes:
  • a control switch tube the control switch tube has a control terminal, a first terminal and a second terminal, the control terminal of the control switch tube is connected to the control signal terminal to obtain a control signal, the first terminal of the control switch is connected to the The input node is connected, and the second end of the control switch is connected to the first node;
  • the storage unit includes:
  • first inductor one end of the first inductor is connected to the first node, and the other end is connected to the output node;
  • one end of the first capacitor is connected to the second node, and the other end is connected to the output node;
  • the freewheeling unit includes:
  • the anode of the first diode is connected to the second node, and the cathode of the first diode is connected to the first node;
  • the second node is grounded.
  • the predetermined voltage value is less than or equal to 27 volts.
  • the predetermined voltage ranges from 15 to 26 volts.
  • an embodiment of the present disclosure provides a voltage supply method, which is applied to the voltage supply unit according to any one of the first aspect, and the voltage supply method includes:
  • the step-down circuit receives a first voltage signal, and performs a step-down operation on the first voltage signal to obtain a second voltage signal;
  • the first level conversion circuit receives an input control voltage, a third voltage signal and the second voltage signal, and generates a control voltage signal according to the input control voltage, the third voltage signal and the second voltage signal, so as to making the voltage value of the control voltage signal smaller than a predetermined voltage value.
  • control voltage signal is a square wave voltage signal
  • the high voltage value of the control voltage signal is the voltage value of the second voltage signal, and the low voltage value of the control voltage signal is the voltage value of the third voltage signal;
  • the high voltage value of the control voltage signal is smaller than the predetermined voltage value.
  • an embodiment of the present disclosure provides a display drive module, including a drive circuit, a timing controller, a power management integrated circuit, and the voltage supply unit described in any one of the first aspects;
  • the timing controller is used to provide the input control voltage
  • the power management integrated circuit is used to provide the first voltage signal
  • the voltage supply unit is used for providing a control voltage signal to the driving circuit.
  • the display driving module further includes a second level conversion circuit, the second level conversion circuit is connected with the timing controller, the power management integrated circuit and the driving circuit, so The second level conversion circuit described above is used to receive the first timing control signal, the first driving control signal, the first voltage signal and the third voltage signal, and then generate the second timing signal, the common signal and the second drive control signals and transmit them to the drive circuit.
  • the drive circuit includes:
  • the input subcircuit is connected to the input signal terminal and the pull-up node, and the input subcircuit is used to transmit the input signal provided by the input signal terminal to the pull-up node under the control of the input signal terminal;
  • the pull-down node control subcircuit is connected to the input signal terminal, the first power supply voltage signal terminal, the pull-up node, and the first pull-down node, and the pull-down node control circuit is used to control the first power supply voltage signal terminal and under the control of the pull-up node, transmitting the power supply voltage signal provided by the first power supply voltage signal terminal to the first pull-down node;
  • the output subcircuit is connected with the pull-up node, the clock signal terminal, the first pull-down node, the third voltage signal terminal and the first output signal terminal, and the output subcircuit is used for the pull-up node Under control, the clock signal provided by the clock signal terminal is transmitted to the first output signal terminal, and under the control of the first pull-down node, the third voltage signal provided by the third voltage signal terminal transmitted to the first output signal terminal;
  • noise reduction sub-circuit connected to the pull-up node, the third voltage signal terminal, and the first pull-down node, and the noise reduction sub-circuit is used to, under the control of the first pull-down node, transmitting the third voltage signal provided by the third voltage signal terminal to the pull-up node;
  • the first reset subcircuit is connected to the pull-up node, the first reset signal terminal, and the third voltage signal terminal, and the first reset subcircuit is used for the reset signal provided at the first reset signal terminal. Under control, the third voltage signal provided by the third voltage signal terminal is transmitted to the first pull-down node.
  • an embodiment of the present disclosure provides a display device, including the display driving module described in any one of the third aspects.
  • the voltage supply unit of the embodiment of the present disclosure is applied to a display panel, and is used to provide a control voltage signal for a driving circuit.
  • the voltage supply unit includes a step-down circuit and a first level conversion circuit; the step-down circuit is used to receive the first level conversion circuit. a voltage signal, and perform a step-down operation on the first voltage signal to obtain a second voltage signal; the first level conversion circuit is connected to the step-down circuit for receiving an input control voltage and a third voltage signal and the second voltage signal, and generate a control voltage signal according to the input control voltage, the third voltage signal and the second voltage signal, so that the voltage value of the control voltage signal is less than a predetermined voltage value.
  • the embodiments of the present disclosure can realize the level control of the control voltage signal by setting the step-down circuit and the first level conversion circuit, which can reduce the impact of the high level of the control voltage signal on the performance of the display panel, and help to improve the performance of the display panel. Display panel reliability.
  • FIG. 1A is a circuit diagram of a driving circuit in an embodiment of the present disclosure
  • FIG. 1B is another circuit diagram of a driving circuit in an embodiment of the present disclosure
  • Fig. 2 is a driving timing diagram of the driving circuit shown in Fig. 1B;
  • FIG. 3 is a schematic diagram of a simulation of a transistor in an embodiment of the present disclosure
  • FIG. 4 is a relationship curve between an initial state and a failure state of a transistor in an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a failure mechanism of hot carrier injection in an embodiment of the present disclosure.
  • FIG. 6 is a circuit diagram of a test circuit in an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a display driving module provided in an embodiment of the present disclosure.
  • FIG. 8 is a circuit diagram of a step-down circuit according to an embodiment of the present disclosure.
  • Oxide TFT oxide thin film transistor
  • the inventors of the present disclosure found in the process of implementing the technical solutions of the present application that large-sized, high-resolution, high-refresh display panels require relatively high driving voltage.
  • Many large-size display panels use Gate driver On Array (GOA, array substrate drive circuit, when it is located in the row direction of the display panel, it is also called array substrate row drive) driving method to achieve narrow frame display and also help to reduce costs.
  • GOA Gate driver On Array
  • the driving circuit is used as an example for illustration.
  • the high level of GOA of a certain display panel is above 30V, and the low level is below -10V.
  • the driving voltage of GOA is usually about 32V for high-voltage VGH, and about -15V for low-voltage LVGL.
  • the driving circuit in the display device may include a multi-level driving sub-circuit, and the driving circuit may be used to provide a driving signal for a pixel circuit located in the effective display area.
  • the driving signal may be, for example, a gate driving signal. or light control signals, but not limited thereto.
  • a driving circuit is provided.
  • the driving circuit includes: an input subcircuit 101 , a pull-down node control subcircuit 102 , an output subcircuit 103 , a noise reduction subcircuit 104 and a first reset subcircuit 105 .
  • the input subcircuit 101 includes a first transistor M1, and the input subcircuit is connected to the input signal terminal I and the pull-up node PU, specifically, the first transistor M1
  • the control pole and the first pole of the control pole are connected to the input signal terminal I, and the second pole is connected to the pull-up node PU.
  • the input sub-circuit 101 is used to transmit the input signal provided by the input signal terminal I to the upper Pull node PU.
  • the pull-down node control sub-circuit 102 includes a fifth transistor M5, and the pull-down node control sub-circuit 102 is connected to the first power voltage signal terminal V1, the pull-up node PU, and the first pull-down node PD1.
  • the control electrode and the first electrode of the fifth transistor M5 are connected to the first power supply voltage signal terminal V1, and the second electrode of the fifth transistor M5 is connected to the first pull-down node PD1.
  • the pull-down node control circuit 102 is used to transmit the power voltage signal provided by the first power voltage signal terminal V1 to the first pull-down node PD1 under the control of the first power voltage signal terminal V1 and the pull-up node PU.
  • the pull-down node control subcircuit 102 further includes a first access unit, the first access unit specifically includes a sixth transistor M6, and in some embodiments, the first access unit further includes an eighth transistor M6′ .
  • the control pole of the sixth transistor M6 is connected to the input signal terminal I, the first pole is connected to the first pull-down node PD1, and the second pole is connected to the third voltage signal terminal V3.
  • the control pole of the eighth transistor M6' is connected to the pull-up node PU, the first pole is connected to the first pull-down node PD1, and the second pole is connected to the third voltage signal terminal V3.
  • the first access unit can transmit the third voltage signal provided by the third voltage signal terminal V3 to the first pull-down node PD1 under the control of the input signal terminal I.
  • the potential of the first pull-down node PD1 can be set at a low level, which helps to more accurately ensure that the noise reduction sub-circuit 104, the output
  • the sub-circuit 103 and the transistor connected to the third voltage signal terminal V3 in the sub-circuit 103 and the cascaded sub-circuit are not conducted, so as to ensure the normal operation of the circuit and improve the accuracy of the output signal.
  • the pull-down node control sub-circuit 102 further includes a fourth transistor M5', the control electrode and the first electrode of the fourth transistor M5' are connected to the second power supply voltage signal terminal V2, and the fourth transistor M5' The diode is connected to the second pull-down node PD2.
  • the pull-down node control subcircuit 102 further includes a second access unit, the second access unit specifically includes a sixteenth transistor M16, and in some embodiments, the second access unit further includes a seventeenth transistor M16'.
  • the control electrode of the sixteenth transistor M16 is connected to the pull-up node PU, the first electrode is connected to the second pull-down node PD2, and the second electrode is connected to the third voltage signal terminal V3.
  • the control pole of the seventeenth transistor M16' is connected to the input signal terminal I, the first pole is connected to the second pull-down node PD2, and the second pole is connected to the third voltage signal terminal V3.
  • the first power supply voltage signal terminal V1 when the first power supply voltage signal terminal V1 provides a high level, the second power supply voltage signal terminal V2 provides a low level, and when the first power supply voltage signal terminal V1 provides a low level, the second power supply voltage signal terminal V2 provides a high level. Every certain cycle, the first power supply voltage signal terminal V1 and the second power supply voltage signal terminal V2 perform level conversion, so as to realize the level control of the first pull-down node PD1 and the second pull-down node PD2.
  • the output sub-circuit 103 includes a third transistor M3 and an eleventh transistor M11.
  • the output sub-circuit 103 is connected to the pull-up node PU, the clock signal terminal CK, the first pull-down node PD1, the third voltage signal terminal V3 and the first output signal terminal O1.
  • the control pole of the third transistor M3 is connected to the pull-up node PU, the first pole is connected to the clock signal terminal CK, and the second pole is connected to the first output signal terminal O1.
  • the control pole of the eleventh transistor M11 is connected to the first pull-down node PD1, the first pole is connected to the first output signal terminal O1, and the second pole is connected to the third voltage signal terminal V3.
  • the output sub-circuit 103 may further include a fourteenth transistor M11', the control pole of the fourteenth transistor M11' is connected to the second pull-down node PD2, the first pole is connected to the first output signal terminal O1, and the second pole is connected to the third voltage The signal terminal V3 is connected.
  • the output sub-circuit 103 is used to transmit the clock signal provided by the clock signal terminal CK to the first output signal terminal O1 under the control of the pull-up node PU, and under the control of the first pull-down node PD1 or the second pull-down node PD2 , transmitting the third voltage signal provided by the third voltage signal terminal V3 to the first output signal terminal O1 to output the driving signal.
  • the noise reduction sub-circuit 104 includes a tenth transistor M10, and the noise reduction sub-circuit 104 is connected to the pull-up node PU, the third voltage signal terminal V3, and the first pull-down node PD1.
  • the control electrode of the tenth transistor M10 is connected to the first pull-down node PD1, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the third voltage signal terminal V3.
  • the noise reduction sub-circuit 104 further includes a ninth transistor M10', the control pole of the ninth transistor M10' is connected to the second pull-down node PD2, the first pole is connected to the pull-up node PU, and the second pole is connected to the second pull-down node PD2.
  • the three-voltage signal terminal V3 is connected.
  • the noise reduction sub-circuit 104 is used to transmit the third voltage signal provided by the third voltage signal terminal V3 to the pull-up node PU under the control of the first pull-down node PD1.
  • the first reset sub-circuit 105 includes a second transistor M2, and the first reset sub-circuit 105 is connected to the pull-up node PU, the first reset signal terminal Rs, and the third voltage signal terminal V3.
  • the control pole of the second transistor M2 is connected to the first reset signal terminal Rs, the first pole is connected to the pull-up node PU, and the second pole is connected to the third voltage signal terminal V3.
  • the first reset sub-circuit 105 is configured to transmit the third voltage signal provided by the third voltage signal terminal V3V3 to the pull-down node under the control of the reset signal provided by the first reset signal terminal Rs.
  • the driving circuit may further include a cascaded subcircuit.
  • the cascaded subcircuit includes a thirteenth transistor M13 and a twelfth transistor M12 .
  • the cascade sub-circuit is connected to the pull-up node PU, the clock signal terminal CK, the first pull-down node PD1, the third voltage signal terminal V3 and the second output signal terminal O2.
  • control pole of the thirteenth transistor M13 is connected to the pull-up node PU, the first pole is connected to the clock signal terminal CK, and the second pole is connected to the second output signal terminal O2.
  • the control pole of the twelfth transistor M12 is connected to the first pull-down node PD1, the first pole is connected to the second output signal terminal O2, and the second pole is connected to the third voltage signal terminal V3.
  • the cascade sub-circuit further includes a fifteenth transistor M12', the control electrode of the fifteenth transistor M12' is connected to the second pull-down node PD2, the first electrode is connected to the second output signal terminal O2, and the second The pole is connected to the third voltage signal terminal V3.
  • the cascade sub-circuit is used to transmit the clock signal provided by the clock signal terminal CK to the second output signal terminal O2 under the control of the pull-up node PU, and transmit the third voltage signal to the second output signal terminal O2 under the control of the first pull-down node PD1.
  • the third voltage signal provided by the terminal V3 is transmitted to the second output signal terminal O2 to output a carry control signal.
  • the second reset subcircuit is used to realize the global reset of the cascaded subcircuit
  • the second reset subcircuit includes a seventh transistor M7, the control electrode of the seventh transistor M7 is connected to the first Two reset control signal terminals STV are connected, the first pole is connected to the pull-up node PU, and the second pole is connected to the third voltage signal terminal V3.
  • the second reset subcircuit is used to transmit the third voltage signal provided by the third voltage signal terminal V3 to the pull-up node PU under the control of the second reset control signal provided by the second reset control signal terminal STV, so as to turn the pull-up node The potential of the PU is pulled low to reset.
  • control process of the second pull-down node PD2 is similar to that of the first pull-down node PD1. Therefore, in this embodiment, only the control process corresponding to the first pull-down node PD1 is used as an example for illustration.
  • the pull-down node driving subcircuit includes a fifth transistor M5, and the pull-down node driving subcircuit is connected to the first power supply voltage signal terminal V1, the second power supply voltage signal terminal V2, the pull-up node PU, and the first pull-down node PD1.
  • the pull-down node driving subcircuit is configured to transmit the first power voltage signal provided by the first voltage signal terminal V1 to the first pull-down node PD1 under the control of the first voltage signal terminal V1 and the pull-up node PU.
  • STV0 and STV1 correspond to the second reset control signal provided by the above-mentioned second reset control signal terminal STV, and CLK1 to CLK10 are provided by the above-mentioned clock signal terminal CK.
  • VDD1 is the first control voltage signal provided by the first voltage signal terminal V1
  • VDD2 is the second control voltage signal provided by the second voltage signal terminal V2
  • VGL and LVGL are voltage signals with a constant level
  • S-out In order to correspond to the above-mentioned first output signal G_out1, the t1 period corresponds to the Nth frame image, the t3 period corresponds to the N+1th frame image, the t2 period corresponds to the blank interval between the Nth frame image and the N+1th frame image, and the t4 period corresponds to Close the display panel.
  • the fifth transistor M5 is turned on for a long time, so that the first pull-down node PD1 is in a high level state for a long time, so that the sixth transistor M6 and the sixteenth transistor M16 are subjected to long-term High voltage pressure, specifically, the source of the sixth transistor M6 is connected to the low level of LVGL, the drain is connected to the first pull-down node PD1, and the gate is connected to the pulse signal of the pull-up node PU. In this way, the sixth transistor M6 is easy to invalidated.
  • the sixth transistor M6 fails, the potential of the first pull-down node PD1 cannot be pulled down, the potential of the pull-up node PU, the first output signal G_out and the second output signal G_out2 cannot be set high, and thus cannot be output normally.
  • FIG. 3 is a simulation result of the sixth transistor M6, wherein the abscissa is time (microseconds), the ordinate is voltage (volts), and Vgs represents the voltage difference between the gate and source of the sixth transistor M6, Vds represents the voltage difference between the source and the drain of the sixth transistor M6, wherein the gate is the control electrode of the sixth transistor M6, one of the source and the drain is the first pole of the sixth transistor M6, and the other is the first pole of the sixth transistor M6. The other is the second pole of the sixth transistor M6.
  • FIG. 4 is a relationship curve between the initial state and the failure state of the sixth transistor M6, wherein the curve 401 corresponds to the initial state, and the curve 402 corresponds to the failure state.
  • the abscissa Vg represents the threshold voltage (volts), the ordinate Id is the drain current (ampere), and the on-state current is the ordinate.
  • the sixth transistor M6 it is susceptible to the hot carrier effect, which is expressed as the threshold voltage There is no significant shift in Vth, but the on-state current Ion attenuates significantly, and the output capability is reduced.
  • the upper images of the three states on the right correspond to section A-A', and the images below the three states on the right correspond to section B-B'.
  • n-type IGZO (indium gallium zinc oxide) semiconductors the lower the temperature, the closer the Fermi level is to the conduction band; the hot carrier-induced interface state near the conduction band has a greater impact on the device characteristics; so it shows , transistors are more prone to failure at low temperatures.
  • the valence band is higher, and the Fermi level is closer to the conduction band. The carrier effect fails.
  • the voltage received by the sixth transistor M6 has the following characteristics: when Vgs is at a high level, Vds is at a low level, at this time, electrons accumulate at the interface between the gate insulating layer and the IGZO at the source terminal S and the drain terminal D; Normally, Vds is at a high level. At this time, at the source terminal S and the drain terminal D, electrons are discharged from the interface to IGZO, and at the same time gather toward the drain terminal S under the electric field between the source and drain; electrons obtain high voltage from the electric field energy, generating hot carriers. Therefore, defects are generated at the interface of the semiconductor and the gate insulating layer, and degradation is caused.
  • the connection relationship between the fifth transistor M5 and the sixth transistor M6 is simulated, and the corresponding first power supply voltage signal terminal V1, the voltage change of the pull-up node PU, and the voltage of -15V are provided. Constant voltage LVGL.
  • the high and low levels of the first power supply voltage signal terminal V1 in the original signal are 32V and -15V respectively, and the high and low levels of the pull-up node PU Levels are 40V and -15V respectively.
  • the measured high and low levels of the first pull-down node PD1 are 22V and -10V respectively.
  • Table 1 Effects of the first power supply voltage signal and the pull-up node voltage on the sixth transistor M6
  • the sixth transistor M6 when the first power supply voltage signal is greater than 27V, the sixth transistor M6 attenuates significantly, and its Ion attenuates by about 40%, It shows that the hot carrier injection effect is significant at this time.
  • the first power supply voltage signal drops below 27V, the Ion attenuation of the sixth transistor M6 is significantly improved, and the Ion attenuation is about 15%, and the attenuation is slightly improved when the first power supply voltage signal terminal V1 continues to decrease.
  • An embodiment of the present disclosure provides a voltage supply unit, which is applied to a display panel and used to provide a control voltage signal for a driving circuit.
  • the voltage supply unit includes a step-down circuit 701 and a first level conversion circuit 702 .
  • the step-down circuit 701 is used for receiving the first voltage signal VGH, and performing a step-down operation on the first voltage signal VGH to obtain a second voltage signal VGH'.
  • the first level conversion circuit 702 is connected with the step-down circuit 701 for receiving the input control voltage VDD, the third voltage signal VGL and the second voltage signal VGH', and according to the input control voltage VDD, the third voltage signal VGL and the second
  • the voltage signal VGH' generates the control voltage signals VDDO, VDDE such that the voltage values of the control voltage signals VDDO, VDDE are smaller than a predetermined voltage value.
  • control voltage signals VDDO and VDDE respectively correspond to the first power voltage signal provided by the first power voltage signal terminal V1 and the second power voltage signal provided by the second power voltage signal terminal V2 in the embodiment shown in FIG. 1B .
  • the predetermined voltage value is less than or equal to 27V, and further, the predetermined voltage value ranges from 15V to 26V. According to the above experimental results, it can be known that controlling the predetermined voltage value to be less than or equal to 27V can reduce possible adverse effects on transistors, for example, the sixth transistor M6 mentioned above.
  • the first level conversion circuit 702 can select a potential shifter (Level shifter), and the first level conversion circuit 702 provides the waveform of the input control voltage VDD signal and the third voltage signal VGL and the second voltage signal VGH according to the timing controller 705 'The level is high or low, and the control voltage signals VDDO and VDDE are generated.
  • the timing controller may be a logic board TCON.
  • the step-down circuit 701 in this embodiment can choose an existing or improved step-down circuit 701 as long as it can meet the step-down requirement.
  • the step-down circuit 701 includes a switch unit, a storage unit and a freewheeling unit.
  • the first end of the switch unit is connected to the input node 801 of the step-down circuit 701
  • the second end of the switch unit is connected to the first node N1
  • the switch unit is configured to input the step-down circuit 701
  • the signal is transmitted to the storage unit.
  • the storage unit is respectively connected to the first node N1, the second node N2 and the output node 802 of the step-down circuit 701, and the storage unit is configured to store and transmit the signal from the switch unit to the output node 802 when the switch unit is turned on, The stored signal from the switching unit is transmitted to the output node 802 when the switching unit is turned off.
  • the freewheeling unit is connected to the first node N1 and the second node N2, and the freewheeling unit is configured to convert the signal stored in the storage unit into a current when the switch unit is turned off, so as to maintain the continuity of the current.
  • the switch unit includes: a control switch tube T, the control switch tube T has a control terminal, a first terminal and a second terminal, the control terminal of the control switch tube T is connected to the control signal terminal Ctrl to obtain a control signal, the control The first end of the switch is connected to the input node 801, and the second end of the control switch is connected to the first node N1.
  • the storage unit includes: a first inductor L, one end of the first inductor L is connected to the first node N1, and the other end is connected to the output node 802; a first capacitor C1, one end of the first capacitor C1 is connected to the second node N2, and the other end is connected to the output node 802.
  • the freewheeling unit includes: a first diode VD, the anode of the first diode VD is connected to the second node N2, and the cathode of the first diode VD is connected to the first node N1; the second node N2 is grounded.
  • the step-down circuit of this embodiment can adjust the third voltage signal VGL with a higher level to the second voltage signal VGH' with a lower level to realize voltage regulation.
  • An embodiment of the present disclosure provides a voltage providing method, which is applied to any one of the voltage providing units described above.
  • the voltage providing method includes:
  • the step-down circuit receives the first voltage signal VGH, and performs a step-down operation on the first voltage signal VGH to obtain a second voltage signal VGH';
  • the first level conversion circuit receives the input control voltage VDD, the third voltage signal VGL and the second voltage signal VGH', and generates the control voltage signals VDDO, VGH' according to the input control voltage VDD, the third voltage signal VGL and the second voltage signal VGH' VDDE, so that the voltage values VDDO and VDDE of the control voltage signal are smaller than a predetermined voltage value.
  • the first level conversion circuit generates the control voltage signals VDDO and VDDE according to the waveform of the input control voltage signal VDD provided by the timing controller and the levels of the third voltage signal VGL and the second voltage signal VGH'.
  • control voltage signal is a square wave voltage signal
  • the high voltage value of the control voltage signals VDDO, VDDE is the voltage value of the second voltage signal VGH', and the low voltage value of the control voltage signals VDDO, VDDE is the voltage value of the third voltage signal VGL;
  • the high voltage value of the control voltage signal VDDO, VDDE is smaller than the predetermined voltage value.
  • both the first voltage signal VGH and the third voltage signal VGL are constant voltage signals, and correspondingly, the second voltage signal VGH' obtained by stepping down the first voltage signal VGH is also a constant voltage signal.
  • the adjustment process it is inconvenient to maintain the period and duty cycle of the input control voltage signal VDD, and adjust the high level of the input control voltage signal VDD based on the second voltage signal VGH', and adjust the level of the input control voltage signal VDD based on the third voltage signal VGL. Low level, get control voltage signals VDDO, VDDE.
  • the predetermined voltage value is less than or equal to 27V, and further, the predetermined voltage value ranges from 15V to 26V. Controlling the predetermined voltage value to be less than or equal to 27V can reduce possible adverse effects on the transistor.
  • control voltage signals VDDO, VDDE have the same period and duty cycle as the input control voltage VDD.
  • the high level of the input control voltage VDD can be reduced to obtain the control voltage signals VDDO and VDDE, avoiding the possible adverse effects of the high level on the transistor, and helping to improve the reliability of the display panel.
  • Exemplary It may be the above-mentioned sixth transistor M6.
  • An embodiment of the present disclosure provides a display driving module, as shown in FIG. 7 , including a driving circuit 704, a timing controller 705, a power management integrated circuit 703, and any voltage supply unit in the above-mentioned embodiments.
  • the timing controller 705 is used to provide the input control voltage VDD
  • the power management integrated circuit 703 can be a PMIC (Power Management IC)
  • the power management integrated circuit 703 is used to provide the first voltage signal VGH
  • the voltage supply unit is used to control the voltage signal VDDO, VDDE to drive circuit 704 .
  • the display driving module further includes a second level conversion circuit 406.
  • the second level conversion circuit 706 When applied to the driving circuit 704 shown in FIG. 1B, the second level conversion circuit 706 is used to receive the first timing control signals CLK1-CLK10 , the first driving control signal STVN, the third voltage signal VGL and the first voltage signal VGH, and then adjust the first timing control signals CLK1 ⁇ CLK10 and the first driving Control the level of the signal STVN to obtain the second timing control signals CLK1' ⁇ CLK10' and the second driving control signal STVN', and output them to the driving circuit 704.
  • the second level shifting circuit 706 is also used to provide A common voltage VSS is provided.
  • the first driving control signal STVN refers to the above-mentioned second reset control signal, for example, it may be STV0 and STV1 shown in FIG. signal of.
  • the driving circuit 704 includes a pull-down node control circuit, which is respectively connected to the control voltage terminal and the pull-down node, and used to transmit the control voltage signals VDDO and VDDE from the control voltage terminal to the pull-down node.
  • the control voltage signals VDDO and VDDE are relatively low, the influence of high voltages on the transistors connected to the pull-down nodes can be avoided.
  • it can be the first The six transistors M6 help to reduce the possibility of transistor failure, thereby helping to improve the reliability of the display panel.
  • An embodiment of the present disclosure provides a display device, including any one of the above display driving modules.
  • the display device of the embodiment of the present disclosure includes all the technical solutions of the above-mentioned display driver module embodiment, so at least all the above-mentioned technical effects can be achieved, and details are not repeated here.

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Abstract

本公开提供一种电压提供单元、电压提供方法、显示驱动模组和显示装置。电压提供单元，应用于显示面板，用于为驱动电路提供控制电压信号，电压提供单元包括降压电路和第一电平转换电路；降压电路用于接收第一电压信号，并对第一电压信号进行降压操作，得到第二电压信号；第一电平转换电路与降压电路连接，用于接收输入控制电压、第三电压信号和第二电压信号，并根据输入控制电压、第三电压信号和第二电压信号生成控制电压信号，以使得控制电压信号的电压值小于预定电压值。本公开实施例能够实现对于控制电压信号的电平控制，能够降低控制电压信号的电平过高对显示面板的性能造成影响，有助于提高显示面板的可靠性。

Description

一种指纹识别基板、电子设备和指纹识别方法 技术领域
本公开实施例涉及显示技术领域，尤其涉及一种电压提供单元、电压提供方法、显示驱动模组和显示装置。
背景技术
大尺寸显示面板由于具有更大的显示面积，受到人们的欢迎，同时，氧化物薄膜晶体管(Oxide TFT)由于具有高迁移率等技术优势，也逐渐应用到各种显示面板中。
发明内容
第一方面，本公开实施例提供了一种电压提供单元，应用于显示面板，用于为驱动电路提供控制电压信号，所述电压提供单元包括降压电路和第一电平转换电路；
所述降压电路用于接收第一电压信号，并对所述第一电压信号进行降压操作，得到第二电压信号；
所述第一电平转换电路与所述降压电路连接，用于接收输入控制电压、第三电压信号和所述第二电压信号，并根据所述输入控制电压、所述第三电压信号和所述第二电压信号生成控制电压信号，以使得所述控制电压信号的电压值小于预定电压值。
在一些实施例中，所述降压电路包括开关单元、存储单元和续流单元；
所述开关单元的第一端与所述降压电路的输入节点连接，所述开关单元的第二端与第一节点连接，所述开关单元配置为在开启时，将输入所述降压电路的信号传输至所述存储单元；
所述存储单元分别与第一节点、第二节点和所述降压电路的输出节点连接，所述存储单元配置为，在所述开关单元导通时，将来自所述开关单元的信号存储并传输至所述输出节点，在所述开关单元断开时，将存储的来自所述开关单元的信号传输至所述输出节点；
所述续流单元与所述第一节点和所述第二节点连接，所述续流单元被配置为，在所述开关单元断开的情况下，将所述存储单元存储的信号转化为电流。
在一些实施例中，所述开关单元包括：
控制开关管，所述控制开关管具有控制端、第一端和第二端，所述控制开关管的控制端与控制信号端连接以获取控制信号，所述控制开关的第一端与所述输入节点连接，所述控制开关的第二端与所述第一节点连接；
所述存储单元包括：
第一电感，所述第一电感的一端连接所述第一节点，另一端连接所述输出节点；
第一电容，所述第一电容的一端连接所述第二节点，另一端连接所述输出节点；
所述续流单元包括：
第一二极管，所述第一二极管的正极连接第二节点，所述第一二极管的负极连接所述第一节点；
所述第二节点接地。
在一些实施例中，所述预定电压值小于或等于27伏。
在一些实施例中，所述预定电压值的范围为15至26伏。
第二方面，本公开实施例提供了一种电压提供方法，应用于如第一方面中任一项所述的电压提供单元，所述电压提供方法包括：
所述降压电路接收第一电压信号，并对所述第一电压信号进行降压操作，得到第二电压信号；
第一电平转换电路接收输入控制电压、第三电压信号和所述第二电压信号，并根据所述输入控制电压、所述第三电压信号和所述第二电压信号生成控制电压信号，以使得所述控制电压信号的电压值小于预定电压值。
在一些实施例中，所述控制电压信号为方波电压信号；
所述控制电压信号的高电压值为所述第二电压信号的电压值，所述控制电压信号的低电压值为所述第三电压信号的电压值；
所述控制电压信号的高电压值小于所述预定电压值。
第三方面，本公开实施例提供了一种显示驱动模组，包括驱动电路、时序控制器、电源管理集成电路和第一方面中任一项所述的电压提供单元；
所述时序控制器用于提供所述输入控制电压；
所述电源管理集成电路用于提供所述第一电压信号；
所述电压提供单元用于提供控制电压信号至所述驱动电路。
在一些实施例中，所述显示驱动模组还包括第二电平转换电路，所述第二电平转换电路与所述时序控制器、所述电源管理集成电路和所述驱动电路连接，所述用于第二电平转换电路用于接收第一时序控制信号、第一驱动控制信号、所述第一电压信号和所述第三电压信号，然后生成第二时序信号、公共信号和第二驱动控制信号，并传输至所述驱动电路。
在一些实施例中，所述驱动电路包括：
输入子电路，与输入信号端、上拉节点连接，所述输入子电路用于在输入信号端的控制下，将所述输入信号端提供的输入信号传输至所述上拉节点；
下拉节点控制子电路，与所述输入信号端、第一电源电压信号端、所述上拉节点、第一下拉节点连接，所述下拉节点控制电路用于在所述第一电源电压信号端和所述上拉节点的控制下，将所述第一电源电压信号端提供的电源电压信号传输至所述第一下拉节点；
输出子电路，与所述上拉节点、时钟信号端、所述第一下拉节点、第三电压信号端和第一输出信号端连接，所述输出子电路用于在所述上拉节点的控制下，将所述时钟信号端提供的时钟信号传输至所述第一输出信号端，以及在所述第一下拉节点的控制下，将所述第三电压信号端提供的第三电压信号传输至所述第一输出信号端；
降噪子电路，与所述上拉节点、所述第三电压信号端、所述第一下拉节点连接，所述降噪子电路用于在所述第一下拉节点的控制下，将所述第三电压信号端提供的第三电压信号传输至所述上拉节点；
第一复位子电路，与所述上拉节点、第一复位信号端、所述第三电压信号端连接，所述第一复位子电路用于在所述第一复位信号端提供的复位信号的控制下，将所述第三电压信号端提供的第三电压信号传输至所述第一下拉节点。
第四方面，本公开实施例提供了一种显示装置，包括第三方面中任一项所述的显示驱动模组。
本公开实施例的电压提供单元，应用于显示面板，用于为驱动电路提供控制电压信号，所述电压提供单元包括降压电路和第一电平转换电路；所述降压电路用于接收第一电压信号，并对所述第一电压信号进行降压操作，得到第二电压信号；所述第一电平转换电路与所述降压电路连接，用于接收输入控制电压、第三电压信号和所述第二电压信号，并根据所述输入控制电压、所述第三电压信号和所述第二电压信号生成控制电压信号，以使得所述控制电压信号的电压值小于预定电压值。本公开实施例通过设置降压电路和第一电平转换电路，能够实现对于控制电压信号的电平控制，能够降低控制电压信号的电平过高对显示面板的性能造成影响，有助于提高显示面板的可靠性。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1A是本公开一实施例中驱动电路的电路图；
图1B是本公开一实施例中驱动电路的又一电路图；
图2是图1B所示驱动电路的驱动时序图；
图3是本公开一实施例中对于晶体管的仿真模拟示意图；
图4是本公开一实施例中晶体管的初始状态和失效状态的关系曲线；
图5是本公开一实施例中热载流子注入失效机理示意图；
图6是本公开一实施例中测试电路的电路图；
图7是本公开一实施例中提供的显示驱动模组的结构示意图；
图8是本公开一实施例中降压电路的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行 清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
使用氧化物薄膜晶体管(Oxide TFT)的液晶显示面板(LCD)技术由于迁移率高的优势，正在逐步取代使用a-Si TFT(非晶硅薄膜晶体管)的LCD。但是，Oxide TFT相比现有的a-Si TFT，稳定性和良率有一定差距。
本公开的发明人在实现本申请的技术方案的过程中发现，大尺寸、高分辨率、高刷新率的显示面板对于驱动电压要求较高。许多大尺寸显示面板均采用Gate driver On Array(GOA，阵列基板驱动电路，当其位于显示面板的行方向上时，又称作阵列基板行驱动)的驱动方式，以实现窄边框显示，同时也有助于降低成本。本公开实施例中以驱动电路为GOA做示例性说明。
为减小大尺寸及高分辨率带来的信号衰减和延迟，相关技术中通常通过提高驱动电压实现，例如某一显示面板的GOA高电平在30V以上，低电平在-10V以下。
当显示面板的要求较高时，例如尺寸较大、刷新频率较高或分辨率加高时，其驱动电压会进一步提高。例如，以110寸8K 120Hz(8000分辨率，120Hz刷新频率)的Oxide TFT显示面板为例，为降低RC Delay(电容电阻延迟)，GOA驱动电压通常为高压VGH约32V，低压LVGL约-15V。
在本公开至少一实施例中，显示装置中的驱动电路可以包括多级驱动子电路，驱动电路可以用于为位于有效显示区域内的像素电路提供驱动信号，驱动信号例如可以为栅极驱动信号或发光控制信号，但不以此为限。
在本公开的至少一实施例中，提供了一种驱动电路。
如图1A所示，该驱动电路包括：输入子电路101、下拉节点控制子电路102、输出子电路103、降噪子电路104和第一复位子电路105。
进一步的，如图1A和图1B所示，在一些实施例中，输入子电路101包括第一晶体管M1，输入子电路与输入信号端I、上拉节点PU连接，具体的，第一晶体管M1的控制极和第一极与输入信号端I连接，第二极与上拉节点PU连接，输入子电路101用于在输入信号端I的控制下，将输入信号端I提供的输入信号传输至上拉节点PU。
下拉节点控制子电路102包括第五晶体管M5，下拉节点控制子电路102与第一电源电压信号端V1、上拉节点PU、第一下拉节点PD1连接。
第五晶体管M5的控制极和第一极与第一电源电压信号端V1连接，第五晶体管M5的第二极与第一下拉节点PD1连接。
下拉节点控制电路102用于在第一电源电压信号端V1和上拉节点PU的控制下，将第一电源电压信号端V1提供的电源电压信号传输至第一下拉节点PD1。
在一些实施例中，下拉节点控制子电路102还包括第一接入单元，第一接入单元具体包括第六晶体管M6，在一些实施例中，第一接入单元还包括第八晶体管M6’。
第六晶体管M6的控制极与输入信号端I连接，第一极与第一下拉节点PD1连接，第二极与第三电压信号端V3连接。
第八晶体管M6’的控制极与上拉节点PU连接，第一极与第一下拉节点PD1连接，第二极与第三电压信号端V3连接。
该第一接入单元能够在输入信号端I的控制下通过将第三电压信号端V3提供的第三电压信号传输至第一下拉节点PD1。这样，在输入信号端I提供的输入信号为高电平的情况下，可以将第一下拉节点PD1的电位置位为低电平，有助于更准确地保证降噪子电路104、输出子电路103和级联子电路中与第三电压信号端V3连接的晶体管不导通，进而保证电路正常工作，提高输出信号准确性。
在一些实施例中，下拉节点控制子电路102还包括第四晶体管M5’，晶体管第四晶体管M5’的控制极和第一极与第二电源电压信号端V2连接，第四晶体管M5’的第二极与第二下拉节点PD2连接。
在一些实施例中，下拉节点控制子电路102还包括第二接入单元，第二接入单元具体包括第十六晶体管M16，在一些实施例中，第二接入单元还包括第十七晶体管M16’。
第十六晶体管M16的控制极与上拉节点PU连接，第一极与第二下拉节点PD2连接，第二极与第三电压信号端V3连接。
第十七晶体管M16’的控制极与输入信号端I连接，第一极与第二下拉 节点PD2连接，第二极与第三电压信号端V3连接。
如图2所示，当第一电源电压信号端V1提供高电平时，第二电源电压信号端V2提供低电平，当第一电源电压信号端V1提供低电平时，第二电源电压信号端V2提供高电平。每隔一定周期，第一电源电压信号端V1和第二电源电压信号端V2进行电平转换，从而实现对第一下拉节点PD1和第二下拉节点PD2的电平控制。
输出子电路103包括第三晶体管M3和第十一晶体管M11。输出子电路103与上拉节点PU、时钟信号端CK、第一下拉节点PD1、第三电压信号端V3和第一输出信号端O1连接。
第三晶体管M3的控制极与上拉节点PU连接，第一极与时钟信号端CK连接，第二极与第一输出信号端O1连接。
第十一晶体管M11的控制极与第一下拉节点PD1连接，第一极与第一输出信号端O1连接，第二极与第三电压信号端V3连接。
输出子电路103还可以包括第十四晶体管M11’，第十四晶体管M11’的控制极与第二下拉节点PD2连接，第一极与第一输出信号端O1连接，第二极与第三电压信号端V3连接。
输出子电路103用于在上拉节点PU的控制下，将时钟信号端CK提供的时钟信号传输至第一输出信号端O1，以及在第一下拉节点PD1或第二下拉节点PD2的控制下，将第三电压信号端V3提供的第三电压信号传输至第一输出信号端O1，以输出驱动信号。
降噪子电路104包括第十晶体管M10，降噪子电路104与上拉节点PU、第三电压信号端V3、第一下拉节点PD1连接。
第十晶体管M10的控制极与第一下拉节点PD1连接，第一极与上拉节点PU连接，第二极与第三电压信号端V3连接。
在一些实施例中，降噪子电路104还包括第九晶体管M10’，第九晶体管M10’的控制极与第二下拉节点PD2连接，第一极与上拉节点PU连接，第二极与第三电压信号端V3连接。
降噪子电路104用于在第一下拉节点PD1的控制下，将第三电压信号端V3提供的第三电压信号传输至上拉节点PU。
第一复位子电路105包括第二晶体管M2，第一复位子电路105与上拉节点PU、第一复位信号端Rs、第三电压信号端V3连接。
第二晶体管M2的控制极与第一复位信号端Rs连接，第一极与上拉节点PU连接，第二极与第三电压信号端V3连接。
第一复位子电路105用于在第一复位信号端Rs提供的复位信号的控制下，将第三电压信号端V3V3提供的第三电压信号传输至下拉节点。
在本公开的一些实施例中，驱动电路还可以包括级联子电路，如图1B所示，级联子电路包括第十三晶体管M13、第十二晶体管M12。
级联子电路与上拉节点PU、时钟信号端CK、第一下拉节点PD1、第三电压信号端V3和第二输出信号端O2连接。
具体的，第十三晶体管M13的控制极与上拉节点PU连接，第一极与时钟信号端CK连接，第二极与第二输出信号端O2连接。
第十二晶体管M12的控制极与第一下拉节点PD1连接，第一极与第二输出信号端O2连接，第二极与第三电压信号端V3连接。
在一些实施例中，级联子电路还包括第十五晶体管M12’，第十五晶体管M12’的控制极与第二下拉节点PD2连接，第一极与第二输出信号端O2连接，第二极与第三电压信号端V3连接。
级联子电路用于在上拉节点PU的控制下，将时钟信号端CK提供的时钟信号传输至第二输出信号端O2，以及在第一下拉节点PD1的控制下，将第三电压信号端V3提供的第三电压信号传输至第二输出信号端O2，以输出进位控制信号。
在一些实施例中，还包括第二复位子电路，第二复位子电路用于实现级联子电路的全局复位，第二复位子电路包括第七晶体管M7，第七晶体管M7的控制极与第二复位控制信号端STV连接，第一极与上拉节点PU连接，第二极与第三电压信号端V3连接。
第二复位子电路用于在第二复位控制信号端STV提供的第二复位控制信号的控制下，将第三电压信号端V3提供的第三电压信号传输至上拉节点PU，以将上拉节点PU的电位拉低而进行复位。
当输入信号由输入信号端I进入时，上拉节点PU的电位拉高，通过第六 晶体管M6拉低第一下拉节点PD1的电位，当上拉节点PU的电位被第二晶体管M2的复位信号拉低时，第一下拉节点PD1的电位重新恢复高电位，通过分别通过第十晶体管M10进行上拉节点PU的降噪，通过第十一晶体管M11进行第一输出信号G_out1的降噪，通过第十二晶体管M12进行第二输出信号G_out2的降噪。
本实施例中，第二下拉节点PD2的控制过程与第一下拉节点PD1类似，因此，本实施例中仅以包括第一下拉节点PD1对应的控制过程做示例性说明。
下拉节点驱动子电路包括第五晶体管M5，下拉节点驱动子电路与第一电源电压信号端V1、第二电源电压信号端V2、上拉节点PU、第一下拉节点PD1连接。
下拉节点驱动子电路被配置为在第一电压信号端V1和上拉节点PU的控制下，将第一电压信号端V1提供的第一电源电压信号传输至第一下拉节点PD1。
请进一步结合图2所示的显示基板的驱动时序图，图2中，STV0和STV1对应上述第二复位控制信号端STV提供的第二复位控制信号，CLK1至CLK10为上述时钟信号端CK提供的时钟信号，VDD1为第一电压信号端V1提供的第一控制电压信号，VDD2为第二电压信号端V2提供的第二控制电压信号，VGL和LVGL为具有恒定电平的电压信号，S-out为对应上述第一输出信号G_out1，t1时段对应第N帧图像，t3时段对应第N+1帧图像，t2时段对应第N帧图像和第N+1帧图像之间的空白区间，t4时段对应关闭显示面板。
结合图1B和图2可知，第五晶体管M5长时间开启，这样，会使第一下拉节点PD1长时间处于高电平状态，这样，第六晶体管M6和第十六晶体管M16受到长时间的高电压压力，具体的，第六晶体管M6的源极连接LVGL低电平，漏极连接第一下拉节点PD1，栅极则是连接上拉节点PU的脉冲信号，这样，第六晶体管M6容易失效。当第六晶体管M6失效时，会导致第一下拉节点PD1的电位无法拉低，上拉节点PU的电位、第一输出信号G_out和第二输出信号G_out2无法置高，从而无法正常输出。
图3为对于第六晶体管M6的仿真模拟结果，其中，横坐标为时间(微 秒)，纵坐标为电压(伏特)，Vgs代表第六晶体管M6的栅极和源极之间的电压差，Vds代表第六晶体管M6源极和漏极之间的电压差，其中，栅极为第六晶体管M6的控制极，源极和漏极中的一者为第六晶体管M6的第一极，另一者为第六晶体管M6的第二极。图4为第六晶体管M6的初始状态和失效状态的关系曲线，其中，曲线401对应初始状态，曲线402对应失效状态。横坐标Vg代表阈值电压(伏特)，纵坐标Id为漏极电流(安培)，开态电流为纵坐标为对于第六晶体管M6来说，易受到热载流子效应的影响，表现为阈值电压Vth无显著偏移，但是开态电流Ion衰减显著，输出能力降低。
如图5所示，其中，右侧三个状态的上方图像对应截面A-A’处，右侧三个状态的下方的图像对应截面B-B’处。由于库伦散射加剧缘故，低温下热载流子注入造成的损伤更严重。对于n型IGZO(铟镓锌氧化物)半导体而言，温度越低，费米能级越靠近导带；靠近导带的热载流子诱导界面态对器件特性的影响更大；所以表现出，低温下晶体管更易失效。对于高迁移率氧化物薄膜晶体管来说，相比传统的IGZO薄膜晶体管，其价带更高，费米能级更靠近导带，因此，其热载流子注入效应更显著，器件更易由于热载流子效应失效。
综上可知，第六晶体管M6受到的电压具有以下特点：Vgs高电平时，Vds低电平，此时源极端S和漏极端D处，电子在栅极绝缘层与IGZO界面累积；Vgs低电平时，Vds高电平，此时，源极端S和漏极端D处，电子从界面被排出到IGZO，同时在源极和漏极之间电场下往漏极端S聚集；电子从电场中获得高能量，产生热载流子。因此，在半导体与栅极绝缘层的界面上会产生缺陷，并引起退化。
如图6所示，本公开实施例中，模拟了第五晶体管M5和第六晶体管M6的连接关系，并提供相应的第一电源电压信号端V1、上拉节点PU的电压变化、-15V的恒定电压LVGL。
调整上拉节点PU的电压和第一电源电压信号端V1，如表1所示，原始信号中第一电源电压信号端V1的高低电平分别为32V和-15V，上拉节点PU的高低电平分别为40V和-15V，此时，实测第一下拉节点PD1的高低电平分别为22V和-10V。
请继续参阅表1中实验2，当改变第一电源电压信号端V1的高电平为20V时，发现第一电源电压信号端V1的高电平降低后，第六晶体管M6的特性变化较小。
请参阅表1中实验3，当上拉节点PU的高电平变化后，由40变化为28V时，第六晶体管M6依旧发生特性劣化，由此可证明降低第一电源电压信号端V1的高电平可减小对第六晶体管M6的损伤。
表1：第一电源电压信号和上拉节点电压对第六晶体管M6的影响
Figure PCTCN2021120187-appb-000001
为得到第一电源电压信号端V1提供的第一电源电压信号的电压范围，本公开实施例中进一步设置不同第一电源电压信号的电压进行测试。
示例性的，如表2所示，针对某款禁带宽度2.9e的高迁移率Oxide TFT而言，第一电源电压信号大于27V时，第六晶体管M6衰减显著，其Ion衰减约40％，说明此时，热载流子注入效应显著。第一电源电压信号降低至27V以下，第六晶体管M6的Ion衰减显著改善，Ion衰减约15％，继续降低第一电源电压信号端V1，衰减轻微改善。
表2：不同第一电源电压信号对于第六晶体管M6的影响
Figure PCTCN2021120187-appb-000002
Figure PCTCN2021120187-appb-000003
经过研究发现，第一电源电压信号降低至26V以下时，漏极端D与栅极端电场强度降低，热载流子效应不明显。
基于上述研究结果认为，为了使GOA输出的高压差和延迟小，VGH和LVGL/VGL电压需保持较高的压差，并提出技术方案如下。
本公开实施例提供了一种电压提供单元，应用于显示面板，用于为驱动电路提供控制电压信号。
如图7所示，在其中一些实施例中，电压提供单元包括降压电路701和第一电平转换电路702。
降压电路701用于接收第一电压信号VGH，并对第一电压信号VGH进行降压操作，得到第二电压信号VGH’。
第一电平转换电路702与降压电路701连接，用于接收输入控制电压VDD、第三电压信号VGL和第二电压信号VGH’，并根据输入控制电压VDD、第三电压信号VGL和第二电压信号VGH’生成控制电压信号VDDO、VDDE，以使得控制电压信号VDDO、VDDE的电压值小于预定电压值。
这里，控制电压信号VDDO、VDDE分别对应图1B所示实施例中的第一电源电压信号端V1提供的第一电源电压信号和第二电源电压信号端V2提供的第二电源电压信号。
在一些实施例中，预定电压值小于或等于27V，进一步的，预定电压值的范围为15V至26V。根据上述实验结果可知，将预定电压值控制在小于或等于27V，能够降低对于晶体管，可能造成的不利影响，示例性的，可以是上述第六晶体管M6。
第一电平转换电路702可以选择电位转移器(Level shifter)，第一电平转换电路702根据时序控制器705提供的输入控制电压VDD信号的波形以及第三电压信号VGL和第二电压信号VGH’的电平高低，生成控制电压信号VDDO、VDDE。这里，时序控制器可以是逻辑板TCON。
本实施例中的降压电路701可以选择现有的或改进的降压电路701，只要能够满足降压需求即可。
在一些实施例中，降压电路701包括开关单元、存储单元和续流单元。
如图8所示，开关单元的第一端与降压电路701的输入节点801连接，开关单元的第二端与第一节点N1连接，开关单元配置为在开启时，将输入降压电路701的信号传输至存储单元。
存储单元分别与第一节点N1、第二节点N2和降压电路701的输出节点802连接，存储单元配置为，在开关单元导通时，将来自开关单元的信号存储并传输至输出节点802，在开关单元断开时，将存储的来自开关单元的信号传输至输出节点802。
续流单元与第一节点N1和第二节点N2连接，续流单元被配置为，在开关单元断开的情况下，将存储单元存储的信号转化为电流，从而保持电流的连续性。
在一些实施例中，开关单元包括：控制开关管T，控制开关管T具有控制端、第一端和第二端，控制开关管T的控制端与控制信号端Ctrl连接以获取控制信号，控制开关的第一端与输入节点801连接，控制开关的第二端与第一节点N1连接。
存储单元包括：第一电感L，第一电感L的一端连接第一节点N1，另一端连接输出节点802；第一电容C1，第一电容C1的一端连接第二节点N2，另一端连接输出节点802；续流单元包括：第一二极管VD，第一二极管VD的正极连接第二节点N2，第一二极管VD的负极连接第一节点N1；第二节 点N2接地。
本实施例的降压电路能够将电平较高的第三电压信号VGL调整为电平较低的第二电压信号VGH’，实现电压调节。
本公开实施例提供了一种电压提供方法，应用于以上任一项所述的电压提供单元。
在一个实施例中，该电压提供方法包括：
所述降压电路接收第一电压信号VGH，并对第一电压信号VGH进行降压操作，得到第二电压信号VGH’；
第一电平转换电路接收输入控制电压VDD、第三电压信号VGL和第二电压信号VGH’，并根据输入控制电压VDD、第三电压信号VGL和第二电压信号VGH’生成控制电压信号VDDO、VDDE，以使得控制电压信号的电压值VDDO、VDDE小于预定电压值。
本实施例中，第一电平转换电路根据时序控制器提供的输入控制电压信号VDD的波形以及第三电压信号VGL和第二电压信号VGH’的电平高低，生成控制电压信号VDDO、VDDE。
在一些实施例中，所述控制电压信号为方波电压信号；
控制电压信号VDDO、VDDE的高电压值为第二电压信号VGH’的电压值，所述控制电压信号VDDO、VDDE的低电压值为第三电压信号VGL的电压值；
控制电压信号VDDO、VDDE的高电压值小于所述预定电压值。
在一些实施例中，第一电压信号VGH和第三电压信号VGL均为恒定的电压信号，相应的，第一电压信号VGH降压获得的第二电压信号VGH’也是恒定的电压信号。调整过程中，保持输入控制电压信号VDD的周期和占空比不便，并基于第二电压信号VGH’调整输入控制电压信号VDD的高电平，基于第三电压信号VGL调整输入控制电压信号VDD的低电平，获得控制电压信号VDDO、VDDE。
在一些实施例中，预定电压值小于或等于27V，进一步的，预定电压值的范围为15V至26V。将预定电压值控制在小于或等于27V，能够降低对于晶体管，可能造成的不利影响。
在其中一些实施例中，控制电压信号VDDO、VDDE与输入控制电压VDD具有相同的周期和占空比。
通过设置该降压电路，能够将降低输入控制电压VDD的高电平获得控制电压信号VDDO、VDDE，避免高电平对于晶体管可能造成的不利影响，有助于提高显示面板的可靠性，示例性的，可以是上述第六晶体管M6。
本公开实施例提供了一种显示驱动模组，如图7所示，包括驱动电路704、时序控制器705、电源管理集成电路703和上述实施例中任一项电压提供单元。其中，时序控制器705用于提供输入控制电压VDD，电源管理集成电路703可以是PMIC(Power Management IC)，电源管理集成电路703用于提供第一电压信号VGH，电压提供单元用于控制电压信号VDDO、VDDE至驱动电路704。
在一些实施例中，显示驱动模组还包括第二电平转换电路406，当应用于图1B所示驱动电路704时，第二电平转换电路706用于接收第一时序控制信号CLK1～CLK10、第一驱动控制信号STVN、第三电压信号VGL和第一电压信号VGH，然后根据第一电压信号VGH和第三电压信号VGL的电平高低调节第一时序控制信号CLK1～CLK10和第一驱动控制信号STVN的电平，获得第二时序控制信号CLK1’～CLK10’、第二驱动控制信号STVN’，并输出至驱动电路704，同时，第二电平转换电路706还用于向驱动电路704提供公共电压VSS。
这里，第一驱动控制信号STVN指的是上述第二复位控制信号，示例性的，可以是图2中所示STV0及STV1，第三电压信号VGL和第一电压信号VGH对应上述具有固定电平的信号。
在一些实施例中，驱动电路704包括下拉节点控制电路，下拉节点控制电路分别与控制电压端和下拉节点连接，用于将来自控制电压端的控制电压信号VDDO、VDDE传输至下拉节点。
本实施例中，由于控制电压信号VDDO、VDDE的高电压相对较低，能够避免高电压对于与下拉节点连接的晶体管造成的影响，示例性的，可以是图1B所示驱动电路704中的第六晶体管M6，有助于降低晶体管失效的可能性，从而有助于提高显示面板的可靠性。
本公开实施例提供了一种显示装置，包括以上任一项的显示驱动模组。
本公开实施例的显示装置包括上述显示驱动模组实施例的全部技术方案，因此至少能够实现上述全部技术效果，此处不再赘述。
以上所述是本公开实施例的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (11)

  1. 一种电压提供单元，应用于显示面板，用于为驱动电路提供控制电压信号，所述电压提供单元包括降压电路和第一电平转换电路；
    所述降压电路用于接收第一电压信号，并对所述第一电压信号进行降压操作，得到第二电压信号；
    所述第一电平转换电路与所述降压电路连接，用于接收输入控制电压、第三电压信号和所述第二电压信号，并根据所述输入控制电压、所述第三电压信号和所述第二电压信号生成控制电压信号，以使得所述控制电压信号的电压值小于预定电压值。
  2. 如权利要求1所述的电压提供单元，其中，所述降压电路包括开关单元、存储单元和续流单元；
    所述开关单元的第一端与所述降压电路的输入节点连接，所述开关单元的第二端与第一节点连接，所述开关单元配置为在开启时，将输入所述降压电路的信号传输至所述存储单元；
    所述存储单元分别与第一节点、第二节点和所述降压电路的输出节点连接，所述存储单元配置为，在所述开关单元导通时，将来自所述开关单元的信号存储并传输至所述输出节点，在所述开关单元断开时，将存储的来自所述开关单元的信号传输至所述输出节点；
    所述续流单元与所述第一节点和所述第二节点连接，所述续流单元被配置为，在所述开关单元断开的情况下，将所述存储单元存储的信号转化为电流。
  3. 根据权利要求2所述的电压提供单元，其中，所述开关单元包括：
    控制开关管，所述控制开关管具有控制端、第一端和第二端，所述控制开关管的控制端与控制信号端连接以获取控制信号，所述控制开关的第一端与所述输入节点连接，所述控制开关的第二端与所述第一节点连接；
    所述存储单元包括：
    第一电感，所述第一电感的一端连接所述第一节点，另一端连接所述输出节点；
    第一电容，所述第一电容的一端连接所述第二节点，另一端连接所述输出节点；
    所述续流单元包括：
    第一二极管，所述第一二极管的正极连接第二节点，所述第一二极管的负极连接所述第一节点；
    所述第二节点接地。
  4. 根据权利要求1至3中任一项所述的电压提供单元，其中，所述预定电压值小于或等于27伏。
  5. 根据权利要求4所述的电压提供单元，其中，所述预定电压值的范围为15至26伏。
  6. 一种电压提供方法，应用于如权利要求1至5中任一项所述的电压提供单元，所述电压提供方法包括：
    所述降压电路接收第一电压信号，并对所述第一电压信号进行降压操作，得到第二电压信号；
    第一电平转换电路接收输入控制电压、第三电压信号和所述第二电压信号，并根据所述输入控制电压、所述第三电压信号和所述第二电压信号生成控制电压信号，以使得所述控制电压信号的电压值小于预定电压值。
  7. 如权利要求6所述的电压提供方法，其中，所述控制电压信号为方波电压信号；
    所述控制电压信号的高电压值为所述第二电压信号的电压值，所述控制电压信号的低电压值为所述第三电压信号的电压值；
    所述控制电压信号的高电压值小于所述预定电压值。
  8. 一种显示驱动模组，包括驱动电路、时序控制器、电源管理集成电路和如权利要求1至5中任一项所述的电压提供单元；
    所述时序控制器用于提供所述输入控制电压；
    所述电源管理集成电路用于提供所述第一电压信号；
    所述电压提供单元用于提供控制电压信号至所述驱动电路。
  9. 根据权利要求8所述的显示驱动模组，其中，所述显示驱动模组还包括第二电平转换电路，所述第二电平转换电路与所述时序控制器、所述电源 管理集成电路和所述驱动电路连接，所述用于第二电平转换电路用于接收第一时序控制信号、第一驱动控制信号、所述第一电压信号和所述第三电压信号，然后生成第二时序信号、公共信号和第二驱动控制信号，并传输至所述驱动电路。
  10. 如权利要求8所述的显示驱动模组，其中，所述驱动电路包括：
    输入子电路，与输入信号端、上拉节点连接，所述输入子电路用于在输入信号端的控制下，将所述输入信号端提供的输入信号传输至所述上拉节点；
    下拉节点控制子电路，与所述输入信号端、第一电源电压信号端、所述上拉节点、第一下拉节点连接，所述下拉节点控制电路用于在所述第一电源电压信号端和所述上拉节点的控制下，将所述第一电源电压信号端提供的电源电压信号传输至所述第一下拉节点；
    输出子电路，与所述上拉节点、时钟信号端、所述第一下拉节点、第三电压信号端和第一输出信号端连接，所述输出子电路用于在所述上拉节点的控制下，将所述时钟信号端提供的时钟信号传输至所述第一输出信号端，以及在所述第一下拉节点的控制下，将所述第三电压信号端提供的第三电压信号传输至所述第一输出信号端；
    降噪子电路，与所述上拉节点、所述第三电压信号端、所述第一下拉节点连接，所述降噪子电路用于在所述第一下拉节点的控制下，将所述第三电压信号端提供的第三电压信号传输至所述上拉节点；
    第一复位子电路，与所述上拉节点、第一复位信号端、所述第三电压信号端连接，所述第一复位子电路用于在所述第一复位信号端提供的复位信号的控制下，将所述第三电压信号端提供的第三电压信号传输至所述第一下拉节点。
  11. 一种显示装置，包括权利要求8或9所述的显示驱动模组。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105375762A (zh) * 2015-12-15 2016-03-02 深圳市华星光电技术有限公司 一种升降压变换电路、电源管理模块及液晶驱动装置
CN109410822A (zh) * 2018-10-16 2019-03-01 友达光电股份有限公司 电压电平转换电路及显示面板驱动控制方法
CN111429845A (zh) * 2020-04-30 2020-07-17 京东方科技集团股份有限公司 电源管理集成电路及驱动方法、电路板、显示装置
CN111508449A (zh) * 2020-05-29 2020-08-07 京东方科技集团股份有限公司 电压供给电路、显示驱动电路、显示装置和显示驱动方法
US20210020119A1 (en) * 2018-11-12 2021-01-21 HKC Corporation Limited Display device driving method, and display device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9059076B2 (en) * 2013-04-01 2015-06-16 Transphorm Inc. Gate drivers for circuits based on semiconductor devices
CN104682699B (zh) * 2015-03-20 2018-07-06 深圳市华星光电技术有限公司 一种升降压变换电路、电源管理模块及液晶驱动装置
CN109166600B (zh) * 2018-10-26 2021-01-15 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
US11837164B2 (en) * 2019-09-17 2023-12-05 Hefei Xinsheng Optoelectronics Technology Co., Ltd. Drive control circuit and related driving method thereof, and display panel

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105375762A (zh) * 2015-12-15 2016-03-02 深圳市华星光电技术有限公司 一种升降压变换电路、电源管理模块及液晶驱动装置
CN109410822A (zh) * 2018-10-16 2019-03-01 友达光电股份有限公司 电压电平转换电路及显示面板驱动控制方法
US20210020119A1 (en) * 2018-11-12 2021-01-21 HKC Corporation Limited Display device driving method, and display device
CN111429845A (zh) * 2020-04-30 2020-07-17 京东方科技集团股份有限公司 电源管理集成电路及驱动方法、电路板、显示装置
CN111508449A (zh) * 2020-05-29 2020-08-07 京东方科技集团股份有限公司 电压供给电路、显示驱动电路、显示装置和显示驱动方法

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