WO2023042617A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023042617A1
WO2023042617A1 PCT/JP2022/031873 JP2022031873W WO2023042617A1 WO 2023042617 A1 WO2023042617 A1 WO 2023042617A1 JP 2022031873 W JP2022031873 W JP 2022031873W WO 2023042617 A1 WO2023042617 A1 WO 2023042617A1
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Prior art keywords
electrode
semiconductor layer
layer
source
gate
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Ceased
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PCT/JP2022/031873
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English (en)
French (fr)
Japanese (ja)
Inventor
学 柳原
浩隆 大嶽
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to CN202280061275.9A priority Critical patent/CN117916889A/zh
Priority to JP2023548380A priority patent/JPWO2023042617A1/ja
Publication of WO2023042617A1 publication Critical patent/WO2023042617A1/ja
Priority to US18/592,594 priority patent/US20240258389A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/021—Manufacture or treatment of air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20—Air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Definitions

  • HEMTs high electron mobility transistors
  • GaN gallium nitride
  • 2DEG two-dimensional electron gas
  • Power devices using HEMTs are recognized as devices capable of low on-resistance and high-speed/high-frequency operation compared to typical silicon (Si) power devices.
  • Patent Document 1 discloses providing a guard ring forming region that shields static electricity around an element region in order to increase resistance to static electricity.
  • a 2DEG is formed in the carrier transport layer heterojunction with the barrier layer, and an electrode (shielding layer) in ohmic contact with the 2DEG is provided on the barrier layer in the guard ring forming region. ing.
  • the shielding layer and the 2DEG existing directly under the shielding layer play a role of shielding static electricity.
  • each gate electrode 28 includes a first gate electrode portion 281 and a second gate electrode portion 282 extending in the second direction (Y direction) and parallel to each other, and It includes a first connecting portion 283 and a second connecting portion 284 extending parallel to each other.
  • the first gate electrode portion 281 and the second gate electrode portion 282 are connected to each other by the first connection portion 283 and the second connection portion 284, thereby forming each gate electrode 28 in a ring shape.
  • the semiconductor device 10 employs a POA structure.
  • the POA structure since the source pad 42, the drain pad 44, and the gate pad 46 are provided in the active region, the area of the non-active region (that is, the peripheral portion R11) occupying the element region R1 is reduced, thereby reducing the chip area. can do.
  • the distance between the scribe line SL (or the boundary B1 between the element region R1 and the element isolation region R2) and the active region is narrow, so that the guard ring of the semiconductor device 10 has higher surge resistance. required for structure.
  • the electron transit layer 16 is a GaN layer
  • the electron supply layer 18 is an AlGaN layer.
  • the 2DEG 20 is formed in the AlGaN layer (electron transit layer 16) near the interface between the GaN layer (electron transit layer 16) and the AlGaN layer (electron supply layer 18) which are heterojunctioned to each other.
  • the guard ring 30 By applying the guard ring 30 to such a configuration, it is possible to provide the semiconductor device 10 (HEMT) that suppresses the penetration of surges into the 2DEG 20 of the element region R1 and improves surge resistance.
  • the first shield electrode 50 is arranged over both the shield portion 32 and the electron supply layer 18 . Therefore, the wiring structure of the guard ring 30 including the wiring electrode 48 and the guard ring connection electrode 48E arranged in the first embodiment can be omitted. In addition, since the wiring structure of the guard ring 30 is not required, the width of the shielding portion 32 of the guard ring 30 (shielding widths W3 and W4 in FIG. 1) can be reduced to reduce the chip area as long as the required surge resistance can be obtained. can be reduced.
  • the guard ring 30A is arranged near the boundary B1 in the outer peripheral portion R11 of the element region R1.
  • the guard ring 30A includes a shielding portion 32A arranged on the electron supply layer 18 and a first shielding electrode 34A arranged on the shielding portion 32A. 48A.
  • the shielding portion 32A of the guard ring 30A, the first shielding electrode 34A, and the guard ring connection electrode 48EA are configured similarly to the shielding portion 32 of the guard ring 30, the first shielding electrode 34, and the guard ring connection electrode 48E.
  • the wiring electrodes 48A of the third embodiment are formed with a wider width than the wiring electrodes 48 of the first embodiment.
  • the semiconductor device 10 is not limited to a HEMT using GaN, and may be configured as a HEMT using other Group III-V semiconductors.
  • Only the electron supply layer 18 may be removed in the element isolation region R2. That is, the main surface (upper surface) of the electron transit layer 16 may be flush with or substantially flush with the element region R1 and the element isolation region R2. If the electron supply layer 18 is removed in the element isolation region R2, the 2DEG 20 will not occur in the electron transit layer 16 in the element isolation region R2, so that the same advantages as in the above embodiment can be obtained.
  • the element isolation region (R2) includes the substrate (12) and the first semiconductor layer (16); The semiconductor device (10) according to Appendix A1 or A2, wherein the second semiconductor layer (18) is removed in the isolation region (R2).

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  • Junction Field-Effect Transistors (AREA)
PCT/JP2022/031873 2021-09-14 2022-08-24 半導体装置 Ceased WO2023042617A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202280061275.9A CN117916889A (zh) 2021-09-14 2022-08-24 半导体装置
JP2023548380A JPWO2023042617A1 (https=) 2021-09-14 2022-08-24
US18/592,594 US20240258389A1 (en) 2021-09-14 2024-03-01 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021149205 2021-09-14
JP2021-149205 2021-09-14

Related Child Applications (1)

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US18/592,594 Continuation US20240258389A1 (en) 2021-09-14 2024-03-01 Semiconductor device

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WO2023042617A1 true WO2023042617A1 (ja) 2023-03-23

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US (1) US20240258389A1 (https=)
JP (1) JPWO2023042617A1 (https=)
CN (1) CN117916889A (https=)
WO (1) WO2023042617A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118136664A (zh) * 2024-05-07 2024-06-04 英诺赛科(苏州)半导体有限公司 一种半导体结构及其制备方法、半导体产品

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN121284999A (zh) * 2025-06-26 2026-01-06 厦门市三安集成电路有限公司 一种半导体芯片及应用

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010080633A (ja) * 2008-09-25 2010-04-08 Furukawa Electric Co Ltd:The 半導体装置、ウエハ構造体および半導体装置の製造方法
JP2010103158A (ja) * 2008-10-21 2010-05-06 Panasonic Corp 双方向スイッチ
JP2011124385A (ja) * 2009-12-10 2011-06-23 Sanken Electric Co Ltd 化合物半導体装置及びその製造方法
WO2012043334A1 (ja) * 2010-10-01 2012-04-05 シャープ株式会社 窒化物半導体装置
JP2013201262A (ja) * 2012-03-23 2013-10-03 Toshiba Corp 窒化物半導体装置
WO2016098390A1 (ja) * 2014-12-15 2016-06-23 シャープ株式会社 電界効果トランジスタ
WO2016157718A1 (ja) * 2015-04-02 2016-10-06 パナソニック株式会社 窒化物半導体装置
JP2017152655A (ja) * 2016-02-26 2017-08-31 株式会社豊田中央研究所 半導体装置
JP2021516454A (ja) * 2018-02-27 2021-07-01 シリコニックス インコーポレイテッドＳｉｌｉｃｏｎｉｘ Ｉｎｃｏｒｐｏｒａｔｅｄ フィールドプレート設計を最適化した電力用半導体デバイス
WO2021153266A1 (ja) * 2020-01-28 2021-08-05 ローム株式会社 窒化物半導体装置

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010080633A (ja) * 2008-09-25 2010-04-08 Furukawa Electric Co Ltd:The 半導体装置、ウエハ構造体および半導体装置の製造方法
JP2010103158A (ja) * 2008-10-21 2010-05-06 Panasonic Corp 双方向スイッチ
JP2011124385A (ja) * 2009-12-10 2011-06-23 Sanken Electric Co Ltd 化合物半導体装置及びその製造方法
WO2012043334A1 (ja) * 2010-10-01 2012-04-05 シャープ株式会社 窒化物半導体装置
JP2013201262A (ja) * 2012-03-23 2013-10-03 Toshiba Corp 窒化物半導体装置
WO2016098390A1 (ja) * 2014-12-15 2016-06-23 シャープ株式会社 電界効果トランジスタ
WO2016157718A1 (ja) * 2015-04-02 2016-10-06 パナソニック株式会社 窒化物半導体装置
JP2017152655A (ja) * 2016-02-26 2017-08-31 株式会社豊田中央研究所 半導体装置
JP2021516454A (ja) * 2018-02-27 2021-07-01 シリコニックス インコーポレイテッドＳｉｌｉｃｏｎｉｘ Ｉｎｃｏｒｐｏｒａｔｅｄ フィールドプレート設計を最適化した電力用半導体デバイス
WO2021153266A1 (ja) * 2020-01-28 2021-08-05 ローム株式会社 窒化物半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118136664A (zh) * 2024-05-07 2024-06-04 英诺赛科(苏州)半导体有限公司 一种半导体结构及其制备方法、半导体产品

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CN117916889A (zh) 2024-04-19

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