WO2023040253A1 - 一种测试板卡、测试系统和测试方法 - Google Patents

一种测试板卡、测试系统和测试方法 Download PDF

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Publication number
WO2023040253A1
WO2023040253A1 PCT/CN2022/087047 CN2022087047W WO2023040253A1 WO 2023040253 A1 WO2023040253 A1 WO 2023040253A1 CN 2022087047 W CN2022087047 W CN 2022087047W WO 2023040253 A1 WO2023040253 A1 WO 2023040253A1
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test
signal
memory
tested
instruction
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PCT/CN2022/087047
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English (en)
French (fr)
Inventor
钱进
马茂松
石宏龙
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长鑫存储技术有限公司
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Publication of WO2023040253A1 publication Critical patent/WO2023040253A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Definitions

  • the present disclosure relates to but not limited to a test board, a test system and a test method.
  • Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) is a semiconductor storage device commonly used in computers. Before the DRAM leaves the factory, it is necessary to perform a signal integrity test (Signal integrity, SI) on the DRAM.
  • SI Signal integrity
  • the DRAM chip is welded on the DRAM chip package of the system motherboard through a special interposer (generally referred to as SI Interposer), and then the probe head of the high-speed oscilloscope is welded on the test point of the special interposer, thereby Take the SI test.
  • an embodiment of the present disclosure provides a test board, the test board includes a registered clock driver RCD module and a memory to be tested, and the output end of the RCD module is connected to the input end of the memory to be tested;
  • the RCD module is used to determine the target test command; and after entering the offline mode, send the target test command to the memory to be tested;
  • the memory to be tested is used for receiving target test instructions and outputting test results according to the target test instructions.
  • the test board also includes a connection module; the connection module is connected to the test machine, used to receive the control command sent by the test machine, and send the control command to the RCD module, so that the RCD module goes offline model.
  • connection module is also used to receive the test instruction to be processed sent by the test machine, and send the test instruction to be processed to the RCD module; the RCD module is specifically used to receive the test instruction to be processed, and according to the pending test instruction The test order identifies the target test order.
  • connection module is also used to receive the first power signal provided by the test machine, and drive the RCD module and the memory to be tested through the first power signal; or the connection module is also used to receive the first power signal provided by the test machine.
  • the first power signal and the second power signal drive the RCD module through the first power signal, and drive the memory to be tested through the second power signal.
  • the test instruction to be processed includes a first address signal, a first control signal and a first system clock signal; the RCD module is specifically configured to receive the first address signal, the first control signal and the first system clock signal from the test machine a system clock signal, and determine the target test instruction according to the first address signal, the first control signal and the first system clock signal.
  • the test instruction to be processed includes a first address signal and a first control signal; the test board also includes a clock signal source; the clock signal source is used to generate the first system clock signal; the RCD module is specifically used for slave
  • the test machine receives the first address signal and the first control signal, receives the first system clock signal from the clock signal source, and determines the target test instruction according to the first address signal, the first control signal and the first system clock signal.
  • the target test instruction includes a second address signal, a second control signal and a second system clock signal
  • the test result includes a test data signal and a test data control signal
  • the test board also includes a first output interface and The second output interface, and both the first output interface and the second output interface are connected to the preset oscilloscope; wherein, the memory to be tested is specifically used to receive the second address signal, the second control signal and the second system clock signal, and according to The second address signal, the second control signal and the second system clock signal output the test data signal and the test data control signal; the first output interface is used to receive the test data signal and send the test data signal to the preset An oscilloscope is provided; the second output interface is used to receive the test data control signal and send the test data control signal to the preset oscilloscope.
  • the test board further includes a first output resistor and a second output resistor, and both the first output resistor and the second output resistor are connected to the ground terminal; wherein, the memory to be tested is also used to signal, the second control signal and the second system clock signal, output data signal and data control signal; the first output resistor is used to receive the data signal and transmit the data signal to the ground; the second output resistor is used to receive the data control signal signal, and transmits the data control signal to ground.
  • the voltage of the first power signal is 1.1 volts, and the voltage of the second power signal is 1.8 volts; the impedances of the first output resistor and the second output resistor are both 50 ohms.
  • the test machine includes a field programmable logic array FPGA, the FPGA is connected to the connection module through the I2C bus, and the connection module is connected to the RCD module through the I2C bus.
  • an embodiment of the present disclosure provides a test system, which includes at least a test machine and the test board as described in any one of the first aspect.
  • an embodiment of the present disclosure provides a test method, which is applied to a test system including a test machine and a test board, and the test board includes an RCD module and a memory to be tested; the method includes:
  • the target test command is determined through the test board; after the test machine controls the RCD module to enter the offline mode, based on the target test command, the signal integrity test is performed on the memory to be tested through the RCD module. Determine the test results.
  • the method further includes:
  • the module drives the memory to be tested through the second power signal.
  • the determining the target test instruction through the test board includes:
  • the method further includes:
  • the pending test instruction includes a first address signal, a first control signal, and a first system clock signal;
  • the determination of the target test instruction through the RCD module based on the test instruction to be processed includes:
  • the target test command is determined by the RCD module.
  • the test instruction to be processed includes a first address signal and a first control signal; the test board also includes a clock signal source;
  • the determination of the target test instruction through the RCD module based on the test instruction to be processed includes:
  • a first system clock signal is generated by a clock signal source; and a target test instruction is determined by an RCD module according to the first address signal, the first control signal and the first system clock signal.
  • the target test instruction includes a second address signal, a second control signal and a second system clock signal
  • the test result includes a test data signal and a test data control signal
  • the target-based test instruction performs a signal integrity test on the memory to be tested through the RCD module to determine the test result, including:
  • the second system clock signal, the second address signal and the second control signal, the test data signal and the test data control signal are output through the memory to be tested.
  • the test system also includes a preset oscilloscope
  • the test board also includes a first output interface and a second output interface; after determining the test result, the method also includes:
  • test data signal is sent to the preset oscilloscope through the first output interface; the test data control signal is sent to the preset oscilloscope through the second output interface.
  • the test board also includes a first output resistor and a second output resistor, and both the first output resistor and the second output resistor are connected to the ground; the method also includes:
  • the second address signal and the second control signal output the data signal and the data control signal through the memory to be tested; transmit the data signal to the ground through the first output resistance, and control the data through the second output resistance
  • the signal is transmitted to ground.
  • FIG. 1 is a schematic structural diagram of a test board provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another test board provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of the composition and structure of a test system provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic flow diagram of a testing method provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a working process of a test board provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a working process of another test board provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific ordering of objects. Understandably, “first ⁇ second ⁇ third 3" where permitted, the specific order or sequence may be interchanged such that the embodiments of the disclosure described herein can be practiced in sequences other than those illustrated or described herein.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • Double Data Rate SDRAM DDR: double rate SDRAM
  • DDR5 The technical specification of the fifth edition of DDR
  • DIMM Dual Inline Memory Module
  • RDIMM Registered dual in-line memory module
  • SI signal integrity test
  • SI Interposer an adapter board dedicated to signal integrity testing
  • CPU central processing unit
  • Field Programmable Gate Array field programmable logic gate array
  • Sub-Miniature-A, SMA a high-frequency data interface
  • I2C two-wire serial bus
  • VHost offline mode.
  • the dynamic random access memory is a semiconductor storage device commonly used in computers, and before the DRAM leaves the factory, an SI test needs to be performed on the DRAM.
  • the special adapter board in the SI test in order to perform SI test on the memory to be tested, it is first necessary to solder the special adapter board in the SI test to the DRAM chip package of the system motherboard.
  • the limitation of this test method is that the SI test of the DRAM chip cannot be performed separately from the system motherboard, because the DRAM controller in the CPU chip will perform out-of-order operations, and the test pattern (Pattern) is not easy to modify.
  • an embodiment of the present disclosure provides a test board, the test board includes a registered clock driver RCD module and a memory to be tested, and the output of the RCD module is connected to the input of the memory to be tested; wherein, the RCD module, It is used to determine the target test instruction; and after entering the offline mode, send the target test instruction to the memory to be tested; the memory to be tested is used to receive the target test instruction and output the test result according to the target test instruction.
  • the embodiment of the present disclosure provides a test board that supports offline mode. In the offline mode, the RCD module is used as a virtual controller to complete the signal integrity test of the memory to be tested, that is, the test board is allowed to leave the system. The main board tests the memory to be tested, and can conveniently modify test-related parameters to improve the flexibility and efficiency of the test.
  • FIG. 1 shows a schematic structural diagram of a test board 10 provided by an embodiment of the present disclosure.
  • this test board 10 comprises register clock driver RCD module 101 and memory 102 to be tested, and the output end of RCD module 101 is connected with the input end of memory 102 to be tested;
  • the RCD module 101 is used to determine the target test instruction; and after entering the offline mode, send the target test instruction to the memory to be tested 102;
  • the memory to be tested 102 is configured to receive a target test instruction and output a test result according to the target test instruction.
  • test board 10 provided by the embodiment of the present disclosure is applied to the testing process of various storage devices, and the storage devices may be DRAM, SRAM, SDRAM and so on.
  • the test board 10 is described in the subsequent description by taking the signal integrity test as an application scenario, but this does not constitute a relevant limitation.
  • the test board 10 may include an RCD module 101 and a memory to be tested 102 .
  • the RCD module 101 can determine the target test command, and send the target test command to the memory to be tested 102 in the offline mode (VHost mode), and then the memory to be tested 102 outputs relevant data signals, so that the staff can determine the test result.
  • the RCD module 101 can also be called an RCD chip, which can register relevant data commands (such as address signals, control signals and system clock signals), generate memory-oriented data commands, and redefine the sending time of data commands.
  • relevant data commands such as address signals, control signals and system clock signals
  • the RCD chip is originally used for data buffering.
  • the RCD module 101 is used to register the relevant test instruction (ie, the target test instruction), and then use the test instruction to perform the SI test on the memory 102 to be tested.
  • the RCD module 101 can control the memory 102 to be tested as a virtual host, thereby allowing the SI test to be carried out without the memory controller, improving the flexibility of the SI test; in addition, due to the existence of the RCD module 101, there is no need for
  • the test memory 102 configures the data bus and the command bus, which simplifies the test process and facilitates the modification of various parameters in the SI test.
  • the memory to be tested 102 refers to a memory connected to the main body of the test board 10 in a preset manner, that is, the memory to be tested 102 is replaceable.
  • the preset method can include multiple types, such as installing the memory in the preset slot of the test board 10 body, connecting the memory with the peripheral interface of the test board 10 body, welding the memory on the test board 10 The body is medium.
  • test board 10 can perform the corresponding test function, so the embodiment of the present disclosure temporarily considers that the memory to be tested 102 is a test board part of the card. But, from the angle of product processing, test board can not comprise the memory to be tested, but only be provided with the interface that can be connected to the memory to be tested (this interface can be the peripheral interface of various types), this does not contain the memory to be tested.
  • the memory test board is also within the protection scope of the embodiments of the present disclosure.
  • the test board needs to rely on the test machine to complete the SI test.
  • FIG. 2 it shows a schematic structural diagram of another test board 10 provided by an embodiment of the present disclosure. As shown in Figure 2, the test board 10 also includes a connection module 103;
  • connection module 103 is connected with the test machine 20, and is used for receiving the control command sent by the test machine 20, and sending the control command to the RCD module 101, so that the RCD module 101 enters the offline mode.
  • test board 10 needs to establish an electrical connection with the test machine 20 through the connection module 103 .
  • the staff can write various test programs in the test machine 20 according to the test requirements, so that the test machine 20 can send control instructions to the test board 10 to control the RCD module 101 to enter the offline mode.
  • test board 10 can also be connected with the test machine 20 in various ways, for example, the test board 10 is installed in the preset slot of the test machine 20 body, and the test board 10 is connected to the test machine. 20 The peripheral interface connection of the main body, etc.
  • connection module 103 can be embodied as various types of connection elements, such as slots, peripheral interfaces, solder joints and so on.
  • the test bench 20 includes memory controller related functions. Therefore, the connection module 103 is also used to receive the test instruction to be processed sent by the test machine 20, and send the test instruction to be processed to the RCD module 101;
  • the RCD module 101 is specifically configured to receive a test instruction to be processed, and determine a target test instruction according to the test instruction to be processed.
  • the test machine 20 before controlling the RCD module 101 to enter the VHost mode, the test machine 20 also needs to send a test command to be processed to the RCD module 101 through the connection module 103, and the RCD module 101 generates a test command for the memory to be tested according to the test command to be processed.
  • the test command includes at least an address signal (ADDR), a control signal (CTRL) and a system clock signal (CLK), and these signals may all be provided by the test machine 20 . Therefore, in a specific embodiment, the test instruction to be processed includes a first address signal (ADDR1), a first control signal (CTRL1) and a first system clock signal (CLK1);
  • the RCD module 101 is specifically used to receive the first address signal (ADDR1), the first control signal (CTRL1) and the first system clock signal (CLK1) from the testing machine 20, and according to the first address signal (ADDR1), the first A control signal (CTRL1) and a first system clock signal (CLK1) determine the target test command.
  • the RCD module 101 can determine the address signal in the target test command signal according to the first address signal (ADDR1), that is, the second address signal (ADDR2); determine the control signal in the target test command signal according to the first control signal (CTRL1) , that is, the second control signal (CTRL2); determine the system clock signal in the target test command signal, that is, the second system clock signal (CLK2) according to the first system clock signal (CLK1).
  • the test board 10 is provided with a clock signal source 104, and the clock signal source 104 is used to generate the first system clock signal (CLK1).
  • CLK1 first system clock signal
  • the test board 10 can generate the first system clock signal (CLK1) through the clock signal source 104, that is, the test machine 20 only needs to provide the first address signal (ADDR1) and the first control signal (CTRL1). That is, the test command to be processed includes a first address signal ( ADDR1 ) and a first control signal ( CTRL1 ).
  • the RCD module 101 is specifically used to receive the first address signal (ADDR1) and the first control signal (CTRL1) from the testing machine 20, and receive the first system clock signal (CLK1) from the clock signal source 104. ), and determine the target test command according to the first address signal (ADDR1), the first control signal (CTRL1) and the first system clock signal (CLK1).
  • the clock signal source 104 may be a connection point for introducing a clock signal generated by an external circuit, and then determining the clock signal generated by the external circuit as the first system clock signal (CLK1); or, the clock signal source 104 It may also be a clock circuit for directly generating a clock signal, that is, the first system clock signal CLK1.
  • the clock signal generated by the test board 10 through the clock signal source 104 is more accurate and has better synchronization, so that the result of the SI test is more accurate.
  • test machine needs to be configured in advance with two test signal output modes, that is, only output the first address signal and the first control signal, or output the first address signal, the first control signal and the system clock signal, so as to cope with different test environments .
  • test signal output modes that is, only output the first address signal and the first control signal, or output the first address signal, the first control signal and the system clock signal, so as to cope with different test environments .
  • some test machines may not support the state of the external clock signal source, and at this time, the test board needs to use the first clock signal provided by the test machine.
  • test results include a test data signal (LBDQ) and a test data control signal (LBDQS);
  • the memory to be tested 102 is specifically used for receiving the second address signal (ADDR2), the second control signal (CTRL2) and the second system clock signal (CLK2), and according to the second address signal (ADDR2), the second control signal (CTRL2) ) and the second system clock signal (CLK2), output test data signal (LBDQ) and test data control signal (LBDQS);
  • test board 10 may also include a first output interface and a second output interface, and both the first output interface and the second output interface are connected to a preset oscilloscope; wherein,
  • the first output interface is used to receive the test data signal (LBDQ), and send the test data signal (LBDQ) to a preset oscilloscope;
  • the second output interface is used to receive the test data control signal (LBDQS) and send the test data control signal (LBDQS) to the preset oscilloscope.
  • the RCD module 101 will send the target test instruction signal (ADDR2 signal, CTRL2 signal and CLK2 signal) to the memory to be tested 102, and the memory to be tested 102 performs specified data operations, Output test data signal (LBDQ) and test data control signal (LBDQS); Then, the test board 10 sends the test data signal (LBDQ) to the high-speed oscilloscope through the first output interface, and tests the test by the second output interface. Send to high-speed oscilloscope with data control signal (LBDQS).
  • the test board 10 also includes a first output resistor and a second output resistor, and both the first output resistor and the second output resistor are connected to the ground; wherein,
  • the memory to be tested 102 is also used to output a data signal (DQ) and a data control signal (DQS) according to the second address signal, the second control signal and the second system clock signal;
  • DQ data signal
  • DQS data control signal
  • the first output resistor is used to receive the data signal (DQ) and transmit the data signal (DQ) to the ground;
  • the second output resistor is used to receive the data control signal (DQS) and transmit the data control signal (DQS) to ground.
  • test data signal LBDQ
  • test data control signal LPDQS
  • DQ data control signal
  • the LBDQ/LBDQS signal is only drawn out in the test environment to determine the test result, and will not be output backward when the memory is in a normal use environment; while the DQ The /DQS signal is just the opposite.
  • the DQ/DQS signal will be output backward when the memory is in normal use, and will be transmitted to the ground through the output resistor in the test environment.
  • DQ/DQS and LBDQ/LBDQS are only used to exemplarily indicate signals output by the memory to be tested, and are not associated with any signals with specific physical meanings in practice, and do not constitute limitations to the embodiments of the present disclosure.
  • the number of signals output by the memory to be tested may also be more or less, and this embodiment of the present disclosure is only an example.
  • the impedances of the first output resistor and the second output resistor are both 50 ohms, but this does not constitute a relevant limitation.
  • the test machine 20 also needs to provide power for the test board 10 . Therefore, the connection module 103 is also used to receive the first power signal provided by the testing machine 20, and drive the RCD module 101 and the memory to be tested 102 through the first power signal; or
  • connection module 103 is also used to receive the first power signal and the second power signal provided by the testing machine 20, drive the RCD module 101 through the first power signal, and drive the memory under test 102 through the second power signal.
  • the test machine 20 only needs to provide a power signal to the test board 10, and the RCD module can be driven simultaneously by using the power signal 101 and the memory to be tested 102. If the operating voltages of the RCD module 101 and the memory to be tested 102 differ greatly, then the test machine 20 needs to provide two power signals to the test board 10, and use the two power signals to drive the RCD module 101 and the memory to be tested 102 respectively.
  • the working voltage of the RCD module 101 is generally 1.1 volts, and according to DDR5 regulations, the working voltage of the DRAM may be 1.1 volts, or may be 1.8 volts. Therefore, the voltage of the first power signal may be 1.1 volts, and the voltage of the second power signal may be 1.8 volts.
  • test machine 20 can be implemented by a field programmable logic array FPGA, the FPGA is connected to the connection module 103 through the I2C bus, and the connection module 103 is connected to the RCD module 101 through the I2C bus.
  • FPGA is a circuit that can be modified by user programming after manufacture.
  • I2C bus is a two-wire serial bus, which is often used for the connection between microcontrollers and peripherals.
  • test machine 20 can be implemented by a field programmable logic array FPGA, the staff can easily modify the test logic of the test machine 20, flexibly modify the test mode and other test parameters, and at the same time be compatible with multiple rules.
  • the test memory 102 improves the flexibility and efficiency of SI testing.
  • I2C bus a communication connection can be conveniently established between the test machine 20 and the test board 10, reducing hardware costs.
  • An embodiment of the present disclosure provides a test board, the test board includes a register clock driver RCD module and a memory to be tested, and the output of the RCD module is connected to the input of the memory to be tested; wherein, the RCD module is used to determine a target test command; and after entering the offline mode, sending the target test command to the memory to be tested; the memory to be tested is used to receive the target test command and output the test result according to the target test command.
  • the embodiment of the present disclosure provides a test board that supports offline mode. In the offline mode, the RCD module is used as a virtual controller to complete the signal integrity test of the memory to be tested, that is, the test board is allowed to leave the system. The main board tests the memory to be tested, and can conveniently modify test-related parameters to improve the flexibility and efficiency of the test.
  • FIG. 3 shows a schematic structural diagram of a test system 30 provided by an embodiment of the present disclosure.
  • the test system 30 at least includes a test machine 20 and the aforementioned test board 10 .
  • the test board 10 includes an RCD module, and the RCD module can be used as a virtual controller in offline mode to perform a signal integrity test on the memory to be tested.
  • An embodiment of the present disclosure provides a test system, including a test board that supports offline mode.
  • the RCD module is used as a virtual controller to complete the signal integrity test of the memory to be tested, that is, the test board allows The memory to be tested can be tested separately from the main board of the system, and relevant parameters of the test can be easily modified to improve the flexibility and efficiency of the test.
  • FIG. 4 shows a schematic flowchart of a testing method provided by an embodiment of the present disclosure. As shown in Figure 4, the method may include:
  • test method in the embodiment of the present disclosure is applied to a test system including a test machine and a test board, and the test board includes an RCD module and a memory to be tested.
  • the RCD module can be used as a virtual host to control the memory to be tested, thereby allowing the SI test to be performed without the memory controller, improving the flexibility of the SI test; in addition, due to the existence of the RCD module, there is no need to configure the data bus for the memory to be tested And the command bus, which simplifies the test process and facilitates the modification of various parameters in the SI test.
  • test board can be connected to the test machine in various ways, such as slots, peripheral interfaces, etc.
  • test board After the test board is connected to the test machine, there is a communication connection between the test board and the test machine.
  • I2C bus can be used as an information channel between the test board and the test machine.
  • the method may further include:
  • the RCD module is fixedly installed in the test board and has a fixed working voltage.
  • the memory to be tested needs to be replaced, and different types of memory to be tested have different working voltages. Therefore, the working voltage of the memory to be tested and the working voltage of the RCD module may be the same or different.
  • the test board when the operating voltage of the memory to be tested is the same as that of the RCD module, after the test board is connected to the test machine, the test board will also obtain the first power signal from the test machine, and according to the A power signal drives the memory to be tested and the RCD module.
  • the test board needs to obtain two different power signals from the test machine, that is, the first power signal and the second power signal, and according to The first power signal drives the RCD module, and drives the memory to be tested according to the second power signal.
  • the working voltage of the RCD module is generally 1.1 volts.
  • the 5th generation DRAM allows two working voltages, namely 1.1 volts and 1.8 volts.
  • the test board only needs to obtain the first power signal (voltage is 1.1 volts) from the test machine to drive the RCD module and the memory to be tested at the same time;
  • the operating voltage of the memory to be tested is 1.8 volts, and the test board only needs to obtain the first power signal (1.1 volts) and the second power signal (1.8 volts) from the test machine to drive the RCD module and the standby Test memory.
  • the determination of the target test instruction through the test board may include:
  • the target test instructions are determined by the RCD module.
  • the test machine sends the test command to be processed to the test board, and the RCD module in the test board can process the test command to be processed into a memory-oriented
  • the target test command is registered and the target test command is sent to the memory to be tested at a specific moment.
  • the RCD module can redefine the timing of pending test instructions.
  • ADDR address signal
  • CRL control signal
  • CRL system clock signal
  • the test machine can provide the above three types of signals, that is, the test instruction to be processed can include the first address signal (ADDR1), the first control signal (CTRL1) and the first system clock signal ( CLK1).
  • the test instruction to be processed can include the first address signal (ADDR1), the first control signal (CTRL1) and the first system clock signal ( CLK1).
  • the determination of the target test instruction through the RCD module based on the test instruction to be processed may include:
  • the target test command is determined by the RCD module.
  • an independent clock signal source can be included in the test board, and the test machine can only provide address signals and control signals at this time, that is, the test instructions to be processed include the first address signal (ADDR1) and a first control signal (CTRL1);
  • determining the target test instruction by the RCD module may include:
  • the target test command is determined by the RCD module.
  • the RCD module receives the first address signal (ADDR1), the first control signal (CTRL1) and the first system clock signal (CLK1), and converts them into the second address signal (ADDR2) for the memory to be tested. ), the second control signal (CTRL2) and the second system clock signal (CLK2), and the target test instruction is obtained.
  • the RCD module determines the target test command including the second address signal (ADDR2), the second control signal (CTRL2) and the second system clock signal (CLK2).
  • test machine controls the RCD module to enter the offline mode, based on the target test instruction, perform a signal integrity test on the memory to be tested through the RCD module, and determine a test result.
  • the RCD module can register target test instructions, and after entering the offline mode, it can be used as a virtual controller to control the memory to be tested.
  • the method may further include:
  • the RCD module is controlled to enter the offline mode.
  • test machine After the test machine sends the pending test command to the test board, the test machine also sends a control command to the test board, and the control command is used to instruct the RCD module to enter the offline mode.
  • the SI test can be separated from the test machine at the control level (the test machine still needs to provide power at the physical level), thereby improving the flexibility of the SI test; in addition, the RCD module of the test board can be used as Virtual controller, so there is no need to configure the address and command bus, which can be very convenient for testing.
  • the target test command includes a second address signal (ADDR2), a second control signal (CTRL2) and a second system clock signal (CLK2).
  • ADDR2 a second address signal
  • CRL2 a second control signal
  • CLK2 a second system clock signal
  • the test result includes a test data signal (LBDQ) and a test data control signal (LBDQS). Therefore, the said target-based test instruction, through the RCD module to carry out the signal integrity test of the memory to be tested, to determine the test result, may include:
  • a test data signal ( LBDQ ) and a test data control signal ( LBDQS ) are output through the memory to be tested.
  • the test system also includes a preset oscilloscope
  • the test board also includes a first output interface and a second output interface; after determining the test result, the method may also include:
  • the memory to be tested outputs the test data signal (LBDQ) and the test control data signal (LBDQS) according to the target test command signal, and sends the test data signal (LBDQ) to the preset oscilloscope display through the first output interface. , sending the test control data signal (LBDQS) to a preset oscilloscope display through the second output interface.
  • the method may also include:
  • the second address signal (ADDR2) the second control signal (CTRL2) and the second system clock signal (CLK2), output the data signal (DQ) and the data control signal (DQS) through the memory to be tested;
  • test board also includes a first output resistor and a second output resistor, and both the first output resistor and the second output resistor are connected to the ground terminal; the data signal (DQ) is transmitted to the ground through the first output resistor, and The data control signal (DQS) is transmitted to ground through the second output resistor.
  • the memory to be tested actually outputs two pairs of signals DQ/DQS and LBDQ/LBDQS at the same time.
  • the essence of the DQ/DQS signal and the LBDQ/LBDQS signal are the same, and the LBDQ/LBDQS signal is only drawn out in the test environment for subsequent determination of the test results of the SI, and will not be output backwards when the memory is in a normal use environment ;
  • the DQ/DQS signal is just the opposite.
  • the DQ/DQS signal will be output backward when the memory is in a normal use environment, and it will be transmitted to the ground through the output resistor in the test environment.
  • the impedances of the first output resistor and the second output resistor are both 50 ohms, but this does not constitute a relevant limitation.
  • An embodiment of the present disclosure provides a test method, which is applied to a test system including a test machine and a test board, and the test board includes an RCD module and a memory to be tested; the method includes: on the test machine and After the test board is connected, the target test instruction is determined through the test board; after the test machine controls the RCD module to enter the offline mode, based on the target test instruction, the RCD module is used to process the target test instruction.
  • the test memory performs a signal integrity test to determine a test result.
  • the RCD module is used as a virtual controller to complete the signal integrity test of the memory to be tested, that is, the test board is allowed to be separated from the system motherboard.
  • the memory to be tested can be tested, and relevant parameters of the test can be modified conveniently, so as to improve the flexibility and efficiency of the test.
  • FIG. 5 shows a schematic diagram of a working process of a test board 10 provided by an embodiment of the present disclosure.
  • the test board and the test machine (not shown in FIG. 5 ) constitute a complete test system, and the test system is applied to the test verification of DDR5 RDIMM SI.
  • the test machine using FPGA design
  • DDR5 RCD chip or called DDR5 RCD chip
  • the memory to be tested or called DDR5 SDRAM, DDR5 particles, DDR5 storage particles
  • the test board is used for debugging and testing of DDR5 RDIMM.
  • the test board 10 is also called the DDR5 RDIMM reading test board, and includes an RCD chip (equivalent to an RCD module) and a memory to be tested.
  • the test board can be designed in two versions, X8 and X16, respectively matching the memory with an output data bit width of 8 bits and the memory to be tested with a data bit width of 16 bits.
  • the test board has a memory slot connector compatible with various types of memory (for example, the model is DDR4 288pin memory slot connector), and there is a socket (Socket) to facilitate the replacement of DDR5 storage particles.
  • the RCD chip is soldered on the test board.
  • the test board 10 also has a connection module (such as UDIMM Connector), which is used to connect with the test machine.
  • a connection module such as UDIMM Connector
  • the test machine includes a motherboard (or FPGA Board) built with FPGA circuits. That is to say, UDIMM Connector is used to connect to FPGA Board.
  • the RCD chip can register the test instructions and act as a virtual controller after entering the VHost mode.
  • the DQ/DQS signal is transmitted to the ground through a 50 ohm (ohm) resistance; the LBDQ/LBDQS signal is input to a high-speed oscilloscope through a pin for display, so that the staff can determine the test result.
  • the test board is respectively connected to a high-speed oscilloscope through two high-frequency connector interfaces (for example, SMA interface), and outputs LBDQ signal and LBDQS signal respectively.
  • test instructions are sent to the memory to be tested, and during the SI test, the test board draws the data input and output (Input/Output, IO) interface, and connect a 50-ohm resistor to the ground in series to transmit the DQ/DQS signal to the ground through a 50-ohm resistor for reading test; in addition, the test board will also lead out the LBDQ/LBDQS signal and send it to Display for a high-speed oscilloscope to complete the SI test.
  • IO Input/Output
  • the test board 10 also has the design of switching the FPGA internal clock and the external input clock of the test machine, which is convenient to use the external clock signal for testing, thereby improving the clock synchronization, and then improving the accuracy of the SI test results.
  • the test board 10 does not include an external clock generator (equivalent to the aforementioned clock signal source), and the CLK1 signal is provided by the FPGA internal clock of the test machine; referring to Figure 6, it shows an embodiment of the present disclosure A schematic diagram of the working process of another test board 10 is provided.
  • the test board 10 includes an external clock generator (equivalent to the aforementioned clock signal source), and the CLK1 signal is provided by an external input clock.
  • the test machine can make the RCD chip enter the VHost mode through the I2C bus, so that there is no need to configure the address and command bus, which is convenient for modifying test parameters and improving test flexibility.
  • the test machine can provide a Power signal (i.e. power supply 1), which drives the RCD chip and the memory to be tested at the same time; or the test machine can provide two Power signals (i.e. power supply 1 and power supply 1). 2), two Power signals respectively drive the RCD chip and the memory to be tested.
  • a Power signal i.e. power supply 1
  • two Power signals respectively drive the RCD chip and the memory to be tested.
  • VHost mode allows the DRAM test to be used without the memory controller. It only needs to send a series of instructions to the RCD chip through the I2C bus, and then the RCD chip can be used as a virtual host to control the DRAM chip and perform a series of tests.
  • the VHost mode has the following characteristics: it supports up to 4 test instructions; each instruction can be a 1-cycle or 2-cycle instruction; the number of interval clocks can be set between each instruction, for example, it can be 2, 4, 8, 16, 64, 256 and 1024 interval clocks; after the end of the last instruction, the loop can be restarted from any instruction.
  • the FPGA test machine controls the RCD chip to enter the VHost mode through the I2C bus, and then the RCD chip tests the DDR5 particles, and uses a high-speed oscilloscope to obtain DQS and DQ signals. Determine SI test results;
  • the embodiment of the present disclosure also provides a SI testing method for DDR5 RDIMM, which can be applied to DDR5 chip SI testing, and has at least the following advantages: On the one hand, it supports controlling the RCD chip to enter the VHost mode through the I2C bus; on the other hand On the one hand, use RCD to send commands to control DRAM to enter the test mode; on the other hand, modify the test pattern conveniently through RCD; on the other hand, it can run independently from the CPU of the system platform.
  • the embodiment of the present disclosure provides a test board, including an RCD module and a memory to be tested.
  • a test board including an RCD module and a memory to be tested.
  • the specific implementation method of the foregoing embodiment is described in detail. It can be seen that the embodiment of the present disclosure provides a Support the test method of offline mode, use the RCD module as a virtual controller in the offline mode, and then complete the signal integrity test of the memory to be tested, that is, the test board allows testing the memory to be tested without the system motherboard, and can be easily modified Test related parameters to improve the flexibility and efficiency of testing.
  • serial numbers of the above-mentioned embodiments of the present disclosure are for description only, and do not represent the advantages and disadvantages of the embodiments.
  • the methods disclosed in the several method embodiments provided in the present disclosure can be combined arbitrarily to obtain new method embodiments if there is no conflict.
  • the features disclosed in several product embodiments provided in the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments.
  • the features disclosed in several method or device embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.
  • Embodiments of the present disclosure provide a test board, a test system and a test method, the test board includes a registered clock driver RCD module and a memory to be tested, and the output of the RCD module is connected to the input of the memory to be tested; wherein, The RCD module is used to determine the target test instruction; and after entering the offline mode, sends the target test instruction to the storage to be tested; the storage to be tested is used to receive the target test instruction and output the test result according to the target test instruction.
  • the embodiment of the present disclosure provides a test board supporting an offline mode, which allows the memory to be tested to be tested without the main board of the system, can conveniently modify test-related parameters, and improves the flexibility and efficiency of the test.

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Abstract

本公开实施例提供了一种测试板卡、测试系统和测试方法，该测试板卡包括寄存时钟驱动器RCD模块和待测试存储器，且RCD模块的输出端与待测试存储器的输入端连接；其中，RCD模块，用于确定目标测试指令；以及在进入脱机模式后，向待测试存储器发送目标测试指令；待测试存储器，用于接收目标测试指令，并根据目标测试指令输出测试结果。这样，本公开实施例提供了一种支持脱机模式的测试板卡，允许脱离系统主板对待测试存储器进行测试，能够方便地修改测试相关参数，提高测试的灵活性和效率。

Description

一种测试板卡、测试系统和测试方法
相关申请的交叉引用
本公开要求在2021年09月16日提交中国专利局、申请号为202111084968.3、申请名称为“一种测试板卡、测试系统和测试方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种测试板卡、测试系统和测试方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件。在DRAM出厂之前，需要对DRAM进行信号完整性测试(Signal integrity，SI)。在相关技术中，将DRAM芯片通过专用转接板(一般称为为SI Interposer)焊接在系统主板的DRAM芯片封装处，然后将高速示波器的探头前端焊接在专用转接板的测试点上，从而进行SI测试。
然而，这种方法步骤复杂，而且不能脱离系统主板来进行DRAM芯片的SI测试，所以无法方便地修改测试相关的参数，从而导致测试灵活性差且效率低下。
发明内容
第一方面，本公开实施例提供了一种测试板卡，测试板卡包括寄存时钟驱动器RCD模块和待测试存储器，且RCD模块的输出端与待测试存储器的输入端连接；其中，
RCD模块，用于确定目标测试指令；以及在进入脱机模式后，向待测试存储器发送目标测试指令；
待测试存储器，用于接收目标测试指令，并根据目标测试指令输出测试结果。
在一些实施例中，测试板卡还包括连接模块；连接模块，与测试机台连接，用于接收测试机台发送的控制指令，并将控制指令发送给RCD模块，以使得RCD模块进入脱机模式。
在一些实施例中，连接模块，还用于接收测试机台发送的待处理测试指令，并将待处理测试指令发送给RCD模块；RCD模块，具体用于接收待处理测试指令，并根据待处理测试指令确定目标测试指令。
在一些实施例中，连接模块，还用于接收测试机台提供的第一电源信号，并通过第一电源信号驱动RCD模块和待测试存储器；或者连接模块，还用于接收测试机台提供的第一电源信号和第二电源信号，通过第一电源信号驱动RCD模块，以及通过第二电源信号驱动待测试存储器。
在一些实施例中，待处理测试指令包括第一地址信号、第一控制信号和第一系统时钟信号；RCD模块，具体用于从测试机台处接收第一地址信号、第一控制信号和第一系统时钟信号，并根据第一地址信号、第一控制信号和第一系统时钟信号，确定目标测试指令。
在一些实施例中，待处理测试指令包括第一地址信号和第一控制信号；测试板卡还包括时钟信号源；时钟信号源，用于生成第一系统时钟信号；RCD模块，具体用于从测试机台处接收第一地址信号和第一控制信号，从时钟信号源处接收第一系统时钟信号，并根据第一地址信号、第一控制信号和第一系统时钟信号，确定目标测试指令。
在一些实施例中，目标测试指令包括第二地址信号、第二控制信号和第二系统时钟信号，测试结果包括测试用数据信号和测试用数据控制信号；测试板卡还包括第一输出接口和第二输出接口，且第一输出接口和第二输出接口均与预设示波器连接；其中，待测试存储器，具体用于接收第二地址信号、第二控制信号和第二系统时钟信号，并根据第二地址信号、第二控制信号和第二系统时钟信号，输出测试用数据信号和测试用数据控制信号；第一输出接口，用于接收测试用数据信号，并将测试用数据信号发送给预设示波器；第二输出接口，用于接收测试用数据控制信号，并将测试用数据控制信号发送给预设示波器。
在一些实施例中，测试板卡还包括第一输出电阻和第二输出电阻，且第一输出电阻和第二输出电阻均与接地端连接；其中，待测试存储器，还用于根据第二地址信号、第二控制信号和第二系统时钟信号，输出数据信号和数据控制信号；第一输出电阻，用于接收数据信号，并将数据信号传输到地；第二输出电阻，用于接收数据控制信号，并将数据控制信号传输到地。
在一些实施例中，第一电源信号的电压为1.1伏特，第二电源信号的电压为1.8伏特；第一输出电阻和第二输出电阻的阻抗均为50欧姆。
在一些实施例中，测试机台包括现场可编程逻辑阵列FPGA，FPGA通过I2C总线与连接模块连接，且连接模块通过I2C总线与RCD模块连接。
第二方面，本公开实施例提供了一种测试系统，该测试系统至少包括测试机台和如第一方面中任一项所述的测试板卡。
第三方面，本公开实施例提供了一种测试方法，应用于包括测试机台和测试板卡的测试系统，且测试板卡包括RCD模块和待测试存储器；该方法包括：
在测试机台和测试板卡连接后，通过测试板卡确定目标测试指令；在测试机台控制RCD模块进入脱机模式后，基于目标测试指令，通过RCD模块对待测试存储器进行信号完整性测试，确定测试结果。
在一些实施例中，在测试机台和测试板卡连接后，该方法还包括：
接收测试机台提供的第一电源信号，并基于第一电源信号驱动RCD模块和待测试存储器；或者接收测试机台提供的第一电源信号和第二电源信号，并通过第一电源信号驱动RCD模块，通过第二电源信号驱动待测试存储器。
在一些实施例中，所述通过测试板卡确定目标测试指令，包括：
通过测试机台向测试板卡发送待处理测试指令；基于待处理测试指令，通过RCD模块确定目标测试指令。
在一些实施例中，在通过测试机台向测试板卡发送待处理测试指令之后，该方法还包括：
通过测试机台向测试板卡发送控制指令；基于控制指令，控制RCD模块进入脱机模式。
在一些实施例中，待处理测试指令包括第一地址信号、第一控制信号和第一系统时钟信号；
相应的，所述基于待处理测试指令，通过RCD模块确定目标测试指令，包括：
根据第一地址信号、第一控制信号和第一系统时钟信号，通过RCD模块确定目标测试指令。
在一些实施例中，待处理测试指令包括第一地址信号和第一控制信号；测试板卡还包括时钟信号源；
相应的，所述基于待处理测试指令，通过RCD模块确定目标测试指令，包括：
通过时钟信号源生成第一系统时钟信号；根据第一地址信号、第一控制信号和第一系统时钟信号，通过RCD模块确定目标测试指令。
在一些实施例中，目标测试指令包括第二地址信号、第二控制信号和第二系统时钟信号，测试结果包括测试用数据信号和测试用数据控制信号；
相应的，所述基于目标测试指令，通过RCD模块对待测试存储器进行信号完整性测试，确定测试结果，包括：
根据第二系统时钟信号、第二地址信号和第二控制信号，通过待测试存储器输出测试用数据信号和测试用数据控制信号。
在一些实施例中，测试系统还包括预设示波器，测试板卡还包括第一输出接口和第二输出接口；在确定测试结果之后，该方法还包括：
通过第一输出接口将测试用数据信号发送给预设示波器；通过第二输出接口将测试用数据控制信号发送给预设示波器。
在一些实施例中，测试板卡还包括第一输出电阻和第二输出电阻，且第一输出电阻和第二输出电阻均与接地端连接；该方法还包括：
根据第二系统时钟信号、第二地址信号和第二控制信号，通过待测试存储器输出数据信号和数据控制信号；通过第一输出电阻将数据信号传输到地，以及通过第二输出电阻将数据控制信号传输到地。
附图说明
图1为本公开实施例提供的一种测试板卡的结构示意图；
图2为本公开实施例提供的另一种测试板卡的结构示意图；
图3为本公开实施例提供的一种测试系统的组成结构示意图；
图4为本公开实施例提供的一种测试方法的流程示意图；
图5为本公开实施例提供的一种测试板卡的工作过程示意图；
图6为本公开实施例提供的另一种测试板卡的工作过程示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
以下对本公开实施例中涉及到的英文词汇及其缩写进行说明。
Dynamic Random Access Memory，DRAM：动态随机存取存储器；
Static Random-Access Memory，SRAM：静态随机存储存储器；
Synchronous Dynamic Random Access Memory，SDRAM：同步动态随机存储器；
Double Data Rate SDRAM，DDR：双倍速率SDRAM；
DDR5：第5版DDR的技术规范；
Dual Inline Memory Module，DIMM：双列直插内存模块；
RDIMM：带寄存器的双列直插式存储模块；
Signal integrity，SI：信号完整性测试；
SI Interposer：信号完整性测试专用的转接板；
Central Processing Unit，CPU：中央处理器。
Field Programmable Gate Array：现场可编辑逻辑门阵列：
Sub-Miniature-A，SMA：一种高频数据接口；
Inter-Integrated Circuit，I2C：两线式串行总线；
VHost：脱机模式。
应理解，动态随机存取存储器是计算机中常用的半导体存储器件，在DRAM出厂之前，需要对DRAM进行SI测试。
在相关技术中，为了对待测试存储器进行SI测试，首先需要将SI测试中的专用转接板焊接在系统主板的DRAM芯片封装处，特别地，专用转接板下方一般存在1毫米以上的垫高(Riser)，方便排除主板上其他元器件的干涉；然后，将DRAM芯片焊接在该专用转接板上；最后，将高速示波器的探头前端焊接在专用转接板的测试点上，从而进行SI测试。然而，这种测试方法的局限性在于：不能脱离系统主板来进行DRAM芯片的SI测试，因为CPU芯片里DRAM 控制器会进行乱序操作，同时测试模式(Pattern)不容易修改。
基于此，本公开实施例提供了一种测试板卡，该测试板卡包括寄存时钟驱动器RCD模块和待测试存储器，且RCD模块的输出端与待测试存储器的输入端连接；其中，RCD模块，用于确定目标测试指令；以及在进入脱机模式后，向待测试存储器发送目标测试指令；待测试存储器，用于接收目标测试指令，并根据目标测试指令输出测试结果。这样，本公开实施例提供了一种支持脱机模式的测试板卡，在脱机模式中利用RCD模块作为虚拟控制器，进而完成对待测试存储器的信号完整性测试，即测试板卡允许脱离系统主板对待测试存储器进行测试，能够方便地修改测试相关参数，提高测试的灵活性和效率。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图1，其示出了本公开实施例提供的一种测试板卡10的结构示意图。如图1所示，该测试板卡10包括寄存时钟驱动器RCD模块101和待测试存储器102，且RCD模块101的输出端与待测试存储器102的输入端连接；其中，
RCD模块101，用于确定目标测试指令；以及在进入脱机模式后，向待测试存储器102发送目标测试指令；
待测试存储器102，用于接收目标测试指令，并根据目标测试指令输出测试结果。
需要说明的是，本公开实施例提供的测试板卡10应用于多种存储器件的测试过程，存储器件可以是DRAM、SRAM和SDRAM等等。在本公开实施例中，以信号完整性测试为应用场景对测试板卡10进行后续说明，但这并不构成相关限制。
在本公开实施例中，测试板卡10可以包括RCD模块101和待测试存储器102。RCD模块101能够确定目标测试指令，并在脱机模式(VHost模式)下将目标测试指令发送给待测试存储器102，然后待测试存储器102输出相关的数据信号，以便工作人员确定测试结果。
需要说明的是，RCD模块101也可以称为RCD芯片，能够寄存相关数据指令(例如地址信号、控制信号和系统时钟信号)，并产生面向存储器的数据指令，并重新定义数据指令的发送时间。在相关技术中，RCD芯片原本用于数据缓冲。而在本公开实施例，通过RCD模块101来寄存相关的测试指令(即目标测试指令)，进而利用该测试指令对待测试存储器102进行SI测试。也就是说，RCD模块101可以作为虚拟主机控制待测试存储器102，从而允许SI测试在脱离内存控制器的情况下进行，提高SI测试的灵活性；另外，由于RCD模块101的存在，无需针对待测试存储器102配置数据总线和命令总线，即简化了测试过程，而且便于修改SI测试中的各种参数。
还需要说明的是，待测试存储器102是指通过预设方式连接在测试板卡10本体上的存储器，即待测试存储器102是可更换的。在这里，预设方式可以包括多种类型，例如将存储器安装在测试板卡10本体的预设插槽中，将存储器与测试板卡10本体的外设接口连接，将存储器焊接在测试板卡10本体中等。
应理解，从逻辑层面来看，仅当待测试存储器102安装于测试板卡10中之 后，测试板卡10才能够执行相应的测试功能，因此本公开实施例暂认为待测试存储器102是测试板卡的一部分。但是，从产品加工的角度，测试板卡可以不包括待测试存储器，而是仅设置可供待测试存储器连接的接口(该接口可以为各种类型的外设接口)，这种不含有待测试存储器的测试板卡同样在本公开实施例的保护范围之内。
在一些实施例中，测试板卡需要依赖于测试机台完成SI测试。参见图2，其示出了本公开实施例提供的另一种测试板卡10的结构示意图。如图2所示，测试板卡10还包括连接模块103；
连接模块103，与测试机台20连接，用于接收测试机台20发送的控制指令，并将控制指令发送给RCD模块101，以使得RCD模块101进入脱机模式。
需要说明的是，在进行SI测试之前，测试板卡10还需要通过连接模块103与测试机台20建立电性连接。在这里，工作人员可以根据测试需求在测试机台20中编写各种测试程序，从而测试机台20能够向测试板卡10发送控制指令，控制RCD模块101进入脱机模式。
类似地，测试板卡10也可以通过多种方式与测试机台20建立连接，例如将测试板卡10安装在测试机台20本体的预设插槽中，将测试板卡10与测试机台20本体的外设接口连接等。换句话说，连接模块103可以体现为多种类型的连接件，例如插槽、外设接口、焊点等等。
在一些实施例中，测试机台20包含了内存控制器的相关功能。因此，连接模块103，还用于接收测试机台20发送的待处理测试指令，并将待处理测试指令发送给RCD模块101；
RCD模块101，具体用于接收待处理测试指令，并根据待处理测试指令确定目标测试指令。
需要说明的是，在控制RCD模块101进入VHost模式前，测试机台20还需要通过连接模块103向RCD模块101发送待处理测试指令，而RCD模块101根据待处理测试指令生成针对于待测试存储器的目标测试指令。
应理解，对于存储器来说，测试指令至少包括地址信号(ADDR)、控制信号(CTRL)和系统时钟信号(CLK)，这些信号可以均由测试机台20提供。因此，在一种具体的实施例中，待处理测试指令包括第一地址信号(ADDR1)、第一控制信号(CTRL1)和第一系统时钟信号(CLK1)；
RCD模块101，具体用于从测试机台20处接收第一地址信号(ADDR1)、第一控制信号(CTRL1)和第一系统时钟信号(CLK1)，并根据第一地址信号(ADDR1)、第一控制信号(CTRL1)和第一系统时钟信号(CLK1)，确定目标测试指令。
这样，RCD模块101可以根据第一地址信号(ADDR1)确定目标测试指令信号中的地址信号，即第二地址信号(ADDR2)；根据第一控制信号(CTRL1)确定目标测试指令信号中的控制信号，即第二控制信号(CTRL2)；根据第一系统时钟信号(CLK1)确定目标测试指令信号中的系统时钟信号，即第二系统时钟信号(CLK2)。
在另一种具体的实施例中，如图2所示，测试板卡10上设置有时钟信号源 104，时钟信号源104用于生成第一系统时钟信号(CLK1)。
此时，测试板卡10可以通过时钟信号源104来生成第一系统时钟信号(CLK1)，即测试机台20仅需要提供第一地址信号(ADDR1)和第一控制信号(CTRL1)。即待处理测试指令包括第一地址信号(ADDR1)和第一控制信号(CTRL1)。
也就是说，RCD模块101，具体用于从测试机台20处接收第一地址信号(ADDR1)和第一控制信号(CTRL1)，从所述时钟信号源104处接收第一系统时钟信号(CLK1)，并根据第一地址信号(ADDR1)、第一控制信号(CTRL1)和第一系统时钟信号(CLK1)，确定目标测试指令。
需要说明的是，时钟信号源104可以为一连接点，用于引入外部电路产生的时钟信号，进而将外部电路产生的时钟信号确定为第一系统时钟信号(CLK1)；或者，时钟信号源104也可以为一时钟电路，用于直接产生时钟信号，即第一系统时钟信号CLK1。
在本公开实施例中，相比较于测试机台20提供的时钟信号，测试板卡10通过时钟信号源104生成的时钟信号更为准确，同步性更好，从而SI测试的结果更加精准。
另外，测试机台需要提前配置两种测试信号输出模式，即仅输出第一地址信号和第一控制信号，或者输出第一地址信号、第一控制信号和系统时钟信号，从而应对不同的测试环境。当然，部分测试机台可能不支持外部时钟信号源的状态，此时测试板卡需要采用测试机台提供的第一时钟信号。
在一些实施例中，测试结果包括测试用数据信号(LBDQ)和测试用数据控制信号(LBDQS)；
待测试存储器102，具体用于接收第二地址信号(ADDR2)、第二控制信号(CTRL2)和第二系统时钟信号(CLK2)，并根据第二地址信号(ADDR2)、第二控制信号(CTRL2)和第二系统时钟信号(CLK2)，输出测试用数据信号(LBDQ)和测试用数据控制信号(LBDQS)；
相应地，测试板卡10还可以包括第一输出接口和第二输出接口，且第一输出接口和第二输出接口均与预设示波器连接；其中，
第一输出接口，用于接收测试用数据信号(LBDQ)，并将测试用数据信号(LBDQ)发送给预设示波器；
第二输出接口，用于接收测试用数据控制信号(LBDQS)，并将测试用数据控制信号(LBDQS)发送给预设示波器。
需要说明的是，在RCD模块101进入VHost模式后，RCD模块101将包括目标测试指令信号(ADDR2信号、CTRL2信号和CLK2信号)发送给待测试存储器102，待测试存储器102进行指定的数据操作，输出测试用数据信号(LBDQ)和测试用数据控制信号(LBDQS)；然后，测试板卡10通过第一输出接口将测试用数据信号(LBDQ)发送到高速示波，通过第二输出接口将测试用数据控制信号(LBDQS)发送到高速示波器。
在一些实施例中，测试板卡10还包括第一输出电阻和第二输出电阻，且第一输出电阻和第二输出电阻均与接地端连接；其中，
待测试存储器102，还用于根据第二地址信号、第二控制信号和第二系统时钟信号，输出数据信号(DQ)和数据控制信号(DQS)；
第一输出电阻，用于接收数据信号(DQ)，并将数据信号(DQ)传输到地；
第二输出电阻，用于接收数据控制信号(DQS)，并将数据控制信号(DQS)传输到地。
需要说明的是，对于待测试存储器102而言，在输出测试用数据信号(LBDQ)和测试用数据控制信号(LBDQS)的同时，也会输出数据信号(DQ)和数据控制信号(DQS)。
在这里，DQ/DQS信号和LBDQ/LBDQS信号的本质是相同的，LBDQ/LBDQS信号仅在测试环境中引出，用于确定测试结果，在存储器处于正常使用环境时不会向后输出；而DQ/DQS信号刚好相反，DQ/DQS信号在存储器处于正常使用环境时会向后输出，在测试环境中则通过输出电阻传输到地。
应理解，DQ/DQS、LBDQ/LBDQS这些简写仅用于示例性的指示待测试存储器输出的信号，并不与任何实际中特定物理含义的信号关联，不构成对本公开实施例的限制。类似的，待测试存储器输出的信号数量也可以更多或者更少，本公开实施例仅为一种示例。
示例性地，第一输出电阻和第二输出电阻的阻抗均为50欧姆，但这并不构成相关限制。
在一些实施例中，测试机台20还需要为测试板卡10供电。因此，连接模块103，还用于接收测试机台20提供的第一电源信号，并通过第一电源信号驱动RCD模块101和待测试存储器102；或者
连接模块103，还用于接收测试机台20提供的第一电源信号和第二电源信号，通过第一电源信号驱动RCD模块101，以及通过第二电源信号驱动待测试存储器102。
需要说明的是，如果RCD模块101和待测试存储器102的工作电压相同或者差异较小，那么测试机台20仅需要向测试板卡10提供一个电源信号，利用该电源信号即可同时驱动RCD模块101和待测试存储器102。如果RCD模块101和待测试存储器102的工作电压差异较大，那么测试机台20需要向测试板卡10提供两个电源信号，利用两个电源信号分别驱动RCD模块101和待测试存储器102。
示例性地，RCD模块101的工作电压一般为1.1伏特，根据DDR5的规定，DRAM的工作电压可以为1.1伏特，或者可以为1.8伏特。因此，第一电源信号的电压可以为1.1伏特，第二电源信号的电压可以为1.8伏特。
用于示例地，测试机台20可以通过现场可编程逻辑阵列FPGA实现，FPGA通过I2C总线与连接模块103连接，且连接模块103通过I2C总线与RCD模块101连接。FPGA是一种在制造后可以被用户编程修改的电路，I2C总线是一种两线式串行总线，常用于微控制器与外设之间的连接。
这样，由于测试机台20可以通过现场可编程逻辑阵列FPGA实现，工作人员可以方便地对测试机台20的测试逻辑进行修改，灵活地修改测试模式以及其他测试参数，同时兼容多种规则的待测试存储器102，提高SI测试的灵活性和 效率。另外，通过I2C总线，可以方便地在测试机台20和测试板卡10之间建立通信连接，减小硬件成本。
本公开实施例提供了一种测试板卡，该测试板卡包括寄存时钟驱动器RCD模块和待测试存储器，且RCD模块的输出端与待测试存储器的输入端连接；其中，RCD模块，用于确定目标测试指令；以及在进入脱机模式后，向待测试存储器发送目标测试指令；待测试存储器，用于接收目标测试指令，并根据目标测试指令输出测试结果。这样，本公开实施例提供了一种支持脱机模式的测试板卡，在脱机模式中利用RCD模块作为虚拟控制器，进而完成对待测试存储器的信号完整性测试，即测试板卡允许脱离系统主板对待测试存储器进行测试，能够方便地修改测试相关参数，提高测试的灵活性和效率。
在本公开的另一实施例中，参见图3，其示出了本公开实施例提供的一种测试系统30的结构示意图。如图3所示，该测试系统30至少包括测试机台20和前述的测试板卡10。
在这里，测试板卡10中包括RCD模块，该RCD模块能够在脱机模式下作为虚拟控制器对待测试存储器进行信号完整性测试。
本公开实施例提供了一种测试系统，包括支持脱机模式的测试板卡，在脱机模式中利用RCD模块作为虚拟控制器，进而完成对待测试存储器的信号完整性测试，即测试板卡允许脱离系统主板对待测试存储器进行测试，能够方便地修改测试相关参数，提高测试的灵活性和效率。
在本公开的另一实施例中，参见图4，其示出了本公开实施例提供的一种测试方法的流程示意图。如图4所示，该方法可以包括：
S401：在测试机台和测试板卡连接后，通过测试板卡确定目标测试指令。
需要说明的是，本公开实施例中的测试方法应用于包括测试机台和测试板卡的测试系统，且测试板卡包括RCD模块和待测试存储器。
在对待测试存储器进行SI测试时，需要将待测试存储器安装在测试板卡上，并将测试板卡连接到测试机台上；然后，利用测试板卡中RCD模块寄存测试机台发来的目标测试指令，并通过测试机台控制RCD模块进行VHost模式；最后，利用目标测试指令对待测试存储器进行测试，得到测试结果。这样，RCD模块可以作为虚拟主机控制待测试存储器，从而允许SI测试在脱离内存控制器的情况下进行，提高SI测试的灵活性；另外，由于RCD模块的存在，无需针对待测试存储器配置数据总线和命令总线，即简化了测试过程，而且便于修改SI测试中的各种参数。
在这里，测试板卡可以通过多种方式连接与测试机台建立连接，例如插槽、外设接口等。在测试板卡与测试机台连接后，测试板卡和测试机台之间存在通信连接。示例性地，可以利用I2C总线作为测试板卡和测试机台之间的信息通道。
在一些实施例中，在测试机台和测试板卡连接后，该方法还可以包括：
接收测试机台提供的第一电源信号，并基于第一电源信号驱动RCD模块和待测试存储器；或者
接收测试机台提供的第一电源信号和第二电源信号，并通过第一电源信号 驱动RCD模块，通过第二电源信号驱动待测试存储器。
需要说明的是，RCD模块是固定安装在测试板卡中的，具有一固定的工作电压。但是，待测试存储器是需要进行更换的，而不同型号的待测试存储器的工作电压是不同的。所以待测试存储器的工作电压和RCD模块的工作电压可能是相同，也可能是不同的。
因此，在待测试存储器的工作电压和RCD模块的工作电压相同的情况下，在测试板卡和测试机台连接后，测试板卡还会从测试机台处获得第一电源信号，并根据第一电源信号驱动待测试存储器和RCD模块。
反之，在待测试存储器的工作电压和RCD模块的工作电压不同的情况下，测试板卡需要从测试机台处获得两个不同的电源信号，即第一电源信号和第二电源信号，并根据第一电源信号驱动RCD模块，根据第二电源信号驱动待测试存储器。
示例性地，RCD模块的工作电压一般为1.1伏特，根据DDR5的规定，第5代DRAM允许两种工作电压，分别是1.1伏特和1.8伏特。换句话说，若待测试存储器的工作电压为1.1伏特，则测试板卡仅需要从测试机台处获取第一电源信号(电压为1.1伏特)，即可同时驱动RCD模块和待测试存储器；若待测试存储器的工作电压为1.8伏特，则测试板卡仅需要从测试机台处获取第一电源信号(电压为1.1伏特)和第二电源信号(电压为1.8伏特)，分别驱动RCD模块和待测试存储器。
在一些实施例中，所述通过测试板卡确定目标测试指令，可以包括：
通过测试机台向测试板卡发送待处理测试指令；
基于待处理测试指令，通过RCD模块确定目标测试指令。
需要说明的是，在测试机台和测试板卡建立连接之后，测试机台向测试板卡发送待处理测试指令，测试板卡中的RCD模块可以将待处理测试指令处理成面向待测试存储器的目标测试指令，并将目标测试指令进行寄存并在特定的时刻向待测试存储器发出目标测试指令。换句话说，RCD模块可以重新定义待处理测试指令的时序。
需要说明的是，在待测试存储器的SI测试过程中，需要涉及三种类型的信号，即地址信号(ADDR)、控制信号(CTRL)和系统时钟信号(CTRL)。
在一种具体的实施例中，测试机台可以提供以上三种类型的信号，即待处理测试指令可以包括第一地址信号(ADDR1)、第一控制信号(CTRL1)和第一系统时钟信号(CLK1)。
相应的，所述基于待处理测试指令，通过RCD模块确定目标测试指令，可以包括：
根据第一地址信号(ADDR1)、第一控制信号(CTRL1)和第一系统时钟信号(CLK1)，通过RCD模块确定目标测试指令。
在另一种具体的实施例中，测试板卡中可以包括独立的时钟信号源，此时测试机台可以仅提供地址信号和控制信号，即待处理测试指令包括第一地址信号(ADDR1)和第一控制信号(CTRL1)；
相应的，所述基于待处理测试指令，通过RCD模块确定目标测试指令，可 以包括：
通过时钟信号源生成第一系统时钟信号；
根据第一地址信号(ADDR1)、第一控制信号(CTRL1)和第一系统时钟信号(CLK1)，通过RCD模块确定目标测试指令。
需要说明的是，在RCD模块接收到第一地址信号(ADDR1)、第一控制信号(CTRL1)和第一系统时钟信号(CLK1)，将其转化为面向待测试存储器的第二地址信号(ADDR2)、第二控制信号(CTRL2)和第二系统时钟信号(CLK2)，也就得到了目标测试指令。
这样，通过以上步骤，RCD模块确定了包括第二地址信号(ADDR2)、第二控制信号(CTRL2)和第二系统时钟信号(CLK2)的目标测试指令。
S402：在测试机台控制RCD模块进入脱机模式后，基于目标测试指令，通过RCD模块对待测试存储器进行信号完整性测试，确定测试结果。
需要说明的是，RCD模块可以寄存目标测试指令，并在进入脱机模式后，作为虚拟控制器对待测试存储器进行控制。
在一些实施例中，在通过测试机台向测试板卡发送待处理测试指令之后，该方法还可以包括：
通过测试机台向测试板卡发送控制指令；
基于控制指令，控制RCD模块进入脱机模式。
需要说明的是，在测试机台向测试板卡发送待处理测试指令之后，测试机台还会向测试板卡发送控制指令，该控制指令用于指示RCD模块进入脱机模式。
这样，借由测试板卡的存在，SI测试在控制层面可以脱离测试机台(物理层面仍需测试机台提供电源)，从而提高SI测试的灵活性；另外，通过测试板卡的RCD模块作为虚拟控制器，从而无需配置地址和命令总线，可以非常方便的进行测试。
根据前述内容，目标测试指令包括第二地址信号(ADDR2)、第二控制信号(CTRL2)和第二系统时钟信号(CLK2)。
另外，在本公开实施例中，测试结果包括测试用数据信号(LBDQ)和测试用数据控制信号(LBDQS)。因此，所述基于目标测试指令，通过RCD模块对待测试存储器进行信号完整性测试，确定测试结果，可以包括：
根据第二地址信号(ADDR2)、第二控制信号(CTRL2)和第二系统时钟信号(CLK2)，通过待测试存储器输出测试用数据信号(LBDQ)和测试用数据控制信号(LBDQS)。
在一些实施例中，测试系统还包括预设示波器，测试板卡还包括第一输出接口和第二输出接口；在确定测试结果之后，该方法还可以包括：
通过第一输出接口将测试用数据信号(LBDQ)发送给预设示波器；
通过第二输出接口将测试用数据控制信号(LBDQS)发送给预设示波器。
需要说明的是，待测试存储器根据目标测试指令信号输出测试用数据信号(LBDQ)和测试用控制数据信号(LBDQS)，通过第一输出接口将测试用数据信号(LBDQ)发送给预设示波器显示，通过第二输出接口将测试用控制数据信 号(LBDQS)发送给预设示波器显示。
在一些实施例中，该方法还可以包括：
根据第二地址信号(ADDR2)、第二控制信号(CTRL2)和第二系统时钟信号(CLK2)，通过待测试存储器输出数据信号(DQ)和数据控制信号(DQS)；
相应地，测试板卡还包括第一输出电阻和第二输出电阻，且第一输出电阻和第二输出电阻均与接地端连接；通过第一输出电阻将数据信号(DQ)传输到地，以及通过第二输出电阻将数据控制信号(DQS)传输到地。
需要说明的是，在接收到目标测试指令信号后，待测试存储器实际上会同时输出DQ/DQS和LBDQ/LBDQS两对信号。在这里，DQ/DQS信号和LBDQ/LBDQS信号的本质是相同的，LBDQ/LBDQS信号仅在测试环境中引出，用于后续确定SI的测试结果，在存储器处于正常使用环境时不会向后输出；而DQ/DQS信号刚好相反，DQ/DQS信号在存储器处于正常使用环境时会向后输出，在测试环境中则通过输出电阻传输到地。
示例性地，第一输出电阻和第二输出电阻的阻抗均为50欧姆，但这并不构成相关限制。
本公开实施例提供了一种测试方法，应用于包括测试机台和测试板卡的测试系统，且所述测试板卡包括RCD模块和待测试存储器；该方法包括：在所述测试机台和所述测试板卡连接后，通过所述测试板卡确定目标测试指令；在所述测试机台控制RCD模块进入脱机模式后，基于所述目标测试指令，通过所述RCD模块对所述待测试存储器进行信号完整性测试，确定测试结果。这样，本公开实施例提供了一种支持脱机模式的测试方法，在脱机模式中利用RCD模块作为虚拟控制器，进而完成对待测试存储器的信号完整性测试，即测试板卡允许脱离系统主板对待测试存储器进行测试，能够方便地修改测试相关参数，提高测试的灵活性和效率。
在本公开的又一实施例中，参见图5，其示出了本公开实施例提供的一种测试板卡10的工作过程示意图。在本公开实施例中，测试板卡和测试机台(图5未示出)构成完整的测试系统，该测试系统应用于DDR5 RDIMM SI的测试验证，通过利用测试机台(采用FPGA设计)对RCD芯片(或称为DDR5 RCD芯片)及待测试存储器(或称为DDR5 SDRAM、DDR5颗粒、DDR5存储颗粒)进行控制和写入，利用高速示波器对待测试存储器输出的DQS信号和DQ信号进行SI测试。也就是说，测试板卡应用于DDR5 RDIMM的调试和测试。
该测试板卡10又称为DDR5 RDIMM读取测试板卡，包括RCD芯片(相当于RCD模块)和待测试存储器。具体地，测试板卡可以设计为X8和X16两个版本，分别匹配输出数据位宽为8位的存储器和数据位宽为16位的待测试存储器。测试板卡具有兼容多种类型的存储器的内存条插槽连接器(例如型号为DDR4 288pin内存条插槽连接器)，有一个插口(Socket)方便更换DDR5存储颗粒。另外，RCD芯片焊接在测试板卡上。
该测试板卡10还具有连接模块(例如UDIMM Connector)，用于与测试机台连接。在这里，测试机台中包括FPGA电路搭建的主板(或称为FPGA Board)。也就是说，UDIMM Connector用于连接到FPGA Board。
这样，通过测试机台中的FPGA Board向RCD芯片发送测试指令(包括CLK1信号、ADDR1信号和CTRL1信号)，RCD芯片可以寄存测试指令，并在进入VHost模式后作为虚拟控制器，基于所寄存的测试指令，向待测试存储器发送CLK2信号、ADDR2信号和CTRL2信号，从而待测试存储器输出DQ/DQS信号和LBDQ/LBDQS信号。其中，DQ/DQS信号通过50欧姆(ohm)的电阻传输到地；LBDQ/LBDQS信号通过引脚输入到高速示波器进行显示，以便工作人员确定测试结果。在这里，测试板卡通过两个高频连接器接口(例如SMA接口)分别与高速示波器连接，分别输出LBDQ信号和LBDQS信号。
也就是说，在RCD芯片进入VHost模式后，将测试指令发送给待测试存储器，在SI测试的过程中，测试板卡引出待测试存储器(例如DDR5存储芯片)的数据输入输出(Input/Output，IO)接口，并串联50欧姆的电阻到地，以将DQ/DQS信号通过50欧姆的电阻传输到地，进行读取测试；另外，测试板卡还会引出LBDQ/LBDQS信号，并将其发送给高速示波器进行显示，从而完成SI测试。
测试板卡10同时具有切换测试机台的FPGA内部时钟和外部输入时钟的设计，方便使用外部时钟信号进行测试，从而提高时钟同步性，进而提高SI测试结果的准确性。如图5所示，测试板卡10不包括外部时钟产生器(相当于前述的时钟信号源)，CLK1信号由测试机台的FPGA内部时钟提供；参见图6，其示出了本公开实施例提供的另一种测试板卡10的工作过程示意图。如图6所示，测试板卡10包括外部时钟产生器(相当于前述的时钟信号源)，CLK1信号由外部输入时钟提供。
测试机台可通过I2C总线使RCD芯片进入VHost模式从而无需配置地址和命令总线，方便修改测试参数，提高测试灵活性。
根据待测试存储器规格的不同，测试机台可以提供一个Power信号(即电源1)，该Power信号同时驱动RCD芯片和待测试存储器；或者测试机台可以提供两个Power信号(即电源1和电源2)，两个Power信号分别驱动RCD芯片和待测试存储器。
还需要说明的是，VHost模式允许DRAM测试脱离内存控制器使用，只需要通过I2C总线发送一系列指令到RCD芯片，即可将RCD芯片作为虚拟主机控制DRAM芯片，进行一系列测试。
应理解，VHost模式有以下特点：最多支持4条测试指令；每条指令可以为1周期或2周期指令；每条指令之间可设置间隔时钟数量，例如可以为2、4、8、16、64、256和1024个间隔时钟；最后一个指令结束后，可以从任意指令开始重新循环。
基于图5和图6示出的测试板卡10，整个测试过程可以分为以下阶段：
(1)在FPGA测试机台电源关闭的状态下，将测试板卡插入FPGA测试机台的DIMM插槽中；
(2)将示波器高速探头前端连接到50欧姆电阻两端；
(3)对整个测试系统上电，待各个芯片正常工作后，FPGA测试机台通过I2C总线控制RCD芯片进入VHost模式，然后RCD芯片对DDR5颗粒进行测 试，并使用高速示波器获取DQS和DQ信号，确定SI测试结果；
(4)重复上一步骤，直至对需要测量的所有信号进行测量。
综上所述，本公开实施例还提供了一种对DDR5 RDIMM的SI测试方法，可应用在DDR5芯片SI测试，至少具有以下优点：一方面，支持通过I2C总线控制RCD芯片进入VHost模式；另一方面，使用RCD发送命令控制DRAM进入测试模式；又一方面，通过RCD方便地修改测试Pattern；再一方面，可脱离系统平台的CPU独立运行。
本公开实施例提供了一种测试板卡，包括RCD模块和待测试存储器，通过本实施例对前述实施例的具体实施方法进行了详细阐述，从中可以看出，本公开实施例提供了一种支持脱机模式的测试方法，在脱机模式中利用RCD模块作为虚拟控制器，进而完成对待测试存储器的信号完整性测试，即测试板卡允许脱离系统主板对待测试存储器进行测试，能够方便地修改测试相关参数，提高测试的灵活性和效率。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种测试板卡、测试系统和测试方法，该测试板卡包括寄存时钟驱动器RCD模块和待测试存储器，且RCD模块的输出端与待测试存储器的输入端连接；其中，RCD模块，用于确定目标测试指令；以及在进入脱机模式后，向待测试存储器发送目标测试指令；待测试存储器，用于接收目标测试指令，并根据目标测试指令输出测试结果。这样，本公开实施例提供了一种支持脱机模式的测试板卡，允许脱离系统主板对待测试存储器进行测试，能够方便地修改测试相关参数，提高测试的灵活性和效率。

Claims (20)

  1. 一种测试板卡，所述测试板卡包括寄存时钟驱动器RCD模块和待测试存储器，且所述RCD模块的输出端与所述待测试存储器的输入端连接；其中，
    所述RCD模块，用于确定目标测试指令；以及在进入脱机模式后，向所述待测试存储器发送所述目标测试指令；
    所述待测试存储器，用于接收所述目标测试指令，并根据所述目标测试指令输出测试结果。
  2. 根据权利要求1所述的测试板卡，其中，所述测试板卡还包括连接模块；
    所述连接模块，与测试机台连接，用于接收所述测试机台发送的控制指令，并将所述控制指令发送给RCD模块，以使得所述RCD模块进入脱机模式。
  3. 根据权利要求2所述的测试板卡，其中，
    所述连接模块，还用于接收所述测试机台发送的待处理测试指令，并将所述待处理测试指令发送给所述RCD模块；
    所述RCD模块，具体用于接收所述待处理测试指令，并根据所述待处理测试指令确定所述目标测试指令。
  4. 根据权利要求3所述的测试板卡，其中，
    所述连接模块，还用于接收所述测试机台提供的第一电源信号，并通过所述第一电源信号驱动所述RCD模块和所述待测试存储器；或者
    所述连接模块，还用于接收所述测试机台提供的第一电源信号和第二电源信号，通过所述第一电源信号驱动所述RCD模块，以及通过所述第二电源信号驱动所述待测试存储器。
  5. 根据权利要求3所述的测试板卡，其中，所述待处理测试指令包括第一地址信号、第一控制信号和第一系统时钟信号；
    所述RCD模块，具体用于从所述测试机台处接收所述第一地址信号、所述第一控制信号和所述第一系统时钟信号，并根据所述第一地址信号、所述第 一控制信号和所述第一系统时钟信号，确定所述目标测试指令。
  6. 根据权利要求3所述的测试板卡，其中，所述待处理测试指令包括第一地址信号和第一控制信号；所述测试板卡还包括时钟信号源；
    所述时钟信号源，用于生成第一系统时钟信号；
    所述RCD模块，具体用于从所述测试机台处接收所述第一地址信号和所述第一控制信号，从所述时钟信号源处接收所述第一系统时钟信号，并根据所述第一地址信号、所述第一控制信号和所述第一系统时钟信号，确定所述目标测试指令。
  7. 根据权利要求4所述的测试板卡，其中，所述目标测试指令包括第二地址信号、第二控制信号和第二系统时钟信号，所述测试结果包括测试用数据信号和测试用数据控制信号；
    所述测试板卡还包括第一输出接口和第二输出接口，且所述第一输出接口和所述第二输出接口均与预设示波器连接；其中，
    所述待测试存储器，具体用于接收所述第二地址信号、所述第二控制信号和所述第二系统时钟信号，并根据所述第二地址信号、所述第二控制信号和所述第二系统时钟信号，输出所述测试用数据信号和所述测试用数据控制信号；
    所述第一输出接口，用于接收所述测试用数据信号，并将所述测试用数据信号发送给所述预设示波器；
    所述第二输出接口，用于接收所述测试用数据控制信号，并将所述测试用数据控制信号发送给所述预设示波器。
  8. 根据权利要求7所述的测试板卡，其中，所述测试板卡还包括第一输出电阻和第二输出电阻，且所述第一输出电阻和第二输出电阻均与接地端连接；其中，
    所述待测试存储器，还用于根据所述第二地址信号、所述第二控制信号和所述第二系统时钟信号，输出数据信号和数据控制信号；
    所述第一输出电阻，用于接收所述数据信号，并将所述数据信号传输到地；
    所述第二输出电阻，用于接收所述数据控制信号，并将所述数据控制信号 传输到地。
  9. 根据权利要求8所述的测试板卡，其中，所述第一电源信号的电压为1.1伏特，所述第二电源信号的电压为1.8伏特；
    所述第一输出电阻和所述第二输出电阻的阻抗均为50欧姆。
  10. 根据权利要求2所述的测试板卡，其中，
    所述测试机台包括现场可编程逻辑阵列FPGA，所述FPGA通过I2C总线与所述连接模块连接，且所述连接模块通过I2C总线与所述RCD模块连接。
  11. 一种测试系统，所述测试系统至少包括测试机台和如权利要求1至10任一项所述的测试板卡。
  12. 一种测试方法，应用于包括测试机台和测试板卡的测试系统，且所述测试板卡包括RCD模块和待测试存储器；所述方法包括：
    在所述测试机台和所述测试板卡连接后，通过所述测试板卡确定目标测试指令；
    在所述测试机台控制RCD模块进入脱机模式后，基于所述目标测试指令，通过所述RCD模块对所述待测试存储器进行信号完整性测试，确定测试结果。
  13. 根据权利要求12所述的测试方法，其中，在所述测试机台和所述测试板卡连接后，所述方法还包括：
    接收所述测试机台提供的第一电源信号，并基于所述第一电源信号驱动所述RCD模块和所述待测试存储器；或者
    接收所述测试机台提供的所述第一电源信号和第二电源信号，并通过所述第一电源信号驱动所述RCD模块，通过所述第二电源信号驱动所述待测试存储器。
  14. 根据权利要求13所述的测试方法，其中，所述通过所述测试板卡确定目标测试指令，包括：
    通过所述测试机台向所述测试板卡发送待处理测试指令；
    基于所述待处理测试指令，通过所述RCD模块确定所述目标测试指令。
  15. 根据权利要求14所述的测试方法，其中，在所述通过所述测试机台 向所述测试板卡发送待处理测试指令之后，所述方法还包括：
    通过所述测试机台向所述测试板卡发送控制指令；
    基于所述控制指令，控制所述RCD模块进入脱机模式。
  16. 根据权利要求14所述的测试方法，其中，所述待处理测试指令包括第一地址信号、第一控制信号和第一系统时钟信号；
    所述基于所述待处理测试指令，通过所述RCD模块确定所述目标测试指令，包括：
    根据所述第一地址信号、所述第一控制信号和所述第一系统时钟信号，通过所述RCD模块确定所述目标测试指令。
  17. 根据权利要求14所述的测试方法，其中，所述待处理测试指令包括第一地址信号和第一控制信号；所述测试板卡还包括时钟信号源；
    所述基于所述待处理测试指令，通过所述RCD模块确定所述目标测试指令，包括：
    通过所述时钟信号源生成第一系统时钟信号；
    根据所述第一地址信号、所述第一控制信号和所述第一系统时钟信号，通过所述RCD模块确定所述目标测试指令。
  18. 根据权利要求14所述的测试方法，其中，所述目标测试指令包括第二地址信号、第二控制信号和第二系统时钟信号，所述测试结果包括测试用数据信号和测试用数据控制信号；
    所述基于所述目标测试指令，通过所述RCD模块对所述待测试存储器进行信号完整性测试，确定测试结果，包括：
    根据所述第二系统时钟信号、所述第二地址信号和所述第二控制信号，通过所述待测试存储器输出所述测试用数据信号和所述测试用数据控制信号。
  19. 根据权利要求18所述的测试方法，其中，所述测试系统还包括预设示波器，所述测试板卡还包括第一输出接口和第二输出接口；在所述确定测试结果之后，所述方法还包括：
    通过所述第一输出接口将所述测试用数据信号发送给所述预设示波器；
    通过所述第二输出接口将所述测试用数据控制信号发送给所述预设示波器。
  20. 根据权利要求18所述的测试方法，其中，所述测试板卡还包括第一输出电阻和第二输出电阻，且所述第一输出电阻和所述第二输出电阻均与接地端连接；所述方法还包括：
    根据所述第二系统时钟信号、所述第二地址信号和所述第二控制信号，通过所述待测试存储器输出数据信号和数据控制信号；
    通过所述第一输出电阻将所述数据信号传输到地，以及通过所述第二输出电阻将所述数据控制信号传输到地。
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