WO2023039840A1 - 比较器及相关图像传感器及电子装置 - Google Patents

比较器及相关图像传感器及电子装置 Download PDF

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WO2023039840A1
WO2023039840A1 PCT/CN2021/119093 CN2021119093W WO2023039840A1 WO 2023039840 A1 WO2023039840 A1 WO 2023039840A1 CN 2021119093 W CN2021119093 W CN 2021119093W WO 2023039840 A1 WO2023039840 A1 WO 2023039840A1
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signal
transistor
output
comparator
drain
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PCT/CN2021/119093
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English (en)
French (fr)
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周健荣
徐嘉骏
徐建昌
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迪克创新科技有限公司
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Priority to CN202180004887.XA priority Critical patent/CN114245985A/zh
Priority to PCT/CN2021/119093 priority patent/WO2023039840A1/zh
Publication of WO2023039840A1 publication Critical patent/WO2023039840A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters

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  • the present application relates to a circuit, in particular to a comparator and related image sensors and electronic devices.
  • CMOS image sensors not only need to have a large-scale pixel array, but also require high signal processing speed.
  • the design of a single analog-to-digital conversion circuit is difficult to realize, so the column-based analog-to-digital conversion circuit is produced.
  • the existing column analog-to-digital conversion circuit used for CMOS image sensors needs to read the value of the counter at any time, and high power consumption is a problem that is criticized by people. Therefore, how to solve the above problems has become an urgent problem in this field. one of the problems.
  • One of the objectives of the present application is to disclose a comparator and related image sensor and electronic device to solve the above problems.
  • An embodiment of the present application discloses a comparator for generating a comparator output signal according to a ramp signal and a pixel output signal, including: an input stage receiving the ramp signal and the pixel output signal, when the ramp signal When the output signal of the pixel is changed from being larger than the output signal of the pixel to being smaller than the output signal of the pixel, or the slope signal is changed from being smaller than the output signal of the pixel to being larger than the output signal of the pixel, the first signal output by the input stage is changed by the first a voltage level is converted to a second voltage level; a gain stage is used to provide gain to the first signal and output a second signal; an output stage is used to output a third signal according to the second signal; and an arithmetic unit, and used for outputting the comparator output signal according to the second signal and the third signal.
  • An embodiment of the present application discloses a comparator for generating a comparator output signal according to a ramp signal and a pixel output signal, including: an input stage receiving the ramp signal and the pixel output signal, when the ramp signal When the output signal of the pixel is changed from being larger than the output signal of the pixel to being smaller than the output signal of the pixel, or the slope signal is changed from being smaller than the output signal of the pixel to being larger than the output signal of the pixel, the first signal output by the input stage is changed by the first The voltage level is converted to a second voltage level; a gain stage is used to provide gain to the first signal and output a second signal; an output stage is used to output a third signal according to the second signal; a copy gain stage, used to provide gain to the first signal and output a fourth signal; and an operation unit used to output the comparator output signal according to the fourth signal and the third signal.
  • An embodiment of the present application discloses an image sensor, including: a pixel array, including at least one pixel column; an analog-to-digital conversion unit, including: the above-mentioned comparator, coupled to the at least one pixel column; and at least one latch A device, coupled to the at least one comparator; a row decoder, used to control the at least one pixel column to output the pixel output signal; a ramp signal generating circuit, used to generate the ramp signal; and a counter, used to perform counting operation and outputting the counting result; wherein the at least one comparator generates the comparator output signal to control the enable time of the at least one latch, and when the at least one latch is enabled, continuously and latching the counting result of the counter.
  • An embodiment of the present application discloses an electronic device, including: the above-mentioned image sensor.
  • the comparators and associated image sensors and electronics of the present application can reduce the power consumption of column analog-to-digital converters in image sensors.
  • FIG. 1 is a schematic diagram of an embodiment of an image sensor.
  • FIG. 2 is a schematic diagram of a first embodiment of a comparator proposed in this application.
  • FIG. 3 is an operation timing diagram of the comparator of the present application.
  • FIG. 4 is a schematic diagram of a second embodiment of the comparator proposed in this application.
  • FIG. 5 is a schematic diagram of a third embodiment of the comparator proposed in the present application.
  • first and second features are in direct contact with each other; and may also include additional components are formed between the first and second features, such that the first and second features may not be in direct contact.
  • this disclosure may reuse reference symbols and/or labels in various embodiments. Such repetition is for the sake of brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.
  • FIG. 1 is a schematic diagram of an embodiment of an image sensor.
  • the image sensor 100 includes a pixel array 102 , an analog-to-digital conversion unit 106 , a row decoder 104 , a ramp signal generation circuit 108 and a counter 110 .
  • the pixel array 102 includes multiple columns of pixel columns and multiple rows of one pixel row
  • the analog-to-digital conversion unit 106 includes multiple columns of analog-to-digital conversion circuits that are correspondingly coupled to the multiple columns of pixel columns, wherein each column of analog-to-digital conversion circuits includes a comparator and a lock memory. It should be noted that the multi-column pixel columns and multi-column analog-to-digital conversion circuits shown in FIG. digital conversion circuit.
  • the row decoder 104 is used to control each pixel column in the pixel array 102 to output pixel output signals, and the counter 110 is used to perform a counting operation and output a counting result.
  • the output pixel output signal PXO and the ramp signal Vramp generated by the ramp signal generating circuit 108 will pass through the comparator 1062
  • the comparison is performed, and a comparator output signal Scmp is output to control the enable time of the latch 1064 . Because the latch 1064 will continuously latch the counting result of the counter 110 only when it is enabled.
  • the embodiment of the comparator proposed in this application can reduce the power consumption of the column ADC by reducing the enable time of the latch 1064 without affecting the performance of the image sensor 100 . Its details are as follows.
  • FIG. 2 is a schematic diagram of a first embodiment of a comparator proposed in this application.
  • the comparator 200 is used to generate the comparator output signal Scmp according to the ramp signal Vramp and the pixel output signal PXO, and the comparator 200 can be used to realize all or part of the comparator in FIG. 1 .
  • the comparator 200 includes an input stage 202 , a gain stage 204 , an output stage 206 and an operation unit 208 .
  • FIG. 3 is an operation timing diagram of the comparator of the present application.
  • the input stage 202 is used as a differential amplifier to receive the ramp signal Vramp and the pixel output signal PXO. middle), the output signal S1 of the input stage 202 will be triggered to drop from a high voltage level to a low voltage level at the time point T1, and the time point T1 will be slightly later than the time point T0.
  • the input stage 202 includes an input stage current source 2022, a transistor M1, a transistor M2, a transistor M3 and a transistor M4 to form a differential amplifier, wherein the source of the transistor M1 is coupled to the input stage current source 2022, and the gate of the transistor M1 is used to receive Ramp signal Vramp.
  • the source of the transistor M2 is coupled to the input stage current source 2022 , the gate of the transistor M2 is used to receive the pixel output signal PXO, and the drain of the transistor M2 is used to output the signal S1 .
  • the drain and gate of the transistor M3 are coupled to each other, and the drain of the transistor M3 is also coupled to the drain of the transistor M1.
  • the gate of the transistor M4 is coupled to the gate of the transistor M3, and the drain of the transistor M3 is further coupled to the drain of the transistor M2.
  • the implementation of the input stage 202 of the present application is not limited to FIG. 2 .
  • the operation timing diagram in FIG. 3 may also be adjusted to obtain different aspects, but it should still belong to the scope of the present application.
  • the ramp signal Vramp can be from bottom to top, so that when the ramp signal Vramp changes from being smaller than the pixel output signal PX0 to being larger than the pixel output signal, the signal S1 output from the input stage 202 climbs from a low voltage level to a high voltage level.
  • the gain stage 204 is used to provide gain to the signal S1 and output a signal S2.
  • the gain stage 204 includes a gain stage current source 2042 and a transistor M5, wherein the drain of the transistor M5 is coupled to the gain stage current source 2042, the gate of the transistor M5 is used to receive the signal S1, and the drain of the transistor M5 is also used to output the signal S2 .
  • the signal S1 drops from a high voltage level to a low voltage level at the time point T1
  • the signal S2 output by the gain stage 204 will climb from a low voltage level to a high voltage level at the time point T2, and the time Point T2 will be slightly later than time point T1.
  • the embodiment of the gain stage 204 of the present application is not limited to FIG. 2 .
  • the output stage 206 is used for outputting the signal S3 according to the signal S2.
  • the output stage 206 includes an output stage current source 2062 and a transistor M6, wherein the drain of the transistor M6 is coupled to the output stage current source 2062, the gate of the transistor M6 is used to receive the signal S2, and the drain of the transistor M6 is also used to output the signal S3 .
  • FIG. 3 when the signal S2 climbs from a low voltage level to a high voltage level at the time point T2, the signal S3 output by the output stage 206 will fall from a high voltage level to a low voltage level at the time point T3. Point T3 will be slightly later than time point T2. It should be noted that the embodiment of the output stage 206 of the present application is not limited to FIG. 2 .
  • the computing unit 208 is used for outputting the comparator output signal Scmp according to the signal S2 and the signal S3 .
  • the operation unit 208 includes an AND gate 2082, and the AND gate 2082 is used to perform an "AND" operation on the signal S2 and the signal S3 to obtain the signal Scmp.
  • the signal Scmp is at a high voltage level between the time point T2 and the time point T3 , and is at a low voltage level at other times. It should be noted that, for convenience of illustration, the timing diagram in FIG. 3 does not consider the delay time of the AND gate 2082 .
  • the latch 1064 it is only necessary to latch the counting result of the counter 110 at the moment when the value of the signal Scmp changes. Therefore, when the comparator 200 of the present application is applied to the comparator 1062 of FIG. 1 , only The latch 1064 is enabled only after the relationship between the ramp signal Vramp and the pixel output signal PXO changes, specifically, the latch 1064 is only enabled between the time point T2 and the time point T3, and does not need to be fixed at The latch 1064 is enabled before the relationship between the ramp signal Vramp and the pixel output signal PXO changes (for example, at time point Tz). Therefore, unnecessary latch operations of the latch 1064 can be avoided, in other words, the power consumption of the column ADC can be reduced.
  • the input stage 202 and the gain stage 204 belong to the first power domain (corresponding to the reference voltage VDD1 and VSS1)
  • the output stage 206 and the operation unit 208 belong to the second power domain (corresponding to the reference voltage VDD2 and VSS2), wherein
  • the operating voltage of the second power domain is lower than the operating voltage of the first power domain, that is, the reference voltage VDD2 is lower than the reference voltage VDD1.
  • the present application is not limited thereto.
  • FIG. 4 is a schematic diagram of a second embodiment of the comparator proposed in this application.
  • the difference between the comparator 400 and the comparator 200 is that the comparator 400 additionally adds a replica gain stage 404 , and the structure of the replica gain stage 404 may be substantially the same as that of the gain stage 204 .
  • the replica gain stage 404 is used to provide gain to the signal S1 and output a signal S4.
  • the replica gain stage 404 includes a replica gain stage current source 4042 and a transistor M7, wherein the drain of the transistor M7 is coupled to the replica gain stage current source 4042, the gate of the transistor M7 is used to receive the signal S1, and the drain of the transistor M7 is also used to Output signal S4.
  • the main function of the replica gain stage 404 is to replace the gain stage 204 to provide signals to the operation unit 208 , so the AND gate 2082 in FIG. 4 performs an "AND" operation on the signal S4 and the signal S3 to obtain the signal Scmp.
  • the advantage of doing this is that the arithmetic unit 208 does not become the load of the gain stage 204, and the signal S3 output by the output stage 206 is avoided due to insufficient thrust of the signal S2.
  • the width-to-length ratio (W/L) of the channel of the transistor M7 is smaller than the width-to-length ratio of the channel of the transistor M5, which can suppress the ability of the transistor M7 to pull down the voltage, which is equivalent to enhancing the replication gain stage 404 Therefore, compared with signal S2, the time for signal S4 to climb from a low voltage level to a high voltage level can be slightly earlier than time point T2, so as to avoid the interval between time point T2 and time point T3. The time of the high voltage level of the output signal Scmp of the comparator is too short to ensure that the counting result of the counter 110 can be correctly latched by the latch 1064 .
  • FIG. 5 is a schematic diagram of a third embodiment of the comparator proposed in the present application.
  • the difference between the comparator 500 and the comparator 400 is that the replica gain stage 504 of the comparator 500 additionally includes a transistor M8 compared with the replica gain stage 404 .
  • the transistor M8 is used as a switch and the transistor M7 is connected in series, for example, the drain of the transistor M8 is coupled to the source of the transistor M7.
  • the gate of the transistor M8 is used to receive the enable signal EN.
  • the difference between the comparator 500 and the comparator 400 is that the operation unit 508 further includes a multiplexer 5084 for outputting the signal S3 or the signal S5 output by the AND gate 2082 as the comparator output signal Scmp according to the enable signal EN.
  • the comparator 500 can be switched between the normal mode and the power-saving mode.
  • the enable signal EN is 0, the transistor M8 is not turned on, and thus the replica gain stage 504 is turned off.
  • the multiplexer 5084 directly outputs the signal S3 output by the output stage 206 as the comparator output signal Scmp.
  • the enable signal EN is 1, and the transistor M8 is turned on, so that the replica gain stage 504 can work normally and output the signal S4.
  • the AND gate 2082 generates a signal S5 according to the signal S4 and the signal S3, and the multiplexer 5084 outputs the signal S5 as the comparator output signal Scmp according to the enable signal EN.
  • the present application also proposes an electronic device including an image sensor 100, wherein the image sensor 100 includes a comparator 200/400/500.
  • the electronic devices include but are not limited to mobile communication equipment, ultra-mobile personal computer equipment, portable entertainment equipment and other electronic equipment with data interaction functions.
  • the characteristic of mobile communication equipment is that it has mobile communication functions, and its main goal is to provide voice and data communication.
  • Such terminals include: smart phones (such as iPhone), multimedia phones, feature phones, and low-end phones.
  • Ultra-mobile personal computer devices belong to the category of personal computers, which have computing and processing functions, and generally have mobile Internet access features.
  • Such terminals include: PDA, MID and UMPC equipment, such as iPad.
  • Portable entertainment devices can display and play multimedia content.
  • Such devices include: audio and video players (such as iPod), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.
  • the latch 1064 is enabled only after the relationship between the ramp signal Vramp and the pixel output signal PXO changes. Therefore, unnecessary latch operation of the latch 1064 can be avoided, in other words, power consumption can be reduced. Moreover, the comparator 200/400/500 synthesizes the comparator output signal Scmp by referring to the output signal of the gain stage 204 or the replica gain stage 404/504, which can reduce the cost and the delay time of the comparator output signal Scmp as much as possible.

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Abstract

一种比较器（200, 400, 500）、相关图像传感器（100）及电子装置。该比较器（200, 400, 500）用来依据斜坡信号以及像素输出信号产生比较器输出信号，包括：输入级（202），接收该斜坡信号以及该像素输出信号，当该斜坡信号由大于该像素输出信号改变为小于该像素输出信号，或该斜坡信号由小于该像素输出信号改变为大于该像素输出信号时，该输入级输出的第一信号由第一电压电平转变为第二电压电平；增益级（204），用来对该第一信号提供增益并输出第二信号；输出级（206），用来依据该第二信号输出第三信号；以及运算单元（208, 508），用来依据该第二信号以及该第三信号输出该比较器输出信号。

Description

比较器及相关图像传感器及电子装置 技术领域
本申请涉及一种电路，尤其涉及一种比较器及相关图像传感器及电子装置。
背景技术
随着技术的进步，CMOS图像传感器除了需具备大规模像素阵列，同时还要求具备高的信号处理速度，但随着像素阵列规模的增大，像素阵列中单个像素的尺寸却在不断缩小，导致单个模数转换电路设计难以实现，基于列的模数转换电路便因此产生。然而，现有的用于CMOS图像传感器的列模数转换电路因为要随时读取计数器的值，高耗电量是一个为人诟病的问题，因此如何解决上述问题，已成为本领域亟需解决的问题之一。
发明内容
本申请的目的之一在于公开一种比较器及相关图像传感器及电子装置，来解决上述问题。
本申请的一实施例公开了一种比较器，用来依据斜坡信号以及像素输出信号产生比较器输出信号，包括：输入级，接收所述斜坡信号以及所述像素输出信号，当所述斜坡信号由大于所述像素输出信号改变为小于所述像素输出信号，或所述斜坡信号由小于所述像素输出信号改变为大于所述像素输出信号时，所述输入级输出的第一信号由第一电压电平转变为第二电压电平；增益级，用来对所述第一信号提供增益并输出第二信号；输出级，用来依据所述第二信号输出第三信号；以及运算单元，用来依据所述第二信号以及所述第三信号输出所述比较器输出信号。
本申请的一实施例公开了一种比较器，用来依据斜坡信号以及像素输出信号产生比较器输出信号，包括：输入级，接收所述斜坡信号以及所述像素输出信号，当所述斜坡信号由大于所述像素输出信号改变为小于所述像素输出信号，或所述斜坡信号由小于所述像素输出信号改变为大于所述像素输出信号时，所述输入级输出的第一信号由第一电压电平转变为第二电压电平；增益级，用来对所述第一信号提供增益并输出第二信号；输出级，用来依据所述第二信号输出第三信号；复制增益级，用来对所述第一信号提供增益并输出第四信号；以及运算单元，用来依据所述第四信号以及所述第三信号输出所述比较器输出信号。
本申请的一实施例公开了一种图像传感器，包括：像素阵列，包括至少一像素列；模拟数字转换单元，包括：上述的比较器，耦接所述至少一像素列；以及至少一锁存器，耦接所述至少一比较器；行解码器，用来控制所述至少一像素列输出所述像素输出信号；斜坡信号发生电路，用来产生所述斜坡信号；以及计数器，用来进行计数操作并输出计数结果；其中所述至少一比较器产生所述比较器输出信号以控制所述至少一锁存器的使能时间，所述至少一锁存器在被使能时，持续地锁存所述计数器的所述计数结果。
本申请的一实施例公开了一种电子装置，包括：上述的图像传感器。
本申请的比较器及相关图像传感器及电子装置可降低图像传感器中的列模数转换器的功耗。
附图说明
图1为图像传感器的实施例的示意图。
图2为本申请提出的比较器的第一实施例的示意图。
图3为本申请的比较器的操作时序图。
图4为本申请提出的比较器的第二实施例的示意图。
图5为本申请提出的比较器的第三实施例的示意图。
具体实施方式
以下揭示内容提供了多种实施方式或例示，其能用以实现本揭示内容的不同特征。下文所述之组件与配置的具体例子系用以简化本揭示内容。当可想见，这些叙述仅为例示，其本意并非用于限制本揭示内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本揭示内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比例及其他相似者)均经过「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
图1为图像传感器的实施例的示意图。图像传感器100包括像素阵列102、模拟数字转换单元106、行解码器104、斜坡信号发生电路108以及计数器110。像素阵列102包括多列像素列以及多行一像素行，模拟数字转换单元106包括多列模数转换电路对应地耦接到多列像素列，其中各列模数转换电路皆包括比较器以及锁存器。应注意的是，图1中绘示了多列像素列以及多列模数转换电路仅为示意用途，本申请不以此为限，实际上图像传感器100也可以仅包含一列像素列以及一列模数转换电路。
行解码器104用来控制像素阵列102中的各像素列输出像素输出信号，计数器110用来进行计数操作并输出计数结果。以像素阵列102的最左边的像素列以及模数转换电路中的比较器1062和锁存器1064为例，输出的像素输出信号PXO以及斜坡信号发生电路108产生的斜坡信号Vramp会通过比较器1062进行比较，并输出比较器输出信号Scmp来控制锁存器1064的使能时间。因为锁存器1064只有在被使能时，才会持续地锁存计数器110的所述计数结果。本申请提出的比较器的实施例，可以在不影响图像传感器100的效能的情况下，通过降低锁存器1064的使能时间来降低列模数转换器的功耗。其细节说明如下。
图2为本申请提出的比较器的第一实施例的示意图。比较器200用来依据斜坡信号Vramp以及像素输出信号PXO产生比较器输出信号Scmp，比较器200可用于实现图1的全部或部分的比较器。比较器200包括输入级202、增益级204、输出级206以及运算单元208。
请一并参阅图3，图3为本申请的比较器的操作时序图。具体来说，输入级202作为差动放大器并用来接收斜坡信号Vramp以及像素输出信号PXO，当斜坡信号Vramp由大于像素输出信号PXO改变为小于像素输出信号PXO时(时间点T0，未标示于图中)，会触发输入级202的输出信号S1在时间点T1由高电压电平落至低电压电平，时间点T1会稍晚于时间点T0。
输入级202包括输入级电流源2022、晶体管M1、晶体管M2、 晶体管M3以及晶体管M4以构成差动放大器，其中晶体管M1的源极耦接至输入级电流源2022，晶体管M1的栅极用来接收斜坡信号Vramp。晶体管M2的源极耦接至输入级电流源2022，晶体管M2的栅极用来接收像素输出信号PXO，晶体管M2的漏极用来输出信号S1。晶体管M3的漏极和栅极彼此耦接，晶体管M3的漏极还耦接至晶体管M1的漏极。晶体管M4的栅极耦接晶体管M3的栅极，晶体管M3的漏极还耦接至晶体管M2的漏极。
由于差动放大器的其他可能实施方式和变化繁多，在此不多做赘述，且本申请的输入级202的实施方式不以图2为限。此外，图3的操作时序图也可能通过调整得到不同的态样，但应仍属本申请的范围。例如斜坡信号Vramp可以是由下往上，使得当斜坡信号Vramp由小于像素输出信号PXO改变为大于所述像素输出信号时，输入级202输出的信号S1由低电压电平爬升至高电压电平。
增益级204用来对信号S1提供增益并输出信号S2。增益级204包括增益级电流源2042以及晶体管M5，其中晶体管M5的漏极耦接至增益级电流源2042，晶体管M5的栅极用来接收信号S1，晶体管M5的漏极还用来输出信号S2。如图3所示，当信号S1在时间点T1由高电压电平降为低电压电平，增益级204输出的信号S2会在时间点T2由低电压电平爬升为高电压电平，时间点T2会稍晚于时间点T1。应注意的是，本申请的增益级204的实施方式不以图2为限。
输出级206用来依据信号S2输出信号S3。输出级206包括输出级电流源2062以及晶体管M6，其中晶体管M6的漏极耦接至输出级电流源2062，晶体管M6的栅极用来接收信号S2，晶体管M6的漏极还用来输出信号S3。如图3所示，当信号S2在时间点T2由低电压电平爬升为高电压电平，输出级206輸出的信号S3会在时间点T3由高电压电平落至低电压电平，时间点T3会稍晚于时间点T2。应注意的是，本申请的输出级206的实施方式不以图2为限。
运算单元208用来依据信号S2以及信号S3输出比较器输出信号Scmp。在本实施例中，运算单元208包括与门2082，与门2082用来 对信号S2以及信号S3进行“与”操作以得到信号Scmp。如图3所示，信号Scmp在时间点T2和时间点T3之间为高电压电平，其余时间为低电压电平。应注意的是，为方便说明，图3中的时序图不考虑与门2082的延迟时间。
对锁存器1064来说，只需锁存到信号Scmp的值发生改变的那一刻的计数器器110的计数结果，因此，本申请的比较器200当应用在图1的比较器1062时，仅会在斜坡信号Vramp和像素输出信号PXO的关系改变之后才使能锁存器1064，具体来说，仅在时间点T2和时间点T3之间使能锁存器1064，而不需要固定地在斜坡信号Vramp和像素输出信号PXO的关系改变之前(例如时间点Tz)就使能锁存器1064。因此，可以避免锁存器1064进行不必要的锁存操作，换句话说，可降低列模数转换器的功耗。
在本实施例中，输入级202以及增益级204属于第一电源域(对应参考电压VDD1以及VSS1)，输出级206和运算单元208属于第二电源域(对应参考电压VDD2以及VSS2)，其中所述第二电源域的操作电压低于所述第一电源域的操作电压，即参考电压VDD2低于参考电压VDD1。但本申请不以此为限。
图4为本申请提出的比较器的第二实施例的示意图。比较器400和比较器200的差异在于，比较器400额外增加了复制增益级404，复制增益级404的结构可以和增益级204大致相同。具体来说，复制增益级404用来对信号S1提供增益并输出信号S4。复制增益级404包括复制增益级电流源4042以及晶体管M7，其中晶体管M7的漏极耦接至复制增益级电流源4042，晶体管M7的栅极用来接收信号S1，晶体管M7的漏极还用来输出信号S4。
复制增益级404主要的功能是取代增益级204来提供信号至运算单元208，因此图4的与门2082对信号S4以及信号S3进行“与”操作以得到信号Scmp。这样做的好处在于可以让运算单元208不成为增益级204的负载，避免因信号S2的推力不足而影响输出级206输出的信号S3。
在本实施例中，晶体管M7的通道的宽长比(W/L)小于晶体管M5的通道的宽长比，这样可以抑制晶体管M7把电压往下拉的能力，等效上就是增强复制增益级404把电压往上抬的能力，因此信号S4相较于信号S2，由低电压电平爬升为高电压电平的时间可以稍早于时间点T2，以避免时间点T2和时间点T3的间隔过小造成比较器输出信号Scmp的高电压电平的时间太短，这样更加能够确保锁存器1064正确地锁存计数器110的所述计数结果。
图5为本申请提出的比较器的第三实施例的示意图。比较器500和比较器400的差异在于，比较器500的复制增益级504相较于复制增益级404还额外包括晶体管M8。具体来说，利用晶体管M8做为开关并串接晶体管M7，例如将晶体管M8的漏极耦接至晶体管M7的源极。晶体管M8的栅极用来接收使能信号EN。此外，比较器500和比较器400的差异还在于运算单元508还包括复用器5084，用来依据使能信号EN将信号S3或与门2082输出的信号S5输出为比较器输出信号Scmp。
比较器500可在一般模式和省电模式之间切换，例如在一般模式下，使能信号EN为0，晶体管M8不导通，因此使复制增益级504被关闭。此时复用器5084直接将输出级206输出的信号S3输出为比较器输出信号Scmp。在省电模式下，使能信号EN为1，晶体管M8导通，因此使复制增益级504可正常工作并输出信号S4。与门2082依据信号S4和信号S3产生信号S5，复用器5084依据使能信号EN将信号S5输出为比较器输出信号Scmp。
本申请还提出一种包含图像传感器100的电子装置，其中图像传感器100包含比较器200/400/500。具体的，所述电子装置包括但不限于移动通信设备、超移动个人计算机设备、便携式娱乐设备和其他具有数据交互功能的电子设备。移动通信设备的特点是具备移动通信功能，并且以提供话音、数据通信为主要目标。这类终端包括：智能手机(例如iPhone)、多媒体手机、功能性手机，以及低端手机等。超移动个人计算机设备属于个人计算机的范畴，有计算和处理功能，一 般也具备移动上网特性。这类终端包括：PDA、MID和UMPC设备等，例如iPad。便携式娱乐设备可以显示和播放多媒体内容。该类设备包括：音频、视频播放器(例如iPod)，掌上游戏机，电子书，以及智能玩具和便携式车载导航设备。
当本申请的比较器200/400/500应用在图1的比较器1062时，仅会在斜坡信号Vramp和像素输出信号PXO的关系改变之后才使能锁存器1064。因此，可以避免锁存器1064进行不必要的锁存操作，换句话说，可降低功耗。且比较器200/400/500参考增益级204或复制增益级404/504输出的信号来合成比较器输出信号Scmp，可以尽量地降低成本以及比较器输出信号Scmp的延迟时间。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本申请所属技术领域具有通常知识者能够更全面地理解本揭示内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本揭示内容作为基础，来设计或更动其他工艺与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本揭示内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本揭示内容之精神与范围。

Claims (19)

  1. 一种比较器，用来依据斜坡信号以及像素输出信号产生比较器输出信号，其特征在于，包括：
    输入级，接收所述斜坡信号以及所述像素输出信号，当所述斜坡信号由大于所述像素输出信号改变为小于所述像素输出信号，或所述斜坡信号由小于所述像素输出信号改变为大于所述像素输出信号时，所述输入级输出的第一信号由第一电压电平转变为第二电压电平；
    增益级，用来对所述第一信号提供增益并输出第二信号；
    输出级，用来依据所述第二信号输出第三信号；以及
    运算单元，用来依据所述第二信号以及所述第三信号输出所述比较器输出信号。
  2. 如权利要求1所述的比较器，其特征在于，所述输入级包括差分放大器。
  3. 如权利要求2所述的比较器，其特征在于，所述差分放大器包括:
    输入级电流源；
    第一晶体管，所述第一晶体管的源极耦接至所述输入级电流源，所述第一晶体管的栅极用来接收所述斜坡信号；
    第二晶体管，所述第二晶体管的源极耦接至所述输入级电流源，所述第二晶体管的栅极用来接收所述像素输出信号，所述第二晶体管的漏极用来输出所述第一信号；
    第三晶体管，所述第三晶体管的漏极和栅极彼此耦接，所述第三晶体管的漏极还耦接至所述第一晶体管的漏极；以及
    第四晶体管，所述第四晶体管的栅极耦接所述第三晶体管的栅极，所述第三晶体管的漏极还耦接至所述第二晶体管的漏极。
  4. 如权利要求1所述的比较器，其特征在于，所述增益级包括:
    增益级电流源；
    第五晶体管，所述第五晶体管的漏极耦接至所述增益级电流源，所述第五晶体管的栅极用来接收所述第一信号，所述第五晶体管的漏极用来输出所述第二信号。
  5. 如权利要求1所述的比较器，其特征在于，所述输出级包括:
    输出级电流源；
    第六晶体管，所述第六晶体管的漏极耦接至所述输出级电流源，所述第六晶体管的栅极用来接收所述第二信号，所述第六晶体管的漏极用来输出所述第三信号。
  6. 如权利要求1所述的比较器，其特征在于，所述输入级以及所述增益级属于第一电源域，所述输出级和所述运算单元属于第二电源域，其中所述第二电源域的操作电压低于所述第一电源域的操作电压。
  7. 如权利要求1至6中任一项所述的比较器，其特征在于，所述运算单元包括：
    与门，用来依据所述第二信号以及所述第三信号产生所述比较器输出信号。
  8. 一种比较器，用来依据斜坡信号以及像素输出信号产生比较器输出信号，其特征在于，包括：
    输入级，接收所述斜坡信号以及所述像素输出信号，当所述斜坡信号由大于所述像素输出信号改变为小于所述像素输出信号，或所述斜坡信号由小于所述像素输出信号改变为大于所述像素输出信号时，所述输入级输出的第一信号由第一电压电平转变为第二电压电平；
    增益级，用来对所述第一信号提供增益并输出第二信号；
    输出级，用来依据所述第二信号输出第三信号；
    复制增益级，用来对所述第一信号提供增益并输出第四信号；以及
    运算单元，用来依据所述第四信号以及所述第三信号输出所述比较器输出信号。
  9. 如权利要求8所述的比较器，其特征在于，所述输入级包括差分放大器。
  10. 如权利要求9所述的比较器，其特征在于，所述差分放大器包括:
    输入级电流源；
    第一晶体管，所述第一晶体管的源极耦接至所述输入级电流源，所述第一晶体管的栅极用来接收所述斜坡信号；
    第二晶体管，所述第二晶体管的源极耦接至所述输入级电流源，所述第二晶体管的栅极用来接收所述像素输出信号，所述第二晶体管的漏极用来输出所述第一信号；
    第三晶体管，所述第三晶体管的漏极和栅极彼此耦接，所述第三晶体管的漏极还耦接至所述第一晶体管的漏极；以及
    第四晶体管，所述第四晶体管的栅极耦接所述第三晶体管的栅极，所述第三晶体管的漏极还耦接至所述第二晶体管的漏极。
  11. 如权利要求8所述的比较器，其特征在于，所述增益级包括:
    增益级电流源；
    第五晶体管，所述第五晶体管的漏极耦接至所述增益级电流源，所述第五晶体管的栅极用来接收所述第一信号，所述第五晶体管的漏极用来输出所述第二信号。
  12. 如权利要求8所述的比较器，其特征在于，所述输出级包括:
    输出级电流源；
    第六晶体管，所述第六晶体管的漏极耦接至所述输出级电流源，所述第六晶体管的栅极用来接收所述第二信号，所述第六晶体管的漏极用来输出所述第三信号。
  13. 如权利要求11所述的比较器，其特征在于，所述复制增益级包括:
    复制增益级电流源；
    第七晶体管，所述第七晶体管的漏极耦接至所述复制增益级电流源，所述第七晶体管的栅极用来接收所述第一信号，所述第七晶体管的漏极用来输出所述第四信号。
  14. 如权利要求8所述的比较器，其特征在于，所述输入级、所述增益级以及所述复制增益级属于第一电源域，所述输出级和所述运算单元属于第二电源域，其中所述第二电源域的操作电压低于所 述第一电源域的操作电压。
  15. 如权利要求13所述的比较器，其特征在于，所述第七晶体管的通道的宽长比小于所述第五晶体管的通道的宽长比。
  16. 如权利要求8至15中任一项所述的比较器，其特征在于，所述运算单元包括：
    与门，用来依据所述第四信号以及所述第三信号产生所述比较器输出信号。
  17. 如权利要求13所述的比较器，其特征在于，所述复制增益级还包括:
    第八晶体管，所述第八晶体管的栅极用来接收使能信号，所述第八晶体管的漏极耦接至所述第七晶体管的源极；以及
    所述运算单元包括：
    与门，用来依据所述第四信号以及所述第三信号产生第五信号；以及
    复用器，用来依据所述使能信号将所述第三信号或所述第五信号输出为所述比较器输出信号。
  18. 一种图像传感器，其特征在于，包括：
    像素阵列，包括至少一像素列；
    模拟数字转换单元，包括：
    至少一如权利要求1至17中任一项所述的比较器，耦接所述至少一像素列；以及
    至少一锁存器，耦接所述至少一比较器；
    行解码器，用来控制所述至少一像素列输出所述像素输出信号；
    斜坡信号发生电路，用来产生所述斜坡信号；以及
    计数器，用来进行计数操作并输出计数结果；
    其中所述至少一比较器产生所述比较器输出信号以控制所述至少一锁存器的使能时间，所述至少一锁存器在被使能时，持续地锁存所述计数器的所述计数结果。
  19. 一种电子装置，其特征在于，包括：
    如权利要求18所述的图像传感器。
PCT/CN2021/119093 2021-09-17 2021-09-17 比较器及相关图像传感器及电子装置 WO2023039840A1 (zh)

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