WO2023035427A1 - 基于fifo存储器的信息生成方法、装置、设备及介质 - Google Patents

基于fifo存储器的信息生成方法、装置、设备及介质 Download PDF

Info

Publication number
WO2023035427A1
WO2023035427A1 PCT/CN2021/134434 CN2021134434W WO2023035427A1 WO 2023035427 A1 WO2023035427 A1 WO 2023035427A1 CN 2021134434 W CN2021134434 W CN 2021134434W WO 2023035427 A1 WO2023035427 A1 WO 2023035427A1
Authority
WO
WIPO (PCT)
Prior art keywords
read
write
enable signal
credit
data enable
Prior art date
Application number
PCT/CN2021/134434
Other languages
English (en)
French (fr)
Inventor
孙旭
杨萌
宋琪
Original Assignee
苏州浪潮智能科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州浪潮智能科技有限公司 filed Critical 苏州浪潮智能科技有限公司
Priority to US18/256,355 priority Critical patent/US20240020246A1/en
Publication of WO2023035427A1 publication Critical patent/WO2023035427A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order

Definitions

  • the present application relates to the technical field of data storage, and more specifically, to an information generation method, device, device and medium based on a FIFO memory.
  • FIFO First Input First Output, first-in-first-out
  • FIFO memory is the buffer link of the system. It mainly has the following functions: 1. Cache the continuous data stream to prevent data loss during loading and storage operations; Avoid frequent bus operations and reduce the burden on the CPU (central processing unit, central processing unit); 3. Allow the system to perform DMA (Direct Memory Access, direct memory access) operations to improve data transmission speed.
  • DMA Direct Memory Access, direct memory access
  • the depth of the current synchronous FIFO memory is 128, the data bit width is 8bit, and the front-end device of the FIFO memory is a DDR (Double Data Rate, double-rate synchronous dynamic random access memory) controller or PCIe (peripheral component interconnect express, high-speed serial Line computer expansion bus standard machine memory), DDR controller or PCIe when sending data packets to the FIFO memory, because the front-end data is sent continuously, so when the data starts to be sent, no matter whether there is space in the back-stage FIFO memory to store Data, the data must be sent continuously from the front stage to the back stage.
  • DDR Double Data Rate, double-rate synchronous dynamic random access memory
  • PCIe peripheral component interconnect express, high-speed serial Line computer expansion bus standard machine memory
  • the general way to solve this problem is to judge the empty state of the FIFO memory at present, and start writing data when the FIFO memory is empty, and the data space that can be written at this moment is the capacity of the FIFO memory itself.
  • the FIFO memory When the FIFO memory is called, it will ensure that its data space is not less than the data size of one continuous write of the previous stage.
  • there is a big waste of efficiency in this method For example: currently 64 pieces of data with a data bit width of 8bit are cached in the FIFO memory. You can only wait for the FIFO to be read empty, that is, when the empty state signal is 1, you can read it, because the empty and full indication signal cannot judge how much data has been stored in the FIFO. It can be seen that the use of the FIFO memory is reduced in this way. efficiency.
  • the purpose of the present application is to provide a method, device, device and medium for generating information based on FIFO memory, so as to improve the use efficiency of FIFO memory.
  • the present application provides a method for generating information based on FIFO memory, including:
  • the write credit represents the number of data groups that can be normally written into the FIFO memory
  • the read credit represents the number of data groups that the FIFO memory can normally read
  • the use of the total capacity of the FIFO memory, the read address, the write address, the read data enable signal value, and the write data enable signal value determines the current write credit of the FIFO memory Points and reading credits, including:
  • the determining the write credit points according to the read address, the write address, the read data enable signal value, the write data enable signal value and the first determination rule includes:
  • the determining the write credit points according to the total capacity, the read address, the write address, the read data enable signal value, the write data enable signal value and the second determination rule includes:
  • the determining the read credit points according to the total capacity, the read address, the write address, the read data enable signal value, the write data enable signal value and the third determination rule includes:
  • the determining the read credit points according to the read address, the write address, the read data enable signal value, the write data enable signal value and the fourth determination rule includes:
  • the sending the writing credit points and the reading credit points to the front-end equipment includes:
  • the unit value is used to represent the number of bytes of data in each data group;
  • the write credit and the read credit based on each unit value are determined, and the write credit and the read credit based on each unit value are transmitted to the preceding device.
  • the determination is based on write credits and read credits for each unit value, including:
  • the present application further provides an information generation device based on FIFO memory, including:
  • the first obtaining module is used to obtain the read address and write address of the current FIFO memory
  • the second obtaining module is used to obtain the read data enable signal value and the write data enable signal value of the current FIFO memory
  • a determining module configured to use the total capacity of the FIFO memory, the read address, the write address, the value of the read data enable signal, and the value of the write data enable signal to determine the current writing capacity of the FIFO memory Credit points and read credit points; the write credit points represent the number of data groups that can be normally written into the FIFO memory; the read credit points represent the number of data groups that the FIFO memory can normally read;
  • a sending module configured to send the write credits and the read credits to a front-end device, so that the front-end device reads and writes data according to the write credits and the read credits.
  • an electronic device including:
  • the processor is configured to realize the steps of the above-mentioned FIFO memory-based information generation method when executing the computer program.
  • the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned information generation method based on FIFO memory are realized .
  • the information generation method, device, device and medium based on the FIFO memory will use the total capacity of the FIFO memory, the read address, write address, read data enable signal value and The write data enable signal value determines the write credit and read credit of the current FIFO memory; the write credit represents the number of data groups that can be normally written into the FIFO memory; the read credit represents the data that the FIFO memory can normally read The number of groups; after sending the write credits and read credits to the front-end device, the front-end device can know the number of data groups that can be written and read normally in the current FIFO memory according to the write credits and read credits, and Read and write data according to write credits and read credits, realize system flow control, ensure that data does not overflow or block, and improve the use efficiency of FIFO memory.
  • FIG. 1 is a schematic structural diagram of an information generation system based on a FIFO memory disclosed in an embodiment of the present application;
  • FIG. 2 is a schematic flowchart of a method for generating information based on a FIFO memory disclosed in an embodiment of the present application;
  • FIG. 3 is a schematic structural diagram of an information generating device based on a FIFO memory disclosed in an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of an electronic product disclosed in an embodiment of the present application.
  • FIG. 1 it is a schematic structural diagram of an information generation system based on a FIFO memory disclosed in an embodiment of the present application.
  • the synchronous FIFO module can be divided into the following parts in hardware implementation: write address generation module Wr_addr, read address generation module Rd_addr, storage module Memory, credit point generation module Credit, and generate FIFO empty signal module through credit points Cr_empty, generate FIFO full signal module Cr_full through credit points. See Table 1 for a description of the interface signals of the synchronous FIFO module:
  • Write address generation module Wr_addr This module generates an address for writing data into the storage module according to the input write enable wr_en signal. After the reset is completed, the write address is 0. When wr_en is high, write data into the current Memory address, and at the same time add 1 to the write address as the data address for the next write. It is automatically cleared when the write address reaches the maximum value.
  • Read address generation module rd_addr This module generates an address for reading data from the storage module according to the input read enable rd_en signal. After reset, the read address is 0. When rd_en is high, the current read Memory address is given to the read address of the subsequent storage module, and at the same time the read address is increased by 1 as the address of the next read data. It is automatically cleared when the read address reaches the maximum value.
  • This module is to call or generate a synchronous dual-port static random access memory, which can be RAM memory (Random Access Memory, random access memory).
  • FIFO empty signal module Cr_empty through credit points This module generates an empty state signal or an almost empty state signal according to the write credit points and read credit points calculated by the credit point generation module Credit;
  • FIG. 2 a schematic flowchart of a method for generating information based on a FIFO memory provided in an embodiment of the present application, the method includes:
  • the read address and read data enable signal value are obtained from the read address generation module rd_addr, and the write address and write data enable signal value are obtained from the write address generation module Wr_addr.
  • the value of the read data enable signal is determined according to the read data enable signal rd_en, if the received data enable signal rd_en is high, the value of the read data enable signal is 1, otherwise it is 0; similarly, the write data enable signal The enable signal value is determined according to the write data enable signal wr_en, if the write data enable signal wr_en is received as high, the write data enable signal value is 1, otherwise it is 0.
  • the write address is greater than the read address.
  • the newly written data will re-cover the written address, and the write address will change from Starting from the initial address, there will be a situation where the read address is greater than the write address. Therefore, in this embodiment, for the determination process of writing credit points and reading credit points, these two situations are fully considered.
  • the present embodiment determines the process of writing the credit points of the current FIFO memory as:
  • the second determination rule is to determine the write credit points.
  • the present embodiment determines the process of reading the credit points of the current FIFO memory as:
  • S104 Send the write credit score and the read credit score to the front-end device, so that the front-end device reads and writes data according to the write credit score and the read credit score.
  • the credit mechanism is a method of controlling data flow.
  • the write credits in this solution represent the number of data groups that can be written normally in this synchronous FIFO, and the read credits represent that the synchronous FIFO can be read normally.
  • the number of data groups, the subsequent stage feeds back the number of data that it can receive or send to the superior in real time or regularly, so as to realize the flow control of the entire system and ensure that the data does not overflow or block.
  • the unit of the data group in this scheme is different. If the unit value of the data group is 1Byte, then this scheme is represented by the suffix of credit_1.
  • the unit value of the data group is 4Byte/16Byte, and the suffix of credit_4/credit_16 is used Indicates that at the same time, this solution also supports users to customize the data size according to the usage requirements, which is indicated by the credit_user suffix.
  • this program sends the write credit points and read credit points to the front-end equipment, it is necessary to determine the unit value of the data group; the unit value is used to represent the number of bytes of data in each data group; and then determine based on each unit value Write credits and read credits, and send the write credits and read credits based on each unit value to the front-end device.
  • the ratio of the writing credit points to each unit value is calculated, and the ratio is rounded down to obtain the writing credit points based on each unit value. Calculate the ratio of the reading credit score to each unit value, and round down the ratio to obtain the reading credit score based on each unit value.
  • wr_credit_1 fifo_capa - wr_addr + rd_addr + rd_en - wr_en.
  • wr_credit_1 rd_addr - wr_addr + rd_en - wr_en.
  • the wr_credit_1 calculated at this time is based on the writing credit score with a unit value of 1.
  • Other writing credit points are calculated as follows:
  • wr_credit_4 wr_credit_1/4, rounded down;
  • wr_credit_16 wr_credit_1/16, rounded down;
  • wr_credit_user wr_credit_1/wr_credit_user, rounded down.
  • rd_credit_1 wr_addr-rd_addr-rd_en+wr_en;
  • rd_credit_1 fifo_capa + wr_addr - rd_addr - rd_en + wr_en.
  • the rd_credit_1 calculated at this time is based on the reading credit score with a unit value of 1.
  • Other reading credit scores are calculated as follows:
  • rd_credit_4 rd_credit_1/4, rounded down;
  • rd_credit_16 rd_credit_1/16, rounded down;
  • rd_credit_user rd_credit_1/wr_credit_user, rounded down.
  • this solution essentially provides a synchronous FIFO memory with a credit mechanism interface, and the read and write ends generate independent credit points and support user-defined credit points.
  • the empty and almost empty signals of the FIFO memory can be generated by reading the credits, and the full and almost full signals of the FIFO memory can be generated by writing the credits.
  • the front-end equipment can directly know how many sets of data can be read and written to the FIFO memory through reading and writing credit points, without the need for separate calculations on external devices, which simplifies the calculation process of external interface signals, and can also directly communicate with PCIe and other support credits.
  • the system connection of the mechanism improves the reusability and reliability of the synchronous FIFO module, thereby improving the development efficiency of the entire SOC (System on Chip, system on a chip), thereby improving product competitiveness.
  • the information generating apparatus, equipment, and medium provided in the embodiments of the present application are introduced below, and the information generating apparatus, equipment, and medium described below and the information generating method described above may refer to each other.
  • a schematic structural diagram of an information generation device based on a FIFO memory provided by an embodiment of the present application includes:
  • the first obtaining module 11 is used to obtain the read address and write address of the current FIFO memory
  • the second obtaining module 12 is used to obtain the read data enable signal value and the write data enable signal value of the current FIFO memory;
  • Determining module 13 for using the total capacity of the FIFO memory and the read address, the write address, the read data enable signal value, the write data enable signal value, to determine the current FIFO memory Write credits and read credits;
  • the write credits represent the number of data groups that can be normally written into the FIFO memory;
  • the read credits represent the number of data groups that the FIFO memory can normally read;
  • the sending module 14 is configured to send the write credits and the read credits to the front-end equipment, so that the front-end equipment can read and write data according to the write credits and the read credits.
  • the determination module includes:
  • the first judging unit is used to judge whether the write address is smaller than the read address; if so, trigger the first determining unit; if not, trigger the second determining unit;
  • the first determining unit is configured to determine write credit points according to the read address, the write address, the value of the read data enable signal, the value of the write data enable signal, and a first determination rule;
  • the second determination unit is configured to determine write credit points according to the total capacity, the read address, the write address, the read data enable signal value, the write data enable signal value, and a second determination rule;
  • the second judging unit is used to judge whether the write address is smaller than the read address; if so, trigger the third determining unit, and if not, trigger the fourth determining unit;
  • the third determination unit is configured to determine the read credit according to the total capacity, the read address, the write address, the read data enable signal value, the write data enable signal value, and a third determination rule;
  • the fourth determining unit is configured to determine the read credit according to the read address, the write address, the value of the read data enable signal, the value of the write data enable signal, and a fourth determination rule.
  • the first determination unit is specifically used for:
  • described first determination rule is:
  • the second determining unit is specifically configured to:
  • described second determination rule is:
  • Write credit total capacity - write address + read address + read data enable signal value - write data enable signal value.
  • the third determination unit is specifically used for:
  • the third determination rule is:
  • Read credit total capacity + write address - read address - read data enable signal value + write data enable signal value;
  • the fourth determining unit is specifically configured to:
  • the fourth determination rule is:
  • Read credit write address - read address - read data enable signal value + write data enable signal value.
  • the device also includes:
  • a first signal generating module configured to generate an empty state signal of 1 when the read credit is 0, and generate an almost empty state signal of 1 when the read credit is 1;
  • the second signal generating module is configured to generate a full state signal of 1 when the write credit score is 0, and generate an almost full state signal of 1 when the write credit score is 1.
  • the sending module includes:
  • the fifth determination unit is used to determine the unit value of the data group; the unit value is used to represent the number of bytes of data in each data group;
  • the sixth determining unit is used to determine the writing credit points and reading credit points based on each unit value
  • a sending unit for sending the write credit and the read credit based on each unit value to the preceding device.
  • the sixth determination unit includes:
  • the first calculation subunit is used to calculate the ratio of the writing credit points to each unit value, and round down the ratio to obtain the writing credit points based on each unit value;
  • the second calculation subunit is used to calculate the ratio of the read credit points to each unit value, and round down the ratio to obtain the read credit points based on each unit value.
  • FIG. 4 it is a schematic structural diagram of an electronic device provided in an embodiment of the present application, including:
  • Memory 21 used to store computer programs
  • the processor 22 is configured to implement the steps of the method for generating information based on the FIFO memory described in the above embodiments when executing the computer program.
  • the device may be a PC (Personal Computer, personal computer), or may be a terminal device such as a smart phone, a tablet computer, a palmtop computer, or a portable computer.
  • PC Personal Computer
  • terminal device such as a smart phone, a tablet computer, a palmtop computer, or a portable computer.
  • the device may include a memory 21 , a processor 22 and a bus 23 .
  • the memory 21 includes at least one type of readable storage medium, and the readable storage medium includes flash memory, hard disk, multimedia card, card type memory (for example, SD or DX memory, etc.), magnetic memory, magnetic disk, optical disk, etc.
  • the storage 21 may be an internal storage unit of the device in some embodiments, such as a hard disk of the device.
  • Memory 21 may also be an external storage device of the device in other embodiments, such as a plug-in hard disk equipped on the device, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash memory card (Flash Card) etc.
  • the memory 21 may also include both an internal storage unit of the device and an external storage device.
  • the memory 21 can not only be used to store application software and various data installed in the device, such as program codes for executing the information generating method, but also can be used to temporarily store outputted or to-be-outputted data.
  • Processor 22 can be a central processing unit (Central Processing Unit, CPU), controller, microcontroller, microprocessor or other data processing chip in some embodiments, is used for running the program code stored in memory 21 or processing Data, such as program codes for executing information generation methods, etc.
  • CPU Central Processing Unit
  • controller microcontroller
  • microprocessor or other data processing chip in some embodiments, is used for running the program code stored in memory 21 or processing Data, such as program codes for executing information generation methods, etc.
  • the bus 23 may be a peripheral component interconnect standard (PCI for short) bus or an extended industry standard architecture (EISA for short) bus or the like.
  • PCI peripheral component interconnect standard
  • EISA extended industry standard architecture
  • the bus can be divided into address bus, data bus, control bus and so on. For ease of representation, only one thick line is used in FIG. 4 , but it does not mean that there is only one bus or one type of bus.
  • the device can also include a network interface 24, and the network interface 24 can optionally include a wired interface and/or a wireless interface (such as a WI-FI interface, a bluetooth interface, etc.), which are usually used for communication between the device and other electronic devices Establish a communication connection.
  • a network interface 24 can optionally include a wired interface and/or a wireless interface (such as a WI-FI interface, a bluetooth interface, etc.), which are usually used for communication between the device and other electronic devices Establish a communication connection.
  • the device may further include a user interface 25, which may include a display (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 25 may also include a standard wired interface and a wireless interface.
  • the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode, organic light-emitting diode) touch device, and the like.
  • the display may also be properly referred to as a display screen or a display unit, and is used for displaying information processed in the device and for displaying a visualized user interface.
  • FIG. 4 only shows a device with components 21-25. Those skilled in the art can understand that the structure shown in FIG. 4 does not constitute a limitation to the device, and may include fewer or more components than those shown in the figure. Or combine certain components, or different component arrangements.
  • the embodiment of the present application also provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the information based on the FIFO memory described in the above-mentioned embodiments is realized. The steps to generate the method.
  • the storage medium may include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk, etc., which can store program codes. medium.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

一种基于FIFO存储器的信息生成方法、装置、设备及介质；在该方法、装置、设备及介质中，会利用FIFO存储器的总容量、当前FIFO存储器的读地址、写地址、读数据使能信号值及写数据使能信号值，确定当前FIFO存储器的写信用积分及读信用积分；该写信用积分代表FIFO存储器能正常写入的数据组的数量；该读信用积分代表FIFO存储器能正常读出的数据组的数量；并将写信用积分及读信用积分发送至前级设备后，前级设备便可根据写信用积分及读信用积分了解当前FIFO存储器能正常写入及读出的数据组数量，并根据写信用积分及读信用积分进行数据的读写，实现系统的流量控制，保证数据不溢出不阻塞，提高FIFO存储器的使用效率。

Description

基于FIFO存储器的信息生成方法、装置、设备及介质
本申请要求在2021年9月7日提交中国专利局、申请号为202111040858.7、发明名称为“基于FIFO存储器的信息生成方法、装置、设备及介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据存储技术领域，更具体地说，涉及一种基于FIFO存储器的信息生成方法、装置、设备及介质。
背景技术
随着微电子技术的飞速发展，FIFO(First Input First Output，先进先出)存储器芯片以其灵活、方便、高效的特性，逐渐在高速数据采集、高速数据处理、高速数据传输以及多机处理系统中得到越来越广泛的应用。FIFO存储器是系统的缓冲环节，它主要有以下几方面的功能：1、对连续的数据流进行缓存，防止在进机和存储操作时丢失数据；2、数据集中起来进行进机和存储，可避免频繁的总线操作，减轻CPU(central processing unit，中央处理器)的负担；3、允许系统进行DMA(Direct Memory Access，直接存储器访问)操作，提高数据的传输速度。
当前，大部分的数字电路都是同步的，即采用同一时钟来控制所有时钟控制器件，如对触发器等进行控制。同步电路作为主导设计方法，其成熟的工具几乎覆盖了整个大规模数字集成电路设计流程，从高层次语言描述到一个完整的芯片版图只需要极少的人工干预。当前的同步FIFO存储器在正常的读写功能基础上一般只提供空满指示信号、几乎空几乎满指示信号，这在一定程度上限制了FIFO存储器的使用范围。例如：当前同步FIFO存储器的深度为128，数据位宽为8bit，FIFO存储器的前级设备为DDR(Double Data Rate，双倍速率同步动态随机存储器)控制器或PCIe(peripheral component interconnect express，高速串行计算机扩展总线标准机存储器)，DDR控制器或PCIe在向FIFO存储器发送数据包时，由于前级数据是连续发送的，因此在 数据开始发送时，不管后级FIFO存储器是否还有空间可以存储数据，数据必须连续的从前级发送至后级。若当前级数据包只发送了一部分数据，后级FIFO存储器已经处于满状态，则后半部分的数据无法缓存至FIFO存储器中，或者将之前的FIFO存储器中的数据覆盖，造成数据的丢失。
目前解决此问题的通用办法是判断FIFO存储器的空状态，当FIFO存储器为空时开始写入数据，此时可以写入的数据空间即为FIFO存储器本身的容量。在进行FIFO存储器调用时，会保证其数据空间不小于前级一次连续的写的数据大小。但是，该方式存在很大效率浪费问题，例如：目前FIFO存储器中缓存了64个数据位宽为8bit的数据，此时空满信号均为0，而前级想要发送一组32个8Bit数据则只能等待FIFO被读空，即空状态信号为1时才可读取，因为通过空满指示信号并不能判断此FIFO中到底已经存储了多少数据，可见，通过该方式降低了FIFO存储器的使用效率。
发明内容
本申请的目的在于提供一种基于FIFO存储器的信息生成方法、装置、设备及介质，以提高FIFO存储器的使用效率。
为实现上述目的，本申请提供一种基于FIFO存储器的信息生成方法，包括：
获取当前FIFO存储器的读地址和写地址；
获取当前所述FIFO存储器的读数据使能信号值及写数据使能信号值；
利用所述FIFO存储器的总容量及所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值，确定当前所述FIFO存储器的写信用积分及读信用积分；所述写信用积分代表所述FIFO存储器能正常写入的数据组的数量；所述读信用积分代表所述FIFO存储器能正常读出的数据组的数量；
将所述写信用积分及所述读信用积分发送至前级设备，以使所述前级设备根据所述写信用积分及所述读信用积分进行数据的读写。
其中，所述利用所述FIFO存储器的总容量及所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值，确定当前所述FIFO存储器的写信用积分及读信用积分，包括：
判断所述写地址是否小于所述读地址；若是，则根据所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第一确定规则确定写信用积分；若否，则根据所述总容量、所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第二确定规则确定写信用积分；
判断所述写地址是否小于所述读地址；若是，则根据所述总容量、所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第三确定规则确定读信用积分；若否，则根据所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第四确定规则确定读信用积分。
其中，所述根据所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第一确定规则确定写信用积分，包括：
利用所述第一确定规则确定写信用积分，所述第一确定规则为：写信用积分＝读地址-写地址+读数据使能信号值-写数据使能信号值；
相应的，所述根据所述总容量、所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第二确定规则确定写信用积分，包括：
利用所述第二确定规则确定写信用积分，所述第二确定规则为：写信用积分＝总容量-写地址+读地址+读数据使能信号值-写数据使能信号值。
其中，所述根据所述总容量、所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第三确定规则确定读信用积分，包括：
利用所述第三确定规则确定读信用积分，所述第三确定规则为：读信用积分＝总容量+写地址-读地址-读数据使能信号值+写数据使能信号值；
相应的，所述根据所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第四确定规则确定读信用积分，包括：
利用所述第四确定规则确定读信用积分，所述第四确定规则为：读信用积分＝写地址-读地址-读数据使能信号值+写数据使能信号值。
其中，所述确定当前所述FIFO存储器的写信用积分及读信用积分之后，还包括：
若所述读信用积分为0，则生成空状态信号为1，若所述读信用积分为1，则生成几乎空状态信号为1；
若所述写信用积分为0，则生成满状态信号为1，若所述写信用积分为1，则生成几乎满状态信号为1。
其中，所述将所述写信用积分及所述读信用积分发送至前级设备，包括：
确定数据组的单位值；所述单位值用于表示每个数据组中数据的字节数；
确定基于每个单位值的写信用积分及读信用积分，并将基于每个单位值的写信用积分及读信用积分发送至前级设备。
其中，所述确定基于每个单位值的写信用积分及读信用积分，包括：
计算所述写信用积分与每个单位值的比值，并将比值向下取整后得到基于每个单位值的写信用积分；
计算所述读信用积分与每个单位值的比值，并将比值向下取整后得到基于每个单位值的读信用积分。
为实现上述目的，本申请进一步提供一种基于FIFO存储器的信息生成装置，包括：
第一获取模块，用于获取当前FIFO存储器的读地址和写地址；
第二获取模块，用于获取当前所述FIFO存储器的读数据使能信号值及写数据使能信号值；
确定模块，用于利用所述FIFO存储器的总容量及所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值，确定当前所述FIFO存储器的写信用积分及读信用积分；所述写信用积分代表所述FIFO存储器能正常写入的数据组的数量；所述读信用积分代表所述FIFO存储器能正常读出的数据组的数量；
发送模块，用于将所述写信用积分及所述读信用积分发送至前级设备，以使所述前级设备根据所述写信用积分及所述读信用积分进行数据的读写。
为实现上述目的，本申请进一步提供一种电子设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行所述计算机程序时实现上述基于FIFO存储器的信息生成方法的步骤。
为实现上述目的，本申请进一步提供一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现上述基于FIFO存储器的信息生成方法的步骤。
通过以上方案可知，本申请实施例提供的基于FIFO存储器的信息生成方法、装置、设备及介质，会利用FIFO存储器的总容量、当前FIFO存储器的 读地址、写地址、读数据使能信号值及写数据使能信号值，确定当前FIFO存储器的写信用积分及读信用积分；该写信用积分代表FIFO存储器能正常写入的数据组的数量；该读信用积分代表FIFO存储器能正常读出的数据组的数量；并将写信用积分及读信用积分发送至前级设备后，前级设备便可根据写信用积分及读信用积分了解当前FIFO存储器能正常写入及读出的数据组数量，并根据写信用积分及读信用积分进行数据的读写，实现系统的流量控制，保证数据不溢出不阻塞，提高FIFO存储器的使用效率。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例公开的一种基于FIFO存储器的信息生成系统结构示意图；
图2为本申请实施例公开的一种基于FIFO存储器的信息生成方法流程示意图；
图3为本申请实施例公开的一种基于FIFO存储器的信息生成装置结构示意；
图4为本申请实施例公开的一种电子产品结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例公开了一种基于FIFO存储器的信息生成方法、装置、设备及介质，以提高FIFO存储器的使用效率。为了便于理解，下面对本申请的技术方案所适用的系统架构进行介绍，参见图1，为本申请实施例公开的一种基 于FIFO存储器的信息生成系统结构示意图。通过图1可以看出，同步FIFO模块在硬件实现时可分为以下部分：写地址生成模块Wr_addr、读地址生成模块Rd_addr、存储模块Memory、信用积分生成模块Credit、通过信用积分生成FIFO空信号模块Cr_empty、通过信用积分生成FIFO满信号模块Cr_full。参见表1，为同步FIFO模块接口信号的说明：
表1
Figure PCTCN2021134434-appb-000001
下面结合表1对图1中的各模块进行说明：
1、写地址生成模块Wr_addr：该模块根据输入的写使能wr_en信号生成数据写入存储模块的地址。复位完成后，写地址为0。当wr_en为高时，将数 据写入当前的Memory地址中，同时写地址加1作为下一次写入的数据地址。当写地址达到最大之后自动清零。
2、读地址生成模块rd_addr：该模块根据输入的读使能rd_en信号生成从存储模块读出数据的地址。复位完成后，读地址为0。当rd_en为高时，将当前的读Memory地址给到后级存储模块的读地址中，同时读地址加1作为下一次读数据的地址。当读地址达到最大之后自动清零。
3、存储模块Memory：该模块为调用或生成一个同步的双端口静态随机存储器，该存储模块可为RAM存储器(Random Access Memory，随机存取存储器)。
4、信用积分生成模块Credit：该模块执行后文所述的信息生成方法，生成写信用积分及读信用积分；
5、通过信用积分生成FIFO空信号模块Cr_empty：该模块根据信用积分生成模块Credit计算出的写信用积分及读信用积分，生成空状态信号或者几乎空状态信号；
6、通过信用积分生成FIFO满信号模块Cr_full：该模块根据信用积分生成模块Credit计算出的写信用积分及读信用积分，生成满状态信号或者几乎满状态信号。
下面对本方案基于FIFO存储器生成信息的方法进行具体说明。
参见图2，本申请实施例提供的一种基于FIFO存储器的信息生成方法流程示意图，该方法包括：
S101、获取当前FIFO存储器的读地址和写地址；
S102、获取当前FIFO存储器的读数据使能信号值及写数据使能信号值；
具体来说，本实施例从读地址生成模块rd_addr获取读地址及读数据使能信号值，从写地址生成模块Wr_addr获取写地址及写数据使能信号值。其中，读数据使能信号值是根据读数据使能信号rd_en确定的，若接收到数据使能信号rd_en为高，则读数据使能信号值为1，否则为0；同理，写数据使能信号值是根据写数据使能信号wr_en确定的，若接收到写数据使能信号wr_en为高，则写数据使能信号值为1，否则为0。在本实施例中，仅以先执行S101再执行S102为例进行说明，并不具体限定这两个步骤的执行顺序，如：可以 先获取读数据使能信号值及写数据使能信号值，再获取读地址和写地址，也可以同时获取读数据使能信号值、写数据使能信号值、读地址和写地址。
S103、利用FIFO存储器的总容量及读地址、写地址、读数据使能信号值、写数据使能信号值，确定当前FIFO存储器的写信用积分及读信用积分；该写信用积分代表FIFO存储器能正常写入的数据组的数量；该读信用积分代表FIFO存储器能正常读出的数据组的数量；
在本实施例中，数据刚写入FIFO存储器后，写地址大于读地址，但是，随着数据不断写入，新写入的数据会重新覆盖已写入的地址，此时写地址便会从初始地址开始，便会出现读地址大于写地址的情况。因此在本实施例中，针对写信用积分及读信用积分的确定过程，充分考虑了这两种情况。
其中，本实施例确定当前FIFO存储器的写信用积分的过程为：
判断写地址是否小于读地址；若是，则根据读地址、写地址、读数据使能信号值、写数据使能信号值及第一确定规则确定写信用积分；若否，则根据总容量、读地址、写地址、读数据使能信号值、写数据使能信号值及第二确定规则确定写信用积分；
具体来说，本方案利用第一确定规则确定写信用积分，第一确定规则为：写信用积分＝读地址-写地址+读数据使能信号值-写数据使能信号值；本方案利用第二确定规则确定写信用积分，第二确定规则为：写信用积分＝总容量-写地址+读地址+读数据使能信号值-写数据使能信号值。
其中，本实施例确定当前FIFO存储器的读信用积分的过程为：
判断写地址是否小于读地址；若是，则根据总容量、读地址、写地址、读数据使能信号值、写数据使能信号值及第三确定规则确定读信用积分；若否，则根据读地址、写地址、读数据使能信号值、写数据使能信号值及第四确定规则确定读信用积分。
具体来说，本方案利用第三确定规则确定读信用积分，第三确定规则为：读信用积分＝总容量+写地址-读地址-读数据使能信号值+写数据使能信号值；本方案利用第四确定规则确定读信用积分，第四确定规则为：读信用积分＝写地址-读地址-读数据使能信号值+写数据使能信号值。
S104、将写信用积分及读信用积分发送至前级设备，以使前级设备根据写信用积分及读信用积分进行数据的读写。
在本实施例中，信用机制是一种控制数据流量的方法，本方案中的写信用积分代表此同步FIFO中可以正常写入的数据组数，读信用积分代表此同步FIFO中可以正常读出的数据组数，后级通过实时或定时的向上级反馈其可以接收或发送的数据个数，实现整个系统的流量控制，保证数据不溢出不阻塞。并且，本方案中数据组的单位是不同的，若数据组的单位值为1Byte，则本方案通过用credit_1的后缀表示，数据组的单位值为4Byte/16Byte大小，则用credit_4/credit_16的后缀表示，同时本方案也支持用户根据使用需求自定义数据大小，用credit_user后缀表示。
因此本方案将写信用积分及读信用积分发送至前级设备时，需要确定数据组的单位值；该单位值用于表示每个数据组中数据的字节数；然后确定基于每个单位值的写信用积分及读信用积分，并将基于每个单位值的写信用积分及读信用积分发送至前级设备。在确定基于每个单位值的写信用积分及读信用积分时，具体是计算写信用积分与每个单位值的比值，并将比值向下取整后得到基于每个单位值的写信用积分，计算读信用积分与每个单位值的比值，并将比值向下取整后得到基于每个单位值的读信用积分。
例如：设定读地址为rd_addr，写地址为wr_addr，读数据使能信号值为rd_en，写数据使能信号值为wr_en，并且，在使用同步FIFO存储器前，定义FIFO存储器的总容量大小，记为fifo_capa，单位为byte。
1、计算写信用积分wr_credit的过程如下：
首先比较wr_addr和rd_addr的地址大小；
若wr_addr＝>rd_addr，则：
wr_credit_1＝fifo_capa-wr_addr+rd_addr+rd_en–wr_en。
若wr_addr<rd_addr，则：
wr_credit_1＝rd_addr-wr_addr+rd_en–wr_en。
此时计算的wr_credit_1为基于单位值为1的写信用积分，其他写信用积分的计算方式如下：
wr_credit_4＝wr_credit_1/4，向下取整；
wr_credit_16＝wr_credit_1/16，向下取整；
wr_credit_user＝wr_credit_1/wr_credit_user，向下取整。
2、计算读信用积分rd_credit的过程如下：
首先比较wr_addr和rd_addr的地址大小；
若wr_addr＝>rd_addr，则：
rd_credit_1＝wr_addr-rd_addr-rd_en+wr_en；
若wr_addr<rd_addr，则：
rd_credit_1＝fifo_capa+wr_addr-rd_addr-rd_en+wr_en。
此时计算的rd_credit_1为基于单位值为1的读信用积分，其他读信用积分的计算方式如下：
rd_credit_4＝rd_credit_1/4，向下取整；
rd_credit_16＝rd_credit_1/16，向下取整；
rd_credit_user＝rd_credit_1/wr_credit_user，向下取整。
需要说明的是，在本实施例中，确定当前所述FIFO存储器的写信用积分及读信用积分之后，若读信用积分为0，则生成空状态信号为1，若读信用积分为1，则生成几乎空状态信号为1；若写信用积分为0，则生成满状态信号为1，若写信用积分为1，则生成几乎满状态信号为1。需要说明的是，空状态信号、几乎空状态信号、满状态信号和几乎满状态信号默认情况下均为0，只有满足上述条件后才会对应设置为1。
也就是说：前文记载的Cr_empty模块，在rd_credit_1＝0时(rd_credit_1为0代表此时没有可以再读出的数据)，此时FIFO为空状态，empty信号为1。当rd_credit_1＝1时(d_credit_1为1代表此时只有一个可以读出的数据)，此时FIFO为几乎空状态，aempty信号为1。前文记载的Cr_full模块，当wr_credit_1＝0时(wr_credit_1为0代表此时无法再写入数据)，此时FIFO为满状态，full信号为1。当wr_credit_1＝1时(wr_credit_1为1代表此时只有一个可以再写入的数据空间)，此时FIFO为几乎满状态，afull信号为1。本方案生成的空状态信号、几乎空状态信号、满状态信号和几乎满状态信号同样可以发送至前级设备，前级设备仍然可以根据上述信号进行数据的读写。
综上可以看出，本方案实质提供了具有信用机制接口的同步FIFO存储器，读写端生成独立的信用积分并且支持用户自定义信用积分。通过读信用积分可以生成FIFO存储器的空和几乎空信号，通过写信用积分可以生成FIFO存储器的满和几乎满信号。通过该方式，可以让前级设备直接通过读写信用积分了解可向FIFO存储器读写几组数据，不需要在外部设备单独计算，简化 外部接口信号的计算过程，还可以直接与PCIe等支持信用机制的系统相连，提高了同步FIFO模块的复用性和可靠性，进而提高整个SOC(System on Chip,片上系统)的开发效率，进而提高产品竞争力。
下面对本申请实施例提供的信息生成装置、设备及介质进行介绍，下文描述的信息生成装置、设备及介质与上文描述的信息生成方法可以相互参照。
参见图3，本申请实施例提供的一种基于FIFO存储器的信息生成装置结构示意图，包括：
第一获取模块11，用于获取当前FIFO存储器的读地址和写地址；
第二获取模块12，用于获取当前所述FIFO存储器的读数据使能信号值及写数据使能信号值；
确定模块13，用于利用所述FIFO存储器的总容量及所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值，确定当前所述FIFO存储器的写信用积分及读信用积分；所述写信用积分代表所述FIFO存储器能正常写入的数据组的数量；所述读信用积分代表所述FIFO存储器能正常读出的数据组的数量；
发送模块14，用于将所述写信用积分及所述读信用积分发送至前级设备，以使所述前级设备根据所述写信用积分及所述读信用积分进行数据的读写。
其中，所述确定模块包括：
第一判断单元，用于判断所述写地址是否小于所述读地址；若是，则触发第一确定单元；若否，则触发第二确定单元；
所述第一确定单元，用于根据所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第一确定规则确定写信用积分；
所述第二确定单元，用于根据所述总容量、所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第二确定规则确定写信用积分；
第二判断单元，用于判断所述写地址是否小于所述读地址；若是，则触发第三确定单元，若否，则触发第四确定单元；
所述第三确定单元，用于根据所述总容量、所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第三确定规则确定读信用积分；
所述第四确定单元，用于根据所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第四确定规则确定读信用积分。
其中，所述第一确定单元具体用于：
利用所述第一确定规则确定写信用积分，所述第一确定规则为：
写信用积分＝读地址-写地址+读数据使能信号值-写数据使能信号值；
相应的，所述第二确定单元具体用于：
利用所述第二确定规则确定写信用积分，所述第二确定规则为：
写信用积分＝总容量-写地址+读地址+读数据使能信号值-写数据使能信号值。
其中，所述第三确定单元具体用于：
利用所述第三确定规则确定读信用积分，所述第三确定规则为：
读信用积分＝总容量+写地址-读地址-读数据使能信号值+写数据使能信号值；
相应的，所述第四确定单元具体用于：
利用所述第四确定规则确定读信用积分，所述第四确定规则为：
读信用积分＝写地址-读地址-读数据使能信号值+写数据使能信号值。
其中，所述装置还包括：
第一信号生成模块，用于在所述读信用积分为0时生成空状态信号为1，在所述读信用积分为1时生成几乎空状态信号为1；
第二信号生成模块，用于在所述写信用积分为0时生成满状态信号为1，在所述写信用积分为1时生成几乎满状态信号为1。
其中，所述发送模块包括：
第五确定单元，用于确定数据组的单位值；所述单位值用于表示每个数据组中数据的字节数；
第六确定单元，用于确定基于每个单位值的写信用积分及读信用积分；
发送单元，用于将基于每个单位值的写信用积分及读信用积分发送至前级设备。
其中，所述第六确定单元包括：
第一计算子单元，用于计算所述写信用积分与每个单位值的比值，并将比值向下取整后得到基于每个单位值的写信用积分；
第二计算子单元，用于计算所述读信用积分与每个单位值的比值，并将比值向下取整后得到基于每个单位值的读信用积分。
参见图4，为本申请实施例提供的一种电子设备结构示意图，包括：
存储器21，用于存储计算机程序；
处理器22，用于执行所述计算机程序时实现上述实施例所述的基于FIFO存储器的信息生成方法的步骤。
在本实施例中，设备可以是PC(Personal Computer，个人电脑)，也可以是智能手机、平板电脑、掌上电脑、便携计算机等终端设备。
该设备可以包括存储器21、处理器22和总线23。
其中，存储器21至少包括一种类型的可读存储介质，所述可读存储介质包括闪存、硬盘、多媒体卡、卡型存储器(例如，SD或DX存储器等)、磁性存储器、磁盘、光盘等。存储器21在一些实施例中可以是设备的内部存储单元，例如该设备的硬盘。存储器21在另一些实施例中也可以是设备的外部存储设备，例如设备上配备的插接式硬盘，智能存储卡(Smart Media Card,SMC)，安全数字(Secure Digital,SD)卡，闪存卡(Flash Card)等。进一步地，存储器21还可以既包括设备的内部存储单元也包括外部存储设备。存储器21不仅可以用于存储安装于设备的应用软件及各类数据，例如执行信息生成方法的程序代码等，还可以用于暂时地存储已经输出或者将要输出的数据。
处理器22在一些实施例中可以是一中央处理器(Central Processing Unit,CPU)、控制器、微控制器、微处理器或其他数据处理芯片，用于运行存储器21中存储的程序代码或处理数据，例如执行信息生成方法的程序代码等。
该总线23可以是外设部件互连标准(peripheral component interconnect，简称PCI)总线或扩展工业标准结构(extended industry standard architecture，简称EISA)总线等。该总线可以分为地址总线、数据总线、控制总线等。为便于表示，图4中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
进一步地，设备还可以包括网络接口24，网络接口24可选的可以包括有线接口和/或无线接口(如WI-FI接口、蓝牙接口等)，通常用于在该设备与其他电子设备之间建立通信连接。
可选地，该设备还可以包括用户接口25，用户接口25可以包括显示器(Display)、输入单元比如键盘(Keyboard)，可选的用户接口25还可以包括标准的有线接口、无线接口。可选地，在一些实施例中，显示器可以是LED 显示器、液晶显示器、触控式液晶显示器以及OLED(Organic Light-Emitting Diode，有机发光二极管)触摸器等。其中，显示器也可以适当的称为显示屏或显示单元，用于显示在设备中处理的信息以及用于显示可视化的用户界面。
图4仅示出了具有组件21-25的设备，本领域技术人员可以理解的是，图4示出的结构并不构成对设备的限定，可以包括比图示更少或者更多的部件，或者组合某些部件，或者不同的部件布置。
为本申请实施例还提供了一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现上述实施例所述的基于FIFO存储器的信息生成方法的步骤。
其中，该存储介质可以包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (12)

  1. 一种基于FIFO存储器的信息生成方法，其特征在于，包括：
    获取当前FIFO存储器的读地址和写地址；
    获取当前所述FIFO存储器的读数据使能信号值及写数据使能信号值；
    利用所述FIFO存储器的总容量及所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值，确定当前所述FIFO存储器的写信用积分及读信用积分；所述写信用积分代表所述FIFO存储器能正常写入的数据组的数量；所述读信用积分代表所述FIFO存储器能正常读出的数据组的数量；
    将所述写信用积分及所述读信用积分发送至前级设备，以使所述前级设备根据所述写信用积分及所述读信用积分进行数据的读写。
  2. 根据权利要求1所述的信息生成方法，其特征在于，利用所述FIFO存储器的总容量及所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值，确定当前所述FIFO存储器的写信用积分及读信用积分，包括：
    判断所述写地址是否小于所述读地址；若是，则根据所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值及第一确定规则确定写信用积分；若否，则根据所述总容量、所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值及第二确定规则确定写信用积分；
    判断所述写地址是否小于所述读地址；若是，则根据所述总容量、所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值及第三确定规则确定读信用积分；若否，则根据所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值及第四确定规则确定读信用积分。
  3. 根据权利要求2所述的信息生成方法，其特征在于，所述根据所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值及第一确定规则确定写信用积分，包括：
    利用所述第一确定规则确定写信用积分，所述第一确定规则为：写信用积分＝读地址-写地址+读数据使能信号值-写数据使能信号值；
    相应的，所述根据所述总容量、所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值及第二确定规则确定写信用积分，包括：
    利用所述第二确定规则确定写信用积分，所述第二确定规则为：写信用积分＝总容量-写地址+读地址+读数据使能信号值-写数据使能信号值。
  4. 根据权利要求2所述的信息生成方法，其特征在于，所述根据所述总容量、所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值及第三确定规则确定读信用积分，包括：
    利用所述第三确定规则确定读信用积分，所述第三确定规则为：读信用积分＝总容量+写地址-读地址-读数据使能信号值+写数据使能信号值；
    相应的，所述根据所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值及第四确定规则确定读信用积分，包括：
    利用所述第四确定规则确定读信用积分，所述第四确定规则为：读信用积分＝写地址-读地址-读数据使能信号值+写数据使能信号值。
  5. 根据权利要求1所述的信息生成方法，其特征在于，所述确定当前所述FIFO存储器的写信用积分及读信用积分之后，还包括：
    若所述读信用积分为0，则生成空状态信号为1，若所述读信用积分为1，则生成几乎空状态信号为1；
    若所述写信用积分为0，则生成满状态信号为1，若所述写信用积分为1，则生成几乎满状态信号为1。
  6. 根据权利要求1至5中任意一项所述的信息生成方法，其特征在于，所述将所述写信用积分及所述读信用积分发送至前级设备，包括：
    确定数据组的单位值；所述单位值用于表示每个数据组中数据的字节数；
    确定基于每个单位值的写信用积分及读信用积分，并将基于每个单位值的写信用积分及读信用积分发送至前级设备。
  7. 根据权利要求6所述的信息生成方法，其特征在于，所述确定基于每个单位值的写信用积分及读信用积分，包括：
    计算所述写信用积分与每个单位值的比值，并将比值向下取整后得到基于每个单位值的写信用积分；
    计算所述读信用积分与每个单位值的比值，并将比值向下取整后得到基于每个单位值的读信用积分。
  8. 根据权利要求2所述的信息生成方法，其特征在于，所述获取当前所述FIFO存储器的读数据使能信号值及写数据使能信号值，包括：若接收到数 据使能信号为高，则所述读数据使能信号值为1，否则为0；若接收到写数据使能信号为高，则所述写数据使能信号值为1，否则为0。
  9. 一种基于FIFO存储器的信息生成装置，其特征在于，包括：
    第一获取模块，用于获取当前FIFO存储器的读地址和写地址；
    第二获取模块，用于获取当前所述FIFO存储器的读数据使能信号值及写数据使能信号值；
    确定模块，用于利用所述FIFO存储器的总容量及所述读地址、所述写地址、所述读数据使能信号值、所述写数据使能信号值，确定当前所述FIFO存储器的写信用积分及读信用积分；所述写信用积分代表所述FIFO存储器能正常写入的数据组的数量；所述读信用积分代表所述FIFO存储器能正常读出的数据组的数量；
    发送模块，用于将所述写信用积分及所述读信用积分发送至前级设备，以使所述前级设备根据所述写信用积分及所述读信用积分进行数据的读写。
  10. 根据权利要求9所述的信息生成装置，其特征在于，
    所述第二获取模块被配置为：若接收到数据使能信号为高，则设置所述读数据使能信号值为1，否则为0；若接收到写数据使能信号为高，则设置所述写数据使能信号值为1，否则为0；
    所述确定模块包括：
    第一判断单元，用于判断所述写地址是否小于所述读地址；若是，则触发第一确定单元；若否，则触发第二确定单元；
    所述第一确定单元，用于根据所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第一确定规则确定写信用积分；
    所述第二确定单元，用于根据所述总容量、所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第二确定规则确定写信用积分；
    第二判断单元，用于判断所述写地址是否小于所述读地址；若是，则触发第三确定单元，若否，则触发第四确定单元；
    所述第三确定单元，用于根据所述总容量、所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第三确定规则确定读信用积分；
    所述第四确定单元，用于根据所述读地址、所述写地址、所述读数据使能信号值、写数据使能信号值及第四确定规则确定读信用积分。
  11. 一种电子设备，其特征在于，包括：
    存储器，用于存储计算机程序；
    处理器，用于执行所述计算机程序时实现如权利要求1至8任一项所述的基于FIFO存储器的信息生成方法的步骤。
  12. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至8任一项所述的基于FIFO存储器的信息生成方法的步骤。
PCT/CN2021/134434 2021-09-07 2021-11-30 基于fifo存储器的信息生成方法、装置、设备及介质 WO2023035427A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/256,355 US20240020246A1 (en) 2021-09-07 2021-11-30 Method for Generating Information Based on FIFO Memory and Apparatus, Device and Medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111040858.7A CN113485672B (zh) 2021-09-07 2021-09-07 基于fifo存储器的信息生成方法、装置、设备及介质
CN202111040858.7 2021-09-07

Publications (1)

Publication Number Publication Date
WO2023035427A1 true WO2023035427A1 (zh) 2023-03-16

Family

ID=77946561

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/134434 WO2023035427A1 (zh) 2021-09-07 2021-11-30 基于fifo存储器的信息生成方法、装置、设备及介质

Country Status (3)

Country Link
US (1) US20240020246A1 (zh)
CN (1) CN113485672B (zh)
WO (1) WO2023035427A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113485672B (zh) * 2021-09-07 2021-11-19 苏州浪潮智能科技有限公司 基于fifo存储器的信息生成方法、装置、设备及介质
CN113608786B (zh) 2021-10-09 2022-02-18 苏州浪潮智能科技有限公司 一种向量读写方法、向量寄存器系统、设备及介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007157162A (ja) * 2005-12-07 2007-06-21 Korea Electronics Telecommun 双方向データ通信用単一ポートメモリ制御装置およびその制御方法
CN106776357A (zh) * 2016-12-28 2017-05-31 无锡芯响电子科技有限公司 一种多路读写多容量选择的fifo控制器
CN111279327A (zh) * 2017-10-31 2020-06-12 高通股份有限公司 用于非易失性存储器的写入信用管理
CN113126903A (zh) * 2019-12-30 2021-07-16 美光科技公司 用于在存储器接口中实现写后读命令的系统和方法
CN113485672A (zh) * 2021-09-07 2021-10-08 苏州浪潮智能科技有限公司 基于fifo存储器的信息生成方法、装置、设备及介质

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6671747B1 (en) * 2000-08-03 2003-12-30 Apple Computer, Inc. System, apparatus, method, and computer program for execution-order preserving uncached write combine operation
CN100536020C (zh) * 2004-07-23 2009-09-02 华为技术有限公司 一种先入先出存储器及其读写地址的调整方法
JP4760052B2 (ja) * 2005-02-24 2011-08-31 ヤマハ株式会社 伝送制御装置およびサンプリング周波数変換装置
US9189199B2 (en) * 2012-12-06 2015-11-17 Nvidia Corporation Folded FIFO memory generator
CN206431615U (zh) * 2016-12-28 2017-08-22 无锡芯响电子科技有限公司 一种多路读写多容量选择的fifo控制器
US20210248087A1 (en) * 2018-09-27 2021-08-12 Intel Corporation Data stored or free space based fifo buffer
CN112199071B (zh) * 2020-10-26 2024-02-09 中国兵器工业集团第二一四研究所苏州研发中心 一种地址可控异步缓存器及异步缓存方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007157162A (ja) * 2005-12-07 2007-06-21 Korea Electronics Telecommun 双方向データ通信用単一ポートメモリ制御装置およびその制御方法
CN106776357A (zh) * 2016-12-28 2017-05-31 无锡芯响电子科技有限公司 一种多路读写多容量选择的fifo控制器
CN111279327A (zh) * 2017-10-31 2020-06-12 高通股份有限公司 用于非易失性存储器的写入信用管理
CN113126903A (zh) * 2019-12-30 2021-07-16 美光科技公司 用于在存储器接口中实现写后读命令的系统和方法
CN113485672A (zh) * 2021-09-07 2021-10-08 苏州浪潮智能科技有限公司 基于fifo存储器的信息生成方法、装置、设备及介质

Also Published As

Publication number Publication date
US20240020246A1 (en) 2024-01-18
CN113485672B (zh) 2021-11-19
CN113485672A (zh) 2021-10-08

Similar Documents

Publication Publication Date Title
USRE49875E1 (en) Memory system having high data transfer efficiency and host controller
WO2023035427A1 (zh) 基于fifo存储器的信息生成方法、装置、设备及介质
US6192428B1 (en) Method/apparatus for dynamically changing FIFO draining priority through asynchronous or isochronous DMA engines in response to packet type and predetermined high watermark being reached
KR100708128B1 (ko) 낸드 플래시 메모리 제어 장치 및 방법
US8041856B2 (en) Skip based control logic for first in first out buffer
CN113900974B (zh) 一种存储装置、数据存储方法及相关设备
TWI528183B (zh) 使用資料傳輸率節流來執行序列ａｔａ連接的資料傳輸之方法、電腦可讀媒體和系統
US20070079015A1 (en) Methods and arrangements to interface a data storage device
TWI410963B (zh) 作業系統輔助碟片快取電腦系統、方法與製圖子系統
JP2003316732A (ja) データ転送制御装置、電子機器及びデータ転送制御方法
US7185122B2 (en) Device and method for controlling data transfer
CN115237349A (zh) 数据读写控制方法、控制装置、计算机存储介质和电子设备
US20140013066A1 (en) Memory sub-system and computing system including the same
CN115033520A (zh) Iic数据传输方法、装置、单片机设备及存储介质
CN114721983A (zh) 一种ddr4加速读写装置
US8645791B2 (en) Data cache controller, devices having the same, and method of operating the same
CN110781118B (zh) 实现并行总线从模式的方法及装置、计算机设备、介质
WO2018058570A1 (zh) 充电控制方法、充电控制系统和计算设备
CN118035162A (zh) 数据传输方法、装置、设备及存储介质
JP4281367B2 (ja) データ転送制御回路、電子機器及びデータ転送制御方法
TWI521349B (zh) 攜帶式電子裝置資料寫入方法
CN103034598B (zh) 保存dma下行数据时写使能信号的处理方法及系统
CN115391248A (zh) 自动填充数据的方法、系统、电子设备及存储介质
KR101101867B1 (ko) 모바일 스토리지 제어 장치
CN116540951A (zh) 存储器、数据存取方法、存储装置及存储介质

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21956598

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 18256355

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE