WO2023035271A1 - 驱动电路以及电子设备 - Google Patents

驱动电路以及电子设备 Download PDF

Info

Publication number
WO2023035271A1
WO2023035271A1 PCT/CN2021/118021 CN2021118021W WO2023035271A1 WO 2023035271 A1 WO2023035271 A1 WO 2023035271A1 CN 2021118021 W CN2021118021 W CN 2021118021W WO 2023035271 A1 WO2023035271 A1 WO 2023035271A1
Authority
WO
WIPO (PCT)
Prior art keywords
switch
pole
control
signal
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/118021
Other languages
English (en)
French (fr)
Inventor
徐敏
金健
孙梦园
张卫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fudan University
Original Assignee
Fudan University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fudan University filed Critical Fudan University
Priority to PCT/CN2021/118021 priority Critical patent/WO2023035271A1/zh
Publication of WO2023035271A1 publication Critical patent/WO2023035271A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the invention relates to the field of electronic technology, in particular to a driving circuit and electronic equipment.
  • GaN transistors As a third-generation device, GaN transistors have smaller volume, higher operating frequency, low switching loss, and are suitable for high-frequency operation.
  • the half-bridge system of the prior art two transistor switches are generally connected in series, and a sufficient dead time is set between the upper transistor and the lower transistor to avoid simultaneous conduction of the upper transistor and the lower transistor.
  • the bridge driver sets the dead time for the two control signals input to the H1 and L1 ports to avoid simultaneous conduction of G1 and G2; although the setting of the dead time is easier to implement, for the GaN half-bridge system, Due to the high operating frequency and short cycle of GaN transistors, the generally set dead time is only a few nanoseconds, and process errors can easily lead to the upper and lower transistors. Setting too long dead time will lead to increased system losses.
  • the invention provides a driving circuit and electronic equipment to solve the problems of low control accuracy and high loss of a GaN half-bridge system.
  • a driving circuit for driving the first switch and the second switch further comprising: a first control module, a second control module;
  • the first control module is connected to the first control signal, and the first control module is connected to the control pole of the first switch; the first control module is used for: monitoring the signal of the control pole of the second switch, generating a first switch drive signal according to the first control signal and the signal of the gate electrode of the second switch, and using the first switch drive signal to drive the first switch on and off;
  • the second control module is connected to a second control signal, and the second control module is connected to the control pole of the second switch; the second control module is used for: monitoring the signal of the control pole of the first switch, generating a second switch drive signal according to the second control signal and the signal of the gate electrode of the first switch, and using the second switch drive signal to drive the second switch on and off;
  • the first power supply supplies power to the first pole of the first switch, the second pole of the first switch is connected to the first pole of the second switch, and the second pole of the second switch is connected to ground;
  • the load is connected in parallel between the first pole of the second switch and ground.
  • the first control module includes a first logic unit and a level shift unit
  • the second control module includes a detection and level shift unit and a second logic unit
  • the first input terminal of the first logic unit is connected to the first control signal
  • the second input terminal of the first logic unit is connected to the output terminal of the second logic unit
  • the output of the first logic unit The terminal is connected to the level shift unit;
  • the first logic unit is used to: generate a control level according to the first control signal and the second switch driving signal generated by the second logic unit, and transfer the control level feedback to the level shift unit;
  • the level shifting unit is connected to the second pole of the first switch, the level shifting unit is directly or indirectly connected to the control pole of the first switch, and the level shifting unit is used for: according to the first The voltage of the second pole of the switch is used to increase the control level to a target level interval to obtain the first switch drive signal to drive the first switch to be turned on and off;
  • the detection and level shift unit is connected between the level shift unit and the control pole of the first switch, and the detection and level shift unit is connected to the first input end of the second logic unit; the The detection and level shifting unit is used to: detect the signal of the control pole of the first switch, step down the signal of the control pole of the first switch, and convert the switch state signal of the first switch obtained after stepping down to Feedback to the second logic unit; the switch state signal represents the on-off state of the corresponding switch;
  • the second input terminal of the second logic unit is connected to the second control signal, the output terminal of the second logic unit is directly or indirectly connected to the control pole of the second switch, and the second logic unit is used for : generating the second switch drive signal according to the switch status signal of the first switch and the second control signal, so as to drive the second switch to be turned on and off.
  • control level includes a first control level and a second control level
  • second switch drive signal includes a first level and a second level
  • the first logical unit is specifically used for:
  • the control level is generated to control the on-off of the first switch
  • the second logic unit is specifically used for:
  • the second level is generated to drive the second switch to be in the off state.
  • the first control module further includes a first inverter and a second inverter
  • the detection and level shift unit includes a first detection switch, a second detection switch, and a level shift subunit
  • the first terminal of the first inverter is connected to the level shift unit, the first inverter is connected to the second pole of the first switch, and the first inverter is connected to the second inverter phase device;
  • the second inverter is connected to the second pole of the first switch, and the second inverter is connected to the control pole of the first switch;
  • the control pole of the first detection switch is connected between the first inverter and the second inverter, the first pole of the first detection switch is connected to the second power supply, and the first detection switch
  • the second pole is connected to the level shift subunit; the first detection switch is used to: conduct when the first switch is in the on state, and turn off when the first switch is in the off state;
  • the control pole of the second detection switch is connected between the second inverter and the control pole of the first switch, the first pole of the second detection switch is connected to the second power supply, and the second The second pole of the detection switch is connected to the level shift subunit; the second detection switch is used to: conduct when the first switch is in the off state, and conduct when the first switch is in the conduction state off when on;
  • the level shift subunit is connected to the second input end of the second logic unit
  • the level shift subunit is used for:
  • the voltage of the second pole of the first detection switch is stepped down to obtain the conduction state signal of the first switch, and the conduction state signal of the first switch is feeding back the state signal to the second logic unit;
  • the drive circuit also includes capacitors and diodes,
  • the anode of the diode is connected to the second power supply, the cathode of the diode is connected to the first pole of the first detection switch and the first pole of the second detection switch,
  • the first end of the capacitor is connected to the cathode of the diode, and the second end of the capacitor is connected to the second electrode of the first switch.
  • the level shift subunit includes a first transistor, a second transistor, a third transistor and a fourth transistor;
  • the first pole of the first transistor is connected to the second pole of the first detection switch; the control pole of the first transistor and the control pole of the second transistor are connected to the second power supply;
  • the second pole of the first transistor is connected to the first pole of the third transistor and the control pole of the fourth transistor;
  • the first pole of the second transistor is connected to the second pole of the second detection switch, and the second pole of the second transistor is connected to the control pole of the third transistor and the first pole of the fourth transistor;
  • the second pole of the first transistor is connected to the second logic unit.
  • the level shift subunit further includes a third inverter and a fourth inverter;
  • the input end of the third inverter is connected to the second pole of the first transistor, the output end of the third inverter is connected to the input end of the fourth inverter, and the output end of the fourth inverter The output terminal is connected to the second logic unit.
  • the second control module further includes a fifth inverter and a sixth inverter;
  • the fifth inverter is connected to the output terminal of the second logic unit, the fifth inverter is connected to the second power supply, and the fifth inverter is connected to the second pole of the second switch, so The fifth inverter is connected to the sixth inverter;
  • the sixth inverter is connected to the second power supply, the sixth inverter is connected to the second pole of the second switch, and the sixth inverter is connected to the control pole of the second switch.
  • the drive circuit also includes an output matching module,
  • the output matching module is connected to the second pole of the first switch, and the output matching module is connected to ground;
  • the load is connected in parallel between the output matching module and ground.
  • an electronic device including the driving circuit described in the first aspect of the present invention and its optional solutions.
  • the driving circuit and electronic equipment provided by the present invention not only control the on-off of the first switch and the second switch through the first control signal and the second control signal, but also use the signal of the control pole of the first switch as the driving
  • the condition for the second switch to be turned on and off is to use the signal of the control electrode of the second switch as the condition to drive the first switch to be turned on and off.
  • the dead time is set when driving the first switch and the second switch, so as to
  • the actual on-off state of the switch is the control condition, which can detect the change of the on-off state of the two switches in time and accurately, avoiding the simultaneous conduction of the two switches due to the tolerance, and the control is more flexible and accurate;
  • the drive circuit and the electronic device provided by the present invention can effectively avoid the simultaneous conduction of the two switches, and the control accuracy of the first switch and the second switch is high and the loss is low.
  • FIG. 1 is a schematic circuit diagram of a GaN half-bridge system in the prior art
  • Fig. 2 is a circuit schematic diagram 1 of a driving circuit in an embodiment of the present invention.
  • Fig. 3 is a schematic circuit diagram 2 of a driving circuit in an embodiment of the present invention.
  • Fig. 4 is a schematic circuit diagram 3 of a driving circuit in an embodiment of the present invention.
  • Fig. 5 is a circuit schematic diagram 4 of a driving circuit in an embodiment of the present invention.
  • FIG. 6 is a fifth schematic diagram of the driving circuit in an embodiment of the present invention.
  • GaN1-first switch GaN2-first switch; PWM1-first control signal; PWM2-second control signal;
  • Vcc1-first power supply Vcc2-second power supply
  • U1-first inverter U2-second inverter; U3-third inverter; U4-fourth inverter; U5-fifth inverter; U6-sixth inverter;
  • P1-first detection switch P2-second detection switch; N1-first transistor; N2-second transistor; N3-third transistor; N4-fourth transistor;
  • D-diode C1-capacitor; L-matching inductor; C2-matching capacitor.
  • an embodiment of the present invention provides a driving circuit for driving a first switch GaN1 and a second switch GaN2, and further includes: a first control module 1 and a second control module 2;
  • the first control module 1 is connected to the first control signal PWM1, and the first control module is connected to the control electrode of the first switch GaN1; the first control module 1 is used for: monitoring the second switch GaN2 The signal of the gate electrode, according to the first control signal PWM1 and the signal of the gate electrode of the second switch GaN2, generate a first switch drive signal, and use the first switch drive signal to drive the first switch GaN1 On and off;
  • the second control module 2 is connected to the second control signal PWM2, and the second control module 2 is connected to the control electrode of the second switch GaN2; the second control module 2 is used for: monitoring the first switch GaN1 According to the signal of the gate electrode of the second control signal PWM2 and the signal of the gate electrode of the first switch GaN1, a second switch driving signal is generated, and the second switch GaN2 is driven by the second switch driving signal on-off;
  • the first power supply Vcc1 supplies power to the first pole of the first switch GaN1, the second pole of the first switch GaN1 is connected to the first pole of the second switch GaN2, and the second pole of the second switch GaN2 is connected to land;
  • the load is connected in parallel between the first pole of the second switch GaN2 and the ground (for example, between Out+ and Out ⁇ in FIG. 1 .
  • the first control module 1 detects the signal of the control electrode of the second switch GaN2, it can be understood that the signal of the control electrode of the second switch GaN2 can indicate whether the second switch GaN2 is in the on state or the off state, and further, The switch state of the second switch GaN2 can be obtained by detecting the signal of the control electrode of the second switch GaN2, and then the first control module 1 generates the first switch driving signal according to the detected switch state of the second switch GaN2 and the first control signal PWM1
  • the first control module 1 detects the signal of the control pole of the second switch GaN2, it can be directly connected to the control pole of the second switch GaN2 to obtain a switch state signal representing the on-off state of the second switch, or it can be connected to the second control module 2, that is, the second switch driving signal is received;
  • the second control module 2 detects the signal of the gate electrode of the first switch GaN1 for the same reason.
  • the present invention controls the on-off of the first switch and the second switch
  • the signal of the control pole of the first switch is used as the condition for driving the second switch to be on-off
  • the signal of the control pole of the second switch is used as the condition for driving the first switch to be turned on and off.
  • the dead time is set when driving the first switch and the second switch, and the actual on-off state of the switch is used as the control Conditions, the change of the on-off state of the two switches can be detected timely and accurately, avoiding the simultaneous conduction of the two switches due to tolerances, and the control is more flexible and accurate;
  • the driving circuit provided by the present invention can effectively avoid simultaneous conduction of the two switches, and has high control accuracy and low loss for the first switch and the second switch.
  • the first switch GaN1 and the second switch GaN2 are GaN transistors
  • the first electrode of the first switch GaN1 and the control electrode of the second switch GaN2 can be understood as the gate of the GaN transistor
  • the first The first pole of the switch GaN1 and the first pole of the second switch GaN2 can be understood as the drain of the GaN transistor
  • the second pole of the first switch GaN1 and the second pole of the second switch GaN2 can be understood as the source of the GaN transistor.
  • the voltages for driving the conduction of the first switch GaN1 and the second switch GaN2 may be equal or unequal.
  • the first power supply Vcc1 is directly connected to the first pole of the first switch GaN1. In one example, the first power supply Vcc1 is connected to the first pole of the first switch GaN1 after DCDC step-down conversion. In a further example, The first power supply Vcc1 is 48V, which is 12V after step-down.
  • the first control module 1 includes a first logic unit 11, a level shift unit 12;
  • the second control module 2 includes a detection and level shift unit 21, a second logic unit Unit 22;
  • the first input terminal of the first logic unit 11 is connected to the first control signal PWM1, the second input terminal of the first logic unit 11 is connected to the output terminal of the second logic unit 22, and the first The output end of the logic unit 11 is connected to the level shift unit 12; the first logic unit 11 is used to generate: according to the first control signal PWM1 and the second switch drive signal generated by the second logic unit 22 controlling the level, and feeding back the control level to the level shift unit 12;
  • the level shift unit 12 is connected to the second pole of the first switch GaN1, the level shift unit 12 is directly or indirectly connected to the control pole of the first switch GaN1, and the level shift unit 12 is used for: According to the voltage of the second pole of the first switch GaN1, the control level is raised to a target level interval to obtain the first switch drive signal to drive the first switch GaN1 on and off; wherein After the control level is raised to the first drive signal, the difference between the high level and the low level of the control level is equal to the difference between the high level and the low level of the first drive signal, that is, the level shift unit 12 The increase of the control level is an equal increase, not equal or proportional increase;
  • the detection and level shift unit 21 is connected between the level shift unit 12 and the control electrode of the first switch GaN1, and the detection and level shift unit 21 is connected to the first logic unit 22 of the second logic unit 22.
  • Input terminal; the detection and level shift unit 21 is used to: detect the signal of the control pole of the first switch GaN1, step down the signal of the control pole of the first switch GaN1, and obtain The switch state signal of the first switch GaN1 is fed back to the second logic unit 22; the switch state signal represents the on-off state of the corresponding switch; the on-off state includes an on-state and an off-state; for the first
  • the voltage reduction of the signal of the control electrode of the switch GaN1 can be reduced to the control level before the voltage boost, or the voltage range that can match the function of the second logic unit 22 can be suppressed, that is, the voltage boost of the level shift unit 12
  • the amount and the voltage drop of the detection and level shifting unit 21 can be correspondingly equal or unequal;
  • the second input terminal of the second logic unit 22 is connected to the second control signal PWM2, the output terminal of the second logic unit 22 is directly or indirectly connected to the control electrode of the second switch GaN2, and the second The logic unit 22 is configured to: generate the second switch drive signal according to the switch status signal of the first switch GaN1 and the second control signal PWM2, so as to drive the second switch GaN2 on and off;
  • the first logic unit 11 can be understood as a logic gate circuit capable of performing logical operations on the first control signal PWM1 and the second switch drive signal, which can be a single device, such as a NOR gate, or can include multiple devices, such as an OR
  • the combination of gates and NOT gates, such as the combination of logic gates and flip-flops, etc.; the second logic unit 22 is the same, the first logic unit 11 and the second logic unit 22 can be the same, or different devices can be used, as long as they can Just implement the corresponding function.
  • control level is raised to the target level range according to the voltage of the second pole of the first switch through the level shift unit, so that the first switch driving signal can be adapted to the floating second pole of the first switch voltage to ensure that the first switch can be turned on when it needs to be driven on.
  • control level includes a first control level and a second control level
  • second switch drive signal includes a first level and a second level
  • first control level and the first The levels can be equal
  • second control level can be equal to the second level
  • the first logic unit 11 is specifically used for:
  • the second logic unit 22 is specifically used for:
  • the second switch driving signal is generated to drive the second Switch GaN2 on and off;
  • the switch state signal of the first switch GaN1 indicates that the first switch GaN1 is in the on state
  • the second level is generated to drive the second switch GaN2 in the off state.
  • the first switch GaN1 and the second switch GaN2 are N-type GaN transistors, the first control level and the first level are high level, and the second control level and the second level are low level.
  • the first control module 1 further includes a first inverter U1 and a second inverter U2, and the detection and level shift unit 21 includes a first detection switch P1, The second detection switch P2, the level shift subunit 211;
  • the first terminal of the first inverter U1 is connected to the level shift unit 12, the first inverter U1 is connected to the second pole of the first switch GaN1, and the first inverter U1 is connected to the second inverter U2;
  • the second inverter U2 is connected to the second pole of the first switch GaN1, and the second inverter U2 is connected to the control pole of the first switch GaN1;
  • the control pole of the first detection switch P1 is connected between the first inverter U1 and the second inverter U2, the first pole of the first detection switch P1 is connected to the second power supply Vcc2, the The second pole of the first detection switch P1 is connected to the level shift subunit 211; the first detection switch P1 is used to: conduct when the first switch GaN1 is in the conduction state, and conduct when the first switch GaN1 is in the conduction state. Turn off when GaN1 is in the off state;
  • the control pole of the second detection switch P2 is connected between the second inverter U2 and the control pole of the first switch GaN1, and the first pole of the second detection switch P2 is connected to the second power supply Vcc2 , the second pole of the second detection switch is connected to the level shift subunit; the second detection switch is used to: conduct when the first switch GaN1 is in the off state, and when the first switch GaN1 is in the off state, a switch GaN1 is turned off when it is in the conduction state;
  • the level shift subunit 211 is connected to the second input end of the second logic unit 22;
  • the level shift subunit 211 is used for:
  • the voltage of the second pole of the first detection switch P1 is stepped down to obtain the conduction state signal of the first switch GaN1, and the first The conduction state signal of the switch GaN1 is fed back to the second logic unit 22;
  • the first inverter and the second inverter are connected in series between the level shift unit and the control pole of the first switch, which can be used to feed back the first switch to the first detection switch and the second detection switch.
  • the signal of the control pole that is, the on-off of the two detection switches can reflect the on-off of the first switch, and multi-stage inverters can be connected in series to form a buffer to strengthen the current of the first switch drive signal generated by the level shift unit.
  • the driving capability is to drive the on-off of the first switch.
  • the first detection switch P1 and the second detection switch P2 are PMOS transistors
  • the control electrode of the first detection switch P1 and the control electrode of the second detection switch P2 are the gate of the PMOS transistor
  • the second detection switch P1 of the first detection switch P1 One pole and the first pole of the second detection switch P2 are the source of the PMOS transistor
  • the second pole of the first detection switch P1 and the second pole of the second detection switch P2 are the drain of the PMOS transistor.
  • the second power supply Vcc2 is +5V.
  • the level shift subunit 211 includes a first transistor N1, a second transistor N2, a third transistor N3 and a fourth transistor N4;
  • the first pole of the first transistor N1 is connected to the second pole of the first detection switch P1; the control pole of the first transistor N1 and the control pole of the second transistor N2 are connected to the second power supply Vcc2;
  • the second pole of the first transistor N1 is connected to the first pole of the third transistor N3 and the control pole of the fourth transistor N4;
  • the first pole of the second transistor N2 is connected to the second pole of the second detection switch P2, and the second pole of the second transistor N2 is connected to the control pole of the third transistor N3 and the fourth transistor N4 the first pole of
  • the second pole of the third transistor N3 and the second pole of the fourth transistor N4 are grounded;
  • the second pole of the first transistor N1 is connected to the second logic unit 22 .
  • four transistors are used to step down the driving signal of the first switch to obtain the switch state signal of the first switch, and then when logically processing the switch state signal of the first switch and the second control signal,
  • the two signals can be in the same interval to realize more accurate control of the second switch.
  • the first transistor N1, the second transistor N2, the third transistor N3 and the fourth transistor N4 are NMOS transistors, further, the control pole of the transistor is the gate of the NMOS transistor, and the first pole of the transistor is the drain of the NMOS transistor. Pole, the second pole of the transistor is the source of the NMOS tube.
  • the level shift subunit 211 further includes a third inverter U3 and a fourth inverter U4;
  • the input end of the third inverter U3 is connected to the second pole of the first transistor N1, the output end of the third inverter U3 is connected to the input end of the fourth inverter U4, and the fourth The output end of the inverter U4 is connected to the second logic unit 22 .
  • the third inverter and the fourth inverter are connected in series between the second pole of the first transistor and the second logic unit, and can shape the waveform of the output switching state signal of the first switch, A more stable switch state signal is obtained, and a wrong switch state of the first switch is obtained, thereby avoiding the situation that the two switches are turned on at the same time.
  • the second control module 2 further includes a fifth inverter U5 and a sixth inverter U6;
  • the fifth inverter U5 is connected to the output terminal of the second logic unit 22, the fifth inverter U5 is connected to the second power supply Vcc2, and the fifth inverter U5 is connected to the second switch GaN2 The second pole of the fifth inverter U5 is connected to the sixth inverter U6;
  • the sixth inverter U6 is connected to the second power supply Vcc2, the sixth inverter is connected to the second pole of the second switch GaN2, and the sixth inverter U6 is connected to the second switch GaN2 gate.
  • the fifth inverter and the sixth inverter are connected in series between the second logic unit and the control electrode of the second switch, and the buffer can be formed by connecting multi-stage inverters in series to strengthen the second logic unit.
  • the current driving capability of the generated second switch driving signal drives the second switch to be turned on and off.
  • the first logic unit 11 and the second logic unit 22 are NOR gates, namely:
  • the first switch GaN1 When the second switch GaN1 is turned off and the first control signal PWM1 is at low level, the first switch GaN1 is driven to be turned on, and the switch state signal of the first switch GaN1 received by the second logic unit 22 is at high level. level, no matter whether the second control signal PWM2 is high level or low level, the second switch 2 is in the off state;
  • the switch status signal of the first switch GaN1 received by the second logic unit 22 is at low level
  • the second control signal PWM2 is at high level
  • the second switch GaN2 is turned off
  • the second control signal PWM2 is at a low level
  • the second switch GaN2 is driven to be turned on.
  • the drive circuit further includes a capacitor C1 and a diode D,
  • the anode of the diode D is connected to the second power supply Vcc2, the cathode of the diode D is connected to the first pole of the first detection switch P1 and the first pole of the second detection switch P1,
  • a first end of the capacitor C1 is connected to the cathode of the diode D, and a second end of the capacitor C1 is connected to the second electrode of the first switch GaN1.
  • the drive circuit further includes an output matching module 3,
  • the output matching module 3 is connected to the second pole of the first switch GaN1, and the output matching module 3 is connected to ground;
  • the load is connected in parallel between the output matching module 3 and ground.
  • the output matching module 3 includes a matching capacitor C2 and a matching inductor L, the first end of the matching inductor L is connected to the second pole of the first switch GaN1, and the second end of the matching inductor L is connected to the first end of the matching capacitor C2 ; The second end of the matching capacitor C2 is grounded, and the load is connected in parallel to both ends of the matching capacitor C2.
  • the first switch GaN1 and the second switch GaN2 are N-type GaN transistors
  • the first detection switch P1 and the second detection switch P2 are PMOS
  • the first transistor N1, the second transistor N2, the third transistor N3 and the fourth transistor N4 Taking NMOS as an example, the voltage of the second power supply Vcc2 is +5V; the voltage of the first power supply Vcc1 is vin;
  • the gate voltage of the first switch GaN1 is high level, the first inverter U1 outputs a low voltage, and the first detection switch P1 is turned on, the drain voltage Ton of the first detection switch P1 rises to vin+5V, since the initial state of the first transistor N1 is in the conduction state, the gate voltage of the fourth transistor N4 will rise, when the fourth transistor N4 When the gate voltage reaches +5V, the fourth transistor N4 will be turned on, the first transistor N1 and the third transistor N3 will be turned off, and the fourth inverter U4 will feed back the switching state signal TGON of the first switch GaN1 of the NOR gate NOR2 is a high level, the NOR gate NOR2 will output a low level, and the second switch GaN2 remains in an off state, at this time, the second switch driving signal BGON fed back to the NOR gate NOR1 is a low level;
  • the gate voltage of the first switch GaN1 is low level
  • the second inverter U2 outputs a low voltage
  • the second detection switch P2 is turned on
  • the drain voltage Toff of the second detection switch P2 When it rises to +5V, the second transistor N2 is turned off, the third transistor N3 is turned on, the fourth transistor N4 is turned off, and the fourth inverter U4 feeds back the switching state signal TGON of the first switch GaN1 of the NOR gate NOR2 to be low Level
  • the second control signal PWM2 is low level
  • the NOR gate NOR2 will output high level
  • the second switch GaN2 is turned on
  • the second switch drive signal BGON fed back to the NOR gate NOR1 is high level at this time , the first switch GaN1 remains closed; if the second control signal PWM2 is at a high level, the NOR gate NOR2 will output a low level, and the second switch GaN2 is turned off.
  • the present invention can also include a circuit for setting the dead time, and then, the switch state signal detected by the first control module and the second control module can be used as another control condition to prevent the two switches from being turned on at the same time, so as to prevent due to the tolerance of the switch, The set dead time is too short, and the two switches are turned on at the same time.
  • An embodiment of the present invention also provides an electronic device, including the aforementioned drive circuit.

Landscapes

  • Power Conversion In General (AREA)

Abstract

一种驱动电路以及电子设备，包括：第一开关（GaN1）与第二开关（GaN2），第一控制模块（1）、第二控制模块（2）；第一控制模块（1）接入第一控制信号（PWM1），第一控制模块（1）连接第一开关（GaN1）的控制极；第二控制模块（2）接入第二控制信号（PWM2），第二控制模块（2）连接第二开关（GaN2）的控制极；第一电源（Vcc1）向第一开关（GaN1）的第一极供电，第一开关（GaN1）的第二极连接第二开关（GaN2）的第一极，第二开关（GaN2）的第二极连接地。不仅通过第一控制信号（PWM1）和第二控制信号（PWM2）进行控制，还将第一开关（GaN1）的控制极的信号作为驱动第二开关（GaN2）通断的条件，将第二开关（GaN2）的控制极的信号作为驱动第一开关（GaN1）通断的条件，对于第一开关（GaN1）和第二开关（GaN2）的控制准确度高、损耗低。

Description

驱动电路以及电子设备 技术领域
本发明涉及电子技术领域，尤其涉及一种驱动电路以及电子设备。
背景技术
GaN晶体管作为第三代器件，具有更小的体积，更高的工作频率，开关损耗低，适合高频工作。
现有技术的半桥式系统，一般将两个晶体管开关串联，通过在上管和下管之间设置足够的死区时间，避免上管和下管的同时导通，例如图1中采用半桥式驱动器，对输入到H1个L1端口的两个控制信号设置死区时间，避免G1和G2同时导通；虽然死区时间的设置实现起来更加容易，但是对于GaN半桥式系统来讲，由于GaN晶体管工作频率高、周期短，一般设置的死区时间只有几纳秒，工艺的误差很容易导致上管和下管，设置过长的死区时间又会导致系统损耗增加。
发明内容
本发明提供一种驱动电路以及电子设备，以解决GaN半桥式系统控制准确度低、损耗高的问题。
根据本发明的第一方面，提供了一种驱动电路，用于驱动第一开关与第二开关，还包括：第一控制模块、第二控制模块；
所述第一控制模块接入第一控制信号，所述第一控制模块连接所述第一开关的控制极；所述第一控制模块用于：监测所述第二开关的控制极的信号，根据所述第一控制信号以及所述第二开关的控制极的信号，产生第一开关驱动信号，并利用所述第一开关驱动信号驱动所述第一开关的通断；
所述第二控制模块接入第二控制信号，所述第二控制模块连接所述第二开关的控制极；所述第二控制模块用于：监测所述第一开关的控制极的信号，根据所述第二控制信号以及所述第一开关的控制极的信号，产生第二开关驱动信号，并利用所述第二开关驱动信号驱动所述第二开关的通断；
第一电源向所述第一开关的第一极供电，所述第一开关的第二极连接所述第二开关的第一极，所述第二开关的第二极连接地；
负载并联于所述第二开关的第一极与地之间。
可选的，所述第一控制模块包括第一逻辑单元、电平位移单元；所述第二控制模块包括检测与电平位移单元、第二逻辑单元；
所述第一逻辑单元的第一输入端接入所述第一控制信号，所述第一逻辑单元的第二输入端连接所述第二逻辑单元的输出端，所述第一逻辑单元的输出端连接所述电平位移单元；所述第一逻辑单元用于：根据所述第一控制信号以及所述第二逻辑单元产生的第二开关驱动信号，生成控制电平，并将所述控制电平反馈至所述电平位移单元；
所述电平位移单元连接所述第一开关的第二极，所述电平位移单元直接或间接连接所述第一开关的控制极，所述电平位移单元用于：根据所述第一开关的第二极的电压，将所述控制电平提升到目标电平区间，得到所述第一开关驱动信号，以驱动所述第一开关的通断；
所述检测与电平位移单元连接所述电平位移单元与所述第一开关的控制极之间，所述检测与电平位移单元连接所述第二逻辑单元的第一输入端；所述检测与电平位移单元用于：检测所述第一开关的控制极的信号，将所述第一开关的控制极的信号进行降压，并将降压后得到的第一开关的开关状态信号反馈至所述第二逻辑单元；所述开关状态信号表征了对应开关的通断状态；
所述第二逻辑单元的第二输入端接入所述第二控制信号，所述第二逻辑单元的输出端直接或间接连接所述第二开关的控制极，所述第二逻辑单元用于：根据所述第一开关的开关状态信号以及所述第二控制信号，产生所述第二开关驱动信号，以驱动所述第二开关的通断。
可选的，所述控制电平包括第一控制电平和第二控制电平；所述第二开关驱动信号包括第一电平和第二电平；
所述第一逻辑单元具体用于：
当所述第二开关驱动信号为所述第二电平时，根据所述第一控制信号，产生所述控制电平，控制所述第一开关的通断；
当所述第二开关驱动信号为所述第一电平时，产生所述第二控制电平，以使所述第一开关处于所述关断状态；
所述第二逻辑单元具体用于：
当所述第一开关的开关状态信号表征出所述第一开关处于所述关断状态时，根据所述第二控制信号，产生所述第二开关驱动信号，驱动所述第二开关的通断；
当所述第一开关的开关状态信号表征出所述第一开关处于所述导通状态时，产生所述第二电平，驱动所述第二开关处于所述关断状态。
可选的，所述第一控制模块还包括第一反相器、第二反相器，所述检测与电平位移单元包括第一检测开关、第二检测开关、电平位移子单元；
所述第一反相器的第一端连接所述电平位移单元，所述第一反相器连接所述第一开关的第二极，所述第一反相器连接所述第二反相器；
所述第二反相器连接所述第一开关的第二极，所述第二反相器连接所述第一开关的控制极；
所述第一检测开关的控制极连接所述第一反相器与所述第二反相器之间，所述第一检测开关的第一极连接第二电源，所述第一检测开关的第二极连接所述电平位移子单元；所述第一检测开关用于：当所述第一开关处于导通状态时导通，当所述第一开关处于关断状态时关断；
所述第二检测开关的控制极连接所述第二反相器与所述第一开关的控制极之间，所述第二检测开关的第一极连接所述第二电源，所述第二检测开关的第二极连接所述电平位移子单元；所述第二检测开关用于：当所述第一开关处于所述关断状态时导通，当所述第一开关处于所述导通状态时关断；
所述电平位移子单元连接所述第二逻辑单元的第二输入端；
所述电平位移子单元用于：
当所述第一检测开关导通时，将所述第一检测开关的第二极的电压进行降压处理，得到所述第一开关的导通状态信号，并将所述第一开关的导通状态信号反馈至所述第二逻辑单元；
当所述第一检测开关关断时，将所述第二检测开关的第二极的电压进行降压处理，得到所述第一开关的关断状态信号，并将所述第一开关的关断状态信号反馈至所述第二逻辑单元。
可选的，所述驱动电路还包括电容和二极管，
所述二极管的正极连接第二电源，所述二极管的负极连接所述第一检测 开关的第一极和所述第二检测开关的第一极，
所述电容的第一端连接所述二极管的负极，所述电容的第二端连接所述第一开关的第二极。
可选的，所述电平位移子单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管；
所述第一晶体管的第一极连接所述第一检测开关的第二极；所述第一晶体管的控制极和所述第二晶体管的控制极连接所述第二电源；
所述第一晶体管的第二极连接所述第三晶体管的第一极和所述第四晶体管的控制极；
所述第二晶体管的第一极连接所述第二检测开关的第二极，所述第二晶体管的第二极连接所述第三晶体管的控制极和所述第四晶体管的第一极；
所述第三晶体管的第二极和所述第四晶体管的第二极接地；
所述第一晶体管的第二极连接所述第二逻辑单元。
可选的，所述电平位移子单元还包括第三反相器、第四反相器；
所述第三反相的输入端连接所述第一晶体管的第二极，所述第三反相器的输出端连接所述第四反相器的输入端，所述第四反相器的输出端连接所述第二逻辑单元。
可选的，所述第二控制模块还包括第五反相器、第六反相器；
所述第五反相器的连接所述第二逻辑单元的输出端，所述第五反相器连接第二电源，所述第五反相器连接所述第二开关的第二极，所述第五反相器连接所述第六反相器；
所述第六反相器的连接所述第二电源，所述第六反相器连接所述第二开关的第二极，所述第六反相器连接所述第二开关的控制极。
可选的，所述驱动电路还包括输出匹配模块，
所述输出匹配模块连接所述第一开关的第二极，所述输出匹配模块连接地；
所述负载并联于所述输出匹配模块与地之间。
根据本发明的第二方面，提供了一种电子设备，包括本发明第一方面及其可选方案所述的驱动电路。
本发明提供的驱动电路以及电子设备，在控制第一开关和第二开关的通 断时，不仅通过第一控制信号和第二控制信号进行控制，还将第一开关的控制极的信号作为驱动第二开关通断的条件，将第二开关的控制极的信号作为驱动第一开关通断的条件，相比于部分方案中，在驱动第一开关和第二开关时设置死区时间，以开关的实际通断状态为控制条件，可以及时、准确地检测到两个开关通断状态的改变，避免了由于公差造成的两个开关同时导通，控制更加灵活、准确；
因此，本发明提供的驱动电路以及电子设备，可以有效避免两个开关的同时导通，对于第一开关和第二开关的控制准确度高、损耗低。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中GaN半桥式系统的电路示意图；
图2是本发明一实施例中驱动电路的电路示意图一；
图3是本发明一实施例中驱动电路的电路示意图二；
图4是本发明一实施例中驱动电路的电路示意图三；
图5是本发明一实施例中驱动电路的电路示意图四；
图6是本发明一实施例中驱动电路的电路示意图五。
附图标记说明：
1-第一控制模块；2-第二控制模块；3-输出匹配模块；
11-第一逻辑单元；12-电平位移单元；21-检测与电平位移单元；22-第二逻辑单元；211-电平位移子单元；
GaN1-第一开关；GaN2-第一开关；PWM1-第一控制信号；PWM2-第二控制信号；
Vcc1-第一电源；Vcc2-第二电源；
U1-第一反相器；U2-第二反相器；U3-第三反相器；U4-第四反相器；U5-第五反相器；U6-第六反相器；
P1-第一检测开关；P2-第二检测开关；N1-第一晶体管；N2-第二晶体管； N3-第三晶体管；N4-第四晶体管；
D-二极管；C1-电容；L-匹配电感；C2-匹配电容。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
下面以具体地实施例对本发明的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
请参考图2，本发明一实施例提供了一种驱动电路，用于驱动第一开关GaN1与第二开关GaN2，还包括：第一控制模块1、第二控制模块2；
所述第一控制模块1接入第一控制信号PWM1，所述第一控制模块连接所述第一开关GaN1的控制极；所述第一控制模块1用于：监测所述第二开关GaN2的控制极的信号，根据所述第一控制信号PWM1以及所述第二开关GaN2的控制极的信号，产生第一开关驱动信号，并利用所述第一开关驱动信号驱动所述第一开关GaN1的通断；
所述第二控制模块2接入第二控制信号PWM2，所述第二控制模块2连接所述第二开关GaN2的控制极；所述第二控制模块2用于：监测所述第一开关GaN1的控制极的信号，根据所述第二控制信号PWM2以及所述第一开 关GaN1的控制极的信号，产生第二开关驱动信号，并利用所述第二开关驱动信号驱动所述第二开关GaN2的通断；
第一电源Vcc1向所述第一开关GaN1的第一极供电，所述第一开关GaN1的第二极连接所述第二开关GaN2的第一极，所述第二开关GaN2的第二极连接地；
负载并联于所述第二开关GaN2的第一极与地之间(可例如连接于图1中的Out+与Out-之间。
其中的，第一控制模块1检测第二开关GaN2的控制极的信号，可以理解为，第二开关GaN2的控制极的信号可以表征第二开关GaN2是处于导通状态还是关断状态，进而，检测第二开关GaN2的控制极的信号可以得到第二开关GaN2的开关状态，然后第一控制模块1根据检测到的第二开关GaN2的开关状态与第一控制信号PWM1，产生第一开关驱动信号；第一控制模块1在检测第二开关GaN2的控制极的信号时，可以直接连接第二开关GaN2的控制极，得到表征第二开关通断状态的开关状态信号，也可以连接第二控制模块2的输出端，即接收到第二开关驱动信号；
第二控制模块2检测第一开关GaN1的控制极的信号同理。
本发明在控制第一开关和第二开关的通断时，不仅通过第一控制信号和第二控制信号进行控制，还将第一开关的控制极的信号作为驱动第二开关通断的条件，将第二开关的控制极的信号作为驱动第一开关通断的条件，相比于部分方案中，在驱动第一开关和第二开关时设置死区时间，以开关的实际通断状态为控制条件，可以及时、准确地检测到两个开关通断状态的改变，避免了由于公差造成的两个开关同时导通，控制更加灵活、准确；
因此，本发明提供的驱动电路，可以有效避免两个开关的同时导通，对于第一开关和第二开关的控制准确度高、损耗低。
一种举例中，其中的第一开关GaN1和第二开关GaN2为GaN管，进一步地，第一开关GaN1的第一极和第二开关GaN2的控制极可以理解为GaN管的栅极，第一开关GaN1的第一极和第二开关GaN2的第一极可以理解为GaN管的漏极，第一开关GaN1的第二极和第二开关GaN2的第二极可以理解为GaN管的源极。
一种举例中，驱动第一开关GaN1与第二开关GaN2的导通的电压可以 是相等的，也可以是不相等的。
一种举例中，第一电源Vcc1直接连接第一开关GaN1的第一极，一种举例中，第一电源Vcc1经过DCDC降压变换后，连接第一开关GaN1的第一极，进一步举例中，第一电源Vcc1为48V，降压后为12V。
请参考图3，一种实施方式中，所述第一控制模块1包括第一逻辑单元11、电平位移单元12；所述第二控制模块2包括检测与电平位移单元21、第二逻辑单元22；
所述第一逻辑单元11的第一输入端接入所述第一控制信号PWM1，所述第一逻辑单元11的第二输入端连接所述第二逻辑单元22的输出端，所述第一逻辑单元11的输出端连接所述电平位移单元12；所述第一逻辑单元11用于：根据所述第一控制信号PWM1以及所述第二逻辑单元22产生的第二开关驱动信号，生成控制电平，并将所述控制电平反馈至所述电平位移单元12；
所述电平位移单元12连接所述第一开关GaN1的第二极，所述电平位移单元12直接或间接连接所述第一开关GaN1的控制极，所述电平位移单元12用于：根据所述第一开关GaN1的第二极的电压，将所述控制电平提升到目标电平区间，得到所述第一开关驱动信号，以驱动所述第一开关GaN1的通断；其中的控制电平提升为第一驱动信号后，控制电平的高电平与低电平的差值和第一驱动信号的搞电平与低电平的差值是相等的，即电平位移单元12对控制电平的提升为等量的提升，而不等量或等比例地提升；
所述检测与电平位移单元21连接所述电平位移单元12与所述第一开关GaN1的控制极之间，所述检测与电平位移单元21连接所述第二逻辑单元22的第一输入端；所述检测与电平位移单元21用于：检测所述第一开关GaN1的控制极的信号，将所述第一开关GaN1的控制极的信号进行降压，并将降压后得到的第一开关GaN1的开关状态信号反馈至所述第二逻辑单元22；所述开关状态信号表征了对应开关的通断状态；其中的通断状态包括导通状态和关断状态；对于第一开关GaN1的控制极的信号的降压，可以将其降压至升压前的控制电平，也可以将压制能够匹配第二逻辑单元22功能的电压范围，即电平位移单元12的升压量和检测与电平位移单元21的降压量可以是对应相等的，也可以是不相等的；
所述第二逻辑单元22的第二输入端接入所述第二控制信号PWM2，所述 第二逻辑单元22的输出端直接或间接连接所述第二开关GaN2的控制极，所述第二逻辑单元22用于：根据所述第一开关GaN1的开关状态信号以及所述第二控制信号PWM2，产生所述第二开关驱动信号，以驱动所述第二开关GaN2的通断；
其中的第一逻辑单元11可以理解为能够对第一控制信号PWM1以及第二开关驱动信号进行逻辑运算的逻辑门电路，可以为单个器件，例如或非门，也可以包括多个器件，例如或门和非门的组合，再例如采用逻辑门以及触发器的组合等；第二逻辑单元22同理，第一逻辑单元11与第二逻辑单元22可以相同，也可以采用不同的器件，只要能实现对应的功能即可。
以上实施方式中，通过电平位移单元，将控制电平根据第一开关的第二极的电压提升到目标电平区间，使得第一开关驱动信号可以适配浮动的第一开关的第二极的电压，以确保第一开关在需要被驱动导通时，能够打开。
一种实施方式中，所述控制电平包括第一控制电平和第二控制电平；所述第二开关驱动信号包括第一电平和第二电平；其中，第一控制电平与第一电平可以相等，第二控制电平与第二电平可以相等；
所述第一逻辑单元11具体用于：
当所述第二开关驱动信号为所述第二电平时，根据所述第一控制信号，产生所述控制电平，控制所述第一开关GaN1的通断；
当所述第二开关驱动信号为所述第一电平时，产生所述第二控制电平，以使所述第一开关GaN1处于所述关断状态；
所述第二逻辑单元22具体用于：
当所述第一开关GaN1的开关状态信号表征出所述第一开关GaN1处于所述关断状态时，根据所述第二控制信号PWM2，产生所述第二开关驱动信号，驱动所述第二开关GaN2的通断；
当所述第一开关GaN1的开关状态信号表征出所述第一开关GaN1处于所述导通状态时，产生所述第二电平，驱动所述第二开关GaN2处于所述关断状态。
一种举例中，第一开关GaN1与第二开关GaN2为N型GaN管，第一控制电平与第一电平为高电平，第二控制电平与第二电平为低电平。
请参考图4，一种实施方式中，所述第一控制模块1还包括第一反相器 U1、第二反相器U2，所述检测与电平位移单元21包括第一检测开关P1、第二检测开关P2、电平位移子单元211；
所述第一反相器U1的第一端连接所述电平位移单元12，所述第一反相器U1连接所述第一开关GaN1的第二极，所述第一反相器U1连接所述第二反相器U2；
所述第二反相器U2连接所述第一开关GaN1的第二极，所述第二反相器U2连接所述第一开关GaN1的控制极；
所述第一检测开关P1的控制极连接所述第一反相器U1与所述第二反相器U2之间，所述第一检测开关P1的第一极连接第二电源Vcc2，所述第一检测开关P1的第二极连接所述电平位移子单元211；所述第一检测开关P1用于：当所述第一开关GaN1处于导通状态时导通，当所述第一开关GaN1处于关断状态时关断；
所述第二检测开关P2的控制极连接所述第二反相器U2与所述第一开关GaN1的控制极之间，所述第二检测开关P2的第一极连接所述第二电源Vcc2，所述第二检测开关的第二极连接所述电平位移子单元；所述第二检测开关用于：当所述第一开关GaN1处于所述关断状态时导通，当所述第一开关GaN1处于所述导通状态时关断；
所述电平位移子单元211连接所述第二逻辑单元22的第二输入端；
所述电平位移子单元211用于：
当所述第一检测开关P1导通时，将所述第一检测开关P1的第二极的电压进行降压处理，得到所述第一开关GaN1的导通状态信号，并将所述第一开关GaN1的导通状态信号反馈至所述第二逻辑单元22；
当所述第一检测开关P1关断时，将所述第二检测开关P2的第二极的电压进行降压处理，得到所述第一开关GaN1的关断状态信号，并将所述第一开关GaN1的关断状态信号反馈至所述第二逻辑单元22。
以上实施方式中，将第一反相器与第二反相器串联在电平位移单元与第一开关的控制极之间，可以用来向第一检测开关与第二检测开关反馈第一开关的控制极的信号，即两个检测开关的通断可以反映第一开关的通断，也可以多级反相器串联形成缓冲器，加强电平位移单元产生的第一开关驱动信号的电流的驱动能力，驱动第一开关的通断。
一种举例中，第一检测开关P1和第二检测开关P2为PMOS管，第一检测开关P1的控制极和第二检测开关P2的控制极为PMOS管的栅极，第一检测开关P1的第一极和第二检测开关P2的第一极为PMOS管的源极，第一检测开关P1的第二极和第二检测开关P2的第二极为PMOS管的漏极。
一种举例中，第二电源Vcc2为+5V。
请参考图5，一种实施方式中，所述电平位移子单元211包括第一晶体管N1、第二晶体管N2、第三晶体管N3和第四晶体管N4；
所述第一晶体管N1的第一极连接所述第一检测开关P1的第二极；所述第一晶体管N1的控制极和所述第二晶体管N2的控制极连接所述第二电源Vcc2；
所述第一晶体管N1的第二极连接所述第三晶体管N3的第一极和所述第四晶体管N4的控制极；
所述第二晶体管N2的第一极连接所述第二检测开关P2的第二极，所述第二晶体管N2的第二极连接所述第三晶体管N3的控制极和所述第四晶体管N4的第一极；
所述第三晶体管N3的第二极和所述第四晶体管N4的第二极接地；
所述第一晶体管N1的第二极连接所述第二逻辑单元22。
以上实施方式中，通过四个晶体管，实现对第一开关驱动信号的降压，得到第一开关的开关状态信号，进而在对第一开关的开关状态信号与第二控制信号进行逻辑处理时，能够使的两个信号在同一区间，实现对第二开关更加准确的控制。
一种举例中，第一晶体管N1、第二晶体管N2、第三晶体管N3和第四晶体管N4为NMOS管，进一步地，晶体管的控制极为NMOS管的栅极，晶体管的第一极为NMOS管的漏极，晶体管的第二极为NMOS管的源极。
一种实施方式中，所述电平位移子单元211还包括第三反相器U3、第四反相器U4；
所述第三反相U3的输入端连接所述第一晶体管N1的第二极，所述第三反相器U3的输出端连接所述第四反相器U4的输入端，所述第四反相器U4的输出端连接所述第二逻辑单元22。
以上实施方式中，第三反相器和第四反相器串联于第一晶体管的第二极 与第二逻辑单元的之间，可以将输出的第一开关的开关状态信号进行波形的整形，得到更加稳定的开关状态信号，避免得到错误的第一开关的开关状态，进而出现两个开关同时导通的情况。
一种实施方式中，所述第二控制模块2还包括第五反相器U5、第六反相器U6；
所述第五反相器U5的连接所述第二逻辑单元22的输出端，所述第五反相器U5连接第二电源Vcc2，所述第五反相器U5连接所述第二开关GaN2的第二极，所述第五反相器U5连接所述第六反相器U6；
所述第六反相器U6的连接所述第二电源Vcc2，所述第六反相器连接所述第二开关GaN2的第二极，所述第六反相器U6连接所述第二开关GaN2的控制极。
以上实施方式中，将第五反相器与第六反相器串联第二逻辑单元与第二开关的控制极之间，可以通过多级反相器的串联组成缓冲器，加强第二逻辑单元产生的第二开关驱动信号的电流的驱动能力，驱动第二开关的通断。
一种举例中，第一逻辑单元11与第二逻辑单元22为或非门，即：
当第二开关GaN1关断时，且第一控制信号PWM1为低电平时，第一开关GaN1被驱动导通，此时第二逻辑单元22接收到的第一开关GaN1的开关状态信号为高电平，则无论第二控制信号PWM2为高电平还是低电平，第二开关2均处于关断状态；
当第一开关GaN1关断时，此时：第二逻辑单元22接收到的第一开关GaN1的开关状态信号为低电平，当第二控制信号PWM2为高电平时，第二开关GaN2关断，当第二控制信号PWM2为低电平时，第二开关GaN2被驱动导通。
请参考图6，一种是实施方式中，所述驱动电路还包括电容C1和二极管D，
所述二极管D的正极连接第二电源Vcc2，所述二极管D的负极连接所述第一检测开关P1的第一极和所述第二检测开关P1的第一极，
所述电容C1的第一端连接所述二极管D的负极，所述电容C1的第二端连接所述第一开关GaN1的第二极。
一种是实施方式中，所述驱动电路还包括输出匹配模块3，
所述输出匹配模块3连接所述第一开关GaN1的第二极，所述输出匹配模块3连接地；
所述负载并联于所述输出匹配模块3与地之间。
一种举例中，输出匹配模块3包括匹配电容C2和匹配电感L，匹配电感L的第一端连接第一开关GaN1的第二极，匹配电感L的第二端连接匹配电容C2的第一端；匹配电容C2的第二端接地，负载并联于匹配电容C2的两端。
下面结合图6，详细阐述本发明一实施例的工作原理：
图中第一开关GaN1和第二开关GaN2为N型GaN管，第一检测开关P1和第二检测开关P2为PMOS，第一晶体管N1、第二晶体管N2、第三晶体管N3和第四晶体管N4为NMOS为例，第二电源Vcc2的电压为+5V；第一电源Vcc1的电压为vin；
当第一开关GaN1导通时(此时第一控制信号PWM1为低电平)，第一开关GaN1的栅极电压为高电平，第一反相器U1输出低电压，第一检测开关P1导通，第一检测开关P1的漏极电压Ton升高到vin+5V，由于第一晶体管N1初始状态为导通状态，第四晶体管N4的栅极电压会升高，当第四晶体管N4的栅极电压达到+5V时，第四晶体管N4会导通，第一晶体管N1和第三晶体管N3关断，第四反相器U4反馈到或非门NOR2的第一开关GaN1的开关状态信号TGON为高电平，或非门NOR2会输出低电平，第二开关GaN2维持关断状态，此时反馈到或非门NOR1的第二开关驱动信号BGON为低电平；
当第一开关GaN1关断时，第一开关GaN1的栅极电压为低电平，第二反相器U2输出低电压，第二检测开关P2导通，第二检测开关P2的漏极电压Toff升高到+5V，第二晶体管N2关断，第三晶体管N3打开，第四晶体管N4关断，第四反相器U4反馈到或非门NOR2的第一开关GaN1的开关状态信号TGON为低电平，若第二控制信号PWM2为低电平时，或非门NOR2会输出高电平，第二开关GaN2导通，此时反馈到或非门NOR1的第二开关驱动信号BGON为高电平，第一开关GaN1维持关闭状态；若第二控制信号PWM2为高电平时，或非门NOR2会输出低电平，第二开关GaN2关断，此时反馈到或非门NOR1的第二开关驱动信号BGON为低电平，可以通过改变 第一控制信号的高低电平，控制第一开关通断。
本发明还可以包括设置死区时间的电路，进而，第一控制模块和第二控制模块检测到的开关状态信号可以作为防止两个开关同时导通的另一个控制条件，防止由于开关的公差，使得设置的死区时间太短，两个开关出现同时导通。
本发明一实施例还提供了一种电子设备，包括前文所述的驱动电路。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

  1. 一种驱动电路，用于驱动第一开关与第二开关，其特征在于，还包括：第一控制模块、第二控制模块；
    所述第一控制模块接入第一控制信号，所述第一控制模块连接所述第一开关的控制极；所述第一控制模块用于：监测所述第二开关的控制极的信号，根据所述第一控制信号以及所述第二开关的控制极的信号，产生第一开关驱动信号，并利用所述第一开关驱动信号驱动所述第一开关的通断；
    所述第二控制模块接入第二控制信号，所述第二控制模块连接所述第二开关的控制极；所述第二控制模块用于：监测所述第一开关的控制极的信号，根据所述第二控制信号以及所述第一开关的控制极的信号，产生第二开关驱动信号，并利用所述第二开关驱动信号驱动所述第二开关的通断；
    第一电源向所述第一开关的第一极供电，所述第一开关的第二极连接所述第二开关的第一极，所述第二开关的第二极连接地；
    负载并联于所述第二开关的第一极与地之间。
  2. 根据权利要求1所述的驱动电路，其特征在于，所述第一控制模块包括第一逻辑单元、电平位移单元；所述第二控制模块包括检测与电平位移单元、第二逻辑单元；
    所述第一逻辑单元的第一输入端接入所述第一控制信号，所述第一逻辑单元的第二输入端连接所述第二逻辑单元的输出端，所述第一逻辑单元的输出端连接所述电平位移单元；所述第一逻辑单元用于：根据所述第一控制信号以及所述第二逻辑单元产生的第二开关驱动信号，生成控制电平，并将所述控制电平反馈至所述电平位移单元；
    所述电平位移单元连接所述第一开关的第二极，所述电平位移单元直接或间接连接所述第一开关的控制极，所述电平位移单元用于：根据所述第一开关的第二极的电压，将所述控制电平提升到目标电平区间，得到所述第一开关驱动信号，以驱动所述第一开关的通断；
    所述检测与电平位移单元连接所述电平位移单元与所述第一开关的控制极之间，所述检测与电平位移单元连接所述第二逻辑单元的第一输入端；所述检测与电平位移单元用于：检测所述第一开关的控制极的信号，将所述第一开关的控制极的信号进行降压，并将降压后得到的第一开关的开关状态信 号反馈至所述第二逻辑单元；所述开关状态信号表征了对应开关的通断状态；
    所述第二逻辑单元的第二输入端接入所述第二控制信号，所述第二逻辑单元的输出端直接或间接连接所述第二开关的控制极，所述第二逻辑单元用于：根据所述第一开关的开关状态信号以及所述第二控制信号，产生所述第二开关驱动信号，以驱动所述第二开关的通断。
  3. 根据权利要求2所述的驱动电路，其特征在于，所述控制电平包括第一控制电平和第二控制电平；所述第二开关驱动信号包括第一电平和第二电平；
    所述第一逻辑单元具体用于：
    当所述第二开关驱动信号为所述第二电平时，根据所述第一控制信号，产生所述控制电平，控制所述第一开关的通断；
    当所述第二开关驱动信号为所述第一电平时，产生所述第二控制电平，以使所述第一开关处于关断状态；
    所述第二逻辑单元具体用于：
    当所述第一开关的开关状态信号表征出所述第一开关处于所述关断状态时，根据所述第二控制信号，产生所述第二开关驱动信号，驱动所述第二开关的通断；
    当所述第一开关的开关状态信号表征出所述第一开关处于导通状态时，产生所述第二电平，驱动所述第二开关处于所述关断状态。
  4. 根据权利要求2所述的驱动电路，其特征在于，所述第一控制模块还包括第一反相器、第二反相器，所述检测与电平位移单元包括第一检测开关、第二检测开关、电平位移子单元；
    所述第一反相器的第一端连接所述电平位移单元，所述第一反相器连接所述第一开关的第二极，所述第一反相器连接所述第二反相器；
    所述第二反相器连接所述第一开关的第二极，所述第二反相器连接所述第一开关的控制极；
    所述第一检测开关的控制极连接所述第一反相器与所述第二反相器之间，所述第一检测开关的第一极连接第二电源，所述第一检测开关的第二极连接所述电平位移子单元；所述第一检测开关用于：当所述第一开关处于导通状态时导通，当所述第一开关处于关断状态时关断；
    所述第二检测开关的控制极连接所述第二反相器与所述第一开关的控制极之间，所述第二检测开关的第一极连接所述第二电源，所述第二检测开关的第二极连接所述电平位移子单元；所述第二检测开关用于：当所述第一开关处于所述关断状态时导通，当所述第一开关处于所述导通状态时关断；
    所述电平位移子单元连接所述第二逻辑单元的第二输入端；
    所述电平位移子单元用于：
    当所述第一检测开关导通时，将所述第一检测开关的第二极的电压进行降压处理，得到所述第一开关的导通状态信号，并将所述第一开关的导通状态信号反馈至所述第二逻辑单元；
    当所述第一检测开关关断时，将所述第二检测开关的第二极的电压进行降压处理，得到所述第一开关的关断状态信号，并将所述第一开关的关断状态信号反馈至所述第二逻辑单元。
  5. 根据权利要求4所述的驱动电路，其特征在于，还包括电容和二极管，
    所述二极管的正极连接第二电源，所述二极管的负极连接所述第一检测开关的第一极和所述第二检测开关的第一极，
    所述电容的第一端连接所述二极管的负极，所述电容的第二端连接所述第一开关的第二极。
  6. 根据权利要求4所述的驱动电路，其特征在于，所述电平位移子单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管；
    所述第一晶体管的第一极连接所述第一检测开关的第二极；所述第一晶体管的控制极和所述第二晶体管的控制极连接所述第二电源；
    所述第一晶体管的第二极连接所述第三晶体管的第一极和所述第四晶体管的控制极；
    所述第二晶体管的第一极连接所述第二检测开关的第二极，所述第二晶体管的第二极连接所述第三晶体管的控制极和所述第四晶体管的第一极；
    所述第三晶体管的第二极和所述第四晶体管的第二极接地；
    所述第一晶体管的第二极连接所述第二逻辑单元。
  7. 根据权利要求6所述的驱动电路，其特征在于，所述电平位移子单元还包括第三反相器、第四反相器；
    所述第三反相的输入端连接所述第一晶体管的第二极，所述第三反相器 的输出端连接所述第四反相器的输入端，所述第四反相器的输出端连接所述第二逻辑单元。
  8. 根据权利要求2至7任一项所述的驱动电路，其特征在于，所述第二控制模块还包括第五反相器、第六反相器；
    所述第五反相器的连接所述第二逻辑单元的输出端，所述第五反相器连接第二电源，所述第五反相器连接所述第二开关的第二极，所述第五反相器连接所述第六反相器；
    所述第六反相器的连接所述第二电源，所述第六反相器连接所述第二开关的第二极，所述第六反相器连接所述第二开关的控制极。
  9. 根据权利要求1所述的驱动电路，其特征在于，所述第一开关与所述第二开关为GaN晶体管。
  10. 一种电子设备，其特征在于，包括权利要求1至9任一项所述的驱动电路。
PCT/CN2021/118021 2021-09-13 2021-09-13 驱动电路以及电子设备 Ceased WO2023035271A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/118021 WO2023035271A1 (zh) 2021-09-13 2021-09-13 驱动电路以及电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/118021 WO2023035271A1 (zh) 2021-09-13 2021-09-13 驱动电路以及电子设备

Publications (1)

Publication Number Publication Date
WO2023035271A1 true WO2023035271A1 (zh) 2023-03-16

Family

ID=85506980

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/118021 Ceased WO2023035271A1 (zh) 2021-09-13 2021-09-13 驱动电路以及电子设备

Country Status (1)

Country Link
WO (1) WO2023035271A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116667832A (zh) * 2023-07-26 2023-08-29 广东巨风半导体有限公司 一种驱动电路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070085589A1 (en) * 2005-09-29 2007-04-19 Kabushiki Kaisha Toshiba Semiconductor device
CN102843023A (zh) * 2011-06-20 2012-12-26 登丰微电子股份有限公司 晶体管控制电路
CN104410300A (zh) * 2014-11-24 2015-03-11 深圳创维－Rgb电子有限公司 同步整流驱动电路及电视机
US10530258B1 (en) * 2019-01-21 2020-01-07 University Of Electronic Science And Technology Of China Predictive dead time generating circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070085589A1 (en) * 2005-09-29 2007-04-19 Kabushiki Kaisha Toshiba Semiconductor device
CN102843023A (zh) * 2011-06-20 2012-12-26 登丰微电子股份有限公司 晶体管控制电路
CN104410300A (zh) * 2014-11-24 2015-03-11 深圳创维－Rgb电子有限公司 同步整流驱动电路及电视机
US10530258B1 (en) * 2019-01-21 2020-01-07 University Of Electronic Science And Technology Of China Predictive dead time generating circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116667832A (zh) * 2023-07-26 2023-08-29 广东巨风半导体有限公司 一种驱动电路
CN116667832B (zh) * 2023-07-26 2024-04-05 广东巨风半导体有限公司 一种驱动电路

Similar Documents

Publication Publication Date Title
CN102570782B (zh) 用于自举开关驱动器的系统和方法
US8063613B2 (en) Power converter driver with split power supply
US20220321116A1 (en) Gate drive circuit of switching circuit
CN102522066B (zh) 给光源供电的差分驱动电路及驱动系统
US9203309B2 (en) Multi-output boost regulator with single control loop
JP5794855B2 (ja) 電源装置の駆動回路及び電源装置
US8850233B2 (en) Multi-phase voltage regulator module system
US10056845B1 (en) Power conversion apparatus and synchronous rectification controller thereof
US8106901B2 (en) Power circuit and liquid crystal display device using same
CN215835383U (zh) 电子电路
US7551004B2 (en) Inverter apparatus with improved gate drive for power MOSFET
US8390337B2 (en) Electronic device and method for DC-DC conversion
US9595967B2 (en) Level shift circuit and driver circuit
US7911192B2 (en) High voltage power regulation using two power switches with low voltage transistors
CN104917359A (zh) 一种上开关管驱动电路及应用其的同步boost电路
WO2023035271A1 (zh) 驱动电路以及电子设备
US8416006B1 (en) Electronic device with gate driver for high voltage level shifter
US10411581B1 (en) Switching power conversion apparatus and multi-level switching power converter circuit therein
CN113659972B (zh) 驱动电路以及电子设备
CN102469665B (zh) 发光二极管驱动系统及驱动方法
CN104753320A (zh) 用于对半桥进行操作的电路和方法
CN108539973A (zh) Tft-lcd显示器及其驱动电路、开关电源
US20110068832A1 (en) Driving circuit for power mosfet
US20250124844A1 (en) Scan driver
CN112837647A (zh) 一种低功耗显示屏的gip驱动电路及其控制方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21956449

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21956449

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 31/10/2024)

122 Ep: pct application non-entry in european phase

Ref document number: 21956449

Country of ref document: EP

Kind code of ref document: A1