WO2023035136A1 - 用于存储器的数据保护方法及其存储装置 - Google Patents

用于存储器的数据保护方法及其存储装置 Download PDF

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Publication number
WO2023035136A1
WO2023035136A1 PCT/CN2021/117127 CN2021117127W WO2023035136A1 WO 2023035136 A1 WO2023035136 A1 WO 2023035136A1 CN 2021117127 W CN2021117127 W CN 2021117127W WO 2023035136 A1 WO2023035136 A1 WO 2023035136A1
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Prior art keywords
storage
memory
check code
block
data
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PCT/CN2021/117127
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English (en)
French (fr)
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陈永刚
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长江存储科技有限责任公司
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Priority to KR1020237019115A priority Critical patent/KR20230097192A/ko
Priority to CN202311240546.XA priority patent/CN117093156A/zh
Priority to CN202180002502.6A priority patent/CN113966499B/zh
Priority to PCT/CN2021/117127 priority patent/WO2023035136A1/zh
Priority to US17/687,004 priority patent/US20230070503A1/en
Publication of WO2023035136A1 publication Critical patent/WO2023035136A1/zh

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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
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    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
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    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
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    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
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    • G06F3/0689—Disk arrays, e.g. RAID, JBOD

Definitions

  • the present invention generally relates to the technical field of data storage, and more specifically, relates to a method capable of protecting data stored in a memory based on RAID and a storage device thereof.
  • RAID Redundant Array of Independent Disks, Redundant Array of Independent Disks
  • RAID is a disk array formed by combining multiple independent disks in different combinations. Since RAID can provide fault tolerance through data verification/mirroring functions, the security of data storage is enhanced. Therefore, RAID has been widely used in various fields of data storage and data protection.
  • 3D NAND Flash Memory Device In recent years, in order to further increase the bit density and reduce the cost of flash memory devices, three-dimensional (3D) NAND flash memory (3D NAND Flash Memory Device) has been developed. However, in the programming process of 3D NAND flash memory, sometimes programming failure or data programming error occurs, and at this time the data cannot be read from the 3D NAND flash memory, resulting in data loss. With RAID technology, lost data can be recovered. Specifically, performing an "exclusive OR" operation on the successfully programmed data and the check code obtained through all the data to be programmed can restore the lost data.
  • a 3D NAND flash memory may include n memory modules, each memory module including (for example) 2 memory blocks.
  • each memory module including (for example) 2 memory blocks.
  • multiple memory blocks can be programmed in parallel at the same time.
  • data loss of the adjacent memory block 1 in the memory module 1 may also be caused. Since the data of two storage blocks is lost at the same time, if only one check code is generated, the lost data cannot be recovered using RAID technology.
  • a data protection method for a memory includes a plurality of storage modules, each storage module includes a first storage block and a second storage block, the method includes: in the During the programming process of the memory, a first check code is generated based on the storage data of the corresponding first storage block of each of the storage modules in the plurality of storage modules, and based on the storage data of each of the storage modules in the plurality of storage modules generating a second check code from stored data of a corresponding second memory block of the module; and generating an additional check code based on the first check code and the second check code after the programming process of the memory , wherein the additional check code is used to restore data in one of the first storage block and the second storage block of the plurality of storage modules.
  • the memory module is a memory die or a memory plane.
  • the first storage block and the second storage block of each storage module are physically adjacent storage blocks.
  • an XOR operation is performed on the storage data of the corresponding first storage block of each storage module in the plurality of storage modules to generate the first check code, and for the storage modules in the plurality of storage modules
  • the storage data of the corresponding second storage block of each storage module of each storage module performs an exclusive OR operation to generate the second check code, and performs an exclusive OR operation on the first check code and the second check code to generate The additional check code is generated.
  • the memory is 3D NAND flash memory.
  • it further includes the step of using the additional check code and the The data in the one storage block is recovered from the non-lost data stored in the first storage block and the second storage block of the plurality of storage modules.
  • the first check code and the second check code are stored in corresponding caches.
  • it further includes a step of: deleting the first check code and the second check code from the cache after storing the additional check code in the memory.
  • it also includes the step of: before deleting the first check code and the second check code from the cache, based on RAID technology and using the first check code and the second check code
  • the second check code restores the data of one or more storage blocks in the first storage block and the second storage block of the plurality of storage modules.
  • a memory system including: a memory, the memory includes a plurality of storage modules, and each of the storage modules includes a first storage block and a second storage block; and a controller, the The controller is connected to the memory and is configured to: during the programming of the memory, generate a first check based on the storage data of the corresponding first memory block of each of the plurality of memory modules code, and based on the storage data of the corresponding second storage block of each storage module in the plurality of storage modules to generate a second check code; and after the programming process of the memory, based on the first check code code and the second check code to generate an additional check code, wherein the additional check code is used to restore the storage block of one of the first storage block and the second storage block of the plurality of storage modules data.
  • the memory module is a memory die or a memory plane.
  • the first storage block and the second storage block of each storage module are physically adjacent storage blocks.
  • the controller is configured to perform an exclusive OR operation on the stored data of the corresponding first storage block of each of the plurality of storage modules to generate the first check code, for Execute an exclusive OR operation on the storage data of the corresponding second storage block of each storage module in the plurality of storage modules to generate the second check code, and perform an exclusive OR operation on the first check code and the second check code Execute an exclusive OR operation on the verification code to generate the additional verification code.
  • the controller is further configured to store the additional check code in the memory.
  • the memory is 3D NAND flash memory.
  • the controller is configured to use the additional check code in the case of data loss in one of the first storage block and the second storage block of the plurality of storage modules and the non-lost data stored in the first storage block and the second storage block of the plurality of storage modules to recover the data of the one storage block.
  • the controller is further configured to store the first check code and the second check code in a corresponding cache before storing the additional check code in the memory middle.
  • the controller is further configured to delete the first check code and the second check code from the cache after storing the additional check code in the memory .
  • the controller is further configured to use the first check code based on RAID technology before deleting the first check code and the second check code from the cache. performing a recovery operation on the data of one or more storage blocks in the first storage block and the second storage block of the plurality of storage modules together with the second check code.
  • a computer-readable storage medium on which program code is stored, and when the program code is executed by a processor, the processor is made to execute the method according to the present invention.
  • Fig. 1 shows a schematic diagram of a method for recovering data that cannot be recovered by using a check code in the case of data loss in two adjacent storage blocks in the same storage module.
  • Fig. 2 shows a schematic diagram of a data protection method for a memory according to an embodiment of the present disclosure.
  • Fig. 3 shows a schematic diagram of a data protection method for a memory according to yet another embodiment of the present disclosure.
  • FIG. 4 shows a flow chart of a data protection method for a memory according to yet another embodiment of the present disclosure.
  • FIG. 5 shows a schematic diagram of a memory system according to an embodiment of the disclosure.
  • references in the specification to "one embodiment,” “an embodiment,” “some embodiments,” etc. mean that the described embodiments may include particular features, structures, or characteristics, but not necessarily that every embodiment including that particular feature, structure or characteristic. Furthermore, such terms are not necessarily referring to the same embodiment.
  • references in the specification to "one embodiment,” “an embodiment,” “some embodiments,” etc. mean that the described embodiments may include particular features, structures, or characteristics, but not necessarily that every embodiment including that particular feature, structure or characteristic. Furthermore, such terms are not necessarily referring to the same embodiment.
  • references in the specification to "one embodiment,” “an embodiment,” “some embodiments,” etc. mean that the described embodiments may include particular features, structures, or characteristics, but not necessarily that every embodiment including that particular feature, structure or characteristic. Furthermore, such terms are not necessarily referring to the same embodiment.
  • when a particular feature, structure or characteristic is described in conjunction with an embodiment it should be within the knowledge of those skilled in the relevant art to implement such feature, structure or characteristic in combination with other embodiments that are explicitly or not explicitly described.
  • EEPROM Electrically Erasable Programmable ROM
  • NOR Flash Phase Change RAM
  • MRAM Magnetic RAM
  • RRAM resistive RAM
  • FRAM ferroelectric RAM
  • Fig. 2 shows a schematic diagram of a data protection method for a memory according to an embodiment of the present disclosure.
  • the 3D NAND flash memory includes n memory modules, each memory module including (for example) 2 memory blocks.
  • the check code P0 is generated using the stored data in the storage block 0 in the storage module 0, the storage block 0 in the storage module 1, ... the storage block 0 in the storage module n , while using the stored data in the storage block 1 in the storage module 0, the storage block 1 in the storage module 1, ...
  • the storage block 1 in the storage module n to generate another check code P1.
  • Use the check code P0 and the non-lost data stored in the storage block 0 in the storage module 0, the storage block 0 in the storage module 2, the storage block 0 in the storage module 3, ... the storage block 0 in the storage module n can restore the lost data in storage block 0 in storage module 1; ...the unlost data stored in the storage block 1 in the storage module n can recover the lost data in the storage block 1 in the storage module 1.
  • storing the check codes P0 and P1 may occupy a large amount of memory. In the case of limited memory, it may be necessary to store the check codes P0 and P1 in the 3D NAND flash memory cache, which will cause a large number of NAND flash memory caches to be written and read, thereby seriously affecting the speed of data storage.
  • FIG. 3 shows a schematic diagram of a data protection method 300 for a memory according to yet another embodiment of the present disclosure.
  • the 3D NAND flash memory includes storage module 0, storage module 1, storage module 2, ... storage module n.
  • Each memory module includes memory block 0 and memory block 1, for example.
  • a programming failure of a storage block may cause data loss of its physical adjacent storage blocks located in the same storage module .
  • a programming failure of memory block 0 in memory module 1 may result in data loss for memory block 1 in memory module 1 (which is physically adjacent to memory block 0).
  • the check code P0 is generated based on the data stored in the storage block 0 in the storage module 0, the storage block 0 in the storage module 1, the storage block 0 in the storage module 2, ... the storage block 0 in the storage module n . Additionally, another check is generated based on the data stored in block 1 in block 0, block 1 in block 1, block 1 in block 2, ... block 1 in block n Code P1.
  • the storage modules may be physically adjacently arranged.
  • the check codes P0 and P1 generated during the programming process can be temporarily stored in the corresponding cache and occupy a certain cache space; it will be understood that after deleting the temporarily stored check codes P0 and P1 from the cache Before, similar to the method of the embodiment shown in FIG. 2 , a certain Data lost in block 0 and block 1 of a memory module.
  • the check code P0 can be passed to the storage block 0 in the storage module 0, the storage block 0 in the storage module 1, the storage block 0 in the storage module 2, ... the storage block 0 in the storage module n
  • Exclusive OR (XOR) operation is performed on the data stored in to generate
  • the check code P1 can be generated by the storage block 1 in the storage module 0, the storage block 1 in the storage module 1, and the storage block 1 in the storage module 2 , ...
  • the data stored in the storage block 1 in the storage module n is generated by performing an "exclusive OR" (XOR) operation.
  • XOR can be a logical operation on two operands, it produces a logical value "1" if the two values that are “exclusively ORed” are different; if the two values that are “exclusively ORed” are the same, it produces a logical value "0".
  • the inventors have discovered through research that a programming failure of a memory block may lead to data loss in another memory block that is physically adjacent to it and located in the same memory module, and generally occurs in the programming stage. That is to say, once the programming of the 3D NAND flash memory is completed, even if the data of a certain memory block (such as the memory block 0 in the memory module 1) is lost due to the lapse of time during the data retention phase, for example, it will not cause the memory block located in the same memory block Loss of data stored in a storage block physically adjacent to the same storage module (for example, storage block 1 in storage module 1). Therefore, 3D NAND flash memory only has data loss in at most one storage block during the data retention phase.
  • the method of the embodiment shown in FIG. 3 is different from the method of the embodiment shown in FIG. 2 in that in the programming stage or after the programming is completed, an additional check code is further generated based on the check code P0 and the check code P1 p.
  • the additional check code P and the non-lost data stored in the storage block 0 and the storage block 1 of the n storage modules are used to restore the data lost in a certain storage block in the data retention phase.
  • the additional check code P can also be generated by performing an "exclusive OR" (XOR) operation on the check codes P0 and P1. After the additional parity code P is generated, it can be stored in the 3D NAND flash memory cache.
  • the temporarily stored first check code P0 and the second check code P1 can be deleted from the cache.
  • the additional check code P is obtained based on the check code P0 and the check code P1, which can be based on the additional check code P and the storage blocks 0 and 1 of the n memory modules
  • the stored non-lost data is used to recover the lost data in a storage block after the programming operation is completed, and the check code data that needs to be stored is greatly reduced, thereby reducing the corresponding demand such as memory usage.
  • the additional check code P needs to be stored in the 3D NAND flash memory cache, it will greatly reduce the number of reads and writes of the 3D NAND flash memory cache, improve system performance, and reduce equipment loss.
  • each storage module includes two storage blocks, namely storage block 0 and storage block 1 .
  • each storage module may include multiple storage blocks, for example, each storage module may include storage block 0, storage block 1, storage block 2, ... storage block n.
  • an "exclusive OR" operation can be performed on each corresponding storage block of storage module 0 to storage module n, so as to obtain n check codes, for example, P0, P1, P2, . . . Pn.
  • the " Exclusive OR" (XOR) operation to generate check code P0; for storage block 1 in storage module 0, storage block 1 in storage module 1, storage block 1 in storage module 2, ...
  • the storage module may be a storage plane (Plane), and each storage plane may include multiple storage blocks.
  • the 3D NAND flash memory may include, for example, four storage planes, and each storage plane may include, for example, six storage blocks.
  • Each memory block may include a plurality of memory cells arranged in a vertical memory string (Memory String), where each memory cell may be addressed through interconnections such as bit lines and word lines.
  • the memory module may also be a memory die.
  • Fig. 4 shows a flowchart of a data protection method 400 for a memory according to an embodiment of the present invention.
  • the memory includes a plurality of storage modules, and each storage module includes a first storage block and a second storage block.
  • the method 400 includes: during the programming process of the memory, generating a first check code based on the storage data of the corresponding first storage block of each storage module in the plurality of storage modules, And generate a second check code based on the storage data of the corresponding second storage block of each storage module in the plurality of storage modules (step S410); and after the programming process of the memory, based on the first A check code and the second check code are used to generate an additional check code, wherein the additional check code is used to restore one of the first storage block and the second storage block of the plurality of storage modules to store block data (step S420). Steps 410 and 420 are described as follows:
  • Step S410 During the programming process of the memory, generate a first check code based on the storage data of the corresponding first storage block of each of the multiple storage modules, and based on the multiple storage modules The storage data of the corresponding second storage block of each storage module in the storage module is used to generate the second check code.
  • each storage module in storage module 0, storage module 1, storage module 2, ... storage module n includes two storage blocks (such as storage block 0 , storage block 1), based on storage block 0 in storage module 0, storage block 0 in storage module 1, storage block 0 in storage module 2, ...
  • the first storage block and the second storage block (eg, storage block 0, storage block 1) of each storage module are physically adjacent storage blocks.
  • Step S420 After the programming process of the memory, generate an additional check code based on the first check code and the second check code, wherein the additional check code is used to recover the multiple One of the first storage block and the second storage block of the storage module stores data of the block.
  • an "exclusive OR" operation is performed on the check code P0 and the check code P1 to generate an additional check code P.
  • each storage module in storage module 0, storage module 1, storage module 2, ... storage module n includes n storage blocks, after the programming process, for example, the check code P0, calibration The check code P1, check code P2, ... check code Pn performs an "exclusive OR" operation to generate an additional check code P.
  • it also includes storing the additional check code P in the 3D NAND flash memory, for example, a certain part of the storage array of the 3D NAND flash memory can be pre-determined as a cache for storing the additional check code area.
  • the generated additional check code P and the non-lost data stored in the first storage block and the second storage block of the plurality of storage modules it is possible to recover the loss of a certain storage block of the memory after the programming process.
  • the data For example, still taking the method shown in FIG. 3 as an example, assume that after the programming process, the data stored in the memory block 0 of the memory module 1 is lost.
  • the generated additional check code P can be firstly performed with the data stored in the storage block 1 of the storage module n to perform an "exclusive OR” operation, and then the obtained result can be combined with the storage module
  • the data stored in the storage block 1 of n-1 performs the "exclusive OR” operation again until the result of sequentially performing the "exclusive OR” operation and the data stored in the storage block 1 of the storage module 0 perform the "exclusive OR” operation again, Then perform an "exclusive OR” operation with the result of the n times of "exclusive OR” operations and the data stored in the storage block 0 of the storage module n, and then combine the obtained result with the data stored in the storage block 0 of the storage module n-1 Execute the "exclusive OR” operation again until the results of the sequential execution of the "exclusive OR” operation and the data stored in the storage block 0 of the storage module 2 perform the "exclusive OR” operation again, thereby obtaining the above-mentioned total 2n-2 times of "exclusive OR”
  • the data stored in the storage block 1 of n-1 performs
  • FIG. 5 shows a schematic diagram of a system 500 with memory according to an embodiment of the disclosure.
  • System 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, game console, printer, pointing device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or Any other suitable electronic device for memory.
  • system 500 may include a host 510 and a memory system 520 having one or more memories 501 and a memory controller 502 .
  • Host 510 may be configured to send data to or receive data from memory 501 .
  • Memory 501 may be any memory disclosed herein, such as 3D NAND flash memory, which includes a plurality of memory modules (e.g., memory dies), each memory module including a first memory block and a second memory block, as detailed above stated.
  • 3D NAND flash memory which includes a plurality of memory modules (e.g., memory dies), each memory module including a first memory block and a second memory block, as detailed above stated.
  • the memory controller 502 includes a front-end interface 5021 and a back-end interface 5022, the front-end interface 5021 is coupled to the host 510 through channels Lane 0, Lane 1, Lane2, and Lane3, and the back-end interface 5022 is coupled to the host 510 through channels CH1, CH2, CH3, and CH4 are coupled to the memory 501, wherein the front-end interface 5021 can communicate with the host 510 according to a specific communication protocol (for example, PCIe, NVMe);
  • a specific communication protocol for example, PCIe, NVMe
  • the first check code is generated based on the storage data of the corresponding first storage block of each storage module in the multiple storage modules of the memory 501, and based on the corresponding storage data of each storage module in the multiple storage modules
  • the stored data of the second storage block is used to generate a second check code; and after the programming process of the memory 501, an additional check code is generated based on the first check code and the second check code for use in The lost data of one memory block of the memory 501 is
  • the memory controller 502 also includes a processing module 5023 having a processing unit 1, a processing unit 2, ..., a processing unit n, and the corresponding processing unit can be configured with corresponding firmware, for example, to realize FTL (Flash to Logic, flash memory to logic) function
  • the corresponding firmware running on the processing unit can control the operations of the memory 501 based on instructions received from the host 510, such as read, erase and program operations.
  • Memory controller 502 also includes static random access memory (SRAM) 5024, dynamic random access memory (DRAM) controller 5025, dynamic random access memory (DRAM) interface 5026, wherein dynamic random access memory (DRAM) interface 5026 Coupled to dynamic random access memory (DRAM) 503 .
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM dynamic random access memory
  • DRAM dynamic random access memory
  • DRAM dynamic random access memory
  • DRAM dynamic random access memory
  • DRAM dynamic random access memory
  • DRAM dynamic random access memory
  • DRAM dynamic random access memory
  • the memory system 520 can recover the data loss of a plurality of memory blocks during the programming process of the memory 501, and after the programming process, the memory system 520 based on the first memory block and An XOR operation is added to the check codes respectively obtained from the second storage blocks of the plurality of storage modules, so that the lost data of a certain storage block in the data retention stage memory 501 can be recovered, and the check code data that needs to be stored Greatly reduced and reduced memory usage.
  • the verification code data needs to be stored in the memory cache, the number of reads and writes of the memory cache will be greatly reduced, the system performance will be improved, and equipment loss will be reduced.
  • a computer-readable storage medium on which program codes are stored, and when the program codes are executed by a processor, the processors can perform the operations described in this specification in conjunction with FIGS. 2-3 .
  • a system or device equipped with a readable storage medium can be provided, on which a software program code for realizing the functions of any one of the above embodiments is stored, and the computer or device of the system or device can The processor reads and executes the instructions stored in the readable storage medium.
  • Examples of the readable storage medium include nonvolatile memory cards, ROMs, and the like.
  • the program code can be downloaded from a server computer or cloud via a communication network.
  • the execution order of each step is not fixed, and can be determined as required.
  • the device structures described in the above embodiments may be physical structures or logical structures, that is, some units may be realized by the same physical entity, or some units may be realized by multiple physical entities, or may be realized by multiple physical entities. Certain components in individual devices are implemented together.
  • Controllers have been described in connection with various apparatus and methods.
  • the controller may be implemented using electronic hardware, computer software, or any combination thereof. Whether the controller is implemented as hardware or software will depend upon the particular application and overall design constraints imposed on the system.
  • a controller, any portion of a controller, or any combination of controllers presented in this disclosure may be implemented as a microprocessor, microcontroller, digital signal processor (DSP), field programmable gate array (FPGA) ), programmable logic devices (PLDs), state machines, gate logic, discrete hardware circuits, and other suitable processing components configured to perform the various functions described in this disclosure.
  • DSP digital signal processor
  • FPGA field programmable gate array
  • PLDs programmable logic devices
  • state machines gate logic, discrete hardware circuits, and other suitable processing components configured to perform the various functions described in this disclosure.
  • the functionality of the controller, any portion of the controller, or any combination of controllers presented in this disclosure may be implemented as software executed by a microprocessor, microcontroller, DSP, or other

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Abstract

一种能够基于RAID来保护存储器中存储的数据的方法及其存储装置，所述存储器包括多个存储模块，每个存储模块包括第一存储块和第二存储块，所述方法包括：在所述存储器的编程过程中，基于所述多个存储模块中的每个存储模块的相应第一存储块的存储数据来生成第一校验码，并且基于所述多个存储模块中的每个存储模块的相应第二存储块的存储数据来生成第二校验码（S410）；以及在所述存储器的编程过程之后，基于所述第一校验码和所述第二校验码来生成附加校验码，其中，所述附加校验码用于恢复所述多个存储模块的第一存储块和第二存储块中的其中一个存储块的数据（S420）。

Description

用于存储器的数据保护方法及其存储装置 技术领域
本发明总体上涉及数据存储技术领域，以及更具体地，涉及一种能够基于RAID来保护存储器中存储的数据的方法及其存储装置。
背景技术
RAID(Redundant Array of Independent Disks，独立磁盘冗余阵列)是将多个独立磁盘通过不同的组合方式组合在一起形成的磁盘阵列。由于RAID可以通过数据校验/镜像功能提供容错，从而增强了数据存储的安全性。因此，RAID已经广泛应用于数据存储和数据保护的各个领域中。
近年来，为了进一步提高闪速存储器件的位密度以及降低其成本，开发出了三维(3D)NAND闪存存储器(3D NAND Flash Memory Device)。但是，在3D NAND闪存存储器的编程过程中，有时会编程失败或数据编程错误，这时数据无法从3D NAND闪存存储器读出，造成数据丢失。利用RAID技术，可以恢复丢失的数据。具体地说，对编程成功的数据以及通过所有待编程的数据获得的校验码执行“异或”操作可以恢复丢失的数据。
如图1中所示，3D NAND闪存存储器可以包括n个存储模块，每个存储模块包括(例如)2个存储块。为了提高编程速度，可以同时对多个存储块并行编程。但是，当对存储模块1中的存储块0编程失败时，还可能伴随导致存储模块1中的相邻存储块1的数据丢失。由于同时有两个存储块的数据丢失，如果只生成一个校验码，将无法利用RAID技术恢复丢失的数据。
因此，需要一种用于存储器的数据保护方法及其存储装置，其能够在存储器中的多个存储块数据丢失时恢复丢失的数据。
发明内容
根据本公开的实施例，提供了一种用于存储器的数据保护方法，所述 存储器包括多个存储模块，每个存储模块包括第一存储块和第二存储块，所述方法包括：在所述存储器的编程过程中，基于所述多个存储模块中的每个存储模块的相应第一存储块的存储数据来生成第一校验码，并且基于所述多个存储模块中的每个存储模块的相应第二存储块的存储数据来生成第二校验码；以及在所述存储器的编程过程之后，基于所述第一校验码和所述第二校验码来生成附加校验码，其中，所述附加校验码用于恢复所述多个存储模块的第一存储块和第二存储块中的其中一个存储块的数据。
在一些实施例中，所述存储模块为存储管芯或存储面。
在一些实施例中，每个存储模块的所述第一存储块和所述第二存储块为物理相邻的存储块。
在一些实施例中，对所述多个存储模块中的每个存储模块的相应第一存储块的存储数据执行异或操作来生成所述第一校验码，对所述多个存储模块中的每个存储模块的相应第二存储块的存储数据执行异或操作来生成所述第二校验码，并且对所述第一校验码和所述第二校验码执行异或操作来生成所述附加校验码。
在一些实施例中，还包括将所述附加校验码存储至所述存储器。
在一些实施例中，所述存储器为3D NAND闪存存储器。
在一些实施例中，还包括步骤：在所述多个存储模块的第一存储块和第二存储块中的其中一个存储块发生数据丢失的情况下，使用所述附加校验码以及所述多个存储模块的第一存储块和第二存储块中存储的未丢失的数据来恢复所述一个存储块的数据。
在一些实施例中，在将所述附加校验码存储至所述存储器之前，所述第一校验码和所述第二校验码被存储在相应的缓存中。
在一些实施例中，还包括步骤：在将所述附加校验码存储至所述存储器之后，从所述缓存中删除所述第一校验码和所述第二校验码。
在一些实施例中，还包括步骤：在从所述缓存中删除所述第一校验码和所述第二校验码之前，基于RAID技术并且使用所述第一校验码和所述第二校验码对所述多个存储模块的第一存储块和第二存储块中的一个或多个存储块的数据进行恢复操作。
根据本公开的实施例，提供了一种存储器系统，包括：存储器，所述 存储器包括多个存储模块，并且每个所述存储模块包括第一存储块和第二存储块；以及控制器，所述控制器连接至所述存储器并且被配置为：在所述存储器的编程过程中，基于所述多个存储模块中的每个存储模块的相应第一存储块的存储数据来生成第一校验码，并且基于所述多个存储模块中的每个存储模块的相应第二存储块的存储数据来生成第二校验码；以及在所述存储器的编程过程之后，基于所述第一校验码和所述第二校验码来生成附加校验码，其中，所述附加校验码用于恢复所述多个存储模块的第一存储块和第二存储块中的其中一个存储块的数据。
在一些实施例中，所述存储模块为存储管芯或存储面。
在一些实施例中，每个存储模块的所述第一存储块和所述第二存储块为物理相邻的存储块。
在一些实施例中，所述控制器被配置为对所述多个存储模块中的每个存储模块的相应第一存储块的存储数据执行异或操作来生成所述第一校验码，对所述多个存储模块中的每个存储模块的相应第二存储块的存储数据执行异或操作来生成所述第二校验码，并且对所述第一校验码和所述第二校验码执行异或操作来生成所述附加校验码。
在一些实施例中，所述控制器还被配置为将所述附加校验码存储至所述存储器。
在一些实施例中，所述存储器为3D NAND闪存存储器。
在一些实施例中，所述控制器被配置为在所述多个存储模块的第一存储块和第二存储块中的其中一个存储块发生数据丢失的情况下，使用所述附加校验码以及所述多个存储模块的第一存储块和第二存储块中存储的未丢失的数据来恢复所述一个存储块的数据。
在一些实施例中，所述控制器还被配置为在将所述附加校验码存储至所述存储器之前，将所述第一校验码和所述第二校验码存储在相应的缓存中。
在一些实施例中，所述控制器还被配置为在将所述附加校验码存储至所述存储器之后，从所述缓存中删除所述第一校验码和所述第二校验码。
在一些实施例中，所述控制器还被配置为在从所述缓存中删除所述第一校验码和所述第二校验码之前，基于RAID技术并且使用所述第一校验 码和所述第二校验码对所述多个存储模块的第一存储块和第二存储块中的一个或多个存储块的数据进行恢复操作。
根据本公开的实施例，提供了一种计算机可读存储介质，在其上存储有程序代码，当所述程序代码由处理器执行时，使得所述处理器执行根据本发明所述的方法。
附图说明
附图被并入本文并形成说明书的一部分，例示了本公开的实施例并与说明书一起进一步用以解释本公开的原理，并使相关领域的技术人员能够做出和使用本公开。
图1示出了在同一存储模块中的两相邻存储块数据丢失的情况下利用一个校验码将无法恢复数据的方法的示意图。
图2示出了根据本公开一实施例的用于存储器的数据保护方法的示意图。
图3示出了根据本公开又一实施例的用于存储器的数据保护方法的示意图。
图4示出了根据本公开再一实施例的用于存储器的数据保护方法的流程图；以及
图5示出了根据本公开一实施例的存储器系统的示意图。
具体实施方式
现在将参考示例实施方式讨论本文描述的主题。应该理解，讨论这些实施方式只是为了使得本领域技术人员能够更好地理解从而实现本文描述的主题，并非是对权利要求书中所阐述的保护范围、适用性或者示例的限制。可以在不脱离本说明书内容的保护范围的情况下，对所讨论的元素的功能和排列进行改变。各个示例可以根据需要，省略、替代或者添加各种过程或组件。例如，所描述的方法可以按照与所描述的顺序不同的顺序来执行，以及各个步骤可以被添加、省略或者组合。另外，相对一些示例所描述的特征在其它例子中也可以进行组合。
要指出的是，在说明书中提到“一个实施例”、“实施例”、“一些实施 例”等表示所述的实施例可包括特定的特征、结构或特性，但未必每个实施例都包括该特定特征、结构或特性。此外，这样的措辞用语未必是指相同的实施例。另外，在结合实施例描述特定的特征、结构或特性时，结合明确或未明确描述的其它实施例实现此类特征、结构或特性应在相关领域技术人员的知识范围之内。
尽管将参考3D NAND闪存存储器来描述本发明的实施例，但应当理解，本发明创造性概念的实施例不限于此配置。例如，在不脱离本发明的范围的情况下，本发明适用于其他非易失性存储器件，例如电可擦除可编程ROM(EEPROM)、NOR闪存、相变RAM(PRAM)、磁RAM(MRAM)、电阻RAM(RRAM)、铁电RAM(FRAM)等。
图2示出了根据本公开一实施例的用于存储器的数据保护方法的示意图。与图1中所示的一样，3D NAND闪存存储器包括n个存储模块，每个存储模块包括(例如)2个存储块。同样地，当对存储模块1的存储块0编程失败时，可能伴随导致存储模块1中的相邻存储块1的数据丢失。但是，与图1中所示不同的是，利用存储模块0中的存储块0、存储模块1中的存储块0、……存储模块n中的存储块0中的存储数据生成校验码P0，同时利用存储模块0中的存储块1、存储模块1中的存储块1、……存储模块n中的存储块1中的存储数据生成另一校验码P1。利用校验码P0以及存储模块0中的存储块0、存储模块2中的存储块0、存储模块3中的存储块0、……存储模块n中的存储块0中存储的未丢失的数据，可以恢复存储模块1中的存储块0中丢失的数据；并且利用校验码P1以及存储模块0中的存储块1、存储模块2中的存储块1、存储模块3中的存储块1、……存储模块n中的存储块1中存储的未丢失的数据，可以恢复存储模块1中的存储块1中丢失的数据。但是，在这种情况下，存储校验码P0和P1可能占用大量的内存。在内存有限的情况下，可能需要将校验码P0和P1存储至3D NAND闪存存储器缓存中，这将导致大量的NAND闪存存储器缓存的写入和读出，从而严重影响数据存储的速度。
图3示出了根据本公开又一实施例的用于存储器的数据保护方法300的示意图。如图3中所示，3D NAND闪存存储器包括存储模块0、存储模块1、存储模块2、……存储模块n。每个存储模块例如包括存储块0和存 储块1。
在对3D NAND闪存存储器的多个存储模块中的多个存储块并行编程时，有时候一个存储块(Block)的编程失败可能导致与其物理相邻并且位于同一存储模块中的存储块的数据丢失。例如，存储模块1中的存储块0的编程失败可能导致存储模块1中的存储块1(其与存储块0物理相邻)的数据丢失。
在一实施例中，为了利用RAID技术同时找回存储模块1的存储块0和存储块1中丢失的数据(例如因为编程过程中编程错误等所丢失的数据)，与图2中所示的一样，基于存储模块0中的存储块0、存储模块1中的存储块0、存储模块2中的存储块0、……存储模块n中的存储块0中存储的数据来生成校验码P0。另外，基于存储模块0中的存储块1、存储模块1中的存储块1、存储模块2中的存储块1、……存储模块n中的存储块1中存储的数据来生成另一校验码P1。也就是说，为多个存储模块上的第一存储块和对应该多个存储模块的第二存储块分别准备不同的校验码(例如P0和P1)，第一存储块和第二存储块在存储模块上可以物理相邻地布置。在一实施例中，编程过程中生成的校验码P0、P1可以临时地存储在相应的缓存中并占用一定的缓存空间；将理解，在从缓存中删除临时存储的校验码P0、P1之前，与图2中所示实施例的方法类似，利用编程过程中生成的校验码P0、P1以及n个存储模块的存储块0和存储块1中存储的未丢失的数据，能够恢复某一存储模块的存储块0和存储块1中丢失的数据。
在一实施例中，校验码P0可以通过对存储模块0中的存储块0、存储模块1中的存储块0、存储模块2中的存储块0、……存储模块n中的存储块0中存储的数据执行“异或”(XOR)操作来生成，并且校验码P1可以通过对存储模块0中的存储块1、存储模块1中的存储块1、存储模块2中的存储块1、……存储模块n中的存储块1中存储的数据执行“异或”(XOR)操作来生成。XOR可以是对两个操作数的逻辑运算，如果进行“异或”的两个值不同，则它产生逻辑值“1”；如果进行“异或”的两个值相同，则它产生逻辑值“0”。例如，如果存储模块0的存储块0存储的数据为“11001010”，并且存储模块1的存储块0存储的数据为“10000011”，则“异或”之后的结果为“01001001”；接下来，将上述结果与存储模块2的 存储块0中存储的数据再执行“异或”操作，直至执行n-2次“异或”操作之后将所得的结果与存储模块n的存储块0中存储的数据再执行“异或”操作，从而计算得到n个存储模块的对应存储块0的校验码P0。类似地，可以得到n个存储模块的对应存储块1的校验码P1。
发明人研究发现，一个存储块的编程失败可能导致与其物理相邻并且位于同一存储模块中的另一存储块发生数据丢失，并且一般发生在编程阶段。也就是说，一旦3D NAND闪存存储器编程完成，即使例如在数据保持阶段因为随着时间的流逝导致某一存储块(例如存储模块1中的存储块0)的数据丢失，也不会导致与其位于同一存储模块中并且与其物理相邻的存储块(例如存储模块1中的存储块1)中存储的数据的丢失。因此，3D NAND闪存存储器在数据保持阶段最多只有一个存储块存在数据丢失。
鉴于此考虑，图3所示实施例的方法与图2所示实施例的方法不同的是，在编程阶段或编程完成后，进一步基于校验码P0和校验码P1来生成附加校验码P。利用该附加校验码P以及n个存储模块的存储块0和存储块1中存储的未丢失的数据来恢复在数据保持阶段某一个存储块中丢失的数据。在一实施例中，附加校验码P同样可以通过对校验码P0和P1执行“异或”(XOR)操作来生成。在生成附加校验码P之后，可以将其存储至3D NAND闪存存储器缓存中。在一个实施例中，在将附加校验码P存储至3D NAND闪存存储器缓存之后，可以从所述缓存中删除临时存储的第一校验码P0和第二校验码P1。
在图3所示实施例的方法300中，在3D NAND闪存存储器的编程过程中，即使例如存储模块1中的存储块0的编程失败导致存储模块1中的存储块1也发生数据丢失，由于校验码P0和校验码P1的存在，能够恢复存储模块1中的存储块0和存储块1中丢失的数据。另外，通过增加的“异或”操作，基于校验码P0和校验码P1获得附加校验码P，能够基于该附加校验码P以及n个存储模块的存储块0和存储块1中存储的未丢失的数据来恢复在编程操作完成之后某一存储块中丢失的数据，并且使得需要存储的校验码数据大大减小，从而减少相应的例如内存的用量需求。在需要将附加校验码P存储至3D NAND闪存存储器缓存中时，将大大减少3D NAND闪存存储器缓存的读写次数，提高系统性能，减少设备损耗。
在图3所示的方法中，每个存储模块包括两个存储块，即存储块0和存储块1。但是对于本领域技术人员来说，每个存储模块可以包括多个存储块，例如每个存储模块可以包括存储块0、存储块1、存储块2、……存储块n。在这种情况下，可以分别对存储模块0至存储模块n的每个相应存储块执行“异或”操作，从而得到n个校验码，例如，P0、P1、P2、……Pn。示例地，可以通过对存储模块0中的存储块0、存储模块1中的存储块0、存储模块2中的存储块0、……存储模块n中的存储块0中存储的数据依次执行“异或”(XOR)操作来生成校验码P0；对存储模块0中的存储块1、存储模块1中的存储块1、存储模块2中的存储块1、……存储模块n中的存储块1中存储的数据依次执行“异或”(XOR)操作来生成校验码P1；…….对存储模块0中的存储块n、存储模块1中的存储块n、存储模块2中的存储块n、……存储模块n中的存储块n中存储的数据依次执行“异或”(XOR)操作来生成校验码Pn。然后，可以对校验码P0、P1、P2、……Pn执行“异或”(XOR)操作来生成附加校验码P。
在图3所示的方法中，存储模块可以为存储面(Plane)，每个所述存储面可以包括多个存储块。在一个实施例中，3D NAND闪存存储器可以包括例如四个存储面，并且每一存储面可以包括例如六个存储块。每一存储块可以包括多个存储单元，多个存储单元可以以垂直存储串(Memory String)的形式布置，其中，可以通过诸如位线和字线的互连对每一存储单元进行寻址。在另一实施例中，存储模块还可以为存储管芯。
图4示出了根据本发明一实施例的用于存储器的数据保护方法400的流程图，所述存储器包括多个存储模块，每个存储模块包括第一存储块和第二存储块。如图4中所示，方法400包括：在所述存储器的编程过程中，基于所述多个存储模块中的每个存储模块的相应第一存储块的存储数据来生成第一校验码，并且基于所述多个存储模块中的每个存储模块的相应第二存储块的存储数据来生成第二校验码(步骤S410)；以及在所述存储器的编程过程之后，基于所述第一校验码和所述第二校验码来生成附加校验码，其中，所述附加校验码用于恢复所述多个存储模块的第一存储块和第二存储块中的其中一个存储块的数据(步骤S420)。步骤410和420说明如下：
步骤S410：在所述存储器的编程过程中，基于所述多个存储模块中的 每个存储模块的相应第一存储块的存储数据来生成第一校验码，并且基于所述多个存储模块中的每个存储模块的相应第二存储块的存储数据来生成第二校验码。仍以图3所示的方法为例，在编程过程中，在存储模块0、存储模块1、存储模块2、……存储模块n中的每一个存储模块包括两个存储块(例如存储块0、存储块1)的情况下，基于存储模块0中的存储块0、存储模块1中的存储块0、存储模块2中的存储块0、……存储模块n中的存储块0中存储的数据进行“XOR”操作生成校验码P0；基于存储模块0中的存储块1、存储模块1中的存储块1、存储模块2中的存储块1、……存储模块n中的存储块1中存储的数据进行“XOR”操作生成校验码P1。应理解，在存储模块0、存储模块1、存储模块2、……存储模块n中的每一个存储模块包括n个存储块的情况下，基于类似的方法可以生成n个校验码P0、P1、P2、……Pn。
在一实施例中，每个存储模块的第一存储块和第二存储块(例如存储块0、存储块1)是物理相邻的存储块。
步骤S420：在所述存储器的编程过程之后，基于所述第一校验码和所述第二校验码来生成附加校验码，其中，所述附加校验码用于恢复所述多个存储模块的第一存储块和第二存储块中的其中一个存储块的数据。仍以图3所示的方法为例，在编程过程之后，例如对校验码P0和校验码P1执行“异或”操作来生成附加校验码P。应理解，在存储模块0、存储模块1、存储模块2、……存储模块n中的每一个存储模块包括n个存储块的情况下，可以在编程过程之后，例如对校验码P0、校验码P1、校验码P2、……校验码Pn执行“异或”操作来生成附加校验码P。
在一实施例中，还包括将附加校验码P存储至3D NAND闪存存储器中，例如，3D NAND闪存存储器的存储阵列的某部分区域可以预先地被确定为用来存储附加校验码的缓存区域。
在一个实施例中，可以基于生成的附加校验码P以及多个存储模块的第一存储块和第二存储块中存储的未丢失的数据来恢复在编程过程之后存储器的某一个存储块丢失的数据。例如，仍以图3所示的方法为例，假设在编程过程之后，存储模块1的存储块0中存储的数据丢失。为了恢复存储模块1的存储块0中丢失的数据，可以首先将生成的附加校验码P与存 储模块n的存储块1中存储的数据执行“异或”操作，然后将所得结果与存储模块n-1的存储块1中存储的数据再执行“异或”操作，直至将依次执行“异或”操作的结果与存储模块0的存储块1中存储的数据再执行“异或”操作，然后再将这n次“异或”操作的结果与存储模块n的存储块0中存储的数据执行“异或”操作，然后将所得结果与存储模块n-1的存储块0中存储的数据再执行“异或”操作，直至将依次执行“异或”操作的结果与存储模块2的存储块0中存储的数据再执行“异或”操作，从而获得上述一共2n-2次“异或”操作的最终结果，该最终结果也是存储模块0的存储块0中存储的数据与存储模块1的存储块0中存储的数据执行“异或”操作的结果。因此，利用基于第一校验码P0和第二校验码P1生成的附加校验码P，可以恢复在编程过程之后存储模块1的存储块0中丢失的数据。应理解，在存储模块0、存储模块1、存储模块2、……存储模块n中的每一个存储模块包括n个存储块的情况下，基于类似的方法可以恢复在编程过程之后存储器的某一个存储块中丢失的数据。
图5示出了根据本公开一实施例的具有存储器的系统500的示意图。系统500可以是移动电话、台式计算机、膝上型计算机、平板计算机、游戏控制台、打印机、定位设备、可穿戴电子设备、智能传感器、虚拟现实(VR)设备、增强现实(AR)设备或具有存储器的任何其他合适电子设备。如图5中所示，系统500可以包括主机510和具有一个或多个存储器501和存储器控制器502的存储器系统520。主机510可以被配置为将数据发送到存储器501或从存储器501接收数据。
存储器501可以是本文所公开的任何存储器，例如3D NAND闪存存储器，其包括多个存储模块(例如，存储管芯)，每个存储模块包括第一存储块和第二存储块，如上文详细所述。
如图5中所示，存储器控制器502包括前端接口5021和后端接口5022，前端接口5021通过通道Lane 0、Lane 1、Lane2、Lane3耦接到主机510，并且后端接口5022通过通道CH1、CH2、CH3、CH4耦接到存储器501，其中前端接口5021可以根据特定通信协议(例如，PCIe、NVMe)与主机510通信；后端接口5022包括RAID模块，RAID模块被配置为在存储器501的编程过程中，基于存储器501的多个存储模块中的每个存储模块的相应第一存储 块的存储数据来生成第一校验码，并且基于所述多个存储模块中的每个存储模块的相应第二存储块的存储数据来生成第二校验码；以及在存储器501的编程过程之后，基于所述第一校验码和所述第二校验码来生成附加校验码，以用于恢复存储器501的一个存储块丢失的数据。RAID模块具体可以通过例如后端接口5022的控制器中所写入的固件(Firmware)等实现。
存储器控制器502还包括具有处理单元1、处理单元2、……、处理单元n的处理模块5023，对应处理单元可以配置有相应的固件，例如，实现FTL(Flash to Logic，闪存到逻辑)功能的固件，处理单元上运行的相应固件可以基于接收的来自主机510的指令来控制存储器501的操作，例如，读取、擦除和编程操作。存储器控制器502还包括静态随机存取存储器(SRAM)5024、动态随机存取存储器(DRAM)控制器5025、动态随机存取存储器(DRAM)接口5026，其中动态随机存取存储器(DRAM)接口5026耦接至动态随机存取存储器(DRAM)503。如图5中所示，存储器控制器502的各部件可以连接至总线&电桥5027。
如上所述，根据本发明一实施例的存储器系统520能够恢复在对存储器501的编程过程中多个存储块的数据丢失，并且在编程过程之后针对基于多个存储模块上的第一存储块和对应该多个存储模块的第二存储块分别获得的校验码增加一次异或操作，从而能够恢复数据保持阶段存储器501中的某一个存储块丢失的数据，同时使得需要存储的校验码数据大大减小，减少内存的用量。在需要将校验码数据存储至存储器缓存中时，将大大减少存储器缓存的读写次数，提高系统性能，减少设备损耗。
多个存储模块上的第一存储块和对应该多个存储模块的第二存储块分别获得的校验码
根据一个实施例，提供了一种计算机可读存储介质，在其上存储有程序代码，当所述程序代码由处理器执行时，使得所述处理器能够执行本说明书结合图2-3描述的各个实施例中的各种操作和功能。具体地，可以提供配有可读存储介质的系统或者装置，在该可读存储介质上存储着实现上述实施例中任一实施例的功能的软件程序代码，且使该系统或者装置的计算机或处理器读出并执行存储在该可读存储介质中的指令。
可读存储介质的实施例包括非易失性存储卡和ROM等。可选择地， 可以由通信网络从服务器计算机上或云上下载程序代码。
需要说明的是，上述各流程和各系统结构图中不是所有的步骤和单元都是必须的，可以根据实际的需要忽略某些步骤或单元。各步骤的执行顺序不是固定的，可以根据需要进行确定。上述各实施例中描述的装置结构可以是物理结构，也可以是逻辑结构，即，有些单元可能由同一物理实体实现，或者，有些单元可能分由多个物理实体实现，或者，可以由多个独立设备中的某些部件共同实现。
已经结合各种装置和方法描述了控制器。所述控制器可以使用电子硬件、计算机软件或其任意组合来实施。所述控制器是实施为硬件还是软件将取决于具体的应用以及施加在系统上的总体设计约束。作为示例，本公开中给出的控制器、控制器的任意部分、或者控制器的任意组合可以实施为微处理器、微控制器、数字信号处理器(DSP)、现场可编程门阵列(FPGA)、可编程逻辑器件(PLD)、状态机、门逻辑、分立硬件电路、以及配置用于执行在本公开中描述的各种功能的其它适合的处理部件。本公开给出的控制器、控制器的任意部分、或者控制器的任意组合的功能可以实施为由微处理器、微控制器、DSP或其它适合的平台所执行的软件。
本公开内容的上述描述被提供来使得本领域任何普通技术人员能够实现或者使用本公开内容。对于本领域普通技术人员来说，对本公开内容进行的各种修改是显而易见的，并且，也可以在不脱离本公开内容的保护范围的情况下，将本文所定义的一般性原理应用于其它变型。因此，本公开内容并不限于本文所描述的示例和设计，而是与符合本文公开的原理和新颖性特征的最广范围相一致。

Claims (21)

  1. 一种用于存储器的数据保护方法，所述存储器包括多个存储模块，每个存储模块包括第一存储块和第二存储块，所述方法包括：
    在所述存储器的编程过程中，基于所述多个存储模块中的每个存储模块的相应第一存储块的存储数据来生成第一校验码，并且基于所述多个存储模块中的每个存储模块的相应第二存储块的存储数据来生成第二校验码；以及
    在所述存储器的编程过程之后，基于所述第一校验码和所述第二校验码来生成附加校验码，其中，所述附加校验码用于恢复所述多个存储模块的第一存储块和第二存储块中的其中一个存储块的数据。
  2. 根据权利要求1所述的方法，其中，所述存储模块为存储管芯或存储面。
  3. 根据权利要求1所述的方法，其中，每个存储模块的所述第一存储块和所述第二存储块为物理相邻的存储块。
  4. 根据权利要求1所述的方法，其中，对所述多个存储模块中的每个存储模块的相应第一存储块的存储数据执行异或操作来生成所述第一校验码，对所述多个存储模块中的每个存储模块的相应第二存储块的存储数据执行异或操作来生成所述第二校验码，并且对所述第一校验码和所述第二校验码执行异或操作来生成所述附加校验码。
  5. 根据权利要求1所述的方法，还包括将所述附加校验码存储至所述存储器。
  6. 根据权利要求1所述的方法，其中，所述存储器为3D NAND闪存存储器。
  7. 根据权利要求1所述的方法，还包括步骤：在所述多个存储模块的第一存储块和第二存储块中的其中一个存储块发生数据丢失的情况下，使用所述附加校验码以及所述多个存储模块的第一存储块和第二存储块中存储的未丢失的数据来恢复所述一个存储块的数据。
  8. 根据权利要求5所述的方法，其中，在将所述附加校验码存储至所述存储器之前，所述第一校验码和所述第二校验码被存储在相应的缓存中。
  9. 根据权利要求8所述的方法，还包括步骤：
    在将所述附加校验码存储至所述存储器之后，从所述缓存中删除所述第一校验码和所述第二校验码。
  10. 根据权利要求9所述的方法，还包括步骤：
    在从所述缓存中删除所述第一校验码和所述第二校验码之前，基于RAID技术并且使用所述第一校验码和所述第二校验码对所述多个存储模块的第一存储块和第二存储块中的一个或多个存储块的数据进行恢复操作。
  11. 一种存储器系统，包括：
    存储器，所述存储器包括多个存储模块，并且每个所述存储模块包括第一存储块和第二存储块；以及
    控制器，所述控制器连接至所述存储器并且被配置为：在所述存储器的编程过程中，基于所述多个存储模块中的每个存储模块的相应第一存储块的存储数据来生成第一校验码，并且基于所述多个存储模块中的每个存储模块的相应第二存储块的存储数据来生成第二校验码；以及在所述存储器的编程过程之后，基于所述第一校验码和所述第二校验码来生成附加校验码，其中，所述附加校验码用于恢复所述多个存储模块的第一存储块和第二存储块中的其中一个存储块的数据。
  12. 根据权利要求11所述的存储器系统，其中，所述存储模块为存储 管芯或存储面。
  13. 根据权利要求11所述的存储器系统，其中，每个存储模块的所述第一存储块和所述第二存储块为物理相邻的存储块。
  14. 根据权利要求11所述的存储器系统，其中，所述控制器被配置为对所述多个存储模块中的每个存储模块的相应第一存储块的存储数据执行异或操作来生成所述第一校验码，对所述多个存储模块中的每个存储模块的相应第二存储块的存储数据执行异或操作来生成所述第二校验码，并且对所述第一校验码和所述第二校验码执行异或操作来生成所述附加校验码。
  15. 根据权利要求11所述的存储器系统，所述控制器还被配置为将所述附加校验码存储至所述存储器。
  16. 根据权利要求11所述的存储器系统，其中，所述存储器为3D NAND闪存存储器。
  17. 根据权利要求11所述的存储器系统，其中，所述控制器被配置为在所述多个存储模块的第一存储块和第二存储块中的其中一个存储块发生数据丢失的情况下，使用所述附加校验码以及所述多个存储模块的第一存储块和第二存储块中存储的未丢失的数据来恢复所述一个存储块的数据。
  18. 根据权利要求15所述的存储器系统，其中，所述控制器还被配置为在将所述附加校验码存储至所述存储器之前，将所述第一校验码和所述第二校验码存储在相应的缓存中。
  19. 根据权利要求18所述的存储器系统，其中，所述控制器还被配置为在将所述附加校验码存储至所述存储器之后，从所述缓存中删除所述第一校验码和所述第二校验码。
  20. 根据权利要求19所述的存储器系统，其中，所述控制器还被配置为在从所述缓存中删除所述第一校验码和所述第二校验码之前，基于RAID技术并且使用所述第一校验码和所述第二校验码对所述多个存储模块的第一存储块和第二存储块中的一个或多个存储块的数据进行恢复操作。
  21. 一种计算机可读存储介质，在其上存储有程序代码，当所述程序代码由处理器执行时，使得所述处理器执行根据权利要求1至10中的任一项所述的方法。
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