WO2023050147A1 - 用于存储器的数据保护方法及其存储装置 - Google Patents
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
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Definitions
- the present disclosure generally relates to the field of data storage, and more specifically, relates to a RAID-based method capable of recovering lost data of a storage block in a memory and a storage device thereof.
- RAID Redundant Array of Independent Disks, Redundant Array of Independent Disks
- RAID is a disk array formed by combining multiple independent disks in different combinations. Since RAID can provide fault tolerance through data verification/mirroring functions, the security of data storage is enhanced. Therefore, RAID has been widely used in various fields of data storage and data protection.
- 3D NAND Flash Memory Device In recent years, in order to further increase the bit density and reduce the cost of flash memory devices, three-dimensional (3D) NAND flash memory (3D NAND Flash Memory Device) has been developed. However, in the process of writing to a storage block of 3D NAND flash memory, due to various reasons (such as power failure, writing failure, etc.), all the data to be written cannot be successfully written to this storage block. In the block, writing to this storage block has not been completed at this time, so a part of data written to this storage block will not be available. When restarting writing, this memory block will also be skipped and written from an adjacent memory block.
- a data protection method for a memory including a plurality of storage blocks, the method comprising: storing data based on a plurality of valid storage blocks in the plurality of storage blocks generating check code data of a check factor; configuring a first plurality of address pointers for the plurality of storage blocks in the check factor; and setting a second plurality of address pointers in each of the valid storage blocks, wherein, each of the second plurality of address pointers in each of the valid storage blocks respectively points to a corresponding other valid storage block, the first plurality of address pointers and the second plurality of address pointers of the plurality of valid storage blocks
- the address pointers can together form an address chain covering all valid storage blocks of the plurality of valid storage blocks.
- the first multiple address pointers are 2 address pointers
- the second multiple address pointers are 2 address pointers
- the data in a certain valid storage block of the multiple valid storage blocks In the case of loss and the loss of the second multiple address pointers corresponding to the setting, the first multiple address pointers and the second multiple address pointers of other valid storage blocks of the multiple valid storage blocks can together form a Address chains of all valid storage blocks of other valid storage blocks among the plurality of valid storage blocks.
- the method further includes the step of: when the data of a certain valid storage block among the plurality of valid storage blocks is lost, the check code data based on the check factor and through the The address chain formed by the first plurality of address pointers and the second plurality of address pointers of other valid storage blocks of the plurality of valid storage blocks reads the storage data of the corresponding valid storage blocks of the plurality of valid storage blocks to restore The lost data of the certain valid storage block.
- the first multiple address pointers are N address pointers
- the second multiple address pointers are N address pointers
- N is an integer greater than or equal to 2; set for a certain valid storage block
- the N address pointers of the valid storage block respectively point to one of the N valid storage blocks that have been successfully written recently before the effective storage block is successfully written; the N address pointers of the check factor point to the valid storage block respectively.
- the N address pointers of the first successfully written valid storage block of the plurality of valid storage blocks of the plurality of storage blocks point to empty, and the (N-M)th success of the plurality of storage blocks Among the N address pointers of the valid storage block to be written, (M+1) address pointers point to null, and M is an integer greater than or equal to 0 and less than N.
- the address chain automatically skips invalid memory blocks in the plurality of memory blocks.
- the check code data of the check factor is generated based on the storage data of all valid storage blocks in the plurality of storage blocks.
- an exclusive OR operation is performed on the storage data of the plurality of valid storage blocks among the plurality of storage blocks to generate the check code data of the check factor.
- an XOR operation is performed on the check code data and the storage data of the corresponding valid storage block read through the address chain to recover the lost data of the certain valid storage block.
- the memory is 3D NAND flash memory.
- a data recovery method for a memory includes a plurality of storage blocks, the method includes: determining the number of valid storage blocks in the plurality of storage blocks The data of a certain valid storage block is lost; and the check code data based on the check factor and the storage data of the corresponding valid storage block of the plurality of valid storage blocks are read through the address chain to restore the certain valid storage block The lost data; wherein, the check factor includes the check code data and a first plurality of address pointers configured for the plurality of storage blocks, and the address chain passes through the first plurality of address pointers and The second plurality of address pointers set in each of the valid storage blocks is formed, and each of the second plurality of address pointers in each of the valid storage blocks points to a corresponding one of the other valid storage blocks, so that the The address chain can cover all valid storage blocks of the plurality of valid storage blocks.
- the first multiple address pointers are 2 address pointers
- the second multiple address pointers are 2 address pointers
- the data in a certain valid storage block of the multiple valid storage blocks In the case of loss and the loss of the second multiple address pointers corresponding to the setting, the first multiple address pointers and the second multiple address pointers of other valid storage blocks of the multiple valid storage blocks can together form a Address chains of all valid storage blocks of other valid storage blocks among the plurality of valid storage blocks.
- the second multiple address pointers stored in the certain valid storage block are also read, and based on the second multiple address pointers Determine the corresponding valid memory block to read next.
- the first multiple address pointers are N address pointers
- the second multiple address pointers are N address pointers
- N is an integer greater than or equal to 2; set for a certain valid storage block
- the N address pointers of the valid storage block respectively point to one of the N valid storage blocks that have been successfully written recently before the effective storage block is successfully written; the N address pointers of the check factor point to the valid storage block respectively.
- an XOR operation is performed on the check code data and the storage data of the corresponding valid storage block read through the address chain to recover the lost data of the certain valid storage block.
- a memory system including: a memory including a plurality of memory blocks; and a memory controller coupled to the memory and configured to: Generate check code data of a check factor based on storage data of a plurality of valid storage blocks in the plurality of storage blocks; configure a first plurality of address pointers for the plurality of storage blocks in the check factor; and A second plurality of address pointers is set in each of the valid storage blocks, wherein each of the second plurality of address pointers in each of the valid storage blocks points to a corresponding one of the other valid storage blocks, and the first A plurality of address pointers and a second plurality of address pointers of the plurality of valid memory blocks can together form an address chain covering all valid memory blocks of the plurality of valid memory blocks.
- the first multiple address pointers are 2 address pointers
- the second multiple address pointers are 2 address pointers
- the data in a certain valid storage block of the multiple valid storage blocks In the case of loss and the loss of the second multiple address pointers corresponding to the setting, the first multiple address pointers and the second multiple address pointers of other valid storage blocks of the multiple valid storage blocks can together form a Address chains of all valid storage blocks of other valid storage blocks among the plurality of valid storage blocks.
- the controller is further configured to: when the data of a certain valid storage block among the plurality of valid storage blocks is lost, based on the check code data of the check factor and through the The address chain formed by the first plurality of address pointers and the second plurality of address pointers of the other valid storage blocks of the plurality of valid storage blocks reads the storage data of the corresponding valid storage block of the plurality of valid storage blocks, to The lost data of the certain valid storage block is recovered.
- the first multiple address pointers are N address pointers
- the second multiple address pointers are N address pointers
- N is an integer greater than or equal to 2; set for a certain valid storage block
- the N address pointers of the valid storage block respectively point to one of the N valid storage blocks that have been successfully written recently before the effective storage block is successfully written; the N address pointers of the check factor point to the valid storage block respectively.
- the N address pointers of the first successfully written valid storage block of the plurality of valid storage blocks of the plurality of storage blocks point to empty, and the (N-M)th success of the plurality of storage blocks Among the N address pointers of the valid storage block to be written, (M+1) address pointers point to null, and M is an integer greater than or equal to 0 and less than N.
- the address chain automatically skips invalid memory blocks in the plurality of memory blocks.
- the controller is configured to generate check code data of the check factor based on storage data of all valid storage blocks in the plurality of storage blocks.
- the controller is configured to perform an exclusive OR operation on the storage data of the plurality of valid storage blocks among the plurality of storage blocks to generate the check code data of the check factor.
- the controller is configured to perform an XOR operation on the check code data and the storage data of the corresponding valid storage block read through the address chain to restore the data stored in the certain valid storage block. missing data.
- the memory is 3D NAND flash memory.
- a memory system including: a memory including a plurality of memory blocks; and a memory controller coupled to the memory and configured to: Determining the data loss of one of the multiple valid storage blocks among the multiple valid storage blocks; and reading the corresponding valid data of the multiple valid storage blocks based on the check factor and the address chain storage data of the storage block to restore the lost data of the certain effective storage block; wherein the check factor includes check code data and the first plurality of address pointers configured for the plurality of storage blocks, so The address chain is formed by the first plurality of address pointers and the second plurality of address pointers set in each of the valid storage blocks, each of the second plurality of address pointers in each of the valid storage blocks One points to a corresponding one of the other valid storage blocks, so that the address chain can cover all valid storage blocks of the plurality of valid storage blocks.
- the first multiple address pointers are 2 address pointers
- the second multiple address pointers are 2 address pointers
- the data in a certain valid storage block of the multiple valid storage blocks In the case of loss and the loss of the second multiple address pointers corresponding to the setting, the first multiple address pointers and the second multiple address pointers of other valid storage blocks of the multiple valid storage blocks can together form a Address chains of all valid storage blocks of other valid storage blocks among the plurality of valid storage blocks.
- the memory controller is configured such that when reading the storage data of a certain valid storage block, the second plurality of address pointers stored in the certain valid storage block are also read, and based on The second plurality of address pointers determines corresponding valid memory blocks to be read next.
- the first multiple address pointers are N address pointers
- the second multiple address pointers are N address pointers
- N is an integer greater than or equal to 2; set for a certain valid storage block
- the N address pointers of the valid storage block respectively point to one of the N valid storage blocks that have been successfully written recently before the effective storage block is successfully written; the N address pointers of the check factor point to the valid storage block respectively.
- the memory controller is configured to perform an exclusive OR operation on the check code data and the storage data of the corresponding valid storage block read through the address chain to restore the certain valid storage block the lost data.
- a memory system including: a memory, the memory includes a storage area for verification and a plurality of memory blocks; and a memory controller, the memory controller is coupled to The memory; the verification storage area stores verification factors corresponding to a plurality of valid storage blocks of the plurality of storage blocks, and the verification factors include verification code data and are configured for the plurality of storage blocks
- the first plurality of address pointers each of the effective storage blocks is provided with a second plurality of address pointers, and each of the second plurality of address pointers in each of the effective storage blocks points to a corresponding one of the other valid storage blocks.
- a storage block; wherein, the first plurality of address pointers and the second plurality of address pointers of the plurality of valid storage blocks can together form an address chain covering all valid storage blocks of the plurality of valid storage blocks.
- Fig. 1 shows a schematic diagram of a data protection method for a memory according to an embodiment of the present disclosure.
- Fig. 2 shows a schematic diagram of a data protection method for a memory according to yet another embodiment of the present disclosure.
- FIG. 3 shows a flowchart of a data protection method for a memory according to an embodiment of the present disclosure
- FIG. 4 shows a flow chart of a data recovery method for a memory according to an embodiment of the present disclosure.
- FIG. 5 shows a schematic diagram of a memory system according to an embodiment of the disclosure.
- references in the specification to "one embodiment,” “an embodiment,” “some embodiments,” etc. mean that the described embodiments may include particular features, structures, or characteristics, but not necessarily that every embodiment including that particular feature, structure or characteristic. Furthermore, such terms are not necessarily referring to the same embodiment.
- references in the specification to "one embodiment,” “an embodiment,” “some embodiments,” etc. mean that the described embodiments may include particular features, structures, or characteristics, but not necessarily that every embodiment including that particular feature, structure or characteristic. Furthermore, such terms are not necessarily referring to the same embodiment.
- references in the specification to "one embodiment,” “an embodiment,” “some embodiments,” etc. mean that the described embodiments may include particular features, structures, or characteristics, but not necessarily that every embodiment including that particular feature, structure or characteristic. Furthermore, such terms are not necessarily referring to the same embodiment.
- when a particular feature, structure or characteristic is described in conjunction with an embodiment it should be within the knowledge of those skilled in the relevant art to implement such feature, structure or characteristic in combination with other embodiments that are explicitly or not explicitly described.
- EEPROM Electrically Erasable Programmable ROM
- NOR Flash Phase Change RAM
- MRAM Magnetic RAM
- RRAM resistive RAM
- FRAM ferroelectric RAM
- Fig. 1 shows a schematic diagram of a data protection method for a memory according to an embodiment of the present disclosure, wherein which data is skipped is recorded in the form of a bitmap. That is to say, the bitmap data is used as additional data of the check factor F.
- the 3D NAND flash memory 100 includes a storage block D0, a storage block D1, a storage block D2, ..., a storage block Dn.
- the storage block that has been written is marked as "valid" and represented by "0" in the bitmap, and the storage block that has not completed the writing and makes part of its written data unavailable is marked as "skipped". ” and represented by “1” in the bitmap.
- bitmap as additional data for the check factor F needs to occupy 16 bytes or 32 bytes, this will result in wasted space of 16 bytes or 32 bytes per valid storage block which cannot Used to store data, because even if data is written in these spaces of each valid storage block, it is impossible to use RAID technology to recover data that was successfully written in this space of a valid storage block and was later lost after the writing is completed. data. Therefore, in addition to the need to reserve a large space for additional data (for example, bitmap) in the check factor F, thereby greatly reducing the ECC error correction capability of the system, each effective storage block also wastes the additional data. same size space.
- Fig. 2 shows a schematic diagram of a data protection method for a memory according to yet another embodiment of the present disclosure.
- the 3D NAND flash memory 200 includes a storage block D0, a storage block D1, a storage block D2, ... a storage block D126.
- the storage block D of successful writing is marked as " valid ", for example storage block D0, storage block D2, ... storage block D123, storage block D125 , Storage block D126.
- the storage block D whose data has not been successfully written is marked as "skip", such as storage block D1, storage block D3, ... Memory block D124, the data in the memory block marked as "skipped" is not available.
- the check code data P can be generated by performing an "exclusive OR” (XOR) operation on data stored in a plurality of valid storage blocks D in all storage blocks of the 3D NAND flash memory 200.
- the check code data P can be generated by performing an exclusive OR (XOR) operation on the data stored in all valid storage blocks D of the 3D NAND flash memory 200.
- XOR is a logical operation on two operands that produces a logical value "1" if the two values that are “exclusively ORed” are different; if the two values that are “exclusively ORed” are the same, it produces a logical value" 0".
- the result after the "exclusive OR” is "01001001”.
- the check factor F used to recover the lost data of a certain valid storage block D after writing is completed includes additional data in addition to the check code data P.
- an address chain is used as the additional data of the check factor F.
- the check factor F includes two address pointers L1, L2, these two address pointers L1, L2 respectively point to a corresponding effective storage block D of the 3D NAND flash memory 200.
- the two address pointers L1 and L2 respectively record the number of the corresponding valid storage block D.
- the two address pointers L1 and L2 can only occupy two bytes of space; if the RAID ratio is 255:1, the two address pointers L1 and L2 may only occupy four bytes of space.
- the two address pointers L1 and L2 as additional data of the check factor F can respectively point to one of the two valid memory blocks that are last successfully written in the 3D NAND flash memory 200 in terms of time.
- the address pointer L2 points to the last valid storage block D126 successfully written into
- the address pointer L1 points to the penultimate valid storage block D125 successfully written into. It should be understood that the situation shown in Fig.
- each effective storage block In addition to the stored data written in D, it also occupies two bytes of space to store two address pointers D L1 and D L2 respectively.
- These two address pointers D L1 and D L2 respectively point to One of the two most recent valid memory blocks D that were successfully written prior to the block D's write.
- address pointers D126 L1 and D126 L2 are also stored in the valid storage block D126, wherein the address pointer D126 L2 points to the effective storage block D126 before successfully writing the Let’s talk about the most recently successfully written valid storage block, such as D125, and the address pointer D126 L1 points to the penultimate valid storage block successfully written before the valid storage block D126 is successfully written, such as D123. Because memory block D124 is marked as "skipped", address pointer D126 L1 will not point to memory block D124 even though memory block D124 is closer to valid memory block D126 than memory block D123.
- two address pointers D125 L1 and D125 L2 are also stored, wherein the address pointer D125 L2 points to the valid memory block that was successfully written recently before the effective memory block D125 was successfully written.
- storage block such as D123
- the address pointer D125 L1 points to the penultimate valid storage block that is successfully written before the effective storage block D125, such as D122 (not shown in FIG. 2 ).
- storage block D124 is marked as "skip" although storage block D124 is closer to valid storage block D125 than storage block D123, the two address pointers D125 L1 and D125 L2 in valid storage block D125 will not point to storage block D124 .
- the storage blocks pointed to by the two address pointers D L1 and D L2 stored in each valid storage block D can be determined.
- the writing process to 3D NAND flash memory 200 is as follows: first, storage block D0 is written, if storage block D0 is successfully written (marked as "valid"), because the storage block D0 is written into Before D0 is successfully written, no storage block D is successfully written, so the two address pointers D0 L1 and D0 L2 in the effective storage block D0 point to empty; Next, write to the storage block D1, during the writing process, Due to a certain reason (for example, power failure), memory block D1 was not successfully written (marked as "skipped”); next, after resuming the writing process, write to memory block D2, if the memory Block D2 is successfully written (marked as "valid"), because only storage block D0 is successfully written before storage block D2 is successfully written, then address pointer D2 L2 in valid storage block D2 points to valid storage block D0, and The address pointer D2 L1 of effective storage block D2 points to empty; Next, write to storage block D3, write process, cause storage block D3 to fail to write
- the lost data in the valid storage block D can be recovered by using the RAID technology.
- the lost data of a valid storage block D in addition to the storage data in the valid storage block D that needs to be successfully written in all the multiple storage blocks of the 3D NAND flash memory 200 in the writing process
- the address pointer in the check factor F and the other valid storage blocks except the valid storage block D with lost data can be passed
- the address chain formed by the address pointers in D is used to read the data stored in the corresponding valid storage block D.
- the check code data P obtained based on the storage data in all valid storage blocks D of the 3D NAND flash memory 200 and other valid storage blocks D read except for the valid storage block D123 with missing data
- Exclusive OR operation is performed on the stored data in the corresponding valid storage block D to restore the lost data in the storage block D123.
- the address pointer L2 of the verification factor F points to the storage block D126, because the data stored in the storage block D126 cannot be read at this time, so the address pointer L1 of the verification factor F can be used to point to the effective storage block D125 at this time, and the first read Get the data stored in the valid storage block D125.
- the check code data P obtained based on the storage data in all valid storage blocks D of the 3D NAND flash memory 200 in the writing process and the valid storage blocks except the lost data through the address pointer in the check factor F
- the check code data P After the address chain formed by the address pointers in other valid storage blocks D other than D126 reads the stored data in other valid storage blocks D except the valid storage block D126 that lost data, the check code data P And the read stored data in the corresponding valid storage block D performs an "exclusive OR" operation to restore the lost data in the storage block D126.
- an "exclusive OR" operation can be performed on the generated check code data P and the storage data of the corresponding valid storage block read through the address chain to restore the data lost in a certain valid storage block D after the writing process.
- the data For example, still taking the method shown in FIG. 2 as an example, assume that after the writing process, the data stored in the valid storage block D123 is lost.
- the generated additional check code P and the stored data in the valid storage block D126 read through the address pointer L2 in the check factor F can be performed "exclusive OR” operation , and then carry out the "exclusive OR” operation with the obtained result and the storage data in the effective storage block D125 read by the address pointer L2 in the effective storage block D126, and then combine the obtained result with the address pointer in the effective storage block D125
- the stored data in the valid storage block D122 (not shown in Fig. 2) read by L1 performs an "exclusive OR" operation, ...
- the two address pointers L1, L2 of the verification factor F point to one of two valid storage blocks that are successfully written at last in the valid storage block D of the 3D NAND flash memory 200 respectively, in When the data stored in the valid storage block D that was not successfully written last is lost later, the address pointer L2 of the verification factor F and the address pointers in other valid storage blocks D other than the valid storage block D that lost the data are used to form The address chain is used to read the data stored in other valid storage blocks D except the valid storage block D where the data is lost.
- the address pointer L1 of the check factor F and the data stored in the last successfully written valid storage block D can be utilized.
- the address chains formed by the address pointers in other valid storage blocks D are used to read the data stored in other valid storage blocks D except the last successfully written valid storage block D. Since one of the two address pointers L1 and L2 of the check factor F can be selectively used as the address chain at the head of the chain to read the data stored in the corresponding valid storage block D according to the position of the valid storage block D where data loss occurs, So no broken chain will happen.
- the verification factor F has only one address pointer L and the address pointer L points to the valid storage block D successfully written in the valid storage block at last, such as the valid storage block D126
- the data stored in the valid storage block D126 is lost , the data stored in other valid storage blocks D except the valid storage block D126 cannot be read. That is to say, at this moment, a broken link will occur, so that the RAID technology cannot be utilized to recover the lost data in the storage block D126.
- the parity factor F shown in FIG. 2 including two address pointers L1, L2 and each valid memory block D including two address pointers are merely exemplary.
- the check factor F may include N address pointers (N is an integer greater than or equal to 2), which respectively point to the last successfully written N valid addresses in the valid storage block D of the 3D NAND flash memory 200.
- N is an integer greater than or equal to 2
- each valid storage block D also includes N address pointers (N is an integer greater than or equal to 2), which respectively point to the corresponding valid storage block D successfully written One of the N valid storage blocks D that were successfully written last before entering.
- the check factor F can include three address pointers L1, L2, L3 and each valid memory block D can include three address pointers, the address pointer L3 of the check factor F points to the last successful write in the valid memory block D
- the address pointer L2 points to the penultimate valid storage block in the valid storage block D that is successfully written
- the address pointer L1 points to the penultimate valid storage block in the valid storage block D that is successfully written.
- the three address pointers of each valid storage block D respectively point to one of the three valid storage blocks that were successfully written last before the valid storage block D was successfully written.
- Fig. 3 shows a flowchart of a data protection method for a memory according to an embodiment of the present disclosure, and the memory includes a plurality of storage blocks.
- the method 300 includes: generating check code data of a check factor based on storage data of a plurality of valid storage blocks in the plurality of storage blocks (step S310); in the check factor is The plurality of storage blocks are configured with a first plurality of address pointers (step S320); and a second plurality of address pointers are set in each of the effective storage blocks, wherein the second plurality of address pointers in each of the effective storage blocks Each of the address pointers respectively points to a corresponding one of the other valid storage blocks, and the first plurality of address pointers and the second plurality of address pointers of the plurality of valid storage blocks can form together to cover the plurality of valid storage blocks Address chains of all valid storage blocks (step S330). Steps S310-S330 are described as follows:
- Step S310 Generate check code data of a check factor based on storage data of a plurality of valid storage blocks in the plurality of storage blocks. Still taking the method shown in Figure 2 as an example, during the writing process of the 3D NAND flash memory, an "exclusive OR" operation can be performed on the data stored in all valid storage blocks D to generate the check code data P of the check factor F .
- Step S320 Configure the first plurality of address pointers for the plurality of storage blocks in the check factor.
- the check factor F in addition to the check code data P obtained in step S310, also includes two address pointers L1, L2 configured as additional data for the plurality of storage blocks, so The two address pointers L1 and L2 respectively point to one of the last two valid storage blocks that are successfully written in among the plurality of valid storage blocks.
- Step S330 setting a second plurality of address pointers in each of the valid storage blocks, wherein each of the second plurality of address pointers in each of the valid storage blocks respectively points to a corresponding other valid storage block,
- the first plurality of address pointers and the second plurality of address pointers of the plurality of valid storage blocks can together form an address chain covering all valid storage blocks of the plurality of valid storage blocks.
- two address pointers are also provided, and the two address pointers point to the successful storage data in the valid storage block D respectively.
- the two address pointers L1 and L2 of the check factor F and the two address pointers of each valid storage block D can form an address chain covering all valid storage blocks D together.
- Fig. 4 shows a flow chart of a data recovery method for a memory according to an embodiment of the present disclosure, and the memory includes a plurality of storage blocks.
- the method 400 includes: determining the data loss of a certain valid storage block of the plurality of valid storage blocks in the plurality of storage blocks (step S410); and the check code data based on the check factor and Read the storage data of the corresponding valid storage block of the plurality of valid storage blocks through the address chain to restore the lost data of the certain valid storage block, wherein the check factor includes the check code data and A first plurality of address pointers configured for the plurality of storage blocks, the address chain is formed by the first plurality of address pointers and the second plurality of address pointers set in each of the effective storage blocks, each Each of the second plurality of address pointers in one of the valid storage blocks respectively points to a corresponding other valid storage block, so that the address chain can cover all valid storage blocks of the plurality of valid storage blocks (step S420) .
- FIG. 5 shows a schematic diagram of a system 500 with memory according to an embodiment of the disclosure.
- System 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, game console, printer, pointing device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or Any other suitable electronic device for memory.
- system 500 may include a host 510 and a memory system 520 having one or more memories 501 and a memory controller 502 .
- Host 510 may be configured to send data to or receive data from memory 501 .
- the memory 501 can be any memory disclosed herein, such as 3D NAND flash memory, which includes a storage area 5011 for inspection and a plurality of storage blocks, such as storage block 0, storage block 1, storage block 2, ..., storage block n.
- the verification storage area 5011 stores verification factors of a plurality of valid storage blocks corresponding to the plurality of storage blocks, and the verification factors include verification code data and a plurality of first address pointers configured for the plurality of storage blocks.
- each valid storage block of the multiple storage blocks of the memory 501 is provided with a second plurality of address pointers, and each of the second plurality of address pointers of each valid storage block respectively points to a corresponding other valid storage block.
- the first plurality of address pointers and the second plurality of address pointers of the plurality of valid storage blocks can together form an address chain covering all valid storage blocks of the plurality of valid storage blocks.
- the memory controller 502 includes a front-end interface 5021 and a back-end interface 5022, the front-end interface 5021 is coupled to the host 510 through channels Lane 0, Lane 1, Lane2, Lane3, and the back-end interface 5022 is coupled to the host 510 through channels CH0, CH1, ..., CHn are coupled to the storage area 5011 for inspection of the memory 501 and corresponding storage blocks, wherein the front-end interface 5021 can communicate with the host 510 according to a specific communication protocol (for example, PCIe, NVMe); the back-end interface 5022 includes a RAID module .
- the RAID module can be realized by, for example, firmware (Firmware) written in the controller of the back-end interface 5022, or can be realized by a dedicated hardware engine circuit.
- the RAID module can be configured to generate the check code data of the check factor based on the storage data of multiple valid storage blocks in the multiple storage blocks of the memory 501;
- a plurality of storage blocks are configured with a first plurality of address pointers; and a second plurality of address pointers are set in each of the effective storage blocks for storage data stored therein, wherein the second plurality of address pointers in each of the effective storage blocks
- Each of the address pointers respectively points to a corresponding one of the other valid storage blocks, and the first plurality of address pointers and the second plurality of address pointers of the plurality of valid storage blocks can form together to cover the plurality of valid storage blocks
- the RAID module can be configured to determine the data loss of a certain valid storage block of the multiple valid storage blocks in the multiple storage blocks of the memory 501;
- the address chain reads the storage data of the corresponding valid storage blocks of the plurality of valid storage blocks to recover the lost data of the certain valid storage block;
- the check factor includes check code data and is the A first plurality of address pointers configured by a plurality of storage blocks, the address chain passing through the first plurality of address pointers and a second plurality of address pointers set in each of the valid storage blocks for the storage data stored therein Address pointers are formed, and each of the second plurality of address pointers in each of the valid storage blocks points to a corresponding one of the other valid storage blocks, so that the address chain can cover all valid storage blocks of the plurality of valid storage blocks. storage block.
- the memory controller 502 also includes a processing module 5023 having a processing unit 1, a processing unit 2, ..., a processing unit n, and the corresponding processing unit can be configured with corresponding firmware, for example, to realize FTL (Flash to Logic, flash memory to logic) function
- the corresponding firmware running on the processing unit can control the operations of the memory 501 based on instructions received from the host 510, such as read, erase and program operations.
- Memory controller 502 also includes static random access memory (SRAM) 5024, dynamic random access memory (DRAM) controller 5025, dynamic random access memory (DRAM) interface 5026, wherein dynamic random access memory (DRAM) interface 5026 Coupled to dynamic random access memory (DRAM) 503 .
- SRAM static random access memory
- DRAM dynamic random access memory
- DRAM dynamic random access memory
- DRAM dynamic random access memory
- DRAM dynamic random access memory
- DRAM dynamic random access memory
- DRAM dynamic random access memory
- DRAM dynamic random access memory
- DRAM dynamic random access memory
- the memory system 520 can use the address chain as the additional data of the check factor, thereby greatly reducing the space requirement for the additional data of the check factor, maintaining the ECC error correction capability of the system, and Greatly reduce the waste of memory space.
- a computer-readable storage medium on which program codes are stored, and when the program codes are executed by a processor, the processors can perform the operations described in this specification in conjunction with FIGS. 1-4 .
- Various operations and functions in various embodiments Specifically, a system or device equipped with a readable storage medium can be provided, on which a software program code for realizing the functions of any one of the above embodiments is stored, and the computer or device of the system or device can The processor reads and executes the instructions stored in the readable storage medium.
- Examples of the readable storage medium include nonvolatile memory cards, ROMs, and the like.
- the program code can be downloaded from a server computer or cloud via a communication network.
- the execution order of each step is not fixed, and can be determined as required.
- the device structures described in the above embodiments may be physical structures or logical structures, that is, some units may be realized by the same physical entity, or some units may be realized by multiple physical entities, or may be realized by multiple physical entities. Certain components in individual devices are implemented together.
- Controllers have been described in connection with various apparatus and methods.
- the controller may be implemented using electronic hardware, computer software, or any combination thereof. Whether the controller is implemented as hardware or software will depend upon the particular application and overall design constraints imposed on the system.
- a controller, any portion of a controller, or any combination of controllers presented in this disclosure may be implemented as a microprocessor, microcontroller, digital signal processor (DSP), field programmable gate array (FPGA) ), programmable logic devices (PLDs), state machines, gate logic, discrete hardware circuits, and other suitable processing components configured to perform the various functions described in this disclosure.
- DSP digital signal processor
- FPGA field programmable gate array
- PLDs programmable logic devices
- state machines gate logic, discrete hardware circuits, and other suitable processing components configured to perform the various functions described in this disclosure.
- the functionality of the controller, any portion of the controller, or any combination of controllers presented in this disclosure may be implemented as software executed by a microprocessor, microcontroller, DSP, or other
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Abstract
一种能够基于RAID来恢复存储器中的一个存储块丢失的数据的方法及其存储装置,所述存储器包括多个存储块,所述方法包括:基于所述多个存储块中的多个有效存储块的存储数据生成校验因子的校验码数据;在所述校验因子中为所述多个存储块配置第一多个地址指针;以及在每一个所述有效存储块中设置第二多个地址指针,其中,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,所述第一多个地址指针以及所述多个有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的全部有效存储块的地址链。
Description
本公开总体上涉及数据存储领域,以及更具体地,涉及一种能够基于RAID来恢复存储器中的一个存储块丢失的数据的方法及其存储装置。
RAID(Redundant Array of Independent Disks,独立磁盘冗余阵列)是将多个独立磁盘通过不同的组合方式组合在一起形成的磁盘阵列。由于RAID可以通过数据校验/镜像功能提供容错,从而增强了数据存储的安全性。因此,RAID已经广泛应用于数据存储和数据保护的各个领域中。
近年来,为了进一步提高闪速存储器件的位密度以及降低其成本,开发出了三维(3D)NAND闪存存储器(3D NAND Flash Memory Device)。但是,在对3D NAND闪存存储器的某一存储块进行写入的过程中,由于各种原因(例如掉电、写入失败等),导致要写入的数据不能全部成功写入到这一存储块中,此时对这一存储块的写入并未完成,从而写入到这一存储块的一部分数据将不可用。在重新开始写入时,也将跳过这一存储块从相邻的存储块开始写入。为了能够在写入完成后利用RAID技术来恢复一个“成功写入”的存储块中丢失的数据,在基于多个“成功写入”的存储块中的存储数据计算校验码数据时将跳过那些“未成功写入”的存储块中的不可用数据,并且在利用校验码数据恢复所述一个“成功写入”的存储块中后来丢失的数据时也同样需要跳过那些“未成功写入”的存储块中的不可用数据,所以在计算校验码数据时还需要生成用于记录跳过了哪些数据的附加数据,其中,校验码数据和附加数据一起形成用于恢复某一个“成功写入”的存储块中后来丢失的数据的校验因子。
因此,需要一种用于存储器的数据保护方法及其存储装置,其能够大大降低对校验因子的附加数据的空间要求,维持系统的ECC纠错能力,并且大大降低存储器的空间浪费。
发明内容
根据本公开的实施例,提供了一种用于存储器的数据保护方法,所述存储器包括多个存储块,所述方法包括:基于所述多个存储块中的多个有效存储块的存储数据生成校验因子的校验码数据;在所述校验因子中为所述多个存储块配置第一多个地址指针;以及在每一个所述有效存储块中设置第二多个地址指针,其中,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,所述第一多个地址指针以及所述多个有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的全部有效存储块的地址链。
在一些实施例中,所述第一多个地址指针为2个地址指针,所述第二多个地址指针为2个地址指针,在所述多个有效存储块的某一个有效存储块的数据丢失及其对应设置的第二多个地址指针丢失的情况下,所述第一多个地址指针以及所述多个有效存储块的其他有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的其他有效存储块的全部有效存储块的地址链。
在一些实施例中,所述方法还包括步骤:当所述多个有效存储块中的某一个有效存储块的数据丢失时,基于所述校验因子的所述校验码数据以及通过所述第一多个地址指针和所述多个有效存储块的其他有效存储块的第二多个地址指针形成的地址链读取所述多个有效存储块的相应有效存储块的存储数据,来恢复所述某一个有效存储块所丢失的数据。
在一些实施例中,所述第一多个地址指针为N个地址指针,所述第二多个地址指针为N个地址指针,N为大于或等于2的整数;针对某一个有效存储块设置的N个地址指针分别指向在所述某一个有效存储块成功写入之前最近成功写入的N个有效存储块之一;所述校验因子的N个地址指针分别指向所述有效存储块中的最后成功写入的N个有效存储块之一。
在一些实施例中,所述多个存储块的多个有效存储块的最先成功写入的有效存储块的N个地址指针指向为空,所述多个存储块的第(N-M)个成功写入的有效存储块的N个地址指针中,(M+1)个地址指针指向为空,M为大于或等于0且小于N的整数。
在一些实施例中,所述地址链自动跳过所述多个存储块中的无效存储块。
在一些实施例中,基于所述多个存储块中的全部有效存储块的存储数据生成所述校验因子的校验码数据。
在一些实施例中,对所述多个存储块中的所述多个有效存储块的存储数据执行异或操作来生成所述校验因子的校验码数据。
在一些实施例中,对所述校验码数据以及通过所述地址链读取的相应有效存储块的存储数据执行异或操作来恢复所述某一个有效存储块所丢失的数据。
在一些实施例中,所述存储器为3D NAND闪存存储器。
根据本公开的另一实施例,提供了一种用于存储器的数据恢复方法,所述存储器包括多个存储块,所述方法包括:确定所述多个存储块中的多个有效存储块的某一个有效存储块的数据丢失;以及基于校验因子的校验码数据以及通过地址链读取所述多个有效存储块的相应有效存储块的存储数据,来恢复所述某一个有效存储块所丢失的数据;其中,所述校验因子包括所述校验码数据和为所述多个存储块配置的第一多个地址指针,所述地址链通过所述第一多个地址指针以及在每一个所述有效存储块中设置的第二多个地址指针形成,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,从而所述地址链能够覆盖所述多个有效存储块的全部有效存储块。
在一些实施例中,所述第一多个地址指针为2个地址指针,所述第二多个地址指针为2个地址指针,在所述多个有效存储块的某一个有效存储块的数据丢失及其对应设置的第二多个地址指针丢失的情况下,所述第一多个地址指针以及所述多个有效存储块的其他有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的其他有效存储块的全部有效存储块的地址链。
在一些实施例中,在读取某一个有效存储块的存储数据时,存储在所述某一个有效存储块的第二多个地址指针也被读取,并且基于所述第二多个地址指针确定接下来读取的相应有效存储块。
在一些实施例中,所述第一多个地址指针为N个地址指针,所述第二多 个地址指针为N个地址指针,N为大于或等于2的整数;针对某一个有效存储块设置的N个地址指针分别指向在所述某一个有效存储块成功写入之前最近成功写入的N个有效存储块之一;所述校验因子的N个地址指针分别指向所述有效存储块中的最后成功写入的N个有效存储块之一。
在一些实施例中,对所述校验码数据以及通过所述地址链读取的相应有效存储块的存储数据执行异或操作来恢复所述某一个有效存储块所丢失的数据。
根据本公开的再一实施例,提供了一种存储器系统,包括:存储器,所述存储器包括多个存储块;以及存储器控制器,所述存储器控制器耦接至所述存储器并且被配置为:基于所述多个存储块中的多个有效存储块的存储数据生成校验因子的校验码数据;在所述校验因子中为所述多个存储块配置第一多个地址指针;以及在每一个所述有效存储块中设置第二多个地址指针,其中,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,所述第一多个地址指针以及所述多个有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的全部有效存储块的地址链。
在一些实施例中,所述第一多个地址指针为2个地址指针,所述第二多个地址指针为2个地址指针,在所述多个有效存储块的某一个有效存储块的数据丢失及其对应设置的第二多个地址指针丢失的情况下,所述第一多个地址指针以及所述多个有效存储块的其他有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的其他有效存储块的全部有效存储块的地址链。
在一些实施例中,所述控制器还被配置为当所述多个有效存储块中的某一个有效存储块的数据丢失时,基于所述校验因子的所述校验码数据以及通过所述第一多个地址指针和所述多个有效存储块的其他有效存储块的第二多个地址指针形成的地址链读取所述多个有效存储块的相应有效存储块的存储数据,来恢复所述某一个有效存储块所丢失的数据。
在一些实施例中,所述第一多个地址指针为N个地址指针,所述第二多个地址指针为N个地址指针,N为大于或等于2的整数;针对某一个有效存储块设置的N个地址指针分别指向在所述某一个有效存储块成功写入 之前最近成功写入的N个有效存储块之一;所述校验因子的N个地址指针分别指向所述有效存储块中的最后成功写入的N个有效存储块之一。
在一些实施例中,所述多个存储块的多个有效存储块的最先成功写入的有效存储块的N个地址指针指向为空,所述多个存储块的第(N-M)个成功写入的有效存储块的N个地址指针中,(M+1)个地址指针指向为空,M为大于或等于0且小于N的整数。
在一些实施例中,所述地址链自动跳过所述多个存储块中的无效存储块。
在一些实施例中,所述控制器被配置为基于所述多个存储块中的全部有效存储块的存储数据生成所述校验因子的校验码数据。
在一些实施例中,所述控制器被配置为对所述多个存储块中的所述多个有效存储块的存储数据执行异或操作来生成所述校验因子的校验码数据。
在一些实施例中,所述控制器被配置为对所述校验码数据以及通过所述地址链读取的相应有效存储块的存储数据执行异或操作来恢复所述某一个有效存储块所丢失的数据。
在一些实施例中,所述存储器为3D NAND闪存存储器。
根据本公开的再一实施例,提供了一种存储器系统,包括:存储器,所述存储器包括多个存储块;以及存储器控制器,所述存储器控制器耦接至所述存储器并且被配置为:确定所述多个存储块中的多个有效存储块的某一个有效存储块的数据丢失;以及基于校验因子的校验码数据以及通过地址链读取所述多个有效存储块的相应有效存储块的存储数据,来恢复所述某一个有效存储块所丢失的数据;其中,所述校验因子包括校验码数据和为所述多个存储块配置的第一多个地址指针,所述地址链通过所述第一多个地址指针以及在每一个所述有效存储块中设置的第二多个地址指针形成,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,从而所述地址链能够覆盖所述多个有效存储块的全部有效存储块。
在一些实施例中,所述第一多个地址指针为2个地址指针,所述第二多个地址指针为2个地址指针,在所述多个有效存储块的某一个有效存储块的 数据丢失及其对应设置的第二多个地址指针丢失的情况下,所述第一多个地址指针以及所述多个有效存储块的其他有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的其他有效存储块的全部有效存储块的地址链。
在一些实施例中,所述存储器控制器被配置为在读取某一个有效存储块的存储数据时,存储在所述某一个有效存储块的第二多个地址指针也被读取,并且基于所述第二多个地址指针确定接下来读取的相应有效存储块。
在一些实施例中,所述第一多个地址指针为N个地址指针,所述第二多个地址指针为N个地址指针,N为大于或等于2的整数;针对某一个有效存储块设置的N个地址指针分别指向在所述某一个有效存储块成功写入之前最近成功写入的N个有效存储块之一;所述校验因子的N个地址指针分别指向所述有效存储块中的最后成功写入的N个有效存储块之一。
在一些实施例中,所述存储器控制器被配置为对所述校验码数据以及通过所述地址链读取的相应有效存储块的存储数据执行异或操作来恢复所述某一个有效存储块所丢失的数据。
根据本公开的再一实施例,提供了一种一种存储器系统,包括:存储器,所述存储器包括校验用存储区域和多个存储块;以及存储器控制器,所述存储器控制器耦接至所述存储器;所述校验用存储区域存储有对应所述多个存储块的多个有效存储块的校验因子,所述校验因子包括校验码数据和为所述多个存储块配置的第一多个地址指针;每一个所述有效存储块中设置有第二多个地址指针,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块;其中,所述第一多个地址指针以及所述多个有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的全部有效存储块的地址链。
附图被并入本文并形成说明书的一部分,例示了本公开的实施例并与说明书一起进一步用以解释本公开的原理,并使相关领域的技术人员能够做出和使用本公开。
图1示出了根据本公开一实施例的用于存储器的数据保护方法的示意 图。
图2示出了根据本公开又一实施例的用于存储器的数据保护方法的示意图。
图3示出了根据本公开一实施例的用于存储器的数据保护方法的流程图;
图4示出了根据本公开一实施例的用于存储器的数据恢复方法的流程图;以及
图5示出了根据本公开一实施例的存储器系统的示意图。
现在将参考示例实施方式讨论本文描述的主题。应该理解,讨论这些实施方式只是为了使得本领域技术人员能够更好地理解从而实现本文描述的主题,并非是对权利要求书中所阐述的保护范围、适用性或者示例的限制。可以在不脱离本说明书内容的保护范围的情况下,对所讨论的元素的功能和排列进行改变。各个示例可以根据需要,省略、替代或者添加各种过程或组件。例如,所描述的方法可以按照与所描述的顺序不同的顺序来执行,以及各个步骤可以被添加、省略或者组合。另外,相对一些示例所描述的特征在其它例子中也可以进行组合。
要指出的是,在说明书中提到“一个实施例”、“实施例”、“一些实施例”等表示所述的实施例可包括特定的特征、结构或特性,但未必每个实施例都包括该特定特征、结构或特性。此外,这样的措辞用语未必是指相同的实施例。另外,在结合实施例描述特定的特征、结构或特性时,结合明确或未明确描述的其它实施例实现此类特征、结构或特性应在相关领域技术人员的知识范围之内。
尽管将参考3D NAND闪存存储器来描述本公开的实施例,但应当理解,本公开创造性概念的实施例不限于此配置。例如,在不脱离本公开的范围的情况下,本公开适用于其他非易失性存储器件,例如电可擦除可编程ROM(EEPROM)、NOR闪存、相变RAM(PRAM)、磁RAM(MRAM)、电阻RAM(RRAM)、铁电RAM(FRAM)等。
图1示出了根据本公开一实施例的用于存储器的数据保护方法的示意 图,其中,以位图形式记录跳过了哪些数据。也就是说,位图数据作为校验因子F的附加数据。如图1中所示,3D NAND闪存存储器100包括存储块D0、存储块D1、存储块D2、……、存储块Dn。在写入过程中,完成写入的存储块标记为“有效”并且在位图中以“0”来表示,未完成写入导致其写入的一部分数据不可用的存储块标记为“跳过”并且在位图中以“1”来表示。为了利用RAID技术来恢复在某一有效存储块中成功写入并且在写入完成后丢失的数据,在基于多个有效存储块中的存储数据计算校验码数据时将跳过这些标记为“1”的存储块中的不可用数据,并且在利用校验码数据恢复所述存储块中丢失的数据时也同样需要跳过这些标记为“1”的存储块中的不可用数据
然而,即使以位图形式进行压缩,仍然需要占用很大的存储器空间。在如图1所示的用于存储器的数据保护方法中,在RAID的比例(被保护数据的量和校验因子的量)为127:1的情况下,位图需要占用16个字节;在RAID的比例为255:1的情况下,位图更是需要占用32个字节。在作为校验因子F的附加数据的位图需要占用16个字节或32个字节的情况下,这将导致每个有效存储块的16个字节或32个字节的空间浪费而不能用于存储数据,因为即使在每个有效存储块的这些空间中写入数据,也无法在写入完成后利用RAID技术来恢复在某一有效存储块的该空间中成功写入且后来丢失的数据。因此,除了需要在校验因子F中保留很大的空间用于附加数据(例如,位图),从而极大降低系统的ECC纠错能力之外,每个有效存储块还浪费与该附加数据大小相同的空间。
图2示出了根据本公开又一实施例的用于存储器的数据保护方法的示意图。如图2中所示,3D NAND闪存存储器200包括存储块D0、存储块D1、存储块D2、……存储块D126。
如图2中所示,在3D NAND闪存存储器200的写入过程中,成功写入的存储块D标记为“有效”,例如存储块D0、存储块D2、……存储块D123、存储块D125、存储块D126。在写入过程中因为某些原因(例如,掉电、写入失败等)导致数据未能全部成功写入的存储块D标记为“跳过”,例如存储块D1、存储块D3、……存储块D124,被标记为“跳过”的存储块中的数据不可用。也就是说,在完成对存储器200的写入之后,如果某一有 效存储块D中存储的数据丢失,如果利用RAID技术来恢复该有效存储块D中丢失的数据,在计算用来恢复该有效存储块D中丢失的数据的校验码数据P时不能用到这些被标记为“跳过”的存储块D中写入的数据。
如图2中所示,校验码数据P可以通过对3D NAND闪存存储器200的全部存储块中的多个有效存储块D中存储的数据执行“异或”(XOR)操作来生成。在一个实施例中,校验码数据P可以通过对3D NAND闪存存储器200的全部有效存储块D中存储的数据执行“异或”(XOR)操作来生成。XOR是对两个操作数的逻辑运算,如果进行“异或”的两个值不同,则它产生逻辑值“1”;如果进行“异或”的两个值相同,则它产生逻辑值“0”。例如,如果有效存储块D0存储的数据为“11001010”,并且有效存储块D2存储的数据为“10000011”,则“异或”之后的结果为“01001001”。接下来,将上述结果与下一个有效存储块D中存储的数据再执行“异或”操作,直至全部有效存储块D中存储的数据都执行了“异或”操作,从而得到校验码数据P。
与图1所示的一样,用来恢复某一有效存储块D在写入完成后丢失的数据的校验因子F除了校验码数据P之外,同样还包括附加数据。但是与图1中使用位图作为校验因子F的附加数据不同的是,在图2中,使用地址链作为校验因子F的附加数据。例如,如图2中所示,校验因子F除了通过对多个有效存储块D中存储的数据进行“异或”操作得到的校验码数据P之外,还包括两个地址指针L1、L2,这两个地址指针L1、L2分别指向3D NAND闪存存储器200的相应一个有效存储块D。在一个实施例中,这两个地址指针L1、L2中分别记录了所述相应一个有效存储块D的编号。在这种情况下,如果RAID的比例为127:1,则这两个地址指针L1、L2可以只需要占用两个字节的空间;如果RAID的比例为255:1,则这两个地址指针L1、L2可以只需要占用四个字节的空间。
如图2中所示,作为校验因子F的附加数据的两个地址指针L1、L2可以分别指向3D NAND闪存存储器200中的从时间上来说最后成功写入的两个有效存储块之一。例如,地址指针L2指向最后成功写入的有效存储块D126,并且地址指针L1指向倒数第二个成功写入的有效存储块D125。应理解,图2中所示的情况是示例性的,假如最后一个存储块D126被标记为 “跳过”,从时间上来说最后成功写入的有效存储块为D125,并且从时间上来说倒数第二个成功写入的有效存储块为D124,则作为校验因子F的附加数据的地址指针L2指向有效存储块D125,并且地址指针L1指向有效存储块D124。
与图1中位图作为校验因子F的附加数据一样,在图2中,在校验因子F的两个地址指针L1、L2占用两个字节的空间的情况下,每个有效存储块D中除了写入的存储数据之外,还分别占用两个字节的空间来存储两个地址指针D
L1、D
L2,这两个地址指针D
L1、D
L2分别指向在完成对该有效存储块D的写入之前最近成功写入的两个有效存储块D之一。如图2中所示,有效存储块D126中除了存储的数据之外,还存储有两个地址指针D126
L1、D126
L2,其中地址指针D126
L2指向在对有效存储块D126成功写入之前从时间上来说最近成功写入的有效存储块,例如D125,并且地址指针D126
L1指向在对有效存储块D126成功写入之前倒数第二个成功写入的有效存储块,例如D123。因为存储块D124被标记为“跳过”,尽管存储块D124比存储块D123更接近有效存储块D126,但是地址指针D126
L1也不会指向存储块D124。类似地,有效存储块D125中除了存储的数据之外,还存储有两个地址指针D125
L1、D125
L2,其中地址指针D125
L2指向在对有效存储块D125成功写入之前最近成功写入的有效存储块,例如D123,并且地址指针D125
L1指向在对有效存储块D125成功写入之前倒数第二个成功写入的有效存储块,例如D122(图2中未示出)。因为存储块D124被标记为“跳过”,尽管存储块D124比存储块D123更接近有效存储块D125,但是有效存储块D125中的两个地址指针D125
L1、D125
L2都不会指向存储块D124。依次类推,可以确定每个有效存储块D存储的两个地址指针D
L1、D
L2分别所指向的存储块。
如图2中所示,对3D NAND闪存存储器200的写入过程如下:首先对存储块D0进行写入,假如对存储块D0写入成功(被标记为“有效”),因为在对存储块D0成功写入之前没有存储块D被成功写入,所以有效存储块D0中的两个地址指针D0
L1、D0
L2指向为空;接下来,对存储块D1进行写入,写入过程中,因为某一原因(例如,掉电)导致存储块D1未能成功写入(被标记为“跳过”);接下来,在恢复写入过程之后,对存储块D2进 行写入,假如对存储块D2成功写入(被标记为“有效”),因为在对存储块D2成功写入之前只有存储块D0成功写入,则有效存储块D2中的地址指针D2
L2指向有效存储块D0,并且有效存储块D2的地址指针D2
L1指向为空;接下来,对存储块D3进行写入,写入过程中,因为某一原因(例如,掉电)导致存储块D3未能成功写入(被标记为“跳过”);接下来,在恢复写入过程之后,对存储块D4(图2中未示出)进行写入,假如对存储块D4成功写入,因为在对存储块D4成功写入之前存储块D0、存储块D2被成功写入,则有效存储块D4中的地址指针D4
L2指向在有效存储块D4成功写入之前最近成功写入的有效存储块D2,并且有效存储块D4中的地址指针D4
L1指向在有效存储块D4成功写入之前倒数第二个成功写入的有效存储块D0,……,依次类推,直至完成所有存储块D的写入。
在完成3D NAND闪存存储器200的写入之后,如果某一有效存储块D存储的数据丢失,则利用RAID技术能够恢复该有效存储块D中丢失的数据。具体而言,为了恢复某一有效存储块D丢失的数据,除了需要在写入过程中基于3D NAND闪存存储器200的多个存储块中全部成功写入的有效存储块D中的存储数据得到的校验码数据P之外,还需要读取3D NAND闪存存储器200的多个存储块D中除丢失数据的有效存储块D之外的其他有效存储块D中的存储数据。为了读取除丢失数据的有效存储块D之外的其他有效存储块D中的存储数据,可以通过校验因子F中的地址指针以及除丢失数据的有效存储块D之外的其他有效存储块D中的地址指针形成的地址链来读取相应有效存储块D中存储的数据。例如,在完成对3D NAND闪存存储器200的写入之后,假设有效存储块D123中存储的数据丢失,为了恢复有效存储块D123中丢失的数据,根据校验因子F中的地址指针L2,知道存储块D126成功写入,因此需要读取有效存储块D126中的存储数据;接下来,根据有效存储块D126中的地址指针D126
L2,知道存储块D125成功写入,因此需要读取有效存储块D125中的存储数据;再接下来,因为有效存储块D125中的地址指针D125
L2指向存储块D123,但是存储块D123中的数据丢失已经无法读取,这时利用有效存储块D125中的地址指针D125
L1,知道存储块D122(图2中未示出)成功写入,因此需要读取有效存储块D122中的存储数据;再接下来,根据有效存储块D122中的地址指 针D122
L2,……;依次类推,直至有效存储块D0中的存储数据也被读取。由此可见,通过校验因子F中的地址指针以及除丢失数据的有效存储块D123之外的其他有效存储块D中的地址指针形成的地址链可以自动跳过3D NAND闪存存储器200中被标记为“跳过”的存储块D以及丢失数据的有效存储块D123。也就是说,该地址链自动跳过3D NAND闪存存储器200的多个存储块D中的无效存储块。在获得写入过程中基于3D NAND闪存存储器200的全部有效存储块D中的存储数据得到的校验码数据P以及读取到的除丢失数据的有效存储块D123之外的其他有效存储块D中的存储数据之后,可以对校验码数据P以及通过校验因子F中的地址指针和除丢失数据的有效存储块D123之外的其他有效存储块D中的地址指针形成的地址链读取的相应有效存储块D中的存储数据执行“异或”操作,以恢复存储块D123中丢失的数据。
在图2所示的实施例中,如果在完成对3D NAND闪存存储器200的写入之后,如果有效存储块D126中存储的数据丢失,为了利用RAID技术恢复该有效存储块D126中后来丢失的数据,需要读取除有效存储块D126之外的其他有效存储块D中的存储数据。校验因子F的地址指针L2指向存储块D126,因为此时已经无法读取到存储块D126中存储的数据,所以此时可以利用校验因子F的地址指针L1指向有效存储块D125,先读取有效存储块D125中存储的数据。接下来,根据有效存储块D125中的地址指针D125
L2,知道存储块D123成功写入,因此需要读取有效存储块D123中的存储数据;再接下来,根据有效存储块D123中的地址指针D123
L2,……;依次类推,直至有效存储块D0中的存储数据也被读取。同样地,在获得写入过程中基于3D NAND闪存存储器200的全部有效存储块D中的存储数据得到的校验码数据P以及通过校验因子F中的地址指针和除丢失数据的有效存储块D126之外的其他有效存储块D中的地址指针形成的地址链读取到的除丢失数据的有效存储块D126之外的其他有效存储块D中的存储数据之后,可以对校验码数据P以及所读取的相应有效存储块D中的存储数据执行“异或”操作,以恢复存储块D126中丢失的数据。
在一个实施例中,可以对生成的校验码数据P以及通过地址链读取的相应有效存储块的存储数据执行“异或”操作来恢复在写入过程之后某一 个有效存储块D中丢失的数据。例如,仍以图2所示的方法为例,假设在写入过程之后,有效存储块D123中存储的数据丢失。为了恢复有效存储块D123中丢失的数据,可以首先将生成的附加校验码P与通过校验因子F中的地址指针L2读取到的有效存储块D126中的存储数据执行“异或”操作,然后将所得结果与通过有效存储块D126中的地址指针L2读取到的有效存储块D125中的存储数据再执行“异或”操作,然后将所得结果与通过有效存储块D125中的地址指针L1读取到的有效存储块D122(图2中未示出)中的存储数据再执行“异或”操作,……,直至将所得结果与读取到的有效存储块D2中的存储数据再执行“异或”操作,从而获得上述多个“异或”操作的最终结果,该最终结果也是有效存储块D0中存储的数据与有效存储块123中原来存储的数据执行“异或”操作的结果。因此,通过对生成的校验码数据P以及通过地址链读取的相应有效存储块的存储数据执行“异或”操作可以恢复在写入过程之后有效存储块D123中丢失的数据。
在图2所示的实施例中,因为校验因子F的两个地址指针L1、L2分别指向3D NAND闪存存储器200的有效存储块D中最后成功写入的两个有效存储块之一,在不是最后成功写入的有效存储块D中存储的数据后来丢失时,利用校验因子F的地址指针L2以及除丢失数据的有效存储块D之外的其他有效存储块D中的地址指针形成的地址链,来读取除数据丢失的有效存储块D之外的其他有效存储块D中存储的数据。另外,即使在最后成功写入的有效存储块D(例如,存储块D126)中存储的数据后来丢失时,也可以利用校验因子F的地址指针L1以及除最后成功写入的有效存储块D之外的其他有效存储块D中的地址指针形成的地址链,来读取除最后成功写入的有效存储块D之外的其他有效存储块D中存储的数据。由于可以根据发生数据丢失的有效存储块D的位置选择性地利用校验因子F的两个地址指针L1、L2之一作为链首的地址链来读取相应有效存储块D中存储的数据,所以不会发生断链。相反地,如果校验因子F只有一个地址指针L并且该地址指针L指向有效存储块中最后成功写入的有效存储块D,例如有效存储块D126,当有效存储块D126中存储的数据丢失时,将不能读取除有效存储块D126之外的其他有效存储块D中存储的数据。也就是说,这时将发生断链,从而无法利用RAID技术来恢复存储块D126中丢失的数 据。
另外,在RAID的比例为127:1的情况下,如果如图1所示的以位图形式记录跳过了哪些数据,作为校验因子F的附加数据的位图需要占用16个字节的空间,并且每个有效存储块D也相应地浪费16个字节的空间;而如图2所示的以地址链的形式记录哪些存储块存储中的数据有效,作为校验因子F的附加数据的地址链只需要占用2个字节的空间,并且每个有效存储块D也相应地只浪费例如2个字节的空间,从而大大节省存储器的空间。
应理解,图2中所示的校验因子F包括两个地址指针L1、L2以及每个有效存储块D包括两个地址指针仅仅是示例性的。在一个实施例中,校验因子F可以包括N个地址指针(N为大于或等于2的整数),其分别指向3D NAND闪存存储器200的有效存储块D中的最后成功写入的N个有效存储块之一。在这种情况下,每个有效存储块D除了所写入的存储数据之外,同样包括N个地址指针(N为大于或等于2的整数),其分别指向在相应有效存储块D成功写入之前最近成功写入的N个有效存储块D之一。例如,校验因子F可以包括三个地址指针L1、L2、L3并且每个有效存储块D可以包括三个地址指针,校验因子F的地址指针L3指向有效存储块D中的最后成功写入的有效存储块,地址指针L2指向有效存储块D中倒数第二个成功写入的有效存储块,并且地址指针L1指向有效存储块D中倒数第三个成功写入的有效存储块。相应地,每个有效存储块D的三个地址指针分别指向在该有效存储块D成功写入之前最近成功写入的三个有效存储块之一。
图3示出了根据本公开一实施例的用于存储器的数据保护方法的流程图,存储器包括多个存储块。如图3中所示,方法300包括:基于所述多个存储块中的多个有效存储块的存储数据生成校验因子的校验码数据(步骤S310);在所述校验因子中为所述多个存储块配置第一多个地址指针(步骤S320);以及在每一个所述有效存储块中设置第二多个地址指针,其中,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,所述第一多个地址指针以及所述多个有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的全部有效存储块的 地址链(步骤S330)。步骤S310-S330说明如下:
步骤S310:基于所述多个存储块中的多个有效存储块的存储数据生成校验因子的校验码数据。仍以图2所示的方法为例,在3D NAND闪存存储器的写入过程中,可以对全部有效存储块D中存储的数据执行“异或”操作生成校验因子F的校验码数据P。
步骤S320:在所述校验因子中为所述多个存储块配置第一多个地址指针。如图2中所示,校验因子F除了在步骤S310中得到的校验码数据P之外,还包括为所述多个存储块配置的作为附加数据的两个地址指针L1、L2,所述两个地址指针L1、L2分别指向所述多个有效存储块中的最后成功写入的两个有效存储块之一。
步骤S330:在每一个所述有效存储块中设置第二多个地址指针,其中,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,所述第一多个地址指针以及所述多个有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的全部有效存储块的地址链。仍以图2所示的方法为例,每一个有效存储块D中除了写入的存储数据之外,还设置有两个地址指针,所述两个地址指针分别指向在该有效存储块D成功写入之前最近成功写入的两个有效存储块之一。校验因子F的两个地址指针L1、L2以及每一个有效存储块D的两个地址指针能够一起形成覆盖全部有效存储块D的地址链。
图4示出了根据本公开一实施例的用于存储器的数据恢复方法的流程图,所述存储器包括多个存储块。如图4中所示,方法400包括:确定所述多个存储块中的多个有效存储块的某一个有效存储块的数据丢失(步骤S410);以及基于校验因子的校验码数据以及通过地址链读取所述多个有效存储块的相应有效存储块的存储数据,来恢复所述某一个有效存储块所丢失的数据,其中,所述校验因子包括所述校验码数据和为所述多个存储块配置的第一多个地址指针,所述地址链通过所述第一多个地址指针以及在每一个所述有效存储块中设置的第二多个地址指针形成,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,从而所述地址链能够覆盖所述多个有效存储块的全部有效存储块(步骤S420)。
仍以图2所示的方法为例,首先确定多个有效存储块的某一个有效存储块D的数据丢失,例如,在写入过程之后,确定存储块D123中存储的数据丢失;然后读取除丢失数据的有效存储块D123之外的其他有效存储块D中的存储数据,为了读取其他有效存储块D中的存储数据,可以通过校验因子F中的两个地址指针以及其他有效存储块D中的地址指针形成的地址链来读取除有效存储块D123之外的全部有效存储块D中存储的数据;最后,可以对写入过程中基于3D NAND闪存存储器200的全部有效存储块D中的存储数据得到的校验码数据P以及通过所述地址链读取到的除有效存储块D123之外的全部有效存储块D中的存储数据执行“异或”操作,以恢复存储块D123中丢失的数据。
图5示出了根据本公开一实施例的具有存储器的系统500的示意图。系统500可以是移动电话、台式计算机、膝上型计算机、平板计算机、游戏控制台、打印机、定位设备、可穿戴电子设备、智能传感器、虚拟现实(VR)设备、增强现实(AR)设备或具有存储器的任何其他合适电子设备。如图5中所示,系统500可以包括主机510和具有一个或多个存储器501和存储器控制器502的存储器系统520。主机510可以被配置为将数据发送到存储器501或从存储器501接收数据。
存储器501可以是本文所公开的任何存储器,例如3D NAND闪存存储器,其包括检验用存储区域5011和多个存储块,例如存储块0、存储块1、存储块2、……、存储块n。检验用存储区域5011存储有对应多个存储块的多个有效存储块的校验因子,所述校验因子包括校验码数据和为所述多个存储块配置的第一多个地址指针。另外,存储器501的多个存储块的每一个有效存储块中设置有第二多个地址指针,每一个有效存储块的第二多个地址指针中的每一个分别指向相应一个其他有效存储块。其中,第一多个地址指针以及所述多个有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的全部有效存储块的地址链。
如图5中所示,存储器控制器502包括前端接口5021和后端接口5022,前端接口5021通过通道Lane 0、Lane 1、Lane2、Lane3耦接到主机510,并且后端接口5022通过通道CH0、CH1、……、CHn耦接到存储器501的检验用存储区域5011以及相应存储块,其中前端接口5021可以根据特定通信协 议(例如,PCIe、NVMe)与主机510通信;后端接口5022包括RAID模块。RAID模块具体可以通过例如在后端接口5022的控制器中所写入的固件(Firmware)等实现,也可以通过专用的硬件引擎电路实现。
在一个实施例中,RAID模块可以被配置为基于存储器501的多个存储块中的多个有效存储块的存储数据生成校验因子的校验码数据;在所述校验因子中为所述多个存储块配置第一多个地址指针;以及在每一个所述有效存储块中针对其存储的存储数据设置第二多个地址指针,其中,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,所述第一多个地址指针以及所述多个有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的全部有效存储块的地址链。在另一实施例中,RAID模块可以被配置为确定存储器501的多个存储块中的多个有效存储块的某一个有效存储块的数据丢失;以及基于校验因子的校验码数据以及通过地址链读取所述多个有效存储块的相应有效存储块的存储数据,来恢复所述某一个有效存储块所丢失的数据;其中,所述校验因子包括校验码数据和为所述多个存储块配置的第一多个地址指针,所述地址链通过所述第一多个地址指针以及在每一个所述有效存储块中针对其存储的所述存储数据而设置的第二多个地址指针形成,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,从而所述地址链能够覆盖所述多个有效存储块的全部有效存储块。
存储器控制器502还包括具有处理单元1、处理单元2、……、处理单元n的处理模块5023,对应处理单元可以配置有相应的固件,例如,实现FTL(Flash to Logic,闪存到逻辑)功能的固件,处理单元上运行的相应固件可以基于接收的来自主机510的指令来控制存储器501的操作,例如,读取、擦除和编程操作。存储器控制器502还包括静态随机存取存储器(SRAM)5024、动态随机存取存储器(DRAM)控制器5025、动态随机存取存储器(DRAM)接口5026,其中动态随机存取存储器(DRAM)接口5026耦接至动态随机存取存储器(DRAM)503。如图5中所示,存储器控制器502的各部件可以连接至总线&电桥5027。
如上所述,根据本公开一实施例的存储器系统520能够利用地址链作为校验因子的附加数据,从而能够大大降低对校验因子的附加数据的空间 要求,维持系统的ECC纠错能力,并且大大降低存储器的空间浪费。
根据一个实施例,提供了一种计算机可读存储介质,在其上存储有程序代码,当所述程序代码由处理器执行时,使得所述处理器能够执行本说明书结合图1-4描述的各个实施例中的各种操作和功能。具体地,可以提供配有可读存储介质的系统或者装置,在该可读存储介质上存储着实现上述实施例中任一实施例的功能的软件程序代码,且使该系统或者装置的计算机或处理器读出并执行存储在该可读存储介质中的指令。
可读存储介质的实施例包括非易失性存储卡和ROM等。可选择地,可以由通信网络从服务器计算机上或云上下载程序代码。
需要说明的是,上述各流程和各系统结构图中不是所有的步骤和单元都是必须的,可以根据实际的需要忽略某些步骤或单元。各步骤的执行顺序不是固定的,可以根据需要进行确定。上述各实施例中描述的装置结构可以是物理结构,也可以是逻辑结构,即,有些单元可能由同一物理实体实现,或者,有些单元可能分由多个物理实体实现,或者,可以由多个独立设备中的某些部件共同实现。
已经结合各种装置和方法描述了控制器。所述控制器可以使用电子硬件、计算机软件或其任意组合来实施。所述控制器是实施为硬件还是软件将取决于具体的应用以及施加在系统上的总体设计约束。作为示例,本公开中给出的控制器、控制器的任意部分、或者控制器的任意组合可以实施为微处理器、微控制器、数字信号处理器(DSP)、现场可编程门阵列(FPGA)、可编程逻辑器件(PLD)、状态机、门逻辑、分立硬件电路、以及配置用于执行在本公开中描述的各种功能的其它适合的处理部件。本公开给出的控制器、控制器的任意部分、或者控制器的任意组合的功能可以实施为由微处理器、微控制器、DSP或其它适合的平台所执行的软件。
本公开内容的上述描述被提供来使得本领域任何普通技术人员能够实现或者使用本公开内容。对于本领域普通技术人员来说,对本公开内容进行的各种修改是显而易见的,并且,也可以在不脱离本公开内容的保护范围的情况下,将本文所定义的一般性原理应用于其它变型。因此,本公开内容并不限于本文所描述的示例和设计,而是与符合本文公开的原理和新颖性特征的最广范围相一致。
Claims (31)
- 一种用于存储器的数据保护方法,所述存储器包括多个存储块,所述方法包括:基于所述多个存储块中的多个有效存储块的存储数据生成校验因子的校验码数据;在所述校验因子中为所述多个存储块配置第一多个地址指针;以及在每一个所述有效存储块中设置第二多个地址指针,其中,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,所述第一多个地址指针以及所述多个有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的全部有效存储块的地址链。
- 根据权利要求1所述的方法,其中,所述第一多个地址指针为2个地址指针,所述第二多个地址指针为2个地址指针,在所述多个有效存储块的某一个有效存储块的数据丢失及其对应设置的第二多个地址指针丢失的情况下,所述第一多个地址指针以及所述多个有效存储块的其他有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的其他有效存储块的全部有效存储块的地址链。
- 根据权利要求1所述的方法,其中,还包括步骤:当所述多个有效存储块中的某一个有效存储块的数据丢失时,基于所述校验因子的所述校验码数据以及通过所述第一多个地址指针和所述多个有效存储块的其他有效存储块的第二多个地址指针形成的地址链读取所述多个有效存储块的相应有效存储块的存储数据,来恢复所述某一个有效存储块所丢失的数据。
- 根据权利要求1所述的方法,其中,所述第一多个地址指针为N个地址指针,所述第二多个地址指针为N个地址指针,N为大于或等于2的整数;针对某一个有效存储块设置的N个地址指针分别指向在所述某一个有 效存储块成功写入之前最近成功写入的N个有效存储块之一;所述校验因子的N个地址指针分别指向所述有效存储块中的最后成功写入的N个有效存储块之一。
- 根据权利要求4所述的方法,其中,所述多个存储块的多个有效存储块的最先成功写入的有效存储块的N个地址指针指向为空,所述多个存储块的第(N-M)个成功写入的有效存储块的N个地址指针中,(M+1)个地址指针指向为空,M为大于或等于0且小于N的整数。
- 根据权利要求1所述的方法,其中,所述地址链自动跳过所述多个存储块中的无效存储块。
- 根据权利要求1所述的方法,其中,基于所述多个存储块中的全部有效存储块的存储数据生成所述校验因子的校验码数据。
- 根据权利要求1所述的方法,其中,对所述多个存储块中的所述多个有效存储块的存储数据执行异或操作来生成所述校验因子的校验码数据。
- 根据权利要求3所述的方法,其中,对所述校验码数据以及通过所述地址链读取的相应有效存储块的存储数据执行异或操作来恢复所述某一个有效存储块所丢失的数据。
- 根据权利要求1所述的方法,其中,所述存储器为3D NAND闪存存储器。
- 一种用于存储器的数据恢复方法,所述存储器包括多个存储块,所述方法包括:确定所述多个存储块中的多个有效存储块的某一个有效存储块的数据丢失;以及基于校验因子的校验码数据以及通过地址链读取所述多个有效存储块的相应有效存储块的存储数据,来恢复所述某一个有效存储块所丢失的数据;其中,所述校验因子包括所述校验码数据和为所述多个存储块配置的第一多个地址指针,所述地址链通过所述第一多个地址指针以及在每一个所述有效存储块中设置的第二多个地址指针形成,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,从而所述地址链能够覆盖所述多个有效存储块的全部有效存储块。
- 根据权利要求11所述的方法,其中,所述第一多个地址指针为2个地址指针,所述第二多个地址指针为2个地址指针,在所述多个有效存储块的某一个有效存储块的数据丢失及其对应设置的第二多个地址指针丢失的情况下,所述第一多个地址指针以及所述多个有效存储块的其他有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的其他有效存储块的全部有效存储块的地址链。
- 根据权利要求11所述的方法,其中,在读取某一个有效存储块的存储数据时,存储在所述某一个有效存储块的第二多个地址指针也被读取,并且基于所述第二多个地址指针确定接下来读取的相应有效存储块。
- 根据权利要求11所述的方法,其中,所述第一多个地址指针为N个地址指针,所述第二多个地址指针为N个地址指针,N为大于或等于2的整数;针对某一个有效存储块设置的N个地址指针分别指向在所述某一个有效存储块成功写入之前最近成功写入的N个有效存储块之一;所述校验因子的N个地址指针分别指向所述有效存储块中的最后成功写入的N个有效存储块之一。
- 根据权利要求11所述的方法,其中,对所述校验码数据以及通过所述地址链读取的相应有效存储块的存储数据执行异或操作来恢复所述某 一个有效存储块所丢失的数据。
- 一种存储器系统,包括:存储器,所述存储器包括多个存储块;以及存储器控制器,所述存储器控制器耦接至所述存储器并且被配置为:基于所述多个存储块中的多个有效存储块的存储数据生成校验因子的校验码数据;在所述校验因子中为所述多个存储块配置第一多个地址指针;以及在每一个所述有效存储块中设置第二多个地址指针,其中,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,所述第一多个地址指针以及所述多个有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的全部有效存储块的地址链。
- 根据权利要求16所述的存储器系统,其中,所述第一多个地址指针为2个地址指针,所述第二多个地址指针为2个地址指针,在所述多个有效存储块的某一个有效存储块的数据丢失及其对应设置的第二多个地址指针丢失的情况下,所述第一多个地址指针以及所述多个有效存储块的其他有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的其他有效存储块的全部有效存储块的地址链。
- 根据权利要求16所述的存储器系统,其中,所述控制器还被配置为当所述多个有效存储块中的某一个有效存储块的数据丢失时,基于所述校验因子的所述校验码数据以及通过所述第一多个地址指针和所述多个有效存储块的其他有效存储块的第二多个地址指针形成的地址链读取所述多个有效存储块的相应有效存储块的存储数据,来恢复所述某一个有效存储块所丢失的数据。
- 根据权利要求16所述的存储器系统,其中,所述第一多个地址指针为N个地址指针,所述第二多个地址指针为N个地址指针,N为大于或等于2的整数;针对某一个有效存储块设置的N个地址指针分别指向在所述某一个有 效存储块成功写入之前最近成功写入的N个有效存储块之一;所述校验因子的N个地址指针分别指向所述有效存储块中的最后成功写入的N个有效存储块之一。
- 根据权利要求19所述的存储器系统,其中,所述多个存储块的多个有效存储块的最先成功写入的有效存储块的N个地址指针指向为空,所述多个存储块的第(N-M)个成功写入的有效存储块的N个地址指针中,(M+1)个地址指针指向为空,M为大于或等于0且小于N的整数。
- 根据权利要求16所述的存储器系统,其中,所述地址链自动跳过所述多个存储块中的无效存储块。
- 根据权利要求16所述的存储器系统,所述控制器被配置为基于所述多个存储块中的全部有效存储块的存储数据生成所述校验因子的校验码数据。
- 根据权利要求16所述的存储器系统,所述控制器被配置为对所述多个存储块中的所述多个有效存储块的存储数据执行异或操作来生成所述校验因子的校验码数据。
- 根据权利要求18所述的存储器系统,所述控制器被配置为对所述校验码数据以及通过所述地址链读取的相应有效存储块的存储数据执行异或操作来恢复所述某一个有效存储块所丢失的数据。
- 根据权利要求16所述的存储器系统,其中,所述存储器为3D NAND闪存存储器。
- 一种存储器系统,包括:存储器,所述存储器包括多个存储块;以及存储器控制器,所述存储器控制器耦接至所述存储器并且被配置为: 确定所述多个存储块中的多个有效存储块的某一个有效存储块的数据丢失;以及基于校验因子的校验码数据以及通过地址链读取所述多个有效存储块的相应有效存储块的存储数据,来恢复所述某一个有效存储块所丢失的数据;其中,所述校验因子包括校验码数据和为所述多个存储块配置的第一多个地址指针,所述地址链通过所述第一多个地址指针以及在每一个所述有效存储块中设置的第二多个地址指针形成,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块,从而所述地址链能够覆盖所述多个有效存储块的全部有效存储块。
- 根据权利要求26所述的存储器系统,其中,所述第一多个地址指针为2个地址指针,所述第二多个地址指针为2个地址指针,在所述多个有效存储块的某一个有效存储块的数据丢失及其对应设置的第二多个地址指针丢失的情况下,所述第一多个地址指针以及所述多个有效存储块的其他有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的其他有效存储块的全部有效存储块的地址链。
- 根据权利要求26所述的存储器系统,所述存储器控制器被配置为在读取某一个有效存储块的存储数据时,存储在所述某一个有效存储块的第二多个地址指针也被读取,并且基于所述第二多个地址指针确定接下来读取的相应有效存储块。
- 根据权利要求26所述的存储器系统,其中,所述第一多个地址指针为N个地址指针,所述第二多个地址指针为N个地址指针,N为大于或等于2的整数;针对某一个有效存储块设置的N个地址指针分别指向在所述某一个有效存储块成功写入之前最近成功写入的N个有效存储块之一;所述校验因子的N个地址指针分别指向所述有效存储块中的最后成功写入的N个有效存储块之一。
- 根据权利要求26所述的存储器系统,所述存储器控制器被配置为 对所述校验码数据以及通过所述地址链读取的相应有效存储块的存储数据执行异或操作来恢复所述某一个有效存储块所丢失的数据。
- 一种存储器系统,包括:存储器,所述存储器包括校验用存储区域和多个存储块;以及存储器控制器,所述存储器控制器耦接至所述存储器;所述校验用存储区域存储有对应所述多个存储块的多个有效存储块的校验因子,所述校验因子包括校验码数据和为所述多个存储块配置的第一多个地址指针;每一个所述有效存储块中设置有第二多个地址指针,每一个所述有效存储块中的第二多个地址指针中的每一个分别指向相应一个其他有效存储块;其中,所述第一多个地址指针以及所述多个有效存储块的第二多个地址指针能够一起形成覆盖所述多个有效存储块的全部有效存储块的地址链。
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US20180074891A1 (en) * | 2016-09-13 | 2018-03-15 | Sandisk Technologies Llc | Storage System and Method for Reducing XOR Recovery Time |
CN108108148A (zh) * | 2016-11-24 | 2018-06-01 | 舒尔电子(苏州)有限公司 | 一种数据处理方法和装置 |
US20200057578A1 (en) * | 2017-12-19 | 2020-02-20 | Western Digital Technologies, Inc. | Nvme controller memory manager |
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CN114080596A (zh) | 2022-02-22 |
US20230103004A1 (en) | 2023-03-30 |
US20240319926A1 (en) | 2024-09-26 |
US12032860B2 (en) | 2024-07-09 |
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