WO2023030239A1 - 像素电路、图像传感器及电子设备 - Google Patents

像素电路、图像传感器及电子设备 Download PDF

Info

Publication number
WO2023030239A1
WO2023030239A1 PCT/CN2022/115459 CN2022115459W WO2023030239A1 WO 2023030239 A1 WO2023030239 A1 WO 2023030239A1 CN 2022115459 W CN2022115459 W CN 2022115459W WO 2023030239 A1 WO2023030239 A1 WO 2023030239A1
Authority
WO
WIPO (PCT)
Prior art keywords
processing module
photoelectric conversion
reset
signal
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/115459
Other languages
English (en)
French (fr)
Inventor
刘林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vivo Mobile Communication Co Ltd
Original Assignee
Vivo Mobile Communication Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vivo Mobile Communication Co Ltd filed Critical Vivo Mobile Communication Co Ltd
Publication of WO2023030239A1 publication Critical patent/WO2023030239A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS

Definitions

  • the present application belongs to the field of electrical technology, and in particular relates to a pixel circuit, an image sensor and electronic equipment.
  • CMOS image sensor Complementary Metal-Oxide-Semiconductor (CMOS) image sensor (CMOS image sensor, CIS) is an important part of imaging in electronic equipment. If the dynamic range of the CMOS image sensor in the electronic device is insufficient, when the electronic device takes a picture in a bright and strong light scene, overexposure may occur, resulting in image distortion and ultimately affecting imaging.
  • CMOS image sensor Complementary Metal-Oxide-Semiconductor
  • the embodiment of the present application provides a pixel circuit, including: a photoelectric conversion processing module, a reset control module, and a comparison processing module; wherein,
  • Both the photoelectric conversion processing module and the reset control module are connected to the comparison processing module, and the reset control module is connected to the photoelectric conversion processing module;
  • the photoelectric conversion processing module is used to photoelectrically convert the received optical signal to obtain a first electrical signal, and transmit the first electrical signal to the comparison processing module;
  • the comparison processing module outputs a reset control signal to the reset control module when the first voltage value corresponding to the first electrical signal is less than a preset voltage value, and records the number of times the reset control signal is output ;
  • the reset control module is used to reset the photoelectric conversion processing module according to the reset control signal.
  • the embodiment of the present application further provides an image sensor, including the above-mentioned pixel circuit.
  • the embodiment of the present application further provides an electronic device, including the above-mentioned image sensor.
  • a comparison processing module is set in the pixel circuit, and the first voltage value of the first electrical signal obtained by photoelectric conversion by the photoelectric conversion processing module through the comparison processing module is less than the preset voltage value
  • the reset control module is controlled to reset the photoelectric conversion processing module, so that the photoelectric conversion processing module can continue to perform photoelectric conversion, and record and output the Number of reset control signals.
  • the overflow signal can be collected according to the recorded number of times the reset control signal is output. Electrical signals to avoid image distortion, solve the current problem of image distortion due to insufficient dynamic range of the CMOS image sensor, so as to ensure the imaging effect.
  • Fig. 1 shows one of the structural block diagrams of the pixel circuit of the embodiment of the present application
  • FIG. 2 shows the second structural block diagram of the pixel circuit in the embodiment of the present application
  • FIG. 3 shows the third structural block diagram of the pixel circuit in the embodiment of the present application
  • FIG. 4 shows one of the schematic diagrams of the pixel circuit of the embodiment of the present application
  • FIG. 5 shows the fourth structural block diagram of the pixel circuit in the embodiment of the present application.
  • FIG. 6 shows the second schematic diagram of the pixel circuit of the embodiment of the present application.
  • FIG. 7 shows a timing diagram of control signals and outputs of some devices in the pixel circuit according to the embodiment of the present application.
  • the embodiment of the present application provides a pixel circuit, including: a photoelectric conversion processing module 10 , a reset control module 20 and a comparison processing module 30 .
  • both the photoelectric conversion processing module 10 and the reset control module 20 are connected to the comparison processing module 30 , and the reset control module 20 is connected to the photoelectric conversion processing module 10 .
  • the photoelectric conversion processing module 10 is used to photoelectrically convert the received optical signal to obtain a first electrical signal, and transmit the first electrical signal to the comparison processing module 30; the comparison processing module 30 When the first voltage value corresponding to the first electrical signal is less than a preset voltage value, output a reset control signal to the reset control module 20, and record the number of times the reset control signal is output; the reset control module The group 20 is used to reset the photoelectric conversion processing module 10 according to the reset control signal.
  • the photoelectric conversion processing module 10 can be used to perform photoelectric conversion on the received optical signal, that is, convert the received optical signal into an electrical signal, and perform energy storage processing on the converted electrical signal to obtain a corresponding
  • the first electrical signal is used to transmit the first electrical signal to the comparison processing module 30 .
  • the preset voltage value can be output by the photoelectric conversion processing module 10 when the photoelectric conversion processing module 10 reaches the full well capacity (that is, the maximum number of electrons that can be accommodated by the potential well of the pixel) when the photoelectric conversion processing module 10 performs photoelectric conversion.
  • the voltage value is determined.
  • the preset voltage value may be slightly greater than the voltage value output by the photoelectric conversion processing module 10 when the well capacity is full.
  • the voltage value of the photoelectric conversion processing module 10 in the reset state (the initial state when the photoelectric conversion processing module 10 is not performing photoelectric conversion) is 2.80V, and the photoelectric conversion processing module 10 reaches full capacity when performing photoelectric conversion.
  • the voltage value at the well capacity is 1.80V
  • the preset voltage value can be within the open range of 1.80V ⁇ 1.82V (for example, the preset voltage value can be set to 1.81V), of course, the embodiment of the present application is not limited to this .
  • the working process of the pixel circuit can be: in the initial state, the photoelectric conversion processing module 10 can be reset by the reset control module 20 first, so as to ensure the accuracy of collecting optical signals. After the photoelectric conversion processing module 10 is reset, the photoelectric conversion processing module 10 is exposed, so that the photoelectric conversion processing module 10 can perform photoelectric conversion on the received optical signal to obtain a first electrical signal, and convert the second electrical signal An electrical signal is transmitted to the comparison processing module 30 .
  • the preset voltage value is determined according to the voltage value output by the photoelectric conversion processing module 10 when the photoelectric conversion processing module 10 reaches the full well capacity, if the first voltage value corresponding to the first signal is less than the preset voltage value, it means that the The photoelectric conversion processing module 10 has reached the full well capacity when performing photoelectric conversion; if the first voltage value corresponding to the first signal is greater than or equal to the preset voltage value, it means that the photoelectric conversion processing module 10 has not reached the full well capacity when performing photoelectric conversion. Reach full well capacity.
  • the comparison processing module 30 can output a reset control signal to the reset control module 20 when the voltage value corresponding to the first electrical signal is less than a preset voltage value, so that the reset control module 20 can compare the photoelectric conversion processing module 10 resets, then the photoelectric conversion processing module can continue to carry out the photoelectric conversion processing, and record the number of times of outputting the reset control signal (that is, count the number of times that the photoelectric conversion processing module 10 reaches the full well capacity when performing photoelectric conversion); compare When the voltage value corresponding to the first electrical signal is greater than or equal to the preset voltage value, the processing module 30 will not output a reset control signal for controlling the reset control module 20 to reset the photoelectric conversion processing module 10 , and no cumulative counting is performed until the end of the exposure process.
  • recording the number of times the reset control signal is output during the exposure process may include: during one exposure process, recording an initial count value of 0 in the initial state, and detecting the first electrical signal once by the comparison processing module 30 When the corresponding voltage value is less than the preset voltage value (i.e. reaches the full well capacity), record the count value plus 1 until the end of the exposure process to obtain the accumulated count value; for example: during the exposure process, the comparison processing module 30 detects 4 times The voltage value corresponding to the first electrical signal is less than the preset voltage value, and the accumulated count value is 4, and then the electrical signal overflowed during the photoelectric conversion process can be determined according to the accumulated count value. At the end of this exposure process, the count value is reset to 0, so as to count the number of times of reaching the full well capacity in the next exposure process.
  • a comparison processing module 30 is provided in the pixel circuit, and the first voltage value of the first electrical signal obtained by performing photoelectric conversion in the photoelectric conversion processing module 10 through the comparison processing module 30 is less than the preset voltage value.
  • the reset control module 20 is controlled to reset the photoelectric conversion processing module 10, so that the photoelectric conversion processing module 10 can continue to perform photoelectric conversion, and record The number of times to output the reset control signal.
  • the optical signal received by the photoelectric conversion processing module 10 is too strong, causing the electrical signal to overflow when the photoelectric conversion processing module 10 performs photoelectric conversion, it can be collected according to the recorded times of outputting the reset control signal.
  • the overflow electrical signal avoids image distortion, and solves the current problem of image distortion due to insufficient dynamic range of the CMOS image sensor, so as to ensure the imaging effect.
  • the comparison processing module 30 includes: a comparator (Comparer) 31 and a counter (Counter) 32 .
  • the first input terminal of the comparator 31 is connected to the photoelectric conversion processing module 10
  • the second input terminal of the comparator 31 is used to input a preset voltage signal
  • the output terminal of the comparator 31 is connected to the
  • the reset control module 20 is connected to the counter 32; the voltage value of the preset voltage signal is the preset voltage value.
  • the comparator 31 is configured to output the reset control signal to the reset control module 20 and output a count signal to the counter 32 when the first voltage value is less than the preset voltage value;
  • the counter 32 records the number of times plus 1 according to the count signal.
  • the preset voltage signal may be generated by a reference circuit
  • the reference circuit may be a preset reference circuit (such as a voltage divider circuit, a constant voltage power supply circuit, etc.) for generating the preset voltage signal
  • the preset voltage signal output terminal of the reference circuit (such as the voltage division output terminal of the voltage divider circuit, the voltage output terminal of the constant voltage power supply circuit, etc.) is connected with the second input terminal of the comparator 31, so that the reference circuit can directly Output the preset voltage signal to the second input terminal of the comparator 31; of course, the embodiment of the present application can also use other methods to provide the preset voltage signal of the second input terminal of the comparator 31, which is not used here limit.
  • the comparator 31 when the first voltage value of the first electrical signal obtained by photoelectric conversion by the photoelectric conversion processing module 10 is less than the preset voltage value, the comparator 31 outputs a count signal to the counter 32, and passes The counter 32 records the number of times plus 1, that is, counts the number of times that the photoelectric conversion processing module 10 reaches the full well capacity when performing photoelectric conversion; and outputs a reset control signal to the reset control module 20, and controls the reset control module 20 reset the photoelectric conversion processing module 10, so that the photoelectric conversion processing module 10 can continue to perform the next photoelectric conversion processing after the photoelectric conversion processing module 10 reaches the full well capacity.
  • the reset control signal can be output according to the number of times recorded by the counter. , to collect overflowing electrical signals to avoid image distortion, and solve the current problem of image distortion due to the insufficient dynamic range of the CMOS image sensor, so as to ensure the imaging effect.
  • the reset control module 20 includes: a first logic gate control unit 21 and a reset switch unit 22; wherein, the first input terminal of the first logic gate control unit 21 is connected to the comparison processing module 30 The second input terminal of the first logic gate control unit 21 is used to input the first control signal, and the output terminal of the first logic gate control unit 21 is connected to the control terminal of the reset switch unit 22 .
  • the first logic gate control unit 21 is configured to output a second control signal to the The control terminal of the reset switch unit; the reset switch unit 22 is used to reset the photoelectric conversion processing module 10 under the control of the second control signal.
  • the first logic gate control unit 21 may include a combination of one or more logic gates, so that the first logic gate control unit 21 can realize that when the voltage of the reset control signal is the first voltage value or the In the case where the voltage of the first control signal is the first voltage value, it is enough to output the second control signal whose voltage is the first voltage value, and this embodiment of the present application is not limited thereto.
  • the logic gate may be a first logic OR gate, and the first input end of the first logic OR gate is connected to the comparison processing module 30 , the second input terminal of the first logical OR gate is used to input the first control signal, and the output terminal of the first logical OR gate is connected to the control terminal of the reset switch unit 22, so as to ensure that When the voltage of the control signal is the first voltage value or the voltage of the first control signal is the first voltage value, the output voltage is the second control signal of the first voltage value, which is beneficial to reduce the complexity of structural design.
  • the first voltage value may be a value satisfying a preset voltage range, for example, the first voltage value is a voltage value satisfying the conduction of the reset switch unit 22 to reset the photoelectric conversion processing module 10, the first The voltage value may also be referred to as a high level.
  • the first control signal may be a predetermined control signal; if the voltage of the first control signal during the exposure process is a second voltage value, the second voltage value may be called a low level.
  • the first control signal may have a high voltage for a period of time during the signal reading (Readout) process after the exposure process, so that the photoelectric conversion processing module 10 can be reset when the signal is read, and the interference can be eliminated. , so as to ensure the accuracy of signal reading.
  • the first input terminal of the comparator 31 is a negative input terminal, and the second input terminal of the comparator 31 is a positive input terminal;
  • a high-level signal that is, the voltage of the reset control signal is the first voltage value
  • the first A logic gate control unit 21 also outputs a high-level signal (i.e. a second control signal) to the control terminal of the reset switch unit 22 to control the reset switch unit 22 to be in a conduction state, so that the photoelectric conversion processing module Group 10 resets.
  • the first voltage value of the first electrical signal is greater than or equal to the preset voltage value, if the first control signal has a time period in which the voltage is high, the Readout operation can be performed, that is Reading the electrical signal obtained when the photoelectric conversion processing module 10 performs photoelectric conversion and does not reach the full well capacity during the exposure process.
  • the photoelectric conversion processing module 10 includes: a photoelectric conversion unit 11 , an energy storage unit 12 , a second logic gate control unit 13 and a transmission switch unit 14 .
  • one end of the photoelectric conversion unit 11 is connected to the first end of the transmission switch unit 14, and the other end of the photoelectric conversion unit 11 is connected to the first voltage end; one end of the energy storage unit 12 is respectively connected to the The reset switch unit 22 is connected to the transmission switch unit 14, the other end of the energy storage unit 12 is connected to the second voltage end; the first input end of the second logic gate control unit 13 is connected to the comparison processing module group 30 , the second input terminal of the second logic gate control unit 13 is used to input the third control signal, and the output terminal of the second logic gate control unit 13 is connected with the control terminal of the transmission switch unit 14 .
  • the comparison processing module 30 is used to output the reset control signal to the first input terminal of the second logic gate control unit 13, and the second logic gate control unit 13 is used to output the reset control signal to the first input terminal of the third control signal.
  • a fourth control signal is output to the control terminal of the transmission switch unit 14 .
  • the photoelectric conversion unit 11 is used to convert the received optical signal into a second electrical signal; the transmission switch unit 14 is used to transmit the second electrical signal to the second electrical signal under the control of the fourth control signal.
  • An energy storage unit 12 is used to store electrical energy and convert the second electrical signal into the first electrical signal.
  • the first voltage end can make the other end of the photoelectric conversion unit 11 in a stable voltage state of a first target voltage value (the first target voltage value can be zero or non-zero), such as the photoelectric conversion unit 11
  • a photodiode may be included, and the first target voltage value is sufficient to make the photodiode meet the working state of photoelectric conversion; optionally, the first voltage terminal may be a ground terminal or a constant voltage terminal with a non-zero voltage value.
  • the second voltage end can make the other end of the energy storage unit 12 be in a stable state of a second target voltage value (the second target voltage value can be zero or non-zero), such as the energy storage unit 12 A capacitor may be included, and the second target voltage value only needs to be such that the capacitor can store energy; optionally, the second voltage terminal may be a ground terminal or a constant voltage terminal with a non-zero voltage value.
  • the first voltage terminal and the second voltage terminal may be the same or different.
  • the second logic gate control unit 13 may include a combination of one or more logic gates, so that the second logic gate control unit 13 can realize that when the voltage of the reset control signal is the first voltage value or the In the case where the voltage of the third control signal is the first voltage value, the fourth control signal whose voltage is the first voltage value may be output, and the embodiments of the present application are not limited thereto.
  • the logic gate can be a second logic OR gate
  • the first input terminal of the second logic OR gate is connected to the comparison processing module 30 connected
  • the second input end of the second logic OR gate is used to input the third control signal
  • the output end of the second logic OR gate is connected to the control end of the transmission switch unit 14, so that the first
  • the two logic gate control unit 13 can realize the fourth control that the output voltage is the first voltage value when the voltage of the reset control signal is the first voltage value or the voltage of the third control signal is the first voltage value. signal, and helps to reduce the complexity of structural design.
  • the third control signal may be a predetermined control signal; if the voltage of the third control signal during the exposure process is a second voltage value, the second voltage value may be called a low level.
  • the voltage of the third control signal may be at a high level for a period of time during the signal reading (Readout) process after the exposure process. For example, in the Readout process, the time when the voltage of the third control signal is at a high level may be delayed from the time when the voltage of the first control signal is at a high level, so that the energy storage unit is first reset during the Readout process, to eliminate noise interference.
  • the comparator 31 outputs a high-level signal (i.e. reset The voltage of the control signal is the first voltage value) to the first logic gate control unit 21 and the second logic gate control unit 13, and now the first logic gate control unit 21 also outputs a high level signal (ie the second control signal) to The control end of the reset switch unit 22 is used to control the transmission switch unit 14 to be in a conducting state, thereby resetting the photoelectric conversion processing module 10; and the second logic gate control unit 13 also outputs a high level signal ( That is, the fourth control signal) is set to the transmission switch unit 14 to control the transmission switch unit 14 to be in a conducting state, so that the photoelectric conversion unit 11 can transmit the second electrical signal obtained by photoelectric conversion to the energy storage unit 12 to store electric energy , to convert the second electrical signal into the first electrical signal.
  • a high-level signal i.e. reset The voltage of the control signal is the first voltage value
  • the first logic gate control unit 21 also outputs a high level signal (ie the second control signal) to The
  • the first voltage value of the first electrical signal is greater than or equal to the preset voltage value, if the first control signal and the third control signal have a time period in which the voltage is at a high level, then it can Perform the Readout operation, that is, first reset the energy storage unit 12 through the first control signal to eliminate noise interference, and then control the transmission switch unit 14 to be in a conduction state through the third control signal, so that the photoelectric conversion unit 11 can convert the photoelectric
  • the converted second electrical signal is transmitted to the energy storage unit 12 to store electrical energy, so as to convert the second electrical signal into the first electrical signal, and then read the photoelectric conversion processing module 10 during the exposure process.
  • the electrical signal obtained when the photoelectric conversion and the full well capacity is not reached.
  • the pixel circuit further includes: a source follower 60; wherein, the source follower 60 is connected to a power supply or a power supply line (such as a VDD line), and the photoelectric conversion processing module 10 communicates with The comparison processing module 30 is connected.
  • a source follower 60 is connected to a power supply or a power supply line (such as a VDD line), and the photoelectric conversion processing module 10 communicates with The comparison processing module 30 is connected.
  • the reset switch unit 22 can include a reset transistor RST1
  • the transmission switch unit 14 can include a transmission transistor TX1; the anode of the photodiode PD is grounded, and the cathode of the photodiode PD is connected to the first end of the parasitic capacitor FD through the transmission transistor TX1.
  • the first end of the capacitor FD is also connected to the power supply line VDD through the reset transistor RST1, and the second end of the parasitic capacitor FD is grounded.
  • the photodiode PD is used to convert photons into electrons e-
  • the parasitic capacitor FD is used to convert electrons e- into voltage signals.
  • the first end of the parasitic capacitance FD is also connected to the negative input terminal of the comparator 31 through the source follower SF, and the source follower SF is also connected to the power supply line VDD; the positive input terminal of the comparator 31 is used for the input voltage to be the threshold voltage Vth
  • the signal that is, the preset voltage signal, the threshold voltage Vth depends on the voltage value of the parasitic capacitance FD when reaching the full well capacity
  • the output terminal of the comparator 31 is connected to the counter 32 (such as a D flip-flop), the first logic OR gate An input end of S1 and an input end of the second logical OR gate S2; wherein, fclk is the clock signal of the counter 32, and the output end Do of the counter 32 can be connected to the register, and the recorded output reset control signal is read by the register
  • the number of times that is, the number of times that the photoelectric conversion control module 20 reaches the full well capacity.
  • the other input terminal of the first logic OR gate S1 is used to input the reset (Reset, RST) signal (ie the first control signal), and the output terminal of the first logic OR gate S1 is connected to the gate of the reset transistor RST1;
  • the other input terminal of the OR gate S2 is used to input a transmission (TX) signal (ie, the third control signal), and the output terminal of the second logical OR gate S2 is connected to the gate of the transmission transistor TX1 .
  • a column output selection transistor SEL1 can also be provided between the negative input terminal of the comparator 31 and the source follower SF; wherein, the selection (Select, SEL) signal can be directly input to the gate of the column output selection transistor SEL1
  • the selection (Select, SEL) signal can be directly input to the gate of the column output selection transistor SEL1
  • the column output selection transistor SEL1 when the SEL signal is a low-level signal, the column output selection transistor SEL1 is turned on, and when the SEL signal is a high-level signal, the column output selection transistor SEL1 is turned off;
  • Gate S3 is input to the gate of the column output selection transistor SEL1, if the SEL signal is a low level signal, a high level signal is input to the gate of the column output selection transistor SEL1 through the logic NOT gate S3, and the column output
  • the selection transistor SEL1 is turned on, and when the SEL signal is a high-level signal, a low-level signal is input to the gate of the column output
  • the SEL signal, the RST signal, and the TX signal may be preset control signals, and their timing relationship diagram may refer to FIG. 7 .
  • reset the initial state that is, the RST signal and the TX signal are high level, and the outputs of the first logic OR gate S1 and the second logic OR gate S2 are also high level, and at this time, the reset tube RST1 1.
  • the transmission tube TX1 is turned on to reset the photodiode PD and the parasitic capacitance FD.
  • the SEL signal, the RST signal, and the TX signal are all at low level, that is, the output of the logic NOT gate S3 is at a high level, and at this moment, the column output selection transistor SEL1 is turned on; when the photodiode PD During exposure, the photodiode PD converts the received light signal into electron e-, and collects electron e-; The voltage value) is less than the threshold voltage Vth, then the comparator 31 outputs a high level to the counter 32 to count and add 1, and outputs a high level signal to the first logic OR gate S1 and the second logic OR gate S2 to perform The photodiode PD and the parasitic capacitance FD are reset, so that the photodiode PD and the parasitic capacitance FD continue to collect electrons e- again; of course, during the exposure process, it can be counted one or more times to reach the full well capacity, and the steps are the same as above, not here Let me
  • electrons e- that reach an integer multiple of the full well capacity during the exposure process can be collected. Specifically, it can be obtained by reading the value Do of the register, that is, the number of electrons that reaches an integer multiple of the full well capacity during the exposure process is: Do*FWC( e-); where, FWC(e-) represents the number of electrons collected when a full well capacity is reached.
  • the pixel circuit further includes: a first switch module 40 and an analog-to-digital conversion module 50; wherein, the photoelectric conversion processing module 10 passes through the first switch module 40 They are respectively connected with the comparison processing module 30 and the analog-to-digital conversion module 50 .
  • the analog-to-digital conversion module 50 is used for converting analog electrical signals into digital electrical signals.
  • the photoelectric conversion processing module 10 When the first switch module 40 is in the first state, the photoelectric conversion processing module 10 is connected to the analog-to-digital conversion module 50 , and the photoelectric conversion processing module 10 is connected to the comparison The processing module 30 is disconnected; when the first switch module 40 is in the second state, the conduction between the photoelectric conversion processing module 10 and the comparison processing module 30 is conducted, and the photoelectric conversion The processing module 10 is disconnected from the analog-to-digital conversion module 50 .
  • the electron e- which reaches an integral multiple of the full well capacity during the exposure process can be collected by the comparison processing module 30; and, through the first switch module 40
  • electrons e- that do not reach the full well capacity of the photoelectric conversion processing module 10 during the exposure process can be collected to ensure the integrity of the collected electrons e- obtained by photoelectric conversion, so as to ensure the image sensor with the pixel circuit With a wide dynamic range (Wide Dynamic Range, WDR), to reduce image distortion, so as to ensure image quality.
  • WDR Wide Dynamic Range
  • the first switch module 40 includes: a first switch unit 41 and a second switch unit 42; wherein, the photoelectric conversion processing module 10 communicates with the comparison processing module through the first switch unit 41
  • the photoelectric conversion processing module 10 is connected to the analog-to-digital conversion module 50 through the second switch unit 42 .
  • Both the control terminal of the first switch unit 41 and the control terminal of the second switch unit 42 are used to input a fifth control signal; wherein, when the voltage of the fifth control signal is the first voltage value, The first switch module 40 is in the first state; when the voltage of the third control signal is a second voltage value, the first switch module 40 is in the second state.
  • the first switch unit 41 includes a first switch and a logic NOT gate, and the fifth control signal is input to the control terminal of the first switch through a logic NOT gate;
  • the second switch unit 42 includes a second switch, and the fifth control signal The signal is directly input to the control terminal of the second switch.
  • the fifth control signal may be a preset control signal, and during the exposure process, the voltage of the fifth control signal is at a low level.
  • the fifth control signal has a period of high voltage, so that after the exposure process, the electrons e- .
  • the second switch unit 42 includes a first switch and a logic NOT gate, and the fifth control signal is input to the control terminal of the first switch through a logic NOT gate; the first switch unit 41 includes a second switch, and the fifth control signal The signal is directly input to the control terminal of the second switch.
  • the fifth control signal may be a preset control signal, and the voltage of the fifth control signal is at a high level during the exposure process.
  • the fifth control signal has a time period in which the voltage is at a low level, so that after the exposure process, electrons e- .
  • the first switch unit 41 and the second switch unit 42 can also have other structures, so that when the first switch unit 41 is turned on, the second switch unit 42 is turned off, or when the second switch unit When the unit 42 is turned on, the first switch unit 41 is turned off.
  • the first switch unit 41 includes a first switch
  • the second switch unit 42 includes a second switch
  • the control terminals of the first switch and the second switch both input the SEL signal; wherein, when the SEL signal is low , the first switch is turned on, and the second switch is turned off.
  • the SEL signal is at a high level, the first switch is turned off, and the second switch is turned on.
  • the embodiment of the present application is not limited thereto.
  • FIG. 6 a schematic diagram of another pixel circuit is shown. The part of the pixel circuit with the same structure as the pixel circuit in FIG. 4 will not be repeated here. The difference between the pixel circuit in FIG. 6 and the pixel circuit in FIG. 4 will be described below:
  • the first terminal of the parasitic capacitance FD is connected to the negative input terminal of the comparator 31 through the source follower SF and the first column output selection transistor SEL1 in turn, and the first terminal of the parasitic capacitance FD is also sequentially connected through the source follower SF and the second column
  • the output selection tube SEL2 is connected to the digital-to-analog conversion module ADC.
  • the SEL signal can be input to the gate of the first column output selection transistor SEL1 through the logic NOT gate S3, and the SEL signal can be input to the gate of the second column output selection transistor SEL2.
  • a digital-to-analog conversion module (Analog to Digital Converter, ADC) is used to convert an analog signal (such as a voltage signal) into a digital signal (such as a 10-bit digital signal).
  • Column output line (Column output line) is used to connect the digital-to-analog conversion module ADC and multiple pixel circuits, such as multiple pixel circuits can be arranged in a matrix, and multiple pixel circuits on each column can share a column output line and digital-analog Conversion module ADC.
  • the reset of the initial state is carried out in the time period (1), that is, the RST signal and the TX signal are at a high level, and the outputs of the first logic OR gate S1 and the second logic OR gate S2 are also at a high level.
  • the reset tube RST1 and the transmission tube TX1 are turned on to reset the photodiode PD and the parasitic capacitor FD.
  • the SEL signal, the RST signal, and the TX signal are all at low level, that is, the output of the logic NOT gate S3 is at a high level.
  • the first column output selection transistor SEL1 is turned on, and the second The column output selection tube SEL2 is closed; when the photodiode PD is exposed, the photodiode PD converts the received light signal into electron e-, and collects electron e-; when the collected electron e- reaches the full well capacity, the parasitic capacitance FD
  • the voltage value (the voltage value on the negative input terminal of the comparator 31) is less than the threshold voltage Vth, then the comparator 31 outputs a high level to count and add 1 to the counter 32, and to the first logic OR gate S1 and the second logic OR
  • the gate S2 outputs a high-level signal to reset the photodiode PD and the parasitic capacitance FD, so that the photodiode PD and the parasitic capacitance
  • the Readout process is carried out in the period (3), and the SEL signal is at a high level, then the second column output selection transistor SEL2 is turned on, and the first column output selection transistor SEL1 is closed; the RST signal is at a high level (that is, the first logic OR gate S1 output is high level), at this time the TX signal is at low level (that is, the output of the second logic OR gate S2 is low level), at this time the reset tube RST1 is turned on, the transmission tube TX1 is turned off, and the FD is reset to clear noise (noise); then the RST signal is at a low level (that is, the output of the first logic OR gate S1 is low), and at this time the TX signal is at a high level (that is, the output of the second logic or gate S2 is high), At this time, the reset transistor RST1 is turned off, and the transmission transistor TX1 is turned on to neutralize the electron e- collected in the photodiode PD and the positive charge in the parasitic capacit
  • the above-mentioned pixel circuit in the embodiment of the present application can ensure the integrity of the collected electrons e- obtained through photoelectric conversion, so as to avoid overflow after the collected electrons e- reach the full capacity of the well, that is, the problem of overexposure, and pass
  • the photoelectric conversion processing module resets and collects after reaching the full well capacity, which is conducive to improving the dynamic range of the CIS and avoiding image distortion, thereby ensuring the image quality.
  • An embodiment of the present application further provides an image sensor, which includes the above-mentioned pixel circuit, and can achieve the same technical effect as the above-mentioned pixel circuit. To avoid repetition, details are not repeated here.
  • An embodiment of the present application further provides an electronic device, which includes the above-mentioned image sensor, and can achieve the same technical effect as the above-mentioned image sensor. To avoid repetition, details are not repeated here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

本申请公开了一种像素电路、图像传感器及电子设备，该像素电路包括：光电转换处理模组（10）、复位控制模组（20）和比较处理模组（30）；其中，所述光电转换处理模组（10）和所述复位控制模组（20）均与所述比较处理模组（30）连接，所述复位控制模组（20）与所述光电转换处理模组（10）连接；所述光电转换处理模组（10）用于对接收到的光信号进行光电转换，得到第一电信号，将所述第一电信号传输至所述比较处理模组（30）；所述比较处理模组（30）在所述第一电信号对应的第一电压值小于预设电压值的情况下，输出复位控制信号至所述复位控制模组（20），并记录输出所述复位控制信号的次数；所述复位控制模组（20）用于根据所述复位控制信号对所述光电转换处理模组（10）进行复位。

Description

像素电路、图像传感器及电子设备
相关申请的交叉引用
本申请主张在2021年08月30日在中国提交的中国专利申请No.202111002172.9的优先权，其全部内容通过引用包含于此。
技术领域
本申请属于电学技术领域，尤其涉及一种像素电路、图像传感器及电子设备。
背景技术
随着电子设备的快速发展，拍照功能逐渐成为手机等电子设备的必备功能之一。互补金属氧化物半导体(Complementary Metal-Oxide-Semiconductor，CMOS)图像传感器(CMOS image sensor，CIS)是电子设备中实现成像的重要部件。如果电子设备中的CMOS图像传感器的动态范围不足，则电子设备在明亮强光场景下进行拍照时，可能出现过曝的情况，导致图片失真，最终影响成像。
发明内容
为了解决上述技术问题，本申请是这样实现的：
第一方面，本申请实施例提供了一种像素电路，包括：光电转换处理模组、复位控制模组和比较处理模组；其中，
所述光电转换处理模组和所述复位控制模组均与所述比较处理模组连接，所述复位控制模组与所述光电转换处理模组连接；
所述光电转换处理模组用于对接收到的光信号进行光电转换，得到第一电信号，将所述第一电信号传输至所述比较处理模组；
所述比较处理模组在所述第一电信号对应的第一电压值小于预设电压值的情况下，输出复位控制信号至所述复位控制模组，并记录输出所述复位控 制信号的次数；
所述复位控制模组用于根据所述复位控制信号对所述光电转换处理模组进行复位。
第二方面，本申请实施例还提供了一种图像传感器，包括如上所述的像素电路。
第三方面，本申请实施例还提供了一种电子设备，包括如上所述的图像传感器。
这样，本申请的上述方案中，在像素电路中设置比较处理模组，可以通过比较处理模组在光电转换处理模组进行光电转换得到的第一电信号的第一电压值小于预设电压值的情况下，通过输出复位控制信号至复位控制模组，以控制复位控制模组对该光电转换处理模组进行复位，以使得该光电转换处理模组可以继续进行光电转换，并记录输出所述复位控制信号的次数。这样，在光电转换处理模组接收的光信号过强，导致光电转换处理模组进行光电转换时电信号溢出的情况下，可以根据所记录的输出所述复位控制信号的次数，收集到溢出的电信号，以避免图像失真，解决了目前由于CMOS图像传感器的动态范围不足可能导致图片失真的问题，从而能够保证成像效果。
附图说明
图1表示本申请实施例的像素电路的结构框图之一；
图2表示本申请实施例的像素电路的结构框图之二；
图3表示本申请实施例的像素电路的结构框图之三；
图4表示本申请实施例的像素电路的示意图之一；
图5表示本申请实施例的像素电路的结构框图之四；
图6表示本申请实施例的像素电路的示意图之二；
图7表示本申请实施例的控制信号和像素电路中部分器件输出的时序图。
具体实施方式
下面将参照附图更详细地描述本申请的示例性实施例。虽然附图中显示了本申请的示例性实施例，然而应当理解，可以以各种形式实现本申请而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本申请，并且能够将本申请的范围完整的传达给本领域的技术人员。
如图1所示，本申请实施例提供像素电路，包括：光电转换处理模组10、复位控制模组20和比较处理模组30。
其中，所述光电转换处理模组10和所述复位控制模组20均与所述比较处理模组30连接，所述复位控制模组20与所述光电转换处理模组10连接。
所述光电转换处理模组10用于对接收到的光信号进行光电转换，得到第一电信号，将所述第一电信号传输至所述比较处理模组30；所述比较处理模组30在所述第一电信号对应的第一电压值小于预设电压值的情况下，输出复位控制信号至所述复位控制模组20，记录输出所述复位控制信号的次数；所述复位控制模组20用于根据所述复位控制信号对所述光电转换处理模组10进行复位。
可选地，所述光电转换处理模组10可以用于对接收到光信号进行光电转换，即将接收到的光信号转换为电信号，以及对转换得到的电信号进行储能处理，得到对应的第一电信号，将所述第一电信号传输至所述比较处理模组30。
其中，所述预设电压值可以由该光电转换处理模组10在进行光电转换时，达到满井容量(即像素的势井所能容纳的最大电子数)时光电转换处理模组10所输出的电压值确定。可选地，该预设电压值可以略大于达到满井容量时光电转换处理模组10所输出的电压值。例如：该光电转换处理模组10在复位状态时(光电转换处理模组10未进行光电转换时的初始状态)的电压值为2.80V，该光电转换处理模组10在进行光电转换时达到满井容量时的电压值为1.80V，该预设电压值可以在1.80V～1.82V的开区间范围内(如预设电压值可以设置为1.81V)，当然本申请实施例不以此为限。
该像素电路的工作过程可以是：初始状态下，可以先通过复位控制模组 20对所述光电转换处理模组10进行复位，以保证收集光信号的准确性。在对光电转换处理模组10进行复位之后，使得光电转换处理模组10曝光，从而该光电转换处理模组10可以对接收到的光信号进行光电转换，得到第一电信号，并将该第一电信号传输至所述比较处理模组30。
由于预设电压值根据该光电转换处理模组10在进行光电转换时，达到满井容量时所输出的电压值确定，如果第一信号对应的第一电压值小于预设电压值，则表示该光电转换处理模组10在进行光电转换时已达到满井容量；如果第一信号对应的第一电压值大于或等于预设电压值，则表示该光电转换处理模组10在进行光电转换时未达到满井容量。
比较处理模组30可以在该第一电信号对应的电压值小于预设电压值的情况下，输出复位控制信号至复位控制模组20，使得该复位控制模组20对该光电转换处理模组10进行复位，则光电转换处理模组可以继续进行光电转换处理，并记录输出所述复位控制信号的次数(即统计光电转换处理模组10在进行光电转换时达到满井容量的次数)；比较处理模组30在该第一电信号对应的电压值大于或等于预设电压值的情况下，不会输出用于控制复位控制模组20对该光电转换处理模组10进行复位的复位控制信号，也不进行累积计数，直至曝光过程结束。
可选地，在曝光过程中记录输出所述复位控制信号的次数可以包括：在一次曝光过程中，初始状态下记录初始计数值为0，在比较处理模组30检测到一次该第一电信号对应的电压值小于预设电压值(即达到满井容量)时，记录一次计数值加1，直至曝光过程结束得到累积的计数值；例如：在曝光过程中比较处理模组30检测到4次该第一电信号对应的电压值小于预设电压值，则得到累积的计数值为4，进而可以根据该累积的计数值，确定光电转换过程中所溢出的电信号。在本次曝光过程结束时，将该计数值复位为0，以继续下一次曝光过程统计达到满井容量的次数。
该实施例中，在像素电路中设置比较处理模组30，可以通过比较处理模组30在光电转换处理模组10进行光电转换得到的第一电信号的第一电压值 小于预设电压值的情况下，通过输出复位控制信号至复位控制模组，以控制复位控制模组20对该光电转换处理模组10进行复位，以使得该光电转换处理模组10可以继续进行光电转换，，并记录输出所述复位控制信号的次数。这样，在光电转换处理模组10接收的光信号过强，导致光电转换处理模组10进行光电转换时电信号溢出的情况下，可以根据所记录的输出所述复位控制信号的次数，收集到溢出的电信号，以避免图像失真，解决了目前由于CMOS图像传感器的动态范围不足可能导致图片失真的问题，从而能够保证成像效果。
可选地，如图2所示，所述比较处理模组30包括：比较器(Comparer)31和计数器(Counter)32。其中，所述比较器31的第一输入端与所述光电转换处理模组10连接，所述比较器31的第二输入端用于输入预设电压信号，所述比较器31的输出端与所述复位控制模组20和所述计数器32连接；所述预设电压信号的电压值为所述预设电压值。
所述比较器31用于在所述第一电压值小于所述预设电压值的情况下，输出所述复位控制信号至所述复位控制模组20，以及输出计数信号至所述计数器32；所述计数器32根据所述计数信号记录所述次数加1。
可选地，所述预设电压信号可以由参考电路生成，例如：该参考电路可以是预设的用于生成该预设电压信号的参考电路(如分压电路、恒压电源电路等)，该参考电路的预设电压信号输出端(如分压电路的分压输出端、恒压电源电路的电压输出端等)与该比较器31的第二输入端连接，从而可以通过该参考电路直接向该比较器31的第二输入端输出预设电压信号；当然本申请实施例还可以采用除此之外的其他方式来提供比较器31的第二输入端的预设电压信号，这里不以此为限。
该实施例中，通过比较器31在光电转换处理模组10进行光电转换得到的第一电信号的第一电压值小于预设电压值的情况下，输出计数信号至所述计数器32，并通过所述计数器32记录所述次数加1，即统计光电转换处理模组10在进行光电转换时达到满井容量的次数；以及输出复位控制信号至复位 控制模组20，并通过控制复位控制模组20对该光电转换处理模组10进行复位，以使得该光电转换处理模组10在进行光电转换时达到满井容量后可以继续进行下一次的光电转换处理。这样，在光电转换处理模组10接收的光信号过强，导致光电转换处理模组10进行光电转换时电信号溢出的情况下，可以根据所述计数器所记录的输出所述复位控制信号的次数，收集到溢出的电信号，以避免图像失真，解决了目前由于CMOS图像传感器的动态范围不足可能导致图片失真的问题，从而能够保证成像效果。
可选地，所述复位控制模组20包括：第一逻辑门控制单元21和复位开关单元22；其中，所述第一逻辑门控制单元21的第一输入端与所述比较处理模组30连接，所述第一逻辑门控制单元21的第二输入端用于输入第一控制信号，所述第一逻辑门控制单元21的输出端与所述复位开关单元22的控制端连接。
所述第一逻辑门控制单元21用于在所述复位控制信号的电压为第一电压值或所述第一控制信号的电压为第一电压值的情况下，输出第二控制信号至所述复位开关单元的控制端；所述复位开关单元22用于在所述第二控制信号的控制下对所述光电转换处理模组10进行复位。
可选地，该第一逻辑门控制单元21可以包括一个或多个逻辑门的组合，以使得该第一逻辑门控制单元21可以实现在所述复位控制信号的电压为第一电压值或所述第一控制信号的电压为第一电压值的情况下，输出电压为第一电压值的第二控制信号即可，本申请实施例不以此为限。
例如：该第一逻辑门控制单元21包括一个逻辑门的情况下，该逻辑门可以是第一逻辑或门，所述第一逻辑或门的第一输入端与所述比较处理模组30连接，所述第一逻辑或门的第二输入端用于输入第一控制信号，所述第一逻辑或门的输出端与所述复位开关单元22的控制端连接，从而可以保证在所述复位控制信号的电压为第一电压值或所述第一控制信号的电压为第一电压值的情况下，输出电压为第一电压值的第二控制信号，且有利于降低结构设计的复杂度。
可选地，第一电压值可以是满足预设电压范围的值，如该第一电压值是满足复位开关单元22导通，以对光电转换处理模组10进行复位的电压值，该第一电压值也可以称为高电平。
可选地，该第一控制信号可以是预先给定的控制信号；如该第一控制信号在曝光过程中的电压为第二电压值，该第二电压值可以称为低电平。另外，该第一控制信号在曝光过程之后的信号读取(Readout)过程中可以存在电压为高电平的一段时间，以在信号读取时可以对光电转换处理模组10进行复位，消除干扰，从而保证信号读取的精准性。
例如：所述比较器31的第一输入端为负极输入端，比较器31的第二输入端为正极输入端；在曝光过程中，所述比较器31在光电转换处理模组10进行光电转换得到的第一电信号的第一电压值小于预设电压值的情况下，输出高电平信号(即复位控制信号的电压为第一电压值)给第一逻辑门控制单元21，此时第一逻辑门控制单元21也输出高电平信号(即第二控制信号)至所述复位开关单元22的控制端，以控制所述复位开关单元22处于导通状态，从而对该光电转换处理模组10进行复位。或者在曝光过程之后，即曝光过程结束，第一电信号的第一电压值大于或等于预设电压值，如果第一控制信号存在电压为高电平的时间段，则可以执行Readout操作，即读取所述光电转换处理模组10在曝光过程中，进行光电转换且未达到满井容量时所得到的电信号。
可选地，如图3所示，所述光电转换处理模组10包括：光电转换单元11、储能单元12、第二逻辑门控制单元13和传输开关单元14。
其中，所述光电转换单元11的一端与所述传输开关单元14的第一端连接，所述光电转换单元11的另一端与第一电压端连接；所述储能单元12的一端分别与所述复位开关单元22和所述传输开关单元14连接，所述储能单元12的另一端与第二电压端连接；所述第二逻辑门控制单元13的第一输入端与所述比较处理模组30连接，所述第二逻辑门控制单元13的第二输入端用于输入第三控制信号，所述第二逻辑门控制单元13的输出端与所述传输开 关单元14的控制端连接。
所述比较处理模组30用于输出所述复位控制信号至所述第二逻辑门控制单元13的第一输入端，所述第二逻辑门控制单元13用于在所述第三控制信号的电压为第一电压值或所述复位控制信号的电压为第一电压值的情况下，输出第四控制信号至所述传输开关单元14的控制端。
所述光电转换单元11用于将接收到的光信号转换为第二电信号；所述传输开关单元14用于在所述第四控制信号的控制下将所述第二电信号传输至所述储能单元12；所述储能单元12用于储存电能，将所述第二电信号转换为所述第一电信号。
可选地，该第一电压端可以使得该光电转换单元11的另一端处于第一目标电压值(该第一目标电压值可以是零或非零)的稳压状态，如该光电转换单元11可以包括光电二极管，该第一目标电压值以使得该光电二极管满足进行光电转换的工作状态即可；可选地，该第一电压端可以是接地端或者非零电压值的恒定电压端等。
可选地，该第二电压端可以使得该储能单元12的另一端处于第二目标电压值(该第二目标电压值可以是零或非零)的稳压状态，如该储能单元12可以包括电容，该第二目标电压值以使得该电容能够实现储能即可；可选地，该第二电压端可以是接地端或者非零电压值的恒定电压端等。
可选地，所述第一电压端和所述第二电压端可以相同或不同。
可选地，该第二逻辑门控制单元13可以包括一个或多个逻辑门的组合，以使得该第二逻辑门控制单元13可以实现在所述复位控制信号的电压为第一电压值或所述第三控制信号的电压为第一电压值的情况下，输出电压为第一电压值的第四控制信号即可，本申请实施例不以此为限。
例如：所述第二逻辑门控制单元13包括一个逻辑门的情况下，该逻辑门可以是第二逻辑或门，所述第二逻辑或门的第一输入端与所述比较处理模组30连接，所述第二逻辑或门的第二输入端用于输入所述第三控制信号，所述第二逻辑或门的输出端与所述传输开关单元14的控制端连接，以使得该第二 逻辑门控制单元13可以实现在所述复位控制信号的电压为第一电压值或所述第三控制信号的电压为第一电压值的情况下，输出电压为第一电压值的第四控制信号，且有利于降低结构设计的复杂度。
可选地，该第三控制信号可以是预先给定的控制信号；如该第三控制信号在曝光过程中的电压为第二电压值，该第二电压值可以称为低电平。另外，该第三控制信号在曝光过程之后的信号读取(Readout)过程中可以存在电压为高电平的一段时间。如在Readout过程中，该第三控制信号的电压为高电平的时间可以延迟于该第一控制信号的电压为高电平的时间，以使得在Readout过程中先对储能单元进行复位，以消除噪声干扰。
例如：在曝光过程中，所述比较器31在光电转换处理模组10进行光电转换得到的第一电信号的第一电压值小于预设电压值的情况下，输出高电平信号(即复位控制信号的电压为第一电压值)给第一逻辑门控制单元21和第二逻辑门控制单元13，此时第一逻辑门控制单元21也输出高电平信号(即第二控制信号)至所述复位开关单元22的控制端，以控制所述传输开关单元14处于导通状态，从而对该光电转换处理模组10进行复位；以及第二逻辑门控制单元13也输出高电平信号(即第四控制信号)值所述传输开关单元14，以控制所述传输开关单元14处于导通状态，从而光电转换单元11可以将光电转换得到的第二电信号传输至储能单元12储存电能，以将所述第二电信号转换为所述第一电信号。或者在曝光过程之后，即曝光过程结束，第一电信号的第一电压值大于或等于预设电压值，如果第一控制信号和第三控制信号存在电压为高电平的时间段，则可以执行Readout操作，即先通过第一控制信号对储能单元12进行复位，以消除噪声干扰，再通过第三控制信号控制所述传输开关单元14处于导通状态，从而光电转换单元11可以将光电转换得到的第二电信号传输至储能单元12储存电能，以将所述第二电信号转换为所述第一电信号，进而读取所述光电转换处理模组10在曝光过程中，进行光电转换且未达到满井容量时所得到的电信号。
可选地，所述像素电路还包括：源跟随器60；其中，源跟随器60连接 供电电源或供电线(如VDD线)，所述光电转换处理模组10通过所述源跟随器60与所述比较处理模组30连接。
参见图4，给出了一种像素电路的示意图。如上述复位开关单元22可以包括复位管RST1，传输开关单元14可以包括传输管TX1；光电二极管PD的阳极接地，光电二极管PD的阴极通过传输管TX1与寄生电容FD的第一端连接，该寄生电容FD的第一端还通过复位管RST1与供电线VDD连接，该寄生电容FD的第二端接地。其中，光电二极管PD用于将光子转化为电子e-，寄生电容FD用于将电子e-转换为电压信号。
该寄生电容FD的第一端还通过源跟随器SF与比较器31的负极输入端连接，该源跟随器SF还连接供电线VDD；比较器31的正极输入端用于输入电压为门限电压Vth的信号(即预设电压信号，该门限电压Vth取决于达到满井容量时寄生电容FD的电压值)，比较器31的输出端连接至计数器32(如D触发器)、第一逻辑或门S1的一个输入端以及第二逻辑或门S2的一个输入端；其中，fclk为计数器32的时钟信号，计数器32的输出端Do可以连接至寄存器，通过寄存器读取所记录的输出复位控制信号的次数，即光电转换控制模组20达到满井容量的次数。
第一逻辑或门S1的另一输入端用于输入复位(Reset，RST)信号(即第一控制信号)，第一逻辑或门S1的输出端连接至复位管RST1的栅极；第二逻辑或门S2的另一输入端用于输入传输(Transport，TX)信号(即第三控制信号)，第二逻辑或门S2的输出端连接至传输管TX1的栅极。
可选地，在比较器31的负极输入端与源跟随器SF之间还可以设置列输出选择管SEL1；其中，选择(Select，SEL)信号可以直接输入至该列输出选择管SEL1的栅极，如在该SEL信号为低电平信号时，该列输出选择管SEL1导通，在该SEL信号为高电平信号时，该列输出选择管SEL1关断；或者，SEL信号可以通过逻辑非门S3输入至该列输出选择管SEL1的栅极，如在该SEL信号为低电平信号时，通过逻辑非门S3输入高电平信号至该列输出选择管SEL1的栅极，该列输出选择管SEL1导通，在该SEL信号为高电平信号 时，通过逻辑非门S3输入低电平信号至该列输出选择管SEL1的栅极，该列输出选择管SEL1关断。
其中，SEL信号、RST信号、TX信号可以是预先设定的控制信号，其时序关系图可参见图7。在时间段(1)内进行初始状态的复位，即RST信号、TX信号为高电平，第一逻辑或门S1和第二逻辑或门S2的输出也为高电平，此时复位管RST1、传输管TX1打开，对光电二极管PD、寄生电容FD进行复位。
在时间段(2)内进行曝光过程，SEL信号、RST信号、TX信号均为低电平，即逻辑非门S3的输出为高电平，此时列输出选择管SEL1打开；当光电二极管PD曝光时，光电二极管PD将接收的光信号转换为电子e-，收集电子e-；当收集的电子e-达到满井容量时，即寄生电容FD的电压值(比较器31的负极输入端上的电压值)小于门限电压Vth，则比较器31输出一个高电平给计数器32进行计数加1，以及给第一逻辑或门S1和第二逻辑或门S2输出一个高电平信号，以进行光电二极管PD和寄生电容FD的复位，以使得光电二极管PD、寄生电容FD再继续重新收集电子e-；当然，在曝光过程中可以统计到一次或多次达到满井容量，步骤同上，这里不再赘述。
经过上述步骤可以收集到曝光过程中达到满井容量整数倍的电子e-，具体可以通过读取寄存器的数值Do得到，即曝光过程中达到满井容量整数倍的电子数为：Do*FWC(e-)；其中，FWC(e-)表示达到一次满井容量时所收集的电子数。
可选地，如图5所示，所述像素电路还包括：第一开关模组40和模数转换模组50；其中，所述光电转换处理模组10通过所述第一开关模组40分别与所述比较处理模组30和模数转换模组50连接。其中，该模数转换模组50用于将模拟电信号转换为数字电信号。
在所述第一开关模组40处于第一状态的情况下，所述光电转换处理模组10与所述模数转换模组50导通，且所述光电转换处理模组10与所述比较处理模组30断开；在所述第一开关模组40处于第二状态的情况下，所述光电 转换处理模组10与所述比较处理模组30之间导通，且所述光电转换处理模组10与所述模数转换模组50之间断开。
该实施例中，通过第一开关模组40处于第一状态时，可以通过比较处理模组30收集到曝光过程中达到满井容量整数倍的电子e-；以及，通过第一开关模组40处于第二状态时，可以收集到曝光过程中未达到光电转换处理模组10满井容量的电子e-，保证收集光电转换得到的电子e-的完整性，以保证具有该像素电路的图像传感器具有宽动态范围(Wide Dynamic Range，WDR)，以减少图像失真，从而保证图像画质。
可选地，所述第一开关模组40包括：第一开关单元41和第二开关单元42；其中，所述光电转换处理模组10通过所述第一开关单元41与所述比较处理模组30连接，所述光电转换处理模组10通过所述第二开关单元42与所述模数转换模组50连接。
所述第一开关单元41的控制端和所述第二开关单元42的控制端均用于输入第五控制信号；其中，在所述第五控制信号的电压为第一电压值的情况下，所述第一开关模组40处于所述第一状态；在所述第三控制信号的电压为第二电压值的情况下，所述第一开关模组40处于所述第二状态。
例如：该第一开关单元41包括第一开关和逻辑非门，该第五控制信号通过逻辑非门输入到该第一开关的控制端；第二开关单元42包括第二开关，该第五控制信号直接输入到该第二开关的控制端。其中，该第五控制信号可以是预先设定的控制信号，在曝光过程中，该第五控制信号的电压为低电平。另外，在曝光过程之后的Readout过程，该第五控制信号存在电压为高电平的时间段，以使得在曝光过程之后，能够收集到未达到光电转换处理模组10满井容量的电子e-。
或者，该第二开关单元42包括第一开关和逻辑非门，该第五控制信号通过逻辑非门输入到该第一开关的控制端；第一开关单元41包括第二开关，该第五控制信号直接输入到该第二开关的控制端。其中，该第五控制信号可以是预先设定的控制信号，在曝光过程中，该第五控制信号的电压为高电平。 另外，在曝光过程之后的Readout过程，该第五控制信号存在电压为低电平的时间段，以使得在曝光过程之后，能够收集到未达到光电转换处理模组10满井容量的电子e-。
当然，第一开关单元41和第二开关单元42还可以是除此之外的其他结构，以使得第一开关单元41导通时，该第二开关单元42断开，或者在该第二开关单元42导通时，该第一开关单元41断开。例如：该第一开关单元41包括第一开关，该第二开关单元42包括第二开关，且该第一开关和第二开关的控制端均输入SEL信号；其中，当SEL信号为低电平时，该第一开关导通，第二开关断开，当SEL信号为高电平时，该第一开关断开，第二开关导通等，本申请实施例不以此为限。
参见图6，给出了又一种像素电路的示意图。该像素电路中与上述图4中的像素电路中结构相同的部分这里不再赘述，以下针对图6中像素电路与图4中像素电路的不同之处进行说明：
寄生电容FD的第一端依次通过源跟随器SF、第一列输出选择管SEL1连接至比较器31的负极输入端，以及寄生电容FD的第一端还依次通过源跟随器SF、第二列输出选择管SEL2连接至数模转换模组ADC。SEL信号可以通过逻辑非门S3输入至第一列输出选择管SEL1的栅极，以及该SEL信号可以输入至第二列输出选择管SEL2的栅极。
其中，数模转换模组(Analog to Digital Converter，ADC)用于将模拟信号(如电压信号)转换为数字信号(如10bit的数字信号)。列输出线(Column output line)用于连接数模转换模组ADC和多个像素电路，如多个像素电路可以呈矩阵排列，每列上的多个像素电路可以共用一个列输出线和数模转换模组ADC。
如图7，在时间段(1)内进行初始状态的复位，即RST信号、TX信号为高电平，第一逻辑或门S1和第二逻辑或门S2的输出也为高电平，此时复位管RST1、传输管TX1打开，对光电二极管PD、寄生电容FD进行复位。
在时间段(2)内进行曝光过程，SEL信号、RST信号、TX信号均为低 电平，即逻辑非门S3的输出为高电平，此时第一列输出选择管SEL1打开、第二列输出选择管SEL2关闭；当光电二极管PD曝光时，光电二极管PD将接收的光信号转换为电子e-，收集电子e-；当收集的电子e-达到满井容量时，即寄生电容FD的电压值(比较器31的负极输入端上的电压值)小于门限电压Vth，则比较器31输出一个高电平给计数器32进行计数加1，以及给第一逻辑或门S1和第二逻辑或门S2输出一个高电平信号，以进行光电二极管PD和寄生电容FD的复位，以使得光电二极管PD、寄生电容FD再继续重新收集电子e-；当然，在曝光过程中可以统计到一次或多次达到满井容量，步骤同上，这里不再赘述。
在时间段(3)内进行Readout过程，SEL信号处于高电平，则第二列输出选择管SEL2打开，第一列输出选择管SEL1关闭；RST信号处于高电平(即第一逻辑或门S1输出为高电平)，此时TX信号处于低电平(即第二逻辑或门S2输出为低电平)，此时复位管RST1打开，传输管TX1关闭，对FD进行复位，以清除噪声(noise)；然后RST信号处于低电平(即第一逻辑或门S1输出为低电平)，此时TX信号处于高电平(即第二逻辑或门S2输出为高电平)，此时复位管RST1关闭，传输管TX1打开，将光电二极管PD中收集到的电子e-与寄生电容FD中的正电荷进行中和(如寄生电容FD在复位后的初始电压为VDD，由于寄生电容FD中的正电荷与电子e-中和，导致电压下降)，则收集到电压信号的电压值为：ΔV＝VDD-V(e-)。
经过上述步骤可以收集到曝光过程中达到满井容量的整数倍的电子e-，以及未达到满井容量的电子e-；其中，曝光过程中达到满井容量的整数倍的电子数可以通过读取寄存器的数值Do得到，即曝光过程中达到满井容量的整数倍的电子数为：Do*FWC(e-)；其中，FWC(e-)表示达到一次满井容量时所收集的电子数；则最终收集到的电子数为：Do*FWC(e-)+N(e-)，其中，N(e-)表示收集到曝光过程中未达到满井容量的电子数。
这样，通过本申请实施例的上述像素电路可以保证收集光电转换得到的电子e-的完整性，以避免在收集到的电子e-达到满井容量后溢出，即出现过 曝光的问题，并通过光电转换处理模组达到满井容量后的复位再收集，有利于提升CIS的动态范围，避免图像失真，从而保证图像的画质。
本申请实施例还提供一种图像传感器，包括如上所述的像素电路，且能达到与上述像素电路相同的技术效果，为避免重复，这里不再赘述。
本申请实施例还提供一种电子设备，包括如上所述的图像传感器，且能达到与上述图像传感器相同的技术效果，为避免重复，这里不再赘述。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
尽管已描述了本申请实施例的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请实施例范围的所有变更和修改。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者终端设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者终端设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者终端设备中还存在另外的相同要素。
以上所述的是本申请的优选实施方式，应当指出对于本技术领域的普通人员来说，在不脱离本申请所述的原理前提下还可以作出若干改进和润饰，这些改进和润饰也在本申请的保护范围内。

Claims (11)

  1. 一种像素电路，包括：光电转换处理模组、复位控制模组和比较处理模组；其中，
    所述光电转换处理模组和所述复位控制模组均与所述比较处理模组连接，所述复位控制模组与所述光电转换处理模组连接；
    所述光电转换处理模组用于对接收到的光信号进行光电转换，得到第一电信号，将所述第一电信号传输至所述比较处理模组；
    所述比较处理模组在所述第一电信号对应的第一电压值小于预设电压值的情况下，输出复位控制信号至所述复位控制模组，并记录输出所述复位控制信号的次数；
    所述复位控制模组用于根据所述复位控制信号对所述光电转换处理模组进行复位。
  2. 根据权利要求1所述的像素电路，其中，所述比较处理模组包括：比较器和计数器；其中，
    所述比较器的第一输入端与所述光电转换处理模组连接，所述比较器的第二输入端用于输入预设电压信号，所述比较器的输出端与所述复位控制模组和所述计数器连接；所述预设电压信号的电压值为所述预设电压值；
    所述比较器用于在所述第一电压值小于所述预设电压值的情况下，输出所述复位控制信号至所述复位控制模组，以及输出计数信号至所述计数器。
  3. 根据权利要求1所述的像素电路，其中，所述复位控制模组包括：第一逻辑门控制单元和复位开关单元；其中，
    所述第一逻辑门控制单元的第一输入端与所述比较处理模组连接，所述第一逻辑门控制单元的第二输入端用于输入第一控制信号，所述第一逻辑门控制单元的输出端与所述复位开关单元的控制端连接；
    所述第一逻辑门控制单元用于在所述复位控制信号的电压为第一电压值或所述第一控制信号的电压为第一电压值的情况下，输出第二控制信号至所述复位开关单元的控制端；
    所述复位开关单元用于在所述第二控制信号的控制下对所述光电转换处理模组进行复位。
  4. 根据权利要求3所述的像素电路，其中，所述第一逻辑门控制单元包括：第一逻辑或门；
    所述第一逻辑或门的第一输入端与所述比较处理模组连接，所述第一逻辑或门的第二输入端用于输入第一控制信号，所述第一逻辑或门的输出端与所述复位开关单元的控制端连接。
  5. 根据权利要求3或4所述的像素电路，其中，所述光电转换处理模组包括：光电转换单元、储能单元、第二逻辑门控制单元和传输开关单元；其中，
    所述光电转换单元的一端与所述传输开关单元的第一端连接，所述光电转换单元的另一端与第一电压端连接；
    所述储能单元的一端分别与所述复位开关单元和所述传输开关单元连接，所述储能单元的另一端与第二电压端连接；
    所述第二逻辑门控制单元的第一输入端与所述比较处理模组连接，所述第二逻辑门控制单元的第二输入端用于输入第三控制信号，所述第二逻辑门控制单元的输出端与所述传输开关单元的控制端连接；
    所述比较处理模组用于输出所述复位控制信号至所述第二逻辑门控制单元的第一输入端，所述第二逻辑门控制单元用于在所述第三控制信号的电压为第一电压值或所述复位控制信号的电压为第一电压值的情况下，输出第四控制信号至所述传输开关单元的控制端；
    所述光电转换单元用于将接收到的光信号转换为第二电信号；所述传输开关单元用于在所述第四控制信号的控制下将所述第二电信号传输至所述储能单元；所述储能单元用于储存电能，将所述第二电信号转换为所述第一电信号。
  6. 根据权利要求5所述的像素电路，其中，所述第二逻辑门控制单元包括：第二逻辑或门；
    所述第二逻辑或门的第一输入端与所述比较处理模组连接，所述第二逻辑或门的第二输入端用于输入所述第三控制信号，所述第二逻辑或门的输出端与所述传输开关单元的控制端连接。
  7. 根据权利要求1所述的像素电路，其中，所述像素电路还包括：第一开关模组和模数转换模组；其中，
    所述光电转换处理模组通过所述第一开关模组分别与所述比较处理模组和模数转换模组连接；
    在所述第一开关模组处于第一状态的情况下，所述光电转换处理模组与所述模数转换模组导通，且所述光电转换处理模组与所述比较处理模组断开；在所述第一开关模组处于第二状态的情况下，所述光电转换处理模组与所述比较处理模组之间导通，且所述光电转换处理模组与所述模数转换模组之间断开。
  8. 根据权利要求7所述的像素电路，其中，所述第一开关模组包括：第一开关单元和第二开关单元；其中，
    所述光电转换处理模组通过所述第一开关单元与所述比较处理模组连接，所述光电转换处理模组通过所述第二开关单元与所述模数转换模组连接；
    所述第一开关单元的控制端和所述第二开关单元的控制端均用于输入第三控制信号；其中，在所述第三控制信号的电压为第一电压值的情况下，所述第一开关模组处于所述第一状态；在所述第三控制信号的电压为第二电压值的情况下，所述第一开关模组处于所述第二状态。
  9. 根据权利要求7所述的像素电路，其中，所述像素电路还包括：源跟随器；其中，
    所述光电转换处理模组通过所述源跟随器与所述比较处理模组连接。
  10. 一种图像传感器，包括如权利要求1至9中任一项所述的像素电路。
  11. 一种电子设备，包括如权利要求10所述的图像传感器。
PCT/CN2022/115459 2021-08-30 2022-08-29 像素电路、图像传感器及电子设备 Ceased WO2023030239A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111002172.9A CN113709395B (zh) 2021-08-30 2021-08-30 像素电路、图像传感器及电子设备
CN202111002172.9 2021-08-30

Publications (1)

Publication Number Publication Date
WO2023030239A1 true WO2023030239A1 (zh) 2023-03-09

Family

ID=78656613

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/115459 Ceased WO2023030239A1 (zh) 2021-08-30 2022-08-29 像素电路、图像传感器及电子设备

Country Status (2)

Country Link
CN (1) CN113709395B (zh)
WO (1) WO2023030239A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119233115A (zh) * 2024-09-13 2024-12-31 天津大学 自适应复位的大动态范围像素结构、图像传感器及电子设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113709395B (zh) * 2021-08-30 2024-11-26 维沃移动通信有限公司 像素电路、图像传感器及电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107071313A (zh) * 2017-03-15 2017-08-18 华南理工大学 一种宽动态范围cmos图像传感器像素单元电路
CN107995446A (zh) * 2016-10-26 2018-05-04 中国科学院上海高等研究院 脉冲宽度调制像素曝光方法及像素结构
JP2019004225A (ja) * 2017-06-12 2019-01-10 日本放送協会 信号読み出し回路及び固体撮像素子
CN111033193A (zh) * 2017-08-17 2020-04-17 脸谱科技有限责任公司 检测光电传感器中的高强度光
CN112640440A (zh) * 2020-05-15 2021-04-09 深圳市大疆创新科技有限公司 一种成像方法、成像装置、可移动平台和电子设备
CN113709395A (zh) * 2021-08-30 2021-11-26 维沃移动通信有限公司 像素电路、图像传感器及电子设备

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5446282B2 (ja) * 2009-01-21 2014-03-19 ソニー株式会社 固体撮像素子およびカメラシステム
US8729451B2 (en) * 2011-08-30 2014-05-20 Omnivision Technologies, Inc. Multilevel reset voltage for multi-conversion gain image sensor
JP2016092661A (ja) * 2014-11-07 2016-05-23 ソニー株式会社 撮像素子および駆動方法、並びに電子機器
US10051221B2 (en) * 2014-12-25 2018-08-14 Sony Corporation Solid-state imaging device and electronic apparatus
CN106303310A (zh) * 2016-08-26 2017-01-04 上海奕瑞光电子科技有限公司 一种像素阵列及降低图像串扰的读出方法
JP6987603B2 (ja) * 2017-10-26 2022-01-05 ブリルニクス シンガポール プライベート リミテッド 固体撮像装置、固体撮像装置の駆動方法、および電子機器
CN109005329B (zh) * 2018-09-19 2020-08-11 广东工业大学 一种像素单元、图像传感器以及相机
KR20200075962A (ko) * 2018-12-18 2020-06-29 삼성전자주식회사 피드백 루프를 통해 픽셀들의 각각의 변환 이득들을 결정하는 이미지 센서
JP7228790B2 (ja) * 2019-02-05 2023-02-27 パナソニックＩｐマネジメント株式会社 充電制御装置及び充電制御方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107995446A (zh) * 2016-10-26 2018-05-04 中国科学院上海高等研究院 脉冲宽度调制像素曝光方法及像素结构
CN107071313A (zh) * 2017-03-15 2017-08-18 华南理工大学 一种宽动态范围cmos图像传感器像素单元电路
JP2019004225A (ja) * 2017-06-12 2019-01-10 日本放送協会 信号読み出し回路及び固体撮像素子
CN111033193A (zh) * 2017-08-17 2020-04-17 脸谱科技有限责任公司 检测光电传感器中的高强度光
CN112640440A (zh) * 2020-05-15 2021-04-09 深圳市大疆创新科技有限公司 一种成像方法、成像装置、可移动平台和电子设备
CN113709395A (zh) * 2021-08-30 2021-11-26 维沃移动通信有限公司 像素电路、图像传感器及电子设备

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119233115A (zh) * 2024-09-13 2024-12-31 天津大学 自适应复位的大动态范围像素结构、图像传感器及电子设备

Also Published As

Publication number Publication date
CN113709395A (zh) 2021-11-26
CN113709395B (zh) 2024-11-26

Similar Documents

Publication Publication Date Title
US6344877B1 (en) Image sensor with dummy pixel or dummy pixel array
US8767106B2 (en) Comparator, AD converter, solid-state imaging device, and camera system
US10237504B2 (en) Solid-state imaging device and camera system with columm parallel ADC
CN110351500B (zh) 一种兼容两种曝光模式的cmos图像传感器读出电路
US20200204751A1 (en) Image sensor readout method and architecture
KR100719370B1 (ko) 아날로그-디지털 변환기 및 이를 포함하는 씨모스 이미지센서, 그리고 씨모스 이미지 센서의 동작 방법
WO2013127450A1 (en) Self-reset asynchronous pulse frequency modulated droic with extended counting and having reduced quantization noise
WO2023030239A1 (zh) 像素电路、图像传感器及电子设备
TWI403094B (zh) 使用斜面傳輸閘極時脈的類比／數位轉換器
CN107659762A (zh) 一种图像传感器
CN110741629A (zh) 像素单元和图像传感器
WO2021138838A1 (zh) 一种图像读取电路、图像传感器以及终端设备
CN115086580B (zh) 一种像素级模数转换数字读出电路及红外探测器
CN112399113B (zh) 一种实现像素内相关双采样的高速全局曝光像素结构
CN112399099B (zh) 一种电荷域采样低噪声像素结构
CN108848327B (zh) 硅基混成cmos-apd图像传感器系统
CN118055338A (zh) 一种高满阱大动态图像传感器像素结构及其工作方法
CN105554421B (zh) 一种全局像元非线性补偿结构
CN115550581A (zh) 一种像素列读出电路及图像传感器
CN115209075A (zh) 一种像素单元电路、图像传感器及其时序控制方法
CN119653257B (zh) 像素电路、图像传感器、摄像头模组和电子设备
Ho et al. CMOS 3-T digital pixel sensor with in-pixel shared comparator
CN114567738A (zh) 一种应用于cmos图像传感器的两步式单斜模数转换器
CN111787249A (zh) 一种32通道电荷采集读出电路及其控制方法
Pain et al. A single-chip programmable digital CMOS imager with enhanced low-light detection capability

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22863375

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 16/08/2024)

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22863375

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 22863375

Country of ref document: EP

Kind code of ref document: A1