WO2023029635A1 - 芯片供电系统及方法、电子设备、计算机可读存储介质 - Google Patents

芯片供电系统及方法、电子设备、计算机可读存储介质 Download PDF

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WO2023029635A1
WO2023029635A1 PCT/CN2022/097431 CN2022097431W WO2023029635A1 WO 2023029635 A1 WO2023029635 A1 WO 2023029635A1 CN 2022097431 W CN2022097431 W CN 2022097431W WO 2023029635 A1 WO2023029635 A1 WO 2023029635A1
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power supply
chip
cores
partition
core
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PCT/CN2022/097431
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English (en)
French (fr)
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钟军威
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华为技术有限公司
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Publication of WO2023029635A1 publication Critical patent/WO2023029635A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

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  • the present application relates to the field of chip technology, and in particular to a chip power supply system and method, electronic equipment, and a computer-readable storage medium.
  • the application provides a chip power supply system and method, electronic equipment, and a computer-readable storage medium.
  • the present application provides a chip power supply system, including a multi-core chip, a plurality of power supply modules, and at least one power controller;
  • the multi-core chip includes N partitions, and each partition includes at least one core; and at least one of the N partitions
  • each partition includes at least two cores;
  • N power supply modules are set in one-to-one correspondence with N partitions;
  • the power supply controller is connected to at least one power supply module, and the power supply controller is used to control the connected power supply module to receive The received voltage is converted into the voltage required by the core; wherein, the output terminal of the power supply module is electrically connected to the core in the corresponding partition, and the power supply module is used to convert the received voltage to the core in the corresponding partition. voltage.
  • the number of power supply modules can be reduced and the packaging difficulty of the multi-core chip can be reduced;
  • the high-current power supply can be divided into multiple small-current power supplies, which reduces the core power supply current of the multi-core chip
  • the size reduces the current jump drop, and correspondingly reduces the dynamic drop range of the power supply; on the other hand, it can provide different voltages for the cores in different partitions, and can adjust the power supply for the cores in different partitions.
  • one side of the chip includes a plurality of power supply contacts, and the power supply contacts corresponding to the core in any partition form a power supply contact group; the output terminal of the power supply module and the corresponding The power supply contacts in the power supply contact groups of the partitions are electrically connected. Partitioning of cores is achieved by grouping power contacts.
  • the chip power supply system further includes: a printed circuit board and at least one copper sheet; the multi-core chip is arranged on one side of the printed circuit board and is electrically connected to the printed circuit board; at least part of the copper sheet is pasted Attached to the side of the printed circuit board away from the multi-core chip; wherein, at least part of the power supply contacts in the power supply contact group are electrically connected to the corresponding power supply module through the through holes and copper sheets of the printed circuit board.
  • the heat dissipation effect of the printed circuit board and the multi-core chip can be improved by arranging the copper sheet.
  • the power supply contacts in a part of the power supply contact group are electrically connected to the corresponding power supply module through the via holes or blind holes in the printed circuit board, and the power supply contacts in the other part of the power supply contact group
  • the power supply contact is electrically connected with the corresponding power supply module through the copper sheet.
  • the N partitions include the first partition and the second partition, the rated voltages of the cores in the first partition are all the first voltage, and the rated voltages of the cores in the second partition are all the second voltage. Voltage; the first voltage is greater than the second voltage.
  • the cores in the same partition have the same rated voltage, and the cores in the same partition may require the same voltage before and after overclocking during the operation of the cores.
  • the power module provides voltages to all cores in the same partition without the problem of some cores receiving a voltage less than required, and some cores receiving a voltage greater than required
  • the performance of the multi-core chip is guaranteed; on the other hand, since the voltages required by the cores in the partitions corresponding to any power supply module are basically the same, the difficulty of voltage conversion by the power supply module can be reduced.
  • the highest operating frequency of the cores in the first partition is greater than the highest operating frequency of the cores in the second partition. Then the cores in the same partition can perform the same type of operation, and the cores in the same partition have the same type of operation, which can realize that the cores in the same partition require basically the same average voltage during operation.
  • the N partitions include at least two first partitions, and the number of cores in each first partition is the same.
  • the number of cores in different first partitions is the same, that is, the cores for high-frequency operations are equally divided to reduce the difficulty of the power supply module.
  • the N partitions include at least two second partitions, and the number of cores in each second partition is the same.
  • the number of cores in different second partitions is the same, that is, the cores for low-frequency operations are equally divided to reduce the difficulty of the power supply module.
  • the chip power supply system includes at least two power supply controllers, and the at least two power supply controllers are respectively electrically connected to different power supply modules. Setting more power controllers can better control the work of multiple power supply modules with different requirements.
  • the at least two power supply controllers include a first power supply controller and a second power supply controller; among the power supply modules electrically connected to the first power supply controller, each power supply module in the corresponding partition The rated voltage of the core is the first voltage; among the power supply modules electrically connected to the second power controller, the rated voltage of the cores in the partitions corresponding to each power supply module is the second voltage, and the first voltage is greater than the second voltage.
  • the performances of the corresponding cores in the power supply modules controlled by the same power controller are basically the same, so one power controller can easily control multiple power supply modules at the same time.
  • the present application provides a chip power supply method, which is used to supply power to the multi-core chip in the chip power supply system provided in the first aspect; the method includes: receiving a power supply service scheduling instruction of the multi-core chip, Determine the voltage required by the cores in each partition of the multi-core chip; according to the determined voltage required by the cores in each partition of the multi-core chip, control the power supply modules corresponding to each partition to convert the received voltage to the core in the corresponding partition required voltage.
  • the method also includes monitoring the occupancy rate of the cores in each partition of the multi-core chip and the power consumption and/or temperature of the multi-core chip; judging the monitored cores in each partition of the chip Whether the occupancy rate of the multi-core chip, the power consumption and/or temperature of the multi-core chip exceed the threshold value; if the occupancy rate of the core in at least one partition reaches the threshold value and the power consumption and/or temperature of the multi-core chip do not reach the threshold value, control the The corresponding power supply module increases the output voltage.
  • the occupancy rate of the cores in at least one partition does not reach the threshold and the power consumption and/or temperature of the multi-core chip does not reach the threshold, then it is determined according to the power supply service scheduling instruction that in the at least one partition the core voltage required.
  • the present application provides an electronic device, including the chip power supply system as provided in the first aspect.
  • the present application provides a computer-readable storage medium, the computer-readable storage medium includes a stored program, wherein when the stored program is running, the device where the computer storage medium is located is controlled to execute the method provided in the second aspect.
  • FIG. 1 is a schematic diagram of a chip power supply scheme
  • FIG. 2 is a schematic diagram of another chip power supply scheme
  • FIG. 3 is a diagram of an application scenario corresponding to the embodiment of the present application.
  • FIG. 4 is another application scenario diagram corresponding to the embodiment of the present application.
  • FIG. 5 is a schematic diagram of a chip power supply system provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of another chip power supply system provided by the embodiment of the present application.
  • FIG. 7 is a schematic diagram of power supply of a chip power supply system provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of power supply of another chip power supply system provided by the embodiment of the present application.
  • FIG. 9 is a schematic diagram of power supply of another chip power supply system provided by the embodiment of the present application.
  • FIG. 10 is a schematic cross-sectional view of a chip power supply system provided by an embodiment of the present application.
  • FIG. 11 is a schematic cross-sectional view of another chip power supply system provided by the embodiment of the present application.
  • FIG. 12 is a schematic diagram of power supply of another chip power supply system provided by the embodiment of the present application.
  • Fig. 13 is a schematic diagram of power supply of another chip power supply system provided by the embodiment of the present application.
  • FIG. 14 is a flowchart of a chip power supply method provided by an embodiment of the present application.
  • FIG. 15 is a flow chart of another chip power supply method provided by the embodiment of the present application.
  • FIG. 16 is a flow chart of another chip power supply method provided by the embodiment of the present application.
  • An integrated circuit uses a certain process to interconnect components such as transistors, resistors, capacitors, and inductors and wiring required in a circuit, and deploys them on at least one semiconductor wafer or dielectric substrate to form a circuit with all components.
  • Microstructures that require circuit functionality. ICs can include processors, microprocessors, controllers, controller hubs, field-programmable gate arrays (FPGAs), programmable logic arrays (programmable logic arrays (PLA), microcontrollers, advanced programmable Programmable interrupt controller (advanced programmable interrupt controller, APIC) or other semiconductor or electronic devices.
  • FPGAs field-programmable gate arrays
  • PDA programmable logic arrays
  • microcontrollers programmable logic arrays
  • APIC advanced programmable Programmable interrupt controller
  • the structure formed after IC packaging is called a chip.
  • the bottom of the chip is equipped with contacts as the input/output of the circuit. These contacts can be soldered on the printed circuit board, and the chip can be connected to other chips or devices through the printed circuit board and transmit signals to each other.
  • the contacts on the bottom of the chip can have different functions, for example, they can include signal contacts to transmit signals, and power contacts to transmit voltage.
  • Figure 1 is a schematic diagram of a chip power supply scheme
  • Figure 2 is a schematic diagram of another chip power supply scheme.
  • the power supply module 12' that supplies power to all cores H' in the chip 110' is a power supply module 12', and the power supply module 12' adjusts the received voltage and provides it to the chip 110' Each kernel H' in .
  • This solution corresponds to a large number of power supply circuits, which makes the total power supply voltage large, so the power supply design is difficult. For example, the design difficulty of the package solder ball flow sharing increases, the difficulty of the flow design of the printed circuit board increases, and the number of layers of the printed circuit board increases.
  • a power supply module 12' is designed inside the package of the chip 110' to supply power to each core H' of the chip 110', and the power supply module 12' converts the voltage provided by the main board into its corresponding The voltage required by the core H'.
  • the voltage provided by the motherboard is 1.8V
  • the voltage required by a core H' in the chip 110' is 0.9V
  • the power supply module 12' corresponding to the core H' can convert the voltage of 1.8V to 0.9V. is provided to the kernel H'.
  • This solution can provide separate power supply for each core H' of the chip 110', and each power supply system is independently controllable, so this solution can provide the respective required voltages for each core H' in the chip 110', and can be used in When the performance of the core H' in the chip 110' changes, the adjusted voltage is provided for the core H' whose performance changes.
  • multiple power supply modules 12' are included in this solution, it is more difficult to design and package the multiple power supply modules 12' and the chip 110' at the same time, and it is more difficult to process the semiconductor, and the packaging cost of the chip 110' increases.
  • improving the processing performance of the chip 110' usually affects the power supply voltage of at least some of the cores H' in the chip 110'. supply voltage.
  • the power supply voltage has a large surge or drop. Too large will shorten the life of the chip 110', or the drop voltage will cause the power supply voltage to fail to meet the minimum voltage requirement of the chip 110' and cause the machine to crash; scheme 2 can quickly provide the corresponding voltage for the performance change of each core H' in the chip 110' , but since it includes more power supply modules 12', the difficulty of power supply design will also increase.
  • the present application provides a chip power supply system and a chip power supply method to solve the above problems.
  • FIG. 3 is a diagram of an application scenario corresponding to the embodiment of the present application
  • Figure 4 is another application scenario corresponding to the embodiment of the present application.
  • An application scenario graph An application scenario graph.
  • the chip power supply system 10 and the chip power supply method provided by the embodiment of the present application can be applied to a server mainboard, which serves as a high-performance carrier of the server, and the chip it includes is the brain of the server.
  • the chip of the server motherboard not only needs to have good compatibility, interchangeability, and scalability, but also needs extremely high stability.
  • the server motherboard also includes a power input terminal 20 , an interface card connector 30 and a memory stick 40 .
  • AI is being widely used in various applications, but with the rapid development of AI technology and applications, traditional processors have been unable to meet the computing power required by AI, so AI processor modules have emerged.
  • the chip power supply system 10 and the chip power supply method provided by the embodiment of the present application can be applied to AI processor modules.
  • the chips in the AI processor module need to perform a lot of calculations and reasoning, so a large power consumption and stability.
  • the AI processor module also includes a power supply and a signal connector 20'.
  • FIG. 5 is a schematic diagram of a chip power supply system provided by an embodiment of the present application
  • FIG. 6 is a schematic diagram of another chip power supply system provided by an embodiment of the present application.
  • the embodiment of the present application provides a chip power supply system 10 , as shown in FIGS. 5-7 , including a multi-core chip 110 , multiple power supply modules 12 and at least one power controller 13 .
  • the multi-core chip 110 includes multiple cores (Cores) H.
  • the multi-core chip 110 may be a multi-die multi-core (multi-Die multi-core) chip, or a single-die multi-core (single Die multi-core) chip.
  • the core involved in the embodiment of the present application is an independent processing unit packaged in the multi-core chip 110 .
  • a multi-core chip 110 includes multiple partitions 11, and each partition 11 includes at least one core H, as shown in Figures 5-6, the chip 110 in the chip power supply system 10 provided by this application includes N partition 11, and the N partitions 11 are respectively partition 111, . . . , partition 11N, where N is a positive integer greater than or equal to 2. That is to say, the present application groups the multiple cores H in the multi-core chip 110 .
  • each partition 11 in the multi-core chip 110 includes at least two cores H, that is, at least two cores H are divided into the same partition 11 . That is, after the multiple cores H in the multi-core chip 110 are grouped, at least one group includes multiple cores H.
  • all partitions 11 include at least two cores H. In another implementation manner, some partitions 11 each include at least two cores H, and some partitions 11 include only one core H.
  • the power supply module 12 is set corresponding to the partition 11. Specifically, multiple power supply modules 12 can be set in one-to-one correspondence with the multiple partitions 11.
  • the chip power supply system 10 provided by this application includes N power supply modules. module 12, and the N power supply modules 12 are respectively power supply modules 121, ..., power supply modules 12N, and the power supply modules 121, ..., power supply modules 12N are set in one-to-one correspondence with the partitions 111, ..., and 11N.
  • the output terminal of the power supply module 12 is electrically connected to the core H in the corresponding partition 11 , and the power supply module 12 is used to convert the received voltage into the voltage required by the core H in the corresponding partition 11 .
  • the power controller 13 is electrically connected to at least one power supply module 12, and the power controller 13 controls the correspondingly connected power supply module 12 to convert the voltage received by the power supply module 12 into a voltage required by the core.
  • the power supply module 121 receives a voltage of 1.6V, wherein the core H in the partition 111 needs a voltage of 0.8V, and the power controller 13 controls the power supply module 121 to convert the received voltage of 1.6V to After being 0.8V and providing it to the core H in the partition 111; the core in the partition 11N needs a voltage of 0.4V, and the power supply module 12N controlled by the power controller 13 converts the received 1.6V voltage into 0.4V and provides it to Kernel H in partition 11N.
  • the number of power supply modules 12 can be reduced and the packaging difficulty of the multi-core chip can be reduced;
  • the size of the power supply current reduces the current jump drop and correspondingly reduces the dynamic drop range of the power supply; on the other hand, different voltages can be provided for the core H in different partitions 11, and different voltages can be provided for the core H in different partitions 11. power supply adjustment.
  • one power controller 13 can control multiple power supply modules 12 to perform voltage conversion, one power supply module 12 can provide voltage for multiple cores H in one partition 11, and different power supply modules 12 are respectively for different partitions Core H in 11 provides the voltage.
  • the multiple partitions 11 include the first partition and the second partition, the rated voltage of the core H in the first partition is the first voltage, the rated voltage of the core H in the second partition is the second voltage, and the first voltage greater than the second voltage.
  • the partition 111 is the first partition
  • the partition 11N is the second partition
  • the rated voltage of the core H in the partition 111 is higher than the rated voltage of the core H in the partition 11N.
  • the cores H in the chip can be grouped according to the highest frequency to which they can run.
  • the core H that can run to a higher frequency can perform high-performance computing services, and high-performance computing services require a higher operating voltage, then the cores H that can run to a higher frequency can be grouped into the first partition Medium; only the core H that can run to a lower frequency can perform ordinary computing services, and a lower operating voltage is required for ordinary computing services, so the core H that can run to a lower frequency can be grouped into the second partition .
  • the highest operating frequency of each core H in the first partition is greater than the highest operating frequency of each core H in the second partition.
  • the operation types of the cores H in the same partition 11 are the same, for example, the cores H in the same partition 11 are all used for high-performance computing, and/or the cores H in the same partition 11 are all used for scheduling operations.
  • one power controller 13 can control multiple power supply modules 12 to convert the received voltage into the voltage required by the cores H in the corresponding multiple partitions 11 .
  • the cores H in the same partition 11 perform the same operation type, then the voltage required by the power supply module 12 for all the cores H in the same partition 11 is basically the same, and all the cores H in the same partition 11 are in The voltage required by the multi-core chip 110 after overclocking is still basically the same.
  • the voltage provided by the power supply module 12 for all the cores H in the same partition 11 will not cause the problem that the voltage received by some cores H is less than the required voltage, nor will the voltage received by some cores H The problem of being greater than the required voltage ensures the performance of the multi-core chip 110; Difficulty working with voltage conversion.
  • the number of partitions 11 is less than the number of cores H, so the number of power supply modules 12 corresponding to partitions 11 is less than that of cores H If the quantity is small, the design difficulty of the power supply module 12 is reduced, thereby reducing the design difficulty of the chip power supply system.
  • the power supply module 12 may include a transistor switch, the input terminal of the transistor switch receives a voltage, the output terminal is electrically connected to multiple cores H in the partition 11 corresponding to the power supply module 12, and the control terminal is connected to the power supply
  • the controller 13 is electrically connected.
  • the power controller 13 controls the turn-off and turn-on of the transistor switch. Further, by controlling the turn-on duration of the transistor switch in the power supply module 12N, the output voltage of the power supply module 12N can be controlled.
  • the number of power controller 13 may be one.
  • the chip power supply system 10 includes M power controllers 13 , where M is a positive integer greater than or equal to 2, and the M power controllers 13 are power controllers 131 , . . . , power controller 13M.
  • the power controller 131 is electrically connected to the power supply modules 121, ..., and the power supply modules 12i, and the power supply modules 121, ..., and the power supply modules 12i respectively provide voltages for the core H in the partition 111, ..., and the partition 11i, 11 ⁇ i ⁇ 2;
  • the power supply controller 13M is electrically connected to the power supply modules 121k, ..., and the power supply controller 12N, and the power supply modules 12k, ..., and the power supply modules 12N provide voltages for the cores H in the partitions 11k, ..., and 11N respectively , k ⁇ i ⁇ N.
  • the chip power supply system 10 includes M power supply controllers 13 , at least one power supply controller 13 is electrically connected to multiple power supply modules 12 . And among the plurality of power supply modules 12 electrically connected to the same power supply controller 13, the computing performance of the core H in the partition 11 corresponding to each power supply module 12 is the same or similar, and the voltage required by the core H in these partitions 11 is also the same. Basically the same or similar.
  • the multiple power controllers 13 include a first power controller and a second power controller.
  • the rated voltage of the kernel H in the partition 11 corresponding to each power supply module 12 is the first voltage; in the power supply modules 12 electrically connected to the second power supply controller, each power supply module 12 The rated voltage of the core H in the corresponding partition 11 is the second voltage, and the first voltage is greater than the second voltage. That is to say, the power supply modules 12 connected to and controlled by the first power controller are all power supply modules 12 that provide voltage for the core H in the first partition, and the power supply modules 12 connected to the second power controller are all the power supply modules 12 of Confucius in the second partition The core H provides voltage to the power supply module 12 .
  • the type of operation that the core H participates in is usually determined according to the performance of the core H.
  • the performances of the cores H in the partitions 11 electrically connected to the multiple power supply modules 12 electrically connected to the same power controller 13 are the same or similar, that is, when the rated voltage is the same, the power controller 13 can conveniently control these
  • the power supply module 12 converts the received voltage to output the same or similar voltage.
  • Figure 7 is a schematic diagram of power supply for a chip power supply system provided by the embodiment of the present application
  • Figure 8 is a schematic diagram of power supply for another chip power supply system provided by the embodiment of the present application
  • Figure 9 is another chip provided by the embodiment of the present application Schematic diagram of the power supply system.
  • the multiple partitions 11 in the multi-core chip 110 include at least two first partitions, and the cores H included in the at least two first partitions are all high-performance computing cores.
  • all the partitions 11 are the first partitions. As shown in FIG. 7 , the partitions 111 to 11N are all the first partitions, and the cores H in the partitions 111 to 11N are high-performance computing cores.
  • each partition 11 includes j cores.
  • all partitions 11 further include at least one second partition, and the kernel H included in the second partition is a scheduling operation core, that is, the kernel H in some partitions 11 among the multiple partitions 11 of the multi-core chip 110 is Scheduling computing cores.
  • the partition 111 is the second partition and the kernel H in the partition 111 is the scheduling operation core
  • the partition 112 to the partition 11n are the first partitions
  • the kernel H in the partition 112 to the partition 11n is the high-performance computing core .
  • Computing cores are evenly grouped into multiple partitions 11 , for example, as shown in FIG. 8 , each partition 11 includes j high-performance computing cores.
  • partition 111 and partition 11 (n-1) are the second partition and the kernel H in partition 111 and partition 11 (n-1) is a scheduling calculation core, and the kernel H in other partitions is high performance computing cores and each partition 11 may include the same number of j high performance computing cores.
  • the partitions 112 to 11n are the first partitions and the cores H in the partitions 112 to 11n are high-performance computing cores.
  • each second partition when multiple second partitions are included in the multi-core partition 11, the number of scheduling operation cores in each second partition may also be the same, for example, each second partition includes one scheduling operation nuclear.
  • the number of high-performance computing cores in each first partition is the same.
  • FIG. 10 is a schematic cross-sectional view of a chip power supply system provided by an embodiment of the present application
  • FIG. 11 is a schematic cross-sectional view of another chip power supply system provided by an embodiment of the present application.
  • multiple power supply modules 12 in the chip power supply system 10 may be arranged outside the chip packaging structure.
  • the chip power supply system 10 also includes a printed circuit board 15, the power controller 13, the power supply module 12 and the multi-core chip 110 can all be arranged on the printed circuit board 15, and the power supply The controller 13 controls the power supply module 12 to perform voltage conversion through the printed circuit board 15 , and the power supply module 12 outputs voltage to the multi-core chip 110 through the printed circuit board 15 .
  • one side of the multi-core chip 110 is provided with a plurality of power supply contacts 110a, the power supply contacts 110a are welded to the printed circuit board 15, and the power supply contacts 110a receive the voltage output by the power supply module 12 through the printed circuit board 15 and convert the received The voltage is transmitted to the core H in the multi-core chip 110 .
  • the multiple power supply contacts 110a are divided into multiple power supply contact groups, each power supply contact group includes at least one power supply contact 110a, and the multiple power supply contact groups are set in one-to-one correspondence with the multiple partitions 11, and the power supply contact groups
  • the power supply contacts in the point group are the power supply contacts of the core H in the partition corresponding to the power supply contact group.
  • the power supply module 12 outputs voltage to the multi-core chip 110 through the printed circuit board 15, specifically, the power supply module 12 is electrically connected to the printed circuit board 15 and the power supply contact 110a in the corresponding power supply contact group as the core in the corresponding partition 11 H outputs the required voltage.
  • the power supply module 12 is electrically connected to the power supply contacts 110 a in the corresponding power supply contact group through via holes or blind holes in the printed circuit board 15 .
  • the power supply module 12 and the multi-core chip 110 are respectively disposed on opposite sides of the printed circuit board 15 , and the power supply module 12 is electrically connected to the power supply contacts 110 a of the plurality of chips 110 .
  • the chip power supply system 10 further includes at least one copper sheet 14 , and at least part of the copper sheet 14 is attached to the side of the printed circuit board 15 away from the multi-core chip 110 .
  • at least part of the power supply contacts 110a in the power supply contact group are electrically connected to the corresponding power supply module 12 through the copper sheet 14 .
  • the application is provided with a copper sheet 14 on the back side of the printed circuit board 15 bound with the multi-core chip 110. Accelerate the heat dissipation of the chip power supply system. Moreover, by electrically connecting part of the power supply module and the power supply contact 110a through the copper sheet 14, the number of through holes and/or blind holes in the printed circuit board 15 can be reduced, and the number of layers and design difficulty of the printed circuit board 15 can be reduced.
  • the core H in the partition 11 corresponding to the power supply contact 110 a electrically connected to the power supply module 12 through the copper sheet 14 may be a high-performance computing core.
  • the power supply contact 110a corresponding to a part of the partition 11 is electrically connected to the corresponding power supply module 12 through a via hole or a blind hole in the printed circuit board 15, and the power supply contact 110a corresponding to another part of the partition 11 110 a is electrically connected to the corresponding power supply module 12 through the copper sheet 14 .
  • multiple power supply modules 12 in the chip power supply system 10 may also be arranged inside the chip packaging structure.
  • FIG. 12 is a schematic diagram of another chip power supply system provided by the embodiment of the present application
  • FIG. 13 is a schematic diagram of power supply of another chip power supply system provided by the embodiment of the present application.
  • the power supply module 12 may include a one-phase power supply circuit 120 , or may include a multi-phase power supply circuit 120 .
  • each power supply module 12 may include a one-phase power supply circuit 120 respectively, or each power supply module 12 may include the same multi-phase power supply circuit 120 .
  • the power supply module 12 corresponding to the partition 11 containing the high-performance computing core H may contain a multi-phase power supply circuit 120, and the power supply module 12 corresponding to the partition 11 containing the scheduling computing core H may contain Single-phase power supply circuit 120 .
  • FIG. 14 is a flowchart of a chip power supply method provided by an embodiment of the present application.
  • the embodiment of the present application also provides a chip power supply method, which is used to supply power to the multi-core chip in the chip power supply system provided by any one of the above embodiments.
  • the power supply method includes:
  • S1 Receive a power supply service scheduling instruction of the multi-core chip, and determine voltages required by cores in each partition of the multi-core chip according to the power supply service scheduling instruction.
  • the power supply controller communicates with the multi-core chip, and the multi-core chip sends a power supply service scheduling command to the power supply controller, indicating the voltage required by each partition; the core voltage required.
  • the power controller After the power controller receives the power supply business scheduling instruction for supplying power to multi-core chips, it turns on the partition power supply mode, that is, controls multiple power supply modules to turn on, and controls the power supply modules to adjust the voltage output by the power controller to the cores in the corresponding partitions. voltage.
  • the power supply service scheduling instruction received by the power controller is an instruction to adjust the voltage of all cores, all power supply modules are turned on, and all power supply modules are controlled to convert the received voltages.
  • the voltage converted and adjusted by the power supply module is provided to the cores in each partition of the multi-core chip.
  • the power supply service dispatching instruction received by the board management system is an instruction to adjust the voltage of some cores, it will turn on the power supply modules corresponding to the partitions where these cores are located, and control these power supply modules to convert the received voltage.
  • the voltage converted and adjusted by the power supply module is provided to the cores in some partitions of the multi-core chip.
  • the power supply business dispatching instruction it is determined that the voltage required by the cores in other partitions remains unchanged and the state of the corresponding power supply module remains unchanged, then the state of the power supply modules corresponding to the partitions where the cores that do not need voltage regulation are located can be controlled to remain unchanged.
  • the power supply module may include transistors, and controlling the power supply modules corresponding to each partition to convert the received voltage to the voltage required by the core in the corresponding partition means that the power controller controls the power supply module in each power supply module The turn-on time of the transistor, the voltage converted by the different turn-on times of the transistor is different.
  • FIG. 15 is a flow chart of another chip power supply method provided by the embodiment of the present application.
  • the chip power supply method provided in the embodiment of the present application further includes:
  • S3 Monitor the occupancy rate of the cores in each partition of the multi-core chip and the power consumption and/or temperature of the multi-core chip.
  • the occupancy rate of the cores in the partition can indicate the operation status of the cores. If the occupancy rate of the cores in some partitions is detected to reach the threshold, it means that these cores are always in high-performance operation. If conditions permit, these cores that are always in high-performance computing can be overclocked to improve the performance of multi-core chips.
  • the power consumption and temperature of the multi-core chip can reflect whether the multi-core chip has overclocking conditions at this time. If the power consumption or temperature of the multi-core chip reaches the limit, the multi-core chip cannot be overclocked; if the power consumption and temperature of the multi-core chip do not exceed the limit, the overclocking can be started.
  • S4 Determine whether the occupancy rate of cores in each partition of the monitored chip, the power consumption and/or temperature of the multi-core chip exceed a threshold
  • the power supply module corresponding to the at least one partition is controlled to increase the output voltage.
  • the core occupancy rate of some partitions in the multi-core chip reaches the threshold or has exceeded the threshold and the power consumption and temperature of the multi-core chip do not reach the threshold, you can overclock the cores of these partitions; and control these partitions before overclocking
  • the corresponding power supply module increases the output voltage.
  • the overclocking will stop.
  • the base frequency of the cores in a certain partition is 3GHz, and the cores in this partition are overclocked to 3.3GHz, but the power consumption and temperature of the multi-core chips have not reached the limit, then the cores in the partition can continue to be overclocked; when the cores in the partition When the core is overclocked to 3.6GHz, the power consumption and temperature of the multi-core chip are close to the threshold, and the overclocking of the cores in the partition will be stopped; and the cores in the partition will perform high-performance computing at a main frequency of 3.6GHz. At this time, the overclocked core The power consumption will be much larger than that without overclocking.
  • the occupancy rate of the cores in at least one partition does not reach the threshold and the power consumption and/or temperature of the multi-core chip does not reach the threshold, then determine the voltage required by the cores in the at least one partition according to the power supply service scheduling instruction.
  • the power supply service scheduling instruction can be used to determine the cores in each partition of the multi-core chip. voltage.
  • the main frequency of these cores can be lowered or placed in an idle state.
  • FIG. 16 is a flow chart of another chip power supply method provided by the embodiment of the present application.
  • the chip power supply method provided by the embodiment of the present application is systematically introduced below with reference to FIG. 16 .
  • the chip power supply system partitions multiple cores according to the performance of multiple cores in a multi-core chip and the cores in the same partition have the same operation type, the chip power supply system first initializes the partition power supply according to the operation type of the core, and the chip power supply system The power supply enters the normal state.
  • the power supply controller receives the power supply business dispatching instruction of the multi-core chip, and the power supply controller controls the output voltage of multiple power supply modules, that is, adjusts all partitions according to the power supply business scheduling instruction.
  • the core voltage ensures that the cores in the multi-core chip complete the operation.
  • the power controller will receive the power supply business scheduling instruction of the multi-core chip again, the chip power supply system will initialize partition power supply again according to the operation type of the core, and the power supply of the chip power supply system will enter the normal state again.
  • the multi-core chip monitors the occupancy rate of the cores in each partition and the power consumption and temperature of the multi-core chip in real time or periodically.
  • the multi-core chip keeps real-time or regular monitoring of the occupancy rate of the cores in each partition and the power consumption and temperature of the multi-core chip.
  • the power controller will receive the power supply business scheduling instruction of the multi-core chip again, the chip power supply system will initialize partition power supply again according to the operation type of the core, and the power supply of the chip power supply system will enter the normal state again.
  • the voltage in the non-overclocking partition can be lowered simultaneously or the state of the cores in the non-overclocking partition can be adjusted to be idle, thereby reducing the power consumption of the multi-core chip.
  • the embodiment of the present application also provides an electronic device, the electronic device includes the chip power supply system provided in the present application.
  • the electronic device may be a terminal, for example, a personal computer, a mobile phone, a palmtop computer, a wearable electronic device, a vehicle-mounted device, and the like.
  • the electronic device may also be a network device, for example, a switch, a router, a firewall, a base station, a wireless access point, a wireless controller, and the like.
  • the electronic device may also be a storage device, such as a storage server, a storage array, and the like.
  • the electronic device may also be a device providing high performance computing.
  • Various implementations in the present application can be combined with each other on the premise of no conflict, and corresponding technical effects can be achieved.
  • an embodiment of the present application also provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, and when the stored program is running, the electronic device where the computer storage medium is located is controlled to execute the method of any one of the above-mentioned embodiments.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (read-only memory, ROM) or a random access memory (random access memory, RAM), etc.

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Abstract

本申请提供一种芯片供电系统及方法、电子设备、计算机可读存储介质，芯片供电系统包括多核芯片、多个供电模块及至少一个电源控制器；多核芯片包括N个分区，至少部分分区中的每个分区包括至少两个内核；N个供电模块与N个分区一一对应设置；电源控制器与至少一个供电模块连接，且电源控制器用于控制其所连接的供电模块将接收到的电压转换为内核所需的电压；其中，供电模块的输出端与其所对应的分区中的内核电连接，供电模块用于将其所接收的电压转换为其所对应的分区中内核所需的电压。通过将多核芯片中的内核进行分区供电，可以减小供电模块的数量，降低多核芯片的封装难度；可以为不同分区的内核提供不同的电压。

Description

芯片供电系统及方法、电子设备、计算机可读存储介质
本申请要求于2021年8月30日提交中国专利局、申请号为202111006683.8、申请名称为“芯片供电系统及方法、电子设备、计算机可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片技术领域，尤其涉及一种芯片供电系统及方法、电子设备、计算机可读存储介质。
背景技术
第五代移动通信技术(5 th generation mobile network，5G)和人工智能(artificial intelligence，AI)等应用的发展，需要网络芯片提供更强的交换处理能力，也需要中央处理器(central processing unit，CPU)和AI芯片提供更强大的运算能力，这必然导致这些芯片在工作时需要更大的电流和电压。
如何合理地为工作中的芯片提供更大的电流和电压，成为本领域亟待解决的问题。
发明内容
本申请提供了一种芯片供电系统及方法、电子设备、计算机可读存储介质。
第一方面，本申请提供一种芯片供电系统，包括多核芯片、多个供电模块及至少一个电源控制器；多核芯片包括N个分区，各个分区中均包括至少一个内核；且N个分区的至少部分分区中，每个分区包括至少两个内核；N个供电模块与N个分区一一对应设置；电源控制器与至少一个供电模块连接，且电源控制器用于控制其所连接的供电模块将接收到的电压转换为内核所需的电压；其中，供电模块的输出端与其所对应的分区中的内核电连接，供电模块用于将其所接收的电压转换为其所对应的分区中内核所需的电压。通过将多核芯片中的内核进行分区供电，一方面，可以减小供电模块的数量，降低多核芯片的封装难度；另一方面可以大电流电源分成多个小电流电源，降低了多核芯片核电源电流大小，降低了电流跳变落差，相应地减小了电源动态跌落幅度；再一方面，可以为不同分区的内核提供不同的电压，并可以对不同分区中的内核进行不同的供电调整。
在第一方面的一种实现方式中，芯片的一侧包括多个供电触点，任意一个分区中内核对应的供电触点形成一个供电触点组；供电模块的输出端与其所对应的所述分区的所述供电触点组中的所述供电触点电连接。通过将供电触点进行分组实现对内核的分区。
在第一方面的一种实现方式中，芯片供电系统还包括：印刷电路板、至少一个铜 片；多核芯片设置在印刷电路板的一侧且与印刷电路板电连接；铜片的至少部分贴附在印刷电路板背离多核芯片的一侧；其中，至少部分供电触点组中的供电触点通过印刷电路板的通孔及铜片与对应的供电模块电连接。通过设置铜片可以提升印刷电路板及多核芯片的散热效果。
在第一方面的一种实现方式中，部分供电触点组中的供电触点通过印刷电路板中的导通孔或者盲孔与对应的供电模块电连接，另一个部分供电触点组中的供电触点通过铜片与对应的供电模块电连接。一方面可以提升印刷电路板及多核芯片的散热效果，一方面可以降低印刷电路板的设计难度及承办。
在第一方面的一种实现方式中，N个分区中包括第一分区和第二分区，第一分区中内核的额定电压均为第一电压，第二分区中内核的额定电压均为第二电压；第一电压大于第二电压。对多核芯片进行分组时，同一分区中的内核的额定电压相同，则在内核进行运算的过程中，同一分区中的内核所需的电压在超频前可以相同且在超频后也可以相同。一方面，供电模块为同一分区中所有内核所提供的电压，不会产生某些内核接收到的电压小于所需的电压的问题，也不会产生某些内核接收到的电压大于所需的电压的问题，保证了多核芯片的性能；另一方面，由于任意一个供电模块所对应的分区中内核的所需的电压基本相同，则可以减小供电模块进行电压转换的工作难度。
在第一方面的一种实现方式中，第一分区中内核的最高运算频率大于第二分区中内核的最高运算频率。则同一分区中的内核可以进行相同的运算类型，而同一分区中的内核的运算类型相同，可以实现分区中的内核在运算时所需的均电压均基本相同。
在第一方面的一种实现方式中，N个分区中包括至少两个第一分区，各个第一分区中内核的数量均相同。不同第一分区中的内核数量相同，即对高频率运算的内核进行均分，降低供电模块的难度。
在第一方面的一种实现方式中，N个分区中包括至少两个第二分区，各个第二分区中内核的数量均相同。不同第二分区中的内核数量相同，即对低频率运算的内核进行均分，降低供电模块的难度。
在第一方面的一种实现方式中，芯片供电系统包括至少两个电源控制器，该至少两个电源控制器分别与不同的供电模块电连接。设置较多的电源控制器可以更好的控制多个不同需求的供电模块进行工作。
在第一方面的一种实现方式中，至少两个电源控制器包括第一电源控制器和第二电源控制器；第一电源控制器电连接的供电模块中，各个供电模块对应的分区中的内核的额定电压为第一电压；第二电源控制器电连接的供电模块中，各个供电模块对应的分区中的内核的额定电压为第二电压，第一电压大于第二电压。同一电源控制器所控制的供电模块中对应的内核的性能基本相同，则一个电源控制器易于实现对多个供电模块的同时控制。
第二方面，本申请提供一种芯片的供电方法，用于对第一方面提供的芯片供电系统中的多核芯片进行供电；该方法包括：接收多核芯片的供电业务调度指令，根据供电业务调度指令确定多核芯片的各个分区中的内核所需的电压；根据确定的多核芯片的各个分区的内核所需的电压，控制各个分区分别对应的供电模块将接收的电压转换 为其所对应的分区中内核所需的电压。
在第二方面的一种实现方式中，该方法还包括，监测多核芯片的各个分区中的内核的占用率及多核芯片的功耗和/或温度；判断监测到的芯片的各个分区中的内核的占用率、多核芯片的功耗和/或温度是否超过阈值；若至少一个分区中的内核的占用率达到阈值且多核芯片的功耗和/或温度未达到阈值，则控制该至少一个分区所对应的供电模块调高输出的电压。
在第二方面的一种实现方式中，若至少一个分区中的内核的占用率未达到阈值且多核芯片的功耗和/或温度未达到阈值，则根据供电业务调度指令确定该至少一个分区中的内核所需的电压。
第三方面，本申请提供一种电子设备，包括如第一方面提供的芯片供电系统。
第四方面，本申请提供一种计算机可读存储介质，该计算机可读存储介质包括存储程序，其中，在存储程序运行时控制计算机存储介质所在设备执行第二方面提供的方法。
附图说明
图1为一种芯片供电方案的示意图；
图2为另一种芯片供电方案的示意图；
图3为本申请实施例对应的一种应用场景图；
图4为本申请实施例对应的另一种应用场景图；
图5为本申请实施例提供的一种芯片供电系统的示意图；
图6为本申请实施例提供的另一种芯片供电系统的示意图；
图7为本申请实施例提供的一种芯片供电系统的供电示意图；
图8为本申请实施例提供的另一种芯片供电系统的供电示意图；
图9为本申请实施例提供的又一种芯片供电系统的供电示意图；
图10为本申请实施例提供的一种芯片供电系统的剖面示意图；
图11为本申请实施例提供的另一种芯片供电系统的剖面示意图；
图12为本申请实施例提供的再一种芯片供电系统的供电示意图；
图13为本申请实施例提供的还一种芯片供电系统的供电示意图；
图14为本申请实施例提供的一种芯片供电方法的流程图；
图15为本申请实施例提供的另一种芯片供电方法的流程图；
图16为本申请实施例提供的又一种芯片供电方法的流程图。
具体实施方式
本申请的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释，而非旨在限定本申请。
集成电路(integrated circuit，IC)是采用一定的工艺，把一个电路中所需要的晶体管、电阻、电容和电感等元件及布线互联在一起，并部署在至少一个半导体晶片或介质基片上形成具有所需电路功能的微型结构。IC可以包括处理器、微处理器、控制器、控制器集 线器、现场可编程门阵列(field-programmable gate array，FPGA)、可编程逻辑阵列(programmable logic array，PLA)、微控制器、高级可编程中断控制器(advanced programmable interrupt controller，APIC)或其他半导体或者电子器件。本申请将IC封装后形成的结构称为芯片。
芯片的底部部署有触点作为电路的输入端/输出端，这些触点可以焊接在印刷电路板上，则芯片可以通过印刷电路板与其他芯片或者器件连接并相互传输信号。芯片底部的触点可以具备不同的功能，例如，可以包括传输信号的信号触点、传输电压的供电触点。
芯片的主要供电方案有以下两种，图1为一种芯片供电方案的示意图，图2为另一种芯片供电方案的示意图。
方案1，如图1所示，为芯片110’中的所有内核H’供电的供电模块12’为一个供电模块12’，该供电模块12’对接收到的电压进行调整后提供给芯片110’中的每个内核H’。该方案对应的供电路数较多，使得总的供电电压大，因此电源设计难度大。例如，封装焊球均流的设计难度增大，印刷电路板的通流设计难度增大，并且印刷电路板的层数增加。
方案2，如图2所示，在芯片110’封装内部设计有为芯片110’的每个内核H’进行供电的供电模块12’，供电模块12’将主板提供的电压转换为其所对应的内核H’所需的电压。例如主板提供的电压为1.8V，而芯片110’中的一个内核H’所需的电压为0.9V，则该内核H’所对应的供电模块12’可以将1.8V的电压转换为0.9V后提供给该内核H’。该方案可以为芯片110’的每个内核H’进行单独供电，且每一路供电系统独立可控，因此本方案可以为芯片110’中的各个内核H’提供各自所需的电压，并且可以在芯片110’中的内核H’的性能改变时为性能改变的内核H’提供调整后的电压。但是，该方案中包括多个供电模块12’，则将多个供电模块12’与芯片110’同时封装的设计难度较大且半导体的加工难度较大，并且芯片110’的封装成本增加。
随着信息技术和通信技术的发展，对芯片110’处理性能的要求越来越高。然而，芯片110’性能的提高，会导致芯片110’的核数越来越多且芯片110’的核电压越来越大，则方案1对应的电源设计难度会进一步增大，方案2对应的封装难度和成本会进一步增加。
此外，提升芯片110’的处理性能，通常会影响芯片110’中的至少部分内核H’的供电电压，例如通过超频提升芯片110’部分内核H’的性能时，需要提高该部分内核H’的供电电压。芯片110’的业务在高负荷与低负荷之间切换的瞬态变化过程中，电源电压的上冲或者跌落较大，方案1的供电方案无法快速响应芯片110’的业务变化，导致上冲电压太大使得芯片110’寿命缩短，或者跌落电压较大导致供电电压无法满足芯片110’的最小电压要求而死机；方案2虽然可以针对芯片110’中各个内核H’的性能改变快速提供对应的电压，但是由于其包括较多的供电模块12’，则其电源设计难度也会增加。
本申请提供一种芯片供电系统及芯片的供电方法以解决以上问题。
本申请实施例提供的芯片供电系统及芯片的供电方法可以至少应用于以下的两种场景，图3为本申请实施例对应的一种应用场景图，图4为本申请实施例对应的另一种应用场景图。
随着大数据、物联网、AI、5G等技术的迅猛发展，对云端计算力提出了更高的要求，进而推动了服务器相关技术的快速发展。如图3所示，本申请实施例提供的芯片供电系统10及芯片的供电方法可应用于服务器主板，服务器主板作为服务器高性能的载体，其所包括的芯片是服务器的大脑。服务器主板的芯片不仅需要具备良好的兼容性、互换性、扩展性，也需要极高的稳定性。服务器主板除包括芯片供电系统10外，还包括电源输入端20、接口卡连接器30及内存条40。
AI正在被广泛地运用于各式各样的应用上，但是随着AI技术与应用的快速发展，传统的处理器已经难以满足AI所需的算力，因此AI处理器模组应运而生。如图4所示，本申请实施例提供的芯片供电系统10及芯片的供电方法可应用于AI处理器模组，AI处理器模组中的芯片需要进行大量计算与推理，因此需要较大的功耗与稳定性。AI处理器模组除包括芯片供电系统10外，还包括电源和信号连接器20’。
图5为本申请实施例提供的一种芯片供电系统的示意图，图6为本申请实施例提供的另一种芯片供电系统的示意图。
本申请实施例提供一种芯片供电系统10，如图5-图7所示，包括多核芯片110、多个供电模块12及至少一个电源控制器13。
多核芯片110中包括多个内核(Core)H，具体地，多核芯片110可以为多晶粒多核(多Die多核)芯片，也可以为单晶粒多核(单Die多核)芯片。其中，本申请实施例所涉及的内核为封装在多核芯片110内的独立处理单元。
在本申请中，多核芯片110包括多个分区11，且每个分区11中均包括至少一个内核H，如图5-6所示，本申请提供的芯片供电系统10中的芯片110包括N个分区11，且N个分区11分别为分区111、……、分区11N，N为大于等于2的正整数。也就是说，本申请将多核芯片110中的多个内核H进行了分组。
进一步地，多核芯片110中的至少部分分区11中，每个分区11包括至少两个内核H，即至少两个核H被分在同一个分区11中。也就是，对多核芯片110中的多个内核H进行分组后，至少一个组中包括多个内核H。
在一种实现方式中，所有分区11中均包括至少两个内核H。在另一种实现方式中，部分分区11中均包括至少两个内核H，部分分区11中只包括一个内核H。
供电模块12与分区11对应设置，具体地，多个供电模块12可以与多个分区11一一对应设置，则如图5-6所示，本申请提供的芯片供电系统10中包括N个供电模块12，且N个供电模块12分别为供电模块121、……、供电模块12N，供电模块121、……、供电模块12N与分区111、……、分区11N一一对应设置。供电模块12的输出端与其所对应的分区11中的内核H电连接，并且供电模块12用于将其所接收的电压转换为其所对应的分区11中内核H所需的电压。
进一步地，电源控制器13与至少一个供电模块12电连接，电源控制器13控制对应电连接的供电模块12将供电模块12接收到的电压转换为内核所需的电压。例如， 如图5所示，供电模块121接收到1.6V的电压，其中，分区111中的内核H需要0.8V的电压，则电源控制器13控制供电模块121将接收到的1.6V的电压转换为0.8V后并提供给分区111中的内核H；分区11N中的核需要0.4V的电压，电源控制器13控制的供电模块12N将接收到的1.6V的电压转换为0.4V后并提供给分区11N中的内核H。
通过将多核芯片中的内核H进行分区供电，一方面，可以减小供电模块12的数量，降低多核芯片的封装难度；另一方面可以大电流电源分成多个小电流电源，降低了多核芯片核电源电流大小，降低了电流跳变落差，相应地减小了电源动态跌落幅度；再一方面，可以为不同分区11的内核H提供不同的电压，并可以对不同分区11中的内核H进行不同的供电调整。
在本申请实施例中，一个电源控制器13可以控制多个供电模块12进行电压转换，一个供电模块12可以为一个分区11中的多个内核H提供电压且不同的供电模块12分别为不同分区11中的内核H提供电压。
其中，多个分区11中包括第一分区和第二分区，第一分区中内核H的额定电压均为第一电压，第二分区中内核H的额定电压均为第二电压，且第一电压大于第二电压。例如分区111为第一分区，分区11N为第二分区，且设置在分区111中的内核H的额定电压均大于分区11N中的内核H的额定电压。
具体地，可以根据芯片中内核H所能运行到的最高频率对其进行分组。其中，能运行到较高频率的内核H可以进行高性能的运算业务，而进行高性能的运算业务需要更高的工作电压，则可以将能运行到较高频率的内核H分组到第一分区中；仅能运行到较低频率的内核H可以进行普通的运算业务，而进行普通的运算业务需要较低的工作电压，则可以将能运行到较低频率的内核H分组到第二分区中。
也就是说，第一分区中各内核H的最高运算频率大于第二分区各内核H的最高运算频率。
此外，位于同一分区11中的内核H的运算类型相同，例如，同一分区11中的内核H均用于进行高性能运算，和/或，同一分区11中的内核H均用于进行调度运算。
则在本申请实施例中，一个电源控制器13可以控制多个供电模块12将接收到的电压转换为所对应的多个分区11中的内核H所需的电压。
对多核芯片110进行分组时，同一分区11中的内核H所进行的运算类型相同，则供电模块12为同一分区11中所有内核H所需的电压基本相同，且同一分区11中所有内核H在多核芯片110超频后所需的电压仍然基本相同。一方面，供电模块12为同一分区11中所有内核H所提供的电压，不会产生某些内核H接收到的电压小于所需的电压的问题，也不会产生某些内核H接收到的电压大于所需的电压的问题，保证了多核芯片110的性能；另一方面，由于任意一个供电模块12所对应的分区11中内核H的所需的电压基本相同，则可以减小供电模块12进行电压转换的工作难度。
此外，由于可以根据多核芯片110中的内核H的运算类型对多个内核H进行分组，进而分区11的数量少于内核H的数量，因此与分区11对应的供电模块12的数量少于内核H的数量，则供电模块12的设计难度减小，进而减小了芯片供电系统的 设计难度。
在本申请实施例中，其中，供电模块12中可以包括晶体管开关，晶体管开关的输入端接收电压，输出端与该供电模块12对应的分区11中的多个内核H电连接，控制端与电源控制器13电连接。电源控制器13控制晶体管开关的关断与开启，进一步地，通过控制供电模块12N中晶体管开关的开启时长可以控制供电模块12N输出的电压大小。
在本申请实施例提供的芯片供电系统10中，如图5所示，电源控制器13的数量可以为1个。
在本申请实施例提供的芯片供电系统10中，如图6所示，电源控制器13的数量也可以为多个，且不同的电源控制器13分别与不同的供电模块12电连接。例如，芯片供电系统10中包括M个电源控制器13，M为大于等于2的正整数，M个电源控制器13分别为电源控制器131、……、电源控制器13M。例如，电源控制器131与供电模块121、……、供电模块12i电连接，且供电模块121、……、供电模块12i分别为分区111、……、分区11i中的内核H提供电压，11＜i≤2；电源控制器13M与供电模块121k、……、电源控制器12N电连接，且供电模块12k、……、供电模块12N分别为分区11k、……、分区11N中的内核H提供电压，k＜i≤N。
当芯片供电系统10包括M个电源控制器13时，至少存在一个电源控制器13与多个供电模块12电连接。并且与同一电源控制器13电连接的多个供电模块12中，各个供电模块12对应的分区11中的内核H的运算性能相同或相近，则该些分区11中的内核H所需的电压也基本相同或者相近。
多个电源控制器13中包括第一电源控制器和第二电源控制器。第一电源控制器电连接的供电模块12中，各个供电模块12对应的分区11中的内核H的额定电压为第一电压；第二电源控制器电连接的供电模块12中，各个供电模块12对应的分区11中的内核H的额定电压为第二电压，第一电压大于第二电压。也就是说，第一电源控制器所连接控制的供电模块12均为第一分区中的内核H提供电压的供电模块12，第二电源控制器所连接孔子的供电模块12均为第二分区中的内核H提供电压的供电模块12。
在多核芯片110中，通常根据内核H的性能确定该内核H所参与的运算类型。当与同一电源控制器13电连接的多个供电模块12所分别电连接的分区11中的内核H的性能相同或相近时，也就是额定电压相同时，则电源控制器13可以方便控制该些供电模块12将接收到的电压进行转换后所输出的相同或相近电压。
图7为本申请实施例提供的一种芯片供电系统的供电示意图，图8为本申请实施例提供的另一种芯片供电系统的供电示意图，图9为本申请实施例提供的又一种芯片供电系统的供电示意图。
在本申请的一个实施例中，多核芯片110中的多个分区11包括至少两个第一分区，且至少两个第一分区中所包括的内核H均为高性能运算核。
在一种实现方式中，所有分区11均为第一分区，如图7所示，分区111至分区11N均为第一分区，且分区111至分区11N中的内核H均为高性能运算核。
例如，对于均衡型多核芯片110，可以对所包括的内核H的数量进行均分，使得每个分区11中的内核H的数量相等。如图7所示，每个分区11中包括j个核。
在一种实现方式中，所有分区11中还包括至少一个第二分区，第二分区所包括的内核H为调度运算核，即多核芯片110的多个分区11中部分分区11中的内核H为调度运算核。
例如，如图8所示，分区111为第二分区且分区111中的内核H为调度运算核，分区112至分区11n为第一分区且分区112至分区11n中的内核H为高性能运算核。进一步地，如图8所示，多核芯片110内部只有一个核作为调度运算核，且其他核作为高性能运算核，则该多核芯片110中的调度运算核设置在一个分区11，其他所有高性能运算核平均分组设置在多个分区11中，例如，如图8所示，每个分区11中包括j个高性能运算核。
例如，如图9所示，分区111、分区11(n-1)为第二分区且分区111、分区11(n-1)中的内核H为调度运算核，其他分区中的内核H为高性能运算核且每个分区11中可以包括相同数量的j个高性能运算核。分区112至分区11n为第一分区且分区112至分区11n中的内核H为高性能运算核。
此外，如图9所示，当多核分区11中包括多个第二分区时，每个第二分区中的调度运算核的数量也可以相同，如每个第二分区中均包括1个调度运算核。
在本申请实施例中，如图7-图9所示，各个第一分区中的高性能运算核数量均相同。
图10为本申请实施例提供的一种芯片供电系统的剖面示意图，图11为本申请实施例提供的另一种芯片供电系统的剖面示意图。
在本申请的一个实施例中，如图10及图11所示，芯片供电系统10中的多个供电模块12可以设置在芯片封装结构的外侧。
在本实施例中，如图7及图8所示，芯片供电系统10还包括印刷电路板15，电源控制器13、供电模块12及多核芯片110可以均设置在印刷电路板15上，且电源控制器13通过印刷电路板15控制供电模块12进行电压转化，供电模块12通过印刷电路板15向多核芯片110输出电压。
此外，多核芯片110的一侧设置有多个供电触点110a，供电触点110a与印刷电路板15焊接，且供电触点110a通过印刷电路板15接收供电模块12输出的电压并且将接收到的电压传输给多核芯片110中的内核H。
进一步地，多个供电触点110a被分成多个供电触点组，每个供电触点组包括至少一个供电触点110a，多个供电触点组与多个分区11一一对应设置，供电触点组中的供电触点为该供电触点组所对应的分区中的内核H的供电触点。则供电模块12通过印刷电路板15向多核芯片110输出电压，具体为，供电模块12通过与印刷电路板15与对应的供电触点组中的供电触点110a电连接为对应分区11中的内核H输出所需的电压。
在一种实现方式中，供电模块12通过印刷电路板15中的导通孔或者盲孔与对应的供电触点组中的供电触点110a电连接。例如，如图10所示，供电模块12与多核 芯片110分别设置在印刷电路板15的相对两侧，且供电模块12与多个芯片110中的供电触点110a电连接。
在另一种实现方式中，如图11所示，芯片供电系统10还包括至少一个铜片14，铜片14的至少部分贴在印刷电路板15背离多核芯片110的一侧。其中，至少部分供电触点组中的供电触点110a通过铜片14与对应的供电模块12电连接。
在多核芯片110的性能提升时导致所需的供电电压增加，芯片供电系统的散热也是亟待解决的问题，本申请通过在绑定了多核芯片110的印刷电路板15的背面设置铜片14，可以加快芯片供电系统的散热。并且，通过铜片14电连接部分供电模块与供电触点110a，可以减小印刷电路板15中通孔和/或盲孔的数量，并且减小印刷电路板15的层数及设计难度。
此外，通过铜片14与供电模块12电连接的供电触点110a所对应的分区11中的内核H可以为高性能运算核。
在一种具体的技术方案中，部分分区11对应的供电触点110a通过印刷电路板15中的导通孔或者盲孔与对应的供电模块12电连接，另一个部分分区11对应的供电触点110a通过铜片14与对应的供电模块12电连接。
在本申请的一个实施例中，芯片供电系统10中的多个供电模块12也可以设置在芯片封装结构的内侧。
图12为本申请实施例提供的再一种芯片供电系统的供电示意图，图13为本申请实施例提供的还一种芯片供电系统的供电示意图。
在本申请实施例中，供电模块12中可以包括一相供电电路120，也可以包括多相供电电路120。
需要说明的是，如图12所示，各个供电模块12中可以分别包括一相供电电路120，或者，各个供电模块12中可以包括相同的多相供电电路120。
此外，如图13所示，对于包含高性能运算内核H的分区11所对应的供电模块12中可以包含多相供电电路120，包含调度运算内核H的分区11所对应的供电模块12中可以包含单相供电电路120。
图14为本申请实施例提供的一种芯片供电方法的流程图。
本申请实施例还提供一种芯片的供电方法，用于对上述任意一个实施例提供的芯片供电系统中的多核芯片进行供电，如图14所示，该供电方法包括：
S1：接收多核芯片的供电业务调度指令，根据供电业务调度指令确定多核芯片的各个分区中的内核所需的电压。
电源控制器与多核芯片之间进行通信，多核芯片向电源控制器发送供电业务调度指令，说明其各个分区所需的电压；电源控制器根据所接收的供电业务调度指令确定多核芯片的各个分区中的内核所需的电压。
S2：根据确定的多核芯片的各个分区的内核所需的电压，控制各个分区分别对应的供电模块将接收的电压转换为其所对应的分区中内核所需的电压。
电源控制器接收到给多核芯片进行供电的供电业务调度指令后，开启分区供电模式，即控制多个供电模块开启，并控制供电模块将电源控制器输出的电压调整为对应 分区中的内核所需的电压。
若电源控制器接收到的供电业务调度指令为对全部内核进行调压的指令，则开启所有的供电模块，并控制所有的供电模块将接收的电压进行转换。被供电模块转换调整后的电压提供给多核芯片各个分区中的内核。
若单板管理系统接收到的供电业务调度指令为对部分内核进行调压的指令，则开启该些内核所在分区对应的供电模块，并控制该些供电模块将接收的电压进行转换。被供电模块转换调整后的电压提供给多核芯片的部分分区中的内核。此外，根据供电业务调度指令，确定其他分区中的内核所需的电压不变且对应的供电模块状态不变，则可以控制其他不需要调压的内核所在分区对应的供电模块的状态不变。
需要说明的是，供电模块中可以包括晶体管，则控制各个分区分别对应的供电模块将接收的电压转换为其所对应的分区中内核所需的电压是指，电源控制器控制各个供电模块中的晶体管的开启时间，晶体管不同的开启时间所转换得到的电压不同。
图15为本申请实施例提供的另一种芯片供电方法的流程图。
此外，如图15所示，本申请实施例提供的芯片供电方法还包括：
S3：监测多核芯片的各个分区中的内核的占用率及多核芯片的功耗和/或温度。
分区中的内核的占用率能够说明内核的运算状态，如监测到某些分区中的内核的占用率达到阈值，说明该些内核始终处于高性能运算。则在条件允许的情况下可以对该些始终处于高性能运算的内核进行超频，提高多核芯片的性能。
多核芯片的功耗及温度可以反应此时多核芯片是否具备超频条件。若多核芯片的功耗或温度达到极限，则不可以对多核芯片进行超频；若多核芯片的功耗及温度未超过极限，则可以启动超频。
S4：判断监测到的芯片的各个分区中的内核的占用率、多核芯片的功耗和/或温度是否超过阈值；
若至少一个分区中的内核的占用率达到阈值且多核芯片的功耗和/或温度未达到阈值，则控制该至少一个分区所对应的供电模块调高输出的电压。
对监测到的各个分区中的内核的占用率及多核芯片的功耗和/或温度进行数据进行分析判断。
若多核芯片中某些分区的内核的占用率达到阈值或者已经超过了阈值且多核芯片的功耗及温度未达到阈值，则可以对该些分区的内核进行超频；并且在超频前控制该些分区对应的供电模块调高输出电压。
此外，在超频的过程中及超频之后仍然需要实时检测多核芯片的功耗和温度，如果功耗或温度达到阈值，就停止继续超频。比如某一分区中内核的基频是3GHz，在该分区中的内核超频到3.3GHz，多核芯片的功耗及温度未达到极限，则可以对该分区中的内核继续超频；当该分区中的内核超频到3.6GHz时，多核芯片的功耗和温度临近阈值，就停止对该分区中的内核继续超频；并且该分区中的内核以3.6GHz主频进行高性能运算，此时已超频的内核的功耗会比不超频时大很多。
若至少一个分区中的内核的占用率未达到阈值且多核芯片的功耗和/或温度未达到阈值，则根据供电业务调度指令确定该至少一个分区中的内核所需的电压。
对监测到的各个分区中的内核的占用率及多核芯片的功耗和/或温度进行数据进行分析判断。
若多核芯片中某些分区的内核的占用率未达到阈值，在多核芯片的功耗和/或温度未到达阈值的前提下，可以根据供电业务调度指令确定多核芯片的各个分区中的内核所需的电压。
此外，在超频的过程中，如果多核芯片中存在无需超频的内核，在可以把该些内核的主频降下来或者将其置于闲置状态。
图16为本申请实施例提供的又一种芯片供电方法的流程图。以下结合图16对本申请实施例提供的芯片供电方法进行系统介绍。
首先，由于芯片供电系统根据多核芯片中多个内核的性能对多个内核进行了分区且同一分区中的内核的运算类型相同，则芯片供电系统首先根据内核的运算类型初始化分区供电，芯片供电系统的供电进入常规状态。
当多核芯片中的内核的运算性能发生变化时，电源控制器接收到多核芯片的供电业务调度指令，且电源控制器控制多个供电模块的输出电压大小，即根据供电业务调度指令调整所有分区内的内核的电压，保证多核芯片中的内核完成运算。当多核芯片中的内核完成运算后，电源控制器会再次接收到多核芯片的供电业务调度指令，芯片供电系统再次根据内核的运算类型初始化分区供电，芯片供电系统的供电再次进入常规状态。
当芯片供电系统的供电处于常规状态时，多核芯片实时或者定时监测各个分区中内核的占用率及多核芯片的功耗及温度。
若分区中的内核的占用率未超过阈值，则多核芯片保持实时或者定时监测各个分区中内核的占用率及多核芯片的功耗及温度。
若分区中的内核的占用率超过阈值且多核芯片的功耗与温度未超过阈值时，说明需要对该分区中的内核进行超频且多核芯片能够进行超频，则调高超频分区内的内核的电压，保证超频分区内的内核能够完成超频，进而能够实现高性能运算。当多核芯片中的内核完成运算后，电源控制器会再次接收到多核芯片的供电业务调度指令，芯片供电系统再次根据内核的运算类型初始化分区供电，芯片供电系统的供电再次进入常规状态。
此外，在调高超频分区内的内核的电压时，可以同时调低非超频分区内的电压或者将非超频分区内的内核的状态调整为闲置，减小多核芯片的功耗。
本申请实施例还提供一种电子设备，该电子设备包括本申请提供的芯片供电系统。该电子设备可以是终端，例如，个人计算机、手机、掌上电脑、可穿戴电子设备、车载设备等。该电子设备还可以是网络设备，例如，交换机、路由器、防火墙、基站、无线接入点、无线控制器等。该电子设备还可以是存储设备，例如存储服务器、存储阵列等。该电子设备还可以是提供高性能计算的设备。本申请中的各个实施方式可以在不冲突的前提下相互组合，并取得相应的技术效果。
此外，本申请实施例还提供一种计算机可读存储介质，其中，该计算机可读存储介质包括存储程序，在存储程序运行时控制计算机存储介质所在电子设备执行上述任 意一个实施例的方法。该存储介质可为磁碟、光盘、只读存储记忆体(read-only memory，ROM)或随机存储记忆体(random access memory，RAM)等。
本领域的技术人员可以清楚地了解到本发明实施例中的技术可借助软件加必需的通用硬件平台的方式来实现。基于这样的理解，本发明实施例中的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例或者实施例的某些部分所述的方法。
以上所述，仅为本申请的具体实施方式，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种芯片供电系统，其特征在于，包括：
    多核芯片，所述多核芯片包括N个分区，各个所述分区中均包括至少一个内核；所述N个分区的至少部分分区中，每个所述分区包括至少两个所述内核；
    N个供电模块，所述N个供电模块与所述N个分区一一对应设置；
    至少一个电源控制器，所述电源控制器与至少一个所述供电模块连接，且所述电源控制器用于控制其所连接的供电模块将接收到的电压转换为所述内核所需的电压；
    其中，所述供电模块的输出端与其所对应的所述分区中的所述内核电连接，所述供电模块用于将其所接收的电压转换为其所对应的所述分区中所述内核所需的电压。
  2. 根据权利要求1所述的芯片供电系统，其特征在于，所述芯片的一侧包括多个供电触点，任意一个所述分区中所述内核对应的所述供电触点形成一个供电触点组；
    所述供电模块的输出端与其所对应的所述分区的所述供电触点组中的所述供电触点电连接。
  3. 根据权利要求2所述的芯片供电系统，其特征在于，所述芯片供电系统还包括：
    印刷电路板，所述多核芯片设置在所述印刷电路板的一侧且与所述印刷电路板电连接；
    至少一个铜片，所述铜片的至少部分贴附在所述印刷电路板背离所述多核芯片的一侧；
    其中，至少部分所述供电触点组中的所述供电触点通过所述印刷电路板的通孔及所述铜片与对应的所述供电模块电连接。
  4. 根据权利要求3所述的芯片供电系统，其特征在于，部分所述供电触点组中的所述供电触点通过所述印刷电路板中的导通孔或者盲孔与对应的所述供电模块电连接，另一个部分所述供电触点组中的所述供电触点通过所述铜片与对应的所述供电模块电连接。
  5. 根据权利要求1所述的芯片供电系统，其特征在于，所述N个分区中包括第一分区和第二分区，所述第一分区中所述内核的额定电压均为第一电压，所述第二分区中所述内核的额定电压均为第二电压；所述第一电压大于所述第二电压。
  6. 根据权利要求5所述的芯片供电系统，其特征在于，所述第一分区中各所述内核的最高运算频率大于所述第二分区各所述内核的最高运算频率。
  7. 根据权利要求6所述的芯片供电系统，其特征在于，所述N个分区中包括至少两个所述第一分区，各个所述第一分区中所述内核的数量均相同。
  8. 根据权利要求6所述的芯片供电系统，其特征在于，所述N个分区中包括至少两个所述第二分区，各个所述第二分区中所述内核的数量均相同。
  9. 根据权利要求1所述的芯片供电系统，其特征在于，所述芯片供电系统包括至少两个所述电源控制器，所述至少两个电源控制器分别与不同的所述供电模块电连接。
  10. 根据权利要求9所述的芯片供电系统，其特征在于，所述至少两个所述电源控制器包括第一电源控制器和第二电源控制器；
    所述第一电源控制器电连接的所述供电模块中，各个所述供电模块对应的所述分 区中的所述内核的额定电压为第一电压；
    所述第二电源控制器电连接的所述供电模块中，各个所述供电模块对应的所述分区中的所述内核的额定电压为第二电压，所述第一电压大于所述第二电压。
  11. 一种芯片的供电方法，其特征在于，用于对权利要求1-10任意一项所述的芯片供电系统中的所述多核芯片进行供电；所述方法包括：
    接收多核芯片的供电业务调度指令，根据所述供电业务调度指令确定所述多核芯片的各个分区中的内核所需的电压；
    根据确定的所述多核芯片的各个分区的内核所需的电压，控制各个所述分区分别对应的所述供电模块将接收的电压转换为其所对应的所述分区中所述内核所需的电压。
  12. 根据权利要求11所述的方法，其特征在于，所述方法还包括：
    监测所述多核芯片的各个分区中的所述内核的占用率及所述多核芯片的功耗和/或温度；
    判断监测到的所述芯片的各个分区中的所述内核的占用率、所述多核芯片的功耗和/或温度是否超过阈值；
    若至少一个所述分区中的所述内核的占用率达到阈值且所述多核芯片的功耗和/或温度未达到阈值，则控制该所述至少一个所述分区所对应的所述供电模块调高输出的电压。
  13. 根据权利要求12所述的方法，其特征在于，若至少一个所述分区中的所述内核的占用率未达到阈值且所述多核芯片的功耗和/或温度未达到阈值，则根据所述供电业务调度指令确定该至少一个所述分区中的所述内核所需的电压。
  14. 一种电子设备，其特征在于，包括如权利要求1-10任意一项所述的芯片供电系统。
  15. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质包括存储程序，其中，在所述存储程序运行时控制所述计算机存储介质所在设备执行权利要求11-13任意一项所述的方法。
PCT/CN2022/097431 2021-08-30 2022-06-07 芯片供电系统及方法、电子设备、计算机可读存储介质 WO2023029635A1 (zh)

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