WO2023024808A1 - 译码驱动电路及存储芯片 - Google Patents

译码驱动电路及存储芯片 Download PDF

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Publication number
WO2023024808A1
WO2023024808A1 PCT/CN2022/108164 CN2022108164W WO2023024808A1 WO 2023024808 A1 WO2023024808 A1 WO 2023024808A1 CN 2022108164 W CN2022108164 W CN 2022108164W WO 2023024808 A1 WO2023024808 A1 WO 2023024808A1
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Prior art keywords
power supply
signal
decoding
transistor
sub
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PCT/CN2022/108164
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English (en)
French (fr)
Inventor
尚为兵
武贤君
李明浩
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP22860154.8A priority Critical patent/EP4276830A4/en
Priority to US18/155,079 priority patent/US20230170011A1/en
Publication of WO2023024808A1 publication Critical patent/WO2023024808A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Definitions

  • the present disclosure relates to the field of integrated circuits, in particular to a decoding drive circuit and a memory chip.
  • a semiconductor memory chip usually includes a memory array area and a peripheral circuit area, wherein the memory array area is provided with a memory cell array including a plurality of memory cells, and the peripheral circuit area is provided with a control circuit for controlling reading and writing and a mode register for setting storage parameters .
  • the control circuit for controlling reading and writing includes a sense amplifier circuit, a data input and output conversion circuit, a row/column decoding circuit and its control circuit, etc.
  • the volume of the decoding drive circuit in the row decoding circuit can be reduced without reducing the storage capacity of the memory array area, it will undoubtedly be able to effectively reduce the volume of the peripheral circuit area of the semiconductor memory chip, thereby relatively improving the performance of the semiconductor memory chip. Storage capacity per unit area.
  • a decoding driving circuit and a memory chip are provided.
  • the present disclosure provides a decoding driving circuit on the one hand, including a plurality of sub-driving units and a decoding control module, and the sub-driving units are used to output signals according to a power supply voltage signal, a first decoding input signal, and an intermediate decoding output signal.
  • the decoding control module is connected with a plurality of sub-driving units, and is used to generate an intermediate decoding output signal according to the enable control signal and the second decoding input signal; wherein, the intermediate decoding output signal is the first During the state, the main word line driving signal is in a non-driving state.
  • the sub-drive unit includes a first transistor, a second transistor, and a third transistor.
  • the first transistor is configured as follows: the source is connected to the power supply voltage signal, and the gate is connected to the first decoding input signal; the second transistor It is configured as: the source is connected to the power supply voltage signal, and the gate is connected to the intermediate decoding output signal; the third transistor is configured as: the source is connected to the decoding control module, and the drain is connected to the drain of the first transistor and the second The drains of the transistors are all connected, and the gate is connected with the gate of the first transistor and the first decoding input signal.
  • the first transistor and the third transistor by setting the first transistor and the third transistor to form an inverter whose control end is connected to the first decoding input signal, and the output end of the inverter is connected to the output end of the second transistor, and the second transistor
  • the control terminal of the control terminal is connected to the intermediate decoding output signal and the input terminal is connected to the power supply voltage signal, so that the sub-drive unit generates the main word line driving signal according to the power supply voltage signal, the first decoding input signal and the intermediate decoding output signal, so as to realize the utilization
  • a decoding control module controls multiple sub-drive units to realize the control of multiple local word line drive circuits.
  • the enable control signal includes a first enable control signal and a second enable control signal
  • the decoding control module includes a first inverter, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor and the second decoding signal receiving unit
  • the first inverter is configured as: the power supply end is connected to the first power supply, the output end is connected to the gate of the second transistor
  • the fourth transistor is configured as: the source is grounded, and the drain It is connected to the source of the third transistor, the gate is connected to the gate of the second transistor and the output terminal of the first inverter
  • the fifth transistor is configured as follows: the source is connected to the first power supply, and the drain is connected to the first The input end of the inverter is connected, and the gate is connected to the output end of the first inverter and the gate of the second transistor
  • the sixth transistor is configured as: the source is connected to the first power supply, and the drain is connected to the first inverter The input terminal of the phase switch and the drain of the fifth transistor are both connected,
  • the second decoding input signal includes a second main decoding input signal and a second auxiliary decoding input signal
  • the second decoding signal receiving unit includes an eighth transistor and a ninth transistor, and the eighth transistor is configured as : the drain is connected to the source of the seventh transistor, the gate is connected to the second main decoding input signal; the ninth transistor is configured as: the source is grounded, the drain is connected to the source of the eighth transistor, and the gate is connected to the second The second decoding input signal connection.
  • the decoding drive circuit further includes an enabling control module, which is connected to multiple decoding control modules, and is used to provide the first enable to the multiple decoding control modules according to the main word line enable signal. a control signal and a second enabling control signal.
  • the enable control module includes a second inverter, a third inverter, and a fourth inverter
  • the second inverter is configured as follows: the input terminal is connected to the main word line enable signal, and the power supply terminal connected to the first power supply;
  • the third inverter is configured as follows: the input terminal is connected to the output terminal of the second inverter, the power supply terminal is connected to the first power supply, and the output terminal outputs the first enable control signal;
  • the fourth inverter The inverter is configured as follows: the input terminal is connected to the output terminal of the second inverter, the power supply terminal is connected to the second power supply, and the output terminal outputs the second enabling control signal.
  • the magnitude of the output voltage of the first power supply is greater than the magnitude of the output voltage of the second power supply.
  • the decoding drive circuit further includes a power control module, which is connected to each sub-drive unit and used to provide a power supply voltage signal to each sub-drive unit; wherein, the power control module is also used to output Power supply voltage signals with different voltage amplitudes.
  • the power control signal includes a first sub-power control signal and a second sub-power control signal
  • the power control module includes a first power control unit and a second power control unit, and the first power control unit communicates with the third power supply, the second power supply Both the first sub-power supply control signal and the second sub-power supply control signal are connected, and are used to generate a power supply voltage signal with a first amplitude according to the first sub-power supply control signal and the second sub-power supply control signal; the second power supply control unit and the first sub-power supply control unit The power supply and the inversion signal connection of the second sub-power supply control signal are used to generate a power supply voltage signal with a second amplitude according to the inversion signal of the second sub-power supply control signal.
  • the power control module further includes a third power control unit, the third power control unit is connected to the first power supply and the inversion signal of the first sub-power control signal, and is used to control the signal according to the inversion of the first sub-power supply.
  • the signal generates a supply voltage signal having a third magnitude.
  • the first power supply control unit includes a tenth transistor and an eleventh transistor, and the tenth transistor is configured as follows: the source is connected to the third power supply, and the gate is connected to the first sub-power supply control signal; the eleventh transistor The configuration is as follows: the source is connected to the drain of the tenth transistor, the gate is connected to the second sub-power supply control signal, and the drain outputs a power supply voltage signal with a first amplitude.
  • the second power supply control unit includes a twelfth transistor and a thirteenth transistor, and the twelfth transistor is configured as follows: the source is connected to the first power supply, and the gate is connected to the drain; the thirteenth transistor is configured The source is connected to the drain of the twelfth transistor, the gate is connected to the inverted signal of the second sub-power supply control signal, and the drain outputs a power supply voltage signal with a second amplitude.
  • the third power supply control unit includes a fourteenth transistor, and the fourteenth transistor is configured as follows: the source is connected to the first power supply, the gate is connected to the inverted signal of the first sub-power supply control signal, and the drain outputs A supply voltage signal having a third magnitude.
  • the magnitude of the output voltage of the third power supply is smaller than the magnitude of the output voltage of the first power supply; the first magnitude is greater than the second magnitude, and the second magnitude is greater than the third magnitude.
  • another aspect of the present disclosure provides a memory chip, including any decoding driving circuit in any embodiment of the present disclosure.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • the decoding control module is set to connect with multiple sub-drive units, and the decoding control module is set to generate intermediate decoding according to the enable control signal and the second decoding input signal.
  • the code output signal is provided to each sub-drive unit, so that each sub-drive unit generates a main word line drive signal according to the power supply voltage signal, the first decoding input signal and the intermediate decoding output signal, and the main word line drive signal is related to the word
  • the line driving signal and the word line reset signal together realize the control of multiple local word line driving circuits in the row decoding circuit.
  • a decoding control module is used to control multiple sub-drive units to control multiple local word line drive circuits, and the row decoding circuit can be reduced without reducing the storage capacity of the memory array area.
  • the volume of the decoding driving circuit is reduced to effectively reduce the volume of the peripheral circuit area of the semiconductor memory chip, so that the storage capacity per unit area of the semiconductor memory chip can be relatively increased.
  • the decoding driving circuit and the memory chip provided by the embodiments of the present disclosure can reduce the volume of the decoding driving circuit in the row decoding circuit without reducing the storage capacity of the memory array area.
  • FIG. 1 is a structural block diagram of a decoding driving circuit provided in an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of the circuit principle of the i-th sub-drive unit in a decoding drive circuit provided in an embodiment of the present disclosure, where 1 ⁇ i ⁇ n, i and n are both positive integers, and n is the number of the sub-drive unit. quantity;
  • FIG. 3 is a schematic circuit schematic diagram of a decoding control module in a decoding driving circuit provided in an embodiment of the present disclosure
  • FIG. 4 is a structural block diagram of a decoding driving circuit provided in another embodiment of the present disclosure.
  • FIG. 5 is a schematic circuit schematic diagram of an enabling control module in a decoding drive circuit provided in an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a circuit principle of a power control module in a decoding drive circuit provided in an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a circuit principle of a local word line driving circuit provided in an embodiment of the present disclosure.
  • connection is intended to mean an indirect or direct electrical connection. Accordingly, if one device is connected to another device, the connection may be through a direct electrical connection, or through an indirect electrical connection through other devices and connections.
  • first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.
  • a decoding driving circuit 100 including a first sub-driving unit 21, an i-th sub-driving unit 2i, an n-th sub-driving unit 2n, and a decoding control module.
  • the i-th sub-driver unit 2i is used to generate the main word line drive signal according to the power supply voltage signal, the first decoding input signal Intp1 and the intermediate decoding output signal MIntp; the decoding control module 10 and the first sub-driver unit 21 , the i-th sub-drive unit 2i and the n-th sub-drive unit 2n are all connected to generate an intermediate decoding output signal MIntp according to the enable control signal and the second decoding input signal; wherein, the intermediate decoding output signal MIntp is the first During a state period, the main word line driving signal is in a non-driving state.
  • the first sub-driver unit 21 generates the main word line drive signal bMWL0 according to the power supply voltage signal, the first decoded input signal Intp1 and the intermediate decoded output signal MIntp, and the i-th sub-driver unit 2i generates the main word line drive signal bMWL0 according to the power supply voltage signal, the first decoded input signal Intp1 and the intermediate decoding output signal MIntp generate the main word line driving signal bMWLi-1, and the nth sub-driver unit 2n generates the main word line driving signal bMWLn according to the power supply voltage signal, the first decoding input signal Intp1 and the intermediate decoding output signal MIntp -1.
  • 1 ⁇ i ⁇ n, i and n are both positive integers, and n is the number of sub-drive units.
  • each sub-drive unit generates a main word line drive signal according to the power supply voltage signal, the first decoding input signal Intp1 and the intermediate decoding output signal MIntp, the main word line drive signal and the word line drive signal and The word line reset signal realizes the control of a plurality of local word line driving circuits in the row decoding circuit together, and the intermediate decoding output signal MIntp can be set as the first state period, and the main word line driving signal is in a non-driving state, so that the subsequent The word line correspondingly connected to the stage remains inactive; and during the period when the intermediate decoding output signal MIntp is set to the second state, the main word line driving signal is in the driving state to drive
  • a decoding control module 10 is used to control multiple sub-drive units to control multiple local word line drive circuits, which can reduce the row decoding without reducing the storage capacity of the memory array area.
  • the volume of the decoding drive circuit 100 in the circuit can effectively reduce the volume of the peripheral circuit area of the semiconductor memory chip, so that the storage capacity per unit area of the semiconductor memory chip can be relatively increased.
  • the i-th sub-driver unit 2i includes a first transistor M1, a second transistor M2 and a third transistor M3, and the first transistor M1 is configured as follows: the source is connected to the power supply voltage signal PbMWL, and the gate The pole is connected to the first decoding input signal Intp1; the second transistor M2 is configured as: the source is connected to the power supply voltage signal PbMWL, and the gate is connected to the intermediate decoding output signal MIntp; the third transistor M3 is configured as: the source is connected to The decoding control module 10 is connected, the drain is connected to the drain of the first transistor M1 and the drain of the second transistor M2, the gate is connected to the gate of the first transistor M1 and the first decoding input signal Intp1, 1 ⁇ i ⁇ n, i and n are both positive integers, and n is the number of sub-drive units.
  • the gate of the second transistor M2 is connected to the intermediate decoding output signal MIntp and the input end is connected to the power supply voltage signal, so that the correspondingly connected sub-drive unit 20
  • the output signal MIntp generates a main wordline driving signal to drive the wordlines connected to the subsequent stage, so that a decoding control module 10 can be used to control multiple sub-driving units 20 to realize the control of multiple local wordline driving circuits.
  • the enable control signal can be set to include a first enable control signal EN1 and a second enable control signal EN2;
  • the decoding control module 10 includes a first inverter (not shown), a fourth The transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the second decoding signal receiving unit 11,
  • the first inverter is configured as follows: the power supply terminal is connected to the first power supply VDD1, and the output terminal is connected to the second The gate of the transistor M2 is connected;
  • the fourth transistor M4 is configured as follows: the source is grounded, the drain is connected to the source of the third transistor M3, the gate is connected to the gate of the second transistor M2 and the output terminal of the first inverter are connected;
  • the fifth transistor M5 is configured as follows: the source is connected to the first power supply VDD1, the drain is connected to the input terminal of the first inverter, the gate is connected to the output terminal of the first inverter and the second transistor M2
  • the gates are all connected;
  • the sixth transistor M6 is configured
  • the control signal EN1 can be connected; the seventh transistor M7 is configured as follows: the source is connected to the second decoding signal receiving unit 11, the drain is connected to the drain of the sixth transistor M6 and the input terminal of the first inverter, and the gate The pole is connected to the second enable control signal EN2.
  • the decoding control module 10 provides a corresponding intermediate decoding output signal to the sub-drive unit 20 connected to the subsequent stage according to the first enabling control signal EN1, the second enabling control signal EN2 and the signal provided by the second decoding signal receiving unit 11 MIntp, so that the sub-driving unit can generate a main word line driving signal according to the power supply voltage signal PbMWL, the first decoding input signal Intp1 and the intermediate decoding output signal MIntp, so as to drive the word line connected to the subsequent stage.
  • This embodiment can realize that during the period when the intermediate decoding output signal MIntp is in the first state, the main word line driving signal output by each sub-drive unit 20 connected to the subsequent stage is driven to the non-driving state, so that the correspondingly connected word line of the subsequent stage remains inactive. Active state; and when the intermediate decoding output signal MIntp is in the second state, drive the main word line drive signal output by each sub-drive unit 20 connected to the subsequent stage to be in the drive state, so as to drive the word line correspondingly connected to the subsequent stage to maintain the active state .
  • the first inverter may be set to include a transistor Q1 and a transistor Q2, the transistor Q1 is configured as follows: the source is connected to the first power supply VDD1, the gate is connected to the drain of the fifth transistor M5; Q2 is configured as follows: the source is grounded, the drain is connected to the drain of the transistor Q1 and serves as an output terminal of the first inverter, and the gate is connected to the gate of the transistor Q1 and serves as an input terminal of the first inverter.
  • the second decoding input signal includes a second main decoding input signal Intp2 and a second secondary decoding input signal Intp3;
  • the second decoding signal receiving unit 11 includes an eighth transistor M8 and a ninth transistor M8
  • the transistor M9 and the eighth transistor M8 are configured as: the drain is connected to the source of the seventh transistor M7, and the gate is connected to the second main decoding input signal Intp2;
  • the ninth transistor M9 is configured as: the source is grounded, and the drain It is connected to the source of the eighth transistor M8, and the gate is connected to the second sub-decoding input signal Intp3.
  • the second decoding signal receiving unit 11 provides the source signal to the seventh transistor M7 according to the second main decoding input signal Intp2 and the second sub-decoding input signal Intp3, and cooperates with the first enable control signal EN1 and the second enable control signal
  • the signal EN2 controls the actions of the sixth transistor M6 and the seventh transistor M7 to provide a driving signal to the subsequent circuit, so that the decoding control module 10 provides a corresponding intermediate decoding output signal to the sub-driver unit 20 connected to the subsequent stage, so that the sub-driver
  • the unit 20 can generate a main word line driving signal according to the power supply voltage signal PbMWL, the first decoded input signal Intp1 and the intermediate decoded output signal MIntp, so as to drive the word line connected to the subsequent stage.
  • the decoding driving circuit 100 further includes an enabling control module 30, which is connected to a plurality of decoding control modules 10, and is used to provide a plurality of decoding functions according to the main word line enabling signal bMWLEn.
  • the code control module 10 provides a first enable control signal EN1 and a second enable control signal EN2.
  • the enable control module 30 includes a second inverter Inv2, a third inverter Inv3 and a fourth inverter Inv4, and the second inverter Inv2 is configured as: the input terminal and the main word The line enable signal bMWLEn is connected, the power supply terminal is connected to the first power supply VDD1;
  • the third inverter Inv3 is configured as follows: the input terminal is connected to the output terminal of the second inverter Inv2, the power supply terminal is connected to the first power supply VDD1, and the output terminal outputs the first enable control signal EN1;
  • the fourth inverter Inv4 is configured as follows: the input terminal is connected to the output terminal of the second inverter Inv2, the power supply terminal is connected to the second power supply VDD2, and the output terminal outputs the second enable Control signal EN2.
  • the amplitude of the output voltage of the first power supply VDD1 may be set to be greater than the amplitude of the output voltage of the second power supply VDD2.
  • the amplitude of the output voltage of the first power supply VDD1 can be set to 3V, and the amplitude of the output voltage of the second power supply VDD2 can be set to 1.6V.
  • the decoding drive circuit 100 also includes a power control module 40, the power control module 40 is connected to each sub-drive unit, and is used to provide a power supply voltage signal to each sub-drive unit; wherein, the power control module 40 also It is used to output power supply voltage signals with different voltage amplitudes according to the power supply control signal.
  • the power control signal can be set to include a first sub-power control signal Sel1 and a second sub-power control signal Sela;
  • the power control module 40 includes a first power control unit 41 and a second power control unit 42,
  • the first power supply control unit 41 is connected to the third power supply VDD3, the first sub-power supply control signal Sel1 and the second sub-power supply control signal Sela, and is used for generating The power supply voltage signal of the first magnitude;
  • the second power supply control unit 42 is connected with the first power supply VDD1 and the inversion signal Selb of the second sub-power supply control signal, and is used to generate the inversion signal Selb according to the second sub-power supply control signal.
  • the first power supply control unit 41 may be set to include a tenth transistor M10 and an eleventh transistor M11, and the tenth transistor M10 is configured such that the source is connected to the third power supply VDD3, and the gate is connected to the third power supply VDD3.
  • a sub-power supply control signal Sel1 is connected; the eleventh transistor M11 is configured as follows: the source is connected to the drain of the tenth transistor M10, the gate is connected to the second sub-power supply control signal Sela, and the drain output has a first amplitude supply voltage signal.
  • the second power control unit 42 may be set to include a twelfth transistor M12 and a thirteenth transistor M13, and the twelfth transistor M12 is configured as follows: the source is connected to the first power supply VDD1, and the gate connected to the drain; the thirteenth transistor M13 is configured as follows: the source is connected to the drain of the twelfth transistor M12, the gate is connected to the inverted signal Selb of the second sub-power supply control signal, and the output of the drain has a second amplitude value of the supply voltage signal.
  • the amplitude of the output voltage of the first power supply VDD1 can be set to 3V
  • the amplitude of the output voltage of the third power supply VDD3 can be set to 1.8V, so that the first power control unit 41 can output a power supply of 3v-Vt voltage signal, and the second power supply control unit 42 can output a power supply voltage signal of 1.8v.
  • the power control module 40 may be set to further include a third power control unit 43, and the third power control unit 43 is connected to the first power VDD1 and the inversion signal Sel2 of the first sub-power control signal, using A power supply voltage signal with a third amplitude is generated based on the inverted signal Sel2 of the first sub-power supply control signal.
  • the third power supply control unit 43 may be set to include a fourteenth transistor M14, and the fourteenth transistor M14 is configured as follows: the source is connected to the first power supply VDD1, and the gate is connected to the first sub-power supply control The inversion signal Sel2 of the signal is connected, and the drain outputs a power supply voltage signal with a third amplitude.
  • the amplitude of the output voltage of the first power supply VDD1 can be set to 3V, so that the third power supply control unit 43 can output a power supply voltage signal of 3V.
  • the amplitude of the output voltage of the third power supply VDD3 can be set to be smaller than the amplitude of the output voltage of the first power supply VDD1; the first amplitude is greater than the second amplitude, and the second amplitude is greater than the third amplitude value.
  • the amplitude of the output voltage of the first power supply VDD1 can be set to 3V
  • the amplitude of the output voltage of the third power supply VDD3 can be set to 1.8V
  • the first power supply control unit 41 can output a power supply voltage signal of 3v-Vt
  • the control unit 42 can output a power supply voltage signal of 1.8v
  • the third power supply control unit 43 can output a power supply voltage signal of 3v.
  • the 3rd power control unit 43 can output the power supply voltage signal of 3v, reduce the power consumption of frequently switching power supply voltage signal;
  • power control module 40 drive circuit is in standby state , can control the first power supply control unit 41 to be able to output the power supply voltage signal of 3v-Vt, while reducing power consumption, prepare for the working power consumption of the drive circuit;
  • the second power supply control unit 42 can be controlled to output a power supply voltage signal of 1.8v, so as to reduce power consumption of the circuit.
  • the second sub-power control signal Sela can be set to be connected to the control circuit (not shown) through the inverter Inv5
  • the first sub-power control signal Sel1 can be set to be connected to the control circuit through the inverter Inv6. connected so that the control circuit can control the power control module 40 to output a power supply voltage signal of corresponding amplitude according to the actual working state of the drive circuit of the power control module 40, so as to reduce power consumption of the circuit.
  • the circuit of the local word line driver circuit includes a transistor Q3, a transistor Q4 and a transistor Q5, and the transistor Q3 is configured as follows: the source is connected to the word line drive signal WLDV, and the gate The pole is connected to the main word line driving signal bMWL, the drain is connected to the word line WL; the transistor Q4 is configured as follows: the source is grounded, the drain is connected to both the drain of the transistor Q3 and the word line WL, and the gate is driven to the main word line The signal bMWL is connected; the transistor Q5 is configured as: the source is grounded, the drain is connected to the drain of the transistor Q3, the drain of the transistor Q4 and the word line WL, and the gate is connected to the word line reset signal WLRst.
  • the circuit of the local word line driving circuit drives the state of the word line WL according to the main word line driving signal bMWL, the word line reset signal WLRst and the word line driving signal WLDV.
  • the main word line drive signal bMWL output by the decoding drive circuit is in an inactive state, so that the word line WL remains in an inactive state; and the intermediate decoding output signal is set to the second state
  • the main word line driving signal bMWL output by the decoding driving circuit is in a driving state to drive the word line WL to maintain an active state.
  • the word line driving signal WLDV and the word line reset signal WLRst involved in the above embodiments can be implemented by using relevant existing technologies, and the specific implementation principles will not be repeated in this disclosure.
  • the present disclosure provides a memory chip, including any decoding driving circuit in any embodiment of the present disclosure.
  • the decoding control module By setting the decoding control module to be connected to a plurality of sub-drive units, and setting the decoding control module to generate intermediate decoding output signals according to the enable control signal and the second decoding input signal and provide them to each sub-drive unit, so that each sub-drive
  • the unit generates the main word line driving signal according to the power supply voltage signal, the first decoding input signal and the intermediate decoding output signal, and the main word line driving signal, together with the word line driving signal and the word line reset signal, realize multiple
  • the control of the local word line driving circuit can set the intermediate decoding output signal to be in the first state period, and the main word line driving signal is in the non-driving state, so that the correspondingly connected word line of the subsequent stage remains inactive; and set the intermediate decoding When the code output signal is in the second state, the main word line driving signal is in the driving state to drive the correspondingly connected word line in the subsequent stage
  • a decoding control module is used to control multiple sub-drive units to control multiple local word line drive circuits, and the row decoding circuit can be reduced without reducing the storage capacity of the memory array area.
  • the volume of the decoding driving circuit is reduced to effectively reduce the volume of the peripheral circuit area of the semiconductor memory chip, so that the storage capacity per unit area of the semiconductor memory chip can be relatively increased.

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Abstract

本公开涉及一种译码驱动电路及存储芯片，译码驱动电路包括多个子驱动单元及译码控制模块，所述子驱动单元用于根据电源电压信号、第一译码输入信号和中间译码输出信号生成主字线驱动信号；所述译码控制模块与多个所述子驱动单元连接，用于根据使能控制信号及第二译码输入信号生成所述中间译码输出信号；其中，在所述中间译码输出信号为第一状态期间，所述主字线驱动信号为不驱动状态。本公开能够在不减少存储阵列区的存储容量的前提下，减小行译码电路中译码驱动电路的体积，以有效减小半导体存储芯片外围电路区的体积，从而能够相对提高半导体存储芯片单位面积的存储容量。

Description

译码驱动电路及存储芯片
相关申请的交叉引用
本公开要求于2021年08月25日提交中国专利局、申请号为202110981627.X、申请名称为“译码驱动电路及存储芯片”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及集成电路领域，特别是涉及一种译码驱动电路及存储芯片。
背景技术
随着半导体与集成电路技术的快速发展，市场对半导体存储芯片单位面积的存储容量的要求越来越高。
半导体存储芯片通常包括存储阵列区和外围电路区，其中，存储阵列区设置有包括多个存储单元的存储单元阵列，外围电路区设置有控制读写的控制电路和用于设置存储参数的模式寄存器。控制读写的控制电路包括感测放大电路、数据输入输出转换电路、行/列译码电路及其控制电路等。
如果能够在不减少存储阵列区的存储容量的前提下，减小行译码电路中译码驱动电路的体积，无疑能够有效减小半导体存储芯片外围电路区的体积，从而能够相对提高半导体存储芯片单位面积的存储容量。
发明内容
根据本公开的各种实施例，提供一种译码驱动电路及存储芯片。
根据一些实施例，本公开一方面提供一种译码驱动电路，包括多个子驱动单元及译码控制模块，子驱动单元用于根据电源电压信号、第一译码输入信号和中间译码输出信号生成主字线驱动信号；译码控制模块与多个子驱动单元连接，用于根据使能控制信号及第二译码输入信号生成中间译码输出信号；其中，在中间译码输出信号为第一状态期间，主字线驱动信号为不驱动状态。
根据一些实施例，子驱动单元包括第一晶体管、第二晶体管及第三晶体管，第一晶体管被配置为：源极与电源电压信号连接，栅极与第一译码输入信号连接；第二晶体管被配置为：源极与电源电压信号连接，栅极与中间译码输出信号连接；第三晶体管被配置为：源极与译码控制模块连接，漏极与第一晶体管的漏极及第二晶体管的漏极均连接，栅极与第一晶体管的栅极及第一译码输入信号均连接。本实施例中，通过设置第一晶体管与第三晶体管构成一控制端连接第一译码输入信号的反相器，且该反相器的输出端与第二晶体管的输出端连接，第二晶体管的控制端与中间译码输出信号连接且输入端与电源电压信号连接，使得子驱动单元根据电源电压信号、第一译码输入信号和中间译码输出信号生成主字线驱动信号，以实现利用一译码控制模块控制多个子驱动单元来实现对多个本地字线驱动电路的控制。
根据一些实施例，使能控制信号包括第一使能控制信号及第二使能控制信号；译码控制模块包括第一反相器、第四晶体管、第五晶体管、第六晶体管、第七晶体管及第二译码信号接收单元，第一反相器被配置为：电源端与第一电源连接，输出端与第二晶体管的栅极连接；第四晶体管被配置为：源极接地，漏极与第三晶体管的源极连接，栅极与第二晶体管的栅极及第一反相器的输出端均连接；第五晶体管被配置为：源极与第一电源连接，漏极与第一反相器的输入端连接，栅极与第一反相器的输出端及第二晶体管的栅极均连接；第六晶体管被配置为：源极与第一电源连接，漏极与第一反相器的输入端及第五晶体管的漏级均连接，栅极与第一使能控制信号连接；第七晶体管被配置为：源极与第二译码 信号接收单元连接，漏极与第六晶体管的漏极及第一反相器的输入端均连接，栅极与第二使能控制信号连接。
根据一些实施例，第二译码输入信号包括第二主译码输入信号及第二副译码输入信号；第二译码信号接收单元包括第八晶体管及第九晶体管，第八晶体管被配置为：漏极与第七晶体管的源极连接，栅极与第二主译码输入信号连接；第九晶体管被配置为：源极接地，漏极与第八晶体管的源极连接，栅极与第二副译码输入信号连接。
根据一些实施例，译码驱动电路还包括使能控制模块，使能控制模块与多个译码控制模块连接，用于根据主字线使能信号向多个译码控制模块提供第一使能控制信号及第二使能控制信号。
根据一些实施例，使能控制模块包括第二反相器、第三反相器及第四反相器，第二反相器被配置为：输入端与主字线使能信号连接，电源端与第一电源连接；第三反相器被配置为：输入端与第二反相器的输出端连接，电源端与第一电源连接，输出端输出第一使能控制信号；第四反相器被配置为：输入端与第二反相器的输出端连接，电源端与第二电源连接，输出端输出第二使能控制信号。
根据一些实施例，第一电源输出电压的幅值大于第二电源输出电压的幅值。
根据一些实施例，译码驱动电路还包括电源控制模块，电源控制模块与各子驱动单元连接，用于向各子驱动单元提供电源电压信号；其中，电源控制模块还用于根据电源控制信号输出不同电压幅值的电源电压信号。
根据一些实施例，电源控制信号包括第一子电源控制信号及第二子电源控制信号；电源控制模块包括第一电源控制单元及第二电源控制单元，第一电源控制单元与第三电源、第一子电源控制信号及第二子电源控制信号均连接，用于根据第一子电源控制信号及第二子电源控制信号生成具有第一幅值的电源电压信号；第二电源控制单元与第一电源及第二子电源控制信号的反相信号连接，用于根据第二子电源控制信号的反相信号生成具有第二幅值的电源电压信号。
根据一些实施例，电源控制模块还包括第三电源控制单元，第三电源控制单元与第一电源、第一子电源控制信号的反相信号连接，用于根据第一子电源控制信号的反相信号生成具有第三幅值的电源电压信号。
根据一些实施例，第一电源控制单元包括第十晶体管及第十一晶体管，第十晶体管被配置为：源极与第三电源连接，栅极与第一子电源控制信号连接；第十一晶体管被配置为：源极与第十晶体管的漏级连接，栅极与第二子电源控制信号连接，漏级输出具有第一幅值的电源电压信号。
根据一些实施例，第二电源控制单元包括第十二晶体管及第十三晶体管，第十二晶体管被配置为：源极与第一电源连接，栅极与漏级连接；第十三晶体管被配置为：源极与第十二晶体管的漏极连接，栅极与第二子电源控制信号的反相信号连接，漏级输出具有第二幅值的电源电压信号。
根据一些实施例，第三电源控制单元包括第十四晶体管，第十四晶体管被配置为：源极与第一电源连接，栅极与第一子电源控制信号的反相信号连接，漏极输出具有第三幅值的电源电压信号。
根据一些实施例，第三电源输出电压的幅值小于第一电源输出电压的幅值；第一幅值大于第二幅值，且第二幅值大于第三幅值。
根据一些实施例，本公开另一方面提供一种存储芯片，包括任一本公开实施例中的译码驱动电路。
本公开实施例可以/至少具有以下优点：
在本公开实施例提供的译码驱动电路及存储芯片中，通过设置译码控制模块与多个子驱动单元连接，并设置译码控制模块根据使能控制信号及第二译码输入信号生成中间译码 输出信号并提供给各子驱动单元，使得每一子驱动单元根据电源电压信号、第一译码输入信号和所述中间译码输出信号生成主字线驱动信号，主字线驱动信号与字线驱动信号及字线复位信号一起实现对行译码电路中多个本地字线驱动电路的控制。本实施例中实现了利用一译码控制模块控制多个子驱动单元来实现对多个本地字线驱动电路的控制，能够在不减少存储阵列区的存储容量的前提下，减小行译码电路中译码驱动电路的体积，以有效减小半导体存储芯片外围电路区的体积，从而能够相对提高半导体存储芯片单位面积的存储容量。
综上，本公开实施例提供的译码驱动电路及存储芯片，能够在不减少存储阵列区的存储容量的前提下，减小行译码电路中译码驱动电路的体积。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获取其他实施例的附图。
图1为本公开一实施例中提供的一种译码驱动电路的结构框图；
图2为本公开一实施例中提供的一种译码驱动电路中第i子驱动单元的电路原理示意图，其中，1≤i≤n，i、n均为正整数，n为子驱动单元的数量；
图3为本公开一实施例中提供的一种译码驱动电路中译码控制模块的电路原理示意图；
图4为本公开另一实施例中提供的一种译码驱动电路的结构框图；
图5为本公开一实施例中提供的一种译码驱动电路中使能控制模块的电路原理示意图；
图6为本公开一实施例中提供的一种译码驱动电路中电源控制模块的电路原理示意图；
图7为本公开一实施例中提供的一种本地字线驱动电路的电路原理示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
另外，贯穿说明书和跟随的权利要求中所使用的某些术语指代特定元件。本领域的技术人员会理解为，制造商可以用不同的名字指代元件。本文件不想要区分名字不同但是功能相同的元件。在以下的描述和实施例中，术语“包含”和“包括”都是开放式使用的，因此应该解读为“包含，但不限于……”。同样，术语“连接”想要表达间接或直接的电气连接。相应地，如果一个设备被连接到另一个设备上，连接可以通过直接的电气连接完成，或者通过其他设备和连接件的间接电气连接完成。
应当理解，尽管本文可以使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件和另一个元件区分开。例如，在不脱离本公开的范围的情况下，第一元件可以被称为第二元件，并且类似地，第二元件可以被称为第一元件。
请参考图1，在本公开的一个实施例中，提供了一种译码驱动电路100，包括第一子 驱动单元21、第i子驱动单元2i、第n子驱动单元2n及译码控制模块10，其中，第i子驱动单元2i用于根据电源电压信号、第一译码输入信号Intp1和中间译码输出信号MIntp生成主字线驱动信号；译码控制模块10与第一子驱动单元21、第i子驱动单元2i及第n子驱动单元2n均连接，用于根据使能控制信号及第二译码输入信号生成中间译码输出信号MIntp；其中，在中间译码输出信号MIntp为第一状态期间，主字线驱动信号为不驱动状态。第一子驱动单元21根据电源电压信号、第一译码输入信号Intp1和中间译码输出信号MIntp生成主字线驱动信号bMWL0，第i子驱动单元2i根据电源电压信号、第一译码输入信号Intp1和中间译码输出信号MIntp生成主字线驱动信号bMWLi-1，第n子驱动单元2n根据电源电压信号、第一译码输入信号Intp1和中间译码输出信号MIntp生成主字线驱动信号bMWLn-1。本实施例中，1≤i≤n，i、n均为正整数，n为子驱动单元的数量。
具体地，请继续参考图1，通过设置译码控制模块10与多个子驱动单元连接，并设置译码控制模块10根据使能控制信号及第二译码输入信号生成中间译码输出信号MIntp并提供给各子驱动单元，使得每一子驱动单元根据电源电压信号、第一译码输入信号Intp1和中间译码输出信号MIntp生成主字线驱动信号，主字线驱动信号与字线驱动信号及字线复位信号一起实现对行译码电路中多个本地字线驱动电路的控制，可以设置中间译码输出信号MIntp为第一状态期间，所述主字线驱动信号为不驱动状态，使得后级对应连接的字线保持不激活状态；并设置中间译码输出信号MIntp为第二状态期间，所述主字线驱动信号为驱动状态，以驱动后级对应连接的字线保持激活状态。本实施例中实现了利用一译码控制模块10控制多个子驱动单元来实现对多个本地字线驱动电路的控制，能够在不减少存储阵列区的存储容量的前提下，减小行译码电路中译码驱动电路100的体积，以有效减小半导体存储芯片外围电路区的体积，从而能够相对提高半导体存储芯片单位面积的存储容量。
作为示例，请参考图2，可以设置第i子驱动单元2i包括第一晶体管M1、第二晶体管M2及第三晶体管M3，第一晶体管M1被配置为：源极与电源电压信号PbMWL连接，栅极与第一译码输入信号Intp1连接；第二晶体管M2被配置为：源极与电源电压信号PbMWL连接，栅极与中间译码输出信号MIntp连接；第三晶体管M3被配置为：源极与译码控制模块10连接，漏极与第一晶体管M1的漏极及第二晶体管M2的漏极均连接，栅极与第一晶体管M1的栅极及第一译码输入信号Intp1均连接，1≤i≤n，i、n均为正整数，n为子驱动单元的数量。本实施例中，通过设置第一晶体管M1与第三晶体管M3构成一控制端连接第一译码输入信号Intp1的反向器，且该反相器的输出端与第二晶体管M2的输出端连接，第二晶体管M2的栅极与中间译码输出信号MIntp连接且输入端与电源电压信号连接，使得对应连接的子驱动单元20根据电源电压信号PbMWL、第一译码输入信号Intp1和中间译码输出信号MIntp生成主字线驱动信号，以驱动后级连接的字线，实现利用一译码控制模块10控制多个子驱动单元20来实现对多个本地字线驱动电路的控制。
作为示例，请参考图3，可以设置使能控制信号包括第一使能控制信号EN1及第二使能控制信号EN2；译码控制模块10包括第一反相器(未图示)、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7及第二译码信号接收单元11，第一反相器被配置为：电源端与第一电源VDD1连接，输出端与第二晶体管M2的栅极连接；第四晶体管M4被配置为：源极接地，漏极与第三晶体管M3的源极连接，栅极与第二晶体管M2的栅极及第一反相器的输出端均连接；第五晶体管M5被配置为：源极与第一电源VDD1连接，漏极与第一反相器的输入端连接，栅极与第一反相器的输出端及第二晶体管M2的栅极均连接；第六晶体管M6被配置为：源极与第一电源VDD1连接，漏极与第一反相器的输入端及第五晶体管M5的漏级均连接，栅极与第一使能控制信号EN1连接；第七晶体管M7被配置为：源极与第二译码信号接收单元11连接，漏极与第六晶体管M6的漏极及第一反相器的输入 端均连接，栅极与第二使能控制信号EN2连接。译码控制模块10根据第一使能控制信号EN1、第二使能控制信号EN2及第二译码信号接收单元11提供的信号向后级连接的子驱动单元20提供对应的中间译码输出信号MIntp，使得该子驱动单元能够根据电源电压信号PbMWL、第一译码输入信号Intp1和中间译码输出信号MIntp生成主字线驱动信号，以驱动后级连接的字线。本实施例可以实现在中间译码输出信号MIntp为第一状态期间，驱动后级连接的各子驱动单元20输出的主字线驱动信号为不驱动状态，使得后级对应连接的字线保持不激活状态；以及在中间译码输出信号MIntp为第二状态期间，驱动后级连接的各子驱动单元20输出的主字线驱动信号为驱动状态，以驱动后级对应连接的字线保持激活状态。
作为示例，请参考图3，可以设置第一反相器包括晶体管Q1及晶体管Q2，晶体管Q1被配置为：源极与第一电源VDD1连接，栅极与第五晶体管M5的漏极连接；晶体管Q2被配置为：源极接地，漏极与晶体管Q1的漏极连接并作为第一反相器的输出端，栅极与晶体管Q1的栅极连接并作为第一反相器的输入端。
作为示例，请继续参考图3，第二译码输入信号包括第二主译码输入信号Intp2及第二副译码输入信号Intp3；第二译码信号接收单元11包括第八晶体管M8及第九晶体管M9，第八晶体管M8被配置为：漏极与第七晶体管M7的源极连接，栅极与第二主译码输入信号Intp2连接；第九晶体管M9被配置为：源极接地，漏极与第八晶体管M8的源极连接，栅极与第二副译码输入信号Intp3连接。第二译码信号接收单元11根据第二主译码输入信号Intp2及第二副译码输入信号Intp3向第七晶体管M7提供源极信号，协同第一使能控制信号EN1、第二使能控制信号EN2控制第六晶体管M6、第七晶体管M7动作，向后级电路提供驱动信号，使得译码控制模块10向后级连接的子驱动单元20提供对应的中间译码输出信号，使得该子驱动单元20能够根据电源电压信号PbMWL、第一译码输入信号Intp1和中间译码输出信号MIntp生成主字线驱动信号，以驱动后级连接的字线。
作为示例，请参考图4，译码驱动电路100还包括使能控制模块30，使能控制模块30与多个译码控制模块10连接，用于根据主字线使能信号bMWLEn向多个译码控制模块10提供第一使能控制信号EN1及第二使能控制信号EN2。
作为示例，请参考图5，使能控制模块30包括第二反相器Inv2、第三反相器Inv3及第四反相器Inv4，第二反相器Inv2被配置为：输入端与主字线使能信号bMWLEn连接，电源端与第一电源VDD1连接；第三反相器Inv3被配置为：输入端与第二反相器Inv2的输出端连接，电源端与第一电源VDD1连接，输出端输出第一使能控制信号EN1；第四反相器Inv4被配置为：输入端与第二反相器Inv2的输出端连接，电源端与第二电源VDD2连接，输出端输出第二使能控制信号EN2。可以设置第一电源VDD1输出电压的幅值大于第二电源VDD2输出电压的幅值。
作为示例，请继续参考图5，可以设置第一电源VDD1输出电压的幅值为3V，第二电源VDD2输出电压的幅值为1.6V。
作为示例，请参考图6，译码驱动电路100还包括电源控制模块40，电源控制模块40与各子驱动单元连接，用于向各子驱动单元提供电源电压信号；其中，电源控制模块40还用于根据电源控制信号输出不同电压幅值的电源电压信号。
作为示例，请继续参考图6，可以设置电源控制信号包括第一子电源控制信号Sel1及第二子电源控制信号Sela；电源控制模块40包括第一电源控制单元41及第二电源控制单元42，第一电源控制单元41与第三电源VDD3、第一子电源控制信号Sel1及第二子电源控制信号Sela均连接，用于根据第一子电源控制信号Sel1及第二子电源控制信号Sela生成具有第一幅值的电源电压信号；第二电源控制单元42与第一电源VDD1及第二子电源控制信号的反相信号Selb连接，用于根据第二子电源控制信号的反相信号Selb生成具有第二幅值的电源电压信号。
作为示例，请继续参考图6，可以设置第一电源控制单元41包括第十晶体管M10及第十一晶体管M11，第十晶体管M10被配置为：源极与第三电源VDD3连接，栅极与第一子电源控制信号Sel1连接；第十一晶体管M11被配置为：源极与第十晶体管M10的漏级连接，栅极与第二子电源控制信号Sela连接，漏级输出具有第一幅值的电源电压信号。
作为示例，请继续参考图6，可以设置第二电源控制单元42包括第十二晶体管M12及第十三晶体管M13，第十二晶体管M12被配置为：源极与第一电源VDD1连接，栅极与漏级连接；第十三晶体管M13被配置为：源极与第十二晶体管M12的漏极连接，栅极与第二子电源控制信号的反相信号Selb连接，漏级输出具有第二幅值的电源电压信号。
作为示例，请继续参考图6，可以设置第一电源VDD1输出电压的幅值为3V，第三电源VDD3输出电压的幅值为1.8V，使得第一电源控制单元41能够输出3v-Vt的电源电压信号，及第二电源控制单元42能够输出1.8v的电源电压信号。
作为示例，请继续参考图6，可以设置电源控制模块40还包括第三电源控制单元43，第三电源控制单元43与第一电源VDD1、第一子电源控制信号的反相信号Sel2连接，用于根据第一子电源控制信号的反相信号Sel2生成具有第三幅值的电源电压信号。
作为示例，请继续参考图6，可以设置第三电源控制单元43包括第十四晶体管M14，第十四晶体管M14被配置为：源极与第一电源VDD1连接，栅极与第一子电源控制信号的反相信号Sel2连接，漏极输出具有第三幅值的电源电压信号。例如，可以设置第一电源VDD1输出电压的幅值为3V，使得第三电源控制单元43能够输出3v的电源电压信号。
作为示例，请继续参考图6，可以设置第三电源VDD3输出电压的幅值小于第一电源VDD1输出电压的幅值；第一幅值大于第二幅值，且第二幅值大于第三幅值。例如，可以设置第一电源VDD1输出电压的幅值为3V，第三电源VDD3输出电压的幅值为1.8V，使得第一电源控制单元41能够输出3v-Vt的电源电压信号，及第二电源控制单元42能够输出1.8v的电源电压信号，第三电源控制单元43能够输出3v的电源电压信号。在电源控制模块40驱动电路频繁工作的状态下，可以控制第三电源控制单元43能够输出3v的电源电压信号，减少频繁切换电源电压信号的功耗；在电源控制模块40驱动电路处于待机状态下，可以控制第一电源控制单元41能够输出3v-Vt的电源电压信号，在减少功耗的同时为驱动电路的工作用电做好准备；在电源控制模块40驱动电路处于更长时间不工作的状态下，可以控制第二电源控制单元42能够输出1.8v的电源电压信号，以减少电路功耗。
作为示例，请继续参考图6，可以设置第二子电源控制信号Sela经由反相器Inv5与控制电路(未图示)连接，并设置第一子电源控制信号Sel1经由反相器Inv6与控制电路连接，使得控制电路能够根据电源控制模块40驱动电路的实际工作状态控制电源控制模块40输出对应幅值的电源电压信号，以减少电路功耗。
作为示例，请参考图7，本地字线驱动电路的电路(Local Word Line Driver，LWD)包括晶体管Q3、晶体管Q4及晶体管Q5，晶体管Q3被配置为：源极与字线驱动信号WLDV连接，栅极与主字线驱动信号bMWL连接，漏极与字线WL连接；晶体管Q4被配置为：源极接地，漏极与晶体管Q3的漏极及字线WL均连接，栅极与主字线驱动信号bMWL连接；晶体管Q5被配置为：源极接地，漏极与晶体管Q3的漏极、晶体管Q4的漏极及字线WL均连接，栅极与字线复位信号WLRst连接。本地字线驱动电路的电路根据主字线驱动信号bMWL、字线复位信号WLRst及字线驱动信号WLDV驱动字线WL的状态。例如，可以设置中间译码输出信号为第一状态期间，译码驱动电路输出的主字线驱动信号bMWL为不驱动状态，使得字线WL保持不激活状态；并设置中间译码输出信号为第二状态期间，译码驱动电路输出的主字线驱动信号bMWL为驱动状态，以驱动字线WL保持激活状态。
关于上述实施例中涉及的字线驱动信号WLDV及字线复位信号WLRst可以采用相关现有技术实现，具体实现原理本公开不再赘述。
根据一些实施例，本公开提供了一种存储芯片，包括任一本公开实施例中的译码驱动 电路。通过设置译码控制模块与多个子驱动单元连接，并设置译码控制模块根据使能控制信号及第二译码输入信号生成中间译码输出信号并提供给各子驱动单元，使得每一子驱动单元根据电源电压信号、第一译码输入信号和中间译码输出信号生成主字线驱动信号，主字线驱动信号与字线驱动信号及字线复位信号一起实现对行译码电路中多个本地字线驱动电路的控制，可以设置中间译码输出信号为第一状态期间，所述主字线驱动信号为不驱动状态，使得后级对应连接的字线保持不激活状态；并设置中间译码输出信号为第二状态期间，所述主字线驱动信号为驱动状态，以驱动后级对应连接的字线保持激活状态。本实施例中实现了利用一译码控制模块控制多个子驱动单元来实现对多个本地字线驱动电路的控制，能够在不减少存储阵列区的存储容量的前提下，减小行译码电路中译码驱动电路的体积，以有效减小半导体存储芯片外围电路区的体积，从而能够相对提高半导体存储芯片单位面积的存储容量。
请注意，上述实施例仅出于说明性目的而不意味对本发明的限制。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种译码驱动电路，包括：
    多个子驱动单元，用于根据电源电压信号、第一译码输入信号和中间译码输出信号生成主字线驱动信号；
    译码控制模块，所述译码控制模块与多个所述子驱动单元连接，用于根据使能控制信号及第二译码输入信号生成所述中间译码输出信号；
    其中，在所述中间译码输出信号为第一状态期间，所述主字线驱动信号为不驱动状态。
  2. 根据权利要求1所述的译码驱动电路，其中，所述子驱动单元包括：
    第一晶体管，被配置为：源极与所述电源电压信号连接，栅极与所述第一译码输入信号连接；
    第二晶体管，被配置为：源极与所述电源电压信号连接，栅极与所述中间译码输出信号连接；
    第三晶体管，被配置为：源极与所述译码控制模块连接，漏极与所述第一晶体管的漏极及所述第二晶体管的漏极均连接，栅极与所述第一晶体管的栅极及所述第一译码输入信号均连接。
  3. 根据权利要求2所述的译码驱动电路，其中，所述使能控制信号包括第一使能控制信号及第二使能控制信号；所述译码控制模块包括：
    第一反相器，被配置为：电源端与第一电源连接，输出端与所述第二晶体管的栅极连接；
    第四晶体管，被配置为：源极接地，漏极与所述第三晶体管的源极连接，栅极与所述第二晶体管的栅极及所述第一反相器的输出端均连接；
    第五晶体管，被配置为：源极与所述第一电源连接，漏极与所述第一反相器的输入端连接，栅极与所述第一反相器的输出端及所述第二晶体管的栅极均连接；
    第六晶体管，被配置为：源极与所述第一电源连接，漏极与所述第一反相器的输入端及所述第五晶体管的漏级均连接，栅极与所述第一使能控制信号连接；
    第七晶体管，被配置为：源极与第二译码信号接收单元连接，漏极与所述第六晶体管的漏极及所述第一反相器的输入端均连接，栅极与所述第二使能控制信号连接。
  4. 根据权利要求3所述的译码驱动电路，其中，所述第二译码输入信号包括第二主译码输入信号及第二副译码输入信号；所述第二译码信号接收单元包括：
    第八晶体管，被配置为：漏极与所述第七晶体管的源极连接，栅极与所述第二主译码输入信号连接；
    第九晶体管，被配置为：源极接地，漏极与所述第八晶体管的源极连接，栅极与所述第二副译码输入信号连接。
  5. 根据权利要求4所述的译码驱动电路，其中，还包括：
    使能控制模块，与多个所述译码控制模块连接，用于根据主字线使能信号向多个所述译码控制模块提供所述第一使能控制信号及所述第二使能控制信号。
  6. 根据权利要求5所述的译码驱动电路，其中，所述使能控制模块包括：
    第二反相器，被配置为：输入端与所述主字线使能信号连接，电源端与所述第一电源连接；
    第三反相器，被配置为：输入端与所述第二反相器的输出端连接，电源端与所述第一电源连接，输出端输出所述第一使能控制信号；
    第四反相器，被配置为：输入端与所述第二反相器的输出端连接，电源端与第二电源连接，输出端输出所述第二使能控制信号。
  7. 根据权利要求6所述的译码驱动电路，其中，所述第一电源输出电压的幅值大于所述第二电源输出电压的幅值。
  8. 根据权利要求1-7任一项所述的译码驱动电路，其中，还包括：
    电源控制模块，与各所述子驱动单元连接，用于向各所述子驱动单元提供所述电源电压信号；
    所述电源控制模块还用于根据电源控制信号输出不同电压幅值的电源电压信号。
  9. 根据权利要求8所述的译码驱动电路，其中，所述电源控制信号包括第一子电源控制信号及第二子电源控制信号；所述电源控制模块包括：
    第一电源控制单元，与第三电源、所述第一子电源控制信号及所述第二子电源控制信号均连接，用于根据所述第一子电源控制信号及所述第二子电源控制信号生成具有第一幅值的电源电压信号；
    第二电源控制单元，与第一电源及所述第二子电源控制信号的反相信号连接，用于根据所述第二子电源控制信号的反相信号生成具有第二幅值的电源电压信号。
  10. 根据权利要求9所述的译码驱动电路，其中，所述电源控制模块还包括：
    第三电源控制单元，与所述第一电源、所述第一子电源控制信号的反相信号连接，用于根据所述第一子电源控制信号的反相信号生成具有第三幅值的电源电压信号。
  11. 根据权利要求9所述的译码驱动电路，其中，所述第一电源控制单元包括：
    第十晶体管，被配置为：源极与所述第三电源连接，栅极与所述第一子电源控制信号连接；
    第十一晶体管，被配置为：源极与所述第十晶体管的漏级连接，栅极与所述第二子电源控制信号连接，漏级输出所述具有第一幅值的电源电压信号。
  12. 根据权利要求9所述的译码驱动电路，其中，所述第二电源控制单元包括：
    第十二晶体管，被配置为：源极与所述第一电源连接，栅极与漏级连接；
    第十三晶体管，被配置为：源极与所述第十二晶体管的漏极连接，栅极与所述第二子电源控制信号的反相信号连接，漏级输出所述具有第二幅值的电源电压信号。
  13. 根据权利要求10所述的译码驱动电路，其中，所述第三电源控制单元包括：
    第十四晶体管，被配置为：源极与所述第一电源连接，栅极与所述第一子电源控制信号的反相信号连接，漏极输出所述具有第三幅值的电源电压信号。
  14. 根据权利要求13所述的译码驱动电路，其中，所述第三电源输出电压的幅值小于所述第一电源输出电压的幅值；
    所述第一幅值大于所述第二幅值，且所述第二幅值大于所述第三幅值。
  15. 一种存储芯片，包括：
    权利要求1-14任一项所述的译码驱动电路。
PCT/CN2022/108164 2021-08-25 2022-07-27 译码驱动电路及存储芯片 WO2023024808A1 (zh)

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