WO2023024154A1 - 一种用于制备n型选择性发射极晶硅电池的选择性扩散方法及其应用 - Google Patents

一种用于制备n型选择性发射极晶硅电池的选择性扩散方法及其应用 Download PDF

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WO2023024154A1
WO2023024154A1 PCT/CN2021/116818 CN2021116818W WO2023024154A1 WO 2023024154 A1 WO2023024154 A1 WO 2023024154A1 CN 2021116818 W CN2021116818 W CN 2021116818W WO 2023024154 A1 WO2023024154 A1 WO 2023024154A1
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layer
silicon
diffusion
amorphous silicon
selective
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French (fr)
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胡党平
赵文祥
赵迎财
廖晖
马玉超
王义福
单伟
何胜
徐伟智
黄海燕
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正泰新能科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the technical field of N-type crystalline silicon batteries, in particular to a selective diffusion method for preparing N-type selective emitter crystalline silicon batteries.
  • N-type crystalline silicon cells Compared with P-type crystalline silicon cells, N-type crystalline silicon cells have the advantages of high minority carrier lifetime, no light-induced attenuation, good weak light effect, and small temperature coefficient, which is the hope for crystalline silicon solar cells to move towards the theoretical highest efficiency. Boron diffusion is the core technology of N-type crystalline silicon cells. At present, the boron diffusion of mass-produced N-type crystalline silicon cells adopts a uniform junction process, and the square resistance control range is 80-120ohm. limit.
  • Low-concentration doping and shallow junction diffusion can effectively reduce the bulk and surface recombination probability of minority carriers, increase the collection rate of carriers, reduce the reverse saturation current of the battery, and increase the open-circuit voltage Voc and short-circuit current Isc of the battery, thereby Effectively improve the conversion efficiency of the battery.
  • the low-concentration shallow junction structure will pose new challenges to the metal electrode paste.
  • Low-concentration doping can easily lead to poor contact resistance, high battery series resistance, and low fill factor FF.
  • shallow junction diffusion tends to increase the probability of electrode metal permeating into the PN junction region, thereby reducing the conversion efficiency of the battery.
  • the laser SE technology for the mass production of P-type crystalline silicon cells is relatively mature, but due to the difference in the diffusion speed of boron and phosphorus, the laser SE technology used to prepare the selective emitter of P-type crystalline silicon cells is not suitable for For N-type crystalline silicon cells, the selective emitter technology of boron diffusion has become an urgent problem to be solved in improving the efficiency of N-type crystalline silicon cells.
  • patent CN200910029673.9 discloses a selective diffusion process for crystalline silicon solar cells, including high-concentration phosphorus diffusion in the front electrode grid line area, and low-concentration phosphorus diffusion outside the front electrode area, including the following steps: first clean the silicon wafer After texturing, prepare a layer of dense silicon dioxide film on the silicon wafer as a diffusion barrier layer, and then use laser grooving technology to selectively remove the oxide film in the electrode grid line area and form grooves of a certain depth, and then carry out high-concentration phosphorus Diffusion creates heavy doping in the electrode area and light doping outside the electrode area.
  • this method is applied to the preparation of N-type selective emitter crystalline silicon cells, since the diffusion rate of boron in silicon oxide is faster than that in crystalline silicon, it is easy to cause uncontrollable surface concentration and affect the performance of the selective emitter.
  • the present invention provides a selective diffusion method for preparing N-type selective emitter crystalline silicon cells.
  • the method uses the amorphous silicon layer as a mask, which can prevent the boron concentration in the formed doped layer from being uncontrollable, and is beneficial to improving the open-circuit voltage, short-circuit current and filling factor of the N-type crystal silicon battery.
  • the present invention provides a selective diffusion method for preparing N-type selective emitter crystalline silicon cells, including two schemes. in:
  • Option 1 includes the following steps:
  • Selective diffusion can be achieved by using the above method, and an emitter with low surface concentration and shallow PN junction can be formed in the non-metal contact area, which can reduce the recombination probability of minority carriers, improve the collection rate of carriers, and reduce the reverse saturation current of the battery.
  • increase the open-circuit voltage Voc and short-circuit current Isc of the battery reduce the contact resistance with the metal paste, and increase the fill factor FF of the battery; form a high-concentration, deep PN junction emitter in the metal contact area, which can reduce the contact area of the metal paste contact resistance, while reducing the risk of paste burning through PN, and improving the fill factor FF of the battery.
  • the present invention uses the amorphous silicon layer as a mask, because the diffusion of boron in the amorphous silicon layer is very slow, thereby preventing boron concentration from being uncontrollable in the doped layer formed by boron penetrating through the amorphous silicon layer, which is beneficial to Improve the open-circuit voltage, short-circuit current and fill factor of N-type crystalline silicon cells; in addition, the polysilicon mask can be removed by cleaning, and will not remain in the selective emitter to affect the performance of the cell.
  • the diffusion resistance of the low-concentration boron diffusion is 140-200 ohm
  • the surface concentration (boron atoms) is 1.0e 19 -1.5e 19 atoms/cm 3
  • the junction depth is 0.3-0.6 ⁇ m .
  • the diffusion resistance of the high-concentration boron diffusion is 60-100 ohm
  • the surface concentration (boron atoms) is 2.0e 19 -3.0e 19 atoms/cm 3
  • the junction depth is 0.6-1.0 ⁇ m .
  • the thickness of the amorphous silicon layer is 80-200 nm.
  • step (2) low-pressure chemical vapor deposition (LPCVD) is used to deposit amorphous silicon on the lightly doped layer.
  • LPCVD low-pressure chemical vapor deposition
  • Option two includes the following steps:
  • the last step of this scheme is to form light doping, which has the advantages of more controllable doping concentration and junction depth in the lightly doped region, which can further increase the open circuit voltage and short circuit current, and the process stability is better.
  • the thickness of the amorphous silicon layer is 80-200 nm.
  • low-pressure chemical vapor deposition LPCVD
  • LPCVD low-pressure chemical vapor deposition
  • the diffusion resistance of the high-concentration boron diffusion is 60-100 ohm
  • the surface concentration (boron atoms) is 2.0e 19 -3.0e 19 atoms/cm 3
  • the junction depth is 0.6-1.0 ⁇ m .
  • the diffusion resistance of the low-concentration boron diffusion is 140-200 ohm
  • the surface concentration (boron atoms) is 1.0e 19 -1.5e 19 atoms/cm 3
  • the junction depth is 0.3-0.6 ⁇ m .
  • the present invention provides a method for preparing an N-type selective emitter crystalline silicon cell using the selective diffusion method, comprising the following steps: after the selective diffusion is completed by the selective diffusion method, Etch to remove borosilicate glass (BSG) on the back and edge, then deposit a silicon oxide layer and a phosphorus-doped polysilicon layer on the back, anneal and dewind, and then deposit an aluminum oxide passivation layer and a front silicon nitride layer on the front of the silicon wafer in sequence , and deposit a silicon nitride layer on the back of the silicon wafer. After screen printing and sintering, an N-type selective emitter crystalline silicon cell is obtained.
  • BSG borosilicate glass
  • the aluminum oxide passivation layer has a thickness of 3-10 nm
  • the front silicon nitride layer has a thickness of 70-90 nm
  • the back silicon nitride layer has a thickness of 70-90 nm.
  • the present invention has the following advantages:
  • the present invention forms the emitter of low surface concentration and shallow PN junction in the non-metal contact area, and forms the emitter of high concentration and deep PN junction in the metal contact area, which can improve the open circuit voltage and short circuit current of N-type crystalline silicon cells and fill factor;
  • the present invention uses the amorphous silicon layer as a mask to realize selective diffusion, which can prevent the boron concentration in the formed doped layer from being uncontrollable, and is conducive to improving the open circuit voltage, short circuit current and fill factor of the N-type crystalline silicon battery.
  • Fig. 1 is a schematic diagram of the front structure of an N-type selective emitter crystalline silicon cell obtained in the present invention.
  • a method for preparing an N-type selective emitter crystalline silicon cell comprising the following steps:
  • Diffusion of low-concentration boron is performed on the front side of the textured silicon wafer.
  • the diffusion resistance is 140-200ohm
  • the surface concentration is 1.0e 19-1.5e 19 atoms/cm 3
  • the junction depth is 0.3-0.6 ⁇ m, forming a light doped layer (i.e. P + layer);
  • a method for preparing an N-type selective emitter crystalline silicon cell comprising the following steps:
  • Aluminum oxide is deposited on the front side of the silicon wafer to form an aluminum oxide passivation layer with a thickness of 6nm;
  • a method for preparing an N-type selective emitter crystalline silicon cell comprising the following steps:
  • Aluminum oxide is deposited on the front side of the silicon wafer to form an aluminum oxide passivation layer with a thickness of 6nm;
  • a method for preparing an N-type selective emitter crystalline silicon cell comprising the following steps:
  • Aluminum oxide is deposited on the front side of the silicon wafer to form an aluminum oxide passivation layer with a thickness of 7nm;
  • a method for preparing an N-type selective emitter crystalline silicon cell comprising the following steps:
  • Adopt LPCVD method to deposit amorphous silicon on the front side of the silicon wafer after texturing, forming an amorphous silicon layer with a thickness of 80nm;
  • Aluminum oxide is deposited on the front side of the silicon wafer to form an aluminum oxide passivation layer with a thickness of 6nm;
  • a method for preparing an N-type selective emitter crystalline silicon cell comprising the following steps:
  • Adopt LPCVD method to deposit amorphous silicon on the front side of the silicon wafer after texturing, forming an amorphous silicon layer with a thickness of 140nm;
  • Aluminum oxide is deposited on the front side of the silicon wafer to form an aluminum oxide passivation layer with a thickness of 6nm;
  • a method for preparing an N-type selective emitter crystalline silicon cell comprising the following steps:
  • Adopt LPCVD method to deposit amorphous silicon on the front side of the silicon wafer after texturing, forming an amorphous silicon layer with a thickness of 200nm;
  • Aluminum oxide is deposited on the front side of the silicon wafer to form an aluminum oxide passivation layer with a thickness of 10nm;
  • a method for preparing an emitter of an N-type crystalline silicon cell comprising the following steps:
  • Aluminum oxide is deposited on the front side of the silicon wafer to form an aluminum oxide passivation layer with a thickness of 6nm;
  • a method for preparing an N-type selective emitter crystalline silicon cell comprising the following steps:
  • Aluminum oxide is deposited on the front side of the silicon wafer to form an aluminum oxide passivation layer with a thickness of 6nm;
  • a method for preparing an N-type selective emitter crystalline silicon cell comprising the following steps:
  • Aluminum oxide is deposited on the front side of the silicon wafer to form an aluminum oxide passivation layer with a thickness of 3nm;
  • the emitters prepared in Examples 1-6 and Comparative Examples 1-3 were made into N-type crystalline silicon cells, and the open-circuit voltage Voc, short-circuit current Isc, and fill factor FF of the cells were tested, and the results are shown in Table 1. .
  • Example 1 703.6 11.190 83.15 23.88
  • Example 2 703.9 11.195 83.14 23.90
  • Example 3 704.5 11.198 83.19 23.94
  • Example 4 704.1 11.200 83.17 23.92
  • Example 5 704.5 11.211 83.14 23.95
  • Example 6 705.0 11.220 83.12 23.98 Comparative example 1 701.3 11.153 83.10 23.71 Comparative example 2 703.2 11.170 83.12 23.81 Comparative example 3 703.7 11.185 83.15 23.87
  • Comparative Example 1 adopts one-time doping to obtain a common emitter, and Examples 1 and 4 adopt the method of the present invention to obtain a selective emitter.
  • the battery open-circuit voltage, short-circuit current, and fill factor of Examples 1 and 4 are increased, and the battery efficiency is increased by 0.17% and 0.21%, respectively.
  • the reason is: in the selective emitter, the non-metal contact region forms an emitter with low surface concentration and shallow PN junction, which reduces the probability of minority carrier recombination, improves the collection rate of carriers, and reduces the reverse saturation current of the battery.
  • the metal contact area forms a high-concentration, deep PN junction emitter, reduces the contact resistance of the metal paste contact area, and at the same time reduces The risk of the paste burning through the PN increases the fill factor of the battery.
  • Examples 1 and 4 use amorphous silicon as a mask
  • Comparative Examples 2 and 3 use silicon oxide as a mask.
  • the battery open-circuit voltage, short-circuit current, and fill factor of Example 1 increased, thereby improving the battery efficiency by 0.09%
  • Comparative Example 3 the battery open-circuit voltage of Example 4
  • the short-circuit current and fill factor are increased, and the efficiency is increased by 0.05%.
  • Example 1 selective diffusion is carried out in the order of "formation of a lightly doped layer ⁇ deposition of a mask ⁇ laser grooving ⁇ formation of a heavily doped layer ⁇ removal of the mask", while in Example 4, "deposition of a mask ⁇ laser Groove ⁇ formation of heavily doped layer ⁇ removal of mask ⁇ formation of lightly doped layer” sequence.
  • the open-circuit voltage and short-circuit current of the battery in Example 4 are increased, and the battery efficiency is increased by 0.17%.
  • the reason is that adopting the sequence in Embodiment 4 has the advantages of more controllable doping concentration and junction depth of the lightly doped region, can further increase the open circuit voltage and short circuit current, and has better process stability.
  • Raw materials used in the present invention, equipment, if not specified, are commonly used raw materials, equipment in this area; Method used in the present invention, if not specified, are conventional methods in this area.

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Abstract

本发明涉及N型晶硅电池技术领域，公开了一种用于制备N型选择性发射极晶硅电池的选择性扩散方法，包括以下步骤：（1）在制绒后的硅片正面进行低浓度硼扩散，形成轻掺杂层；（2）在轻掺杂层上沉积非晶硅，形成非晶硅层；（3）对非晶硅层进行激光开槽，以去除金属接触区域的非晶硅；（4）在去除非晶硅后的金属接触区域进行高浓度硼扩散，形成重掺杂层；（5）清洗，以去除非金属区域的非晶硅。本发明的选择性扩散方法采用非晶硅层作为掩膜，能防止形成的掺杂层中硼浓度不可控，有利于提高N型晶硅电池的开路电压、短路电流和填充因子。

Description

一种用于制备N型选择性发射极晶硅电池的选择性扩散方法及其应用 技术领域
本发明涉及N型晶硅电池技术领域，尤其涉及一种用于制备N型选择性发射极晶硅电池的选择性扩散方法。
背景技术
相对P型晶硅电池，N型晶硅电池具有少子寿命高，无光致衰减，弱光效应好，温度系数小等优点，是晶硅太阳能电池迈向理论最高效率的希望。硼扩散是N型晶硅电池的核心技术，目前量产N型晶硅电池的硼扩散均采用均匀结的工艺，方阻控制范围在80～120ohm，均匀结电池结构主要受金属浆料特性的限制。低浓度掺杂、浅结扩散可以有效降低少数载流子的体和表面复合几率，提高载流子的收集率，减少电池的反向饱和电流，提高电池的开路电压Voc和短路电流Isc，从而有效提升电池的转换效率。然而低浓度浅结结构会对金属电极浆料提出新的挑战，低浓度掺杂易导致接触电阻差，电池串联电阻高，填充因子FF低。同时，浅结扩散易增加电极金属向PN结区渗透的几率，从而降低电池的转换效率。
为了得到更高的电池转换效率，选择性发射极技术孕育而生。在非金属接触区域采用低浓度浅结，金属接触区域采用高浓度深结，在提高电池的开路电压和短路电流的同时，降低电池的串联电阻，提高电池的填充因子，从而有效提升电池的转换效率。目前，P型晶硅电池量产的激光SE技术已较为成熟，但由于硼和磷在扩散速度等方面的差异，用于制备P型晶硅电池选择性发射极的激光SE技术并不适用于N型晶硅电池，硼扩散的选择性发射极技术就成为N型晶硅电池效率提升亟待解决的问题。
例如，专利CN200910029673.9公开了晶体硅太阳电池选择性扩散工艺，包括在正面电极栅线区域进行高浓度磷扩散，在正面电极区域外进行低浓度磷扩散，包括以下步骤：先将硅片清洗制绒后在硅片上制备一层致密的二氧化硅膜作为扩散阻挡层，然后采用激光刻槽技术选择性去除电极栅线区域的氧化膜并形成一定深度的凹槽，再进行高浓度磷扩散在电极区域形成重掺杂，同时在电极区域外形成轻掺杂。当将该方法应用于N型选择性发射极晶硅电池的制备时，由于硼在氧化硅中的扩散速度比晶硅中快，易导致表面浓度的不可控，影响选择性发射极的性能。
发明内容
为了解决上述技术问题，本发明提供了一种用于制备N型选择性发射极晶硅电池的选 择性扩散方法。该方法采用非晶硅层作为掩膜，能防止形成的掺杂层中硼浓度不可控，有利于提高N型晶硅电池的开路电压、短路电流和填充因子。
本发明的具体技术方案为：
第一方面，本发明提供了一种用于制备N型选择性发射极晶硅电池的选择性扩散方法，包括两种方案。其中：
方案一包括以下步骤：
(1)在制绒后的硅片正面进行低浓度硼扩散，形成轻掺杂层；
(2)在轻掺杂层上沉积非晶硅，形成非晶硅层；
(3)对非晶硅层进行激光开槽，以去除金属接触区域的非晶硅；
(4)在去除非晶硅后的金属接触区域进行高浓度硼扩散，形成重掺杂层；
(5)清洗，以去除非金属区域的非晶硅。
采用上述方法能够实现选择性扩散，在非金属接触区形成低表面浓度、浅PN结的发射极，能够降低少数载流子复合几率，提高载流子的收集率，减少电池的反向饱和电流，提高电池的开路电压Voc和短路电流Isc，并降低和金属浆料接触电阻，提升电池的填充因子FF；在金属接触区形成高浓度、深PN结的发射极，能够降低金属浆料接触区的接触电阻，同时降低浆料烧穿PN的风险，提升电池的填充因子FF。
并且，本发明采用非晶硅层作为掩膜，由于硼在非晶硅中的扩散很慢，因而能防止硼透过非晶硅层而导致形成的掺杂层中硼浓度不可控，有利于提高N型晶硅电池的开路电压、短路电流和填充因子；此外，多晶硅掩膜通过清洗即可去除，不会残留在选择性发射极中而影响电池性能。
作为优选，步骤(1)中，所述低浓度硼扩散的扩散方阻为140～200ohm，表面浓度(硼原子)为1.0e 19～1.5e 19atoms/cm 3，结深为0.3～0.6μm。
作为优选，步骤(4)中，所述高浓度硼扩散的扩散方阻为60～100ohm，表面浓度(硼原子)为2.0e 19～3.0e 19atoms/cm 3，结深为0.6～1.0μm。
作为优选，步骤(2)中，所述非晶硅层的厚度为80～200nm。
作为优选，步骤(2)中，采用低压力化学气相沉积法(LPCVD)在轻掺杂层上沉积非晶硅。
方案二包括以下步骤：
(I)在制绒后的硅片正面沉积非晶硅，形成非晶硅层；
(II)对非晶硅层进行激光开槽，以去除金属接触区域的非晶硅；
(III)在去除非晶硅后的金属接触区域进行高浓度硼扩散，形成重掺杂层；
(IV)清洗，以去除非金属区域的非晶硅；
(V)在清洗后的硅片正面进行低浓度硼扩散，形成轻掺杂层。
相较于形成轻掺杂层→沉积掩膜→激光开槽→形成重掺杂层→去除掩膜而言，采用沉积掩膜→激光开槽→形成重掺杂层→去除掩膜→形成轻掺杂层的方法，该方案最后一步形成轻掺杂，具有轻掺杂区的掺杂浓度和结深更可控的优点，能进一步提升开路电压和短路电流，工艺稳定性更好。
作为优选，步骤(I)中，所述非晶硅层的厚度为80～200nm。
作为优选，步骤(I)中，采用低压力化学气相沉积法(LPCVD)在轻掺杂层上沉积非晶硅。
作为优选，步骤(III)中，所述高浓度硼扩散的扩散方阻为60～100ohm，表面浓度(硼原子)为2.0e 19～3.0e 19atoms/cm 3，结深为0.6～1.0μm。
作为优选，步骤(V)中，所述低浓度硼扩散的扩散方阻为140～200ohm，表面浓度(硼原子)为1.0e 19～1.5e 19atoms/cm 3，结深为0.3～0.6μm。
第二方面，本发明提供了一种利用所述选择性扩散方法制备N型选择性发射极晶硅电池的方法，包括以下步骤：在采用所述选择性扩散方法完成选择性扩散后，通过刻蚀去除背面和边缘的硼硅玻璃(BSG)，然后背面沉积氧化硅层和掺磷多晶硅层，退火处理和去绕镀，而后在硅片正面依次沉积氧化铝钝化层和正面氮化硅层，并在硅片背面沉积背面氮化硅层，经丝网印刷和烧结后，获得N型选择性发射极晶硅电池。
作为优选，所述氧化铝钝化层的厚度为3～10nm，所述正面氮化硅层的厚度为70～90nm，所述背面氮化硅层的厚度为70～90nm。
与现有技术相比，本发明具有以下优点：
(1)本发明在非金属接触区形成低表面浓度、浅PN结的发射极，在金属接触区形成高浓度、深PN结的发射极，能提高N型晶硅电池的开路电压、短路电流和填充因子；
(2)本发明采用非晶硅层作为掩膜实现选择性扩散，能防止形成的掺杂层中硼浓度不可控，有利于提高N型晶硅电池的开路电压、短路电流和填充因子。
附图说明
图1为本发明获得的N型选择性发射极晶硅电池的正面结构示意图。
具体实施方式
下面结合实施例对本发明作进一步的描述。
总实施例
一种制备N型选择性发射极晶硅电池的方法，包括以下步骤：
(1)在硅片表面制绒，形成金字塔绒面；
(2)选择性扩散：
方案一：
(2.1)在制绒后的硅片正面进行低浓度硼扩散，扩散方阻为140～200ohm，表面浓度为1.0e 19～1.5e 19atoms/cm 3，结深为0.3～0.6μm，形成轻掺杂层(即P +层)；
(2.2)采用LPCVD法在轻掺杂层上沉积非晶硅，形成厚度为80～200nm的非晶硅层；
(2.3)对非晶硅层进行激光开槽，以去除金属接触区域的非晶硅；
(2.4)在去除非晶硅后的金属接触区域进行高浓度硼扩散，扩散方阻为60～100ohm，表面浓度为2.0e 19～3.0e 19atoms/cm 3，结深为0.6～1.0μm，形成重掺杂层(即P ++层)；
(2.5)清洗，以去除非金属区域的非晶硅；
方案二：
(2.1)采用LPCVD法在制绒后的硅片正面沉积非晶硅，形成厚度为80～200nm的非晶硅层；
(2.2)对非晶硅层进行激光开槽，以去除金属接触区域的非晶硅；
(2.3)在去除非晶硅后的金属接触区域进行高浓度硼扩散，扩散方阻为60～100ohm，表面浓度为2.0e 19～3.0e 19atoms/cm 3，结深为0.6～1.0μm，形成重掺杂层(即P ++层)；
(2.4)清洗，以去除非金属区域的非晶硅；
(2.5)在清洗后的硅片正面进行低浓度硼扩散，扩散方阻为140～200ohm，表面浓度为1.0e 19～1.5e 19atoms/cm 3，结深为0.3～0.6μm，形成轻掺杂层(即P +层)；
(3)刻蚀，以去除背面和边缘的硼硅玻璃；
(4)采用LPCVD法在硅片背面沉积氧化硅层和掺磷多晶硅层；
(5)退火；
(6)去PSG和RCA清洗，去除正面绕镀；
(7)在硅片正面沉积氧化铝，形成厚度为3～10nm的氧化铝钝化层(即AlO x层)；
(8)在氧化铝钝化层上沉积氮化硅，形成厚度为70～90nm的正面氮化硅层(即SiN x层)；
(9)在硅片背面沉积氮化硅，厚度为70～90nm的背面氮化硅层；
(10)经丝网印刷和烧结后，获得N型选择性发射极晶硅电池，其正面结构如图1所示。
实施例1
一种制备N型选择性发射极晶硅电池的方法，包括以下步骤：
(1)在硅片表面制绒，形成金字塔绒面；
(2)选择性扩散：
(2.1)在制绒后的硅片正面进行低浓度硼扩散，扩散方阻为140ohm，表面浓度为1.2e 19atoms/cm 3，结深为0.6μm，形成轻掺杂层；
(2.2)采用LPCVD法在轻掺杂层上沉积非晶硅，形成厚度为80nm的非晶硅层；
(2.3)对非晶硅层进行激光开槽，以去除金属接触区域的非晶硅；
(2.4)在去除非晶硅后的金属接触区域进行高浓度硼扩散，扩散方阻为60ohm，表面浓度为3.0e 19atoms/cm 3，结深为1.0μm，形成重掺杂层；
(2.5)清洗，以去除非金属区域的非晶硅；
(3)刻蚀，以去除背面和边缘的硼硅玻璃；
(4)采用LPCVD法在硅片背面沉积厚度为1.0nm的氧化硅层和厚度为110nm的掺磷多晶硅层；
(5)退火；
(6)去PSG和RCA清洗，去除正面绕镀；
(7)在硅片正面沉积氧化铝，形成厚度为6nm的氧化铝钝化层；
(8)在氧化铝钝化层上沉积氮化硅，形成厚度为70nm的正面氮化硅层；
(9)在硅片背面沉积氮化硅，厚度为70nm的背面氮化硅层；
(10)经丝网印刷和烧结后，获得N型选择性发射极晶硅电池。
实施例2
一种制备N型选择性发射极晶硅电池的方法，包括以下步骤：
(1)在硅片表面制绒，形成金字塔绒面；
(2)选择性扩散：
(2.1)在制绒后的硅片正面进行低浓度硼扩散，扩散方阻为170ohm，表面浓度为1.2e 19atoms/cm 3，结深为0.5μm，形成轻掺杂层；
(2.2)采用LPCVD法在轻掺杂层上沉积非晶硅，形成厚度为140nm的非晶硅层；
(2.3)对非晶硅层进行激光开槽，以去除金属接触区域的非晶硅；
(2.4)在去除非晶硅后的金属接触区域进行高浓度硼扩散，扩散方阻为70ohm，表面浓度为2.5e 19atoms/cm 3，结深为0.9μm，形成重掺杂层；
(2.5)清洗，以去除非金属区域的非晶硅；
(3)刻蚀，以去除背面和边缘的硼硅玻璃；
(4)采用LPCVD法在硅片背面沉积厚度为1.0nm的氧化硅层和厚度为110nm的掺磷多晶硅层；
(5)退火；
(6)去PSG和RCA清洗，去除正面绕镀；
(7)在硅片正面沉积氧化铝，形成厚度为6nm的氧化铝钝化层；
(8)在氧化铝钝化层上沉积氮化硅，形成厚度为80nm的正面氮化硅层；
(9)在硅片背面沉积氮化硅，厚度为80nm的背面氮化硅层；
(10)经丝网印刷和烧结后，获得N型选择性发射极晶硅电池。
实施例3
一种制备N型选择性发射极晶硅电池的方法，包括以下步骤：
(1)在硅片表面制绒，形成金字塔绒面；
(2)选择性扩散：
(2.1)在制绒后的硅片正面进行低浓度硼扩散，扩散方阻为200ohm，表面浓度为1.0e 19atoms/cm 3，结深为0.4μm，形成轻掺杂层；
(2.2)采用LPCVD法在轻掺杂层上沉积非晶硅，形成厚度为200nm的非晶硅层；
(2.3)对非晶硅层进行激光开槽，以去除金属接触区域的非晶硅；
(2.4)在去除非晶硅后的金属接触区域进行高浓度硼扩散，扩散方阻为60ohm，表面浓度为3.0e 19atoms/cm 3，结深为1.0μm，形成重掺杂层；
(2.5)清洗，以去除非金属区域的非晶硅；
(3)刻蚀，以去除背面和边缘的硼硅玻璃；
(4)采用LPCVD法在硅片背面沉积厚度为1.0nm的氧化硅层和厚度为110nm的掺磷多晶硅层；
(5)退火；
(6)去PSG和RCA清洗，去除正面绕镀；
(7)在硅片正面沉积氧化铝，形成厚度为7nm的氧化铝钝化层；
(8)在氧化铝钝化层上沉积氮化硅，形成厚度为80nm的正面氮化硅层；
(9)在硅片背面沉积氮化硅，厚度为80nm的背面氮化硅层；
(10)经丝网印刷和烧结后，获得N型选择性发射极晶硅电池。
实施例4
一种制备N型选择性发射极晶硅电池的方法，包括以下步骤：
(1)在硅片表面制绒，形成金字塔绒面；
(2)选择性扩散：
(2.1)采用LPCVD法在制绒后的硅片正面沉积非晶硅，形成厚度为80nm的非晶硅层；
(2.2)对非晶硅层进行激光开槽，以去除金属接触区域的非晶硅；
(2.3)在去除非晶硅后的金属接触区域进行高浓度硼扩散，扩散方阻为60ohm，表面浓度为3.0e 19atoms/cm 3，结深为1.0μm，形成重掺杂层；
(2.4)清洗，以去除非金属区域的非晶硅；
(2.5)在清洗后的硅片正面进行低浓度硼扩散，扩散方阻为140ohm，表面浓度为1.2e 19atoms/cm 3，结深为0.6μm，形成轻掺杂层；
(3)刻蚀，以去除背面和边缘的硼硅玻璃；
(4)采用LPCVD法在硅片背面沉积厚度为1.0nm的氧化硅层和厚度为110nm的掺磷多晶硅层；
(5)退火；
(6)去PSG和RCA清洗，去除正面绕镀；
(7)在硅片正面沉积氧化铝，形成厚度为6nm的氧化铝钝化层；
(8)在氧化铝钝化层上沉积氮化硅，形成厚度为80nm的正面氮化硅层；
(9)在硅片背面沉积氮化硅，厚度为80nm的背面氮化硅层；
(10)经丝网印刷和烧结后，获得N型选择性发射极晶硅电池。
实施例5
一种制备N型选择性发射极晶硅电池的方法，包括以下步骤：
(1)在硅片表面制绒，形成金字塔绒面；
(2)选择性扩散：
(2.1)采用LPCVD法在制绒后的硅片正面沉积非晶硅，形成厚度为140nm的非晶硅层；
(2.2)对非晶硅层进行激光开槽，以去除金属接触区域的非晶硅；
(2.3)在去除非晶硅后的金属接触区域进行高浓度硼扩散，扩散方阻为70ohm，表面浓度为2.5e 19atoms/cm 3，结深为0.9μm，形成重掺杂层；
(2.4)清洗，以去除非金属区域的非晶硅；
(2.5)在清洗后的硅片正面进行低浓度硼扩散，扩散方阻为170ohm，表面浓度为1.2e 19atoms/cm 3，结深为0.5μm，形成轻掺杂层；
(3)刻蚀，以去除背面和边缘的硼硅玻璃；
(4)采用LPCVD法在硅片背面沉积厚度为1.0nm的氧化硅层和厚度为110nm的掺磷多晶硅层；
(5)退火；
(6)去PSG和RCA清洗，去除正面绕镀；
(7)在硅片正面沉积氧化铝，形成厚度为6nm的氧化铝钝化层；
(8)在氧化铝钝化层上沉积氮化硅，形成厚度为80nm的正面氮化硅层；
(9)在硅片背面沉积氮化硅，厚度为80nm的背面氮化硅层；
(10)经丝网印刷和烧结后，获得N型选择性发射极晶硅电池。
实施例6
一种制备N型选择性发射极晶硅电池的方法，包括以下步骤：
(1)在硅片表面制绒，形成金字塔绒面；
(2)选择性扩散：
(2.1)采用LPCVD法在制绒后的硅片正面沉积非晶硅，形成厚度为200nm的非晶硅层；
(2.2)对非晶硅层进行激光开槽，以去除金属接触区域的非晶硅；
(2.3)在去除非晶硅后的金属接触区域进行高浓度硼扩散，扩散方阻为90ohm，表面浓度为2.0e 19atoms/cm 3，结深为0.7μm，形成重掺杂层；
(2.4)清洗，以去除非金属区域的非晶硅；
(2.5)在清洗后的硅片正面进行低浓度硼扩散，扩散方阻为200ohm，表面浓度为1.0e 19atoms/cm 3，结深为0.4μm，形成轻掺杂层；
(3)刻蚀，以去除背面和边缘的硼硅玻璃；
(4)采用LPCVD法在硅片背面沉积厚度为1.0nm的氧化硅层和厚度为110nm的掺磷多晶硅层；
(5)退火；
(6)去PSG和RCA清洗，去除正面绕镀；
(7)在硅片正面沉积氧化铝，形成厚度为10nm的氧化铝钝化层；
(8)在氧化铝钝化层上沉积氮化硅，形成厚度为75nm的正面氮化硅层；
(9)在硅片背面沉积氮化硅，厚度为75nm的背面氮化硅层；
(10)经丝网印刷和烧结后，获得N型选择性发射极晶硅电池。
对比例1
一种制备N型晶硅电池发射极的方法，包括以下步骤：
(1)在硅片表面制绒，形成金字塔绒面；
(2)在制绒后的硅片正面进行硼扩散，扩散方阻为100ohm，表面浓度为1.2e 19atoms/cm 3，结深为0.8μm，形成掺杂层；
(3)刻蚀，以去除背面和边缘的硼硅玻璃；
(4)采用LPCVD法在硅片背面沉积厚度为1.0nm的氧化硅层和厚度为110nm的掺磷多晶硅层；
(5)退火；
(6)去PSG和RCA清洗，去除正面绕镀；
(7)在硅片正面沉积氧化铝，形成厚度为6nm的氧化铝钝化层；
(8)在氧化铝钝化层上沉积氮化硅，形成厚度为70nm的正面氮化硅层；
(9)在硅片背面沉积氮化硅，厚度为70nm的背面氮化硅层；
(10)经丝网印刷和烧结后，获得N型选择性发射极晶硅电池。
对比例2
一种制备N型选择性发射极晶硅电池的方法，包括以下步骤：
(1)在硅片表面制绒，形成金字塔绒面；
(2)选择性扩散：
(2.1)在制绒后的硅片正面进行低浓度硼扩散，扩散方阻为140ohm，表面浓度为1.2e 19atoms/cm 3，结深为0.6μm，形成轻掺杂层；
(2.2)采用热氧化法在轻掺杂层上沉积氧化硅，形成厚度为80nm的氧化硅层；
(2.3)对氧化硅层进行激光开槽，以去除金属接触区域的氧化硅；
(2.4)在去除氧化硅后的金属接触区域进行高浓度硼扩散，扩散方阻为60ohm，表面浓度为3.0e 19atoms/cm 3，结深为1.0μm，形成重掺杂层；
(2.5)清洗，以去除非金属区域的氧化硅；
(3)刻蚀，以去除背面和边缘的硼硅玻璃；
(4)采用LPCVD法在硅片背面沉积厚度为1.0nm的氧化硅层和厚度为110nm的掺磷多晶硅层；
(5)退火；
(6)去PSG和RCA清洗，去除正面绕镀；
(7)在硅片正面沉积氧化铝，形成厚度为6nm的氧化铝钝化层；
(8)在氧化铝钝化层上沉积氮化硅，形成厚度为70nm的正面氮化硅层；
(9)在硅片背面沉积氮化硅，厚度为70nm的背面氮化硅层；
(10)经丝网印刷和烧结后，获得N型选择性发射极晶硅电池。
对比例3
一种制备N型选择性发射极晶硅电池的方法，包括以下步骤：
(1)在硅片表面制绒，形成金字塔绒面；
(2)选择性扩散：
(2.1)采用热氧化法在制绒后的硅片正面沉积氧化硅，形成厚度为80nm的氧化硅层；
(2.2)对氧化硅层进行激光开槽，以去除金属接触区域的氧化硅；
(2.3)在去除氧化硅后的金属接触区域进行高浓度硼扩散，扩散方阻为60ohm，表面浓度为3.0e 19atoms/cm 3，结深为1.0μm，形成重掺杂层；
(2.4)清洗，以去除非金属区域的氧化硅；
(2.5)在清洗后的硅片正面进行低浓度硼扩散，扩散方阻为140ohm，表面浓度为1.2e 19atoms/cm 3，结深为0.6μm，形成轻掺杂层；
(3)刻蚀，以去除背面和边缘的硼硅玻璃；
(4)采用LPCVD法在硅片背面沉积厚度为1.0nm的氧化硅层和厚度为110nm的掺磷多晶硅层；
(5)退火；
(6)去PSG和RCA清洗，去除正面绕镀；
(7)在硅片正面沉积氧化铝，形成厚度为3nm的氧化铝钝化层；
(8)在氧化铝钝化层上沉积氮化硅，形成厚度为70nm的正面氮化硅层；
(9)在硅片背面沉积氮化硅，厚度为70nm的背面氮化硅层；
(10)经丝网印刷和烧结后，获得N型选择性发射极晶硅电池。
测试例
采用常规方法，将实施例1～6和对比例1～3制得的发射极制成N型晶硅电池，对电池的开路电压Voc、短路电流Isc和填充因子FF进行检测，结果见表1。
表1
  开路电压Voc/mV 短路电流Isc/mA 填充因子FF/％ 电池效率EFF/％
实施例1 703.6 11.190 83.15 23.88
实施例2 703.9 11.195 83.14 23.90
实施例3 704.5 11.198 83.19 23.94
实施例4 704.1 11.200 83.17 23.92
实施例5 704.5 11.211 83.14 23.95
实施例6 705.0 11.220 83.12 23.98
对比例1 701.3 11.153 83.10 23.71
对比例2 703.2 11.170 83.12 23.81
对比例3 703.7 11.185 83.15 23.87
分析表1数据，可以得出以下结论：
(1)对比例1采用一次掺杂获得普通发射极，实施例1和4采用本发明的方法获得选择性发射极。相较于对比例1而言，实施例1和4的电池开路电压、短路电流、填充因子有所增加，电池效率分别提升0.17％和0.21％。原因在于：在选择性发射极中，非金属接触区形成低表面浓度、浅PN结的发射极，降低少数载流子复合几率，提高载流子的收集率，减少电池的反向饱和电流，提高电池的开路电压和短路电流，并降低和金属浆料接触电阻，提升电池的填充因子；金属接触区形成高浓度、深PN结的发射极，降低金属浆料接触区的接触电阻，同时降低浆料烧穿PN的风险，提升电池的填充因子。
(2)实施例1和4采用非晶硅作为掩膜，对比例2和3采用氧化硅作为掩膜。相较于对比例2而言，实施例1的电池开路电压、短路电流、填充因子有所增加，从而电池效率提升0.09％；相较于对比例3而言，实施例4的电池开路电压、短路电流、填充因子有所增加，效率提升0.05％。原因在于：当采用氧化硅作为掩膜时，由于硼在氧化硅中的扩散速度比晶硅中快，易导致表面浓度的不可控，影响选择性发射极的性能；而当采用非晶硅层作为掩膜时，由于硼在非晶硅中的扩散很慢，因而能防止硼透过非晶硅层而导致形成的掺杂层中硼浓度不可控，有利于提高电池性能。
(3)实施例1采用“形成轻掺杂层→沉积掩膜→激光开槽→形成重掺杂层→去除掩膜”的顺序进行选择性扩散，实施例4则采用“沉积掩膜→激光开槽→形成重掺杂层→去除掩膜→形成轻掺杂层”的顺序。相较于实施例1而言，实施例4的电池开路电压、短路电流有所增加，电池效率提升了0.17％。原因在于：采用实施例4中的顺序，具有轻掺杂区的掺杂浓度和结深更可控的优点，能进一步提升开路电压和短路电流，工艺稳定性更好。
本发明中所用原料、设备，若无特别说明，均为本领域的常用原料、设备；本发明中所用方法，若无特别说明，均为本领域的常规方法。
以上所述，仅是本发明的较佳实施例，并非对本发明作任何限制，凡是根据本发明技术实质对以上实施例所作的任何简单修改、变更以及等效变换，均仍属于本发明技术方案的保护范围。

Claims (10)

  1. 一种用于制备N型选择性发射极晶硅电池的选择性扩散方法，其特征在于，包括以下步骤：
    (1)在制绒后的硅片正面进行低浓度硼扩散，形成轻掺杂层；
    (2)在轻掺杂层上沉积非晶硅，形成非晶硅层；
    (3)对非晶硅层进行激光开槽，以去除金属接触区域的非晶硅；
    (4)在去除非晶硅后的金属接触区域进行高浓度硼扩散，形成重掺杂层；
    (5)清洗，以去除非金属区域的非晶硅。
  2. 如权利要求1所述的选择性扩散方法，其特征在于，步骤(1)中，所述低浓度硼扩散的扩散方阻为140～200ohm，表面浓度为1.0e 19～1.5e 19atoms/cm 3，结深为0.3～0.6μm。
  3. 如权利要求1或2所述的选择性扩散方法，其特征在于，步骤(4)中，所述高浓度硼扩散的扩散方阻为60～100ohm，表面浓度为2.0e 19～3.0e 19atoms/cm 3，结深为0.6～1.0μm。
  4. 如权利要求1所述的选择性扩散方法，其特征在于，步骤(2)中，所述非晶硅层的厚度为80～200nm。
  5. 一种用于制备N型选择性发射极晶硅电池的选择性扩散方法，其特征在于，包括以下步骤：
    (I)在制绒后的硅片正面沉积非晶硅，形成非晶硅层；
    (II)对非晶硅层进行激光开槽，以去除金属接触区域的非晶硅；
    (III)在去除非晶硅后的金属接触区域进行高浓度硼扩散，形成重掺杂层；
    (IV)清洗，以去除非金属区域的非晶硅；
    (V)在清洗后的硅片正面进行低浓度硼扩散，形成轻掺杂层。
  6. 如权利要求5所述的选择性扩散方法，其特征在于，步骤(I)中，所述非晶硅层的厚度为80～200nm。
  7. 如权利要求5所述的选择性扩散方法，其特征在于，步骤(III)中，所述高浓度硼扩散的扩散方阻为60～100ohm，表面浓度为2.0e 19～3.0e 19atoms/cm 3，结深为0.6～1.0μm。
  8. 如权利要求5或7所述的选择性扩散方法，其特征在于，步骤(V)中，所述低浓度硼扩散的扩散方阻为140～200ohm，表面浓度为1.0e 19～1.5e 19atoms/cm 3，结深为0.3～0.6μm。
  9. 一种利用如权利要求1～8之一所述选择性扩散方法制备N型选择性发射极晶硅电池的方法，其特征在于，包括以下步骤：在采用所述选择性扩散方法完成选择性扩散后，通过刻蚀去除背面和边缘的硼硅玻璃，然后背面沉积氧化硅层和掺磷多晶硅层，退火处理和去绕镀，而后在硅片正面依次沉积氧化铝钝化层和正面氮化硅层，并在硅片背面沉积背面氮化硅层，经丝网印刷和烧结后，获得N型选择性发射极晶硅电池。
  10. 如权利要求9所述的方法，其特征在于，所述氧化铝钝化层的厚度为3～10nm，所述正面 氮化硅层的厚度为70～90nm，所述背面氮化硅层的厚度为70～90nm。
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