WO2023023732A1 - Codage de correction d'erreur sans circuit de retour staircase modifié - Google Patents

Codage de correction d'erreur sans circuit de retour staircase modifié Download PDF

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WO2023023732A1
WO2023023732A1 PCT/AU2022/050959 AU2022050959W WO2023023732A1 WO 2023023732 A1 WO2023023732 A1 WO 2023023732A1 AU 2022050959 W AU2022050959 W AU 2022050959W WO 2023023732 A1 WO2023023732 A1 WO 2023023732A1
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Min QIU
Jinhong Yuan
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Newsouth Innovations Pty Limited
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Publication of WO2023023732A1 publication Critical patent/WO2023023732A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/251—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with block coding
    • H—ELECTRICITY
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H—ELECTRICITY
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H—ELECTRICITY
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    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
    • H—ELECTRICITY
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H—ELECTRICITY
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    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
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    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/0048—Decoding adapted to other signal detection operation in conjunction with detection of multiuser or interfering signals, e.g. iteration between CDMA or MIMO detector and FEC decoder
    • H—ELECTRICITY
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    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0066—Parallel concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
    • H04L1/04—Arrangements for detecting or preventing errors in the information received by diversity reception using frequency diversity
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
    • H—ELECTRICITY
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding

Definitions

  • the present invention relates generally to a modified staircase forward error correction coding.
  • FEC Forward Error Correction
  • FIG. 1 An example of a conventional FEC coding is called the staircase FEC (shown in Fig. 1). The staircase FEC will be discussed hereinafter in relation to Fig. 1.
  • the symbol block decomposition and transposition enable the input and parity data of the preceding symbol block to be interwoven within the preceding symbol block. Such interweaving of the input and parity data allows the use of stronger component FEC codes, which in turn improves the overall forward error correction capability of the modified staircase FEC.
  • a method of generating a sequence of symbol blocks, the generated symbol blocks comprising data encoded with forward error correction (FEC) encoding comprising: decomposing one of the symbol blocks; transposing the decomposed symbol block; and generating a proceeding symbol block using the decomposed and transposed symbol block.
  • FEC forward error correction
  • a method of decoding a sequence of received symbol blocks, the received symbol blocks comprising data encoded with forward error correction (FEC) encoding comprising: decomposing one of the symbol blocks; transposing the decomposed symbol block; and determining whether a proceeding received symbol block is correct based on the transposed, decomposed symbol block.
  • FEC forward error correction
  • a computer program product including a computer readable medium having recorded thereon a computer program for implementing any one of the methods described above.
  • Fig. 1 shows a prior art arrangement for performing staircase forward error correction (FEC) coding
  • Fig. 2 shows an arrangement for performing a modified staircase forward error correction (FEC) coding according to the present disclosure
  • Fig. 3 is a flow diagram of a method of performing the modified staircase FEC shown in Fig. 2;
  • Fig. 4 is a flow diagram of a sub-process of generating symbol blocks of the modified staircase FEC of Fig. 3;
  • FIGs. 5 and 6 show illustrations of the symbol blocks of different indices being processed according to the sub-process of Fig. 4;
  • Figs. 7A and 7B show a flow diagram of a method of decoding symbol blocks that are generated using the modified staircase FEC coding of Figs. 2 to 6;
  • Figs. 8A and 8B form a schematic block diagram of a general purpose computer system upon which arrangements described can be practiced.
  • Fig. 9 is a flow diagram of a sub-process of generating symbol blocks of the modified staircase FEC of Fig. 3 when a coupling width is larger than 2;
  • Figs. 10A and 10B show a flow diagram of a method of decoding symbol blocks that are generated using the modified staircase FEC coding of Fig. 9.
  • Fig. 1 shows a conventional staircase FEC 100 having symbol blocks Bi, where each symbol block B i is formed by input data K i and parity data P i (i.e. , the redundant data).
  • B 0 is a symbol block having predetermined symbols.
  • a combination of two symbol blocks B i forms the codewords of component FEC code C, such that of each row in [B T i-1 , B i ] or each column in [B i-1 , B T i ] is a codeword of component FEC code C.
  • component FEC code C is a set of all codewords generated by the FEC encoding.
  • a sequence of symbol blocks Bi , B2, ... are subsequently transmitted via a communication channel and received by a decoder.
  • Each symbol block B i is a two-dimensional array of m by m.
  • Each codeword of component FEC code C has a length of n, where the information in the codeword has a length of k.
  • the parity data P i accordingly is a two-dimensional array of m by n-k.
  • the input data K i is a two-dimensional array of m by k-m.
  • the input data K i is concatenated with the transpose of the preceding symbol block B T i-1 .
  • Each row of the concatenated data i.e., [B T i-1 , K i ]
  • the parity data P i can also be equivalently obtained by processing the encoding method on each column of the transpose of the concatenated data (i.e., [B T i-1 , K i ] T ).
  • each row in [B T i-1 , B i ] or each column in in [B i -i , B T j] is a codeword of the FEC component code C.
  • the transpose of the symbol blocks B i with even indices together with the symbol blocks B i with odd indices results in a staircase-like structure shown in Fig. 1.
  • Fig. 2 shows an illustration of a modified staircase FEC 200 in accordance with the present disclosure.
  • the preceding symbol block B i-1 is used to encode a current symbol block B i .
  • the preceding symbol block B i .1 is first decomposed and transposed before being used to obtain the parity data.
  • the decomposition of a preceding symbol block B i-1 involves dividing the preceding symbol block B i-1 into sub-blocks B i-1 , 1, B i-1 , 2, ... , B i-1 , q and transposing each sub- block.
  • the arrangement of dividing the preceding symbol block B i-1 and transposing each sub-block will be used in describing the modified staircase FEC 200.
  • the sub- blocks indicated by dashed lines i.e. , the predetermined symbol blocks Oi and the predetermined symbol blocks Bo
  • the predetermined symbol blocks Oi and the predetermined symbol blocks Bo are involved in the encoding but are not transmitted.
  • the modified staircase code 200 generates component FEC code Cj.
  • the component FEC code Ci is the set of all codewords generated by the FEC encoding, where each codeword has length ni, predetermined symbol block length ei, data length K i ei, and parity data length ni- K. i
  • Each row of a combination of a symbol block B i , the rearranged preceding symbol block B i-1 , and a predetermined symbol block 0; (or each column of the transpose of that combination) is a codeword of the component FEC code Cj.
  • the predetermined symbol block 0 includes predetermined symbols that are known by the encoder-decoder pair.
  • predetermined symbol block is a zero matrix, where all the predetermined symbols are zero.
  • component FEC codes include but not limited to Bose-Chaudhuri-Hocquenghem codes (BCH) codes, low-density parity-check (LDPC) codes, turbo codes, polar codes, Reed- Solomon (RS) codes, and Hamming codes.
  • BCH Bose-Chaudhuri-Hocquenghem codes
  • LDPC low-density parity-check
  • RS Reed- Solomon
  • the modified staircase FEC 200 has ten parameters that can be adjusted to set the dimension (i.e. , the number of rows and columns) of data block K i , and parity data block P i and, subsequently the symbol block B i . These ten parameters are and e 2 . These ten parameters are positive integers. For parameters there are further requirements where rr?i must be divisible by and must be divisible by The parameters qi , q2 are called symbol block index as these parameters determine the number of sub-blocks decomposed from the preceding symbol block B i-1 , and subsequently the number of transposed sub-blocks and the determination of the parity data (which will be described hereinafter).
  • Each symbol block B i is a two-dimensional array. When / is an odd number, B i is an by m1 matrix filled with symbols.
  • the data block K i is an matrix.
  • the parity data P i is an matrix.
  • C 1 will be used to indicate component FEC code Ci when / is an odd number.
  • m indicates the length of a codeword of the component FEC code C 1 .
  • ki indicates the length of the codeword of C 1 without the parity data P i .
  • ei indicates the length of the predetermined symbol block Oiwhen / is an odd number. Accordingly, the codeword length of C 1 satisfies
  • B i is an rm/qi by m2 matrix filled with rm rm/qi symbols.
  • the data K i is an matrix.
  • the parity data P i is an matrix.
  • C2 will be used to indicate component FEC code Ci when / is an even number.
  • m indicates the length of a codeword of the component FEC code C2.
  • k2 indicates the length of the codeword of the component FEC code C2 without the parity data P i .
  • e 2 indicates the length of the predetermined symbol block Oi when / is an even number. Accordingly, the codeword length of component FEC code C2 satisfies The predetermined symbol block Oi can be different dependent on whether / is an odd or even number.
  • the input data K i is concatenated with a decomposed and transposed preceding symbol block B i-1 and the symbol block Oi.
  • Each row of the concatenated data i.e., predetermined symbol block Oi + decomposed and transposed preceding symbol block B i .i+ data K i
  • the encoding method include but not limited to BCH encoding, turbo encoding, LDPC encoding, polar encoding, RS encoding and Hamming encoding.
  • the modified staircase FEC 200 will be described in further detail in relation to Figs. 3 to 6 hereinafter.
  • the preceding symbol block Bi is subdivided into sub-blocks Bi ,1 , Bi , 2 , and B1,3.
  • Sub-blocks Bi ,1 , Bi , 2 , and B1,3 are then rearranged by moving sub- blocks B1 ,2 and B1,3 below sub-block B1 ,1.
  • the rearranged sub-blocks B1 ,1 , B1 , 2 , and B1,3 are then transposed and concatenated with data K2 and the symbol block O 2 to obtain the parity data P 2 .
  • Symbol block 82 is then obtained by combining the data K2 with the parity data P 2 .
  • a codeword of component FEC code C2 relating to symbol block B 2 is then a column of the symbol block O 2 , the transposed and rearranged sub-blocks Bi ,1 , Bi , 2 , and Bi ,3, the data K 2 , and the parity data P 2 .
  • FIG. 2 The rearrangement of sub-blocks shown in Fig. 2 is an example rearrangement. There are other rearrangements such as permutation, and the like.
  • Fig. 3 shows a flow diagram of a method 300 for generating symbol blocks Bi , B 2 ,... , BL for received input data.
  • the method 300 is a software application program 1333 executable within the computer system 1300 (see the discussion below in relation to Figs. 8A and 8B).
  • sub-process 400 a sequence of symbol blocks Bi , B2,... , BL associated with the sequence of input data K i is generated.
  • the generated sequence of symbol blocks Bi , B2,... , BL can then be sent via the communication channel.
  • the method 300 concludes at the conclusion of the sub-process 400.
  • Fig. 4 shows a flow diagram of the sub-process 400.
  • Sub-process 400 is a software application program 1333 executable within the computer system 1300 (see the discussion below in relation to Figs. 8A and 8B).
  • Sub-process 400 commences at step 402 by initialising the predetermined symbol block Bo.
  • An example of the predetermined symbols Bo is a zero matrix.
  • Sub-process 400 proceeds from step 402 to step 404.
  • step 404 sub-process 400 determines whether the index i is an even or odd number. If the index i is an odd number, then sub-process 400 proceeds from step 404 to step 406A. Otherwise, if the index i is an even number, sub-process 400 proceeds from step 404 to step 406B.
  • step 406A sub-process 400 divides the preceding symbol block B i-1 .
  • symbol block Bo which is the preceding symbol block B i-1 and is initialised at step 402
  • q2 is used as the index i is an odd number.
  • Bo is divided into 2 sub-blocks B 0 ,1 and Bo, 2.
  • Fig. 5(a) shows an example of a preceding symbol block B i-1 when i is an odd number.
  • the preceding symbol block B i-1 is an rm/qi by m2 matrix, as the index i of the preceding symbol block is an even number (see the discussion in relation to Fig. 2 above).
  • Each sub-block B i-1 ,1 and Bi-1 ,2 is an m1/q1 by m2/ q2 matrix.
  • Sub-process 400 proceeds from step 406A to step 408A once the preceding symbol block B i .1 has been subdivided.
  • each of the sub-blocks is transposed.
  • the transposed sub-blocks are represented by Fig. 5(c) shows an illustration of the sub-blocks B i-1 ,I and B i-1 ,2 being transposed.
  • Sub-process 400 proceeds from step 408A to step 410A once all sub-blocks has been transposed.
  • step 410A the transposed sub-blocks are rearranged.
  • the rearrangement is a permutation function of
  • the permutation function TT(.) permutes the row and column position of matrix
  • Step 410A of sub-process 400 is an optional process. If Step 410A is not performed, sub-process 400 proceeds from step 408A to step 412A. Otherwise, sub-process 400 proceeds from step 408A to step 410A and then to step 412A.
  • step 412A the transposed sub-blocks are concatenated with the predetermined symbol block Oi and the data K i to obtain a concatenated block of
  • the predetermined symbol block Oi is an rri2/q2 by ei matrix and includes predetermined symbols that are known to the encoder-decoder pair.
  • the data K i is an matrix. Accordingly, the concatenated block is an by matrix.
  • Fig. 5(d) shows the concatenated block Sub-process 400 proceeds from step 412A to 414A.
  • the parity data P i for the concatenated block is determined.
  • the parity data Pi is obtained for each row of the concatenated block by performing FEC encoding of C 1 on that row.
  • the parity data Pi can be equivalently obtained by performing FEC encoding of C 1 on each column of the matrix transpose of the concatenated block .
  • examples of the FEC encoding include but not limited to BCH encoding, RS encoding, LDPC encoding, Hamming encoding, turbo encoding, and polar encoding. Accordingly, the codeword matrix is represented by where each row of Ci is a codeword of C 1 .
  • Fig. 5(e) shows the concatenated block being combined with the obtained parity data P i .
  • Each row of the combined concatenated block and parity data P i forms a codeword of component FEC code C 1 .
  • Sub-process 400 proceeds from step 414A to step 415A.
  • step 415A sub-process 400 generates a symbol block B i for the associated index /.
  • the symbol block B i is a combination of the data K i and the parity data P i .
  • the data K i is embedded within the generated symbol block B i .
  • Fig. 5(f) shows the data K i being combined with the parity data P i .
  • Sub-process 400 proceeds from step 415A to step 417.
  • sub-process 400 concludes.
  • the symbol blocks B i obtained at steps 415A and 415B (which correspond to the input data received at step 302) are sent via the communication channel.
  • the predetermined symbol block Oi can be removed to reduce the amount of data being transmitted.
  • the decoder provides the symbol block Oi when decoding the received symbol blocks B i (without the symbol block Oi).
  • step 406B sub-process 400 divides the preceding symbol block B i-1 .
  • symbol block B1 (which is the preceding symbol block B i-1 ) is divided into q1 sub- blocks.
  • q 1 is used as the index i is an even number.
  • B1 is divided into 3 sub-blocks B1,1 , B1, 2 , and B1,3.
  • Fig. 6(a) shows an example of a preceding symbol block B i-1 when i is an even number.
  • the preceding symbol block B i-1 is an matrix, as the index i of the preceding symbol block is an even number (see the discussion in relation to Fig. 2 above).
  • Fig. 6(b) then shows the preceding symbol block B i-1 being divided into 3 sub-blocks, as Each sub-block is an by mat rix.
  • Sub-process 400 proceeds from step 406B to step 408B once the preceding symbol block B i .1 has been subdivided.
  • each of the sub-blocks is transposed.
  • the transposed sub-blocks are represented by Fig. 6(c) shows an illustration of the sub-blocks being transposed.
  • Sub-process 400 proceeds from step 408B to step 410B once all sub-blocks has been transposed.
  • step 410B the transposed sub-blocks are rearranged.
  • the rearrangement is a permutation function of
  • the permutation function TT(.) permutes the row and column position of matrix
  • Step 410B of sub-process 400 is an optional process. If Step 410B is not performed, sub-process 400 proceeds from step 408B to step 412B. Otherwise, sub-process 400 proceeds from step 408A to step 410B and then to step 412B.
  • step 412B the transposed sub-blocks are concatenated with the predetermined symbol block Oi and the data K i to obtain a concatenated block of
  • the predetermined symbol block Oi is an by e2 matrix and includes predetermined symbols that are known to the encoder-decoder pair.
  • the data K i is an matrix. Accordingly, the concatenated block is an by matrix.
  • Fig. 6(d) shows the concatenated block
  • Sub-process 400 proceeds from step 412B to 414B.
  • step 414B the parity data Pi for the concatenated block is determined.
  • the parity data Pi is obtained for each row of the concatenated block by performing FEC encoding of component FEC code C2 on that row.
  • the parity data Pi can be equivalently obtained by performing FEC encoding of component FEC code C2 on each column of the matrix transpose of the concatenated block
  • examples of the FEC encoding include but not limited to BCH encoding, RS encoding, LDPC encoding, Hamming encoding, turbo encoding, and polar encoding. Accordingly, the codeword matrix is represented by where each row of Ci is a codeword of component FEC code C 2 .
  • Sub-process 400 proceeds from step 414B to step 415B.
  • Fig. 2 shows that the codewords of component FEC code C2 and its associated symbol blocks Bi (when i is an even number) are in arranged in columns.
  • the column arrangement is for illustration only, to demonstrate the staircase-like structure of the modified staircase FEC code.
  • the codeword matrix is represented by Performing a matrix transpose leads to
  • the matrix transpose (when i is an even number) combined with the codeword matrix Ci (when i is an odd number) gives the illustration in Fig. 2. As described hereinbefore, the sub-blocks indicated by dashed lines are involved in the encoding but are not transmitted. It is unnecessary to perform the matrix transpose (when i is an even number) when generating the symbol blocks Bi.
  • step 415B sub-process 400 generates a symbol block Bi for the associated index i.
  • the symbol block Bi is a combination of the data Ki and the parity data Pi.
  • Fig. 6(f) shows the data Ki being combined with the parity data Pi.
  • Sub-process 400 proceeds from step 415B to step 417, which is already described hereinbefore.
  • the codeword length of such a modified staircase FEC code 200 is In contrast, the codeword length of the conventional staircase FEC code 100 is when L symbol blocks are transmitted.
  • Both the modified staircase FEC code 200 and conventional staircase FEC code 100 have the same code rate if the encoding codes used are the same. Therefore, the modified staircase FEC code 200 has shorter codeword length in comparison to the conventional staircase codes.
  • the modified staircase FEC code 200 can therefore employ encoding codes with stronger error correction capability to achieve improved error correction performance, while having a similar codeword length and the same code rate as the conventional staircase FEC code 100.
  • the modified staircase FEC code 200 provides a similar error correction capability and achieves the same code rate as the conventional staircase FEC code 100 but with shorter codeword length, thereby reducing the latency caused by transmitting the codewords.
  • the overall code rate of the modified staircase FEC code 200 is 0.9407.
  • Each symbol block B i is filled with 260100 bits, where B i is a 255 by 1020 binary matrix. When / is an odd number, K i is a 255 by 965 binary matrix and P i is a 255 by 54 binary matrix. When / is an even number, K i is a 255 by 954 binary matrix and P i is a 255 by 65 binary matrix.
  • the overall code rate of the modified staircase FEC code 200 is 0.9303.
  • the symbol block B i is filled with 193041 bits, where B i is a 241 by 801 binary matrix, K i is a 241 by 736 binary matrix and P i is a 241 by 65 binary matrix.
  • the symbol block B i is filled with 257388 bits, where B i is a 267 by 964 binary matrix, K i is a 267 by 910 binary matrix and P i is a 267 by 54 binary matrix.
  • Figs. 7A and 7B show a flow diagram of a method 800 of decoding a sequence of received symbol blocks Yj to obtain the input data K i .
  • the method 800 is a software application program 1333 executable within the computer system 1300 (see the discussion below in relation to Figs. 8A and 8B).
  • the method 800 commences at step 802 by receiving a sequence of symbol blocks Yj.
  • the symbol blocks Bi are transmitted but not the predetermined symbol block Oi.
  • the decoder also has a parameter called decoding window size W, where 2 ⁇ W ⁇ L.
  • the decoding window W sets the number of received symbol blocks Yj to be considered when performing the decoding.
  • the decoder outputs YL-W+I , ... YL based on the received last W symbol blocks YL-W+I , ... YL.
  • the window size W can be adjusted to adapt to specific latency and performance requirement. When the window size W is large, the decoding performance is better but the latency is higher compared to when the window size W is smaller.
  • the method 800 proceeds from step 802 to step 804.
  • the decoder can choose to operate either in forward scheduling or backward scheduling.
  • forward scheduling among the W received symbol blocks is decoded first, followed by
  • backward scheduling among the W received symbol blocks is decoded first, followed by
  • step 805 the method 800 determines whether (/ + w -1) is an even or odd number. is the w-th symbol block among the W received symbol blocks Y,...,Yj+w-i in a decoding window with size W and 1 ⁇ w ⁇ W. If (/ + w -1) is an even number, then the method 800 proceeds from step 805 to step 806A. Otherwise, if (/ + w-1) is an odd number, the method 800 proceeds from step 805 to step 806B.
  • step 806A the preceding symbol block Yj +w -2 is divided into qi sub-blocks is used as the index of the current symbol block is an even number.
  • the method 800 proceeds from step 806A to step 810A.
  • step 810A each of the sub-block of the preceding symbol block is transposed.
  • the transposed sub-blocks are represented by is an matrix. Therefore, by rri2qi/q2 matrix. If the optional rearrangement step 410A or 41 OB is performed, then the transposed sub-blocks also need to be rearranged accordingly.
  • the method 800 proceeds from step 810A to 812A.
  • step 812A the method 800 constructs a concatenated symbol block
  • the concatenated symbol block is a combination of the predetermined symbol block the transposed sub-blocks of step 810A, and the symbol block .
  • the predetermined symbol block is known by the decoder, as discussed hereinbefore in relation to steps 412A and 412B.
  • the symbol block is by e2 matrix, while the symbol block is an matrix.
  • the concatenated symbol block is an by matrix.
  • the method 800 proceeds from step 812A to 814A.
  • step 814A the method 800 calculates a first syndrome block of the concatenated symbol block and a first index set associated with the concatenated symbol block
  • the first syndrome block is calculated using the equation: where H2 is the parity-check matrix of the component FEC code C2.
  • the parity-check matrix H2 is an n2-k2 by n2 matrix related to the encoding used to obtain the parity data P i .
  • a vector c is a codeword of component FEC code C2 if it satisfies Syndrome block is an by matrix.
  • the first index set is calculated using the equation where s r is the r-th row of If the first syndrome block , the method 800 then proceeds from step 814A to 816A. Otherwise, if the first syndrome block , the method 800 skips the subsequent steps 816A and 818A such that the method 800 effectively proceeds from step 814A to step 820.
  • step 816A the r-th row of the concatenated symbol block is decoded by a component FEC decoder, which corresponds to the FEC encoder used in the sub-process 400.
  • the FEC decoder uses and the first index set which are computed in step 814A.
  • Examples of component FEC decoders include but not limited to BCH decoding, turbo decoding, polar decoding, LDPC decoding, Hamming decoding, and RS decoding.
  • the component FEC decoder returns a decoded sequence.
  • the decoder of the component FEC code C2 can correct up to t2 errors. If the number of errors in a row of the concatenated symbol block is no larger than t2, the decoded sequence is correct. Otherwise, the decoded sequence is incorrect.
  • a decoded symbol block is obtained by the FEC decoder, where each row in is the decoded sequence corresponding to a corresponding row in The method 800 proceeds from step 816A to 818A.
  • step 818A the method 800 calculates a second syndrome block and a second index set based on the decoded symbol block
  • the second syndrome block is calculated using the equation:
  • the second index set is calculated using the equation: where is the r-th row of the second syndrome block is the r-th row of decoded symbol block is the r-th row of predetermined symbol block and are the sub-vectors by taking the first e2 elements of and respectively.
  • the method 800 then proceeds from step 818A to 819A.
  • step 819A the method 800 updates the received symbol blocks and dependent on the r-th rows of the decoded symbol block that have zero syndrome (i.e. , in the second syndrome block and no errors in the first e2 symbols (i.e., where and the second index set are determined in step 818A. Having a zero syndrome in the second syndrome block means that the particular row of the decoded symbol block is a valid codeword of component FEC code C2.
  • step 819A determines whether the received symbol blocks and are correct and, if incorrect, then rectifies the received symbol blocks symbol blocks and accordingly. The method 800 proceeds from step 819A to step 820.
  • step 820 Before describing step 820, the corresponding steps 806B to 818B will be described first.
  • step 806B the preceding symbol block Yj +W .2 is divided into q2 sub-blocks is used as the index of the current symbol block i+w-1 is an odd number.
  • the method 800 proceeds from step 806B to step 810B.
  • step 81 OB each of the sub-blocks of the preceding symbol block is transposed.
  • the transposed sub-blocks are represented by is an mi/qi by m2 matrix. Therefore, is an rri2/q2 by miq2/qi matrix. If the optional rearrangement step 410A or 410B is performed, then the transposed sub-blocks also need to be rearranged accordingly.
  • the method 800 proceeds from step 810B to 812B.
  • step 812B the method 800 constructs a concatenated symbol block
  • the concatenated symbol block is a combination of the predetermined symbol block the transposed sub-blocks of step 810B, and the symbol block Accordingly,
  • the predetermined symbol block is known by the decoder, as discussed hereinbefore in relation to steps 412A and 412B.
  • the symbol block is matrix, while the symbol block is an by m1 matrix.
  • the concatenated symbol block is an matrix.
  • the method 800 proceeds from step 812B to 814B.
  • step 814B the method 800 calculates a first syndrome block of the concatenated symbol block and a first index set associated with the concatenated symbol block
  • the first syndrome block is calculated using the equation: where Hi is the parity-check matrix of the component FEC code C 1 .
  • the parity-check matrix Hi is an ni-ki by m matrix related to the encoding used to obtain the parity data P i .
  • Syndrome block is an rri2/q2 by matrix.
  • the first index set is calculated using the equation where s r is the r-th row of If the first syndrome block the method 800 then proceeds from step 814B to 816B. Otherwise, if the first syndrome block , the method 800 skips the subsequent steps 816B and 818B such that the method 800 effectively proceeds from step 814B to step 820.
  • step 816B the r-th row of the concatenated symbol block is decoded by a component FEC decoder, which corresponds to the FEC encoder used in the sub-process 400.
  • the FEC decoder uses r and the first index set which are computed in step 814B.
  • Examples of component FEC decoders include but not limited to BCH decoding, turbo decoding, polar decoding, LDPC decoding, Hamming decoding, and RS decoding.
  • the component FEC decoder returns a decoded sequence.
  • the decoder of the component FEC code C 1 can correct up to ti errors.
  • a decoded symbol block is obtained by the FEC decoder, where each row in the decoded symbol block is the decoded sequence corresponding to a corresponding row in .
  • the method 800 proceeds from step 816B to 818B.
  • step 818B the method 800 calculates a second syndrome block and a second index set based on the decoded symbol block
  • the second syndrome block is calculated using the equation:
  • the second index set is calculated using the equation: where is the r-th row of the second syndrome block is the r-th row of decoded symbol block is the r-th row of predetermined symbol block r (l: e£) and are the sub-vectors by taking the first ei elements of d r and o r , respectively.
  • the method 800 then proceeds from step 818B to 819B.
  • step 819B the method 800 updates the received symbol blocks and dependent on the r-th rows of the decoded symbol block that have zero syndrome (i.e. , in the second syndrome block and no errors in the first ei symbols (i.e., where and the second index set are determined in step 818B. Having a zero syndrome in the second syndrome block means that the particular row of the decoded symbol block is a valid codeword of component FEC code C 1 .
  • step 819B determines whether the received symbol blocks 2 and are correct and, if incorrect, then rectifies the received symbol blocks symbol blocks and accordingly.
  • the method 800 proceeds from step 819B to step 820.
  • the method 800 determines whether predetermined requirements of the decoding process are met.
  • the predetermined requirement is the number of times I that a cycle of steps 806A/806B to 820 has been performed. If the number of cycle I ⁇ Imax, then the method 800 determines that the predetermined requirement is not met. The method 800 then increases the number of cycle I by 1 .
  • the method 800 determines whether the syndrome blocks The determination that the syndrome block confirms that the decoding of the last W received blocks YL-W+I , ... ,YL is successful.
  • the predetermined requirements can be combined.
  • the decoder performs either forward scheduling or backward scheduling when processing the received symbol blocks within the decoding window W.
  • the method 800 sets the decoder to perform backward scheduling regardless whether the decoder is initially set to perform forward scheduling or backward scheduling. Accordingly, in a first cycle, the decoder performs forward scheduling for a first group (as determined by the size of the decoding window W) of received symbol blocks and performs backward scheduling in subsequent cycles for the subsequent groups of the received symbol blocks. Alternatively, the decoder performs backward scheduling in all cycles for all groups of the received symbol blocks.
  • step 826 the method 800 determines whether there are remaining received data symbols Yi,...Yi+w-1 to process. In one arrangement, the determination is performed by determining whether the index iL-W+1 , where L is the last index (see step 802 above). If i ⁇ L- W+1 (YES), then the method 800 determines that there are remaining data symbols Yi,... Y+w-1 to process. The method 800 then increases the index i by 1. The method 800 then proceeds from step 826 to step 805. Otherwise (i.e., i>L-W+1) (NO), the method 800 concludes.
  • the modified staircase FEC codes can be extended by increasing the number of coupled symbol blocks B i .
  • the modified staircase FEC code uses a preceding symbol block B i-1 to encode the current symbol block B i , meaning two symbol blocks B i are coupled.
  • the number of symbol blocks B i coupled together is called a coupling width U, such that an amount II of the symbol blocks B i are correlated.
  • U-1 sub-blocks from U-1 preceding symbol blocks B i +u-i,... ,B i-1 are used to obtain the current symbol block B i .
  • the encoding process is the sub-process 400.
  • a component FEC code Ci is the set of all codewords generated by its corresponding FEC encoding for the modified staircase code. Each codeword has length ni, predetermined symbol length ei, data length K- i ei and parity data length ni-K. i Each row of a combination of a symbol block B i , the rearranged sub-blocks of preceding symbol blocks B i +u-i,... ,B i .i, and a predetermined symbol block Oi or each column of the transpose of that combination is a codeword of the component FEC code Ci.
  • Fig. 9 shows a flow diagram of sub-process 500.
  • Sub-process 500 is a software application program 1333 executable within the computer system 1300 (see the discussion below in relation to Figs. 8A and 8B).
  • Sub-process 500 commences at step 502 by initialising predetermined symbol block Bo,... ., Bu-2. Examples of the predetermined symbols blocks Bo,... ., BU-2 are zero matrices.
  • Sub-process 500 proceeds from step 502 to step 504.
  • each of the sub-blocks of the preceding symbol blocks is transposed.
  • the transposed sub-blocks are represented by
  • the transposition of the sub-blocks can be followed with rearrangement of the transposed sub-blocks (see steps 410A and 410B above).
  • Sub-process 500 then proceeds from step 506 to step 507.
  • step 507 sub-process 500 recombines the transposed sub-blocks of each of the preceding symbol blocks For example, sub-blocks are recombined into B T ,- U+I . Therefore, the recombined, preceding symbol blocks are Sub-process 500 then proceeds from step 507 to step 508.
  • step 508 each of the recombined, preceding symbol blocks is divided into U-1 sub-blocks of size m/(U-1) by m/q such that Sub-process 500 then proceeds from step 508 to step 510.
  • step 510 sub-process 500 determines whether the index / is an even or odd number. If the index / is an odd number, then sub-process 500 proceeds from step 510 to step 511 A. Otherwise, if the index / is an even number, sub-process 500 proceeds from step 510 to step 511 B.
  • step 511A the l-th transposed sub-blocks obtained at step 508 from where , are concatenated with the predetermined symbol block Oi and the data K i to obtain a concatenated block of
  • the predetermined symbol block Oi is an m/q by ei matrix (as i is an odd number) and includes predetermined symbols that are known to the encoder-decoder pair.
  • the data K i is an m/q by matrix. Accordingly, the concatenated symbol block is an matrix.
  • Sub-process 500 proceeds from step 511A to step 512A.
  • step 512A the parity data P i for the concatenated block is determined.
  • FEC encoding of component FEC code C 1 is performed as the index i is an odd number.
  • the parity data P i is obtained for each row of the concatenated block by performing FEC encoding of component FEC code C 1 on that row.
  • examples of the FEC encoding include but not limited to BCH encoding, RS encoding, LDPC encoding, Hamming encoding, turbo encoding, and polar encoding. Accordingly, the codeword matrix is represented by where each row of C; is a codeword of component FEC code C 1 .
  • Sub-process 500 proceeds from step 512A to step 514A.
  • step 514A sub-process 500 generates a symbol block B i for the associated index i.
  • the symbol block B i is a combination of the data K i and the parity data P i .
  • Sub-process 500 proceeds from step 514A to step 515.
  • the predetermined symbol block Oi can be removed to reduce the amount of data being transmitted.
  • the decoder provides the symbol block Oi when decoding the received symbol blocks B i (without the symbol block Oi).
  • the predetermined symbol block Oi is an m/q by e 2 matrix (as i is an even number) and includes predetermined symbols that are known to the encoder-decoder pair.
  • the data K i is an m/q by k2-m-e2 matrix. Accordingly, the concatenated symbol block is an m/q by k2 matrix.
  • Sub-process 500 proceeds from step 511 B to step 512B.
  • step 512B the parity data P i for the concatenated block is determined.
  • FEC encoding of component FEC code C2 is performed as the index / is an even number.
  • the parity data P i is obtained for each row of the concatenated block by performing FEC encoding of component FEC code C2 on that row.
  • examples of the FEC encoding include but not limited to BCH encoding, RS encoding, LDPC encoding, Hamming encoding, turbo encoding, and polar encoding. Accordingly, the codeword matrix is represented by where each row of C; is a codeword of component FEC code C 1 .
  • Sub-process 500 proceeds from step 512B to step 514B.
  • step 514B sub-process 500 generates a symbol block B i for the associated index /.
  • the symbol block B i is a combination of the data K i and the parity data P i .
  • Sub-process 500 proceeds from step 514B to step 515, which is already described hereinbefore.
  • the modified staircase FEC code has a coupling width II of greater than 2 and the encoding is performed by sub-process 500.
  • the decoding of such a modified staircase FEC code is performed by a decoding method 900 (shown in Fig. 10).
  • the method 900 is a software application program 1333 executable within the computer system 1300 (see the discussion below in relation to Figs. 8A and 8B).
  • the method 900 commences at step 902 by receiving a sequence of symbol blocks Yj.
  • the symbol blocks B i are transmitted, but not the predetermined symbol block Oi.
  • the decoder also has a parameter called decoding window size W, where ll ⁇ W ⁇ L.
  • the decoding window W sets the number of received symbol blocks Yj to be considered when performing the decoding.
  • the decoder receives symbol blocks (or equivalently is the w-th symbol block among the W received symbol blocks Y,...,Y+w-i in a decoding window with size W and 1 ⁇ w ⁇ W) and output Yj.
  • step 902 The method 900 proceeds from step 902 to step 904.
  • step 904 the predetermined symbol blocks are initialised based on the received symbol blocks Y.
  • Step 904 also initialises syndrome blocks because their associated symbol blocks are predetermined and known by the decoder. The values of syndrome blocks are used for improving the decoding reliability.
  • each row of a combination of three symbol blocks Oi, sub-blocks of B i .u+1,... , B i .1 and B i is a codeword of component FEC code Ci.
  • the parameters m, q, ni, ki, n2, k2, ei , and e2as well as the types of component FEC codes C 1 and C2 are known by the decoder.
  • the method 900 proceeds from step 904 to 905.
  • the decoder can choose to operate either in forward scheduling or backward scheduling.
  • forward scheduling among the W received symbol blocks is decoded first, followed by
  • backward scheduling among the W received symbol blocks is decoded first, followed by
  • step 905 each of the preceding symbol blocks is divided into q sub- blocks of size m/q by m/q, The method 900 proceeds from step 905 to step 906.
  • each of the sub-blocks of the preceding symbol block is transposed.
  • the transposed sub-blocks are represented by 2,q].
  • Each of the preceding symbol blocks is an m/q by m matrix. Therefore, each of the sub-blocks transposed preceding symbol blocks is still an m/q by m matrix. If the optional rearrangement step is performed after step 506 is performed, then the transposed sub-blocks also need to be rearranged accordingly.
  • the method 900 proceeds from step 906 to 907.
  • step 907 the method 900 recombines the transposed sub-blocks of each of the preceding symbol blocks For example, sub-blocks are recombined into Therefore, the recombined, preceding symbol blocks are The method 900 then proceeds from step 907 to step 908.
  • step 908 each of the recombined, preceding symbol blocks are divided into U-1 sub-blocks of size m/(U-1) by m/q such that The method 900 then proceeds from step 908 to step 909.
  • step 909 the method 900 determines whether (/ + w -1) is an even or odd number. If (/ + w -1) is an even number, then the method 900 proceeds from step 909 to step 910A. Otherwise, if (/ + w -1) is an odd number, the method 900 proceeds from step 909 to step 910B.
  • step 910A the method 900 determines a concatenated symbol block
  • the predetermined symbol block is known by the decoder, as discussed hereinbefore in relation to step 511 A.
  • the predetermined symbol block is an m/q by e2 matrix as is an even number, while the symbol block is an m/q by m matrix.
  • the concatenated symbol bloc is an m/q by n 2 matrix.
  • the method 900 proceeds from step 910A to 911 A.
  • step 911A the method 900 calculates a first syndrome block of the concatenated symbol block and a first index set associated with the concatenated symbol block
  • the first syndrome block is calculated using the equation: where H2 is the parity-check matrix of the component FEC code C2.
  • the parity-check matrix H2 is an n2-k2 by n2 matrix related to the encoding used to obtain the parity data P i .
  • the first syndrome block Sj+ w -i is an m/q by n2-k2 matrix.
  • the first index set is calculated using the equation where s r is the r-th row of If the first syndrome block the method 900 then proceeds from step 911A to 912A. Otherwise, if the first syndrome block the method 900 then proceeds from step 911 A to step 915.
  • step 912A the r-th row of the concatenated symbol block is decoded by a component FEC decoder, which corresponds to the FEC encoder used in the sub-process 800.
  • the FEC decoder uses and the first index set which are computed in step 911 A.
  • Examples of component FEC decoders include but not limited to BCH decoding, turbo decoding, polar decoding, LDPC decoding, Hamming decoding, and RS decoding.
  • the component FEC decoder returns a decoded sequence.
  • the decoder of the component FEC code C2 can correct up to t2 errors. If the number of errors in a row of the concatenated symbol block is no larger than t2, the decoded sequence is correct.
  • a decoded symbol block is obtained by the FEC decoder, where each row in the decoded symbol block is the decoded sequence corresponding to a corresponding row in the concatenated symbol block Dj+ w -i .
  • the method 900 proceeds from step 912A to step 913A.
  • step 913A the method 900 calculates a second syndrome block and a second index set l i+w -i based on the decoded symbol block
  • the second syndrome block is calculated using the equation:
  • the second index set is calculated using the equation: where s r is the r-th row of the second syndrome block is the r-th row of decoded symbol block is the r-th row of predetermined symbol block an d are th® sub-vectors by taking the first e 2 elements of d r and o r , respectively.
  • the method 900 then proceeds from step 913A to 914A.
  • step 913A determines whether the received symbol blocks and are correct and, if incorrect, then rectifies the received symbol blocks symbol blocks and accordingly.
  • the method 900 proceeds from step 914A to step 915. [00144] Before describing step 915, the corresponding steps 91 OB to 914B will be described first.
  • step 91 OB the method 900 determines a concatenated symbol block
  • the predetermined symbol block is known by the decoder, as discussed hereinbefore in relation to step 511 B.
  • the predetermined symbol block is an m/q by ei matrix as i+w-1 is an odd number, while the symbol block is an m/q by m matrix.
  • the concatenated symbol block Dj+w-i is an m/q by matrix.
  • the method 900 proceeds from step 910B to 911 B.
  • step 911 B the method 900 calculates a first syndrome block of the concatenated symbol block and a first index set associated with the concatenated symbol block
  • the first syndrome block is calculated using the equation: where Hi is the parity-check matrix of the component FEC code C 1 .
  • the parity-check matrix Hi is an ni-ki by ni matrix related to the encoding used to obtain the parity data P i .
  • the first syndrome block is an m/q by m-ki matrix.
  • the first index set is calculated using the equation where s r is the r-th row of If the first syndrome block the method 900 then proceeds from step 911 B to 912B. Otherwise, if the first syndrome block the method 900 then proceeds from step 911 B to step 915.
  • step 912B the r-th row of the concatenated symbol block is decoded by a component FEC decoder, which corresponds to the FEC encoder used in the sub-process 800.
  • the FEC decoder uses and the first index set which are computed in step 911 B.
  • Examples of component FEC decoders include but not limited to BCH decoding, turbo decoding, polar decoding, LDPC decoding, Hamming decoding, and RS decoding.
  • the component FEC decoder returns a decoded sequence.
  • the decoder of the component FEC code C 1 can correct up to ti errors.
  • a decoded symbol block is obtained by the FEC decoder, where each row in the decoded symbol block is the decoded sequence corresponding to a corresponding row in the concatenated symbol block .
  • the method 900 proceeds from step 912B to 913B.
  • step 913B the method 900 calculates a second syndrome block and a second index set based on the decoded symbol block
  • the second syndrome block is calculated using the equation:
  • the second index set is calculated using the equation: where s r is the r-th row of the second syndrome block is the r-th row of decoded symbol block is the r-th row of predetermined symbol block ( ) and are the sub-vectors by taking the first ei elements of d r and o r , respectively.
  • the method 900 then proceeds from step 913B to 914B.
  • step 914B the method 900 updates the received symbol blocks dependent on the r-th rows of the decoded symbol block that have zero syndrome (i.e. , in the second syndrome block and no errors in the first ei symbols , where and the second index set are determined in step 913B. Having a zero syndrome means that the particular row of the decoded symbol block is a valid codeword of component FEC code C 1 .
  • step 909 If the syndrome of the r-th row of the decoded symbol block is zero and at that row the first ei symbols are correct, then the method 900 replaces the r-th row of the concatenated symbol block with the r-th row of the decoded symbol block As discussed in step 909 above, the concatenated symbol block Thus, updating the concatenated symbol block results in the received symbol blocks being updated (where / is an odd number). Therefore, the combination of steps 914A and 914B results in all the received symbol blocks Y being updated (dependent on the syndrome of the corresponding second syndrome block). In other words, step 913B determines whether the received symbol blocks and are correct and, if incorrect, then rectifies the received symbol blocks symbol blocks and accordingly. The method 900 proceeds from step 914B to step 915.
  • step 915 the method 900 determines whether there are remaining decoding window to process.
  • the method 900 determines whether predetermined requirements of the decoding process are met.
  • the predetermined requirement is the number of times I that a cycle of steps 905 to 915 has been performed. If the number of cycle l ⁇ l max , then the method 900 determines that the predetermined requirement is not met. The method 900 then increases the number of cycle by 1.
  • the predetermined requirements can be combined.
  • step 917 If the method 900 determines that the predetermined requirements are met (YES), then the method 900 proceeds from step 917 to step 919. Otherwise (NO), the method 900 proceeds from step 917 to step 905.
  • the method 900 determines that the predetermined requirements are met (YES)
  • the decoder performs either forward scheduling or backward scheduling when processing the received symbol blocks within the decoding window W.
  • the method 900 sets the decoder to perform backward scheduling regardless whether the decoder is initially set to perform forward scheduling or backward scheduling. Accordingly, in a first cycle, the decoder performs forward scheduling for a first group (as determined by the size of the decoding window W) of received symbol blocks and performs backward scheduling in subsequent cycles for the subsequent groups of the received symbol blocks. Alternatively, the decoder performs backward scheduling in all cycles for all groups of the received symbol blocks. If the predetermined requirements are met for times, then the method 900 proceeds from step 917 to step 919.
  • the method 900 proceeds from step 919 to step 921.
  • step 921 the method 900 determines whether there are remaining received data symbols to process. In one arrangement, the determination is performed by determining whether the index where L is the last index (see step 902 above). W+1 (YES), then the method 900 determines that there are remaining data symbols to process. The method 900 then increases the index / by 1. The method 900 then proceeds from step 921 to step 905. Otherwise (i.e., />L-W+1) (NO), the method 900 concludes.
  • FIGs. 8A and 8B depict a general-purpose computer system 1300, upon which an FEC encoder or an FEC decoder described can be practiced.
  • the computer system 1300 includes: a computer module 1301; input devices such as a keyboard 1302, a mouse pointer device 1303, a scanner 1326, a camera 1327, and a microphone 1380; and output devices including a printer 1315, a display device 1314 and loudspeakers 1317.
  • An external Modulator-Demodulator (Modem) transceiver device 1316 may be used by the computer module 1301 for communicating to and from a communications network 1320 via a connection 1321.
  • the communications network 1320 may be a wide-area network (WAN), such as the Internet, a cellular telecommunications network, or a private WAN.
  • WAN wide-area network
  • the modem 1316 may be a traditional “dial-up” modem.
  • the modem 1316 may be a broadband modem.
  • a wireless modem may also be used for wireless connection to the communications network 1320.
  • the computer module 1301 typically includes at least one processor unit 1305, and a memory unit 1306.
  • the memory unit 1306 may have semiconductor random access memory (RAM) and semiconductor read only memory (ROM).
  • the computer module 1301 also includes an number of input/output (I/O) interfaces including: an audio-video interface 1307 that couples to the video display 1314, loudspeakers 1317 and microphone 1380; an I/O interface 1313 that couples to the keyboard 1302, mouse 1303, scanner 1326, camera 1327 and optionally a joystick or other human interface device (not illustrated); and an interface 1308 for the external modem 1316 and printer 1315.
  • the modem 1316 may be incorporated within the computer module 1301 , for example within the interface 1308.
  • the computer module 1301 also has a local network interface 1311 , which permits coupling of the computer system 1300 via a connection 1323 to a local-area communications network 1322, known as a Local Area Network (LAN).
  • LAN Local Area Network
  • the local communications network 1322 may also couple to the wide network 1320 via a connection 1324, which would typically include a so-called “firewall” device or device of similar functionality.
  • the local network interface 1311 may comprise an Ethernet circuit card, a Bluetooth® wireless arrangement or an IEEE 802.11 wireless arrangement; however, numerous other types of interfaces may be practiced for the interface 1311.
  • the I/O interfaces 1308 and 1313 may afford either or both of serial and parallel connectivity, the former typically being implemented according to the Universal Serial Bus (USB) standards and having corresponding USB connectors (not illustrated).
  • Storage devices 1309 are provided and typically include a hard disk drive (HDD) 1310. Other storage devices such as a floppy disk drive and a magnetic tape drive (not illustrated) may also be used.
  • An optical disk drive 1312 is typically provided to act as a non-volatile source of data.
  • Portable memory devices such optical disks (e.g., CD-ROM, DVD, Blu-ray DiscTM), USB-RAM, portable, external hard drives, and floppy disks, for example, may be used as appropriate sources of data to the system 1300.
  • the components 1305 to 1313 of the computer module 1301 typically communicate via an interconnected bus 1304 and in a manner that results in a conventional mode of operation of the computer system 1300 known to those in the relevant art.
  • the processor 1305 is coupled to the system bus 1304 using a connection 1318.
  • the memory 1306 and optical disk drive 1312 are coupled to the system bus 1304 by connections 1319. Examples of computers on which the described arrangements can be practised include IBM-PC’s and compatibles, Sun Sparcstations, Apple MacTM or like computer systems.
  • the method of encoding data to codewords and decoding codewords into data may be implemented using the computer system 1300 wherein the processes of Figs. 3, 4, 8A, and 8B, described above, may be implemented as one or more software application programs 1333 executable within the computer system 1300.
  • the steps of the method of Figs. 3, 4, 8A, and 8B are effected by instructions 1331 (see Fig. 8B) in the software 1333 that are carried out within the computer system 1300.
  • the software instructions 1331 may be formed as one or more code modules, each for performing one or more particular tasks.
  • the software may also be divided into two separate parts, in which a first part and the corresponding code modules performs the encoding and decoding methods and a second part and the corresponding code modules manage a user interface between the first part and the user.
  • the software may be stored in a computer readable medium, including the storage devices described below, for example.
  • the software is loaded into the computer system 1300 from the computer readable medium, and then executed by the computer system 1300.
  • a computer readable medium having such software or computer program recorded on the computer readable medium is a computer program product.
  • the use of the computer program product in the computer system 1300 preferably effects an advantageous apparatus for encoding data into codewords and decoding codewords into data.
  • the software 1333 is typically stored in the HDD 1310 or the memory 1306.
  • the software is loaded into the computer system 1300 from a computer readable medium, and executed by the computer system 1300.
  • the software 1333 may be stored on an optically readable disk storage medium (e.g., CD-ROM) 1325 that is read by the optical disk drive 1312.
  • a computer readable medium having such software or computer program recorded on it is a computer program product.
  • the use of the computer program product in the computer system 1300 preferably effects an apparatus for encoding data into codewords and decoding codewords into data.
  • the application programs 1333 may be supplied to the user encoded on one or more CD-ROMs 1325 and read via the corresponding drive 1312, or alternatively may be read by the user from the networks 1320 or 1322. Still further, the software can also be loaded into the computer system 1300 from other computer readable media.
  • Computer readable storage media refers to any non-transitory tangible storage medium that provides recorded instructions and/or data to the computer system 1300 for execution and/or processing.
  • Examples of such storage media include floppy disks, magnetic tape, CD-ROM, DVD, Blu-rayTM Disc, a hard disk drive, a ROM or integrated circuit, USB memory, a magneto- optical disk, or a computer readable card such as a PCMCIA card and the like, whether or not such devices are internal or external of the computer module 1301.
  • Examples of transitory or non-tangible computer readable transmission media that may also participate in the provision of software, application programs, instructions and/or data to the computer module 1301 include radio or infra-red transmission channels as well as a network connection to another computer or networked device, and the Internet or Intranets including e-mail transmissions and information recorded on Websites and the like.
  • GUIs graphical user interfaces
  • a user of the computer system 1300 and the application may manipulate the interface in a functionally adaptable manner to provide controlling commands and/or input to the applications associated with the GUI(s).
  • Other forms of functionally adaptable user interfaces may also be implemented, such as an audio interface utilizing speech prompts output via the loudspeakers 1317 and user voice commands input via the microphone 1380.
  • Fig. 8B is a detailed schematic block diagram of the processor 1305 and a “memory” 1334.
  • the memory 1334 represents a logical aggregation of all the memory modules (including the HDD 1309 and semiconductor memory 1306) that can be accessed by the computer module 1301 in Fig. 8A.
  • a power-on self-test (POST) program 1350 executes.
  • the POST program 1350 is typically stored in a ROM 1349 of the semiconductor memory 1306 of Fig. 8A.
  • a hardware device such as the ROM 1349 storing software is sometimes referred to as firmware.
  • the POST program 1350 examines hardware within the computer module 1301 to ensure proper functioning and typically checks the processor 1305, the memory 1334 (1309, 1306), and a basic input-output systems software (BIOS) module 1351, also typically stored in the ROM 1349, for correct operation. Once the POST program 1350 has run successfully, the BIOS 1351 activates the hard disk drive 1310 of Fig. 8A.
  • BIOS basic input-output systems software
  • Activation of the hard disk drive 1310 causes a bootstrap loader program 1352 that is resident on the hard disk drive 1310 to execute via the processor 1305.
  • the operating system 1353 is a system level application, executable by the processor 1305, to fulfil various high level functions, including processor management, memory management, device management, storage management, software application interface, and generic user interface.
  • the operating system 1353 manages the memory 1334 (1309, 1306) to ensure that each process or application running on the computer module 1301 has sufficient memory in which to execute without colliding with memory allocated to another process. Furthermore, the different types of memory available in the system 1300 of Fig. 8A must be used properly so that each process can run effectively. Accordingly, the aggregated memory 1334 is not intended to illustrate how particular segments of memory are allocated (unless otherwise stated), but rather to provide a general view of the memory accessible by the computer system 1300 and how such is used.
  • the processor 1305 includes a number of functional modules including a control unit 1339, an arithmetic logic unit (ALU) 1340, and a local or internal memory 1348, sometimes called a cache memory.
  • the cache memory 1348 typically includes a number of storage registers 1344 - 1346 in a register section.
  • One or more internal busses 1341 functionally interconnect these functional modules.
  • the processor 1305 typically also has one or more interfaces 1342 for communicating with external devices via the system bus 1304, using a connection 1318.
  • the memory 1334 is coupled to the bus 1304 using a connection 1319.
  • the application program 1333 includes a sequence of instructions 1331 that may include conditional branch and loop instructions.
  • the program 1333 may also include data 1332 which is used in execution of the program 1333.
  • the instructions 1331 and the data 1332 are stored in memory locations 1328, 1329, 1330 and 1335, 1336, 1337, respectively.
  • a particular instruction may be stored in a single memory location as depicted by the instruction shown in the memory location 1330.
  • an instruction may be segmented into a number of parts each of which is stored in a separate memory location, as depicted by the instruction segments shown in the memory locations 1328 and 1329.
  • the processor 1305 is given a set of instructions which are executed therein.
  • the processor 1305 waits for a subsequent input, to which the processor 1305 reacts to by executing another set of instructions.
  • Each input may be provided from one or more of a number of sources, including data generated by one or more of the input devices 1302, 1303, data received from an external source across one of the networks 1320, 1302, data retrieved from one of the storage devices 1306, 1309 or data retrieved from a storage medium 1325 inserted into the corresponding reader 1312, all depicted in Fig. 8A.
  • the execution of a set of the instructions may in some cases result in output of data. Execution may also involve storing data or variables to the memory 1334.
  • the disclosed arrangements use input variables 1354, which are stored in the memory 1334 in corresponding memory locations 1355, 1356, 1357.
  • the arrangements produce output variables 1361, which are stored in the memory 1334 in corresponding memory locations 1362, 1363, 1364.
  • Intermediate variables 1358 may be stored in memory locations 1359, 1360, 1366 and 1367.
  • each fetch, decode, and execute cycle comprises:
  • a fetch operation which fetches or reads an instruction 1331 from a memory location 1328, 1329, 1330;
  • a further fetch, decode, and execute cycle for the next instruction may be executed.
  • a store cycle may be performed by which the control unit 1339 stores or writes a value to a memory location 1332.
  • Each step or sub-process in the processes of Figs. 3, 4, 8A, and 8B is associated with one or more segments of the program 1333 and is performed by the register section 1344, 1345, 1347, the ALU 1340, and the control unit 1339 in the processor 1305 working together to perform the fetch, decode, and execute cycles for every instruction in the instruction set for the noted segments of the program 1333.
  • the method of encoding and decoding may alternatively be implemented in dedicated hardware such as one or more integrated circuits performing the functions or sub functions of the methods shown in Figs. 3, 4, 8A, and 8B.
  • dedicated hardware may include graphic processors, digital signal processors, or one or more microprocessors and associated memories.
  • the word “comprising” means “including principally but not necessarily solely” or “having” or “including”, and not “consisting only of”. Variations of the word “comprising”, such as “comprise” and “comprises” have correspondingly varied meanings.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

La présente invention concerne un procédé de génération d'une séquence de blocs de symboles. Les blocs de symboles générés comprennent des données codées avec un codage de correction d'erreur sans circuit de retour (FEC). Le procédé comprend la décomposition de l'un des blocs de symboles. Le bloc de symboles décomposé est transposé. Un bloc de symboles de départ est ensuite généré à l'aide du bloc de symboles décomposé et transposé.
PCT/AU2022/050959 2021-08-25 2022-08-23 Codage de correction d'erreur sans circuit de retour staircase modifié WO2023023732A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105429646A (zh) * 2015-06-30 2016-03-23 南京大学 一种咬尾阶梯码的编码及解码方法
US20160308558A1 (en) * 2011-04-13 2016-10-20 Cortina Systems, Inc. Staircase forward error correction coding
WO2017178264A1 (fr) * 2016-04-15 2017-10-19 Alcatel Lucent Procédé et appareil de codage de correction d'erreur sans voie de retour

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160308558A1 (en) * 2011-04-13 2016-10-20 Cortina Systems, Inc. Staircase forward error correction coding
CN105429646A (zh) * 2015-06-30 2016-03-23 南京大学 一种咬尾阶梯码的编码及解码方法
WO2017178264A1 (fr) * 2016-04-15 2017-10-19 Alcatel Lucent Procédé et appareil de codage de correction d'erreur sans voie de retour

Non-Patent Citations (1)

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Title
BENJAMIN P. SMITH, ARASH FARHOOD, ANDREW HUNT, FRANK R. KSCHISCHANG, JOHN LODGE: "Staircase Codes: FEC for 100 Gb/s OTN", JOURNAL OF LIGHTWAVE TECHNOLOGY, IEEE, USA, vol. 30, no. 1, 19 January 2012 (2012-01-19), USA, pages 110 - 117, XP055677577, ISSN: 0733-8724, DOI: 10.1109/JLT.2011.2175479 *

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