AU2022332699A1 - Modified staircase forward error correction coding - Google Patents

Abstract

The present specification relates to a method of generating a sequence of symbol blocks. The generated symbol blocks comprises data encoded with forward error correction (FEC) encoding. The method comprises decomposing one of the symbol blocks. The decomposed symbol block is the transposed. A proceeding symbol block is then generated using the decomposed and transposed symbol block.

Description

MODIFIED STAIRCASE FORWARD ERROR CORRECTION CODING

Technical Field

[0001] The present invention relates generally to a modified staircase forward error correction coding.

Background

[0002] Transmission of data over a noisy or unreliable communication channel would typically result in errors in portions of the transmitted data when received by a receiving device. One method for resolving the errors is called Forward Error Correction (FEC) where redundant data is added into the data itself, such that a decoder can detect and correct some transmission errors. The combination of redundant data and the data is called codewords.

[0003] An example of a conventional FEC coding is called the staircase FEC (shown in Fig. 1). The staircase FEC will be discussed hereinafter in relation to Fig. 1.

Summary

[0004] Disclosed are arrangements to modify the staircase FEC by decomposing the preceding symbol block (which is used to encode a current symbol block) and transposing the decomposed, preceding symbol block used to encode the current symbol block. The symbol block decomposition and transposition enable the input and parity data of the preceding symbol block to be interwoven within the preceding symbol block. Such interweaving of the input and parity data allows the use of stronger component FEC codes, which in turn improves the overall forward error correction capability of the modified staircase FEC.

[0005] According to one aspect of the present disclosure, there is provided a method of generating a sequence of symbol blocks, the generated symbol blocks comprising data encoded with forward error correction (FEC) encoding, the method comprising: decomposing one of the symbol blocks; transposing the decomposed symbol block; and generating a proceeding symbol block using the decomposed and transposed symbol block.

[0006] According to another aspect of the present disclosure, there is provided a method of decoding a sequence of received symbol blocks, the received symbol blocks comprising data encoded with forward error correction (FEC) encoding, the method comprising: decomposing one of the symbol blocks; transposing the decomposed symbol block; and determining whether a proceeding received symbol block is correct based on the transposed, decomposed symbol block.

[0007] According to another aspect of the present disclosure, there is provided an apparatus for implementing any one of the aforementioned methods.

[0008] According to another aspect of the present disclosure, there is provided a computer program product including a computer readable medium having recorded thereon a computer program for implementing any one of the methods described above.

[0009] Other aspects are also disclosed.

Brief Description of the Drawings

[0010] Some aspects of the prior art and at least one embodiment of the present invention will now be described with reference to the drawings and appendices, in which:

[0011] Fig. 1 shows a prior art arrangement for performing staircase forward error correction (FEC) coding;

[0012] Fig. 2 shows an arrangement for performing a modified staircase forward error correction (FEC) coding according to the present disclosure;

[0013] Fig. 3 is a flow diagram of a method of performing the modified staircase FEC shown in Fig. 2;

[0014] Fig. 4 is a flow diagram of a sub-process of generating symbol blocks of the modified staircase FEC of Fig. 3;

[0015] Figs. 5 and 6 show illustrations of the symbol blocks of different indices being processed according to the sub-process of Fig. 4;

[0016] Figs. 7A and 7B show a flow diagram of a method of decoding symbol blocks that are generated using the modified staircase FEC coding of Figs. 2 to 6; and

[0017] Figs. 8A and 8B form a schematic block diagram of a general purpose computer system upon which arrangements described can be practiced. [0018] Fig. 9 is a flow diagram of a sub-process of generating symbol blocks of the modified staircase FEC of Fig. 3 when a coupling width is larger than 2; and

[0019] Figs. 10A and 10B show a flow diagram of a method of decoding symbol blocks that are generated using the modified staircase FEC coding of Fig. 9.

Detailed Description

[0020] Where reference is made in any one or more of the accompanying drawings to steps and/or features, which have the same reference numerals, those steps and/or features have for the purposes of this description the same function(s) or operation(s), unless the contrary intention appears.

[0021] Fig. 1 shows a conventional staircase FEC 100 having symbol blocks Bi, where each symbol block B_i is formed by input data K_i and parity data P_i (i.e. , the redundant data).

However, when /=0, then B₀ is a symbol block having predetermined symbols. A combination of two symbol blocks B_i forms the codewords of component FEC code C, such that of each row in [B^T _i-1 , B_i] or each column in [B_i-1 , B^T _i] is a codeword of component FEC code C. Accordingly, component FEC code C is a set of all codewords generated by the FEC encoding. A sequence of symbol blocks Bi , B2, ... are subsequently transmitted via a communication channel and received by a decoder.

[0022] Each symbol block B_i is a two-dimensional array of m by m. Each codeword of component FEC code C has a length of n, where the information in the codeword has a length of k. The parity data P_i accordingly is a two-dimensional array of m by n-k. The input data K_i is a two-dimensional array of m by k-m.

[0023] To obtain the parity data P_i, the input data K_i is concatenated with the transpose of the preceding symbol block B^T _i-1. Each row of the concatenated data (i.e., [B^T _i-1, K_i]) is then processed with an encoding method to obtain the parity data on each row. The parity data P_i can also be equivalently obtained by processing the encoding method on each column of the transpose of the concatenated data (i.e., [B^T _i-1, K_i]^T).

[0024] Once all the parity data on each row is obtained, the parity data P_i is then added to each symbol block B_i, such that B_i = [K_i, P_i], Equivalently, the transpose of the symbol block B_i is obtained, such that B^Tj = [K_i, P_i]^T. As indicated above, each row in [B^T _i-1, B_i] or each column in in [B_i-i , B^Tj] is a codeword of the FEC component code C. The transpose of the symbol blocks B_i with even indices together with the symbol blocks B_i with odd indices results in a staircase-like structure shown in Fig. 1.

[0025] It is to be noted that the discussions contained in the "Background" section and that above relating to a conventional arrangement relate to discussions of an encoding method which forms public knowledge through their respective publication and/or use. Such should not be interpreted as a representation by the present inventor(s) or the patent applicant that such documents or method in any way form part of the common general knowledge in the art.

[0026] Fig. 2 shows an illustration of a modified staircase FEC 200 in accordance with the present disclosure. In the modified staircase FEC 200, the preceding symbol block B_i-1 is used to encode a current symbol block B_i. During the encoding process, the preceding symbol block B_i.1 is first decomposed and transposed before being used to obtain the parity data. In one arrangement, the decomposition of a preceding symbol block B_i-1 involves dividing the preceding symbol block B_i-1 into sub-blocks B_i-1 , 1, B_i-1 , 2, ... , B_i-1 , _q and transposing each sub- block. Hereinafter, the arrangement of dividing the preceding symbol block B_i-1 and transposing each sub-block will be used in describing the modified staircase FEC 200. In Fig. 2, the sub- blocks indicated by dashed lines (i.e. , the predetermined symbol blocks Oi and the predetermined symbol blocks Bo) are involved in the encoding but are not transmitted.

[0027] The modified staircase FEC 200 includes symbol block B_i, where each symbol block B_i is formed by input data K_i and parity data P_i (i.e., the redundant data). / is an index identifying the order of the symbol block B_i and the associated data K_i and parity data P_i, where i=1 ,2,..., L. Each symbol block B_i is sub-divided into sub-blocks B_i-1 , B_i,2, ... , B_i,_q. The parameters L and q are predetermined.

[0028] The modified staircase code 200 generates component FEC code Cj. The component FEC code Ci is the set of all codewords generated by the FEC encoding, where each codeword has length ni, predetermined symbol block length ei, data length K_iei, and parity data length ni- K._i Each row of a combination of a symbol block B_i, the rearranged preceding symbol block B_i-1 , and a predetermined symbol block 0; (or each column of the transpose of that combination) is a codeword of the component FEC code Cj. The predetermined symbol block 0; includes predetermined symbols that are known by the encoder-decoder pair. An example of predetermined symbol block is a zero matrix, where all the predetermined symbols are zero. Examples of component FEC codes include but not limited to Bose-Chaudhuri-Hocquenghem codes (BCH) codes, low-density parity-check (LDPC) codes, turbo codes, polar codes, Reed- Solomon (RS) codes, and Hamming codes. [0029] However, when /=0, Bo does not contain the input data K_i and parity data P_i. Bo instead contains predetermined symbols. An example of predetermined symbols is a zero matrix, where all the predetermined symbols are zero.

[0030] The modified staircase FEC 200 has ten parameters that can be adjusted to set the dimension (i.e. , the number of rows and columns) of data block K_i, and parity data block P_i and, subsequently the symbol block B_i. These ten parameters are and e₂. These ten parameters are positive integers. For parameters there are further requirements where rr?i must be divisible by and must be divisible by The parameters qi , q2 are called symbol block index as these parameters determine the number of sub-blocks decomposed from the preceding symbol block B_i-1 , and subsequently the number of transposed sub-blocks and the determination of the parity data (which will be described hereinafter).

[0031] Each symbol block B_i is a two-dimensional array. When / is an odd number, B_i is an by m1 matrix filled with symbols. The data block K_i is an matrix. The parity data P_i is an matrix. Hereinafter, for ease of description, C ₁ will be used to indicate component FEC code Ci when / is an odd number.

[0032] m indicates the length of a codeword of the component FEC code C₁. ki indicates the length of the codeword of C₁ without the parity data P_i. ei indicates the length of the predetermined symbol block Oiwhen / is an odd number. Accordingly, the codeword length of C₁ satisfies

[0033] When / is an even number, B_i is an rm/qi by m2 matrix filled with rm rm/qi symbols. The data K_i is an matrix. The parity data P_i is an matrix.

Hereinafter, for ease of description, C2 will be used to indicate component FEC code Ci when / is an even number.

[0034] m indicates the length of a codeword of the component FEC code C2. k2 indicates the length of the codeword of the component FEC code C2 without the parity data P_i. e₂ indicates the length of the predetermined symbol block Oi when / is an even number. Accordingly, the codeword length of component FEC code C2 satisfies The predetermined symbol block Oi can be different dependent on whether / is an odd or even number.

[0035] To obtain the parity data P_i, the input data K_i is concatenated with a decomposed and transposed preceding symbol block B_i-1 and the symbol block Oi. Each row of the concatenated data (i.e., predetermined symbol block Oi + decomposed and transposed preceding symbol block B_i.i+ data K_i) is then processed with an encoding method to obtain the parity data P_i on each row. Examples of the encoding method include but not limited to BCH encoding, turbo encoding, LDPC encoding, polar encoding, RS encoding and Hamming encoding. The modified staircase FEC 200 will be described in further detail in relation to Figs. 3 to 6 hereinafter. Fig. 2 shows an example where the preceding symbol block is divided by either qi=3 or q2=2.

Therefore, in the example shown in Fig. 2, when i=2 (which is an even number), the preceding symbol block Bi is subdivided by q1=3 to obtain sub-blocks Bi ,1 , Bi ,2, and B1,3. When /=3 (which is an odd number), the preceding symbol block B2 is subdivided by <72=2 to obtain sub-blocks B₂,1 , and B2,2.

[0036] When encoding the symbol block 82, the preceding symbol block Bi is subdivided into sub-blocks Bi ,1 , Bi ,₂, and B1,3. Sub-blocks Bi ,1 , Bi ,₂, and B1,3 are then rearranged by moving sub- blocks B1 ,2 and B1,3 below sub-block B1 ,1. The rearranged sub-blocks B1 ,1 , B1 ,₂, and B1,3 are then transposed and concatenated with data K2 and the symbol block O₂ to obtain the parity data P₂. Symbol block 82 is then obtained by combining the data K2 with the parity data P₂. A codeword of component FEC code C2 relating to symbol block B₂ is then a column of the symbol block O₂, the transposed and rearranged sub-blocks Bi ,1 , Bi ,₂, and Bi ,3, the data K₂, and the parity data P₂.

[0037] The rearrangement of sub-blocks shown in Fig. 2 is an example rearrangement. There are other rearrangements such as permutation, and the like.

[0038] The overall code rate of the modified staircase FEC code is:

[0039] Fig. 3 shows a flow diagram of a method 300 for generating symbol blocks Bi , B₂,... , BL for received input data. The method 300 is a software application program 1333 executable within the computer system 1300 (see the discussion below in relation to Figs. 8A and 8B).

[0040] The method 300 commences at step 302 by receiving input data to be transmitted through a communication channel. Examples of input data include voice data, text messages, computer files, and the like. The method 300 then proceeds from step 302 to step 304. [0041] In step 304, the received input data is divided into a sequence of input data Ki, where i = 1 ,... ,L. The method 300 proceeds from step 304 to sub-process 400. In an alternative arrangement, sub-process 500 is used (rather than sub-process 400) if a coupling width II is greater than 2. The coupling width II is described hereinafter in relation to Fig. 9 and its associated description.

[0042] In sub-process 400, a sequence of symbol blocks Bi , B2,... , BL associated with the sequence of input data K_i is generated. The generated sequence of symbol blocks Bi , B2,... , BL can then be sent via the communication channel. The method 300 concludes at the conclusion of the sub-process 400.

[0043] Fig. 4 shows a flow diagram of the sub-process 400. Sub-process 400 is a software application program 1333 executable within the computer system 1300 (see the discussion below in relation to Figs. 8A and 8B).

[0044] Sub-process 400 commences at step 402 by initialising the predetermined symbol block Bo. An example of the predetermined symbols Bo is a zero matrix. Sub-process 400 proceeds from step 402 to step 404.

[0045] In step 404, sub-process 400 determines whether the index i is an even or odd number. If the index i is an odd number, then sub-process 400 proceeds from step 404 to step 406A. Otherwise, if the index i is an even number, sub-process 400 proceeds from step 404 to step 406B.

[0046] In step 406A, sub-process 400 divides the preceding symbol block B_i-1. For example, when i=1 , symbol block Bo (which is the preceding symbol block B_i-1 and is initialised at step 402) is divided into q 2 sub-blocks. As discussed hereinbefore in relation to Fig. 2, q2 is used as the index i is an odd number. As shown in the example of Fig. 2 where q 2 = 2, Bo is divided into 2 sub-blocks B₀,1 and Bo, 2.

[0047] Fig. 5(a) shows an example of a preceding symbol block B_i-1 when i is an odd number. The preceding symbol block B_i-1 is an rm/qi by m2 matrix, as the index i of the preceding symbol block is an even number (see the discussion in relation to Fig. 2 above). Fig. 5(b) then shows the preceding symbol block B_i-1 being divided into 2 sub-blocks, as q2 = 2. Each sub-block B_i-1 ,1 and Bi-1 ,2 is an m1/q1 by m2/ q2 matrix. [0048] Sub-process 400 proceeds from step 406A to step 408A once the preceding symbol block B_i.1 has been subdivided.

[0049] In step 408A, each of the sub-blocks is transposed. The transposed sub-blocks are represented by Fig. 5(c) shows an illustration of the sub-blocks B_i-1 ,I and B_i-1 ,2 being transposed.

[0050] Sub-process 400 proceeds from step 408A to step 410A once all sub-blocks has been transposed.

[0051] In step 410A, the transposed sub-blocks are rearranged. In one arrangement, the rearrangement is a permutation function of

[0052] The permutation function TT(.) permutes the row and column position of matrix

[0053] Step 410A of sub-process 400 is an optional process. If Step 410A is not performed, sub-process 400 proceeds from step 408A to step 412A. Otherwise, sub-process 400 proceeds from step 408A to step 410A and then to step 412A.

[0054] In step 412A, the transposed sub-blocks are concatenated with the predetermined symbol block Oi and the data K_i to obtain a concatenated block of As discussed hereinbefore, the predetermined symbol block Oi is an rri2/q2 by ei matrix and includes predetermined symbols that are known to the encoder-decoder pair. The data K_i is an matrix. Accordingly, the concatenated block is an by matrix.

[0055] Fig. 5(d) shows the concatenated block Sub-process 400 proceeds from step 412A to 414A.

[0056] In step 414A, the parity data P_i for the concatenated block is determined. The parity data Pi is obtained for each row of the concatenated block by performing FEC encoding of C₁ on that row. The parity data Pi can be equivalently obtained by performing FEC encoding of C₁ on each column of the matrix transpose of the concatenated block . As discussed hereinbefore, examples of the FEC encoding include but not limited to BCH encoding, RS encoding, LDPC encoding, Hamming encoding, turbo encoding, and polar encoding. Accordingly, the codeword matrix is represented by where each row of Ci is a codeword of C₁.

[0057] Fig. 5(e) shows the concatenated block being combined with the obtained parity data P_i. Each row of the combined concatenated block and parity data P_i forms a codeword of component FEC code C₁.

[0058] Sub-process 400 proceeds from step 414A to step 415A.

[0059] In step 415A, sub-process 400 generates a symbol block B_i for the associated index /. The symbol block B_i is a combination of the data K_i and the parity data P_i. In other words, the data K_i is embedded within the generated symbol block B_i. Fig. 5(f) shows the data K_i being combined with the parity data P_i. Sub-process 400 proceeds from step 415A to step 417.

[0060] In step 417, sub-process 400 determines whether there are remaining symbol blocks B_i to process. In one arrangement, the determination is performed by determining whether the index i=L, where L is the last index (see step 304 above). If /<L, then sub-process 400 determines that there are remaining symbol blocks B_i to process. Sub-process 400 then increases the index i by 1. Sub-process 400 then proceeds from step 417 to step 404.

Otherwise (i.e. , i=L), sub-process 400 concludes. At the conclusion of sub-process 400, the symbol blocks B_i obtained at steps 415A and 415B (which correspond to the input data received at step 302) are sent via the communication channel. When transmitting the symbol blocks B_i, the predetermined symbol block Oi can be removed to reduce the amount of data being transmitted. As the predetermined symbol block Oi is known by the decoder, the decoder provides the symbol block Oi when decoding the received symbol blocks B_i (without the symbol block Oi).

[0061] The corresponding steps 406B to 415B for obtaining the symbol block B_i, when the index i is an even number, will now be described.

[0062] In step 406B, sub-process 400 divides the preceding symbol block B_i-1 . For example, when i=2, symbol block B1 (which is the preceding symbol block B_i-1) is divided into q1 sub- blocks. As discussed hereinbefore in relation to Fig. 2, q 1 is used as the index i is an even number. As shown in the example of Fig. 2 where q1 = 3, B1 is divided into 3 sub-blocks B1,1 , B1,₂, and B1,3. [0063] Fig. 6(a) shows an example of a preceding symbol block B_i-1 when i is an even number. The preceding symbol block B_i-1 is an matrix, as the index i of the preceding symbol block is an even number (see the discussion in relation to Fig. 2 above). Fig. 6(b) then shows the preceding symbol block B_i-1 being divided into 3 sub-blocks, as Each sub-block is an by mat rix.

[0064] Sub-process 400 proceeds from step 406B to step 408B once the preceding symbol block B_i.1 has been subdivided.

[0065] In step 408B, each of the sub-blocks is transposed. The transposed sub-blocks are represented by Fig. 6(c) shows an illustration of the sub-blocks being transposed.

[0066] Sub-process 400 proceeds from step 408B to step 410B once all sub-blocks has been transposed.

[0067] In step 410B, the transposed sub-blocks are rearranged. In one arrangement, the rearrangement is a permutation function of

[0068] The permutation function TT(.) permutes the row and column position of matrix

[0069] Step 410B of sub-process 400 is an optional process. If Step 410B is not performed, sub-process 400 proceeds from step 408B to step 412B. Otherwise, sub-process 400 proceeds from step 408A to step 410B and then to step 412B.

[0070] In step 412B, the transposed sub-blocks are concatenated with the predetermined symbol block Oi and the data K_i to obtain a concatenated block of As discussed hereinbefore, the predetermined symbol block Oi is an by e2 matrix and includes predetermined symbols that are known to the encoder-decoder pair. The data K_i is an matrix. Accordingly, the concatenated block is an by matrix.

[0071] Fig. 6(d) shows the concatenated block Sub-process 400 proceeds from step 412B to 414B. [0072] In step 414B, the parity data Pi for the concatenated block is determined. The parity data Pi is obtained for each row of the concatenated block by performing FEC encoding of component FEC code C2 on that row. The parity data Pi can be equivalently obtained by performing FEC encoding of component FEC code C2 on each column of the matrix transpose of the concatenated block As discussed hereinbefore, examples of the FEC encoding include but not limited to BCH encoding, RS encoding, LDPC encoding, Hamming encoding, turbo encoding, and polar encoding. Accordingly, the codeword matrix is represented by where each row of Ci is a codeword of component FEC code C₂.

[0073] Sub-process 400 proceeds from step 414B to step 415B.

[0074] Fig. 2 shows that the codewords of component FEC code C2 and its associated symbol blocks Bi (when i is an even number) are in arranged in columns. The column arrangement is for illustration only, to demonstrate the staircase-like structure of the modified staircase FEC code. As described in the paragraph immediately above, the codeword matrix is represented by Performing a matrix transpose leads to

The matrix transpose (when i is an even number) combined with the codeword matrix Ci (when i is an odd number) gives the illustration in Fig. 2. As described hereinbefore, the sub-blocks indicated by dashed lines are involved in the encoding but are not transmitted. It is unnecessary to perform the matrix transpose (when i is an even number) when generating the symbol blocks Bi.

[0075] In step 415B, sub-process 400 generates a symbol block Bi for the associated index i. The symbol block Bi is a combination of the data Ki and the parity data Pi. Fig. 6(f) shows the data Ki being combined with the parity data Pi. Sub-process 400 proceeds from step 415B to step 417, which is already described hereinbefore.

[0076] In one example, a modified staircase FEC 200 has symbol blocks Bi where i=1 ,... ,L and L is an even number. The codeword length of such a modified staircase FEC code 200 is In contrast, the codeword length of the conventional staircase FEC code 100 is when L symbol blocks are transmitted. Both the modified staircase FEC code 200 and conventional staircase FEC code 100 have the same code rate if the encoding codes used are the same. Therefore, the modified staircase FEC code 200 has shorter codeword length in comparison to the conventional staircase codes. The modified staircase FEC code 200 can therefore employ encoding codes with stronger error correction capability to achieve improved error correction performance, while having a similar codeword length and the same code rate as the conventional staircase FEC code 100. Otherwise, if both the modified and conventional FEC codes use the same encoding codes, the modified staircase FEC code 200 provides a similar error correction capability and achieves the same code rate as the conventional staircase FEC code 100 but with shorter codeword length, thereby reducing the latency caused by transmitting the codewords.

[0077] In one example, the parameters set are m1 = m 2 = 1020 and q1 = q2 = 4. The FEC component code C₁ is a binary BCH code with k1 = 1993, n1 = 2047, and e1 = 7. The FEC component code C2 is a binary BCH code with fo = 1982, n₂ = 2047, and 62 = 7. The overall code rate of the modified staircase FEC code 200 is 0.9407. Each symbol block B_i is filled with 260100 bits, where B_i is a 255 by 1020 binary matrix. When / is an odd number, K_i is a 255 by 965 binary matrix and P_i is a 255 by 54 binary matrix. When / is an even number, K_i is a 255 by 954 binary matrix and P_i is a 255 by 65 binary matrix.

[0078] In another example, the parameters are m1 = 964, m2 = 801, q1 = 3, and q2 = 4. The FEC component code C₁ is a binary BCH code with k1 = 1993, n1 = 2047, and ei = 360. The FEC component code C2 is a binary BCH code with fo = 1982, n₂ = 2047, and 62 = 178. The overall code rate of the modified staircase FEC code 200 is 0.9303. When / is an even number, the symbol block B_i is filled with 193041 bits, where B_i is a 241 by 801 binary matrix, K_i is a 241 by 736 binary matrix and P_i is a 241 by 65 binary matrix. When / is an odd number, the symbol block B_i is filled with 257388 bits, where B_i is a 267 by 964 binary matrix, K_i is a 267 by 910 binary matrix and P_i is a 267 by 54 binary matrix.

[0079] Figs. 7A and 7B show a flow diagram of a method 800 of decoding a sequence of received symbol blocks Yj to obtain the input data K_i. The method 800 is a software application program 1333 executable within the computer system 1300 (see the discussion below in relation to Figs. 8A and 8B).

[0080] The method 800 commences at step 802 by receiving a sequence of symbol blocks Yj.

As discussed above in relation to step 417 of sub-process 400, the symbol blocks Bi, are transmitted but not the predetermined symbol block Oi. For ease of identification between the symbol blocks being transmitted and the symbol blocks being received, the transmitted symbol blocks Bi are represented by the received symbol blocks Y, where i=1,... ,L. The decoder also has a parameter called decoding window size W, where 2<W<L. The decoding window W sets the number of received symbol blocks Yj to be considered when performing the decoding. The decoder receives symbol blocks Yj, ... ,Y+w-i (or equivalently Y+_w-i , w = 1 , ... , W) and output Y if i<L-W+1. However, if i=L-W+1, the decoder outputs YL-W+I , ... YL based on the received last W symbol blocks YL-W+I , ... YL. The window size W can be adjusted to adapt to specific latency and performance requirement. When the window size W is large, the decoding performance is better but the latency is higher compared to when the window size W is smaller.

[0081] The method 800 proceeds from step 802 to step 804.

[0082] In step 804, the predetermined symbol block Yo= Bo is initialised based on the received symbol blocks Yj. As discussed in relation to sub-process 400, each row of a combination of three symbol blocks Oi, B_i-1 and B_i is a codeword of component FEC code Ci. The parameters and e2, as well as the types of component FEC codes C₁ and C2 are known by the decoder. The method 800 proceeds from step 804 to 805.

[0083] Within the decoding window W, the decoder can choose to operate either in forward scheduling or backward scheduling. When forward scheduling is performed, among the W received symbol blocks is decoded first, followed by When backward scheduling is performed, among the W received symbol blocks is decoded first, followed by

[0084] In step 805, the method 800 determines whether (/ + w -1) is an even or odd number. is the w-th symbol block among the W received symbol blocks Y,...,Yj+w-i in a decoding window with size W and 1 < w < W. If (/ + w -1) is an even number, then the method 800 proceeds from step 805 to step 806A. Otherwise, if (/ + w-1) is an odd number, the method 800 proceeds from step 805 to step 806B.

[0085] In step 806A, the preceding symbol block Yj_+w-2 is divided into qi sub-blocks is used as the index of the current symbol block is an even number. The method 800 proceeds from step 806A to step 810A.

[0086] In step 810A, each of the sub-block of the preceding symbol block is transposed. The transposed sub-blocks are represented by is an matrix. Therefore, by rri2qi/q2 matrix. If the optional rearrangement step 410A or 41 OB is performed, then the transposed sub-blocks also need to be rearranged accordingly. The method 800 proceeds from step 810A to 812A.

[0087] In step 812A, the method 800 constructs a concatenated symbol block The concatenated symbol block is a combination of the predetermined symbol block the transposed sub-blocks of step 810A, and the symbol block . Accordingly, The predetermined symbol block is known by the decoder, as discussed hereinbefore in relation to steps 412A and 412B. The symbol block is by e2 matrix, while the symbol block is an matrix. The concatenated symbol block is an by matrix. The method 800 proceeds from step 812A to 814A.

[0088] In step 814A, the method 800 calculates a first syndrome block of the concatenated symbol block and a first index set associated with the concatenated symbol block

[0089] The first syndrome block is calculated using the equation: where H2 is the parity-check matrix of the component FEC code C2. The parity-check matrix H2 is an n2-k2 by n2 matrix related to the encoding used to obtain the parity data P_i. A vector c is a codeword of component FEC code C2 if it satisfies Syndrome block is an by matrix.

[0090] The first index set is calculated using the equation where s_r is the r-th row of If the first syndrome block , the method 800 then proceeds from step 814A to 816A. Otherwise, if the first syndrome block , the method 800 skips the subsequent steps 816A and 818A such that the method 800 effectively proceeds from step 814A to step 820.

[0091] In step 816A, the r-th row of the concatenated symbol block is decoded by a component FEC decoder, which corresponds to the FEC encoder used in the sub-process 400. The FEC decoder uses and the first index set which are computed in step 814A. Examples of component FEC decoders include but not limited to BCH decoding, turbo decoding, polar decoding, LDPC decoding, Hamming decoding, and RS decoding. The component FEC decoder returns a decoded sequence. The decoder of the component FEC code C2 can correct up to t2 errors. If the number of errors in a row of the concatenated symbol block is no larger than t2, the decoded sequence is correct. Otherwise, the decoded sequence is incorrect. A decoded symbol block is obtained by the FEC decoder, where each row in is the decoded sequence corresponding to a corresponding row in The method 800 proceeds from step 816A to 818A.

[0092] In step 818A, the method 800 calculates a second syndrome block and a second index set based on the decoded symbol block The second syndrome block is calculated using the equation: The second index set is calculated using the equation: where is the r-th row of the second syndrome block is the r-th row of decoded symbol block is the r-th row of predetermined symbol block and are the sub-vectors by taking the first e2 elements of and respectively. The method 800 then proceeds from step 818A to 819A.

[0093] In step 819A, the method 800 updates the received symbol blocks and dependent on the r-th rows of the decoded symbol block that have zero syndrome (i.e. , in the second syndrome block and no errors in the first e2 symbols (i.e., where and the second index set are determined in step 818A. Having a zero syndrome in the second syndrome block means that the particular row of the decoded symbol block is a valid codeword of component FEC code C2. If the syndrome of the r-th row of the decoded symbol block is zero and in that row the first e₂ symbols are correct, then the method 800 replaces the r-th row of the concatenated symbol block with the r-th row of the decoded symbol block As discussed in step 812A above, the concatenated symbol block Thus, updating the concatenated symbol block results in the received symbol blocks and being updated (where / is an even number). In other words, step 819A determines whether the received symbol blocks and are correct and, if incorrect, then rectifies the received symbol blocks symbol blocks and accordingly. The method 800 proceeds from step 819A to step 820.

[0094] Before describing step 820, the corresponding steps 806B to 818B will be described first.

[0095] In step 806B, the preceding symbol block Yj_+W.2 is divided into q2 sub-blocks is used as the index of the current symbol block i+w-1 is an odd number. The method 800 proceeds from step 806B to step 810B. [0096] In step 81 OB, each of the sub-blocks of the preceding symbol block is transposed. The transposed sub-blocks are represented by is an mi/qi by m2 matrix. Therefore, is an rri2/q2 by miq2/qi matrix. If the optional rearrangement step 410A or 410B is performed, then the transposed sub-blocks also need to be rearranged accordingly. The method 800 proceeds from step 810B to 812B.

[0097] In step 812B, the method 800 constructs a concatenated symbol block The concatenated symbol block is a combination of the predetermined symbol block the transposed sub-blocks of step 810B, and the symbol block Accordingly, The predetermined symbol block is known by the decoder, as discussed hereinbefore in relation to steps 412A and 412B. The symbol block is matrix, while the symbol block is an by m1 matrix. The concatenated symbol block is an matrix. The method 800 proceeds from step 812B to 814B.

[0098] In step 814B, the method 800 calculates a first syndrome block of the concatenated symbol block and a first index set associated with the concatenated symbol block

[0099] The first syndrome block is calculated using the equation: where Hi is the parity-check matrix of the component FEC code C₁. The parity-check matrix Hi is an ni-ki by m matrix related to the encoding used to obtain the parity data P_i. A vector c is a codeword of component FEC code C₁ if it satisfies cHi^T = 0. Syndrome block is an rri2/q2 by matrix.

[00100] The first index set is calculated using the equation where s_r is the r-th row of If the first syndrome block the method 800 then proceeds from step 814B to 816B. Otherwise, if the first syndrome block , the method 800 skips the subsequent steps 816B and 818B such that the method 800 effectively proceeds from step 814B to step 820.

[00101] In step 816B, the r-th row of the concatenated symbol block is decoded by a component FEC decoder, which corresponds to the FEC encoder used in the sub-process 400. The FEC decoder uses r and the first index set which are computed in step 814B. Examples of component FEC decoders include but not limited to BCH decoding, turbo decoding, polar decoding, LDPC decoding, Hamming decoding, and RS decoding. The component FEC decoder returns a decoded sequence. The decoder of the component FEC code C₁ can correct up to ti errors. If the number of errors in a row of the concatenated symbol block is no larger than ti , the decoded sequence is correct. Otherwise, the decoded sequence is incorrect. A decoded symbol block is obtained by the FEC decoder, where each row in the decoded symbol block is the decoded sequence corresponding to a corresponding row in . The method 800 proceeds from step 816B to 818B.

[00102] In step 818B, the method 800 calculates a second syndrome block and a second index set based on the decoded symbol block The second syndrome block is calculated using the equation: The second index set is calculated using the equation: where is the r-th row of the second syndrome block is the r-th row of decoded symbol block is the r-th row of predetermined symbol block _r(l: e£) and are the sub-vectors by taking the first ei elements of d_r and o_r, respectively. The method 800 then proceeds from step 818B to 819B.

[00103] In step 819B, the method 800 updates the received symbol blocks and dependent on the r-th rows of the decoded symbol block that have zero syndrome (i.e. , in the second syndrome block and no errors in the first ei symbols (i.e., where and the second index set are determined in step 818B. Having a zero syndrome in the second syndrome block means that the particular row of the decoded symbol block is a valid codeword of component FEC code C₁. If the syndrome of the r-th row of the decoded symbol block is zero and at that row the first ei symbols are correct, then the method 800 replaces the r-th row of the concatenated symbol block with the r-th row of the decoded symbol block As discussed in step 812B above, the concatenated symbol block Thus, updating the concatenated symbol block results in the received symbol blocks and being updated (where / is an odd number). Therefore, the combination of steps 819A and 819B results in all the received symbol blocks Y being updated (dependent on the syndrome of the corresponding second syndrome block). In other words, step 819B determines whether the received symbol blocks 2 and are correct and, if incorrect, then rectifies the received symbol blocks symbol blocks and accordingly. The method 800 proceeds from step 819B to step 820.

[00104] In step 820, the method 800 determines whether there are remaining decoding window to process. The determination is performed by determining whether the index w=W, where W is the last index (see step 802 above). If w<W, then the method 800 determines that there are remaining decoding window to process. When forward scheduling is used, the method 800 then increases the index w by 1. The method 800 then proceeds from step 820 to step 805. Otherwise (i.e. , w=W), the method 800 proceeds to step 822. When backward scheduling is used, the determination is performed by determining whether the index w=1 , where 1 is the first index (see step 802 above). If w>1 , then the method 800 determines that there are remaining decoding window to process. The method 800 then reduces the index w by 1 . The method 800 then proceeds from step 820 to step 805. Otherwise (i.e., w=1), the method 800 proceeds to step 822.

[00105] In step 822, the method 800 determines whether predetermined requirements of the decoding process are met. In one arrangement, the predetermined requirement is the number of times I that a cycle of steps 806A/806B to 820 has been performed. If the number of cycle I< Imax, then the method 800 determines that the predetermined requirement is not met. The method 800 then increases the number of cycle I by 1 . In another arrangement, the method 800 determines whether the index i=L-W+1 , where L is the last index (see step 802 above). If i < L-W+1 , then the method 800 determines whether a syndrome block Sj=O (i.e., w=1). Since the FEC decoder processes W received symbol blocks Yi,... ,Y_i+w-i and outputs updated symbol blocks Yj (a combination of steps 819A and 819B), the determination that the syndrome block Si=O confirms that the decoding of Yi is successful. Otherwise, if i >L-W+1 , the method 800 determines whether the syndrome blocks The determination that the syndrome block confirms that the decoding of the last W received blocks YL-W+I , ... ,YL is successful. The predetermined requirements can be combined.

[00106] As discussed above, the decoder performs either forward scheduling or backward scheduling when processing the received symbol blocks within the decoding window W. At step 822, the method 800 sets the decoder to perform backward scheduling regardless whether the decoder is initially set to perform forward scheduling or backward scheduling. Accordingly, in a first cycle, the decoder performs forward scheduling for a first group (as determined by the size of the decoding window W) of received symbol blocks and performs backward scheduling in subsequent cycles for the subsequent groups of the received symbol blocks. Alternatively, the decoder performs backward scheduling in all cycles for all groups of the received symbol blocks.

[00107] If the method 800 determines that the predetermined requirements are met (YES), then the method 800 proceeds from step 822 to step 824. Otherwise (NO), the method 800 proceeds from step 822 to step 805. [00108] In step 824, if i < L-W+1 , the updated symbol blocks Yi (i.e. , w=1) is output. Otherwise, if i >L-W+1 , the updated symbol blocks YL-W+I , ... ,YL are output. The method 800 proceeds from step 824 to step 826.

[00109] In step 826, the method 800 determines whether there are remaining received data symbols Yi,...Yi+w-1 to process. In one arrangement, the determination is performed by determining whether the index iL-W+1 , where L is the last index (see step 802 above). If i < L- W+1 (YES), then the method 800 determines that there are remaining data symbols Yi,... Y+w-1 to process. The method 800 then increases the index i by 1. The method 800 then proceeds from step 826 to step 805. Otherwise (i.e., i>L-W+1) (NO), the method 800 concludes.

[00110] The modified staircase FEC codes can be extended by increasing the number of coupled symbol blocks B_i. The modified staircase FEC code uses a preceding symbol block B_i-1 to encode the current symbol block B_i, meaning two symbol blocks B_i are coupled. The number of symbol blocks B_i coupled together is called a coupling width U, such that an amount II of the symbol blocks B_i are correlated. When the coupling width U>2, U-1 sub-blocks from U-1 preceding symbol blocks B_i+u-i,... ,B_i-1 are used to obtain the current symbol block B_i. The construction of modified staircase FEC codes with U>2 further improves the overall error correction capability of the modified staircase FEC codes compared to the case of U=2 (i.e., the modified staircase FEC code described above) when the modified staircase FEC codes in both cases employ the same component FEC codes and have the same codeword length and code rate. When U>2, each sub-block used for obtaining the current symbol block B_i must have the same size such that m1, m2, q1 and q2 satisfy m1=m2, q1=q2. Hereinafter, for ease of description, the parameters mi=m2=m, qi=q2=q will be used when describing the encoding of the modified staircase FEC code having a coupling width of U>2. When U=2, the encoding process is the sub-process 400.

[00111] A component FEC code Ci is the set of all codewords generated by its corresponding FEC encoding for the modified staircase code. Each codeword has length ni, predetermined symbol length ei, data length K-_iei and parity data length ni-K._i Each row of a combination of a symbol block B_i, the rearranged sub-blocks of preceding symbol blocks B_i+u-i,... ,B_i.i, and a predetermined symbol block Oi or each column of the transpose of that combination is a codeword of the component FEC code Ci.

[00112] Fig. 9 shows a flow diagram of sub-process 500. Sub-process 500 is a software application program 1333 executable within the computer system 1300 (see the discussion below in relation to Figs. 8A and 8B). Sub-process 500 commences at step 502 by initialising predetermined symbol block Bo,... ., Bu-2. Examples of the predetermined symbols blocks Bo,... ., BU-2 are zero matrices. Sub-process 500 proceeds from step 502 to step 504.

[00113] In step 504, sub-process 500 divides each of the preceding symbol blocks 1, where i = U-1 , ... ,L and U>2. Each of these U-1 preceding symbol block is an m/q by m matrix. Each of the preceding symbol blocks is divided into q sub-blocks of size m/q by m/q such that Sub-process 500 then proceeds from step 504 to step 506.

[00114] In step 506, each of the sub-blocks of the preceding symbol blocks is transposed. The transposed sub-blocks are represented by

Similar to sub-process 400, the transposition of the sub-blocks can be followed with rearrangement of the transposed sub-blocks (see steps 410A and 410B above). Sub-process 500 then proceeds from step 506 to step 507.

[00115] In step 507, sub-process 500 recombines the transposed sub-blocks of each of the preceding symbol blocks For example, sub-blocks are recombined into B^T,- U+I . Therefore, the recombined, preceding symbol blocks are Sub-process 500 then proceeds from step 507 to step 508.

[00116] In step 508, each of the recombined, preceding symbol blocks is divided into U-1 sub-blocks of size m/(U-1) by m/q such that Sub-process 500 then proceeds from step 508 to step 510.

[00117] In step 510, sub-process 500 determines whether the index / is an even or odd number. If the index / is an odd number, then sub-process 500 proceeds from step 510 to step 511 A. Otherwise, if the index / is an even number, sub-process 500 proceeds from step 510 to step 511 B.

[00118] In step 511A, the l-th transposed sub-blocks obtained at step 508 from where , are concatenated with the predetermined symbol block Oi and the data K_i to obtain a concatenated block of As discussed hereinbefore, the predetermined symbol block Oi is an m/q by ei matrix (as i is an odd number) and includes predetermined symbols that are known to the encoder-decoder pair. The data K_i is an m/q by matrix. Accordingly, the concatenated symbol block is an matrix. Sub-process 500 proceeds from step 511A to step 512A.

[00119] In step 512A, the parity data P_i for the concatenated block is determined. As discussed hereinbefore in relation to step 414A, FEC encoding of component FEC code C₁ is performed as the index i is an odd number. The parity data P_i is obtained for each row of the concatenated block by performing FEC encoding of component FEC code C₁ on that row. As discussed hereinbefore, examples of the FEC encoding include but not limited to BCH encoding, RS encoding, LDPC encoding, Hamming encoding, turbo encoding, and polar encoding. Accordingly, the codeword matrix is represented by where each row of C; is a codeword of component FEC code C₁.

[00120] Sub-process 500 proceeds from step 512A to step 514A.

[00121] In step 514A, sub-process 500 generates a symbol block B_i for the associated index i. The symbol block B_i is a combination of the data K_i and the parity data P_i. Sub-process 500 proceeds from step 514A to step 515.

[00122] In step 515, sub-process 500 determines whether there are remaining symbol blocks B_i to process. In one arrangement, the determination is performed by determining whether the index i=L, where L is the last index (see step 304 above). If i<L, then sub-process 500 determines that there are remaining symbol blocks B_i to process. Sub-process 500 then increases the index i by 1. Sub-process 500 then proceeds from step 515 to step 504. Otherwise (i.e. , i=L), sub-process 500 concludes. At the conclusion of sub-process 500, the symbol blocks B_i obtained at steps 514A and 514B (which correspond to the input data received at step 302) are sent via the communication channel. When transmitting the symbol blocks B_i, the predetermined symbol block Oi can be removed to reduce the amount of data being transmitted. As the predetermined symbol block Oi is known by the decoder, the decoder provides the symbol block Oi when decoding the received symbol blocks B_i (without the symbol block Oi).

[00123] The corresponding steps 511 B to 514B for obtaining the symbol block B_i, when the index i is an even number, will now be described.]

[00124] In step 511 B, the l-th transposed sub-blocks obtained at step 508 from B_i-u+i, where I=1 ,... U-1, are concatenated with the predetermined symbol block Oi and the data K_i to obtain a concatenated block of As discussed hereinbefore, the predetermined symbol block Oi is an m/q by e₂ matrix (as i is an even number) and includes predetermined symbols that are known to the encoder-decoder pair. The data K_i is an m/q by k2-m-e2 matrix. Accordingly, the concatenated symbol block is an m/q by k2 matrix. Sub-process 500 proceeds from step 511 B to step 512B.

[00125] In step 512B, the parity data P_i for the concatenated block is determined. As discussed hereinbefore in relation to step 414B, FEC encoding of component FEC code C2 is performed as the index / is an even number. The parity data P_i is obtained for each row of the concatenated block by performing FEC encoding of component FEC code C2 on that row. As discussed hereinbefore, examples of the FEC encoding include but not limited to BCH encoding, RS encoding, LDPC encoding, Hamming encoding, turbo encoding, and polar encoding. Accordingly, the codeword matrix is represented by where each row of C; is a codeword of component FEC code C₁.

[00126] Sub-process 500 proceeds from step 512B to step 514B.

[00127] In step 514B, sub-process 500 generates a symbol block B_i for the associated index /. The symbol block B_i is a combination of the data K_i and the parity data P_i. Sub-process 500 proceeds from step 514B to step 515, which is already described hereinbefore.

[00128] When the modified staircase FEC code has a coupling width II of greater than 2 and the encoding is performed by sub-process 500. The decoding of such a modified staircase FEC code is performed by a decoding method 900 (shown in Fig. 10). The method 900 is a software application program 1333 executable within the computer system 1300 (see the discussion below in relation to Figs. 8A and 8B).

[00129] The method 900 commences at step 902 by receiving a sequence of symbol blocks Yj. As discussed above in relation to step 515 of sub-process 500, the symbol blocks B_i are transmitted, but not the predetermined symbol block Oi. For ease of identification between the symbol blocks being transmitted and the symbol blocks being received, the transmitted symbol blocks B_i are represented by the received symbol blocks Yj, where i=U-1 ,... ,L and U>2. The decoder also has a parameter called decoding window size W, where ll< W<L. The decoding window W sets the number of received symbol blocks Yj to be considered when performing the decoding. The decoder receives symbol blocks (or equivalently is the w-th symbol block among the W received symbol blocks Y,...,Y+w-i in a decoding window with size W and 1 < w < W) and output Yj.

[00130] The method 900 proceeds from step 902 to step 904.

[00131] In step 904, the predetermined symbol blocks are initialised based on the received symbol blocks Y. Step 904 also initialises syndrome blocks because their associated symbol blocks are predetermined and known by the decoder. The values of syndrome blocks are used for improving the decoding reliability. As discussed in relation to sub-process 500, each row of a combination of three symbol blocks Oi, sub-blocks of B_i.u+1,... , B_i.1 and B_i is a codeword of component FEC code Ci. The parameters m, q, ni, ki, n2, k2, ei , and e2as well as the types of component FEC codes C₁ and C2 are known by the decoder. The method 900 proceeds from step 904 to 905.

[00132] Within the decoding window W, the decoder can choose to operate either in forward scheduling or backward scheduling. When forward scheduling is performed, among the W received symbol blocks is decoded first, followed by When backward scheduling is performed, among the W received symbol blocks is decoded first, followed by

[00133] In step 905, each of the preceding symbol blocks is divided into q sub- blocks of size m/q by m/q, The method 900 proceeds from step 905 to step 906.

[00134] In step 906, each of the sub-blocks of the preceding symbol block is transposed. The transposed sub-blocks are represented by 2,q]. Each of the preceding symbol blocks is an m/q by m matrix. Therefore, each of the sub-blocks transposed preceding symbol blocks is still an m/q by m matrix. If the optional rearrangement step is performed after step 506 is performed, then the transposed sub-blocks also need to be rearranged accordingly. The method 900 proceeds from step 906 to 907.

[00135] In step 907, the method 900 recombines the transposed sub-blocks of each of the preceding symbol blocks For example, sub-blocks are recombined into Therefore, the recombined, preceding symbol blocks are The method 900 then proceeds from step 907 to step 908.

[00136] In step 908, each of the recombined, preceding symbol blocks are divided into U-1 sub-blocks of size m/(U-1) by m/q such that The method 900 then proceeds from step 908 to step 909.

[00137] In step 909, the method 900 determines whether (/ + w -1) is an even or odd number. If (/ + w -1) is an even number, then the method 900 proceeds from step 909 to step 910A. Otherwise, if (/ + w -1) is an odd number, the method 900 proceeds from step 909 to step 910B.

[00138] In step 910A, the method 900 determines a concatenated symbol block The concatenated symbol block is a combination of the predetermined symbol block the l-th transposed sub-blocks from where 1=1 ,... U-1 of step 908, and the symbol block Accordingly, the concatenated symbol block The predetermined symbol block is known by the decoder, as discussed hereinbefore in relation to step 511 A. The predetermined symbol block is an m/q by e2 matrix as is an even number, while the symbol block is an m/q by m matrix. The concatenated symbol bloc is an m/q by n₂ matrix. The method 900 proceeds from step 910A to 911 A.

[00139] In step 911A, the method 900 calculates a first syndrome block of the concatenated symbol block and a first index set associated with the concatenated symbol block The first syndrome block is calculated using the equation: where H2 is the parity-check matrix of the component FEC code C2. The parity-check matrix H2 is an n2-k2 by n2 matrix related to the encoding used to obtain the parity data P_i. The first syndrome block Sj+_w-i is an m/q by n2-k2 matrix.

[00140] The first index set is calculated using the equation where s_r is the r-th row of If the first syndrome block the method 900 then proceeds from step 911A to 912A. Otherwise, if the first syndrome block the method 900 then proceeds from step 911 A to step 915.

[00141] In step 912A, the r-th row of the concatenated symbol block is decoded by a component FEC decoder, which corresponds to the FEC encoder used in the sub-process 800. The FEC decoder uses and the first index set which are computed in step 911 A. Examples of component FEC decoders include but not limited to BCH decoding, turbo decoding, polar decoding, LDPC decoding, Hamming decoding, and RS decoding. The component FEC decoder returns a decoded sequence. The decoder of the component FEC code C2 can correct up to t2 errors. If the number of errors in a row of the concatenated symbol block is no larger than t2, the decoded sequence is correct. Otherwise, the decoded sequence is incorrect. A decoded symbol block is obtained by the FEC decoder, where each row in the decoded symbol block is the decoded sequence corresponding to a corresponding row in the concatenated symbol block Dj+_w-i . The method 900 proceeds from step 912A to step 913A.

[00142] In step 913A, the method 900 calculates a second syndrome block and a second index set l_i+w-i based on the decoded symbol block The second syndrome block is calculated using the equation: The second index set is calculated using the equation: where s_r is the r-th row of the second syndrome block is the r-th row of decoded symbol block is the r-th row of predetermined symbol block ^and ^are th® sub-vectors by taking the first e₂ elements of d_r and o_r, respectively. The method 900 then proceeds from step 913A to 914A.

[00143] In step 914A, the method 900 updates the received symbol blocks dependent on the r-th rows of the decoded symbol block that have zero syndrome (i.e. , s_r = 0) in the second syndrome block and no errors in the first e₂ symbols (i.e., d_r(1: e₂) = and the second index set are determined in step 913A.

Having a zero syndrome in the second syndrome block means that the particular row of the decoded symbol block is a valid codeword of component FEC code C2. If the syndrome of the r-th row of the decoded symbol block D is zero and at that row the first e₂ symbols are correct, then the method 900 replaces the r-th row of the concatenated symbol block with the r-th row of the decoded symbol block As discussed in step 909 above, the concatenated symbol block Thus, updating the concatenated symbol block results in the received symbol blocks being updated (where / is an even number). In other words, step 913A determines whether the received symbol blocks and are correct and, if incorrect, then rectifies the received symbol blocks symbol blocks and accordingly. The method 900 proceeds from step 914A to step 915. [00144] Before describing step 915, the corresponding steps 91 OB to 914B will be described first.

[00145] In step 91 OB, the method 900 determines a concatenated symbol block The concatenated symbol block is a combination of the predetermined symbol block Oi+_w-i, the l-th transposed sub-blocks from where 1=1 ,... U-1 of step 908, and the symbol block Accordingly, the concatenated symbol block The predetermined symbol block is known by the decoder, as discussed hereinbefore in relation to step 511 B. The predetermined symbol block is an m/q by ei matrix as i+w-1 is an odd number, while the symbol block is an m/q by m matrix. The concatenated symbol block Dj+w-i is an m/q by matrix. The method 900 proceeds from step 910B to 911 B.

[00146] In step 911 B, the method 900 calculates a first syndrome block of the concatenated symbol block and a first index set associated with the concatenated symbol block The first syndrome block is calculated using the equation: where Hi is the parity-check matrix of the component FEC code C₁. The parity-check matrix Hi is an ni-ki by ni matrix related to the encoding used to obtain the parity data P_i. The first syndrome block is an m/q by m-ki matrix.

[00147] The first index set is calculated using the equation where s_r is the r-th row of If the first syndrome block the method 900 then proceeds from step 911 B to 912B. Otherwise, if the first syndrome block the method 900 then proceeds from step 911 B to step 915.

[00148] In step 912B, the r-th row of the concatenated symbol block is decoded by a component FEC decoder, which corresponds to the FEC encoder used in the sub-process 800. The FEC decoder uses and the first index set which are computed in step 911 B. Examples of component FEC decoders include but not limited to BCH decoding, turbo decoding, polar decoding, LDPC decoding, Hamming decoding, and RS decoding. The component FEC decoder returns a decoded sequence. The decoder of the component FEC code C₁ can correct up to ti errors. If the number of errors in a row of the concatenated symbol block Dj+w-i is no larger than ti , the decoded sequence is correct. Otherwise, the decoded sequence is incorrect. A decoded symbol block is obtained by the FEC decoder, where each row in the decoded symbol block is the decoded sequence corresponding to a corresponding row in the concatenated symbol block . The method 900 proceeds from step 912B to 913B. [00149] In step 913B, the method 900 calculates a second syndrome block and a second index set based on the decoded symbol block The second syndrome block is calculated using the equation: The second index set is calculated using the equation: where s_r is the r-th row of the second syndrome block is the r-th row of decoded symbol block is the r-th row of predetermined symbol block ( ) and are the sub-vectors by taking the first ei elements of d_r and o_r, respectively. The method 900 then proceeds from step 913B to 914B.

[00150] In step 914B, the method 900 updates the received symbol blocks dependent on the r-th rows of the decoded symbol block that have zero syndrome (i.e. , in the second syndrome block and no errors in the first ei symbols , where and the second index set are determined in step 913B. Having a zero syndrome means that the particular row of the decoded symbol block is a valid codeword of component FEC code C₁. If the syndrome of the r-th row of the decoded symbol block is zero and at that row the first ei symbols are correct, then the method 900 replaces the r-th row of the concatenated symbol block with the r-th row of the decoded symbol block As discussed in step 909 above, the concatenated symbol block Thus, updating the concatenated symbol block results in the received symbol blocks being updated (where / is an odd number). Therefore, the combination of steps 914A and 914B results in all the received symbol blocks Y being updated (dependent on the syndrome of the corresponding second syndrome block). In other words, step 913B determines whether the received symbol blocks and are correct and, if incorrect, then rectifies the received symbol blocks symbol blocks and accordingly. The method 900 proceeds from step 914B to step 915.

[00151] In step 915, the method 900 determines whether there are remaining decoding window to process. When forward scheduling is used, the determination is performed by determining whether the index w=W, where W is the last index (see step 902 above). If w<W, then the method 900 determines that there are remaining decoding window to process. The method 900 then increases the index w by 1. The method 900 then proceeds from step 915 to step 905. Otherwise (i.e., w=W), the method 900 proceeds to step 917. When backward scheduling is used, the determination is performed by determining whether the index w=1, where 1 is the first index (see step 902 above). If w>1 , then the method 900 determines that there are remaining decoding window to process. The method 900 then reduces the index w by 1 . The method 900 then proceeds from step 915 to step 905. Otherwise (i.e., w=1), the method 900 proceeds to step 917.

[00152] In step 917, the method 900 determines whether predetermined requirements of the decoding process are met. In one arrangement, the predetermined requirement is the number of times I that a cycle of steps 905 to 915 has been performed. If the number of cycle l< l_max, then the method 900 determines that the predetermined requirement is not met. The method 900 then increases the number of cycle by 1. In another arrangement, the method 900 determines whether the index /=L-W+1 , where L is the last index (see step 902 above). If / < L- W+1 , then the method 900 determines whether a syndrome block Sj=O (i.e., w=1). Since the FEC decoder processes W received symbol blocks Y,... ,Y+w-i and outputs updated symbol blocks Yj (a combination of steps 914A and 914B), the determination that the syndrome block Sj=O confirms that the decoding of Yj is successful. Otherwise, if / >L-W+1 , the method 900 determines whether the syndrome blocks [SL-W+I , ... ,SL]=0. The determination that the syndrome block confirms that the decoding of the last W received blocks YL-W+I , ... ,YL is successful. The predetermined requirements can be combined.

[00153] In an alternative arrangement, step 917 determines whether the syndrome block Sj.j=O for j=1 ,... , U-1. If it means that the received symbol block Y-j was successfully decoded prior to the decoding of Y,... ,Y+w-i or Yj.j is the predetermined symbol block known by the decoder. Then, j is assigned by its original value prior to the decoding of Otherwise, if no changes are applied to . Updating results in the concatenated symbol block Dj+k (see step 910A and 910B) for k=0,... ,U-2 being updated. Then, the updated syndrome blocks Sj+kfor k=0,... ,U-2, are computed by following step 905 to step 911 A if the index i+k is even or step 905 to step 911 B if the index i+k is odd.

[00154] If the method 900 determines that the predetermined requirements are met (YES), then the method 900 proceeds from step 917 to step 919. Otherwise (NO), the method 900 proceeds from step 917 to step 905.

[00155] In an alternative arrangement, if the method 900 determines that the predetermined requirements are met (YES), then the method 900 proceeds from step 917 to step 905 and sets the cycle I =l_max- Imax2. As discussed above, the decoder performs either forward scheduling or backward scheduling when processing the received symbol blocks within the decoding window W. At step 917, the method 900 sets the decoder to perform backward scheduling regardless whether the decoder is initially set to perform forward scheduling or backward scheduling. Accordingly, in a first cycle, the decoder performs forward scheduling for a first group (as determined by the size of the decoding window W) of received symbol blocks and performs backward scheduling in subsequent cycles for the subsequent groups of the received symbol blocks. Alternatively, the decoder performs backward scheduling in all cycles for all groups of the received symbol blocks. If the predetermined requirements are met for times, then the method 900 proceeds from step 917 to step 919.

[00156] In step 919, if / < L-W+1, the updated symbol block Yj (i.e., w=1) is output. Otherwise, if / the updated symbol blocks are output. The method 900 proceeds from step 919 to step 921.

[00157] In step 921, the method 900 determines whether there are remaining received data symbols to process. In one arrangement, the determination is performed by determining whether the index where L is the last index (see step 902 above). W+1 (YES), then the method 900 determines that there are remaining data symbols to process. The method 900 then increases the index / by 1. The method 900 then proceeds from step 921 to step 905. Otherwise (i.e., />L-W+1) (NO), the method 900 concludes.

Computer Description

[00158] Figs. 8A and 8B depict a general-purpose computer system 1300, upon which an FEC encoder or an FEC decoder described can be practiced.

[00159] As seen in Fig. 8A, the computer system 1300 includes: a computer module 1301; input devices such as a keyboard 1302, a mouse pointer device 1303, a scanner 1326, a camera 1327, and a microphone 1380; and output devices including a printer 1315, a display device 1314 and loudspeakers 1317. An external Modulator-Demodulator (Modem) transceiver device 1316 may be used by the computer module 1301 for communicating to and from a communications network 1320 via a connection 1321. The communications network 1320 may be a wide-area network (WAN), such as the Internet, a cellular telecommunications network, or a private WAN. Where the connection 1321 is a telephone line, the modem 1316 may be a traditional “dial-up” modem. Alternatively, where the connection 1321 is a high capacity (e.g., cable) connection, the modem 1316 may be a broadband modem. A wireless modem may also be used for wireless connection to the communications network 1320.

[00160] The computer module 1301 typically includes at least one processor unit 1305, and a memory unit 1306. For example, the memory unit 1306 may have semiconductor random access memory (RAM) and semiconductor read only memory (ROM). The computer module 1301 also includes an number of input/output (I/O) interfaces including: an audio-video interface 1307 that couples to the video display 1314, loudspeakers 1317 and microphone 1380; an I/O interface 1313 that couples to the keyboard 1302, mouse 1303, scanner 1326, camera 1327 and optionally a joystick or other human interface device (not illustrated); and an interface 1308 for the external modem 1316 and printer 1315. In some implementations, the modem 1316 may be incorporated within the computer module 1301 , for example within the interface 1308. The computer module 1301 also has a local network interface 1311 , which permits coupling of the computer system 1300 via a connection 1323 to a local-area communications network 1322, known as a Local Area Network (LAN). As illustrated in Fig. 8A, the local communications network 1322 may also couple to the wide network 1320 via a connection 1324, which would typically include a so-called “firewall” device or device of similar functionality. The local network interface 1311 may comprise an Ethernet circuit card, a Bluetooth® wireless arrangement or an IEEE 802.11 wireless arrangement; however, numerous other types of interfaces may be practiced for the interface 1311.

[00161] The I/O interfaces 1308 and 1313 may afford either or both of serial and parallel connectivity, the former typically being implemented according to the Universal Serial Bus (USB) standards and having corresponding USB connectors (not illustrated). Storage devices 1309 are provided and typically include a hard disk drive (HDD) 1310. Other storage devices such as a floppy disk drive and a magnetic tape drive (not illustrated) may also be used. An optical disk drive 1312 is typically provided to act as a non-volatile source of data. Portable memory devices, such optical disks (e.g., CD-ROM, DVD, Blu-ray Disc™), USB-RAM, portable, external hard drives, and floppy disks, for example, may be used as appropriate sources of data to the system 1300.

[00162] The components 1305 to 1313 of the computer module 1301 typically communicate via an interconnected bus 1304 and in a manner that results in a conventional mode of operation of the computer system 1300 known to those in the relevant art. For example, the processor 1305 is coupled to the system bus 1304 using a connection 1318. Likewise, the memory 1306 and optical disk drive 1312 are coupled to the system bus 1304 by connections 1319. Examples of computers on which the described arrangements can be practised include IBM-PC’s and compatibles, Sun Sparcstations, Apple Mac™ or like computer systems.

[00163] The method of encoding data to codewords and decoding codewords into data may be implemented using the computer system 1300 wherein the processes of Figs. 3, 4, 8A, and 8B, described above, may be implemented as one or more software application programs 1333 executable within the computer system 1300. In particular, the steps of the method of Figs. 3, 4, 8A, and 8B are effected by instructions 1331 (see Fig. 8B) in the software 1333 that are carried out within the computer system 1300. The software instructions 1331 may be formed as one or more code modules, each for performing one or more particular tasks. The software may also be divided into two separate parts, in which a first part and the corresponding code modules performs the encoding and decoding methods and a second part and the corresponding code modules manage a user interface between the first part and the user.

[00164] The software may be stored in a computer readable medium, including the storage devices described below, for example. The software is loaded into the computer system 1300 from the computer readable medium, and then executed by the computer system 1300. A computer readable medium having such software or computer program recorded on the computer readable medium is a computer program product. The use of the computer program product in the computer system 1300 preferably effects an advantageous apparatus for encoding data into codewords and decoding codewords into data.

[00165] The software 1333 is typically stored in the HDD 1310 or the memory 1306. The software is loaded into the computer system 1300 from a computer readable medium, and executed by the computer system 1300. Thus, for example, the software 1333 may be stored on an optically readable disk storage medium (e.g., CD-ROM) 1325 that is read by the optical disk drive 1312. A computer readable medium having such software or computer program recorded on it is a computer program product. The use of the computer program product in the computer system 1300 preferably effects an apparatus for encoding data into codewords and decoding codewords into data.

[00166] In some instances, the application programs 1333 may be supplied to the user encoded on one or more CD-ROMs 1325 and read via the corresponding drive 1312, or alternatively may be read by the user from the networks 1320 or 1322. Still further, the software can also be loaded into the computer system 1300 from other computer readable media. Computer readable storage media refers to any non-transitory tangible storage medium that provides recorded instructions and/or data to the computer system 1300 for execution and/or processing. Examples of such storage media include floppy disks, magnetic tape, CD-ROM, DVD, Blu-ray™ Disc, a hard disk drive, a ROM or integrated circuit, USB memory, a magneto- optical disk, or a computer readable card such as a PCMCIA card and the like, whether or not such devices are internal or external of the computer module 1301. Examples of transitory or non-tangible computer readable transmission media that may also participate in the provision of software, application programs, instructions and/or data to the computer module 1301 include radio or infra-red transmission channels as well as a network connection to another computer or networked device, and the Internet or Intranets including e-mail transmissions and information recorded on Websites and the like.

[00167] The second part of the application programs 1333 and the corresponding code modules mentioned above may be executed to implement one or more graphical user interfaces (GUIs) to be rendered or otherwise represented upon the display 1314. Through manipulation of typically the keyboard 1302 and the mouse 1303, a user of the computer system 1300 and the application may manipulate the interface in a functionally adaptable manner to provide controlling commands and/or input to the applications associated with the GUI(s). Other forms of functionally adaptable user interfaces may also be implemented, such as an audio interface utilizing speech prompts output via the loudspeakers 1317 and user voice commands input via the microphone 1380.

[00168] Fig. 8B is a detailed schematic block diagram of the processor 1305 and a “memory” 1334. The memory 1334 represents a logical aggregation of all the memory modules (including the HDD 1309 and semiconductor memory 1306) that can be accessed by the computer module 1301 in Fig. 8A.

[00169] When the computer module 1301 is initially powered up, a power-on self-test (POST) program 1350 executes. The POST program 1350 is typically stored in a ROM 1349 of the semiconductor memory 1306 of Fig. 8A. A hardware device such as the ROM 1349 storing software is sometimes referred to as firmware. The POST program 1350 examines hardware within the computer module 1301 to ensure proper functioning and typically checks the processor 1305, the memory 1334 (1309, 1306), and a basic input-output systems software (BIOS) module 1351, also typically stored in the ROM 1349, for correct operation. Once the POST program 1350 has run successfully, the BIOS 1351 activates the hard disk drive 1310 of Fig. 8A. Activation of the hard disk drive 1310 causes a bootstrap loader program 1352 that is resident on the hard disk drive 1310 to execute via the processor 1305. This loads an operating system 1353 into the RAM memory 1306, upon which the operating system 1353 commences operation. The operating system 1353 is a system level application, executable by the processor 1305, to fulfil various high level functions, including processor management, memory management, device management, storage management, software application interface, and generic user interface.

[00170] The operating system 1353 manages the memory 1334 (1309, 1306) to ensure that each process or application running on the computer module 1301 has sufficient memory in which to execute without colliding with memory allocated to another process. Furthermore, the different types of memory available in the system 1300 of Fig. 8A must be used properly so that each process can run effectively. Accordingly, the aggregated memory 1334 is not intended to illustrate how particular segments of memory are allocated (unless otherwise stated), but rather to provide a general view of the memory accessible by the computer system 1300 and how such is used.

[00171] As shown in Fig. 8B, the processor 1305 includes a number of functional modules including a control unit 1339, an arithmetic logic unit (ALU) 1340, and a local or internal memory 1348, sometimes called a cache memory. The cache memory 1348 typically includes a number of storage registers 1344 - 1346 in a register section. One or more internal busses 1341 functionally interconnect these functional modules. The processor 1305 typically also has one or more interfaces 1342 for communicating with external devices via the system bus 1304, using a connection 1318. The memory 1334 is coupled to the bus 1304 using a connection 1319.

[00172] The application program 1333 includes a sequence of instructions 1331 that may include conditional branch and loop instructions. The program 1333 may also include data 1332 which is used in execution of the program 1333. The instructions 1331 and the data 1332 are stored in memory locations 1328, 1329, 1330 and 1335, 1336, 1337, respectively. Depending upon the relative size of the instructions 1331 and the memory locations 1328-1330, a particular instruction may be stored in a single memory location as depicted by the instruction shown in the memory location 1330. Alternately, an instruction may be segmented into a number of parts each of which is stored in a separate memory location, as depicted by the instruction segments shown in the memory locations 1328 and 1329.

[00173] In general, the processor 1305 is given a set of instructions which are executed therein. The processor 1305 waits for a subsequent input, to which the processor 1305 reacts to by executing another set of instructions. Each input may be provided from one or more of a number of sources, including data generated by one or more of the input devices 1302, 1303, data received from an external source across one of the networks 1320, 1302, data retrieved from one of the storage devices 1306, 1309 or data retrieved from a storage medium 1325 inserted into the corresponding reader 1312, all depicted in Fig. 8A. The execution of a set of the instructions may in some cases result in output of data. Execution may also involve storing data or variables to the memory 1334. [00174] The disclosed arrangements use input variables 1354, which are stored in the memory 1334 in corresponding memory locations 1355, 1356, 1357. The arrangements produce output variables 1361, which are stored in the memory 1334 in corresponding memory locations 1362, 1363, 1364. Intermediate variables 1358 may be stored in memory locations 1359, 1360, 1366 and 1367.

[00175] Referring to the processor 1305 of Fig. 8B, the registers 1344, 1345, 1346, the arithmetic logic unit (ALU) 1340, and the control unit 1339 work together to perform sequences of micro-operations needed to perform “fetch, decode, and execute” cycles for every instruction in the instruction set making up the program 1333. Each fetch, decode, and execute cycle comprises:

[00176] a fetch operation, which fetches or reads an instruction 1331 from a memory location 1328, 1329, 1330;

[00177] a decode operation in which the control unit 1339 determines which instruction has been fetched; and

[00178] an execute operation in which the control unit 1339 and/or the ALU 1340 execute the instruction.

[00179] Thereafter, a further fetch, decode, and execute cycle for the next instruction may be executed. Similarly, a store cycle may be performed by which the control unit 1339 stores or writes a value to a memory location 1332.

[00180] Each step or sub-process in the processes of Figs. 3, 4, 8A, and 8B is associated with one or more segments of the program 1333 and is performed by the register section 1344, 1345, 1347, the ALU 1340, and the control unit 1339 in the processor 1305 working together to perform the fetch, decode, and execute cycles for every instruction in the instruction set for the noted segments of the program 1333.

[00181] The method of encoding and decoding may alternatively be implemented in dedicated hardware such as one or more integrated circuits performing the functions or sub functions of the methods shown in Figs. 3, 4, 8A, and 8B. Such dedicated hardware may include graphic processors, digital signal processors, or one or more microprocessors and associated memories. Industrial Applicability

[00182] The arrangements described are applicable to the computer and data processing industries and particularly for the modified staircase forward error correction coding.

[00183] The foregoing describes only some embodiments of the present invention, and modifications and/or changes can be made thereto without departing from the scope and spirit of the invention, the embodiments being illustrative and not restrictive.

[00184] In the context of this specification, the word “comprising” means “including principally but not necessarily solely” or “having” or “including”, and not “consisting only of”. Variations of the word "comprising", such as “comprise” and “comprises” have correspondingly varied meanings.

Claims (23)

CLAIMS:

1. A method of generating a sequence of symbol blocks, the generated symbol blocks comprising data encoded with forward error correction (FEC) encoding, the method comprising: decomposing one of the symbol blocks; transposing the decomposed symbol block; and generating a proceeding symbol block using the decomposed and transposed symbol block.

2. The method of claim 1 , wherein a coupling width determines the number of the symbol blocks being decomposed and transposed, and wherein the proceeding symbol block is generated using the decomposed and transposed symbol blocks.

3. The method of claim 1 or 2, wherein a symbol block is decomposed by dividing the symbol block into sub-blocks.

4. The method of claim 3, wherein the step of transposing the decomposed symbol block comprises transposing each sub-block.

5. The method of any one of claims 1 to 4, further comprising: rearranging the transposed and decomposed symbol block.

6. The method of claim 5, wherein the rearrangement comprises a permutation function.

7. The method of any one of claims 3 to 6, when dependent on claim 2, further comprising: recombining the transposed sub-blocks into a corresponding symbol block; and dividing the recombined symbol block, based on the coupling width, into sub-blocks.

8. The method of any one of claims 1 to 7, further comprising: determining parity data based on the transposed, decomposed symbol block.

9. The method of any one of claims 1 to 8, wherein the step of generating the proceeding symbol block is based on the determined parity data.

10. The method of any one of claims 1 to 9, wherein the generated symbol block is transmitted.

11. The method of any one of claims 1 to 10, wherein the step of decomposing one of the symbol blocks is based on a symbol block index.

12. A method of decoding a sequence of received symbol blocks, the received symbol blocks comprising data encoded with forward error correction (FEC) encoding, the method comprising: decomposing one of the symbol blocks; transposing the decomposed symbol block; and determining whether a proceeding received symbol block is correct based on the transposed, decomposed symbol block.

13. The method of claim 12, wherein a coupling width determines the number of the received symbol blocks being decomposed and transposed, and wherein the proceeding symbol block is generated using the decomposed and transposed symbol blocks.

14. The method of claim 12 or 13, wherein a symbol block is decomposed by dividing the symbol block into sub-blocks.

15. The method of claim 14, wherein the step of transposing the decomposed symbol block comprises transposing each sub-block.

16. The method of claim 14 or 15, when dependent on claim 12, further comprising: recombining the transposed sub-blocks into a corresponding symbol block; and dividing the recombined symbol block, based on the coupling width, into sub-blocks.

17. The method of any one of claims 14 to 16, further comprising: determining a concatenated symbol block based on the divided symbol block; calculating a first syndrome block based on the concatenated symbol block; generating a decode symbol block based on the first syndrome block; calculating a second syndrome block based on the decoded symbol block; determining whether the decoded symbol block is correct based on the second syndrome block; and updating the received symbol block based on the determination whether the decoded symbol block is correct.

18. The method of any one of claims 12 to 17, wherein the step of decomposing one of the symbol blocks is based on a symbol block index.

19. The method of any one of claims 12 to 18, wherein, in a first cycle, a first group of the received symbol blocks is decoded in forward scheduling or backward scheduling, wherein the first group is determined by the size of a decoding window, and wherein, in subsequent cycles, subsequent groups of the received symbol blocks are decoded in backward scheduling, wherein each of the subsequent groups is determined by the size of the decoding window.

20. A computer program product comprising a method generating a sequence of symbol blocks according to any one of claims 1 to 11.

21. A computer program product comprising a method decoding a sequence of received symbol blocks according to any one of claims 12 to 19.

22. An apparatus configured for performing a method generating a sequence of symbol blocks according to any one of claims 1 to 11.

23. An apparatus configured for performing a method decoding a sequence of received symbol blocks according to any one of claims 12 to 19.