WO2023021887A1 - Electronic component module - Google Patents

Abstract

An electronic component module 100 in which components are mounted on both surfaces of a substrate is characterized by being provided with: an inorganic material substrate 110 having a first main surface 111 on which a plurality of first electrodes 141 are provided, and a second main surface 112 on which a plurality of second electrodes 142 are provided; a first electronic component 121 having a mounting surface on which a plurality of external terminals 131 connected to the plurality of first electrodes 141 are provided; a planarizing layer 161 covering the second main surface 112; a plurality of third electrodes 143 which are provided on the planarizing layer 161 and which are connected to the plurality of second electrodes 142; and a second electronic component 122 having a mounting surface on which a plurality of external terminals 132 connected to the plurality of third electrodes 143 are provided.

Description

Electronic component module

The present invention relates to electronic component modules.

Patent Documents 1 and 2 disclose electronic component modules in which electronic components are mounted on one side or both sides of a substrate.

WO2015/098793 JP 2012-33885 A

In recent years, products that mount electronic components such as ICs (Integrated Circuits) that have mounting surfaces with multiple external terminals on both sides of inorganic material substrates such as low temperature co-fired ceramics (LTCC) substrates. is increasing, and it is necessary to minimize the height difference of the unevenness of the mounting portion of the inorganic material substrate to, for example, 15 μm or less. In particular, when one main surface of a low-temperature co-fired ceramic substrate is flattened, the opposite main surface tends to be affected by the wiring inside the substrate and have large unevenness (coplanarity). As a result, depending on the coplanarity and terminal pitch of the electronic component to be mounted, mounting defects, specifically open defects, may occur. In particular, when electronic components (especially ICs) having Cu pillar bumps are mounted on both sides of a low-temperature fired ceramic substrate, mounting defects are likely to occur.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an electronic component module capable of suppressing the occurrence of mounting defects.

An electronic component module of the present invention is an electronic component module in which components are mounted on both sides of a substrate, and has a first main surface provided with a plurality of first electrodes and a second main surface provided with a plurality of second electrodes. a first electronic component having a mounting surface provided with a plurality of external terminals connected to the plurality of first electrodes; a planarizing layer covering the second main surface; and the planarizing layer a second electronic component having a mounting surface provided with a plurality of third electrodes provided thereon and connected to the plurality of second electrodes; and a mounting surface provided with a plurality of external terminals connected to the plurality of third electrodes; characterized by comprising

According to the present invention, it is possible to provide an electronic component module capable of suppressing the occurrence of mounting defects.

FIG. 1 is a cross-sectional view schematically showing an example of an electronic component module of the present invention (first embodiment). FIG. 2 is a cross-sectional view schematically showing an example of Cu pillar bumps included in the electronic component of the present invention (first embodiment). FIG. 3 is an SEM photograph showing a cross section of the LTCC substrate used in the evaluation test. FIG. 4 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (first embodiment) in a manufacturing process, showing a step of mounting the first electronic component. FIG. 5 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (first embodiment) in a manufacturing process, showing a first resin sealing process. FIG. 6 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (first embodiment) in the manufacturing process, showing the grinding process of the sealing resin layer. FIG. 7 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (first embodiment) in the manufacturing process, showing the forming process of the flattening layer. FIG. 8 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (first embodiment) in the manufacturing process, showing a via hole forming process in the planarizing layer. FIG. 9 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (first embodiment) in a manufacturing process, showing a formation process of vias and electrodes. FIG. 10 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (first embodiment) in a manufacturing process, showing a process of mounting the second electronic component and the third electronic component. FIG. 11 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (first embodiment) in a manufacturing process, showing a second resin sealing process. FIG. 12 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (first embodiment) in a manufacturing process, showing a forming process of a metal conductor layer. FIG. 13 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (second embodiment). FIG. 14 is a cross-sectional view schematically showing another example of the electronic component module of the present invention (second embodiment). FIG. 15 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (second embodiment) in a manufacturing process, showing a step of mounting the first electronic component. FIG. 16 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (second embodiment) in the manufacturing process, showing the first resin sealing process. FIG. 17 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (second embodiment) in the manufacturing process, showing the grinding process of the sealing resin layer. FIG. 18 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (second embodiment) in the manufacturing process, showing the forming process of the planarizing layer. FIG. 19 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (second embodiment) in the manufacturing process, showing a via hole forming process in the planarizing layer. FIG. 20 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (second embodiment) in the manufacturing process, showing the formation process of vias and electrodes. FIG. 21 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (second embodiment) in a manufacturing process, showing a process of mounting the second electronic component and the third electronic component. FIG. 22 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (second embodiment) in a manufacturing process, showing a second resin sealing process. FIG. 23 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (second embodiment) in a manufacturing process, showing a forming process of a metal conductor layer. FIG. 24 is a cross-sectional view schematically showing an example of an electronic component module according to a comparative embodiment;

The electronic component module of the present invention will be described below.
However, the present invention is not limited to the following configurations and aspects, and can be appropriately modified and applied without changing the gist of the present invention. A combination of two or more of the individual preferred configurations and aspects of the present invention described below is also the present invention.

[First embodiment]
The electronic component module according to the first embodiment includes an electronic component having Cu (copper) pillar bumps as an electronic component having mounting surfaces provided with a plurality of external terminals on both sides of a low-temperature fired ceramic substrate as an inorganic material substrate ( Preferably, it is a module mounted with an IC), a flattening layer is formed on the major surface of the two surfaces of the low-temperature co-fired ceramic substrate, which has larger unevenness, and the above-mentioned electronic components are mainly mounted on the flattening layer. It is characterized by That is, as the rewiring layer, first, a flattening layer is formed from a resin material or the like on the main surface of the larger unevenness to flatten it, and then the electrodes of the low-temperature co-fired ceramic substrate are pulled out onto the flattening layer for component mounting. By forming the electrodes, that is, the mounting pads, the mounting portion of the electronic component has a flat structure.

FIG. 1 is a cross-sectional view schematically showing an example of an electronic component module of the present invention (first embodiment).
The electronic component module 100 shown in FIG. 1 is a substantially rectangular parallelepiped module, and includes a mounting surface 101, a top surface 102 facing the mounting surface 101, and four side surfaces 103 connecting the mounting surface 101 and the top surface 102. have. The mounting surface 101 is provided with a plurality of input/output electrodes (I/O electrodes) 104 connected to other electronic components and substrates. is composed of a metal conductor layer (shield electrode) 105 for blocking electromagnetic waves.

Further, the electronic component module 100 is an electronic component module in which components are mounted on both sides of a substrate. It includes a substrate (hereinafter, LTCC substrate) 110 , first electronic components 121 mounted on a first main surface 111 , and a plurality of second electronic components 122 mounted on a second main surface 112 .
The first electronic component 121 has a mounting surface provided with a plurality of Cu pillar bumps 131 as external terminals.
Each second electronic component 122 also has a mounting surface provided with a plurality of Cu pillar bumps 132 as external terminals.

The LTCC substrate 110 is a ceramic multilayer substrate in which insulating layers (at least one layer may be provided with vias) and conductor layers provided with wiring and electrodes are laminated. Metal materials such as silver and copper are used as materials for conductor layers and vias, and low-temperature sintered ceramic materials are used as insulating materials for insulating layers. A low-temperature sintering ceramic material is one type of ceramic material, and is a material that can be fired simultaneously with silver and copper used as metal materials at a firing temperature of 1000° C. _or less _. O ₃ —B ₂ O ₃ based glass ceramics or SiO ₂ —MgO—Al ₂ O ₃ —B ₂ O ₃ based glass ceramics.

The first main surface 111 of the LTCC substrate 110 is provided with a plurality of first electrodes (mounting pads) 141 corresponding to the plurality of Cu pillar bumps 131 (external terminals) of the first electronic component 121 one-to-one. The first electronic component 121 is flip-chip mounted on the first main surface 111 by connecting each Cu pillar bump 131 to the corresponding first electrode 141 .
Each first electrode 141 is connected to corresponding wiring (not shown) of the LTCC substrate 110 .

The first electronic component 121 is not particularly limited as long as it has a mounting surface provided with a plurality of external terminals. Here, a surface mount type electronic component having a plurality of Cu pillar bumps 131 as external terminals is mounted. ing.
Also, the first electronic component 121 is preferably an IC, and an SOI (Silicon On Insulator) 121a is mounted here. The first electronic component 121 may be, for example, a GaAs IC, Si IC, SiC IC, or the like.

Further, the electronic component module 100 includes a plurality of input/output electrodes 151 provided on the first main surface 111 of the LTCC substrate 110 and connected to the columnar input/output electrodes 104, the first electronic component 121 and the input/output electrodes. and a sealing resin layer 152 filled around 104 .

At least one first electronic component 121 may be mounted on the first main surface 111 of the LTCC substrate 110, and a plurality of first electronic components 121 may be mounted.

A plurality of second electrodes 142 and a planarizing layer 161 covering the second main surface 112 are provided on the second main surface 112 of the LTCC substrate 110 . Furthermore, a plurality of third electrodes (mounting pads) 143 connected to the plurality of second electrodes 142 are provided on the planarization layer 161 .

The second electrodes 142 are provided in one-to-one correspondence with the plurality of Cu pillar bumps 132 (external terminals) of each second electronic component 122 , and the third electrodes 143 are provided in one-to-one correspondence with the second electrodes 142 . , and each second electronic component 122 is flip-chip mounted on the second main surface 112 by connecting each Cu pillar bump 132 to the second electrode 142 via the corresponding third electrode 143 . It is Also, each third electrode 143 is connected to the corresponding second electrode 142 through vias 162 provided in the planarization layer 161 .
Each second electrode 142 is connected to corresponding wiring (not shown) of the LTCC substrate 110 .

The planarization layer 161 forms a substantially flat surface by absorbing unevenness of the base. The material of the flattening layer 161 is not particularly limited, but a material having fluidity before curing is preferable. mentioned.

The second electronic component 122 is not particularly limited as long as it has a mounting surface provided with a plurality of external terminals. Here, a surface-mounted electronic component having a plurality of Cu pillar bumps 132 as external terminals is mounted. ing.
Also, the second electronic component 122 is preferably an IC, and here, an HBT (Heterojunction Bipolar Transistor) IC 122a, a SAW (Surface Acoustic Wave) filter 122b and a GaAs IC 122c are mounted.

Also, although each third electrode 143 is arranged directly above the corresponding second electrode 142 here, each third electrode 143 extends in the substrate in-plane direction from directly above the corresponding second electrode 142 . , may be connected to the Cu pillar bumps 132 of the second electronic component 122 at locations other than directly above the corresponding second electrodes 142 .

A plurality of third electronic components 123 each having a pair of external electrodes 133 instead of Cu pillar bumps (external terminals) are mounted on the second main surface 112 of the LTCC substrate 110 .

More specifically, the second major surface 112 has a plurality of fourth electrodes 144 and a plurality of fifth electrodes (mounting pads) 145 provided on the planarization layer 161 and connected to the plurality of fourth electrodes 144 . and is provided. The fourth electrodes 144 are provided in one-to-one correspondence with the pair of external electrodes 133 of each third electronic component 123, and the fifth electrodes 145 are provided in one-to-one correspondence with the fourth electrodes 144. Each third electronic component 123 is surface-mounted on the second main surface 112 by connecting each external electrode 133 to a fourth electrode 144 via a corresponding fifth electrode 145 . Each external electrode 133 is connected to a corresponding fifth electrode 145 via, for example, solder 135 , and each fifth electrode 145 is connected to a corresponding fourth electrode 145 via vias 163 provided in the planarization layer 161 . It is connected with the electrode 144 . Although the third electronic component 123 is not particularly limited, here, for example, a chip capacitor 123a and a chip inductor 123b are mounted.
Each fourth electrode 144 is connected to corresponding wiring (not shown) of the LTCC substrate 110 .

The planarization layer 161 covers the plurality of second electrodes 142 and the plurality of fourth electrodes 144 except for the portions where the vias 162 and 163 are formed.
The planarizing layer 161, vias such as the via 162 provided in the planarizing layer 161, and the second electrode 142 and the like provided on the planarizing layer 161 function as a rewiring layer.

The electrodes such as the first electrode 141 provided on the first main surface 111 of the LTCC substrate 110 and the electrodes such as the second electrode 142 and the fourth electrode 144 provided on the second main surface 112 of the LTCC substrate 110 are It is formed by firing together with a low-temperature sintering ceramic material. On the other hand, electrodes such as the third electrode 143 provided on the planarizing layer 161 are formed after the firing.

At least one second electronic component 122 may be mounted on the second main surface 112 of the LTCC substrate 110, and electronic components other than the second electronic component 122 (for example, the third electronic component 123) are omitted. may

A sealing resin layer 153 that covers the second electronic component 122 and the third electronic component 123 is provided on the second main surface 112 of the LTCC substrate 110 .

Furthermore, the LTCC substrate 110 has a plurality of ground electrodes 154 drawn out from the inside of the LTCC substrate 110 to the side surface of the LTCC substrate 110 , and each ground electrode 154 is a metal conductor on the side surface of the electronic component module 100 . It is connected with layer 105 .

FIG. 2 is a cross-sectional view schematically showing an example of Cu pillar bumps included in the electronic component of the present invention (first embodiment).
As shown in FIG. 2, the first electronic component 121 includes a pad electrode 31 formed of gold or the like on the semiconductor 30, a passivation film 32 covering the semiconductor 30 except for the pad electrode formation portion, and a passivation film 32 except for the pad electrode formation portion. A resin layer 33 covering the passivation film 32 and a Cu pillar bump 131 connected to the pad electrode 31 are provided. The resin layer 33 is made of, for example, a thermosetting resin such as benzocyclobutene (BCB), and has a thickness T1 of, for example, 5 μm.

The Cu pillar bump 131 is a bump having a pillar-shaped copper pillar (copper post). For example, as shown in FIG. and a solder cap 36 connected to one end surface of the copper post 35 . The barrier/seed layer 34 has a structure in which a barrier metal layer (for example, TiW with a thickness of 320 nm) and a seed layer (for example, copper with a thickness of 400 nm) are laminated in this order by, for example, sputtering. The copper post 35 is, for example, a cylindrical conductor made of copper, and has a diameter D of 75 μm and a height T2 of 40 μm, for example. The solder cap 36 is formed of an alloy such as Sn-2.5% Ag by electrolytic plating, for example, and has a thickness T3 of 30 μm, for example.

The second electronic component 122 also has Cu pillar bumps 132 similar to the Cu pillar bumps 131 of the first electronic component 121 .

As described above, the electronic component module 100 includes the planarization layer 161 covering the second main surface 112 of the LTCC substrate 110 on which the plurality of second electrodes 142 are provided. is large, the surface of the planarizing layer 161 can be planarized, and the plurality of third electrodes 143 for mounting the second electronic component 122 can be formed on the planar surface. Therefore, even in the second electronic component 122 having a plurality of Cu pillar bumps 132 (external terminals), each Cu pillar bump 132 (external terminal) is connected to the second electrode 142 of the LTCC substrate 110 via the corresponding third electrode 143. It is possible to reliably connect to the That is, it is possible to suppress the occurrence of mounting defects such as open defects.

On the other hand, the first electronic component 121 is directly connected to the plurality of first electrodes 141 provided on the first main surface 111 of the LTCC substrate 110. In general, an inorganic material substrate such as an LTCC substrate has at least one main surface. Since it is possible to make it flat, even in the case of the first electronic component 121 having a plurality of Cu pillar bumps 131 (external terminals), each Cu pillar bump 131 (external terminal) is placed against the first electrode 141 of the LTCC substrate 110. It is possible to connect reliably by

In this way, the difference between the maximum and minimum heights of the plurality of second electrodes 142 with respect to the reference plane (for example, the mounting surface 101) parallel to the LTCC substrate 110 (hereafter referred to as the height variation of the second electrodes 142) ) is the difference between the maximum and minimum heights of the plurality of first electrodes 141 with respect to a reference plane (for example, the mounting surface 101) parallel to the LTCC substrate 110 (hereinafter referred to as the difference between the heights of the first electrodes 141). height variation).
Even in such a case, it is possible to reliably mount the first electronic component 121 and the second electronic component 122 on the LTCC substrate 110 .

Specifically, the height variation of the first electrode 141 is preferably 15 μm or less.
As a result, the first electronic component 121 having a plurality of Cu pillar bumps 131 (external terminals) can be more reliably connected to the first electrodes 141 of the LTCC substrate 110 . This is because it is empirically known that electronic components having external terminals such as Cu pillar bumps can be reliably mounted on the mounting pads if the difference between the maximum and minimum heights of the mounting pads is 15 μm or less.

On the other hand, the height variation of the second electrode 142 may exceed 15 μm.
Even in this case, since the planarization layer 161 is provided on the second main surface 112 , the second electronic component 122 having the plurality of Cu pillar bumps 132 (external terminals) is placed on the planarization layer 161 . It is possible to reliably connect to the second electrode 142 of the LTCC substrate 110 via the three electrodes 143 .

Here, the "height of the electrode with respect to the reference plane" means the shortest distance between the reference plane and the highest point of the electrode, and can be measured with a laser microscope, for example. Also, the “reference plane” may be a plane parallel to the LTCC substrate 110 .
Further, the height variation of the second electrodes 142 is measured for each electrode group for each second electronic component 122 .
Similarly, when a plurality of first electronic components 121 are mounted, the height variation of the first electrodes 141 is measured for each electrode group for each first electronic component 121 .

Variation in height of the first electrode 141 is preferably as small as possible, and the lower limit is not particularly limited. .

Although the upper limit of the height variation of the second electrode 142 is not particularly limited, it may be 50 μm or less, for example.

The rewiring layer (planarization layer 161, etc.) may be provided on either main surface side of the LTCC substrate 110, but should be provided on the second main surface 112 opposite to the mounting surface 101 as described above. is preferred. That is, electronic component module 100 preferably has mounting surface 101 on which input/output electrodes 104 are provided on first main surface 111 side of LTCC substrate 110 .

As shown in Figure 1, the IC and other parts were solder-mounted on the LTCC substrate on which the rewiring layer was formed, and when the mounting state was checked after reflow, it was confirmed that there was no conduction failure.

FIG. 3 shows the unevenness of the LTCC substrate used for this evaluation.
FIG. 3 is an SEM photograph showing a cross section of the LTCC substrate used in the evaluation test.
As shown in FIG. 3, the LTCC substrate used in the evaluation test has a flat lower surface corresponding to the first main surface 111 (see the lower dashed line), while an upper surface corresponding to the second main surface 112 is flat. It was confirmed that there was unevenness and it was not in a flat state (see the upper dashed line).

Electronic component module 100 is manufactured, for example, by the following method.
4 to 12 are cross-sectional views schematically showing an example of the electronic component module of the present invention (first embodiment) in the manufacturing process. FIG. 4 shows the mounting process of the first electronic component, and FIG. shows the first resin sealing step, FIG. 6 shows the sealing resin layer grinding step, FIG. 7 shows the planarizing layer forming step, and FIG. 9 shows the via and electrode forming process, FIG. 10 shows the mounting process of the second electronic component and the third electronic component, FIG. 11 shows the second resin sealing process, and FIG. 12 indicates a step of forming a metal conductor layer.
Although an aggregate substrate made up of a plurality of LTCC substrates will be described below, for the sake of convenience, individualized LTCC substrates are shown as an aggregate substrate in FIGS.

First, as shown in FIG. 4, a plurality of Cu electrodes are formed as external terminals on a first main surface 171 (corresponding to the first main surface 111 of the LTCC substrate 110), which is a flat surface of an aggregate substrate 170 composed of a plurality of LTCC substrates. A first electronic component 121 having pillar bumps 131 is mounted and reflowed. For example, a Cu (copper) pin is formed as the input/output electrode 104 on the input/output electrode 151 .

Next, as shown in FIG. 5, a sealing resin layer 152 is formed on the first main surface 171 of the collective board 170 so as to cover the first electronic components 121 and the input/output electrodes 104 .
Specifically, for example, a sheet-like sealing resin in a semi-cured state (for example, a sheet made of thermosetting resin such as epoxy resin) is placed on the first main surface 171, and then the sealing resin is used for molding. Heat while pressing with a plate. As a result, the sealing resin fluidizes and fills spaces such as gaps between the first electronic component 121 and the collective substrate 170, and then changes to a cured state.

Next, as shown in FIG. 6, the sealing resin layer 152 is ground to a predetermined thickness to expose the top surface of the first electronic component 121 and one end surface of the input/output electrode 104 . At this time, the top surface portion of the first electronic component 121 may be shaved to thin the first electronic component 121 .

Next, as shown in FIG. 7, a planarization layer 161 is formed on the second main surface 172 (corresponding to the second main surface 112 of the LTCC substrate 110), which is the uneven surface of the collective substrate 170. Next, as shown in FIG. As a result, the planarization layer 161 that covers the second electrode 142 and the fourth electrode 144 of the collective substrate 170 and has a flat surface is formed.
Specifically, for example, after placing a semi-cured sheet-like flattening layer resin (for example, a sheet made of a thermosetting resin such as epoxy resin) on the second main surface 172, The resin is heated while being pressed with a molding plate. As a result, the flattening layer resin is fluidized to fill the unevenness of the second main surface 172, and then changes to a cured state.
A non-hardened liquid flattening layer resin (for example, a thermosetting resin material such as epoxy resin) is applied on the second main surface 172 by printing, dispenser, spin coating, or the like, and leveling is adjusted to flatten the surface. After curing, it may be cured by heating with hot air or the like.

The thickness of the flattening layer 161 is not particularly limited as long as it can cover the second electrode 142 and the like and have a flat surface. For example, the thickness may be greater than 15 μm and capable of absorbing height variations of the second electrode 142 of 50 μm or less. Also, the planarization layer 161 may have a thickness of at least 5 μm at the highest point of the second electrode 142 where the height is at its maximum.

The planarizing layer resin may contain fillers such as alumina, silica, silicon nitride, and aluminum hydroxide.
The average particle diameter of the filler contained in the planarizing layer resin may be, for example, 0.5 μm or more and less than 5 μm, 1 μm or more and 3 μm or less, or 1.5 μm or more and 2 μm or more. .5 μm or less, or 2 μm.
Further, the content of the filler contained in the flattening layer resin may be, for example, 20% by weight or more and 60% by weight or less, or 30% by weight or more, based on the total amount of the flattening layer resin. It may be 50% by weight or less, 35% by weight or more and 45% by weight or less, or 40% by weight.
The average particle size of the filler can generally be measured using a laser diffraction particle size distribution analyzer.

The Young's modulus of the flattening layer resin at 25° C. may be, for example, 2 GPa or more and 20 GPa or less.
The Young's modulus can generally be measured by a viscoelasticity measurement method.

Next, as shown in FIG. 8, via holes are formed in the planarization layer 161 by CO ₂ laser or photolithography, and then desmeared to remove resin residue.

Next, as shown in FIG. 9 , vias 162 and 163 are formed in the via holes of the planarization layer 161 and the third electrode 143 and the fifth electrode 145 are formed on the planarization layer 161 .
Specifically, for example, first, a metal film (plating power supply film) is formed on the surface of the planarizing layer 161 by sputtering, and then a plated film is formed in the via holes and on the surface of the planarizing layer 161 by electroplating. do. After that, the plating film is patterned by photolithography to form the third electrode 143 and the fifth electrode 145 .
Note that the vias 162 and 163 may be formed from a conductive paste.

Next, as shown in FIG. 10, a second electronic component 122 having a plurality of Cu pillar bumps 132 as external terminals and other electronic components such as a third electronic component 123 are mounted on the surface on the planarization layer 161 side, reflow.

Next, as shown in FIG. 11, a sealing resin layer 153 is formed on the surface of the flattening layer 161 so as to cover the second electronic component 122 and other electronic components.
The sealing resin layer 153 can be formed in the same manner as the sealing resin layer 152 . That is, for example, after placing a semi-cured sheet-like sealing resin (for example, a sheet made of thermosetting resin such as epoxy resin) on the surface of the flattening layer 161, the sealing resin is placed on the molding plate. Heat while pressing with As a result, the sealing resin is fluidized and filled in the gap between the second electronic component 122 and the planarization layer 161, and then changed to a cured state.

The sealing resin for the sealing resin layers 152 and 153 may contain fillers such as alumina, silica, silicon nitride, aluminum hydroxide, barium titanate, and titania.
The average particle size of the filler contained in the sealing resin for the sealing resin layers 152 and 153 may be, for example, 5 μm or more and 15 μm or less, 7 μm or more and 13 μm or less, or 9 μm. Above, it may be 11 μm or less, or may be 10 μm.
Also, the content of the filler contained in the sealing resin for the sealing resin layers 152 and 153 may be, for example, 70% by weight or more and 98% by weight or less with respect to the total amount of the sealing resin.
The filler content in the flattening layer resin may be less than the filler content in the sealing resins for the sealing resin layers 152 and 153 .

The Young's modulus at 25° C. of the sealing resin for the sealing resin layers 152 and 153 may be, for example, 10 GPa or more and 30 GPa or less.
Thus, the Young's modulus of the resin for the planarization layer at 25° C. may be smaller than the Young's modulus of the sealing resin for the sealing resin layers 152 and 153 at 25° C.

The sealing resins for the sealing resin layers 152 and 153 may have different materials and/or properties, or may be the same.
The sealing resins for the sealing resin layers 152 and 153 may have the same material and characteristics as the flattening layer resin, but are preferably different.

Next, each LTCC substrate 110 is cut out by cutting the collective substrate 170 at a predetermined position with a dicer or the like to individualize it.

Then, as shown in FIG. 12, a metal conductor layer 105 is formed on the surfaces other than the mounting surface 101 .
For example, the LTCC substrate 110 is placed on a tray for sputtering with the mounting surface 101 facing downward. At this time, paste or tape may be attached to the mounting surface 101 in order to prevent the sputtered film from wrapping around. Then, by sputtering, on the surfaces other than the mounting surface 101, for example, a stainless steel thin film (for example, 0.15 μm thick) is formed as an adhesion layer, and then, for example, a copper thin film (for example, 2 μm thick) is sequentially formed as a conductive layer. A conductor layer 105 is formed.

Note that the metal conductor layer 105 may have a multi-layer structure including an adhesion layer, a corrosion-resistant layer, etc. in addition to the conductive layer as described above, or may have a single-layer structure consisting of only the conductive layer.

Thus, the electronic component module 100 according to the first embodiment is manufactured.

[Second embodiment]
In the first embodiment, the ground electrode was pulled out from between the ceramics constituting the insulating layers of the LTCC substrate to the side surface of the LTCC substrate and connected to the metal conductor layer. However, since the brittleness and ductility of the metal conductors that make up the ground electrode and the ceramics differ greatly, in this structure, cracks may occur in the ceramics and the metal conductors may stretch during the process of dividing the aggregate substrate. There is a risk that burrs will occur in the ceramic or the ground electrode, and that the spatter will not flow well when forming the metal conductor layer, resulting in poor adhesion between the ground electrode and the metal conductor layer.

Therefore, in the electronic component module according to the second embodiment, the ground electrode is drawn out on the second main surface of the LTCC substrate, and further, between the planarization layer as the rewiring layer and the sealing resin layer, or between the LTCC substrate The main feature is that the space between the second main surface and the flattened layer as the rewiring layer is pulled out to the side surface of the electronic component module and connected to the metal conductor layer. As a result, cracking of the ceramic and elongation of the metal conductor can be suppressed, and deterioration of adhesion and coverage of the metal conductor layer due to burrs of the ceramic and metal conductor can be suppressed.
This feature will be mainly described in the second embodiment.

FIG. 13 is a cross-sectional view schematically showing an example of the electronic component module of the present invention (second embodiment).
An electronic component module 200 shown in FIG. 13 includes a metal conductor layer 105 forming surfaces other than the mounting surface 101, ie, a top surface 102 and four side surfaces 103, as in the first embodiment.
The electronic component module 200 also includes an LTCC substrate 210 having a first main surface 211 on the mounting surface 101 side and a second main surface 212 on the top surface 102 side.

On the second main surface 212 of the LTCC substrate 210, as in the first embodiment, a plurality of second electrodes 142, a planarizing layer 161, a plurality of third electrodes 143, a plurality of fourth electrodes 144, A fifth electrode 145 and a sealing resin layer 153 are provided, and the second electronic component 122 and the third electronic component 123 are mounted.

On the other hand, the LTCC substrate 210 has a ground electrode 254 provided on the second principal surface 212 . Ground electrode 254 is drawn out from internal electrode 255 of LTCC substrate 210 onto second main surface 212 via via 257 .

The electronic component module 200 further includes a ground wiring 256 provided on the planarization layer 161 and connected to the ground electrode 254 . The ground wiring 256 is connected to the ground electrode 254 through vias 264 provided in the planarization layer 161 .

The ground electrode 254, via 257 and internal electrode 255 are formed by firing together with a low-temperature sintered ceramic material. On the other hand, the ground wiring 256 and via 264 are formed after the firing.

The ground wiring 256 is extended between the planarizing layer 161 and the sealing resin layer 153 and connected to the metal conductor layer 105 .
Here, the material forming the planarizing layer 161 and the sealing resin layer 153 does not usually have brittleness like ceramics, but has ductility like the metal conductor forming the ground wiring 256 . Therefore, compared to the structure in which the ground electrode is pulled out from between the ceramics to the side surface of the LTCC substrate as in the first embodiment, cracking of the ceramic and elongation of the metal conductor can be suppressed in the process of dividing the collective substrate. Deterioration of the adhesion and coverage of the metal conductor layer 105 due to burrs can be suppressed.

The ground wiring 256 extends between the flattening layer 161 and the sealing resin layer 153 from directly above the ground electrode 254 to the side surface of the electronic component module 200, for example, in a straight line. It is connected to layer 105 .

Other differences between this embodiment and the first embodiment will be described below.

A fourth electronic component 224 having a pair of external electrodes 234 instead of Cu pillar bumps (external terminals) is mounted on the first main surface 211 of the LTCC substrate 210 .

More specifically, a plurality of sixth electrodes 246 are provided on the first major surface 211 . The sixth electrodes 246 are provided in one-to-one correspondence with the pair of external electrodes 234 of the fourth electronic component 224 , and each external electrode 234 is connected to the corresponding sixth electrode 246 to form the fourth electrode 246 . An electronic component 224 is mounted on the first major surface 211 . Each external electrode 234 is connected to the corresponding sixth electrode 246 via solder 235, for example. Although the fourth electronic component 224 is not particularly limited, here, for example, a chip capacitor 224a is mounted, and the chip capacitor as the third electronic component 123 is not mounted on the second main surface 212 accordingly.
Each sixth electrode 246 is connected to corresponding wiring (not shown) of the LTCC substrate 210 .

In addition, a planarization layer 281 is provided on the first main surface 211 side of the LTCC substrate 210, and the planarization layer 281 covers the first electronic component 121, the fourth electronic component 224, and the sealing resin layer 152. are doing.

Further, the electronic component module 200 includes columnar electrodes 258 connected to the input/output electrodes 151 provided on the first main surface 211 of the LTCC substrate 210, and the columnar electrodes 258 provided on the planarization layer 281. and connected input/output electrodes 204 . Each input/output electrode 204 is connected to the corresponding columnar electrode 258 through vias 282 provided in the planarization layer 281 .

According to this structure, since the planarization layer 281 covers the electronic components mounted on the first main surface 211, the electronic components mounted on the first main surface 211, especially ICs, are prevented from being damaged by impact. can do.
In general, the area of the input/output electrode is determined according to the size of the mounting pad of the component (for example, substrate) on which it is mounted, and cannot be reduced at will. The arrangement area of the columnar electrode 258 and the via 282 can be reduced while securing the area required for the input/output electrode 204 . Therefore, extra space can be secured on the first main surface 211, and other electronic components such as the fourth electronic component 224 can be further arranged in addition to the first electronic component 121, as described above.

In a plurality of structural products (corresponding to the electronic component module 200 at the stage before forming the metal conductor layer 105, see FIG. 13) in which the ground wiring is pulled out from between the flattening layer and the sealing resin layer to the side surface, A 0.15 μm-thick stainless thin film and a 2 μm-thick copper thin film were formed in this order by sputtering on the surface other than the mounting surface to form a metal conductor layer, and the strength and coverage of the metal conductor layer were checked. Specifically, an adhesive tape was attached to the formed metal conductor layer and then removed, and whether or not the metal conductor layer was peeled off together with the adhesive tape was evaluated, and the structural product after the adhesive tape was peeled off was observed. As a result, it was confirmed that there was no peeling of the metal conductor layer in all the workpieces, and that the metal conductor layer could be covered.

Here, a modified example of this embodiment will be described. In this example, the ground electrode is extended to the side surface of the electronic component module between the second main surface of the LTCC substrate and the planarization layer as the rewiring layer, and is connected to the metal conductor layer.

FIG. 14 is a cross-sectional view schematically showing another example of the electronic component module of the present invention (second embodiment).
An electronic component module 300 shown in FIG. 14 includes an LTCC substrate 310 having a first main surface 311 on the mounting surface 101 side and a second main surface 312 on the top surface 102 side.

LTCC substrate 310 is substantially the same as LTCC substrate 310 shown in FIG. is the same as

The ground electrode 354 is drawn out from the internal electrode 255 of the LTCC substrate 310 onto the second main surface 312 via the via 257 .

The ground electrode 354 is extended between the LTCC substrate 310 and the planarization layer 161 and connected to the metal conductor layer 105 .
As a result, cracking of the ceramic and elongation of the metal conductor can be suppressed in the process of dividing the collective substrate, compared to the structure in which the ground electrode is pulled out from between the ceramics to the side surface of the LTCC substrate as in the first embodiment. Therefore, it is possible to suppress deterioration of adhesion and coverage of the metal conductor layer 105 due to burrs of the ceramic or metal conductor.

13 is more preferable than the electronic component module 300 shown in FIG. 14 from the viewpoint of improving the adhesion and coverage of the metal conductor layer 105 .
On the other hand, in the electronic component module 300 shown in FIG. 14, since it is not necessary to provide the ground wiring on the planarization layer 161, a wider area for mounting the electronic components on the planarization layer 161 is secured accordingly. be able to.

The ground electrode 354 extends between the LTCC substrate 310 and the planarization layer 161 from directly above the internal electrode 255 to the side surface of the electronic component module 300, for example, in a straight line. It is connected to the.

Electronic component module 200 is manufactured, for example, by the following method.
15 to 23 are cross-sectional views schematically showing an example of the electronic component module of the present invention (second embodiment) in the manufacturing process, FIG. 15 shows the mounting process of the first electronic component, and FIG. shows the first resin sealing process, FIG. 17 shows the sealing resin layer grinding process, FIG. 18 shows the planarizing layer forming process, and FIG. 19 shows the planarizing layer via hole forming process. 20 shows the via and electrode forming process, FIG. 21 shows the mounting process of the second electronic component and the third electronic component, FIG. 22 shows the second resin sealing process, and FIG. 23 indicates a step of forming a metal conductor layer.
Although an aggregate substrate made up of a plurality of LTCC substrates will be described below, for the sake of convenience, individualized LTCC substrates are shown as an aggregate substrate in FIGS.

First, as shown in FIG. 15, a plurality of Cu electrodes are formed as external terminals on a first main surface 271 (corresponding to the first main surface 211 of the LTCC substrate 210), which is a flat surface of an aggregate substrate 270 composed of a plurality of LTCC substrates. The first electronic component 121 having the pillar bumps 131 and the fourth electronic component 224 are mounted and reflowed. For example, a Cu (copper) pin is formed as the columnar electrode 258 on the input/output electrode 151 .

Next, as shown in FIG. 16, the first electronic component 121, the fourth electronic component 224, and the columnar electrodes 258 are covered with the first electronic component 121, the fourth electronic component 224, and the columnar electrode 258 in the same manner as described in the first embodiment. A sealing resin layer 152 is formed on the main surface 271 .

Next, as shown in FIG. 17, the sealing resin layer 152 is ground to a predetermined thickness to expose one end surface of the columnar electrode 258 . At this time, the top surface of the first electronic component 121 and/or the top surface of the fourth electronic component 224 may also be exposed. Further, the top surface portion of the first electronic component 121 may be shaved to thin the first electronic component 121 .

Next, as shown in FIG. 18, a planarizing layer 281 is formed on the first main surface 271 of the collective substrate 270, and a second main surface 272 (the second main surface of the LTCC substrate 210), which is an uneven surface of the collective substrate 270, is formed. A planarization layer 161 is formed on the surface (corresponding to the surface 212). As a result, a flattened layer 281 that covers the first electronic component 121 and the like and has a flat surface is formed. Further, a flattening layer 161 having a flat surface is formed to cover the second electrode 142, the fourth electrode 144 and the ground electrode 254 of the collective substrate 270. As shown in FIG.
Specifically, for example, a semi-cured sheet-like flattening layer resin (for example, a sheet made of thermosetting resin such as epoxy resin) is applied on the first principal surface 271 and the second principal surface 272 . After each placement, the resin for the flattening layer is heated while being pressed with a molding plate. As a result, the flattening layer resin on the first main surface 271 side is fluidized and then changed to a cured state. Further, the planarizing layer resin on the second main surface 272 side is fluidized to fill the unevenness of the second main surface 272, and then changes to a cured state.
A non-cured liquid planarization layer resin (for example, a thermosetting resin material such as epoxy resin) is applied to the first main surface 271 by printing, dispenser, spin coating, or the like, and leveling is adjusted to achieve planarization. After curing, it may be cured by heating with hot air or the like.
Similarly, on the second main surface 272, an uncured liquid planarizing layer resin (for example, a thermosetting resin material such as epoxy resin) is applied by printing, dispenser, spin coating, or the like, and leveling is adjusted. It may be cured by heating with hot air or the like after flattening.

As the planarizing layer resin for the planarizing layer 281, the planarizing layer resin for the planarizing layer 161 described in the first embodiment can be used.
The planarizing layer resins for the planarizing layers 161 and 281 may have different materials and/or characteristics, or may be the same.

Next, as shown in FIG. 19, via holes are formed in the planarization layers 161 and 281 by CO ₂ laser or photolithography, and then desmeared to remove resin residues.

Next, as shown in FIG. 20 , vias 282 are formed in the via holes of the planarization layer 281 and the input/output electrodes 204 are formed on the planarization layer 281 . Also, via holes 162 , 163 and 264 are formed in the via holes of the planarization layer 161 , and the third electrode 143 , the fifth electrode 145 and the ground wiring 256 are formed on the planarization layer 161 .
Specifically, for example, first, metal films (plating power supply films) are formed on the surfaces of the planarizing layers 161 and 281 by sputtering, and then electroplating is performed in the via holes of the planarizing layers 161 and 281 and in the respective via holes. A plating film is formed on the surface. Thereafter, the plated film is patterned by photolithography to form the input/output electrodes 204, and the third electrode 143, the fifth electrode 145, and the ground wiring 256 are formed.
Note that vias 282, 162, 163 and 264 may be formed from a conductive paste.

Next, as shown in FIG. 21, a second electronic component 122 having a plurality of Cu pillar bumps 132 as external terminals and other electronic components such as a third electronic component 123 are mounted on the surface on the planarization layer 161 side, reflow.

Next, as shown in FIG. 22, sealing resin is applied to the surface of the flattening layer 161 side so as to cover the second electronic component 122 and other electronic components in the same manner as described in the first embodiment. Layer 153 is formed.

Next, each LTCC substrate 210 is cut out by cutting the collective substrate 270 at a predetermined position with a dicer or the like to individualize it.

Then, as shown in FIG. 23, the metal conductor layer 105 is formed on the surface of the LTCC substrate 210 excluding the mounting surface 101 in the same manner as in the first embodiment.

Thus, the electronic component module 200 according to the second embodiment is manufactured.

Note that the electronic component module 300 is manufactured by the same method as the electronic component module 200, except that the ground wiring 256 and the via 264 for the ground wiring 256 are not formed.

Further, in the above embodiment, the case where the entire surface except for the mounting surface 101 is composed of the metal conductor layer 105 has been described, but the metal conductor layer included in the electronic component module of the present invention constitutes at least one side surface of the electronic component module. It's fine if you do. That is, in the second embodiment, at least the side surface 103 from which the ground wiring 256 or the ground electrode 354 is drawn out should be made of the metal conductor layer 105 . However, from the viewpoint of shielding properties, etc., it is preferable that the metal conductor layer included in the electronic component module of the present invention forms substantially the entire surface of the electronic component module except for the mounting surface.

In addition, in the above-described embodiments, the LTCC substrate is used as the inorganic material substrate, but the inorganic material substrate included in the electronic component module of the present invention is a circuit that uses an inorganic material (preferably ceramic) as an insulating material. There is no particular limitation as long as it is a substrate (preferably a multilayer substrate).

Further, in the above embodiment, when the first electronic component 121 having a mounting surface provided with a plurality of Cu pillar bumps 131 and the second electronic component 122 having a mounting surface provided with a plurality of Cu pillar bumps 132 are mounted, However, the first electronic component and the second electronic component included in the electronic component module of the present invention are not particularly limited as long as they are electronic components having a mounting surface provided with a plurality of external terminals. It may be an electronic component (preferably an IC) having a Land Grid Array (Land Grid Array) structure or an electronic component (preferably an IC) having a BGA (Ball Grid Array) structure.
In addition, in the case of an electronic component having an LGA structure, each external terminal (land) may be connected to the inorganic material substrate with solder.
In either case, three or more external terminals are normally arranged regularly at equal pitches only on the mounting surface. For example, they may be arranged on the mounting surface in a ring shape such as a rectangular shape, or may be arranged in a lattice shape (matrix shape) on the mounting surface.

[Comparative form]
FIG. 24 is a cross-sectional view schematically showing an example of an electronic component module according to a comparative embodiment;
The electronic component module 400 shown in FIG. 24 is substantially the same as the electronic component module 100 according to the first embodiment shown in FIG. 1 except that the planarization layer 161 and the plurality of third electrodes 143 are not provided. It is.

That is, each second electronic component 122 having a plurality of Cu pillar bumps 132 as external terminals is directly connected to the corresponding second electrode 142 .
Each ground electrode 154 drawn out from the inside of the LTCC substrate 110 to the side surface is connected to the metal conductor layer 105 on the side surface of the electronic component module 400 .

As shown in FIG. 24, when ICs and other parts were solder-mounted on an LTCC substrate that did not have a rewiring layer, and the mounting state was checked after reflow, open defects occurred frequently.

In addition, a plurality of structural products (corresponding to the electronic component module 400 at the stage before forming the metal conductor layer 105, see FIG. 24) in which the ground electrodes are pulled out from between the ceramics of the LTCC substrate to the side surface, except for the mounting surface, are provided. A 0.15 μm-thick stainless thin film and a 2 μm-thick copper thin film were formed in this order on the other surface by sputtering to form a metal conductor layer, and the strength and coverage of the metal conductor layer were checked. Specifically, an adhesive tape was attached to the formed metal conductor layer and then removed, and whether or not the metal conductor layer was peeled off together with the adhesive tape was evaluated, and the structural product after the adhesive tape was peeled off was observed. As a result, peeling of the metal conductor layer occurred at the lead-out portion of the ground electrode from the LTCC substrate, and it was confirmed that some workpieces were not covered with the metal conductor layer.

100, 200, 300 electronic component module 101 electronic component module mounting surface 102 electronic component module top surface 103 electronic component module side surfaces 104, 204 input/output electrodes 105 metal conductor layers 110, 210, 310 low temperature fired ceramic substrates 111, 211 , 311 first main surface 112, 212, 312 of low-temperature co-fired ceramic substrate second main surface 121 of low-temperature co-fired ceramic substrate first electronic component 121a SOI
122 second electronic component 122a HBT IC
122b SAW filter 122c GaAs IC
123 Third electronic components 123a, 224a Chip capacitor 123b Chip inductors 131, 132 Cu pillar bumps 133, 234 External electrodes 135, 235 Solder 141 First electrode 142 Second electrode 143 Third electrode 144 Fourth electrode 145 Fifth electrode 151 Input/ output electrodes 152, 153 sealing resin layers 154, 254, 354 ground electrodes 161, 281 planarization layers 162, 163, 257, 264, 282 vias 170, 270 aggregate substrates 171, 271 first major surfaces 172, 272 of aggregate substrates Second main surface 224 of collective board Fourth electronic component 246 Sixth electrode 255 Internal electrode 256 Ground wiring 258 Columnar electrode

Claims (10)

1. An electronic component module in which components are mounted on both sides of a substrate,
   an inorganic material substrate having a first main surface provided with a plurality of first electrodes and a second main surface provided with a plurality of second electrodes;
   a first electronic component having a mounting surface provided with a plurality of external terminals connected to the plurality of first electrodes;
   a planarization layer covering the second main surface;
   a plurality of third electrodes provided on the planarization layer and connected to the plurality of second electrodes;
   a second electronic component having a mounting surface provided with a plurality of external terminals connected to the plurality of third electrodes;
   An electronic component module comprising:
2. The difference between the maximum and minimum heights of the plurality of second electrodes relative to a reference plane parallel to the inorganic material substrate is the maximum height of the plurality of first electrodes relative to a reference plane parallel to the inorganic material substrate. 2. The electronic component module according to claim 1, wherein the difference is greater than the difference between the value and the minimum value.
3. The electronic component module according to claim 2, wherein the difference between the maximum height and the minimum height of the plurality of second electrodes with respect to a reference plane parallel to the inorganic material substrate exceeds 15 µm.
4. 4. The electronic component module according to claim 2, wherein the difference between the maximum and minimum heights of the plurality of first electrodes with respect to a reference plane parallel to the inorganic material substrate is 15 μm or less.
5. The electronic component module according to any one of claims 1 to 4, which has a mounting surface on which input/output electrodes are provided on the first main surface side.
6. a sealing resin layer covering the second electronic component;
   a metal conductor layer forming at least a side surface of the electronic component module;
   a ground electrode provided on the second main surface;
   a ground wiring provided on the planarization layer and connected to the ground electrode;
   6. The electronic component module according to claim 1, wherein the ground wiring extends between the flattening layer and the sealing resin layer and is connected to the metal conductor layer.
7. a mounting surface provided with input/output electrodes;
   a metal conductor layer forming at least a side surface of the electronic component module;
   A ground electrode provided on the second main surface,
   6. The electronic component module according to claim 1, wherein the ground electrode extends between the inorganic material substrate and the planarization layer and is connected to the metal conductor layer.
8. The electronic component module according to any one of claims 1 to 7, wherein the inorganic material substrate is a low temperature fired ceramic substrate.
9. The electronic component module according to any one of claims 1 to 8, wherein the first electronic component is an IC.
10. The electronic component module according to any one of claims 1 to 9, wherein the second electronic component is an IC.

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