WO2023020586A1 - 故障诊断电路、方法、装置及计算机可读存储介质 - Google Patents

故障诊断电路、方法、装置及计算机可读存储介质 Download PDF

Info

Publication number
WO2023020586A1
WO2023020586A1 PCT/CN2022/113373 CN2022113373W WO2023020586A1 WO 2023020586 A1 WO2023020586 A1 WO 2023020586A1 CN 2022113373 W CN2022113373 W CN 2022113373W WO 2023020586 A1 WO2023020586 A1 WO 2023020586A1
Authority
WO
WIPO (PCT)
Prior art keywords
verification
circuit
fault diagnosis
safety protection
result signal
Prior art date
Application number
PCT/CN2022/113373
Other languages
English (en)
French (fr)
Inventor
吴征
李文星
周奕
李晶
刘擎宇
Original Assignee
地平线(上海)人工智能技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 地平线(上海)人工智能技术有限公司 filed Critical 地平线(上海)人工智能技术有限公司
Priority to JP2023542630A priority Critical patent/JP2024503675A/ja
Priority to EP22857895.1A priority patent/EP4270198A1/en
Priority to US18/261,435 priority patent/US20240069098A1/en
Publication of WO2023020586A1 publication Critical patent/WO2023020586A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3187—Built-in tests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S10/00—Systems supporting electrical power generation, transmission or distribution
    • Y04S10/50—Systems or methods supporting the power network operation or management, involving a certain degree of interaction with the load-side end user applications
    • Y04S10/52—Outage or fault management, e.g. fault detection or location

Definitions

  • the present disclosure relates to the technical field of fault diagnosis, and in particular to a fault diagnosis circuit, method, device and computer-readable storage medium.
  • Embodiments of the present disclosure provide a fault diagnosis circuit, method, device and computer-readable storage medium.
  • a fault diagnosis circuit including: a safety protection circuit and a diagnosis module;
  • the safety protection circuit is electrically connected to the protected circuit, and is used to perform a verification operation on the stored data in the protected circuit to obtain first verification data, and second verification data corresponding to the stored data performing error injection on the data, and generating a first verification result signal based on the first verification data and the second verification data after the error injection;
  • the diagnosis module is electrically connected to the safety protection circuit, and the diagnosis module is used for performing fault diagnosis on the safety protection circuit based on the first verification result signal.
  • a fault diagnosis method which is applied to the above fault diagnosis circuit, and the fault diagnosis method includes:
  • Fault diagnosis is performed on the safety protection circuit in the fault diagnosis circuit based on the first verification result signal.
  • a fault diagnosis device which is applied to the above fault diagnosis circuit, and the fault diagnosis device includes:
  • the first processing module is used to perform a verification operation on the stored data in the protected circuit to obtain the first verification data
  • a second processing module configured to perform error injection on the second verification data corresponding to the stored data
  • a first generation module configured to generate a first verification result based on the first verification data obtained by the first processing module and the error-injected second verification data obtained by the second processing module Signal;
  • a third processing module configured to perform fault diagnosis on the safety protection circuit in the fault diagnosis circuit based on the first verification result signal generated by the first generation module.
  • a computer-readable storage medium stores a computer program, and the computer program is used to execute the above fault diagnosis method.
  • an electronic device including:
  • the processor is configured to read the executable instructions from the memory, and execute the instructions to implement the above fault diagnosis method.
  • the safety protection circuit can generate a first verification result signal by obtaining verification data and combining error injection , and provide the generated first verification result signal to the diagnosis module, and the diagnosis module can diagnose the fault of the safety protection circuit accordingly. Therefore, the embodiment of the present disclosure can realize the fault diagnosis of the safety protection circuit through a simple hardware structure , so as to perform troubleshooting based on the diagnosis results, so as to ensure the normal operation of the chip.
  • FIG. 1 is a schematic diagram of a scene to which the present disclosure is applicable.
  • Fig. 2 is a schematic structural diagram of a fault diagnosis circuit provided by an exemplary embodiment of the present disclosure.
  • Fig. 3 is a schematic structural diagram of a safety protection circuit in a fault diagnosis circuit provided by an exemplary embodiment of the present disclosure.
  • Fig. 4 is a schematic structural diagram of a fault diagnosis circuit provided by another exemplary embodiment of the present disclosure.
  • Fig. 5 is a schematic structural diagram of a diagnosis module in a fault diagnosis circuit provided by an exemplary embodiment of the present disclosure.
  • Fig. 6 is a schematic flowchart of error injection in a fault diagnosis circuit provided by an exemplary embodiment of the present disclosure.
  • Fig. 7 is a schematic flowchart of a fault diagnosis method provided by an exemplary embodiment of the present disclosure.
  • Fig. 8 is a schematic flowchart of a fault diagnosis method provided by another exemplary embodiment of the present disclosure.
  • Fig. 9 is a schematic structural diagram of a fault diagnosis device provided by an exemplary embodiment of the present disclosure.
  • Fig. 10 is a schematic structural diagram of a fault diagnosis device provided by another exemplary embodiment of the present disclosure.
  • Fig. 11 is a structural diagram of an electronic device provided by an exemplary embodiment of the present disclosure.
  • plural may refer to two or more than two, and “at least one” may refer to one, two or more than two.
  • Embodiments of the present disclosure may be applied to electronic devices such as terminal devices, computer systems, servers, etc., which may operate with numerous other general purpose or special purpose computing system environments or configurations.
  • Examples of well-known terminal equipment, computing systems, environments and/or configurations suitable for use with electronic equipment such as terminal equipment, computer systems, servers, etc. include, but are not limited to: devices or systems, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, networked personal computers, small computer systems, Mainframe computer systems and distributed cloud computing technology environments including any of the above systems, etc.
  • the inventors found that due to the level requirements of functional safety, some circuits in the chip (which may be called protected circuits) need to have corresponding safety protection circuits, and the safety protection circuits can be protected through specific safety protection. mechanism to protect the protected circuit.
  • the chip may be a chip of a smart car, and the protected circuit may be a register.
  • the safety protection circuit itself may also have faults, which will affect the normal operation of the chip. In order to eliminate the faults of the safety protection circuit and ensure the normal operation of the chip, it is necessary to perform fault diagnosis on the safety protection circuit.
  • a fault diagnosis circuit provided by an embodiment of the present disclosure may be provided.
  • the fault diagnosis circuit may include a safety protection circuit 3 , and the safety protection circuit 3 may be electrically connected to the protected circuit 1 .
  • the fault diagnosis of the safety protection circuit 3 can be realized.
  • the fault diagnosis of the protected circuit 1 can also be realized through the operation of the fault diagnosis circuit.
  • logic gates such as NOT gates, OR gates, AND gates, and multiplexers (MUX).
  • Fig. 2 is a schematic structural diagram of a fault diagnosis circuit provided by an exemplary embodiment of the present disclosure. As shown in FIG. 2 , the fault diagnosis circuit includes: a safety protection circuit 3 and a diagnosis module 5 .
  • the safety protection circuit 3 is electrically connected to the protected circuit 1, and is used to perform a verification operation on the stored data in the protected circuit 1 to obtain the first verification data, and to perform an error on the second verification data corresponding to the stored data. Injecting, and generating a first verification result signal based on the first verification data and the second verification data after error injection;
  • the diagnosis module 5 is electrically connected with the safety protection circuit 3, and the diagnosis module 5 is used for performing fault diagnosis on the safety protection circuit 3 based on the first verification result signal.
  • the protected circuit 1 may be a circuit capable of storing data, such as a register.
  • the registers may be data registers or control registers.
  • the control register can be used to control the functional configuration of the entire chip, subsystems in the chip, or modules in the chip;
  • the data register can store the first-in-first-out (First Input First Output, FIFO) queue of data, and perform data caching wait.
  • the register width can be 4bit, 8bit, 16bit, 32bit, etc. Of course, the register width is not limited to this, and can be selected according to actual needs, and the embodiments of the present disclosure do not make any limitation on this.
  • the security protection circuit 3 can acquire the stored data in the protected circuit 1 .
  • the security protection circuit 3 may perform a verification operation on the stored data according to a preset verification method to obtain the first verification data.
  • the safety protection circuit 3 can use a cyclic redundancy check (Cyclic Redundancy Check, CRC) algorithm to perform CRC calculations on the stored data to obtain corresponding CRC values, and use the obtained CRC values as the first calibration value.
  • CRC Cyclic Redundancy Check
  • the safety protection circuit 3 can adopt a parity check algorithm to perform a parity check operation on the stored data to obtain a corresponding parity check value, and use the obtained parity check value as the first check data .
  • the security protection circuit 3 can also obtain the second verification data corresponding to the stored data.
  • the safety protection circuit 3 can be electrically connected with data buses such as Advanced Extensible Interface (Advanced eXtensible Interface, AXI), Advanced Peripheral Bus (Advanced Peripheral Bus, APB), and can be used for transmission on the data bus.
  • the protected circuit 1 can specifically acquire the data for storage from the data bus and store it, and the data stored by the protected circuit 1 can be regarded as stored data.
  • the security protection circuit 3 can obtain the second verification data corresponding to the stored data based on the data bus.
  • the security protection circuit 3 can obtain data for storage from the data bus, and perform a verification operation on the acquired data according to a preset verification method, and the obtained verification data can be used as the corresponding stored data the second verification data; or, in addition to transmitting the data for storage on the data bus, the verification data corresponding to the data for storage can also be transmitted, the verification data can be according to the preset verification method, for The data transmitted on the data bus for storage is obtained after performing a verification operation, and the verification data transmitted on the data bus can be used as the second verification data corresponding to the stored data.
  • the safety protection circuit 3 can perform error injection on the second verification data to introduce errors into the second verification data, so as to obtain the second verification data after error injection, so that based on the first The verification data and the second verification data after error injection generate a first verification result signal.
  • the security protection circuit 3 may compare the first verification data with the second verification data after error injection, and generate The first verification result signal, the first verification result signal may be a signal that can be used to determine whether the first verification data and the error-injected second verification data are the same.
  • the diagnosis module 5 can obtain the first verification result signal, so that the safety protection circuit 3 can be checked accordingly.
  • Fault diagnosis such as determining whether there is a fault in the safety protection circuit 3 .
  • the safety protection circuit 3 can generate a first verification result signal by acquiring verification data and combining with error injection, and provide the generated first verification result signal to the diagnosis module 5, the diagnostic module 5 can perform fault diagnosis on the safety protection circuit 3 accordingly, therefore, the embodiment of the present disclosure can realize the fault diagnosis of the safety protection circuit 3 through a simple hardware structure, so as to perform troubleshooting based on the diagnosis result, thereby Ensure the normal operation of the chip.
  • the safety protection circuit 3 is also used to generate a second verification result signal based on the first verification data and the second verification data; the diagnostic module 5 is also used to generate a second verification result signal based on the second verification result signal.
  • the protected circuit 1 performs fault diagnosis.
  • the security protection circuit 3 can also compare the first verification data with the second verification data, and generate the second verification data based on the comparison result of the first verification data and the second verification data.
  • the result signal, the second verification result signal may be a signal that can be used to determine whether the first verification data and the second verification data are the same.
  • the diagnosis module 5 can obtain the second verification result signal, so as to perform a check on the protected circuit 1 accordingly. Fault diagnosis, such as determining whether the protected circuit 1 is faulty.
  • the safety protection circuit 3 may include: a processing module 31, a calculation module 33 and a comparison module 35;
  • the comparison module 35 is electrically connected to the processing module 31, the calculation module 33, and the diagnosis module 5 in FIG. 2, respectively, and the calculation module 33 is also electrically connected to the protected circuit 1;
  • the calculation module 33 is used to perform a verification operation on the stored data to obtain the first verification data
  • the processing module 31 is configured to perform error injection on the second verification data
  • the comparison module 35 is configured to generate a third verification result signal based on a comparison result between the first verification data and the error-injected second verification data, and the first verification result signal is generated based on the third verification result signal;
  • the comparison module 35 is further configured to generate a fourth verification result signal based on the comparison result of the first verification data and the second verification data, and the second verification result signal is generated based on the fourth verification result signal.
  • the comparison module 35 may be a comparator.
  • the processing module 31 includes: a first NOT gate 311, a first multiplexer 313, and a memory 315;
  • the first multiplexer 313 is electrically connected to the memory 315, the memory 315 is also electrically connected to the first multiplexer 313 through the first NOT gate 311, and the first multiplexer 313 is also electrically connected to the data bus, The memory 315 is also electrically connected to the comparison module 35;
  • the first multiplexer 313 is used to output the second check data obtained based on the data bus, so that the memory 315 stores the second check data and outputs the second check data. test data to the comparison module 35;
  • the first multiplexer 313 is used to output the inversion result of the second verification data stored in the memory 315 by the first NOT gate 311, so that the memory 315 outputs the first
  • the inversion result of the second verification data is sent to the comparison module 35, and the inversion result of the second verification data is used as the second verification data after error injection.
  • the first NOT gate 311 may have a first port P1 and a second port P2
  • the first multiplexer 313 may have a third port P3, a fourth port P4, and a fifth port P5
  • the memory 315 may have a sixth Port P6 and seventh port P7
  • the comparison module 35 may have an eighth port P8, a ninth port P9 and a tenth port P10.
  • the first port P1 may be electrically connected to the seventh port P7
  • the second port P2 may be electrically connected to the third port P3
  • the fourth port P4 may be electrically connected to the data bus
  • the fifth port P5 may be electrically connected to the sixth port P6
  • the seventh port P7 can be electrically connected to the eighth port P8
  • the ninth port P9 can be electrically connected to the calculation module 33
  • the tenth port P10 can be electrically connected to the diagnosis module 5 .
  • first port P1 can be used as the input terminal of the first NOT gate 311
  • second port P2 can be used as the output terminal of the first NOT gate 311
  • third port P3 and the fourth port P4 can be used as the first multiple An input end of the multiplexer 313
  • the fifth port P5 can be used as the output end of the first multiplexer 313
  • the eighth port P8 and the ninth port P9 can be respectively used as an input end of the comparison module 35
  • the port P10 can serve as an output terminal of the comparison module 35 .
  • the fault diagnosis circuit may include two working modes, namely a first working mode and a second working mode.
  • first working mode the fault diagnosis of the protected circuit 1 can be carried out, and the first working mode can also be called the normal working mode; in the second working mode, the fault diagnosis of the safety protection circuit 3 can be carried out, and the second working mode Also known as the Fault Injection pattern.
  • the comparison module 35 can The first verification data from the calculation module 33 is obtained from the ninth port P9.
  • the first multiplexer 313 can receive the second check data from the fourth port P4 (the second check data comes from reg update among Fig. 3, reg
  • the logic at update can be as follows: obtain the data for storage from the data bus, and perform a verification operation on the acquired data according to the preset verification method, and the obtained verification data is used as the second verification corresponding to the stored data data), and output the received second verification data from the fifth port P5.
  • the memory 315 can receive the second verification data from the first multiplexer 313 from the sixth port P6, the memory 315 can store the received second verification data, and the memory 315 can also output the received data from the seventh port P7 The second verification data of .
  • the comparison module 35 can receive the second verification data from the memory 315 from the eighth port P8, and the comparison module 35 can then compare the first verification data received from the ninth port P9 with the first verification data received from the eighth port P8. The two verification data are compared to generate a fourth verification result signal based on the comparison result of the first verification data and the second verification data.
  • the fourth verification result signal may be used to indicate whether the first verification data and the second verification data are the same.
  • the fourth verification result signal can be a high-level signal, and the fourth verification result signal can be expressed as "1"; otherwise, the fourth verification result signal The signal may be a low level signal, and the fourth verification result signal may represent "0".
  • the fourth verification result signal can be subsequently used to generate the second verification result signal.
  • the memory 315 can output the stored second verification data from the seventh port P7.
  • the first NOT gate 311 can receive the second verification data from the memory 315 from the first port P1, and output the second verification data from the second port P2 after inverting the received second verification data.
  • the inversion result of wherein, in the case of the second verification data expressed as "1", the inversion result of the second verification data is expressed as "0"; in the case of the second verification data expressed as "0" Next, the inverted result of the second verification data is expressed as "1".
  • the first multiplexer 313 can receive the inversion result of the second verification data from the first NOT gate 311 from the third port P3, and output the inversion of the received second verification data from the fifth port P5 result.
  • the memory 315 may receive the inversion result of the second verification data from the first multiplexer 313 from the sixth port P6, and output the inversion result of the received second verification data from the seventh port P7.
  • the comparison module 35 can receive the inversion result of the second verification data from the memory 315 from the eighth port P8.
  • the comparison module 35 is equivalent to receiving the second verification data after error injection from the eighth port P8, and the comparison module 35 Next, the first verification data received from the ninth port P9 can be compared with the second verification data after error injection received from the eighth port P8, so as to The comparison result of the second verification data generates a third verification result signal.
  • the third verification result signal may be used to represent whether the first verification data is the same as the error-injected second verification data.
  • the third verification result signal may be a high-level signal, and the third verification result signal may be expressed as "1"; otherwise, the third verification result signal
  • the third verification result signal may be a low-level signal, and the third verification result signal may represent "0".
  • the third verification result signal can be subsequently used to generate the first verification result signal.
  • the first multiplexer 313 can receive a diagnosis (diagnose) signal, and based on the received diagnose signal, the first multiplexer 313 can determine whether the fault diagnosis circuit is currently in the first working mode or the second working mode mode, and according to the determined working mode, it is further determined whether the second verification data output from the fifth port P5 or the second verification data after error injection is output.
  • diagnosis diagnosis
  • the first multiplexer 313 can determine whether the fault diagnosis circuit is currently in the first working mode or the second working mode mode, and according to the determined working mode, it is further determined whether the second verification data output from the fifth port P5 or the second verification data after error injection is output.
  • the diagnose signal received by the first multiplexer 313 can directly come from a central processing unit (Central Processing Unit, CPU); or, the diagnose signal received by the first multiplexer 313 can directly It comes from a register specially used to store the diagnose signal, and the diagnose signal in the register can be written by the CPU.
  • CPU Central Processing Unit
  • the safety protection circuit further includes: a second NOT gate 37;
  • the comparison module 37 is electrically connected to the diagnostic module 5 through the second NOT gate 37, and the inversion result of the second NOT gate 37 to the third verification result signal is used as the first verification result signal, and the second NOT gate 37 is used for the fourth verification result signal.
  • the inversion result of the result signal is used as the second verification result signal.
  • the second NOT gate 37 may have an eleventh port P11 and a twelfth port P12, the eleventh port P11 may be electrically connected to the tenth port P10, and the twelfth port P12 may be electrically connected to the diagnostic module 5. connect. It should be noted that, the eleventh port P11 may serve as the input end of the second NOT gate 37 , and the twelfth port P12 may serve as the output end of the second NOT gate 37 .
  • the comparison module 35 can output the fourth verification result signal from the tenth port P10, and the second NOT gate 37 can receive the fourth verification result signal from the comparison module 35 from the eleventh port P11. check result signal, the second NOT gate 37 can carry out inversion processing to the received fourth check result signal, to obtain the inversion result of the fourth check result signal, and output the fourth check result signal from the twelfth port P12 The inversion result of the test result signal.
  • diagnosis module 5 can receive the inversion result of the fourth verification result signal from the comparison module 35, so that the diagnosis module 5 is equivalent to receiving the second verification result signal, and the diagnosis module 5 can check the protected circuit accordingly. 1 Carry out fault diagnosis.
  • the comparison module 35 can output the third verification result signal from the tenth port P10, and the second NOT gate 37 can receive the third signal from the comparison module 35 from the eleventh port P11. check result signal, the second NOT gate 37 can carry out inversion processing to the received third check result signal, to obtain the inversion result of the third check result signal, and output the third check result signal from the twelfth port P12 The inversion result of the test result signal.
  • diagnosis module 5 can receive the inversion result of the third verification result signal from the comparison module 35, so that the diagnosis module 5 is equivalent to having received the first verification result signal, and the diagnosis module 5 can check the safety protection circuit accordingly. 3 Carry out fault diagnosis.
  • the second verification result signal can be efficiently and reliably generated based on the fourth verification result signal and the first verification result signal can be generated based on the third verification result signal.
  • the second NOT gate 37 may not be specially provided in the safety protection circuit 3 .
  • the tenth port P10 may not be electrically connected to the diagnostic module 5 through the second NOT gate 37 , but directly electrically connected to the diagnostic module 5 .
  • the third verification result signal may be directly used as the first verification result signal
  • the fourth verification result signal may be directly used as the second verification result signal.
  • the calculation module 33 can efficiently and reliably perform the verification operation to realize the acquisition of the first verification data, by including the first NOT gate 311, the first multiplexer 313 and the memory 315
  • the processing module 31 can use the inversion processing in the element circuit to efficiently and reliably realize the error injection of the second check data, without having to specially calculate an error value as the second check data after the error injection, and then,
  • the comparison module 35 can efficiently and reliably realize the comparison of the corresponding verification data and the generation of the corresponding verification result signal, so as to realize the fault diagnosis of the safety protection circuit 3 and the protected circuit 1 based on the generated verification result signal.
  • the stored data in the protected circuit 1 can be updated, for example, the CPU can update the stored data through the data bus; for another example, the protected circuit 1 can update the stored data through the hardware itself .
  • the second verification data stored in the memory 315 also needs to be updated accordingly.
  • the memory 315 may also have a thirteenth port P13, and the thirteenth port P13 may be electrically connected to a specific circuit, and the specific circuit may be based on the signal transmitted on the data bus and/or the Some signals involved in , generate control and judgment logic, and the control and judgment logic can be used to control the update conditions of the second verification data stored in the memory 315 .
  • the diagnosis module 5 includes: a first logic gate 51, a second logic gate 53 and a second multiplexer 55;
  • the first logic gate 51 and the second logic gate 53 are electrically connected to each safety protection circuit 3 respectively, and the first logic gate 51 and the second logic gate 53 are also electrically connected to the second multiplexer 55;
  • the second multiplexer 55 When the fault diagnosis circuit is in the first working mode, the second multiplexer 55 is used to output the first logic gate 51 to perform the first logic operation on the multiple second verification result signals generated by the multiple safety protection circuits 3
  • the first operation result signal obtained by the operation, the first operation result signal is used to indicate whether there is a faulty protected circuit 1 among the plurality of protected circuits 1;
  • the second multiplexer 55 is used to output the second logic gate 53 to perform a second logic operation on a plurality of first verification result signals generated by a plurality of safety protection circuits 3
  • the second operation result signal obtained through the operation is used to indicate whether there is a faulty safety protection circuit 3 among the plurality of safety protection circuits 3 .
  • the number of safety protection circuits 3 and protected circuits 1 can be multiple (for example, n), n can be 2, 3, 4, 5 or an integer greater than 5, and multiple safety protection circuits 3 and multiple protected circuits
  • the circuits 1 can be electrically connected in a one-to-one correspondence.
  • the first logic gate 51 can be an OR gate
  • the first logic operation can be an OR operation
  • the second logic gate 53 can be an AND gate
  • the second logic operation can be an AND operation
  • the first logic gate 51 can be an AND operation
  • Gate the first logic operation may be an AND operation
  • the second logic gate 53 may be an OR gate
  • the second logic operation may be an OR operation.
  • the first logic gate 51 may have a fourteenth port P14
  • the second logic gate 53 may have a fifteenth port P15
  • the second multiplexer 55 may have a sixteenth port P16, a seventeenth port P17, and a The eighteenth port P18, the sixteenth port P16 may be electrically connected to the fourteenth port P14, and the seventeenth port P17 may be electrically connected to the fifteenth port P15.
  • the fourteenth port P14 can be used as the output terminal of the first logic gate 51
  • the fifteenth port P15 can be used as the output terminal of the second logic gate 53
  • the sixteenth port P16 and the seventeenth port P17 can be used as the output terminal of the second logic gate 53 respectively.
  • An input terminal of the second multiplexer 55 , the eighteenth port P18 serves as an output terminal of the second multiplexer 55 .
  • multiple safety protection circuits 3 can output second verification result signals generated by themselves, and the first logic gate 51 can receive multiple second verification results through multiple input terminals.
  • the result signal (equivalent to Parity 1 error to Parity n error in Fig. 4 and Fig. 5 under the first working mode), and the first logical operation is carried out to a plurality of second verification result signals received to obtain the first
  • the operation result signal (equivalent to the Parity error in Fig. 4 and Fig. 5 in the first working mode), and the first operation result signal is output from the fourteenth port P14.
  • the second multiplexer 55 may receive the first operation result signal from the first logic gate 51 from the sixteenth port P16, and output the received first operation result signal from the eighteenth port P18, based on With the first calculation result signal, relevant personnel can know whether there is a faulty protected circuit 1 among the plurality of protected circuits 1 .
  • each safety protection circuit 3 is provided with the second NOT gate 37 shown in FIG. Parity 1 error to Parity n error in Figure 4 and Figure 5 can be expressed as "0"; otherwise, in the first working mode, at least part of Parity 1 error to Parity n error in Figure 4 and Figure 5 can be expressed to "1".
  • the first logic gate 51 is an OR gate, then in the case that the Parity error in the first operating mode is represented as "0", it can be considered that there is no faulty protected circuit in the plurality of protected circuits 1 1; and in the case that the Parity error in the first working mode is expressed as "1", it can be considered that there is a faulty protected circuit 1 among the plurality of protected circuits 1 .
  • multiple safety protection circuits 3 can output first verification result signals generated by themselves, and the second logic gate 53 can receive multiple first verification results through multiple input terminals.
  • the result signal (equivalent to Parity 1 error to Parity n error in Fig. 4 and Fig. 5 under the second working mode), performs a second logical operation on the received multiple first verification result signals to obtain the second operation
  • the result signal (equivalent to the Parity error in Fig. 4 and Fig. 5 in the second working mode), and output the second operation result signal from the fifteenth port P15.
  • the second multiplexer 55 may receive the second operation result signal from the second logic gate 53 from the seventeenth port P17, and output the received second operation result signal from the eighteenth port P18, based on With the second calculation result signal, relevant personnel can know whether there is a faulty safety protection circuit 3 among the plurality of safety protection circuits 3 .
  • each safety protection circuit 3 is provided with a second NOT gate 37 shown in FIG.
  • Parity 1 error to Parity n error in Figure 4 and Figure 5 can be expressed as "1"; otherwise, in the second working mode, Parity 1 error to Parity n error in Figure 4 and Figure 5 can be expressed as "0" ".
  • the second logic gate 53 is an AND gate, then in the case that the Parity error in the second operating mode is expressed as "1", it can be considered that there is no A faulty safety protection circuit 3; and in the case that the Parity error in the second working mode is "0", it can be considered that there is a faulty safety protection circuit 3 among the multiple safety protection circuits 3 in the fault diagnosis circuit.
  • the second multiplexer 55 can also receive the diagnose signal, and based on the received diagnose signal, the second multiplexer 55 can determine the failure Whether the diagnostic circuit is currently in the first working mode or the second working mode.
  • the diagnosis module 5 including the first logic gate 51, the second logic gate 53 and the second multiplexer 55, based on the logic operation at the first logic gate 51, it can be very efficient Reliably diagnose whether there is a faulty protected circuit 1 in a plurality of protected circuits 1; based on the logic operation at the second logic gate 53, it can be very efficiently and reliably diagnosed whether a plurality of safety protection circuits 3 have a faulty safe Protection circuit 3. That is to say, in the embodiment of the present disclosure, the diagnostic module 5 can realize batch fault diagnosis of the protected circuit 1 and batch fault diagnosis of the safety protection circuit 3 .
  • the diagnostic module 5 includes: a fault location circuit 57;
  • the fault location circuit 57 is electrically connected to each safety protection circuit 3 respectively;
  • the fault location circuit 57 is used to output a plurality of second verification result signals based on a plurality of safety protection circuits 3 to indicate that a fault occurs in a plurality of protected circuits 1
  • the fault location circuit 57 is used to output a plurality of first verification result signals generated based on the plurality of safety protection circuits 3 to indicate that a fault occurs in the plurality of safety protection circuits 3 The second indication signal of the safety protection circuit 3.
  • the number of safety protection circuits 3 and protected circuits 1 can be multiple (for example, n), n can be 2, 3, 4, 5 or an integer greater than 5, and multiple safety protection circuits 3 and multiple protected circuits
  • the circuits 1 can be electrically connected in a one-to-one correspondence.
  • the fault location circuit 57 may have a nineteenth port P19 and a twentieth port P20 , and the nineteenth port P19 and the twentieth port P20 may serve as an output end of the fault location circuit 57 respectively.
  • the fault location circuit 57 can, according to the set order, generate a plurality of second verification result signals for the plurality of safety protection circuits 3 (equivalent to the first working mode, Fig. 4.
  • each safety protection circuit 3 is provided with the second NOT gate 37 shown in FIG.
  • Parity 1 error to Parity n error in Figure 4 and Figure 5 can be expressed as "0"; otherwise, in the first working mode, Parity 1 error to Parity n error in Figure 4 and Figure 5, and the faulty The error corresponding to the protected circuit 1 is expressed as "1".
  • Parity 1 error to Parity n error in Figure 4 and Figure 5 are all expressed as “0", the function error number can be "0" as the default value, and relevant personnel can accordingly It is known that there are no faults in multiple protected circuits 1; if in the first working mode, the Parity 2 error in Figure 4 and Figure 5 is expressed as "1”, the function error number can be "2”, and relevant personnel can learn accordingly The protected circuit 1 corresponding to Parity 2 error is faulty. If in the first working mode, both Parity 1 error and Parity 2 error in Figure 4 and Figure 5 are expressed as "1”, the function error number can be "1", and the relevant personnel can know the protected corresponding to Parity 1 error accordingly.
  • the function error number can be "2"
  • the relevant personnel can know that there is a fault in the protected circuit 1 corresponding to the Parity 2 error, that is, when the number of faulty protected circuits 1 is at least When 1, the function error number can only indicate the protected circuit 1 with the highest or lowest corresponding error number.
  • the fault location circuit 57 can, according to the set order, generate a plurality of first verification result signals for a plurality of safety protection circuits 3 (equivalent to the second working mode, Fig. 4. Scan from Parity 1 error to Parity n error in Figure 5, for example, scan according to the order of error numbers from low to high or from high to low, to determine the safety protection circuit that has failed in multiple safety protection circuits 3 3. According to this, the second indication signal (equivalent to the diagnose error number in Fig. 4 and Fig. 5) is output from the twentieth port P20.
  • each safety protection circuit 3 is provided with a second NOT gate 37 shown in FIG. Parity 1 error to Parity n error in Fig. 4 and Fig. 5 can all be expressed as "1"; otherwise, in the second working mode, Parity 1 error to Parity n error in Fig. 4 and Fig. The error corresponding to the safety protection circuit 3 is expressed as "0".
  • Parity 1 error to Parity n error in Figure 4 and Figure 5 are all expressed as “1"
  • the diagnose error number can be "0" as the default value, and relevant personnel can accordingly
  • the diagnose error number can be "1”
  • relevant personnel can learn accordingly
  • the safety protection circuit 3 corresponding to Parity 1 error is faulty.
  • both Parity 1 error and Parity 2 error in Figure 4 and Figure 5 are expressed as "0"
  • the diagnose error number can be "1”
  • relevant personnel can learn the safety protection circuit corresponding to Parity1error 3 has a fault
  • the diagnose error number can be "2”
  • the relevant personnel can learn that there is a fault in the safety protection circuit 3 corresponding to Parity 2 error, that is, when the number of safety protection circuits 3 with a fault is at least one
  • the diagnose error number can only indicate the corresponding safety protection circuit 3 with the highest or lowest error number.
  • the fault location circuit 57 by setting the fault location circuit 57, it is possible to summarize and locate all the errors of the protected circuit 1 and the errors of the safety protection circuit 3. Specifically, the fault location circuit 57 can be performed in the first working mode. The output of the first indication signal is to accurately indicate the position of the protected circuit 1 where the fault occurs, and the output of the second indication signal is performed in the second working mode to accurately indicate the position of the safety protection circuit 3 where the fault occurs.
  • the fault diagnosis circuit is first placed in the normal working mode.
  • the fault injection function can be enabled by software, so that the fault diagnosis circuit is placed in the fault injection mode, and then See if an error can be detected in the error injection mode (equivalent to detecting whether Parity 1 error to Parity n error in Figure 4 and Figure 5 are all expressed as "1" in the second working mode). If an error can be detected in the error injection mode (equivalent to the second working mode, in which Parity 1 error to Parity n error in Figure 4 and Figure 5 are all represented as "1"), it can be considered that the test is successful, as shown in Figure 4
  • Each safety protection circuit 3 in has no latent failure. Well, you can turn off error injection and switch back to normal working mode.
  • all protected circuits 1 can be diagnosed in batches in the normal working mode, and if any protected circuit 1 fails, the location of the faulty protected circuit 1 can be accurately indicated.
  • batch inversion processing can be performed without separate error injection, which greatly improves the efficiency of error injection, and the software can diagnose all safety protection circuits in batches with only a single operation 3 , if any safety protection circuit 3 breaks down, accurately indicate the position of the safety protection circuit 3 that has failed.
  • Fig. 7 is a schematic flowchart of a fault diagnosis method provided by an exemplary embodiment of the present disclosure. The method shown in FIG. 7 is applied to the fault diagnosis circuit above, and the method shown in FIG. 7 includes step 701 , step 702 , step 703 and step 704 .
  • Step 701 performing a verification operation on the stored data in the protected circuit to obtain first verification data
  • Step 702 performing error injection on the second verification data corresponding to the stored data
  • Step 703 generating a first verification result signal based on the first verification data and the second verification data after error injection;
  • Step 704 based on the first verification result signal, perform fault diagnosis on the safety protection circuit in the fault diagnosis circuit.
  • the fault diagnosis method further includes:
  • Step 711 generating a second verification result signal based on the first verification data and the second verification data
  • Step 712 perform fault diagnosis on the protected circuit based on the second verification result signal.
  • Any fault diagnosis method provided in the embodiments of the present disclosure may be executed by any appropriate device with data processing capabilities, including but not limited to: terminal devices, servers, and the like.
  • any of the fault diagnosis methods provided in the embodiments of the present disclosure may be executed by a processor, for example, the processor executes any of the fault diagnosis methods mentioned in the embodiments of the present disclosure by calling corresponding instructions stored in a memory. I won't go into details below.
  • Fig. 9 is a schematic structural diagram of a fault diagnosis device provided by an exemplary embodiment of the present disclosure.
  • the apparatus shown in FIG. 9 includes a first processing module 901 , a second processing module 902 , a first generating module 903 and a third processing module 904 .
  • the first processing module 901 is configured to perform a verification operation on the stored data in the protected circuit to obtain first verification data
  • the second processing module 902 is configured to perform error injection on the second verification data corresponding to the stored data
  • the first generation module 903 is configured to generate a first verification result signal based on the first verification data obtained by the first processing module 901 and the second verification data after error injection obtained by the second processing module 902;
  • the third processing module 904 is configured to perform fault diagnosis on the safety protection circuit in the fault diagnosis circuit based on the first verification result signal generated by the first generation module 903 .
  • the fault diagnosis device further includes:
  • the second generation module 911 is configured to generate a second verification result signal based on the first verification data and the second verification data obtained by the first processing module 901;
  • the fourth processing module 912 is configured to perform fault diagnosis on the protected circuit based on the second verification result signal generated by the second generating module 911 .
  • the electronic device may be either or both of the first device and the second device, or a stand-alone device independent of them, and the stand-alone device may communicate with the first device and the second device to receive collected data from them. input signal.
  • FIG. 11 illustrates a block diagram of an electronic device according to an embodiment of the present disclosure.
  • an electronic device 1100 includes one or more processors 1101 and a memory 1102 .
  • the processor 1101 may be a CPU or other forms of processing units with data processing capabilities and/or instruction execution capabilities, and may control other components in the electronic device 1100 to perform desired functions.
  • Memory 1102 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory.
  • the volatile memory may include, for example, random access memory (RAM) and/or cache memory (cache).
  • the non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, and the like.
  • One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1101 may execute the program instructions to implement the above-mentioned fault diagnosis methods of various embodiments of the present disclosure and/or other expected functionality.
  • Various contents such as input signal, signal component, noise component, etc. may also be stored in the computer-readable storage medium.
  • the electronic device 1100 may further include: an input device 1103 and an output device 1104, and these components are interconnected through a bus system and/or other forms of connection mechanisms (not shown).
  • the input device 1103 may be a microphone or a microphone array.
  • the input device 13 may be a communication network connector for receiving collected input signals from the first device and the second device.
  • the input device 1103 may also include, for example, a keyboard, a mouse, and the like.
  • the output device 1104 can output various information to the outside, including determined distance information, direction information, and the like.
  • the output device 1104 may include, for example, a display, a speaker, a printer, a communication network and remote output devices connected thereto, and the like.
  • the electronic device 1100 may further include any other appropriate components.
  • embodiments of the present disclosure may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the above-mentioned "exemplary method" of this specification.
  • the steps in the fault diagnosis method according to various embodiments of the present disclosure are described in the section.
  • the methods and apparatus of the present disclosure may be implemented in many ways.
  • the methods and apparatuses of the present disclosure may be implemented by software, hardware, firmware or any combination of software, hardware, and firmware.
  • the above sequence of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the sequence specifically described above unless specifically stated otherwise.
  • the present disclosure can also be implemented as programs recorded in recording media, the programs including machine-readable instructions for realizing the method according to the present disclosure.
  • the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.
  • each component or each step can be decomposed and/or reassembled. These decompositions and/or recombinations should be considered equivalents of the present disclosure.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

公开了一种故障诊断电路、方法、装置及计算机可读存储介质。故障诊断电路包括：安全保护电路和诊断模块；安全保护电路与被保护电路电连接，用于对被保护电路中的已存储数据进行校验运算，以得到第一校验数据，对已存储数据对应的第二校验数据进行错误注入，且基于第一校验数据和错误注入后的第二校验数据，生成第一校验结果信号；诊断模块与安全保护电路电连接，诊断模块用于基于第一校验结果信号，对安全保护电路进行故障诊断。本公开的实施例能够通过简单的硬件结构，实现安全保护电路的故障诊断，以便基于诊断结果进行故障排除，从而保证芯片的正常运行。

Description

故障诊断电路、方法、装置及计算机可读存储介质
本申请要求于2021年8月20日提交到国家知识产权局、申请号为202110958241.7、发明名称为“故障诊断电路、方法、装置及计算机可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及故障诊断技术领域，尤其涉及一种故障诊断电路、方法、装置及计算机可读存储介质。
背景技术
由于功能安全的等级要求，芯片中的一些电路需要有对应的安全保护电路。需要指出的是，安全保护电路本身可能存在故障，这会影响到芯片的正常运行，因此，如何实现安全保护电路的故障诊断对于本领域技术人员而言是一个值得关注的问题。
发明内容
为了解决上述技术问题，提出了本公开。本公开的实施例提供了一种故障诊断电路、方法、装置及计算机可读存储介质。
根据本公开实施例的一个方面，提供了一种故障诊断电路，包括：安全保护电路和诊断模块；
所述安全保护电路与被保护电路电连接，用于对所述被保护电路中的已存储数据进行校验运算，以得到第一校验数据，对所述已存储数据对应的第二校验数据进行错误注入，且基于所述第一校验数据和所述错误注入后的第二校验数据，生成第一校验结果信号；
所述诊断模块与所述安全保护电路电连接，所述诊断模块用于基于所述第一校验结果信号，对所述安全保护电路进行故障诊断。
根据本公开实施例的另一个方面，提供了一种故障诊断方法，应用于上述故障诊断电路，所述故障诊断方法包括：
对被保护电路中的已存储数据进行校验运算，以得到第一校验数据；
对所述已存储数据对应的第二校验数据进行错误注入；
基于所述第一校验数据和所述错误注入后的第二校验数据，生成第一校验结果信号；
基于所述第一校验结果信号，对所述故障诊断电路中的安全保护电路进行故障诊断。
根据本公开实施例的再一个方面，提供了一种故障诊断装置，应用于上述故障诊断电路，所述故障诊断装置包括：
第一处理模块，用于对被保护电路中的已存储数据进行校验运算，以得到第一校验数据；
第二处理模块，用于对所述已存储数据对应的第二校验数据进行错误注入；
第一生成模块，用于基于所述第一处理模块得到的所述第一校验数据和所述第二处理模块得到的所述错误注入后的第二校验数据，生成第一校验结果信号；
第三处理模块，用于基于所述第一生成模块生成的所述第一校验结果信号，对所述故障诊断电路中的安全保护电路进行故障诊断。
根据本公开实施例的又一个方面，提供了一种计算机可读存储介质，所述存储介质存储有计算机程序， 所述计算机程序用于执行上述故障诊断方法。
根据本公开实施例的又一个方面，提供了一种电子设备，包括：
处理器；
用于存储所述处理器可执行指令的存储器；
所述处理器，用于从所述存储器中读取所述可执行指令，并执行所述指令以实现上述故障诊断方法。
基于本公开上述实施例提供的一种故障诊断电路、方法、装置、计算机可读存储介质及电子设备，安全保护电路可以通过校验数据的获取，再结合错误注入，生成第一校验结果信号，并将生成的第一校验结果信号提供给诊断模块，诊断模块可以据此对安全保护电路进行故障诊断，因此，本公开的实施例能够通过简单的硬件结构，实现安全保护电路的故障诊断，以便基于诊断结果进行故障排除，从而保证芯片的正常运行。
下面通过附图和实施例，对本公开的技术方案做进一步的详细描述。
附图说明
通过结合附图对本公开实施例进行更详细的描述，本公开的上述以及其他目的、特征和优势将变得更加明显。附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。在附图中，相同的参考标号通常代表相同部件或步骤。
图1是本公开所适用的场景示意图。
图2是本公开一示例性实施例提供的故障诊断电路的结构示意图。
图3是本公开一示例性实施例提供的故障诊断电路中安全保护电路的结构示意图。
图4是本公开另一示例性实施例提供的故障诊断电路的结构示意图。
图5是本公开一示例性实施例提供的故障诊断电路中诊断模块的结构示意图。
图6是本公开一示例性实施例提供的故障诊断电路中错误注入的流程示意图。
图7是本公开一示例性实施例提供的故障诊断方法的流程示意图。
图8是本公开另一示例性实施例提供的故障诊断方法的流程示意图。
图9是本公开一示例性实施例提供的故障诊断装置的结构示意图。
图10是本公开另一示例性实施例提供的故障诊断装置的结构示意图。
图11是本公开一示例性实施例提供的电子设备的结构图。
具体实施方式
下面，将参考附图详细地描述根据本公开的示例实施例。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是本公开的全部实施例，应理解，本公开不受这里描述的示例实施例的限制。
应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本公开的范围。
本领域技术人员可以理解，本公开实施例中的“第一”、“第二”等术语仅用于区别不同步骤、设备或模块等，既不代表任何特定技术含义，也不表示它们之间的必然逻辑顺序。
还应理解，在本公开实施例中，“多个”可以指两个或两个以上，“至少一个”可以指一个、两个或两个以上。
本公开实施例可以应用于终端设备、计算机系统、服务器等电子设备，其可与众多其它通用或专用计算系统环境或配置一起操作。适于与终端设备、计算机系统、服务器等电子设备一起使用的众所周知的终端设备、计算系统、环境和/或配置的例子包括但不限于：包括芯片(例如汽车芯片、轮船芯片、飞机芯片 等)的设备或系统、个人计算机系统、服务器计算机系统、瘦客户机、厚客户机、手持或膝上设备、基于微处理器的系统、机顶盒、可编程消费电子产品、网络个人电脑、小型计算机系统、大型计算机系统和包括上述任何系统的分布式云计算技术环境，等等。
申请概述
在实现本公开的过程中，发明人发现，由于功能安全的等级要求，芯片中的一些电路(其可以称为被保护电路)需要有对应的安全保护电路，安全保护电路可以通过特定的安全保护机制对被保护电路进行保护。可选地，芯片可以为智能汽车的芯片，被保护电路可以为寄存器。
需要指出的是，安全保护电路本身也可能存在故障，这会影响到芯片的正常运行，为了排除安全保护电路的故障，以保证芯片的正常运行，有必要对安全保护电路进行故障诊断。
示例性系统
如图1所示，对应于被保护电路1，可以设置本公开的实施例提供的故障诊断电路，故障诊断电路可以包括安全保护电路3，安全保护电路3可以与被保护电路1电连接。通过故障诊断电路的运行，可以实现对安全保护电路3的故障诊断，可选地，通过故障诊断电路的运行，还可以实现对被保护电路1的故障诊断。
需要说明的是，本公开的实施例中涉及非门、或门、与门等逻辑门以及多路复用器(MUX)。
示例性电路
图2是本公开一示例性实施例提供的故障诊断电路的结构示意图。如图2所示，故障诊断电路包括：安全保护电路3和诊断模块5。
安全保护电路3与被保护电路1电连接，用于对被保护电路1中的已存储数据进行校验运算，以得到第一校验数据，对已存储数据对应的第二校验数据进行错误注入，且基于第一校验数据和错误注入后的第二校验数据，生成第一校验结果信号；
诊断模块5与安全保护电路3电连接，诊断模块5用于基于第一校验结果信号，对安全保护电路3进行故障诊断。
这里，被保护电路1可以为能够进行数据存储的电路，例如为寄存器。可选地，寄存器可以为数据寄存器或者控制寄存器。可以理解的是，控制寄存器可以用于控制整个芯片、芯片中的子系统或者芯片中的模块的功能配置；数据寄存器可以存放数据的先进先出(First Input First Output，FIFO)队列、进行数据缓存等。寄存器宽度可以为4bit、8bit、16bit、32bit等，当然，寄存器宽度并不局限于此，具体可以根据实际需求进行选择，本公开的实施例对此不做任何限定。
本公开的实施例中，通过安全保护电路3与被保护电路1之间的电连接，安全保护电路3可以获取被保护电路1中的已存储数据。接下来，安全保护电路3可以按照预设校验方式，对已存储数据进行校验运算，以得到第一校验数据。
可选地，安全保护电路3可以采用循环冗余校验(Cyclic Redundancy Check，CRC)算法，对已存储数据进行CRC运算，以得到相应的CRC数值，并将所得到的CRC数值作为第一校验数据；或者，安全保护电路3可以采用奇偶校验算法，对已存储数据进行奇偶校验运算，以得到相应的奇偶校验数值，并将所得到的奇偶校验数值作为第一校验数据。
为了便于理解，本公开的实施例中均以预设校验方式为采用奇偶校验算法的情况为例进行说明。
另外，安全保护电路3还可以获取已存储数据对应的第二校验数据。为了实现第二校验数据的获取，安全保护电路3可以与高级可扩展接口(Advanced eXtensible Interface，AXI)、高级外围总线(Advanced Peripheral Bus，APB)等数据总线电连接，数据总线上可以传输用于存储的数据，被保护电路1具体可以从数据总线上获取用于存储的数据并进行存储，被保护电路1所存储的数据即可作为已存储数据。安全保 护电路3可以基于数据总线，获取已存储数据对应的第二校验数据。
可选地，安全保护电路3可以从数据总线上获取用于存储的数据，并按照预设校验方式，对所获取的数据进行校验运算，得到的校验数据即可作为已存储数据对应的第二校验数据；或者，数据总线上除了传输用于存储的数据之外，还可以传输用于存储的数据对应的校验数据，该校验数据可以为按照预设校验方式，对数据总线上传输的用于存储的数据进行校验运算后得到的，数据总线上传输的校验数据可以作为已存储数据对应的第二校验数据。
在获取第二校验数据之后，安全保护电路3可以对第二校验数据进行错误注入，以将错误引入第二校验数据，从而得到错误注入后的第二校验数据，以便基于第一校验数据和错误注入后的第二校验数据，生成第一校验结果信号。
可选地，安全保护电路3可以将第一校验数据和错误注入后的第二校验数据进行比较，并基于第一校验数据和错误注入后的第二校验数据的比较结果，生成第一校验结果信号，第一校验结果信号可以为能够用于确定第一校验数据和错误注入后的第二校验数据是否相同的信号。
在安全保护电路3生成第一校验结果信号之后，通过诊断模块5与安全保护电路3之间的电连接，诊断模块5可以获取第一校验结果信号，以便据此对安全保护电路3进行故障诊断，例如确定安全保护电路3是否存在故障。
本公开的实施例提供的故障诊断电路中，安全保护电路3可以通过校验数据的获取，再结合错误注入，生成第一校验结果信号，并将生成的第一校验结果信号提供给诊断模块5，诊断模块5可以据此对安全保护电路3进行故障诊断，因此，本公开的实施例能够通过简单的硬件结构，实现安全保护电路3的故障诊断，以便基于诊断结果进行故障排除，从而保证芯片的正常运行。
在一个可选示例中，安全保护电路3还用于基于第一校验数据和第二校验数据，生成第二校验结果信号；诊断模块5还用于基于第二校验结果信号，对被保护电路1进行故障诊断。
本公开的实施例中，安全保护电路3还可以将第一校验数据和第二校验数据进行比较，并基于第一校验数据和第二校验数据的比较结果，生成第二校验结果信号，第二校验结果信号可以为能够用于确定第一校验数据和第二校验数据是否相同的信号。
在安全保护电路3生成第二校验结果信号之后，通过诊断模块5与安全保护电路3之间的电连接，诊断模块5可以获取第二校验结果信号，以便据此对被保护电路1进行故障诊断，例如确定被保护电路1是否存在故障。
可见，本公开的实施例中，通过简单的硬件结构，不仅能够实现安全保护电路3的故障诊断，还能够实现被保护电路1的故障诊断，以便基于诊断结果进行故障排除，从而能够进一步保证芯片的正常运行。
在一个可选示例中，如图3所示，安全保护电路3可以包括：处理模块31、计算模块33和比较模块35；
比较模块35分别与处理模块31、计算模块33、图2中的诊断模块5电连接，计算模块33还与被保护电路1电连接；
计算模块33用于对已存储数据进行校验运算，以得到第一校验数据；
处理模块31用于对第二校验数据进行错误注入；
比较模块35用于基于第一校验数据和错误注入后的第二校验数据的比较结果，生成第三校验结果信号，第一校验结果信号基于第三校验结果信号生成；
比较模块35还用于基于第一校验数据和第二校验数据的比较结果，生成第四校验结果信号，第二校验结果信号基于第四校验结果信号生成。
这里，比较模块35可以为比较器。
在一种具体实施方式中，处理模块31包括：第一非门311、第一多路复用器313和存储器315；
第一多路复用器313与存储器315电连接，存储器315还通过第一非门311与第一多路复用器313电连接，第一多路复用器313还与数据总线电连接，存储器315还与比较模块35电连接；
在故障诊断电路处于第一工作模式的情况下，第一多路复用器313用于输出基于数据总线获取的第二校验数据，以使存储器315存储第二校验数据并输出第二校验数据至比较模块35；
在故障诊断电路处于第二工作模式的情况下，第一多路复用器313用于输出第一非门311对存储器315存储的第二校验数据的取反结果，以使存储器315输出第二校验数据的取反结果至比较模块35，第二校验数据的取反结果作为错误注入后的第二校验数据。
这里，第一非门311可以具有第一端口P1和第二端口P2，第一多路复用器313可以具有第三端口P3、第四端口P4和第五端口P5，存储器315可以具有第六端口P6和第七端口P7，比较模块35可以具有第八端口P8、第九端口P9和第十端口P10。第一端口P1可以与第七端口P7电连接，第二端口P2可以与第三端口P3电连接，第四端口P4可以与数据总线电连接，第五端口P5可以与第六端口P6电连接，第七端口P7可以与第八端口P8电连接，第九端口P9可以与计算模块33电连接，第十端口P10可以与诊断模块5电连接。
需要说明的是，第一端口P1可以作为第一非门311的输入端，第二端口P2可以作为第一非门311的输出端，第三端口P3和第四端口P4可以分别作为第一多路复用器313的一输入端，第五端口P5可以作为第一多路复用器313的输出端，第八端口P8和第九端口P9可以分别作为比较模块35的一输入端，第十端口P10可以作为比较模块35的输出端。
这里，故障诊断电路可以包括两个工作模式，分别是第一工作模式和第二工作模式。在第一工作模式下，可以进行被保护电路1的故障诊断，第一工作模式也可以称为正常工作模式；在第二工作模式下，可以进行安全保护电路3的故障诊断，第二工作模式也可以称为错误注入模式。
本公开的实施例中，由于计算模块33用于对已存储数据进行校验运算，以得到第一校验数据，无论故障诊断电路处于第一工作模式还是第二工作模式，比较模块35均可以从第九端口P9获取来自计算模块33的第一校验数据。
在故障诊断电路处于第一工作模式的情况下，第一多路复用器313可以从第四端口P4接收第二校验数据(该第二校验数据来源于图3中的reg update，reg update处的逻辑可以为：从数据总线获取用于存储的数据，并按照预设校验方式，对所获取的数据进行校验运算，得到的校验数据作为已存储数据对应的第二校验数据)，并从第五端口P5输出接收到的第二校验数据。存储器315可以从第六端口P6接收来自第一多路复用器313的第二校验数据，存储器315可以存储接收到的第二校验数据，存储器315还可以从第七端口P7输出接收到的第二校验数据。比较模块35可以从第八端口P8接收来自存储器315的第二校验数据，比较模块35接下来可以将从第九端口P9接收到的第一校验数据与从第八端口P8接收到的第二校验数据进行比较，以基于第一校验数据和第二校验数据的比较结果，生成第四校验结果信号。
其中，第四校验结果信号可以用于表征第一校验数据和第二校验数据是否相同。在第一校验数据和第二校验数据相同的情况下，第四校验结果信号可以为高电平信号，第四校验结果信号可以表示为“1”；否则，第四校验结果信号可以为低电平信号，第四校验结果信号可以表示为“0”。
需要指出的是，第四校验结果信号后续可以用于第二校验结果信号的生成。
在故障诊断电路处于第二工作模式的情况下，存储器315可以从第七端口P7输出所存储的第二校验数据。第一非门311可以从第一端口P1接收来自存储器315的第二校验数据，并在对接收到的第二校验数据进行取反处理后，从第二端口P2输出第二校验数据的取反结果；其中，在第二校验数据表示为“1”的情况下，第二校验数据的取反结果表示为“0”；在第二校验数据表示为“0”的情况下，第二校验数据 的取反结果表示为“1”。第一多路复用器313可以从第三端口P3接收来自第一非门311的第二校验数据的取反结果，并从第五端口P5输出接收到的第二校验数据的取反结果。存储器315可以从第六端口P6接收来自第一多路复用器313的第二校验数据的取反结果，并从第七端口P7输出接收到的第二校验数据的取反结果。比较模块35可以从第八端口P8接收来自存储器315的第二校验数据的取反结果，这样，比较模块35相当于从第八端口P8接收到了错误注入后的第二校验数据，比较模块35接下来可以将从第九端口P9接收到的第一校验数据与从第八端口P8接收到的错误注入后的第二校验数据进行比较，以基于第一校验数据和错误注入后的第二校验数据的比较结果，生成第三校验结果信号。
其中，第三校验结果信号可以用于表征第一校验数据和错误注入后的第二校验数据是否相同。在第一校验数据和错误注入后的第二校验数据相同的情况下，第三校验结果信号可以为高电平信号，第三校验结果信号可以表示为“1”；否则，第三校验结果信号可以为低电平信号，第三校验结果信号可以表示为“0”。
需要指出的是，第三校验结果信号后续可以用于第一校验结果信号的生成。
可选地，第一多路复用器313可以接收诊断(diagnose)信号，基于所接收的diagnose信号，第一多路复用器313可以确定故障诊断电路当前处于第一工作模式还是第二工作模式，并根据确定的工作模式，进一步确定从第五端口P5输出第二校验数据，还是错误注入后的第二校验数据。
需要说明的是，第一多路复用器313所接收的diagnose信号可以直接来自于中央处理器(Central Processing Unit，CPU)；或者，第一多路复用器313所接收的diagnose信号可以直接来自于一专门用于存储diagnose信号的寄存器，该寄存器中的diagnose信号可以由CPU写入。
可选地，为了实现第一校验结果信号和第二校验结果信号的生成，安全保护电路还包括：第二非门37；
比较模块37通过第二非门37与诊断模块5电连接，第二非门37对第三校验结果信号的取反结果作为第一校验结果信号，第二非门37对第四校验结果信号的取反结果作为第二校验结果信号。
这里，参见图3，第二非门37可以具有第十一端口P11和第十二端口P12，第十一端口P11可以与第十端口P10电连接，第十二端口P12可以与诊断模块5电连接。需要说明的是，第十一端口P11可以作为第二非门37的输入端，第十二端口P12可以作为第二非门37的输出端。
在故障诊断电路处于第一工作模式的情况下，比较模块35可以从第十端口P10输出第四校验结果信号，第二非门37可以从第十一端口P11接收来自比较模块35的第四校验结果信号，第二非门37可以对接收到的第四校验结果信号进行取反处理，以得到第四校验结果信号的取反结果，并从第十二端口P12输出第四校验结果信号的取反结果。
其中，在第四校验结果信号表示为“1”的情况下，第四校验结果信号的取反结果表示为“0”；在第四校验结果信号表示为“0”的情况下，第四校验结果信号的取反结果表示为“1”。
进一步地，诊断模块5可以接收来自比较模块35的第四校验结果信号的取反结果，这样，诊断模块5相当于接收到了第二校验结果信号，诊断模块5可以据此对被保护电路1进行故障诊断。
在故障诊断电路处于第二工作模式的情况下，比较模块35可以从第十端口P10输出第三校验结果信号，第二非门37可以从第十一端口P11接收来自比较模块35的第三校验结果信号，第二非门37可以对接收到的第三校验结果信号进行取反处理，以得到第三校验结果信号的取反结果，并从第十二端口P12输出第三校验结果信号的取反结果。
其中，在第三校验结果信号表示为“1”的情况下，第三校验结果信号的取反结果表示为“0”；在第三校验结果信号表示为“0”的情况下，第三校验结果信号的取反结果表示为“1”。
进一步地，诊断模块5可以接收来自比较模块35的第三校验结果信号的取反结果，这样，诊断模块5相当于接收到了第一校验结果信号，诊断模块5可以据此对安全保护电路3进行故障诊断。
可见，基于第二非门37处的取反处理，能够高效可靠地基于第四校验结果信号生成第二校验结果信 号以及基于第三校验结果信号生成第一校验结果信号。
当然，安全保护电路3中也可以不专门设置第二非门37，这时，第十端口P10可以不通过第二非门37与诊断模块5电连接，而是直接与诊断模块5电连接。这种情况下，第三校验结果信号可以直接作为第一校验结果信号，第四校验结果信号可以直接作为第二校验结果信号。
本公开的实施例中，通过计算模块33，能够高效可靠地进行校验运算，以实现第一校验数据的获取，通过包括第一非门311、第一多路复用器313和存储器315的处理模块31，能够利用元电路中的取反处理，高效可靠地实现对第二校验数据的错误注入，而不必专门计算一个错误值以作为错误注入后的第二校验数据，之后，通过比较模块35，能够高效可靠地实现相应校验数据的比较和相应校验结果信号的生成，以便基于生成的校验结果信号，实现对安全保护电路3和被保护电路1的故障诊断。
需要说明的是，被保护电路1中的已存储数据可以进行更新，例如，CPU可以通过数据总线对已存储数据进行更新；再例如，被保护电路1可以通过硬件自身电路对已存储数据进行更新。在被保护电路1中的已存储数据进行更新的情况下，存储器315中存储的第二校验数据也需要随之进行更新。
可选地，如图3所示，存储器315还可以具有第十三端口P13，第十三端口P13可以与一特定电路电连接，该特定电路可以根据数据总线上传输的信号和/或图3中涉及的一些信号，生成控制判断逻辑，控制判断逻辑可以用于对存储器315中存储的第二校验数据的更新条件进行控制。
在一个可选示例中，如图4所示，安全保护电路3和被保护电路1的数量均为多个，多个安全保护电路3与多个被保护电路1对应电连接；如图5所示，诊断模块5包括：第一逻辑门51、第二逻辑门53和第二多路复用器55；
第一逻辑门51和第二逻辑门53均分别与每个安全保护电路3电连接，第一逻辑门51和第二逻辑门53还均与第二多路复用器55电连接；
在故障诊断电路处于第一工作模式的情况下，第二多路复用器55用于输出第一逻辑门51对多个安全保护电路3生成的多个第二校验结果信号进行第一逻辑运算得到的第一运算结果信号，第一运算结果信号用于表征多个被保护电路1中是否存在出现故障的被保护电路1；
在故障诊断电路处于第二工作模式的情况下，第二多路复用器55用于输出第二逻辑门53对多个安全保护电路3生成的多个第一校验结果信号进行第二逻辑运算得到的第二运算结果信号，第二运算结果信号用于表征多个安全保护电路3中是否存在出现故障的安全保护电路3。
这里，安全保护电路3和被保护电路1的数量均可以多个(例如n个)，n可以为2、3、4、5或者大于5的整数，多个安全保护电路3与多个被保护电路1可以一一对应地电连接。
这里，第一逻辑门51可以为或门，第一逻辑运算可以为或运算，第二逻辑门53可以为与门，第二逻辑运算可以为与运算；或者，第一逻辑门51可以为与门，第一逻辑运算可以为与运算，第二逻辑门53可以为或门，第二逻辑运算可以为或运算。
这里，第一逻辑门51可以具有第十四端口P14，第二逻辑门53可以具有第十五端口P15，第二多路复用器55可以具有第十六端口P16、第十七端口P17和第十八端口P18，第十六端口P16可以与第十四端口P14电连接，第十七端口P17可以与第十五端口P15电连接。
需要说明的是，第十四端口P14可以作为第一逻辑门51的输出端，第十五端口P15可以作为第二逻辑门53的输出端，第十六端口P16和第十七端口P17分别作为第二多路复用器55的一个输入端，第十八端口P18作为第二多路复用器55的输出端。
在故障诊断电路处于第一工作模式的情况下，多个安全保护电路3均可以输出自身生成的第二校验结果信号，第一逻辑门51可以通过多个输入端接收多个第二校验结果信号(相当于第一工作模式下，图4、图5中的Parity 1 error至Parity n error)，并对接收到的多个第二校验结果信号进行第一逻辑运算，以得 到第一运算结果信号(相当于第一工作模式下，图4、图5中的Parity error)，并从第十四端口P14输出第一运算结果信号。
进一步地，第二多路复用器55可以从第十六端口P16接收来自第一逻辑门51的第一运算结果信号，并从第十八端口P18输出接收到的第一运算结果信号，基于第一运算结果信号，相关人员能够获知多个被保护电路1中是否存在出现故障的被保护电路1。
在一个具体例子中，每个安全保护电路3中均设置有图3所示的第二非门37，则理论上来说，如果多个被保护电路1均不存在故障，第一工作模式下，图4、图5中的Parity 1 error至Parity n error均可以表示为“0”；否则，第一工作模式下，图4、图5中的Parity 1 error至Parity n error中的至少部分可以表示为“1”。
由此可以确定，如果第一逻辑门51为或门，则在第一工作模式下的Parity error表示为“0”的情况下，可以认为多个被保护电路1不存在出现故障的被保护电路1；而在第一工作模式下的Parity error表示为“1”的情况下，可以认为多个被保护电路1中存在出现故障的被保护电路1。
在故障诊断电路处于第二工作模式的情况下，多个安全保护电路3均可以输出自身生成的第一校验结果信号，第二逻辑门53可以通过多个输入端接收多个第一校验结果信号(相当于第二工作模式下，图4、图5中的Parity 1 error至Parity n error)，对接收到的多个第一校验结果信号进行第二逻辑运算，以得到第二运算结果信号(相当于第二工作模式下，图4、图5中的Parity error)，并从第十五端口P15输出第二运算结果信号。
进一步地，第二多路复用器55可以从第十七端口P17接收来自第二逻辑门53的第二运算结果信号，并从第十八端口P18输出接收到的第二运算结果信号，基于第二运算结果信号，相关人员能够获知多个安全保护电路3中是否存在出现故障的安全保护电路3。
在一个具体例子中，每个安全保护电路3中均设置有图3所示的第二非门37，则理论上来说，如果多个安全保护电路3均不存在故障，第二工作模式下，图4、图5中的Parity 1 error至Parity n error均可以表示为“1”；否则，第二工作模式下，图4、图5中的Parity 1 error至Parity n error均可以表示为“0”。
由此可以确定，如果第二逻辑门53为与门，则在第二工作模式下的Parity error表示为“1”的情况下，可以认为故障诊断电路中的多个安全保护电路3中不存在出现故障的安全保护电路3；而在第二工作模式下的Parity error表示为“0”的情况下，可以认为故障诊断电路中的多个安全保护电路3中存在出现故障的安全保护电路3。
可选地，与上文中的第一多路复用器313类似，第二多路复用器55也可以接收diagnose信号，基于所接收的diagnose信号，第二多路复用器55可以确定故障诊断电路当前处于第一工作模式还是第二工作模式。
本公开的实施例中，通过包括第一逻辑门51、第二逻辑门53和第二多路复用器55的诊断模块5的设置，基于第一逻辑门51处的逻辑运算，能够非常高效可靠地诊断出多个被保护电路1是否存在出现故障的被保护电路1；基于第二逻辑门53处的逻辑运算，能够非常高效可靠地诊断出多个安全保护电路3是否存在出现故障的安全保护电路3。也即，本公开的实施例中，诊断模块5能够实现对被保护电路1的批量故障诊断以及对安全保护电路3的批量故障诊断。
在一个可选示例中，如图4所示，安全保护电路3和被保护电路1的数量均为多个，多个安全保护电路3与多个被保护电路1对应电连接；如图5所示，诊断模块5包括：故障定位电路57；
故障定位电路57分别与每个安全保护电路3电连接；
在故障诊断电路处于第一工作模式的情况下，故障定位电路57用于基于多个安全保护电路3生成的多个第二校验结果信号，输出用于指示多个被保护电路1中出现故障的被保护电路1的第一指示信号；
在故障诊断电路处于第二工作模式的情况下，故障定位电路57用于基于多个安全保护电路3生成的多个第一校验结果信号，输出用于指示多个安全保护电路3中出现故障的安全保护电路3的第二指示信号。
这里，安全保护电路3和被保护电路1的数量均可以多个(例如n个)，n可以为2、3、4、5或者大于5的整数，多个安全保护电路3与多个被保护电路1可以一一对应地电连接。
这里，故障定位电路57可以具有第十九端口P19和第二十端口P20，第十九端口P19和第二十端口P20可以分别作为故障定位电路57的一输出端。
在故障诊断电路处于第一工作模式的情况下，故障定位电路57可以按照设定顺序，对多个安全保护电路3生成的多个第二校验结果信号(相当于第一工作模式下，图4、图5中的Parity 1 error至Parity n error)进行扫描，例如按照error号从低到高或者从高到低的顺序进行扫描，以确定多个被保护电路1中出现故障的被保护电路1，并据此从第十九端口P19输出第一指示信号(相当于图4、图5中的function error number)。
在一个具体例子中，每个安全保护电路3中均设置有图3所示的第二非门37，则理论上来说，如果多个被保护电路1均不存在故障，第一工作模式下，图4、图5中的Parity 1 error至Parity n error均可以表示为“0”；否则，第一工作模式下，图4、图5中的Parity 1 error至Parity n error中，与存在故障的被保护电路1对应的error表示为“1”。
有鉴于此，如果第一工作模式下，图4、图5中的Parity 1 error至Parity n error均表示为“0”，function error number可以为作为默认值的“0”，相关人员据此能够获知多个被保护电路1均不存在故障；如果第一工作模式下，图4、图5中的Parity 2 error表示为“1”，function error number可以为“2”，相关人员据此能够获知与Parity 2 error对应的被保护电路1存在故障。如果第一工作模式下，图4、图5中的Parity 1 error和Parity 2 error均表示为“1”，function error number可以为“1”，相关人员据此能够获知与Parity 1error对应的被保护电路1存在故障，或者，function error number可以为“2”，相关人员据此能够获知与Parity 2 error对应的被保护电路1存在故障，也即，在存在故障的被保护电路1的数量为至少1个时，function error number可以仅指示所对应error号最高或者最低的被保护电路1。
在故障诊断电路处于第二工作模式的情况下，故障定位电路57可以按照设定顺序，对多个安全保护电路3生成的多个第一校验结果信号(相当于第二工作模式下，图4、图5中的Parity 1 error至Parity n error)进行扫描，例如按照error号从低到高或者从高到低的顺序进行扫描，以确定多个安全保护电路3中出现故障的安全保护电路3，从据此从第二十端口P20输出第二指示信号(相当于图4、图5中的diagnose error number)。
在一个具体例子中，每个安全保护电路3中均设置有图3所示的第二非门37，则理论上来说，如果多个安全保护电路3均不存在故障，第二工作模式下，图4、图5中的Parity 1 error至Parity n error均可以表示为“1”；否则，第二工作模式下，图4、图5中的Parity 1 error至Parity n error中，与存在故障的安全保护电路3对应的error表示为“0”。
有鉴于此，如果第二工作模式下，图4、图5中的Parity 1 error至Parity n error均表示为“1”，diagnose error number可以为作为默认值的“0”，相关人员据此能够获知多个安全保护电路3均不存在故障；如果第二工作模式下，图4、图5中的Parity 1 error表示为“0”，diagnose error number可以为“1”，相关人员据此能够获知与Parity 1 error对应的安全保护电路3存在故障。如果第二工作模式下，图4、图5中的Parity 1 error和Parity 2 error均表示为“0”，diagnose error number可以为“1”，相关人员据此能够获知与Parity1error对应的安全保护电路3存在故障，或者，diagnose error number可以为“2”，相关人员据此能够获知与Parity 2 error对应的安全保护电路3存在故障，也即，在存在故障的安全保护电路3的数量为至少一个时，diagnose error number可以仅指示所对应error号最高或者最低的安全保护电路3。
本公开的实施例中，通过故障定位电路57的设置，能够汇总和定位所有被保护电路1的错误以及安 全保护电路3的错误，具体而言，故障定位电路57可以在第一工作模式下进行第一指示信号的输出，以准确指示出现故障的被保护电路1的位置，并在第二工作模式下进行第二指示信号的输出，以准确指示出现故障的安全保护电路3的位置。
在一个可选示例中，如图6所示，故障诊断电路首先置于正常工作模式，在上电初始化之后，可以通过软件使能错误注入功能，使故障诊断电路置于错误注入模式，接下来看在错误注入模式下是否能够检测到错误(相当于检测第二工作模式下，图4、图5中的Parity 1 error至Parity n error是否均表示为“1”)。如果在错误注入模式下能够检测到错误(相当于第二工作模式下，图4、图5中的Parity 1 error至Parity n error均表示为“1”的情况)，可以认为测试成功，图4中的各安全保护电路3均没有潜在故障。那么，可以关闭错误注入功能并切换回正常工作模式。
如果在错误注入模式下无法检测到错误(相当于第二工作模式下，图4、图5中的Parity 1 error至Parity n error中的至少部分error不表示为“1”的情况)，可以对错误进行定位(相当于确定出现故障的具体是哪些安全保护电路3)，并进行错误处理。例如，重新向图4中的各被保护电路1中写入已存储数据，或者重启(Intellectual Property，IP)模块等；其中，IP模块是指能够实现一定功能的模块。
综上，采用本公开的实施例提供的故障诊断电路，可以在正常工作模式下，批量诊断所有被保护电路1，如果有被保护电路1出现故障，准确指示出现故障的被保护电路1位置，在错误注入模式下，基于上文中的第一非门311可以批量进行取反处理，而不必分开注错，大大提高了注错效率，软件只需单次操作即可批量诊断所有安全保护电路3，如果有安全保护电路3出现故障，准确指示出现故障的安全保护电路3位置。
示例性方法
图7是本公开一示例性实施例提供的故障诊断方法的流程示意图。图7所示的方法应用于上文中的故障诊断电路，图7所示的方法包括步骤701、步骤702、步骤703和步骤704。
步骤701，对被保护电路中的已存储数据进行校验运算，以得到第一校验数据；
步骤702，对已存储数据对应的第二校验数据进行错误注入；
步骤703，基于第一校验数据和错误注入后的第二校验数据，生成第一校验结果信号；
步骤704，基于第一校验结果信号，对故障诊断电路中的安全保护电路进行故障诊断。
在一个可选示例中，如图8所示，故障诊断方法还包括：
步骤711，基于第一校验数据和第二校验数据，生成第二校验结果信号；
步骤712，基于第二校验结果信号，对被保护电路进行故障诊断。
本公开实施例提供的任一种故障诊断方法可以由任意适当的具有数据处理能力的设备执行，包括但不限于：终端设备和服务器等。或者，本公开实施例提供的任一种故障诊断方法可以由处理器执行，如处理器通过调用存储器存储的相应指令来执行本公开实施例提及的任一种故障诊断方法。下文不再赘述。
示例性装置
图9是本公开一示例性实施例提供的故障诊断装置的结构示意图。图9所示的装置包括第一处理模块901、第二处理模块902、第一生成模块903和第三处理模块904。
第一处理模块901，用于对被保护电路中的已存储数据进行校验运算，以得到第一校验数据；
第二处理模块902，用于对已存储数据对应的第二校验数据进行错误注入；
第一生成模块903，用于基于第一处理模块901得到的第一校验数据和第二处理模块902得到的错误注入后的第二校验数据，生成第一校验结果信号；
第三处理模块904，用于基于第一生成模块903生成的第一校验结果信号，对故障诊断电路中的安全保护电路进行故障诊断。
在一个可选示例中，如图10所示，故障诊断装置还包括：
第二生成模块911，用于基于第一处理模块901得到的第一校验数据和第二校验数据，生成第二校验结果信号；
第四处理模块912，用于基于第二生成模块911生成的第二校验结果信号，对被保护电路进行故障诊断。
示例性电子设备
下面，参考图11来描述根据本公开实施例的电子设备。该电子设备可以是第一设备和第二设备中的任一个或两者、或与它们独立的单机设备，该单机设备可以与第一设备和第二设备进行通信，以从它们接收所采集到的输入信号。
图11图示了根据本公开实施例的电子设备的框图。
如图11所示，电子设备1100包括一个或多个处理器1101和存储器1102。
处理器1101可以是CPU或者具有数据处理能力和/或指令执行能力的其他形式的处理单元，并且可以控制电子设备1100中的其他组件以执行期望的功能。
存储器1102可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。所述易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。所述非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在所述计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器1101可以运行所述程序指令，以实现上文所述的本公开的各个实施例的故障诊断方法以及/或者其他期望的功能。在所述计算机可读存储介质中还可以存储诸如输入信号、信号分量、噪声分量等各种内容。
在一个示例中，电子设备1100还可以包括：输入装置1103和输出装置1104，这些组件通过总线系统和/或其他形式的连接机构(未示出)互连。
例如，在该电子设备是第一设备或第二设备时，该输入装置1103可以是麦克风或麦克风阵列。在该电子设备是单机设备时，该输入装置13可以是通信网络连接器，用于从第一设备和第二设备接收所采集的输入信号。
此外，该输入装置1103还可以包括例如键盘、鼠标等等。
该输出装置1104可以向外部输出各种信息，包括确定出的距离信息、方向信息等。该输出装置1104可以包括例如显示器、扬声器、打印机、以及通信网络及其所连接的远程输出设备等等。
当然，为了简化，图11中仅示出了该电子设备1100中与本公开有关的组件中的一些，省略了诸如总线、输入/输出接口等等的组件。除此之外，根据具体应用情况，电子设备1100还可以包括任何其他适当的组件。
示例性计算机程序产品和计算机可读存储介质
除了上述方法和设备以外，本公开的实施例还可以是计算机程序产品，其包括计算机程序指令，所述计算机程序指令在被处理器运行时使得所述处理器执行本说明书上述“示例性方法”部分中描述的根据本公开各种实施例的故障诊断方法中的步骤。
以上结合具体实施例描述了本公开的基本原理，但是，需要指出的是，在本公开中提及的优点、优势、效果等仅是示例而非限制，不能认为这些优点、优势、效果等是本公开的各个实施例必须具备的。另外，上述公开的具体细节仅是为了示例的作用和便于理解的作用，而非限制，上述细节并不限制本公开为必须采用上述具体的细节来实现。
本说明书中各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似的部分相互参见即可。对于系统实施例而言，由于其与方法实施例基本对应， 所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
本公开中涉及的器件、装置、设备、系统的方框图仅作为例示性的例子并且不意图要求或暗示必须按照方框图示出的方式进行连接、布置、配置。如本领域技术人员将认识到的，可以按任意方式连接、布置、配置这些器件、装置、设备、系统。
可能以许多方式来实现本公开的方法和装置。例如，可通过软件、硬件、固件或者软件、硬件、固件的任何组合来实现本公开的方法和装置。用于所述方法的步骤的上述顺序仅是为了进行说明，本公开的方法的步骤不限于以上具体描述的顺序，除非以其它方式特别说明。此外，在一些实施例中，还可将本公开实施为记录在记录介质中的程序，这些程序包括用于实现根据本公开的方法的机器可读指令。因而，本公开还覆盖存储用于执行根据本公开的方法的程序的记录介质。
还需要指出的是，在本公开的装置、设备和方法中，各部件或各步骤是可以分解和/或重新组合的。这些分解和/或重新组合应视为本公开的等效方案。
提供所公开的方面的以上描述以使本领域的任何技术人员能够做出或者使用本公开。对这些方面的各种修改对于本领域技术人员而言是非常显而易见的，并且在此定义的一般原理可以应用于其他方面而不脱离本公开的范围。因此，本公开不意图被限制到在此示出的方面，而是按照与在此公开的原理和新颖的特征一致的最宽范围。

Claims (12)

  1. 一种故障诊断电路，包括：安全保护电路和诊断模块；
    所述安全保护电路与被保护电路电连接，用于对所述被保护电路中的已存储数据进行校验运算，以得到第一校验数据，对所述已存储数据对应的第二校验数据进行错误注入，且基于所述第一校验数据和所述错误注入后的第二校验数据，生成第一校验结果信号；
    所述诊断模块与所述安全保护电路电连接，所述诊断模块用于基于所述第一校验结果信号，对所述安全保护电路进行故障诊断。
  2. 根据权利要求1所述的故障诊断电路，其中，
    所述安全保护电路还用于基于所述第一校验数据和所述第二校验数据，生成第二校验结果信号；
    所述诊断模块还用于基于所述第二校验结果信号，对所述被保护电路进行故障诊断。
  3. 根据权利要求2所述的故障诊断电路，其中，所述安全保护电路包括：处理模块、计算模块和比较模块；
    所述比较模块分别与所述处理模块、所述计算模块、所述诊断模块电连接，所述计算模块还与所述被保护电路电连接；
    所述计算模块用于对所述已存储数据进行校验运算，以得到所述第一校验数据；
    所述处理模块用于对所述第二校验数据进行错误注入；
    所述比较模块用于基于所述第一校验数据和所述错误注入后的第二校验数据的比较结果，生成第三校验结果信号，所述第一校验结果信号基于所述第三校验结果信号生成；
    所述比较模块还用于基于所述第一校验数据和所述第二校验数据的比较结果，生成第四校验结果信号，所述第二校验结果信号基于所述第四校验结果信号生成。
  4. 根据权利要求3所述的故障诊断电路，其中，所述处理模块包括：第一非门、第一多路复用器和存储器；
    所述第一多路复用器与所述存储器电连接，所述存储器还通过所述第一非门与所述第一多路复用器电连接，所述第一多路复用器还与数据总线电连接，所述存储器还与所述比较模块电连接；
    在所述故障诊断电路处于第一工作模式的情况下，所述第一多路复用器用于输出基于所述数据总线获取的所述第二校验数据，以使所述存储器存储所述第二校验数据并输出所述第二校验数据至所述比较模块；
    在所述故障诊断电路处于第二工作模式的情况下，所述第一多路复用器用于输出所述第一非门对所述存储器存储的所述第二校验数据的取反结果，以使所述存储器输出所述第二校验数据的取反结果至所述比较模块，所述第二校验数据的取反结果作为所述错误注入后的第二校验数据。
  5. 根据权利要求4所述的故障诊断电路，其中，所述安全保护电路还包括：第二非门；
    所述比较模块通过所述第二非门与所述诊断模块电连接，所述第二非门对所述第三校验结果信号的取反结果作为所述第一校验结果信号，所述第二非门对所述第四校验结果信号的取反结果作为所述第二校验结果信号。
  6. 根据权利要求2所述的故障诊断电路，其中，所述安全保护电路和所述被保护电路的数量均为多个，多个所述安全保护电路与多个所述被保护电路对应电连接；所述诊断模块包括：第一逻辑门、第二逻辑门和第二多路复用器；
    所述第一逻辑门和所述第二逻辑门均分别与每个所述安全保护电路电连接，所述第一逻辑门和所述第二逻辑门还均与所述第二多路复用器电连接；
    在所述故障诊断电路处于第一工作模式的情况下，所述第二多路复用器用于输出所述第一逻辑门对多个所述安全保护电路生成的多个所述第二校验结果信号进行第一逻辑运算得到的第一运算结果信号，所述第一运算结果信号用于表征多个所述被保护电路中是否存在出现故障的所述被保护电路；
    在所述故障诊断电路处于第二工作模式的情况下，所述第二多路复用器用于输出所述第二逻辑门对多个所述安全保护电路生成的多个所述第一校验结果信号进行第二逻辑运算得到的第二运算结果信号，所述第二运算结果信号用于表征多个所述安全保护电路中是否存在出现故障的所述安全保护电路。
  7. 根据权利要求2所述的故障诊断电路，其中，所述安全保护电路和所述被保护电路的数量均为多个，多个所述安全保护电路与多个所述被保护电路对应电连接；所述诊断模块包括：故障定位电路；
    所述故障定位电路分别与每个所述安全保护电路电连接；
    在所述故障诊断电路处于第一工作模式的情况下，所述故障定位电路用于基于多个所述安全保护电路生成的多个所述第二校验结果信号，输出用于指示所述多个所述被保护电路中出现故障的所述被保护电路的第一指示信号；
    在所述故障诊断电路处于第二工作模式的情况下，所述故障定位电路用于基于多个所述安全保护电路生成的多个所述第一校验结果信号，输出用于指示多个所述安全保护电路中出现故障的所述安全保护电路的第二指示信号。
  8. 一种故障诊断方法，应用于如权利要求1-7中任一所述的故障诊断电路中，所述故障诊断方法包括：
    对被保护电路中的已存储数据进行校验运算，以得到第一校验数据；
    对所述已存储数据对应的第二校验数据进行错误注入；
    基于所述第一校验数据和所述错误注入后的第二校验数据，生成第一校验结果信号；
    基于所述第一校验结果信号，对所述故障诊断电路中的安全保护电路进行故障诊断。
  9. 根据权利要求8所述的故障诊断方法，还包括：
    基于所述第一校验数据和所述第二校验数据，生成第二校验结果信号；
    基于所述第二校验结果信号，对所述被保护电路进行故障诊断。
  10. 一种故障诊断装置，应用于如权利要求1-7中任一所述的故障诊断电路中，所述故障诊断装置包括：
    第一处理模块，用于对被保护电路中的已存储数据进行校验运算，以得到第一校验数据；
    第二处理模块，用于对所述已存储数据对应的第二校验数据进行错误注入；
    第一生成模块，用于基于所述第一处理模块得到的所述第一校验数据和所述第二处理模块得到的所述错误注入后的第二校验数据，生成第一校验结果信号；
    第三处理模块，用于基于所述第一生成模块生成的所述第一校验结果信号，对所述故障诊断电路中的安全保护电路进行故障诊断。
  11. 一种计算机可读存储介质，所述存储介质存储有计算机程序，所述计算机程序用于执行上述权利要求8或9所述的故障诊断方法。
  12. 一种电子设备，包括：
    处理器；
    用于存储所述处理器可执行指令的存储器；
    所述处理器，用于从所述存储器中读取所述可执行指令，并执行所述指令以实现上述权利要求8或9所述的故障诊断方法。
PCT/CN2022/113373 2021-08-20 2022-08-18 故障诊断电路、方法、装置及计算机可读存储介质 WO2023020586A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2023542630A JP2024503675A (ja) 2021-08-20 2022-08-18 故障診断回路、方法、装置およびコンピュータ可読記憶媒体
EP22857895.1A EP4270198A1 (en) 2021-08-20 2022-08-18 Fault diagnosis circuit, method and apparatus, and computer-readable storage medium
US18/261,435 US20240069098A1 (en) 2021-08-20 2022-08-18 Fault diagnosis circuit, method, and apparatus, and computer readable storage medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110958241.7 2021-08-20
CN202110958241.7A CN113656230B (zh) 2021-08-20 2021-08-20 故障诊断电路、方法、装置及计算机可读存储介质

Publications (1)

Publication Number Publication Date
WO2023020586A1 true WO2023020586A1 (zh) 2023-02-23

Family

ID=78481504

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/113373 WO2023020586A1 (zh) 2021-08-20 2022-08-18 故障诊断电路、方法、装置及计算机可读存储介质

Country Status (5)

Country Link
US (1) US20240069098A1 (zh)
EP (1) EP4270198A1 (zh)
JP (1) JP2024503675A (zh)
CN (1) CN113656230B (zh)
WO (1) WO2023020586A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113656230B (zh) * 2021-08-20 2023-06-16 地平线(上海)人工智能技术有限公司 故障诊断电路、方法、装置及计算机可读存储介质
CN115202921B (zh) * 2022-09-16 2022-11-25 北京紫光芯能科技有限公司 一种故障诊断信号指示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108600047A (zh) * 2018-04-04 2018-09-28 天津芯海创科技有限公司 串行传输芯片及serdes电路测试方法
US20190227867A1 (en) * 2018-01-24 2019-07-25 Synopsys, Inc. Method and apparatus of using parity to detect random faults in memory mapped configuration registers
CN111624477A (zh) * 2020-05-31 2020-09-04 西南电子技术研究所（中国电子科技集团公司第十研究所） 智能诊断高集成数字信号处理系统故障的测试系统
CN113295943A (zh) * 2021-04-30 2021-08-24 地平线征程(杭州)人工智能科技有限公司 待测试模块的测试电路、方法及装置
CN113656230A (zh) * 2021-08-20 2021-11-16 地平线(上海)人工智能技术有限公司 故障诊断电路、方法、装置及计算机可读存储介质

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4485467A (en) * 1982-02-18 1984-11-27 Teknekron Infoswitch Corporation Digital information switch matrix with on-line/off-line diagnostic features
JP3274332B2 (ja) * 1995-11-29 2002-04-15 株式会社東芝 コントローラ・大容量メモリ混載型半導体集積回路装置およびそのテスト方法およびその使用方法、並びに半導体集積回路装置およびそのテスト方法
FR2867326A1 (fr) * 2004-03-02 2005-09-09 St Microelectronics Sa Dispositif de protection contre l'injection d'erreur dans une bascule synchrone d'un module logique elementaire
CN108073837B (zh) * 2016-11-15 2021-08-20 华为技术有限公司 一种总线安全保护方法及装置
CN112948167B (zh) * 2021-03-31 2022-10-18 地平线征程(杭州)人工智能科技有限公司 数据通路的保护电路、方法、装置及计算机可读存储介质

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190227867A1 (en) * 2018-01-24 2019-07-25 Synopsys, Inc. Method and apparatus of using parity to detect random faults in memory mapped configuration registers
CN108600047A (zh) * 2018-04-04 2018-09-28 天津芯海创科技有限公司 串行传输芯片及serdes电路测试方法
CN111624477A (zh) * 2020-05-31 2020-09-04 西南电子技术研究所（中国电子科技集团公司第十研究所） 智能诊断高集成数字信号处理系统故障的测试系统
CN113295943A (zh) * 2021-04-30 2021-08-24 地平线征程(杭州)人工智能科技有限公司 待测试模块的测试电路、方法及装置
CN113656230A (zh) * 2021-08-20 2021-11-16 地平线(上海)人工智能技术有限公司 故障诊断电路、方法、装置及计算机可读存储介质

Also Published As

Publication number Publication date
JP2024503675A (ja) 2024-01-26
US20240069098A1 (en) 2024-02-29
EP4270198A1 (en) 2023-11-01
CN113656230A (zh) 2021-11-16
CN113656230B (zh) 2023-06-16

Similar Documents

Publication Publication Date Title
WO2023020586A1 (zh) 故障诊断电路、方法、装置及计算机可读存储介质
US11088782B2 (en) Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection
US6886116B1 (en) Data storage system adapted to validate error detection logic used in such system
EP1224548B1 (en) System and method improving fault isolation and diagnosis in computers
US20130198571A1 (en) System and Method of Computation by Signature Analysis
US10419035B2 (en) Use of multiple cyclic redundancy codes for optimized fail isolation
US8644136B2 (en) Sideband error signaling
US11663100B2 (en) Serial interface with improved diagnostic coverage
CN111414268A (zh) 故障处理方法、装置及服务器
US20140143597A1 (en) Computer system and operating method thereof
CN111858222A (zh) 错误注入的方法、设备、数据存储系统和程序产品
US9299456B2 (en) Matrix and compression-based error detection
CN116501536A (zh) Axi互连模块检查、校验与保护方法、装置及存储介质
US11940888B2 (en) Technology to provide fault tolerance for elliptic curve digital signature algorithm engines
US10846162B2 (en) Secure forking of error telemetry data to independent processing units
JP6217086B2 (ja) 情報処理装置、エラー検出機能診断方法およびコンピュータプログラム
WO2018010084A1 (zh) 应用于数字集成电路的esd检测装置、集成电路及方法
CN111367838A (zh) 用于检测数据存储系统的方法、设备和数据存储系统
US11500717B2 (en) Method for detecting data storage system, device and data storage system
US20240134743A1 (en) Electronic device, electronic system, method for operating an electronic device, and method for operating an electronic system
US9230290B2 (en) Power meter consumption system and method to verify data stored in a register by comparing an address of the register with request for data of the register
US5418794A (en) Error determination scan tree apparatus and method
CN116320379A (zh) 车辆摄像头的状态监测方法、装置、计算机设备及存储介质
CN117711475A (zh) 存储单元的故障检测电路及方法、功能芯片
Beauregard et al. Error-injection-based failure characterization of the IEEE 1394 bus

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22857895

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2023542630

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 18261435

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2022857895

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2022857895

Country of ref document: EP

Effective date: 20230727

NENP Non-entry into the national phase

Ref country code: DE