WO2023020487A1 - 量子程序与量子芯片的映射方法和量子操作系统及计算机 - Google Patents

量子程序与量子芯片的映射方法和量子操作系统及计算机 Download PDF

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WO2023020487A1
WO2023020487A1 PCT/CN2022/112765 CN2022112765W WO2023020487A1 WO 2023020487 A1 WO2023020487 A1 WO 2023020487A1 CN 2022112765 W CN2022112765 W CN 2022112765W WO 2023020487 A1 WO2023020487 A1 WO 2023020487A1
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quantum
mapping relationship
program
logic gate
mapping
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PCT/CN2022/112765
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English (en)
French (fr)
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窦猛汉
赵东一
方圆
汪文涛
王晶
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合肥本源量子计算科技有限责任公司
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Priority claimed from CN202110941261.3A external-priority patent/CN115907024A/zh
Priority claimed from CN202110941255.8A external-priority patent/CN115907023A/zh
Application filed by 合肥本源量子计算科技有限责任公司 filed Critical 合肥本源量子计算科技有限责任公司
Publication of WO2023020487A1 publication Critical patent/WO2023020487A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena

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  • the present application belongs to the technical field of quantum program compilation, in particular to a quantum program-to-quantum chip mapping method, a quantum program-to-quantum chip mapping device, a storage medium, an electronic device, a quantum operating system, and a quantum computer.
  • Quantum computer is a kind of physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information. When a device processes and computes quantum information and runs quantum algorithms, it is a quantum computer. Quantum computer has become a key technology under research because of its ability to deal with mathematical problems more efficiently than ordinary computers, for example, it can speed up the time to crack RSA keys from hundreds of years to hours.
  • each quantum chip has its own specific topology, which reflects the connection relationship between the qubits supported by the quantum chip.
  • the two-qubit logic gates implemented on two adjacent qubits may be limited by the chip structure.
  • the gate cannot be fitted by two qubits to form a two-qubit logic gate. Therefore, it is necessary to exchange and convert any two-qubit logic gate until it is converted into a quantum logic gate supported by the chip, so as to improve the utilization rate of the computing resource of the quantum chip.
  • An object of the embodiments is to provide a mapping scheme between a quantum program and a quantum chip, so as to improve the resource utilization rate of the entire quantum chip.
  • One embodiment provides a mapping method between a quantum program and a quantum chip, the method comprising: obtaining the topology of the physical bits in the quantum chip, the set of logic gates of the initial quantum program, and the initial mapping relationship between the logical bits and the physical bits; determining The execution timing of the logic gate set of the initial quantum program; according to the topology of the physical bits and the initial mapping relationship, adjust the mapping relationship between the logical bits and the physical bits corresponding to each logic gate according to the execution timing to obtain the final mapping relationship; according to the final mapping relationship, construct a quantum program to be mapped that is equivalent to the initial quantum program, so that the number of SWAP quantum logic gates in the quantum program to be mapped is the least.
  • Another embodiment provides a mapping device of a quantum program and a quantum chip, the device comprising: an acquisition module for acquiring the topology of the physical bits in the quantum chip, the set of logic gates of the initial quantum program, and the logic bits and physical bits The initial mapping relationship; the determination module is used to determine the execution timing of the logic gate set of the initial quantum program; the adjustment module is used to adjust each according to the execution timing according to the topology of the physical bits and the initial mapping relationship The mapping relationship between the logical bit and the physical bit corresponding to the logic gate is obtained to obtain the final mapping relationship; the building block is used to construct the quantum program to be mapped equivalent to the initial quantum program according to the final mapping relationship, so that the quantum program to be mapped The number of SWAP quantum logic gates in .
  • Another embodiment provides a mapping method between a quantum program and a quantum chip, the method comprising: obtaining a directed acyclic graph of the quantum program to be executed and the initial mapping relationship between logical bits and physical bits;
  • the directed acyclic graph of the program determines the execution order of the set of logic gates to be mapped in the quantum program to be executed; according to the execution order and the initial mapping relationship, determine each logic in the set of logic gates to be mapped
  • the gate is mapped to the cost of the quantum chip topology; according to the cost of each logic gate mapped to the quantum chip topology, the target mapping of the quantum program to be executed is adjusted to make the cost of the target mapping the lowest.
  • Another embodiment provides a quantum program and quantum chip mapping device, the device includes: an acquisition module, used to acquire the directed acyclic graph of the quantum program to be executed and the initial mapping relationship between logical bits and physical bits; A determination module, used to determine the execution order of the set of logic gates to be mapped in the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed; a second determination module, used to determine the execution order according to the execution order and The initial mapping relationship determines the cost of each logic gate in the set of logic gates to be mapped to the quantum chip topology; the adjustment module is used to map each logic gate to the quantum chip topology according to the cost, The target mapping of the quantum program to be executed is adjusted so that the cost of the target mapping is the lowest.
  • Yet another embodiment provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute the method described in any one of the above when running.
  • Yet another embodiment provides an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to perform the method described in any one of the above.
  • Another embodiment of the present application provides a quantum computer operating system, which implements the mapping between quantum programs and quantum chips according to any of the methods described above.
  • Another embodiment of the present application provides a quantum computer, which includes the quantum computer operating system.
  • At least the impact on the operation of the entire quantum circuit due to the addition of the SWAP gate can be alleviated, thereby improving the resource utilization rate of the entire quantum chip.
  • At least the problem that a single physical bit factor affects the entire quantum circuit can be alleviated. Furthermore, optimal mapping lines for the quantum chip topology can be determined. In addition, the resource utilization of the entire quantum chip can be maximized.
  • Fig. 1 is the block diagram of the hardware structure of the computer terminal provided by the embodiment
  • Fig. 2 is a schematic flow chart of a mapping method between a quantum program and a quantum chip provided by an embodiment
  • Fig. 3 is the schematic diagram of the topological structure of a kind of quantum chip physical bit that the embodiment provides;
  • FIG. 4 is a schematic diagram of a quantum circuit corresponding to an initial quantum program in an embodiment
  • Figure 5 is a schematic diagram of a quantum program to be mapped that is equivalent to the initial quantum program provided by the embodiment
  • Fig. 6 is a schematic structural diagram of a quantum program and quantum chip mapping device provided by the embodiment.
  • Fig. 7 is a schematic flow chart of a quantum program and quantum chip mapping method provided by the embodiment.
  • Fig. 8 is a schematic diagram of a quantum circuit to be executed provided by the embodiment.
  • FIG. 9 is a schematic diagram of a directed acyclic graph corresponding to a quantum circuit to be executed provided by the embodiment.
  • Fig. 10 is a schematic structural diagram of an apparatus for determining the mapping between a quantum program and a quantum chip provided by an embodiment.
  • the methods provided in the embodiments can be applied to electronic devices, such as computer terminals, specifically, ordinary computers, quantum computers, and the like.
  • Fig. 1 is a block diagram of the hardware structure of the computer terminal provided by the embodiment.
  • the computer terminal may include one or more (only one is shown in Figure 1) processors 102 (processors 102 may include but not limited to processing devices such as microprocessor MCU or programmable logic device FPGA, etc.) and a memory 104 for storing data.
  • the above-mentioned computer terminal may further include a transmission device 106 and an input and output device 108 for communication functions.
  • the structure shown in FIG. 1 is only for illustration, and it does not limit the structure of the above computer terminal.
  • the computer terminal may also include more or fewer components than shown in FIG. 1 , or have a different configuration than that shown in FIG. 1 .
  • the memory 104 can be used to store software programs and modules of application software, such as implementing a program instruction/module corresponding to a method for constructing a quantum program to be mapped in the embodiment of the present application, and the processor 102 runs the software program stored in the memory 104 And modules, so as to execute various functional applications and data processing, that is, to realize the above-mentioned method.
  • the memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • the memory 104 may further include a memory that is remotely located relative to the processor 102, and these remote memories may be connected to a computer terminal through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • the transmission device 106 is used to receive or transmit data via a network.
  • the specific example of the above-mentioned network may include a wireless network provided by the communication provider of the computer terminal.
  • the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet.
  • the transmission device 106 may be a radio frequency (Radio Frequency, RF) module, which is used to communicate with the Internet in a wireless manner.
  • RF Radio Frequency
  • a quantum program when running on a quantum chip (also called a physical chip), the state of each physical bit is unstable for multiple physical bits on the same physical chip, for example, a two-bit quantum logic gate Factors such as operating noise, measurement noise, and decoherence time of physical bits will interfere with the effective use of physical bits, thus having an unknown impact on the operation results of the entire quantum circuit.
  • a two-bit quantum logic gate Factors such as operating noise, measurement noise, and decoherence time of physical bits will interfere with the effective use of physical bits, thus having an unknown impact on the operation results of the entire quantum circuit.
  • the decoherence time of each physical bit is different, if the decoherence time of a certain physical bit is short and the quantum circuit depth that the entire quantum chip can run is limited, it will inevitably lead to the waste of other physical bit resources.
  • the unsuitable two-qubit quantum logic gates are transformed into The quantum logic gates supported by the chip.
  • the quantum program contains the CNOT(q1,q3) quantum logic gate.
  • the quantum chip supports the CNOT gate, the physical qubits q1 and q3 in the quantum chip are not directly connected, so they cannot be directly executed. Therefore, it is necessary to exchange the two quantum logic gates in the quantum program with quantum logic gates that can be directly executed by the chip.
  • the existing exchange method is briefly described as: according to the connection relationship between the qubits on the quantum chip, find the connection path between the two qubits q1 and q3 operated by CNOT , assuming that the qubits passed by the path are q1 and q2, executing CNOT(q1,q3) is equivalent to executing in sequence: SWAP(q1,q2), SWAP(q2,q3), CNOT(q2,q3), SWAP( q3, q2), SWAP (q2, q1).
  • the SWAP gate means to perform a swap operation on qubits.
  • FIG. 2 is a schematic flowchart of a mapping method between a quantum program and a quantum chip provided in an embodiment.
  • S201 Obtain the topology structure of physical bits in the quantum chip, the set of logic gates of the initial quantum program, and the initial mapping relationship between logical bits and physical bits.
  • each quantum chip has its own specific topology.
  • the topology reflects the entanglement relationship between the physical bits supported by the quantum chip.
  • the number of physical bits in the quantum chip is limited, and the chip topology is simple, usually in the form of a simple two-dimensional chain (or one-dimensional chain). For a certain physical bit in the quantum chip, it can only be connected with a limited number of physical bits. connected.
  • FIG. 3 is a schematic diagram of a topological structure of physical bits of a quantum chip provided by an embodiment.
  • the quantum chip includes 8 physical bits, namely Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7] ].
  • Physical bits can be coupled through capacitive coupling, and only adjacent physical bits have a coupling relationship. Refer to Figure 3 for specific coupling results.
  • the logic gate set of the initial quantum program is mainly composed of tens, hundreds or even tens of thousands of quantum logic gates.
  • the set of logic gates of the initial quantum program includes: a first set of regular logic gates and a second set of regular logic gates, wherein the first set of regular logic gates includes: single-bit quantum logic gates and two-bit quantum logic with adjacent logic bits gate; the second set of regular logic gates includes: two-bit quantum logic gates with non-adjacent logic bits.
  • the execution process of the initial quantum program is the process of executing all quantum logic gates according to a certain time sequence.
  • the qubit structure in the quantum chip is generally called the physical bit, and the object bit operated in the quantum circuit is called the logical bit.
  • the initial mapping relationship between logical bits and physical bits refers to the "corresponding" relationship between logical bits and physical bits.
  • S202 Determine the execution timing of the logic gate set of the initial quantum program.
  • Timing is the time sequence in which quantum logic gates are executed. Determining the execution timing of the logic gate set of the initial quantum program includes the following steps:
  • FIG. 4 is a schematic diagram of a quantum circuit corresponding to an initial quantum program in an embodiment.
  • An initial quantum program corresponding to this quantum circuit is CNOT(q[0], q[1]) ⁇ CNOT(q[2],q[4]) ⁇ CNOT(q[0],q[2]) ⁇ CNOT(q[2],q[4]) ⁇ CNOT(q[1],q[3]).
  • S2022 Traverse the quantum circuit, set the execution timing of the first set of regular logic gates in the first sequence of each qubit as the priority execution sequence, and set the execution sequence of the second set of regular logic gates in the first sequence of each qubit Timing, set as the second priority execution timing.
  • the quantum circuit shown in FIG. 4 is traversed, wherein the logic gates of the first sequence are CNOT(q[0], q[1]), CNOT(q[2], q[4]), and the logic gates of the first sequence
  • the logic gate of the second sequence is CNOT(q[0], q[2])
  • the logic gate of the third sequence is CNOT(q[2], q[4])
  • the logic gate of the fourth sequence is CNOT(q[ 1], q[3]).
  • the set of logic gates for the first time sequence of each qubit is CNOT(q[0], q[1]) and CNOT(q[2], q[4]), where CNOT(q[0], q[ 1]) conforms to the characteristics of the logic gate of the first rule, and sets its execution timing as the priority execution timing; CNOT(q[2], q[4]) conforms to the characteristics of the logic gate of the second rule, and sets its execution timing as Execution timing for the second priority.
  • delete the logic gates for which timing division is completed that is, delete CNOT(q[0], q[1]), CNOT(q[2], q[4]), at this time, the first timing
  • the logic gate of the second sequence is CNOT(q[0],q[2])
  • the logic gate of the second sequence is CNOT(q[2],q[4])
  • the logic gate of the third sequence is CNOT(q[1] , q[3])
  • continue to execute at this time set the execution timing of the first regular logic gate set of the first timing of each qubit as the priority execution timing, and set the second regular logic gate of the first timing of each qubit
  • the execution sequence of the set is set as the step of the second priority execution sequence, therefore, CNOT(q[0], q[2]), CNOT(q[2], q[4]), CNOT(q[1], q [3]) are all set as the second-priority execution sequence, and the execution sequence division is
  • the initial quantum program may include single-bit quantum logic gates, two-bit quantum logic gates and multi-bit quantum logic gates, but before determining the execution sequence of the initial quantum program logic gate set, the multi-bit quantum logic gates first need to It is transformed into a combination of single-bit quantum logic gates and two-bit quantum logic gates. Since the single-bit quantum logic gate can directly map logical bits to physical bits, the single-bit quantum logic gate obtained after conversion and the single-quantum logic gate existing in the quantum program to be executed before conversion can be deleted (or executed first), Then, based on the two-bit quantum logic gates obtained after conversion and the two-bit quantum logic gates in the initial quantum program before conversion, the execution timing of the logic gate set of the initial quantum program is determined. For the convenience of explanation, the above examples only contain An example of a quantum circuit for a two-bit quantum logic gate.
  • S203 According to the topology structure of the physical bits and the initial mapping relationship, adjust the mapping relationship between the logical bit and the physical bit corresponding to each logic gate according to the execution timing, to obtain a final mapping relationship.
  • mapping relationship traverse each logic gate forward according to the execution timing and adjust the physical bits mapped by each logic gate under the previous mapping relationship, and adjust the previous one. Mapping relationship, until the forward traversal is completed according to the execution time sequence, and the target forward mapping relationship is obtained.
  • the initial mapping relationship q[0] corresponds to Q[0], q[1] corresponds to Q[1], and q[2] corresponds to Q[2] ], q[3] corresponds to Q[3], and q[4] corresponds to Q[4].
  • mapping relationship Based on the current mapping relationship, by inserting SWAP logic gates in Q[2] and Q[3], the logical bit q[2] can be mapped to the physical bit Q[2], and the executable CNOT(q[2], q [4]) for the purpose.
  • the mapping relationship at this time is q[0]--Q[4], q[1]--Q[0], q[2]--Q[2], q[3]--Q[3], q[4]--Q[1].
  • the logic bit q[3] can be mapped to the physical Bit Q[1] also achieves the purpose of executing CNOT(q[1], q[3]).
  • the target forward mapping relationship is obtained as q[0]--Q[4], q[1]--Q[0], q[4]--Q[2], q[2]--Q[ 3], q[3]--Q[1].
  • the target forward mapping relationship traverse each logic gate in reverse according to the execution time sequence and adjust the physical bits mapped by each logic gate under the previous mapping relationship, and adjust the previous mapping relationship until according to The target reverse mapping relationship obtained after the execution sequence reverse traversal is completed is used as the final mapping relationship.
  • the target forward mapping relationship is q[0]--Q[4], q[1]--Q[0], q[4]--Q[2], q[2]--Q [3], q[3]--Q[1].
  • the previous mapping relationship that is, the current target forward mapping relationship.
  • the target reverse mapping relationship obtained after the reverse traversal of the execution time sequence is completed, namely: q[0]--Q[4], q [1]--Q[0], q[4]--Q[2], q[2]--Q[3], q[3]--Q[1], as the final mapping relationship.
  • the SWAP quantum logic gate corresponding to each logic gate generated by running each logic gate according to the execution time sequence is inserted into the corresponding position in the quantum logic gate set.
  • the quantum program obtained after the insertion is completed is determined as the quantum program to be mapped that is equivalent to the initial quantum program.
  • a corresponding SWAP quantum logic gate generated by running each logic gate according to the execution time sequence is inserted at a corresponding position in the quantum logic gate set.
  • Fig. 5 is a schematic diagram of a quantum program to be mapped that is equivalent to the initial quantum program provided by the embodiment.
  • At least the impact of adding the SWAP gate on the operation of the entire quantum circuit can be alleviated, thereby improving the resource utilization rate of the entire quantum chip.
  • Fig. 6 is a schematic structural diagram of a quantum program and quantum chip mapping device provided by the embodiment.
  • the device may include: an acquisition module 601, configured to acquire the topology of the physical bits in the quantum chip, the set of logic gates of the initial quantum program, and the initial mapping relationship between logical bits and physical bits; determine Module 602, for determining the execution timing of the logic gate set of the initial quantum program; adjustment module 603, for adjusting the execution timing corresponding to each logic gate according to the topology of the physical bits and the initial mapping relationship The mapping relationship between logical bits and physical bits is obtained to obtain the final mapping relationship; the construction module 604 is used to construct the quantum program to be mapped equivalent to the initial quantum program according to the final mapping relationship, so that the SWAP in the quantum program to be mapped Quantum logic gates have the fewest number.
  • the determination module includes: an acquisition unit, configured to acquire the quantum circuit corresponding to the initial quantum program; a traversal unit, configured to traverse the quantum circuit, and execute the first regular logic gate set of the first time sequence of each qubit
  • the timing is set as the priority execution timing
  • the execution timing of the second regular logic gate set of the first timing of each qubit is set as the second priority execution timing
  • the iteration unit is used to delete the logic gates whose execution timing division is completed, and continue to execute
  • the execution timing of the first set of regular logic gates in the first timing of each qubit is set as the priority execution timing
  • the execution timing of the second set of regular logic gates in the first timing of each qubit is set as the second priority
  • the step of executing timing until the execution timing division of the quantum circuit logic gate is completed.
  • the adjustment module includes: a first execution unit, configured to traverse each logic gate in a forward direction according to the execution timing according to the topology structure of the physical bits and the initial mapping relationship, and adjust the upper The physical bits mapped under a mapping relationship are adjusted to the previous mapping relationship until the forward traversal is completed according to the execution time sequence, and the target forward mapping relationship is obtained; the second execution unit is used for forward mapping according to the target Reversely traversing each logic gate according to the execution time sequence and adjusting the physical bits mapped by each logic gate under the previous mapping relationship, adjusting the previous mapping relationship until the reverse traversal is completed according to the execution time sequence
  • the target inverse mapping relationship obtained later is used as the final mapping relationship.
  • the building block includes: an insertion unit, which is used to insert the SWAP quantum logic gate corresponding to each logic gate according to the execution time sequence into the corresponding position in the quantum logic gate set according to the final mapping relationship, and complete the insertion
  • the resulting quantum program is determined to be the quantum program to be mapped equal to the initial quantum program.
  • FIG. 7 is a schematic flowchart of a mapping method between a quantum program and a quantum chip provided by an embodiment.
  • S1201 Obtain the directed acyclic graph of the quantum program to be executed and the initial mapping relationship between logical bits and physical bits.
  • the quantum program to be executed is mainly composed of tens, hundreds or even thousands of quantum logic gates.
  • the execution process of a quantum program is the process of executing all quantum logic gates according to a certain time sequence. It should be noted that the time sequence refers to the time sequence in which a single quantum logic gate is executed.
  • Fig. 3 shows a schematic diagram of the topological structure of physical bits of a quantum chip provided by the embodiment. The description about Fig. 3 will not be repeated.
  • Directed acyclic graph is a kind of directed graph. The literal meaning is that there is no cycle in the graph, and it is a directed graph without loops. If there is a non-directed acyclic graph, starting from point A to point B and returning to point A through C, a cycle is formed. If the direction from point C to point A is changed from point A to point C, it becomes a directed acyclic graph. Directed acyclic graphs are often used to represent driver dependencies between events, scheduling between tasks, etc.
  • Obtaining the directed acyclic graph of the quantum program to be executed includes, for example, the following steps.
  • S12011 Obtain the nodes in the quantum program to be executed.
  • a quantum program can be understood as an operation sequence, which mainly includes quantum logic gates, measurement operations (Measure) and so on.
  • the so-called node in the quantum program refers to the data of a specific structure in the relative position of the whole program, which can be quantum logic gate, measurement operation (Measure), etc.
  • the quantum logic gate node is mainly considered.
  • the quantum logic gate nodes in the quantum program can be obtained by traversing the nodes of the quantum program.
  • FIG. 8 is a schematic diagram of a quantum circuit to be executed provided by the embodiment.
  • a quantum program as a whole corresponds to a general quantum circuit
  • the quantum program to be executed refers to the general quantum circuit.
  • the quantum program to be executed is CNOT(q[0], q[1]) ⁇ CNOT(q[2],q[4]) ⁇ CNOT(q[2],q[3]) ⁇ CNOT (q[0], q[2]) ⁇ CNOT(q[2],q[4]) ⁇ CNOT(q[1],q[4]) ⁇ CNOT(q[0],q[ 1]).
  • S12012 Determine the association relationship between the nodes according to the qubits operated by the nodes.
  • the next node of the node is determined from all the quantum operation nodes that are sequentially executed by the qubits operated by the node, and the adjacency relationship between the node and the next node is obtained.
  • the last node corresponding to each bit in the traversal process In the process of traversing the nodes of the quantum circuit, record the qubit sequence number and the unique identifier of the operation of the currently traversed node, so as to update the last node corresponding to each bit in the traversal process.
  • the information of the last node corresponding to each bit and the node currently traversed, and the adjacency relationship between the last node and the node currently traversed are recorded.
  • the last node corresponding to the qubit refers to the predecessor node of the currently traversed quantum logic gate node.
  • the unique identifier of the quantum logic gate is marked according to the execution timing of the quantum logic gate.
  • FIG. 8 shows a schematic diagram of a quantum circuit to be executed.
  • the nodes of the quantum program are traversed sequentially according to the qubits operated by the nodes.
  • traverse CNOT(q[0], q[1]) the sequence numbers of the qubits operated by the CNOT gate are 0 and 1, and its unique identifier is "1";
  • CNOT(q[2] , q[4]) the sequence numbers of the qubits operated by CNOT gates are 2 and 4, their unique identifiers are "2" and the current first-level CNOT gates have no predecessor nodes.
  • the sequence numbers of the qubits operated by the CNOT gate are 2 and 3, and the unique identifier is 3.
  • the predecessor node of CNOT(q[2], q[3]) is CNOT(q[2], q[4]).
  • the adjacency relationship between record bits is recorded in the form of a unique identifier, which can be recorded as ⁇ 2,3 ⁇ , indicating that node 2 and node 3 are adjacent.
  • the CNOT(q[0], q[1]) of the sixth layer obtains the qubits operated by each layer of nodes and determines the relationship between nodes.
  • the processing flow is the same and will not be repeated here.
  • S12013 Generate a directed acyclic graph corresponding to the quantum program to be executed according to the nodes and the association relationship between the nodes.
  • Vertices in the directed acyclic graph represent nodes.
  • Edges in the directed acyclic graph represent association relationships between nodes. The direction of the edge represents the timing relationship in which the nodes corresponding to the vertices connected by the edge are executed.
  • FIG. 9 is a schematic diagram of a directed acyclic graph corresponding to a quantum circuit to be executed provided by an embodiment.
  • S1202 According to the directed acyclic graph of the quantum program to be executed, determine the execution sequence of the set of logic gates to be mapped in the quantum program to be executed.
  • the set of logic gates to be mapped includes the first set of regular logic gates and the second set of regular logic gates as described above.
  • the determination of the execution order of the set of logic gates to be mapped in the quantum program to be executed includes:
  • the execution sequence of the first regular logic gate set of the node whose entry degree is zero in the directed acyclic graph is set as the first priority
  • the described The execution sequence of the second set of regular logic gates of nodes in the directed acyclic graph with an in-degree of zero is set as the second priority.
  • the quantum program to be executed or the initial quantum program may include single-bit quantum logic gates, two-bit quantum logic gates and multi-bit quantum logic gates.
  • FIG. 9 is a schematic diagram of a directed acyclic graph corresponding to a quantum circuit to be executed provided by the embodiment.
  • the nodes with zero in-degree are respectively CNOT(q[0], q[1]) and CNOT(q[2], q[4]).
  • the logical bits of CNOT(q[0], q[1]) are adjacent to each other and are the first regular logic gate, so the execution sequence thereof is set as the first priority.
  • the logical bits of the CNOT(q[2], q[4]) operation are not adjacent and are the second regular logic gate, so its execution sequence is set as the second priority.
  • Deleting the first set of regular logic gates whose execution order division is completed, and continuing to execute the execution order of the first set of regular logic gates of nodes whose in-degree is zero in the directed acyclic graph is set as the first priority;
  • the step of setting the execution sequence of the second set of regular logic gates of the nodes whose in-degree is zero in the directed acyclic graph as the second priority until the division of the execution order of the set of logic gates to be mapped is completed.
  • the first rule logic gate set since the first rule logic gate set does not affect the resource utilization of the entire quantum circuit during operation, it can be directly executed, so in the process of dividing the execution sequence, the first rule logic that has been divided into execution sequences can be deleted Gate set, i.e. delete CNOT(q[0],q[1]).
  • the first rule logic gate set of the node whose in-degree is zero in the directed acyclic graph set it as the first priority, and set the second rule of the node in the directed acyclic graph with the in-degree of zero
  • the execution sequence of the logic gate set is set as the second priority step.
  • the logic gate sets of the first priority include: CNOT(q[0], q[1]), CNOT(q[2], q[3]) and CNOT(q[0], q [1]);
  • the second priority logic gate set includes: CNOT(q[2], q[4]), CNOT(q[0], q[2]), CNOT(q[2], q[ 4]) and CNOT(q[1], q[4]).
  • the cost of mapping each logic gate to the quantum chip topology can be divided into fixed cost and switching cost.
  • Fixed costs can include decoherence time for qubit bits, fidelity, etc.
  • the swap cost includes the number of swap logic gates required to map all the logic gates in the set of logic gates to be mapped. It should be noted that since the fixed cost of the quantum chip is determined by the physical characteristics of the chip during the operation of the quantum circuit, it can only be explained by considering the exchange cost of running the quantum circuit in the quantum chip as an example.
  • the execution order and the initial mapping relationship respectively determine the cost of mapping each logic gate in the set of logic gates to be mapped to the quantum chip topology, including:
  • mapping scheme for mapping each logic gate to a quantum chip topology.
  • the quantum circuit to be executed is converted into a directed acyclic graph structure. Then select a node with an in-degree of zero from the corresponding directed acyclic graph, which can be recorded as the operation layer, which represents the current quantum logic gate operation to be performed.
  • the logic gates that can be executed directly indicate that according to the current mapping relationship, there is no need to introduce any swap logic gate operations, and the logic gates that directly map logical bits to physical bits are satisfied; if there are logic gates that can be directly executed in the operation layer , then delete the logic gates that can be directly executed from the operation layer, and then update the operation layer according to the subsequent logic gates of the logic gates that can be directly executed, and return to the beginning position of the cycle to start the second iteration cycle; if the operation layer There is no logic gate that can be directly executed in , which means that under the current mapping conditions, the logic gate in the operation layer cannot be mapped. At this time, the swap logic gate operation needs to be introduced. The purpose of introducing the swap logic gate is to change the mapping relationship and realize Quantum state
  • the quantum logic gate nodes currently to be executed in the operation layer are CNOT(q[0], q[1]) and CNOT(q[2] ], q[4]).
  • CNOT(q[0],q[2]) CNOT(q[1],q[4] ) to update the operational layer.
  • mapping relationship at this time is q[0]--Q[4], q[1]--Q[0], q[2]--Q[2], q[3]--Q[3], q[4]--Q[1].
  • the logical bit q[2] is mapped to the physical bit Q[0] , also achieve the purpose of implementing CNOT(q[2], q[4]).
  • mapping relationship at this time is q[0]--Q[1], q[1]--Q[2], q[2]--Q[0], q[3]--Q[3], q[4]--Q[4].
  • the logic gates of the operation layer are all nodes with an in-degree of zero, and there are many mapping schemes for implementing CNOT(q[2], q[4]), which are not exhaustive here. However, in the actual application of this application, it is necessary to search for all feasible swap insertion schemes, and then determine the final target mapping by evaluating the different costs of each mapping scheme.
  • the cost formula of the mapping scheme can be constructed by:
  • each mapping scheme is evaluated through the above cost formula, taking into account the shortest path, the fidelity of the two-bit quantum logic gate, the measurement fidelity and the decoherence time and other factors.
  • the final consumption cost of each swap scheme is obtained by weighted summation.
  • the swap logic gate insertion scheme with the least cost is selected to update the current mapping. Then return to the operation layer to judge whether there is a logic gate that can be directly executed. This loop iterates until all the logic gates in the entire quantum circuit to be executed are mapped to the physical bits of the quantum chip topology.
  • T 2 is the decoherence time of quantum chip bits
  • G swap is the number of swap logic gates that need to be introduced to map all logic gates in the set of logic gates to be mapped
  • f double is the fidelity of two-bit quantum logic gates
  • f measure is the measurement Fidelity
  • a 1 , a 2 , a 3 , and a 4 are the preset weight coefficients of the cost expression.
  • S1204 According to the cost of mapping each logic gate to the quantum chip topology, adjust the target mapping of the quantum program to be executed, so as to minimize the cost of the target mapping.
  • the quantum chip topology and initial mapping relationship traverse forward according to the execution order and calculate the cost of mapping each logic gate to the quantum chip topology, and dynamically adjust the mapping relationship of the quantum program to be executed until The forward traversal is completed according to the execution order, and the target forward mapping relationship is obtained.
  • the target forward mapping relationship reversely traverse and calculate the cost of mapping each logic gate to the quantum chip topology according to the execution order, and dynamically adjust the mapping relationship of the quantum program to be executed until it is executed as described
  • the sequential reverse traversal is completed, and the target reverse mapping relationship is obtained.
  • FIG. 4 is a schematic diagram of another quantum circuit to be executed provided by the embodiment.
  • the initial mapping relationship q[0]--Q[0], q[1]--Q[1], q[2]--Q[2], q[3]--Q[3], q[ 4]--Q[4], CNOT(q[0], q[1]), CNOT(q[2], q[4]), CNOT(q[0], q[ 2]), CNOT(q[2], q[4]), CNOT(q[1], q[3]).
  • mapping relationship Since the logical bits are adjacent, the current mapping relationship does not change.
  • CNOT(q[2], q[4] in a possible solution: by inserting swap logic gates in Q[4] and Q[0], and then passing Q[0] and Q[ 1] is inserted into the swap logic gate to realize the mapping of the logical bit q[4] to the physical bit Q[1], and achieve the purpose of executing CNOT(q[2], q[4]).
  • the mapping relationship at this time is q[0]--Q[4], q[1]--Q[0], q[2]--Q[2], q[3]--Q[3], q[4]--Q[1].
  • the logic bit q[2] can be mapped to the physical bit Q[3] by inserting swap logic gates in Q[2] and Q[3], and the executable CNOT(q[0], q [2]).
  • the mapping relationship at this time is q[0]--Q[4], q[1]--Q[0], q[3]--Q[2], q[2]--Q[3], q[4]--Q[1].
  • the logic bit q[2] can be mapped to the physical bit Q[2] by inserting swap logic gates in Q[2] and Q[3], and the executable CNOT(q[2], q [4]) for the purpose.
  • the mapping relationship at this time is q[0]--Q[4], q[1]--Q[0], q[2]--Q[2], q[3]--Q[3], q[4]--Q[1]; Continue to traverse to CNOT(q[1], q[3]).
  • the logical bit q[3] can be mapped to the physical Bit Q[1] also achieves the purpose of executing CNOT(q[1], q[3]).
  • the target forward mapping relationship is obtained as q[0]--Q[4], q[1]--Q[0], q[4]--Q[2], q[2]--Q[ 3], q[3]--Q[1].
  • the target forward mapping relationship is q[0]--Q[4], q[1]--Q[0], q[4]--Q[2], q[2]--Q[ 3], q[3]--Q[1].
  • Dynamically adjust the mapping relationship of the quantum program to be executed such as adjusting the physical bits mapped by CNOT(q[1], q[3]) under the current target forward mapping relationship. Then adjust the previous mapping relationship, that is, the current target forward mapping relationship. Continue to adjust the physical bits mapped by each of the remaining logic gates under the previous mapping relationship until the target reverse mapping relationship obtained after the reverse traversal is completed according to the execution order, namely: q[0]--Q[4], q [1]--Q[0], q[4]--Q[2], q[2]--Q[3], q[3]--Q[1].
  • the quantum circuit mapping problem is an NP-hard problem in the high-bit and high-depth quantum circuit scenario. Therefore, in the high-bit, high-depth quantum circuit scenario, the possibility of finding the optimal solution is extremely small, and the two-way heuristic mapping algorithm is the mainstream idea to solve the problem.
  • the main method of the two-way heuristic mapping algorithm is to randomly give an initial mapping relationship, and then iteratively optimize it gradually to continuously approach the optimal solution. Theoretically, the more iterations, the better the optimization effect.
  • the initial mapping determines the starting point of algorithm optimization, so in the case of comprehensive consideration of time cost, a limited number of iterations can be performed, then the initial mapping will have a great impact on the final mapping result.
  • the cost of the target mapping is minimized by continuously performing forward and reverse iterative mapping or a limited number of forward and reverse iterative mappings.
  • this application first obtains the directed acyclic graph of the quantum program to be executed and the initial mapping relationship between logical bits and physical bits, and determines the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed.
  • the execution order of the set of logic gates to be mapped according to the execution order and the initial mapping relationship, respectively determine the cost of each logic gate in the set of logic gates to be mapped to the topology of the quantum chip, and according to the cost of mapping each logic gate to the topology of the quantum chip Cost, adjust the target mapping of the quantum program to be executed, so that the cost of the target mapping is the lowest, solve the problem of the influence of a single physical bit on the entire quantum circuit, and determine the optimal mapping circuit of the quantum chip topology, so that the entire quantum The resource utilization of the chip is maximized.
  • Fig. 10 is a schematic structural diagram of a quantum program and quantum chip mapping device provided by the embodiment.
  • the device may include:
  • the obtaining module 701 is used to obtain the directed acyclic graph of the quantum program to be executed and the initial mapping relationship between logical bits and physical bits;
  • the first determining module 702 is configured to determine the execution sequence of the set of logic gates to be mapped in the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed;
  • the second determination module 703 is configured to respectively determine the cost of mapping each logic gate in the set of logic gates to be mapped to the quantum chip topology according to the execution sequence and the initial mapping relationship;
  • the adjustment module 704 is configured to adjust the target mapping of the quantum program to be executed according to the cost of mapping each logic gate to the quantum chip topology, so as to minimize the cost of the target mapping.
  • the acquisition module includes:
  • An acquisition unit configured to acquire nodes in the quantum program to be executed
  • a determining unit configured to determine the association relationship between the nodes according to the qubits operated by the nodes
  • a generation unit configured to generate a directed acyclic graph corresponding to the quantum program to be executed according to the nodes and the association relationship between the nodes, wherein the vertices in the directed acyclic graph represent nodes, and the The edges in the directed acyclic graph represent the association relationship between nodes, and the direction of the edge represents the timing relationship in which the nodes corresponding to the vertices connected by the edge are executed.
  • the first determination module includes:
  • a division unit configured to set the execution order of the first set of regular logic gates of the nodes whose indegree is zero in the directed acyclic graph to the first priority according to the directed acyclic graph of the quantum program to be executed level, setting the execution order of the second set of regular logic gates of the nodes whose in-degree is zero in the directed acyclic graph as the second priority;
  • the iterative unit is used to delete the first set of regular logic gates completed by the execution sequence division, and continue to execute the execution order of the first set of regular logic gates in the directed acyclic graph whose entry degree is zero, which is set to
  • the first priority is a step of setting the execution sequence of the second rule logic gate set of the node whose in-degree is zero in the directed acyclic graph as the second priority until the execution of the logic gate set to be mapped Sequential division is complete.
  • the second determination module includes:
  • a mapping unit configured to obtain a mapping scheme for mapping each logic gate to a quantum chip topology according to the execution order and the initial mapping relationship;
  • An evaluation unit configured to construct a cost formula for evaluating the mapping scheme and calculate the cost of the mapping scheme.
  • the adjustment module includes:
  • the forward traversal unit is used to forward traverse and calculate the cost of mapping each logic gate to the quantum chip topology according to the quantum chip topology and initial mapping relationship according to the execution order, and dynamically adjust the to-be-executed The mapping relationship of the quantum program, until the forward traversal is completed according to the execution order, and the target forward mapping relationship is obtained;
  • the reverse traversal unit is used to reversely traverse and calculate the cost of mapping each logic gate to the quantum chip topology according to the target forward mapping relationship according to the execution order, and dynamically adjust the mapping of the quantum program to be executed relationship, until the reverse traversal is completed according to the execution order, and the target reverse mapping relationship is obtained;
  • the adjustment unit is configured to continue forward and reverse alternate iterative mapping, and repeat the step of dynamically adjusting the mapping relationship of the quantum program to be executed, so as to minimize the cost of the target mapping.
  • At least the problem that a single physical bit factor affects the entire quantum circuit can be alleviated. Furthermore, optimal mapping lines for the quantum chip topology can be determined. In addition, resource utilization of the entire quantum chip is maximized.
  • the embodiment also provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps in any one of the above method embodiments when running.
  • the above-mentioned storage medium may be configured to store the computer program for executing the computer program in FIG. 2 or 7 .
  • the above-mentioned storage medium may include but not limited to: U disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), mobile hard disk, magnetic Various media that can store computer programs, such as discs or optical discs.
  • ROM read-only memory
  • RAM random access memory
  • mobile hard disk magnetic Various media that can store computer programs, such as discs or optical discs.
  • the embodiment also provides an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments .
  • the above-mentioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the above-mentioned processor, and the input-output device is connected to the above-mentioned processor.
  • the above-mentioned processor may be configured to execute the steps in Fig. 2 or 7 through a computer program.
  • the embodiment also provides a quantum computer operating system.
  • the quantum computer operating system implements the construction of the quantum program to be mapped according to any of the above method embodiments provided in the embodiment.
  • Embodiments of the present application also provide a quantum computer, which includes the quantum computer operating system.

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Abstract

一种量子程序与量子芯片的映射方法和量子操作系统及计算机。该方法包括：获取量子芯片中物理比特的拓扑结构、初始量子程序的逻辑门集合以及逻辑比特与物理比特的初始映射关系（S201），确定初始量子程序的逻辑门集合的执行时序（S202），根据物理比特的拓扑结构和初始映射关系，依执行时序调整每一逻辑门对应的逻辑比特与物理比特的映射关系，得到最终映射关系（S203），根据最终映射关系，构建与初始量子程序等同的待映射量子程序，以使待映射量子程序中的SWAP量子逻辑门数量最少（S204）。可以提高整个量子芯片的资源利用率。

Description

量子程序与量子芯片的映射方法和量子操作系统及计算机
相关申请的交叉引用
本专利申请要求于2021年08月17日提交的、发明名称为“待执行量子程序目标映射的确定方法、装置及量子计算机”、申请号为CN 202110941255.8的中国专利申请；以及于2021年08月17日提交的、发明名称为“一种构建待映射量子程序的方法、装置及量子计算机”、申请号为CN 202110941261.3的中国专利申请的优先权，所述专利申请在此全部引入作为参考。
技术领域
本申请属于量子程序编译技术领域，特别是一种量子程序与量子芯片的映射方法、量子程序与量子芯片的映射装置、存储介质、电子装置、量子操作系统及量子计算机。
背景技术
量子计算机是一类遵循量子力学规律进行高速数学和逻辑运算、存储及处理量子信息的物理装置。当某个装置处理和计算的是量子信息，运行的是量子算法时，它就是量子计算机。量子计算机因其具有相对普通计算机更高效的处理数学问题的能力，例如，能将破解RSA密钥的时间从数百年加速到数小时，故成为一种正在研究中的关键技术。
在嘈杂中型量子计算(Noisy Intermediate-Scale Quantum)阶段，每个量子芯片都有自己特定的拓扑结构，其反映了量子芯片所支持的各量子比特之间的连接关系。在实际的量子编程中，获取量子程序的逻辑门集合以及逻辑-物理比特的初始映射后，对两两相邻的量子比特实施的两量子比特逻辑门有可能受到芯片结构限制，该两比特逻辑门不能够被两个量子比特适配而形成两量子比特逻辑门。因此，需要对任意的两量子比特逻辑门进行交换转化，直至转化为该芯片所支持的量子逻辑门为止，才能提高量子芯片这个计算资源的利用率。
发明内容
实施例的一个目的是提供一种量子程序与量子芯片的映射方案，以提高整个量子芯片的资源利用率。
一个实施例提供了一种量子程序与量子芯片的映射方法，所述方法包括：获取量子芯片中物理比特的拓扑结构、初始量子程序的逻辑门集合以及逻辑比特与物理比特的初始映射关系；确定初始量子程序的逻辑门集合的执行时序；根据所述物理比特的拓扑结构和所述初始映射关系，依所述执行时序调整每一逻辑门对应的逻辑比特与物理比特的映射关系，得到最终映射关系；根据所述最终映射关系，构建与初始量子程序等同的待映射量子程序，以使所述待映射量子程序中的SWAP量子逻辑门数量最少。
另一个实施例提供了一种量子程序与量子芯片的映射装置，所述装置包括：获取模块，用于获取量子芯片中物理比特的拓扑结构、初始量子程序的逻辑门集合以及逻辑比特 与物理比特的初始映射关系；确定模块，用于确定初始量子程序的逻辑门集合的执行时序；调整模块，用于根据所述物理比特的拓扑结构和所述初始映射关系，依所述执行时序调整每一逻辑门对应的逻辑比特与物理比特的映射关系，得到最终映射关系；构建模块，用于根据所述最终映射关系，构建与初始量子程序等同的待映射量子程序，以使所述待映射量子程序中的SWAP量子逻辑门数量最少。
另一个实施例提供了一种量子程序与量子芯片的映射方法，所述方法包括：获取待执行量子程序的有向无环图以及逻辑比特与物理比特的初始映射关系；根据所述待执行量子程序的有向无环图，确定所述待执行量子程序的待映射逻辑门集合的执行顺序；根据所述执行顺序和所述初始映射关系，分别确定所述待映射逻辑门集合中每个逻辑门映射到量子芯片拓扑结构的成本；根据所述每个逻辑门映射到量子芯片拓扑结构的成本，调整待执行量子程序的目标映射，以使所述目标映射的成本最低。
另一个实施例提供了一种量子程序与量子芯片的映射装置，所述装置包括：获取模块，用于获取待执行量子程序的有向无环图以及逻辑比特与物理比特的初始映射关系；第一确定模块，用于根据所述待执行量子程序的有向无环图，确定所述待执行量子程序的待映射逻辑门集合的执行顺序；第二确定模块，用于根据所述执行顺序和所述初始映射关系，分别确定所述待映射逻辑门集合中每个逻辑门映射到量子芯片拓扑结构的成本；调整模块，用于根据所述每个逻辑门映射到量子芯片拓扑结构的成本，调整待执行量子程序的目标映射，以使所述目标映射的成本最低。
又一实施例提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述任一项中所述的方法。
又一实施例提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述任一项中所述的方法。
本申请的又一实施例提供了一种量子计算机操作系统，所述量子计算机操作系统根据上述任一项中所述方法实现量子程序与量子芯片的映射。
本申请的又一实施例提供了一种量子计算机，所述量子计算机包括所述的量子计算机操作系统。
根据一个实施例，可以至少缓解由于增加SWAP门而对整个量子线路运行的影响，从而提高整个量子芯片的资源利用率。
根据一个实施例，可以至少缓解由于单个物理比特因素对整个量子线路产生影响的问题。此外，可以确定量子芯片拓扑结构的最优映射线路。此外，可以使得整个量子芯片的资源利用最大化。
附图说明
图1为实施例提供的计算机终端的硬件结构框图；
图2为实施例提供的一种量子程序与量子芯片的映射方法的流程示意图；
图3为实施例提供的一种量子芯片物理比特的拓扑结构的示意图；
图4为实施例一种初始量子程序对应的量子线路示意图；
图5为实施例提供的一种与初始量子程序等同的待映射量子程序的示意图；
图6为实施例提供的一种量子程序与量子芯片的映射装置的结构示意图。
图7为实施例提供的一种量子程序与量子芯片的映射方法的流程示意图；
图8为实施例提供的一种待执行量子线路的示意图；
图9为实施例提供的一种待执行量子线路对应有向无环图的示意图；
图10为实施例提供的一种量子程序与量子芯片的映射确定装置的结构示意图。
具体实施方式
下面通过参考附图描述的实施例是示例性的，仅用于解释实施例，而不能解释为对实施例的限制。
实施例中提供的方法可以应用于电子设备，如计算机终端，具体如普通电脑、量子计算机等。
下面以运行在计算机终端上为例对其进行详细说明。图1为实施例提供的计算机终端的硬件结构框图。如图1所示，计算机终端可以包括一个或多个(图1中仅示出一个)处理器102(处理器102可以包括但不限于微处理器MCU或可编程逻辑器件FPGA等的处理装置)和用于存储数据的存储器104，可选地，上述计算机终端还可以包括用于通信功能的传输装置106以及输入输出设备108。本领域普通技术人员可以理解，图1所示的结构仅为示意，其并不对上述计算机终端的结构造成限定。例如，计算机终端还可包括比图1中所示更多或者更少的组件，或者具有与图1所示不同的配置。
存储器104可用于存储应用软件的软件程序以及模块，如本申请实施例中的实现一种构建待映射量子程序的方法对应的程序指令/模块，处理器102通过运行存储在存储器104内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述的方法。存储器104可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器104可进一步包括相对于处理器102远程设置的存储器，这些远程存储器可以通过网络连接至计算机终端。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输装置106用于经由一个网络接收或者发送数据。上述的网络具体实例可包括计算机终端的通信供应商提供的无线网络。在一个实例中，传输装置106包括一个网络适配器(Network Interface Controller，NIC)，其可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中，传输装置106可以为射频(Radio Frequency，RF)模块，其用于通过无线方式与互联网进行通讯。
需要说明的是，当量子程序在量子芯片(又叫物理芯片)上运行时，对于同一块物理芯片上的多个物理比特，其各个物理比特的状态是不稳定的，例如两比特量子逻辑门操作噪声、测量噪声以及物理比特的退相干时间等因素，均会对物理比特的有效利用造成干扰，从而对整个量子线路的运行结果产生未知影响。例如，由于各个物理比特的退相干时间不同，若是因为某个物理比特退相干时间短而限制了整个量子芯片可运行的量子线路深度，必然导致其他物理比特资源的浪费。
现有技术中，一般对无法被量子芯片上的两个量子比特适配的两量子比特量子逻辑门，通过在量子程序中加入SWAP门的方式，将不适配的两量子比特量子逻辑门转化为该芯片所支持的量子逻辑门。例如，量子程序中包含CNOT(q1,q3)量子逻辑门，量子芯片虽支持CNOT门，但量子芯片中的物理量子比特q1与q3并不直接相连，因此无法被直接 执行。故需要对量子程序中的两量子逻辑门进行交换，交换为该芯片可直接执行的量子逻辑门。例如，量子程序包括CNOT(q1,q3)，则现有的交换方法简述为：根据量子芯片上量子比特之间的连接关系，查找CNOT操作的两个量子比特q1、q3之间的连接路径，假设该路径经过的量子比特为q1、q2,则执行CNOT(q1,q3)等价于依次执行：SWAP(q1，q2)、SWAP(q2，q3)、CNOT(q2,q3)、SWAP(q3，q2)、SWAP(q2，q1)。其中，SWAP门表示对量子比特执行交换操作。可见，为了适配量子芯片，对一个两量子比特逻辑门，交换过程就会新增较多数量的量子逻辑门，最终转化后量子程序中的量子逻辑门数量会更为庞大，从而大幅度降低量子程序的计算效率。
基于此，有必要提出一种构建待映射量子程序的最佳方案，用于解决因增加SWAP门对整个量子线路运行的影响，提高整个量子芯片的资源利用率。
图2为实施例提供的一种量子程序与量子芯片的映射方法的流程示意图。
如图2所示，S201：获取量子芯片中物理比特的拓扑结构、初始量子程序的逻辑门集合以及逻辑比特与物理比特的初始映射关系。
例如，每个量子芯片都有自己特定的拓扑结构。拓扑结构反映了量子芯片所支持的各物理比特之间的纠缠关系。现阶段，量子芯片物理比特数目有限，且芯片拓扑结构简单，通常以简单的二维链(或者一维链)形式存在，对量子芯片中的某个物理比特，其只能与有限个物理比特相连。
示例性的，图3为实施例提供的一种量子芯片物理比特的拓扑结构示意图。该量子芯片中包括8个物理比特，分别为Q[0]、Q[1]、Q[2]、Q[3]、Q[4]、Q[5]、Q[6]、Q[7]。物理比特之间可通过电容耦合，且只有相邻的物理比特之间才具有耦合关系，具体耦合结果参考图3。
初始量子程序的逻辑门集合主要由几十上百个甚至千上万个量子逻辑门组成。初始量子程序的逻辑门集合包括：第一规则逻辑门集合和第二规则逻辑门集合，其中，所述第一规则逻辑门集合包括：单比特量子逻辑门和逻辑比特相邻的两比特量子逻辑门；，所述第二规则逻辑门集合包括：逻辑比特不相邻的两比特量子逻辑门。初始量子程序的执行过程，就是对所有的量子逻辑门按照一定时序执行的过程。
为了便于区分，一般将量子芯片中的量子比特结构称为物理比特，量子线路中操作的对象比特称为逻辑比特。逻辑比特与物理比特的初始映射关系，指逻辑比特与物理比特之间比特相互“对应”的关系。
示例性的，针对一段初始量子程序CNOT(q[0]，q[1])<<CNOT(q[2]，q[4])<<CNOT(q[0]，q[2])<<CNOT(q[2]，q[4])<<CNOT(q[1]，q[3])，其操作的逻辑比特分别为q[0]、q[1]、q[2]，q[3]、q[4]，则逻辑比特与物理比特的初始映射关系可设置为q[0]对应Q[0]、q[1]对应Q[1]、q[2]对应Q[2]，q[3]对应Q[3]、q[4]对应Q[4]等多种初始映射关系。
S202：确定初始量子程序的逻辑门集合的执行时序。
时序即量子逻辑门被执行的时间顺序。确定初始量子程序的逻辑门集合的执行时序包括如下步骤：
S2021：获取初始量子程序对应的量子线路。
示例性的，图4为实施例一种初始量子程序对应的量子线路示意图。该量子线路对应的一段初始量子程序为CNOT(q[0]，q[1])<<CNOT(q[2]，q[4])<<CNOT(q[0]，q[2]) <<CNOT(q[2]，q[4])<<CNOT(q[1]，q[3])。
S2022：遍历所述量子线路，将每个量子比特第一时序的第一规则逻辑门集合的执行时序，设为优先执行时序，将每个量子比特第一时序的第二规则逻辑门集合的执行时序，设为次优先执行时序。
示例性的，遍历如图4所示的量子线路，其中，第一时序的逻辑门为CNOT(q[0]，q[1])、CNOT(q[2]，q[4])，第二时序的逻辑门为CNOT(q[0]，q[2])，第三时序的逻辑门为CNOT(q[2]，q[4])，第四时序的逻辑门为CNOT(q[1]，q[3])。因此每个量子比特第一时序的逻辑门集合为CNOT(q[0]，q[1])和CNOT(q[2]，q[4])，其中，CNOT(q[0]，q[1])符合第一规则逻辑门的特征，并将其执行时序设为优先执行时序；CNOT(q[2]，q[4])符合第二规则逻辑门的特征，并将其执行时序设为次优先执行时序。
S2023：删除执行时序划分完成的逻辑门，继续执行所述将每个量子比特第一时序的第一规则逻辑门集合的执行时序，设为优先执行时序，将每个量子比特第一时序的第二规则逻辑门集合的执行时序，设为次优先执行时序的步骤，直至所述量子线路逻辑门的执行时序划分完成。
示例性的，接上述示例，删除执行时序划分完成的逻辑门，即删除CNOT(q[0]，q[1])、CNOT(q[2]，q[4])，此时第一时序的逻辑门为CNOT(q[0]，q[2])，第二时序的逻辑门为CNOT(q[2]，q[4])，第三时序的逻辑门为CNOT(q[1]，q[3])，此时继续执行将每个量子比特第一时序的第一规则逻辑门集合的执行时序，设为优先执行时序，将每个量子比特第一时序的第二规则逻辑门集合的执行时序，设为次优先执行时序的步骤，因此，CNOT(q[0]，q[2])、CNOT(q[2]，q[4])、CNOT(q[1]，q[3])均被设为次优先执行时序，至此执行时序划分完成。
需要说明的是，初始量子程序可包括单比特量子逻辑门、两比特量子逻辑门和多比特量子逻辑门，但在确定初始量子程序逻辑门集合的执行顺序之前，首先需要将多比特量子逻辑门转化成单比特量子逻辑门和两比特量子逻辑门的组合。由于单比特量子逻辑门可直接将逻辑比特映射到物理比特，因此可将转化后得到的单比特量子逻辑门和转化前待执行量子程序中本身存在的单量子逻辑门删除(或优先执行)，再基于转化后得到的两比特量子逻辑门和转化前初始量子程序中本身存在的两比特量子逻辑门，确定初始量子程序的逻辑门集合的执行时序，在这里为了方便说明，上述示例仅以包含两比特量子逻辑门的量子线路举例。
S203：根据所述物理比特的拓扑结构和所述初始映射关系，依所述执行时序调整每一逻辑门对应的逻辑比特与物理比特的映射关系，得到最终映射关系。
根据物理比特的拓扑结构、所述初始映射关系，依所述执行时序正向遍历每一逻辑门并调整所述每一逻辑门在上一个映射关系下所映射的物理比特，调整所述上一个映射关系，直至依所述执行时序正向遍历完成，得到目标正向映射关系。
示例性的，根据如图3所示的物理比特的拓扑结构、所述初始映射关系q[0]对应Q[0]、q[1]对应Q[1]、q[2]对应Q[2]，q[3]对应Q[3]、q[4]对应Q[4]。依所述执行时序正向遍历CNOT(q[0]，q[1])、CNOT(q[2]，q[4])、CNOT(q[0]，q[2])、CNOT(q[2]，q[4])、CNOT(q[1]，q[3])。首先依执行时序正向遍历CNOT(q[0]，q[1])。由于逻辑比特相邻，当前映射关系不改变。当遍历至CNOT(q[2]，q[4])时，在一种可能的方案中：通过在Q[4]与Q[0] 插入SWAP逻辑门，再通过Q[0]与Q[1]间插入SWAP逻辑门，实现将逻辑比特q[4]映射到物理比特Q[1]，达到可执行CNOT(q[2]，q[4])的目的。此时的映射关系为q[0]--Q[4]、q[1]--Q[0]、q[2]--Q[2]，q[3]--Q[3]、q[4]--Q[1]。继续遍历至CNOT(q[0]，q[2])。基于当前映射关系，可以通过在Q[2]与Q[3]插入SWAP逻辑门，实现将逻辑比特q[2]映射到物理比特Q[3]，达到可执行CNOT(q[0]，q[2])的目的。此时的映射关系为q[0]--Q[4]、q[1]--Q[0]、q[3]--Q[2]，q[2]--Q[3]、q[4]--Q[1]。继续遍历至CNOT(q[2]，q[4])。基于当前映射关系，可以通过在Q[2]与Q[3]插入SWAP逻辑门，实现将逻辑比特q[2]映射到物理比特Q[2]，达到可执行CNOT(q[2]，q[4])的目的。此时的映射关系为q[0]--Q[4]、q[1]--Q[0]、q[2]--Q[2]，q[3]--Q[3]、q[4]--Q[1]。继续遍历至CNOT(q[1]，q[3])。基于当前映射关系，可以通过在Q[2]与Q[3]插入SWAP逻辑门，再通过Q[1]与Q[2]间插入SWAP逻辑门，实现将逻辑比特q[3]映射到物理比特Q[1]，也达到可执行CNOT(q[1]，q[3])的目的。此时得到目标正向映射关系为q[0]--Q[4]、q[1]--Q[0]、q[4]--Q[2]，q[2]--Q[3]、q[3]--Q[1]。
根据所述目标正向映射关系，依所述执行时序逆向遍历每一逻辑门并调整所述每一逻辑门在上一个映射关系下所映射的物理比特，调整所述上一个映射关系，直至依所述执行时序逆向遍历完成后得到的目标逆向映射关系，作为所述最终映射关系。
接上述示例，目标正向映射关系为q[0]--Q[4]、q[1]--Q[0]、q[4]--Q[2]，q[2]--Q[3]、q[3]--Q[1]。依执行时序逆向遍历CNOT(q[1]，q[3])、CNOT(q[2]，q[4])、CNOT(q[0]，q[2])、CNOT(q[2]，q[4])及CNOT(q[0]，q[1])。调整上述每一逻辑门在上一个映射关系下所映射的物理比特。如调整CNOT(q[1]，q[3])在当前目标正向映射关系下所映射的物理比特。随后调整上一个映射关系，即当前目标正向映射关系。继续调整余下每一逻辑门在上一个映射关系下所映射的物理比特，直至依所述执行时序逆向遍历完成后得到的目标逆向映射关系，即：q[0]--Q[4]、q[1]--Q[0]、q[4]--Q[2]，q[2]--Q[3]、q[3]--Q[1]，作为所述最终映射关系。
S204：根据所述最终映射关系，构建与初始量子程序等同的待映射量子程序，以使所述待映射量子程序中的SWAP量子逻辑门数量最少。
根据最终映射关系，在量子逻辑门集合中相应位置插入依所述执行时序运行每一逻辑门对应生成的SWAP量子逻辑门。将插入完成后得到的量子程序，确定为与初始量子程序等同的待映射量子程序。
示例性的，在量子逻辑门集合中相应位置插入依所述执行时序运行每一逻辑门对应生成的SWAP量子逻辑门。图5为实施例提供的一种与初始量子程序等同的待映射量子程序示意图。通过在Q[4]与Q[0]插入SWAP逻辑门，再通过Q[0]与Q[1]间插入SWAP逻辑门，实现将逻辑比特q[4]映射到物理比特Q[1]。通过在Q[2]与Q[3]插入SWAP逻辑门，实现将逻辑比特q[2]映射到物理比特Q[3]。通过在Q[2]与Q[3]插入SWAP逻辑门，实现将逻辑比特q[2]映射到物理比特Q[2]。通过在Q[2]与Q[3]插入SWAP逻辑门，再通过Q[1]与Q[2]间插入SWAP逻辑门，得到与初始量子程序等同的待映射量子程序，以使待映射量子程序中的SWAP量子逻辑门数量最少。图中黑色圆点代表CNOT门的控制比特，黑色圈内“+”代表CNOT门的目标比特，两个“X”用竖线连接，代表SWAP逻辑门的示意图。
需要说明的是，两个不相邻的比特间可能存在多种引入SWAP逻辑门方案。但每个方案的保真度、噪声等各不相同，只有选择引入SWAP逻辑门个数较少、保真度高的方案 才能有效的保证待执行量子线路执行准确率。如果在映射过程中，能够将操作较少的逻辑比特映射到退相干时间较短的物理比特上，可以实现物理比特资源利用最大化，同时也提高了量子线路的运行准确率。因此可通过选择保真度高、引入SWAP逻辑门个数少、将操作较少的逻辑比特映射到退相干时间较短的物理比特上，才能有效的保证量子线路执行准确率。
根据一个实施例，可以至少缓解由于增加SWAP门对整个量子线路运行的影响，从而提高整个量子芯片的资源利用率。
图6为实施例提供的一种量子程序与量子芯片的映射装置的结构示意图。与图2所示的流程相对应，该装置可以包括：获取模块601，用于获取量子芯片中物理比特的拓扑结构、初始量子程序的逻辑门集合以及逻辑比特与物理比特的初始映射关系；确定模块602，用于确定初始量子程序的逻辑门集合的执行时序；调整模块603，用于根据所述物理比特的拓扑结构和所述初始映射关系，依所述执行时序调整每一逻辑门对应的逻辑比特与物理比特的映射关系，得到最终映射关系；构建模块604，用于根据所述最终映射关系，构建与初始量子程序等同的待映射量子程序，以使所述待映射量子程序中的SWAP量子逻辑门数量最少。
例如，所述确定模块包括：获取单元，用于获取初始量子程序对应的量子线路；遍历单元，用于遍历所述量子线路，将每个量子比特第一时序的第一规则逻辑门集合的执行时序，设为优先执行时序，将每个量子比特第一时序的第二规则逻辑门集合的执行时序，设为次优先执行时序；迭代单元，用于删除执行时序划分完成的逻辑门，继续执行所述将每个量子比特第一时序的第一规则逻辑门集合的执行时序，设为优先执行时序，将每个量子比特第一时序的第二规则逻辑门集合的执行时序，设为次优先执行时序的步骤，直至所述量子线路逻辑门的执行时序划分完成。
例如，所述调整模块包括：第一执行单元，用于根据物理比特的拓扑结构、所述初始映射关系，依所述执行时序正向遍历每一逻辑门并调整所述每一逻辑门在上一个映射关系下所映射的物理比特，调整所述上一个映射关系，直至依所述执行时序正向遍历完成，得到目标正向映射关系；第二执行单元，用于根据所述目标正向映射关系，依所述执行时序逆向遍历每一逻辑门并调整所述每一逻辑门在上一个映射关系下所映射的物理比特，调整所述上一个映射关系，直至依所述执行时序逆向遍历完成后得到的目标逆向映射关系，作为所述最终映射关系。
例如，所述构建模块包括：插入单元，用于根据所述最终映射关系，在量子逻辑门集合中相应位置插入依所述执行时序运行每一逻辑门对应生成的SWAP量子逻辑门，将插入完成后得到的量子程序，确定为与初始量子程序等同的待映射量子程序。
参见图7，图7为实施例提供的一种量子程序与量子芯片的映射方法的流程示意图。
如图7所示，S1201：获取待执行量子程序的有向无环图以及逻辑比特与物理比特的初始映射关系。
待执行量子程序主要由几十上百个甚至千上万个量子逻辑门组成。量子程序的执行过程，就是对所有的量子逻辑门按照一定时序执行的过程，需要说明的是，时序即单个量子逻辑门被执行的时间顺序。
图3示出了实施例提供的一种量子芯片物理比特的拓扑结构示意图。关于图3的描 述不再重复。
示例性的，针对一段量子程序CNOT(q[0]，q[1])<<CNOT(q[2]，q[4])<<CNOT(q[2]，q[3])<<CNOT(q[0]，q[2])<<CNOT(q[2]，q[4])<<CNOT(q[1]，q[4])<<CNOT(q[0]，q[1])，其操作的逻辑比特分别为q[0]、q[1]、q[2]，q[3]、q[4]，则逻辑比特与物理比特的初始映射关系可设置为q[0]对应Q[0]、q[1]对应Q[1]、q[2]对应Q[2]，q[3]对应Q[3]、q[4]对应Q[4]等多种初始映射关系。
有向无环图(DAG图)是有向图的一种，字面意思的理解就是图中没有环，是一个无回路的有向图。如果有一个非有向无环图，从A点出发向B经过C可以回到A点，则形成一个环。若将从C点到A点的方向改为从A点到C点则变成有向无环图。有向无环图常被用来表示事件间的驱动依赖关系、任务之间的调度等。
获取待执行量子程序的有向无环图例如包括如下步骤。
S12011：获取待执行量子程序中的节点。
量子程序可以理解为一个操作序列，其中主要包含量子逻辑门、测量操作(Measure)等。所谓量子程序中的节点，是指在整个程序的相对位置的一特定结构的数据，可以是量子逻辑门、测量操作(Measure)等，本申请中主要考虑量子逻辑门节点。
例如，可以通过遍历量子程序的节点，得到量子程序中量子逻辑门节点。
例如，图8为实施例提供的一种待执行量子线路的示意图。可以理解的是，一段量子程序整体上对应有一条总的量子线路，所述待执行量子程序即指该条总的量子线路。例如，待执行量子程序为CNOT(q[0]，q[1])<<CNOT(q[2]，q[4])<<CNOT(q[2]，q[3])<<CNOT(q[0]，q[2])<<CNOT(q[2]，q[4])<<CNOT(q[1]，q[4])<<CNOT(q[0]，q[1])。从CNOT(q[0]，q[1])开始遍历，获取待执行量子程序中的节点1至节点7分别为CNOT(q[0]，q[1])、CNOT(q[2]，q[4])、CNOT(q[2]，q[3])、CNOT(q[0]，q[2])、CNOT(q[2]，q[4])、CNOT(q[1]，q[4])、CNOT(q[0]，q[1])。
S12012：根据所述节点操作的量子比特，确定所述节点之间的关联关系。
针对每一所述量子操作节点，从该节点操作的量子比特依序执行的所有量子操作节点中，确定该节点的下一节点，得到该节点与下一节点之间的相邻关系。
在遍历量子线路的节点过程中，记录当前遍历到的节点操作的量子比特序号和唯一标识符，以更新遍历过程中每个比特对应的最后一个节点。记录每个比特对应的最后一个节点及当前遍历到的节点的信息和最后一个节点与当前遍历到的节点之间的相邻关系。量子比特对应的最后一个节点是指当前遍历到的量子逻辑门节点的前驱节点。
需要说明的是，量子逻辑门的唯一标识符按照量子逻辑门的执行时序进行标记。
示例性的，图8示出了一种待执行量子线路示意图。首先，按照节点操作的量子比特依序遍历量子程序的节点。从量子线路的第一层开始，遍历CNOT(q[0]，q[1])，CNOT门操作的量子比特序号为0和1，其唯一标识符为“1”；CNOT(q[2]，q[4])，CNOT门操作的量子比特序号为2和4，其唯一标识符为“2”且当前第一层CNOT门均没有前驱节点。
当遍历至量子线路第二层的起始，即遍历至节点CNOT(q[2]，q[3])时，CNOT门操作的量子比特序号为2和3，唯一标识符为3。此时CNOT(q[2]，q[3])的前驱节点为CNOT(q[2]，q[4])。记录比特之间的相邻关系，以唯一标识符的形式记录，可记为{2,3}，表示节点2和节点3相邻。然后，依序遍历到第三层的CNOT(q[0]，q[2])、第四层的CNOT (q[2]，q[4])、第五层的CNOT(q[1]，q[4])、第六层的CNOT(q[0]，q[1])，获取每一层节点操作的量子比特，确定节点之间的关联关系。处理流程同理，在此不再赘述。
S12013：根据所述节点及节点之间的关联关系，生成与所述待执行量子程序对应的有向无环图。所述有向无环图中的顶点表征节点。所述有向无环图中的边表征节点之间的关联关系。所述边的方向表征该边相连的顶点对应的节点被执行的时序关系。
参见图9，图9为实施例提供的一种待执行量子线路对应有向无环图的示意图。通过构建与量子操作节点对应的顶点并构建具有相邻关系的节点对应的顶点之间的边。边的方向由具有相邻关系的节点中的前一节点对应的顶点指向下一节点对应的顶点，再根据节点及节点之间的关联关系，生成与待执行量子程序对应的有向无环图。
S1202：根据所述待执行量子程序的有向无环图，确定所述待执行量子程序的待映射逻辑门集合的执行顺序。
需要说明的是，所述待映射逻辑门集合包括如上所述的第一规则逻辑门集合和第二规则逻辑门集合。
所述确定所述待执行量子程序的待映射逻辑门集合的执行顺序包括：
根据所述待执行量子程序的有向无环图，将所述有向无环图中入度为零的节点的第一规则逻辑门集合的执行顺序，设为第一优先级，将所述有向无环图中入度为零的节点的第二规则逻辑门集合的执行顺序，设为第二优先级。
如上所述，待执行量子程序或初始量子程序可包括单比特量子逻辑门、两比特量子逻辑门和多比特量子逻辑门。
示例性的，图9为实施例提供的待执行量子线路对应有向无环图的示意图。根据如图9所示的有向无环图，入度为零的节点分别为CNOT(q[0]，q[1])和CNOT(q[2]，q[4])。CNOT(q[0]，q[1])操作的逻辑比特相邻，为第一规则逻辑门，因此将其执行顺序设为第一优先级。CNOT(q[2]，q[4])操作的逻辑比特不相邻，为第二规则逻辑门，因此将其执行顺序设为第二优先级。
删除执行顺序划分完成的第一规则逻辑门集合，继续执行所述将所述有向无环图中入度为零的节点的第一规则逻辑门集合的执行顺序，设为第一优先级；将所述有向无环图中入度为零的节点的第二规则逻辑门集合的执行顺序，设为第二优先级的步骤，直至所述待映射逻辑门集合的执行顺序划分完成。
接上述示例，由于第一规则逻辑门集合在运行过程中并不影响整个量子线路的资源利用率，可以直接执行，因此在划分执行顺序的过程中，可删除执行顺序划分完成的第一规则逻辑门集合，即删除CNOT(q[0]，q[1])。继续执行将有向无环图中入度为零的节点的第一规则逻辑门集合的执行顺序，设为第一优先级，将有向无环图中入度为零的节点的第二规则逻辑门集合的执行顺序，设为第二优先级的步骤。最终执行顺序划分完成，第一优先级的逻辑门集合包括：CNOT(q[0]，q[1])、CNOT(q[2]，q[3])和CNOT(q[0]，q[1])；第二优先级的逻辑门集合包括：CNOT(q[2]，q[4])、CNOT(q[0]，q[2])、CNOT(q[2]，q[4])和CNOT(q[1]，q[4])。
S1203：根据所述执行顺序和所述初始映射关系，分别确定所述待映射逻辑门集合中每个逻辑门映射到量子芯片拓扑结构的成本。
每个逻辑门映射到量子芯片拓扑结构的成本可以分为固定成本和交换成本。固定成 本可以包括量子芯片比特的退相干时间、保真度等。交换成本包括为映射待映射逻辑门集合中所有逻辑门所需要引入的swap逻辑门个数。需要说明的是，由于量子芯片的在运行量子线路的过程中，其固定成本是由芯片的物理特性决定，因此可仅考虑在量子芯片中运行量子线路的交换成本为例进行说明。
根据所述执行顺序和所述初始映射关系，分别确定所述待映射逻辑门集合中每个逻辑门映射到量子芯片拓扑结构的成本，包括：
1、根据所述执行顺序和所述初始映射关系，分别获取每个逻辑门映射到量子芯片拓扑结构的映射方案。
首先将待执行量子线路转换为有向无环图结构。然后从对应有向无环图中选择入度为零的节点，可记为操作层，表示当前要执行的量子逻辑门操作。接下来是一个迭代循环过程：判断操作层是否为空；如果操作层为空，则说明已经完成整个待执行量子线路映射，映射完成；如果操作层不为空，则从操作层中查找可以直接执行的逻辑门，可以直接执行的逻辑门表示根据当前映射关系，不需要引入任何swap逻辑门操作，满足直接将逻辑比特映射到物理比特的逻辑门；如果操作层中存在可以直接执行的逻辑门，则将可以直接执行的逻辑门从操作层中删除，然后根据可以直接执行的逻辑门的后项逻辑门来更新操作层，并回到循环开始位置，开始第二次迭代循环；如果操作层中不存在可以直接执行的逻辑门，说明在当前的映射条件下，无法对操作层中的逻辑门进行映射，这时候需要引入swap逻辑门操作，引入swap逻辑门的目的是改变映射关系、实现量子态转移，来改善当前映射环境。
示例性的，参见如图9所示的有向无环图，首先确定操作层中当前要执行的量子逻辑门节点分别为CNOT(q[0]，q[1])和CNOT(q[2]，q[4])。从它们中查找可以直接执行的逻辑门，即CNOT(q[0]，q[1])，并将CNOT(q[0]，q[1])从操作层中删除。然后，根据可直接执行的逻辑门CNOT(q[0]，q[1])的后项逻辑门CNOT(q[0]，q[2])、CNOT(q[1]，q[4])来更新操作层。由于当前CNOT(q[0]，q[2])、CNOT(q[1]，q[4])的入度都不为0，所以暂时不能更新到操作层，即当前操作层仍为CNOT(q[2]，q[4])，回到循环开始位置。以上述步骤开始第二次迭代循环，直至操作层中不存在可以直接执行的逻辑门。此时引入swap逻辑门操作，动态调整待执行量子程序的映射关系来改善当前映射环境。
示例性的，根据初始映射关系q[0]--Q[0]、q[1]--Q[1]、q[2]--Q[2]，q[3]--Q[3]、q[4]--Q[4]，此时若要执行CNOT(q[2]，q[4])，则有多种引入swap逻辑门的方案。如：通过在Q[4]与Q[0]插入swap逻辑门，再通过Q[0]与Q[1]间插入swap逻辑门，实现将逻辑比特q[4]映射到物理比特Q[1]，达到可执行CNOT(q[2]，q[4])的目的。此时的映射关系为q[0]--Q[4]、q[1]--Q[0]、q[2]--Q[2]，q[3]--Q[3]、q[4]--Q[1]。或通过在Q[2]与Q[1]插入swap逻辑门，再通过Q[0]与Q[1]间插入swap逻辑门，实现将逻辑比特q[2]映射到物理比特Q[0]，也达到可执行CNOT(q[2]，q[4])的目的。此时的映射关系为q[0]--Q[1]、q[1]--Q[2]、q[2]--Q[0]，q[3]--Q[3]、q[4]--Q[4]。需要说明的是，操作层的逻辑门均为入度为零的节点，且实现执行CNOT(q[2]，q[4])的映射方案还有很多种，在此不进行穷举。但是在本申请的实际应用中，需要进行查找可行的所有swap插入方案，然后通过评估每个映射方案的不同成本，再确定最终目标映射。
2、构建评估所述映射方案的成本公式并计算映射方案的成本。
可选的，可以通过构建映射方案的成本公式：
Figure PCTCN2022112765-appb-000001
通过上述成本公式评估各个映射方案的成本，综合考虑了最短路径，两比特量子逻辑门保真度，测量保真度和退相干时间等多方面因素。通过加权求和得到各个swap方案的最终消耗成本。最终选择消耗成本最小的swap逻辑门插入方案，来更新当前映射。然后再回到操作层中判断是否存在可以直接执行的逻辑门。如此循环迭代，直至整个待执行量子线路中的所有逻辑门都映射到量子芯片拓扑结构的物理比特上。T 2为量子芯片比特的退相干时间，G swap为映射待映射逻辑门集合中所有逻辑门所需要引入的swap逻辑门个数，f double为两比特量子逻辑门保真度，f measure为测量保真度，a 1、a 2、a 3、a 4为成本表达式的预设权重系数。
S1204：根据所述每个逻辑门映射到量子芯片拓扑结构的成本，调整待执行量子程序的目标映射，以使所述目标映射的成本最低。
根据所述量子芯片拓扑结构、初始映射关系，依所述执行顺序正向遍历并计算每一逻辑门映射到所述量子芯片拓扑结构的成本，动态调整所述待执行量子程序的映射关系，直至依所述执行顺序正向遍历完成，得到目标正向映射关系。
根据所述目标正向映射关系，依所述执行顺序逆向遍历并计算每一逻辑门映射到所述量子芯片拓扑结构的成本，动态调整所述待执行量子程序的映射关系，直至依所述执行顺序逆向遍历完成，得到目标逆向映射关系。
继续进行正向逆向交替迭代映射，重复动态调整所述待执行量子程序的映射关系的步骤，以使所述目标映射的成本最低。
示例性的，图4为实施例提供的另一种待执行量子线路示意图。根据初始映射关系q[0]--Q[0]、q[1]--Q[1]、q[2]--Q[2]，q[3]--Q[3]、q[4]--Q[4]，依执行顺序正向遍历CNOT(q[0]，q[1])、CNOT(q[2]，q[4])、CNOT(q[0]，q[2])、CNOT(q[2]，q[4])、CNOT(q[1]，q[3])。首先依执行顺序正向遍历CNOT(q[0]，q[1])。由于逻辑比特相邻，当前映射关系不改变。当遍历至CNOT(q[2]，q[4])时，在一种可能的方案中：通过在Q[4]与Q[0]插入swap逻辑门，再通过Q[0]与Q[1]间插入swap逻辑门，实现将逻辑比特q[4]映射到物理比特Q[1]，达到可执行CNOT(q[2]，q[4])的目的。此时的映射关系为q[0]--Q[4]、q[1]--Q[0]、q[2]--Q[2]，q[3]--Q[3]、q[4]--Q[1]。继续遍历至CNOT(q[0]，q[2])。基于当前映射关系，可以通过在Q[2]与Q[3]插入swap逻辑门，实现将逻辑比特q[2]映射到物理比特Q[3]，达到可执行CNOT(q[0]，q[2])的目的。此时的映射关系为q[0]--Q[4]、q[1]--Q[0]、q[3]--Q[2]，q[2]--Q[3]、q[4]--Q[1]。继续遍历至CNOT(q[2]，q[4])。基于当前映射关系，可以通过在Q[2]与Q[3]插入swap逻辑门，实现将逻辑比特q[2]映射到物理比特Q[2]，达到可执行CNOT(q[2]，q[4])的目的。此时的映射关系为q[0]--Q[4]、q[1]--Q[0]、q[2]--Q[2]，q[3]--Q[3]、q[4]--Q[1]；继续遍历至CNOT(q[1]，q[3])。基于当前映射关系，可以通过在Q[2]与Q[3]插入swap逻辑门，再通过Q[1]与Q[2]间插入swap逻辑门，实现将逻辑比特q[3]映射到物理比特Q[1]，也达到可执行CNOT(q[1]，q[3])的目的。此时得到目标正向映射关系为q[0]--Q[4]、q[1]--Q[0]、q[4]--Q[2]，q[2]--Q[3]、q[3]--Q[1]。
此时，目标正向映射关系为q[0]--Q[4]、q[1]--Q[0]、q[4]--Q[2]，q[2]--Q[3]、q[3]--Q[1]。依执行顺序逆向遍历CNOT(q[1]，q[3])、CNOT(q[2]，q[4])、CNOT(q[0]，q[2])、CNOT (q[2]，q[4])及CNOT(q[0]，q[1])。计算每一逻辑门映射到量子芯片拓扑结构的成本。动态调整待执行量子程序的映射关系，如调整CNOT(q[1]，q[3])在当前目标正向映射关系下所映射的物理比特。随后调整上一个映射关系，即当前目标正向映射关系。继续调整余下每一逻辑门在上一个映射关系下所映射的物理比特，直至依所述执行顺序逆向遍历完成后得到的目标逆向映射关系，即：q[0]--Q[4]、q[1]--Q[0]、q[4]--Q[2]，q[2]--Q[3]、q[3]--Q[1]。
然后继续进行正向逆向交替迭代映射，重复动态调整待执行量子程序的映射关系的步骤，并依照成本公式：
Figure PCTCN2022112765-appb-000002
计算各个映射方案的映射成本，使目标映射的成本最低。
需要说明的是，两个不相邻的比特间可能存在多种引入swap逻辑门方案。但每个方案的保真度、噪声等各不相同，只有选择引入swap逻辑门个数较少、保真度高的方案才能有效的保证待执行量子线路执行准确率。如果在映射过程中，能够将操作较少的逻辑比特映射到退相干时间较短的物理比特上，可以实现物理比特资源利用最大化，同时也提高了量子线路的运行准确率。因此通过预设权重系数，选择保真度高、引入swap逻辑门个数少、将操作较少的逻辑比特映射到退相干时间较短的物理比特上，才能有效的保证量子线路执行准确率。
针对整个映射算法，可以对待执行量子线路进行了两次正向顺序映射和一次反向逆序映射。这是一种双向启发式映射算法思想。量子线路映射问题，在高比特、高深度量子线路场景下，是一个NP-hard问题。所以在高比特、高深度量子线路场景下，找到最优解的可能性极小，双向启发式映射算法是解决问题的主流思想。双向启发式映射算法的主要方法是先随机给定一个初始映射关系，然后再逐步迭代优化，不断逼近最优解，理论上迭代次数越多，优化效果越好。初始映射决定了算法优化的起点，所以在综合考虑时间成本的情况下，可以进行有限次的迭代，那么初始映射对最终映射的结果就会产生很大的影响。但基于目前现有技术无法给出一个全局考虑的初始映射，因此通过正向和逆向映射，可以综合考虑整个待执行量子线路中的全局逻辑门信息。先通过随机映射进行正向遍历映射，得到一个目标正向映射关系，然后通过目标正向映射关系再进行一次反向逆序遍历映射，来更新初始映射。通过不断进行正向逆向交替迭代映射或有限次的正向逆向交替迭代映射，以使所述目标映射的成本最低。
与现有技术相比，本申请首先获取待执行量子程序的有向无环图以及逻辑比特与物理比特的初始映射关系，根据待执行量子程序的有向无环图，确定待执行量子程序的待映射逻辑门集合的执行顺序，根据执行顺序和初始映射关系，分别确定待映射逻辑门集合中每个逻辑门映射到量子芯片拓扑结构的成本，根据每个逻辑门映射到量子芯片拓扑结构的成本，调整待执行量子程序的目标映射，以使目标映射的成本最低，解决因单个物理比特因素对整个量子线路产生影响的问题，并且可以确定量子芯片拓扑结构的最优映射线路，使得整个量子芯片的资源利用最大化。
图10为实施例提供的一种量子程序与量子芯片的映射装置的结构示意图。与图7所示的流程相对应，该装置可以包括：
获取模块701，用于获取待执行量子程序的有向无环图以及逻辑比特与物理比特的初始映射关系；
第一确定模块702，用于根据所述待执行量子程序的有向无环图，确定所述待执行量子程序的待映射逻辑门集合的执行顺序；
第二确定模块703，用于根据所述执行顺序和所述初始映射关系，分别确定所述待映射逻辑门集合中每个逻辑门映射到量子芯片拓扑结构的成本；
调整模块704，用于根据所述每个逻辑门映射到量子芯片拓扑结构的成本，调整待执行量子程序的目标映射，以使所述目标映射的成本最低。
所述获取模块包括：
获取单元，用于获取待执行量子程序中的节点；
确定单元，用于根据所述节点操作的量子比特，确定所述节点之间的关联关系；
生成单元，用于根据所述节点及节点之间的关联关系，生成与所述待执行量子程序对应的有向无环图，其中，所述有向无环图中的顶点表征节点，所述有向无环图中的边表征节点之间的关联关系，所述边的方向表征该边相连的顶点对应的节点被执行的时序关系。
所述第一确定模块，包括：
划分单元，用于根据所述待执行量子程序的有向无环图，将所述有向无环图中入度为零的节点的第一规则逻辑门集合的执行顺序，设为第一优先级，将所述有向无环图中入度为零的节点的第二规则逻辑门集合的执行顺序，设为第二优先级；
迭代单元，用于删除执行顺序划分完成的第一规则逻辑门集合，继续执行所述将所述有向无环图中入度为零的节点的第一规则逻辑门集合的执行顺序，设为第一优先级，将所述有向无环图中入度为零的节点的第二规则逻辑门集合的执行顺序，设为第二优先级的步骤，直至所述待映射逻辑门集合的执行顺序划分完成。
所述第二确定模块，包括：
映射单元，用于根据所述执行顺序和所述初始映射关系，分别获取每个逻辑门映射到量子芯片拓扑结构的映射方案；
评估单元，用于构建评估所述映射方案的成本公式并计算映射方案的成本。
所述调整模块，包括：
正向遍历单元，用于根据所述量子芯片拓扑结构、初始映射关系，依所述执行顺序正向遍历并计算每一逻辑门映射到所述量子芯片拓扑结构的成本，动态调整所述待执行量子程序的映射关系，直至依所述执行顺序正向遍历完成，得到目标正向映射关系；
反向遍历单元，用于根据所述目标正向映射关系，依所述执行顺序逆向遍历并计算每一逻辑门映射到所述量子芯片拓扑结构的成本，动态调整所述待执行量子程序的映射关系，直至依所述执行顺序逆向遍历完成，得到目标逆向映射关系；
调整单元，用于继续进行正向逆向交替迭代映射，重复动态调整所述待执行量子程序的映射关系的步骤，以使所述目标映射的成本最低。
根据一个实施例，可以至少缓解由于单个物理比特因素对整个量子线路产生影响的问题。此外，可以确定量子芯片拓扑结构的最优映射线路。此外，整个量子芯片的资源利用最大化。
实施例还提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计 算机程序被设置为运行时执行上述任一项中方法实施例中的步骤。
上述存储介质可以被设置为存储用于执行图2或7中的的计算机程序。
在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(Read-Only Memory，简称为ROM)、随机存取存储器(Random Access Memory，简称为RAM)、移动硬盘、磁碟或者光盘等各种可以存储计算机程序的介质。
实施例还提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述任一项中方法实施例中的步骤。
上述电子装置还可以包括传输设备以及输入输出设备，其中，该传输设备和上述处理器连接，该输入输出设备和上述处理器连接。
上述处理器可以被设置为通过计算机程序执行图2或7中的步骤。
实施例还提供了一种量子计算机操作系统，所述量子计算机操作系统根据实施例中提供的上述任一方法实施例实现构建待映射量子程序。
本申请的实施例还提供了一种量子计算机，所述量子计算机包括所述的量子计算机操作系统。
以上依据图式所示的实施例详细说明了实施例的构造、特征及作用效果，以上所述仅为实施例的较佳实施例，但实施例不以图面所示限定实施范围，凡是依照实施例的构想所作的改变，或修改为等同变化的等效实施例，仍未超出说明书与图示所涵盖的精神时，均应在实施例的范围内。

Claims (15)

  1. 一种量子程序与量子芯片的映射方法，其特征在于，所述方法包括：
    获取量子芯片中物理比特的拓扑结构、初始量子程序的逻辑门集合以及逻辑比特与物理比特的初始映射关系；
    确定初始量子程序的逻辑门集合的执行时序；
    根据所述物理比特的拓扑结构和所述初始映射关系，依所述执行时序调整每一逻辑门对应的逻辑比特与物理比特的映射关系，得到最终映射关系；
    根据所述最终映射关系，构建与初始量子程序等同的待映射量子程序，以使所述逻辑门集合中每个逻辑门映射到量子芯片中物理比特的拓扑结构的成本最低。
  2. 根据权利要求1所述的方法，其中，构建与初始量子程序等同的待映射量子程序包括：
    根据所述最终映射关系，构建与初始量子程序等同的待映射量子程序，以使所述待映射量子程序中的SWAP量子逻辑门数量最少。
  3. 根据权利要求2所述的方法，其特征在于，还包括：
    获取待执行量子程序的有向无环图，
    其中，确定初始量子程序的逻辑门集合的执行时序包括：根据所述待执行量子程序的有向无环图，确定确定初始量子程序的逻辑门集合的执行时序，
    其中，得到最终映射关系还包括：根据所述执行时序和所述初始映射关系，分别确定所述逻辑门集合中每个逻辑门映射到量子芯片中物理比特的拓扑结构的成本，
    其中，构建与初始量子程序等同的待映射量子程序包括：
    根据所述成本，调整待执行量子程序的最终映射关系，以使所述最终映射关系的成本最低。
  4. 根据权利要求1或3所述的方法，其特征在于，所述初始量子程序的逻辑门集合包括：
    第一规则逻辑门集合，其中，所述第一规则逻辑门集合包括：单比特量子逻辑门和逻辑比特相邻的两比特量子逻辑门；
    第二规则逻辑门集合，其中，所述第二规则逻辑门集合包括：逻辑比特不相邻的两比特量子逻辑门。
  5. 根据权利要求4所述的方法，其特征在于，所述确定初始量子程序的逻辑门集合的执行时序，包括：
    获取初始量子程序对应的量子线路；
    遍历所述量子线路，将每个量子比特第一时序的第一规则逻辑门集合的执行时序，设为优先执行时序，将每个量子比特第一时序的第二规则逻辑门集合的执行时序，设为次优先执行时序；
    删除执行时序划分完成的逻辑门，继续执行所述将每个量子比特第一时序的第一规则逻辑门集合的执行时序，设为优先执行时序，将每个量子比特第一时序的第二规则逻辑门集合的执行时序，设为次优先执行时序的步骤，直至所述量子线路逻辑门的执行时序划分完成。
  6. 根据权利要求5所述的方法，其特征在于，所述根据所述物理比特的拓扑结构和所述初始映射关系，依所述执行时序调整每一逻辑门对应的逻辑比特与物理比特的映射关系，得到最终映射关系，包括：
    根据物理比特的拓扑结构、所述初始映射关系，依所述执行时序正向遍历每一逻辑门并调整所述每一逻辑门在上一个映射关系下所映射的物理比特，调整所述上一个映射关系，直至依所述执行时序正向遍历完成，得到目标正向映射关系；
    根据所述目标正向映射关系，依所述执行时序逆向遍历每一逻辑门并调整所述每一逻辑门在上一个映射关系下所映射的物理比特，调整所述上一个映射关系，直至依所述执行时序逆向遍历完成后得到的目标逆向映射关系，作为所述最终映射关系。
  7. 根据权利要求6所述的方法，其特征在于，所述根据所述最终映射关系，构建与初始量子程序等同的待映射量子程序，包括：
    根据所述最终映射关系，在量子逻辑门集合中相应位置插入依所述执行时序运行每一逻辑门对应生成的SWAP量子逻辑门，将插入完成后得到的量子程序，确定为与初始量子程序等同的待映射量子程序。
  8. 根据权利要求4所述的方法，其特征在于，分别确定所述逻辑门集合中每个逻辑门映射到量子芯片中物理比特的拓扑结构的成本，包括：
    根据所述执行时许和所述初始映射关系，分别获取每个逻辑门映射到量子芯片中物理比特的拓扑结构的映射方案；
    构建评估所述映射方案的成本公式并计算映射方案的成本。
  9. 根据权利要求8所述的方法，其特征在于，调整待执行量子程序的最终映射关系，包括：
    根据所述量子芯片中物理比特的拓扑结构、初始映射关系，依所述执行时序正向遍历并计算每一逻辑门映射到所述量子芯片中物理比特的拓扑结构的成本，动态调整所述待执行量子程序的映射关系，直至依所述执行顺序正向遍历完成，得到目标正向映射关系；
    根据所述目标正向映射关系，依所述执行时序逆向遍历并计算每一逻辑门映射到所述量子芯片中物理比特的拓扑结构的成本，动态调整所述待执行量子程序的映射关系，直至依所述执行时序逆向遍历完成，得到目标逆向映射关系；
    继续进行正向逆向交替迭代映射，重复动态调整所述待执行量子程序的映射关系的步骤，以使所述最终映射关系的成本最低。
  10. 根据权利要求9所述的方法，其特征在于，所述评估所述映射方案的成本表达式为：
    Figure PCTCN2022112765-appb-100001
    其中，T 2为量子芯片比特的退相干时间，G swap为映射待映射逻辑门集合中所有逻辑门所需要引入的swap逻辑门个数，f double为两比特量子逻辑门保真度，f measure为测量保真度，a 1、a 2、a 3、a 4为成本表达式的预设权重系数。
  11. 一种量子程序与量子芯片的映射装置，其特征在于，所述装置包括：
    获取模块，用于获取量子芯片中物理比特的拓扑结构、初始量子程序的逻辑门集合以及逻辑比特与物理比特的初始映射关系；
    确定模块，用于确定初始量子程序的逻辑门集合的执行时序；
    调整模块，用于根据所述物理比特的拓扑结构和所述初始映射关系，依所述执行时序调整每一逻辑门对应的逻辑比特与物理比特的映射关系，得到最终映射关系；
    构建模块，用于根据所述最终映射关系，构建与初始量子程序等同的待映射量子程序，以使所述逻辑门集合中每个逻辑门映射到量子芯片中物理比特的拓扑结构的成本最低。
  12. 一种存储介质，其特征在于，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行所述权利要求1至10任一项中所述的方法。
  13. 一种电子装置，包括存储器和处理器，其特征在于，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行所述权利要求1至10任一项中所述的方法。
  14. 一种量子计算机操作系统，其特征在于，所述量子计算机操作系统根据权利要求1至10任一项所述的方法实现构建待映射量子程序。
  15. 一种量子计算机，其特征在于，所述量子计算机包括权利要求14所述的量子计算机操作系统。
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CN110825375A (zh) * 2019-10-12 2020-02-21 合肥本源量子计算科技有限责任公司 一种量子程序的转化方法、装置、存储介质和电子装置
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CN116342961A (zh) * 2023-03-30 2023-06-27 重庆师范大学 基于混合量子神经网络的时间序列分类深度学习系统
CN116342961B (zh) * 2023-03-30 2024-02-13 重庆师范大学 基于混合量子神经网络的时间序列分类深度学习系统

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