WO2023051577A1 - 量子程序与量子芯片的映射方法和量子操作系统及计算机 - Google Patents

量子程序与量子芯片的映射方法和量子操作系统及计算机 Download PDF

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WO2023051577A1
WO2023051577A1 PCT/CN2022/122010 CN2022122010W WO2023051577A1 WO 2023051577 A1 WO2023051577 A1 WO 2023051577A1 CN 2022122010 W CN2022122010 W CN 2022122010W WO 2023051577 A1 WO2023051577 A1 WO 2023051577A1
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quantum
executed
program
fidelity
chip
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PCT/CN2022/122010
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French (fr)
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窦猛汉
汪文涛
方圆
赵东一
王晶
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合肥本源量子计算科技有限责任公司
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Priority claimed from CN202111145141.9A external-priority patent/CN115879562A/zh
Priority claimed from CN202111194665.7A external-priority patent/CN115983392A/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena

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  • the present application belongs to the technical field of quantum compilation technology, in particular, a quantum program-to-quantum chip mapping method, a quantum program-to-quantum chip mapping device, a storage medium, an electronic device, a quantum operating system, and a quantum computer.
  • Quantum computer is a kind of physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information. When a device processes and computes quantum information and runs quantum algorithms, it is a quantum computer. Quantum computer has become a key technology under research because of its ability to deal with mathematical problems more efficiently than ordinary computers, for example, it can speed up the time to crack RSA keys from hundreds of years to hours.
  • An object of the embodiment is to provide a mapping scheme between a quantum program and a quantum chip, to solve the problem of randomness in the initial mapping relationship of the quantum program to be executed, and to determine the optimal initial mapping of the quantum program to be executed, so that the initial The fidelity of the mapping is high, and the utilization of quantum chip resources is maximized.
  • One embodiment provides a mapping method between a quantum program and a quantum chip.
  • the method includes: obtaining a quantum program to be executed and a quantum chip that can be adapted to run; constructing a weighted circuit diagram corresponding to the quantum program to be executed; according to the Including the circuit diagram and the fidelity of the quantum chip, determine the initial mapping of the quantum program to be executed, so that the fidelity corresponding to the initial mapping of the quantum program to be executed is the highest.
  • An embodiment of the present application provides a method for determining the mapping relationship of a quantum program, the method comprising: obtaining the quantum program to be executed and the quantum chip topology, the topology used to represent the physical qubits in the quantum chip and the connection relationship between the physical qubits; constructing a weighted undirected graph corresponding to the quantum program to be executed; according to the weighted undirected graph, determining the first parameter of each logical qubit in the quantum program to be executed; according to According to the quantum chip topology, obtain the second parameter of each physical qubit in the quantum chip; determine the mapping of the quantum program to be executed according to the first parameter, the second parameter and the fidelity of the quantum chip relationship, so that the fidelity corresponding to the mapping relationship of the quantum program to be executed is the highest.
  • An embodiment of the present application provides a quantum program and quantum chip mapping device, the device includes: an acquisition module, used to acquire the quantum program to be executed and a quantum chip that can be adapted to run; a construction module, used to construct the quantum chip to be executed Execute the weighted circuit diagram corresponding to the quantum program; a determination module, configured to determine the initial mapping of the quantum program to be executed according to the weighted circuit diagram and the fidelity of the quantum chip, so that the quantum program to be executed The procedural initial mapping corresponds to the highest fidelity.
  • An embodiment of the present application provides a device for determining the mapping relationship of a quantum program.
  • the device includes: a first acquisition module, used to acquire the quantum program to be executed and the topology of the quantum chip, and the topology is used to represent the The physical qubits in the quantum chip and the connection relationship between the physical qubits; the building module is used to construct the weighted undirected graph corresponding to the quantum program to be executed; the first determination module is used to according to the weighted undirected graph, Determine the first parameter of each logical qubit in the quantum program to be executed; the second acquisition module is used to acquire the second parameter of each physical qubit in the quantum chip according to the quantum chip topology; the second Two determining modules, used to determine the mapping relationship of the quantum program to be executed according to the fidelity of the first parameter, the second parameter and the quantum chip, so that the fidelity corresponding to the mapping relationship of the quantum program to be executed is Highest.
  • Yet another embodiment of the present application provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute the method described in any one of the above when running.
  • Yet another embodiment of the present application provides an electronic device, including a memory and a processor, a computer program is stored in the memory, and the processor is configured to run the computer program to perform any of the above-mentioned Methods.
  • Another embodiment of the present application provides a quantum computer operating system, which implements the mapping between quantum programs and quantum chips according to any of the methods described above.
  • Another embodiment of the present application provides a quantum computer, which includes the quantum computer operating system.
  • the fidelity corresponding to the initial mapping of the quantum program to be executed can be made the highest, the problem of randomness in constructing the initial mapping relationship of the quantum program to be executed can be solved, the number of algorithm executions can be reduced, the execution performance can be optimized, and the quantum program to be executed can be determined
  • the optimal initial mapping of the program makes the fidelity of the initial mapping high and maximizes the utilization of quantum chip resources.
  • mapping relationship of the quantum program to be executed reduces the number of algorithm executions, optimize the execution performance, and determine the optimal initial mapping relationship of the quantum program to be executed, so that the obtained mapping relationship has high fidelity High, maximize the utilization of quantum chip resources.
  • Fig. 1 is a block diagram of the hardware structure of a computer terminal of a method for determining the initial mapping of a quantum program provided by an embodiment
  • Fig. 2 is a schematic flow chart of a method for determining the initial mapping of a quantum program provided by the embodiment
  • Fig. 3 is a schematic diagram of a weighted circuit diagram provided by the embodiment
  • Fig. 4 is a schematic diagram of the topological structure of the physical bits of a quantum chip provided by the embodiment
  • Fig. 5 is a schematic structural diagram of an apparatus for determining an initial mapping of a quantum program provided by an embodiment.
  • FIG. 6 is a schematic flowchart of a method for determining a quantum program mapping relationship provided by an embodiment
  • Fig. 7 is a schematic structural diagram of an apparatus for determining a quantum program mapping relationship provided by an embodiment.
  • the embodiment firstly provides a method for determining the initial mapping of a quantum program, which can be applied to electronic equipment, such as computer terminals, specifically, ordinary computers, quantum computers, and the like.
  • Fig. 1 is a hardware structural block diagram of a computer terminal of a method for determining an initial mapping of a quantum program provided by an embodiment.
  • the computer terminal may include one or more (only one is shown in Figure 1) processors 102 (processors 102 may include but not limited to processing devices such as microprocessor MCU or programmable logic device FPGA, etc.) and a memory 104 for storing data.
  • the above-mentioned computer terminal may further include a transmission device 106 and an input and output device 108 for communication functions.
  • the structure shown in FIG. 1 is only for illustration, and it does not limit the structure of the above computer terminal.
  • the computer terminal may also include more or fewer components than shown in FIG. 1 , or have a different configuration than that shown in FIG. 1 .
  • the memory 104 can be used to store software programs and modules of application software, such as program instructions/modules corresponding to a method for determining the initial mapping of a quantum program in the embodiment of the present application, and the processor 102 runs the software program stored in the memory 104 And modules, so as to execute various functional applications and data processing, that is, to realize the above-mentioned method.
  • the memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • the memory 104 may further include a memory that is remotely located relative to the processor 102, and these remote memories may be connected to a computer terminal through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • the transmission device 106 is used to receive or transmit data via a network.
  • the specific example of the above-mentioned network may include a wireless network provided by the communication provider of the computer terminal.
  • the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet.
  • the transmission device 106 may be a radio frequency (Radio Frequency, RF) module, which is used to communicate with the Internet in a wireless manner.
  • RF Radio Frequency
  • a quantum program when running on a quantum chip (also called a physical chip), the state of each physical bit is unstable for multiple physical bits on the same physical chip, for example, a two-bit quantum logic gate Factors such as operating noise, measurement noise, and decoherence time of physical bits will interfere with the effective use of physical bits, thus having an unknown impact on the operation results of the entire quantum circuit.
  • a two-bit quantum logic gate Factors such as operating noise, measurement noise, and decoherence time of physical bits will interfere with the effective use of physical bits, thus having an unknown impact on the operation results of the entire quantum circuit.
  • the decoherence time of each physical bit is different, if the decoherence time of a certain physical bit is short and the quantum circuit depth that the entire quantum chip can run is limited, it will inevitably lead to the waste of other physical bit resources.
  • the unfit two-qubit logic gates are converted into the The quantum logic gates supported by the chip.
  • the quantum program contains the CNOT(q1, q3) quantum logic gate.
  • the quantum chip supports the CNOT gate, the physical qubits q1 and q3 in the quantum chip are not directly connected, so they cannot be directly executed. Therefore, it is necessary to exchange the two quantum logic gates in the quantum program with quantum logic gates that can be directly executed by the chip.
  • the existing exchange method is simply described as: according to the connection relationship between the qubits on the quantum chip, find the connection path between the two qubits q1 and q3 operated by CNOT , assuming that the qubits passed by the path are q1, q2, executing CNOT(q1, q3) is equivalent to executing in sequence: SWAP(q1, q2), SWAP(q2, q3), CNOT(q2, q3), SWAP( q3, q2), SWAP (q2, q1).
  • the SWAP gate means to perform a swap operation on qubits.
  • FIG. 2 is a schematic flowchart of a mapping method between a quantum program and a quantum chip provided in an embodiment.
  • S201 Obtain a quantum program to be executed and a quantum chip that can be adapted to run.
  • S5201 Obtain the quantum program to be executed and the quantum chip topology, which is used to represent the physical qubits in the quantum chip and the connection relationship between the physical qubits.
  • the quantum program to be executed is mainly composed of tens, hundreds, or even tens of thousands of quantum logic gates.
  • the execution process of a quantum program is the process of executing all quantum logic gates according to a certain time sequence. It should be noted that the time sequence refers to the time sequence in which a single quantum logic gate is executed.
  • the quantum chip topology is used to represent the connection relationship between physical qubits in electronic devices, and the number of physical qubits contained in the topology needs to be greater than or equal to the number of qubits required by the quantum program to be executed, so that the quantum chip conforms to the requirements of the quantum program. execution conditions.
  • a quantum chip that can be adapted to run specifically means that the number of physical qubits contained in the topology of the quantum chip is greater than or equal to the number of qubits required by the quantum program to be executed.
  • the qubit structure in the quantum chip is generally called the physical qubit
  • the object bit operated in the quantum circuit is called the logical qubit.
  • the mapping relationship between logical qubits and physical qubits refers to the "corresponding" relationship between logical qubits and physical qubits.
  • circuit diagram The application of the circuit diagram is very extensive, and it can be a directed graph or an undirected graph.
  • the circuit diagram can be used to represent the driver dependencies between events, the scheduling between tasks, and so on.
  • the weighted road map can refer to the importance of a certain factor or index relative to a certain thing in the edge between the vertices in the road map, reflecting the percentage of a certain factor or index, or emphasizing the relative importance of a certain factor or index degree.
  • S5202 Construct a weighted undirected graph corresponding to the quantum program to be executed.
  • Undirected graphs are widely used and can be used to represent driver dependencies between events, scheduling between tasks, and so on.
  • a weighted undirected graph can mean that the edges between the vertices in the undirected graph contain the importance of a certain factor or indicator relative to a certain thing, reflect the percentage of a certain factor or indicator, or emphasize the importance of a certain factor or indicator relative importance.
  • constructing a weighted circuit diagram corresponding to the quantum program to be executed may include the following steps:
  • S2021 Acquire quantum logic gates in the quantum program to be executed and qubits operated by the quantum logic gates.
  • step S5202 in FIG. 6 may include step S52021: acquiring the quantum logic gates in the quantum program to be executed and the logic qubits for their operations.
  • the quantum program to be executed can be understood as an operation sequence, which mainly includes quantum logic gates, qubits operated by quantum logic gates, and measurement operations (Measure).
  • S2022 Construct a weighted circuit diagram corresponding to the quantum program to be executed based on the quantum logic gate and the qubit operated by the quantum logic gate, wherein the weighted circuit diagram includes: vertices, undirected edges, and edges The vertex is used to represent the qubit operated by the quantum logic gate, the undirected edge is used to represent the quantum logic gate, and the weight of the edge is determined according to the number of quantum logic gates operating the same qubit.
  • step S5202 in FIG. 6 may include step S2022: construct a weighted undirected graph corresponding to the quantum program to be executed based on the quantum logic gate and the logical qubits operated by it, wherein the weighted undirected graph Including: vertices, undirected edges and edge weights, the vertices are used to represent the logical qubits operated by the quantum logic gate, the undirected edges are used to represent the quantum logic gates, and the weights of the edges are based on the operation The number of quantum logic gates of the same qubit is determined.
  • the logical bits of its operation are q[0], q[1], q[2], q[3] respectively, so the weighted circuit diagram corresponding to the quantum program to be executed has a total of 4 vertices; there are CNOT(q[0], q[1]), CNOT(q[0], q[2]), CNOT(q[0], q[3]), CNOT( q[1], q[3]), CNOT(q[0], q[1]), CNOT(q[0], q[1]), CNOT(q[0], q[1]), CNOT(q[1], q[3])7
  • the quantum logic gates that operate the same qubit are 3 CNOT(q[0],q[1]), 2 CNOT(q[1],q[3]), CNOT( 1 each of q[0], q[2]) and CNOT(q[0], q[
  • S203 Determine an initial mapping of the quantum program to be executed according to the weighted circuit diagram and the fidelity of the quantum chip, so that the fidelity corresponding to the initial mapping of the quantum program to be executed is the highest.
  • the fidelity of the quantum chip includes the fidelity of double quantum logic gates between every two physical bits in the topology of the quantum chip and the measurement fidelity corresponding to each physical bit.
  • Fidelity is a measure of the similarity between the output of an electronic device and the reproduction of an input signal. The higher the fidelity, the more realistic the sound or image output by the electronic device. In a quantum chip, the higher the fidelity, the smaller the noise, and the smaller the error of the measurement result obtained after running a quantum program, the closer to the expected execution result.
  • S5203 According to the weighted undirected graph, determine a first parameter of each logical qubit in the quantum program to be executed.
  • the first parameter of each logical qubit is determined according to the degree of each vertex in the weighted undirected graph, wherein the degree is determined according to the sum of weights of adjacent undirected edges of each vertex.
  • the weighted undirected graph there are four vertices in the weighted undirected graph, namely vertices q[0], q[1], q[2] and q[3].
  • the edge has a weight of 1; the undirected edge between q[0] and q[3] has a weight of 1. Therefore, the first parameter value of vertex q[0] is the sum of the weights of its three adjacent undirected edges is 5. Similarly, the first parameter value of vertex q[1] is 5, and the weight of vertex q[2] is respectively obtained.
  • S5204 Acquire the second parameter of each physical qubit in the quantum chip according to the quantum chip topology.
  • the quantum chip topology in the prior art may be a one-dimensional chain structure, that is, all physical qubits are on one line; it may also present a two-dimensional chain structure, for example, the quantum chip topology shown in Figure 3, It is a two-dimensional chain structure.
  • Obtaining the second parameter of each physical qubit in the quantum chip may include the following steps:
  • the second parameter of each physical qubit is determined according to the number of connection edges of each physical qubit.
  • the relationship between each physical qubit connection edge in the quantum chip is: Q[0] is connected with Q[1] and Q[3], Q[4] Connect with Q[1], Q[3] and Q[5], Q[2] connect with Q[1], Q[5], Q[5] connect with Q[2] and Q[4], so
  • the second parameter value of physical qubit Q[0] is 2, the second parameter value of Q[1] is 3, the second parameter value of Q[2] is 2, and the second parameter value of Q[3] is 2 , the second parameter value of Q[4] is 3, and the second parameter value of Q[5] is 2.
  • S5205 According to the fidelity of the first parameter, the second parameter and the quantum chip, determine the mapping relationship of the quantum program to be executed, so that the corresponding fidelity of the mapping relationship of the quantum program to be executed The highest degree.
  • the fidelity of the quantum chip includes the fidelity of double quantum logic gates between every two physical qubits in the topology of the quantum chip and the measurement fidelity corresponding to each physical qubit.
  • Fidelity is a measure of the similarity between the output of an electronic device and the reproduction of an input signal. The higher the fidelity, the more realistic the sound or image output by the electronic device. In a quantum chip, the higher the fidelity, the smaller the noise, and the smaller the error of the measurement result obtained after running a quantum program, the closer to the expected execution result.
  • FIG. 4 is a schematic diagram of the topological structure of a quantum chip physical bit provided by the embodiment.
  • the quantum chip includes 6 physical bits, respectively Q[0], Q[1], Q[ 2], Q[3], Q[4], Q[5], these six physical bits can be capacitively coupled, and only adjacent physical bits have a coupling relationship.
  • Q[0] is connected with Q[1] and Q[3]
  • Q[4] is connected with Q[1], Q[3] and Q[5]
  • Q[2] is connected with Q[1]
  • Q [5] is connected
  • Q[5] is connected with Q[2] and Q[4].
  • the measurement fidelity corresponding to Q[0], Q[1], Q[2], Q[3], Q[4], Q[5] are 0.95, 0.94, 0.93, 0.92, 0.91, 0.90 respectively .
  • the fidelity of the double-quantum logic gate between every two physical bits in the quantum chip topology, the specific acquisition method is: for the physical bit that can directly map the double-quantum logic gate, the fidelity is the fidelity of the corresponding double-quantum logic gate
  • the fidelity of the double quantum logic gate between Q[0] and Q[1] can be directly measured as 0.9
  • the fidelity of the double quantum logic gate between Q[0] and Q[3] is 0.9
  • the Q The fidelity of the double quantum logic gate between [3] and Q[4] is 0.95
  • the fidelity of the double quantum logic gate between Q[4] and Q[1] is 0.85
  • the fidelity of the double quantum logic gate between Q[2] and Q[5] is 0.75
  • the fidelity of the double quantum logic gate between Q[4] and Q[5] is 0.8. degree is 0.7; for physical bits that cannot be directly mapped to dual quantum logic gates, it is necessary to use SWAP quantum
  • the CNOT dual quantum logic gate can be directly mapped, that is, the fidelity of the dual quantum logic gate between Q[0] and Q[1] is 0.9; and if you want to map the CNOT double quantum logic gate on the physical bits Q[0], Q[2], optionally, the path to obtain the fidelity of the physical bits Q[0], Q[2] can be inserted SWAP(q[0], q[1]) and CNOT(q[1], q[2]), SWAP(q[0], q[1]) double quantum logic gate fidelity is corresponding to CNOT(q [0], q[1]) is the cubic of the fidelity of a two-quantum logic gate, so SWAP(q[0],q[1]) and CNOT(q[1],q[2]) correspond to The logic gate fidelity is 0.5832 (0.9*0.9*0.9*0.8).
  • the path to obtain the fidelity of physical bits Q[0], Q[4] can be to insert SWAP(q[0 ], q[3]) and CNOT(q[3], q[4]), so the fidelity of the double quantum logic gate corresponding to CNOT(q[0], q[4]) is 0.69255(0.9*0.9* 0.9*0.95).
  • the following table 1 is a statistical table of the fidelity of the CNOT double-quantum logic gate applied between each qubit.
  • Table 1 Statistical table of fidelity of CNOT dual quantum logic gates applied between qubits
  • determining the initial mapping of the quantum program to be executed may include:
  • Step 1 According to the weighted line graph, construct a first associative container for storing undirected edges and edge weight information of the weighted line graph.
  • a first associative container for storing undirected edges and edge weight information of the weighted line graph is constructed.
  • the first associative container may be a storage container of a standard template library (Standard Template Library, STL), which can provide one-to-one data processing capabilities.
  • STL Standard Template Library
  • the storage information in the first associative container is: (q[0], q[1]): 3, (q[ 1], q[3]): 2, (q[0], q[2]): 1, (q[0], q[3]): 1.
  • Step 2 traverse the first associative container, and determine the mapping priority of the quantum program node to be executed, wherein the mapping priority is arranged in descending order according to the weight.
  • the weight of the node CNOT(q[0],q[1]) is 3, and the node CNOT(q[ 1], q[3]) has a weight of 2, the node CNOT(q[0], q[2]) has a weight of 1, and the node CNOT(q[0], q[3]) has a weight of 1, according to The weight size determines the mapping order of the quantum program nodes to be executed in turn.
  • Step 3 According to the mapping priority of the quantum program node to be executed and the fidelity of the quantum chip, sequentially determine the mapping relationship of the quantum program node to be executed.
  • the first node CNOT(q[0], q[1]) with the highest mapping priority in the quantum program to be executed is prioritized, that is, CNOT(q[0], q[1]) is first mapped to the quantum The highest fidelity position in the chip.
  • calculating the fidelity of a quantum chip can be performed by the following formula:
  • the first node in the first associative container is deleted to obtain a second associative container.
  • the first node CNOT(q[0], q[1]) in the first associative container is deleted to obtain the second associative container.
  • the storage information in the second associative container is: (q[1], q[3]): 2, (q[0], q[2]): 1, (q[0], q[3]): 1.
  • a second mapping relationship of the second node is determined based on the second node and the current fidelity of the quantum chip.
  • the second node that is, the second node CNOT(q[1], q[3]) with the highest mapping priority in the quantum program to be executed is processed first, that is, CNOT( q[1], q[3]) are mapped to the positions with the highest fidelity in current quantum chips.
  • Table 3 Statistical table of current quantum chip fidelity
  • the second mapping relationship of the second node is q[1]--Q[1] and q[3]--Q[3].
  • Table 4 Statistical table of current quantum chip fidelity
  • the current second mapping relationship of the current second node is q[0]--Q[0] and q[2]--Q[4].
  • Delete the current second node CNOT(q[0], q[2]) in the second associative container update the second associative container, that is, delete the storage information (q[0], q[2]): 1, at this time, The second node does not exist in the second associative container.
  • the second node does not exist in the second associative container, obtain the mapping relationship of all nodes determined by the quantum program to be executed.
  • the mapping relationship of all nodes determined by the quantum program to be executed respectively q[0]--Q [0] and q[1]--Q[1], q[1]--Q[1] and q[3]--Q[3], q[0]--Q[0] and q[ 2]--Q[4].
  • Step 4 Arranging the sequentially determined mapping relationships of the quantum program nodes to be executed in order of generation to obtain the initial mapping of the quantum program to be executed.
  • mapping relations q[0]--Q[0] and q[1]--Q[1], q[1]--Q[1] and q[3]--Q[3], q[0]--Q[0] and q[2]--Q[4] are arranged according to the order of generation, that is, the initial mapping relationship of the quantum program to be executed is obtained: q [0]--Q[0], q[1]--Q[1], q[3]--Q[3], and q[2]--Q[4].
  • the quantum program to be executed may include single-bit quantum logic gates, two-bit quantum logic gates and multi-bit quantum logic gates, but before determining the corresponding weighted circuit diagram of the quantum program to be executed, the multi-bit Quantum logic gates are transformed into a combination of single-bit quantum logic gates and two-bit quantum logic gates.
  • the single-bit quantum logic gate can directly map logical bits to physical bits
  • the single-bit quantum logic gate obtained after conversion and the single-quantum logic gate existing in the quantum program to be executed before conversion can be deleted (without affecting the mapping relationship) , and then construct a weighted circuit diagram corresponding to the quantum program to be executed based on the two-bit quantum logic gate obtained after conversion and the two-bit quantum logic gate existing in the quantum program to be executed before conversion.
  • a quantum program to be executed including two-bit quantum logic gates is taken as an example.
  • the weighted circuit diagram corresponding to the quantum program to be executed is constructed, and the initial mapping of the quantum program to be executed is determined according to the weighted circuit diagram and the fidelity of the quantum chip , so that the fidelity of the initial mapping of the quantum program to be executed is the highest, solve the problem of randomness in constructing the initial mapping relationship of the quantum program to be executed, reduce the number of algorithm executions, optimize the execution performance, and determine the optimal initial mapping of the quantum program to be executed Mapping, so that the fidelity of the initial mapping is high and the utilization of quantum chip resources is maximized.
  • determining the mapping relationship of the quantum program to be executed according to the first parameter, the second parameter and the fidelity of the quantum chip may include:
  • Step 1 Determine a first logical qubit in the quantum program to be executed according to the first parameter, wherein the first logical qubit has the largest value of the first parameter.
  • a first associative container for storing vertices and first parameters of the weighted undirected graph is constructed.
  • the first associative container may be a storage container of a standard template library (Standard Template Library, STL), which can provide one-to-one data processing capabilities.
  • STL Standard Template Library
  • the storage information in the first associative container is: q[0]: 5, q[1]: 5, q[2]: 1, q[3]: 3.
  • the first parameter value of logical qubit q[0] is 5
  • the first parameter value of logical qubit q[1] is 5
  • the first parameter value of logical qubit q[2] is 1
  • the first parameter value of q[3] is 3, and the mapping order of the logical qubits in the quantum program to be executed is sequentially determined according to the first parameter value.
  • Step 2 Based on the second parameter and the fidelity of the quantum chip, determine a first mapping relationship of the first logical qubit.
  • the physical qubit with the highest second parameter is obtained, that is, the physical qubit Q[1] and Q[4], and the second parameter values of the two are equal to is 3, and at the same time, since the measurement fidelity of Q[1] is greater than that of Q[4], the first logical qubit q[0] is mapped to the physical qubit Q[1], then it can be determined that The first mapping relationship q[0]--Q[1] of the first logical qubit q[0].
  • Step 3 Delete the first logical qubit, and determine whether there is a second logical qubit in the quantum program to be executed, wherein the first parameter value of the second logical qubit is the largest.
  • the first logical qubit q[0] in the first associative container is deleted to obtain the second associative container.
  • the storage information in the second associative container is: q[1]:5, q[2] :1, q[3]:3.
  • a second mapping relationship of the second logical qubit is determined based on the current second parameter and the fidelity of the quantum chip.
  • the first parameter value of the second logical qubit q[1] is the largest, and the physical qubit with the highest fidelity in the current quantum chip is selected for mapping, because q[0] is mapped, and because the quantum chip topology In the structure, Q[1] has been mapped, so it is necessary to find the highest fidelity physical qubit in Q[0], Q[2], Q[3], Q[4], Q[5], and consider
  • the overall fidelity of the circuit, according to the fidelity calculation method is: The calculation results are shown in Table 5 below.
  • Table 5 Statistical table of current quantum chip fidelity
  • the second mapping relationship of the second logical qubit q[1] is q[1]--Q[0].
  • Deleting the second logical qubit updating the logical qubit in the quantum program to be executed, returning to the step of determining whether there is a second logical qubit in the quantum program to be executed, until the quantum until the second logical qubit does not exist in the program.
  • the first parameter value of the second logical qubit q[3] is the largest, and the physical qubit with the highest fidelity in the current quantum chip is selected for mapping. Since q[0] and q[1] are mapped, And since Q[0] and Q[1] have been mapped in the quantum chip topology, it is necessary to find the highest fidelity physical Qubits, while considering the overall fidelity of the circuit, according to the fidelity calculation method, we get: The calculation results are shown in Table 6 below.
  • the second mapping relationship of the second logical qubit q[3] is q[3]--Q[4].
  • the first parameter value of the second logical qubit q[2] is the largest, and the physical qubit with the highest fidelity in the current quantum chip is selected for mapping, because q[0], q[1], q[ 3] is mapped, and since Q[0], Q[1], Q[4] have been mapped in the quantum chip topology, it is necessary to find the guaranteed The physical qubit with the highest fidelity, while considering the overall fidelity of the circuit, according to the calculation method of fidelity, we get: The calculation results are shown in Table 7 below.
  • Table 7 Statistical table of current quantum chip fidelity
  • the second mapping relationship of the second logical qubit q[2] is q[2]--Q[2].
  • Step 4 If the second logical qubit does not exist in the quantum program to be executed, obtain the mapping relationship of all logical qubits determined by the quantum program to be executed.
  • mapping relations determined by the quantum programs to be executed are arranged according to the order of generation, and the initial mapping relations of the quantum programs to be executed are obtained: q[0]--Q[1], q[1]--Q[0] , q[3]--Q[4] and q[2]--Q[2].
  • the quantum program to be executed may include single-bit quantum logic gates, two-bit quantum logic gates and multi-bit quantum logic gates, but before determining the corresponding weighted undirected graph of the quantum program to be executed, it is first necessary to Bit quantum logic gates are transformed into a combination of single-bit quantum logic gates and two-bit quantum logic gates.
  • the single-bit quantum logic gate can directly map logical qubits to physical qubits
  • the single-bit quantum logic gate obtained after conversion and the single-quantum logic gate that exists in the quantum program to be executed before conversion can be deleted (without affecting the mapping relationship), and then construct a weighted undirected graph corresponding to the quantum program to be executed based on the two-bit quantum logic gate obtained after conversion and the two-bit quantum logic gate existing in the quantum program to be executed before conversion.
  • a quantum program to be executed including two-bit quantum logic gates is taken as an example.
  • this application first obtains the quantum program to be executed and the topology structure of the quantum chip, constructs the weighted undirected graph corresponding to the quantum program to be executed, and then determines the quantum program to be executed according to the weighted undirected graph.
  • Fig. 5 is a schematic structural diagram of a quantum program initial mapping determination device provided by an embodiment, corresponding to the process shown in Fig. 2, the device may include:
  • An acquisition module 501 configured to acquire a quantum program to be executed and a quantum chip that can be adapted to run;
  • a construction module 502 configured to construct a weighted circuit diagram corresponding to the quantum program to be executed
  • a determination module 503 configured to determine the initial mapping of the quantum program to be executed according to the weighted circuit diagram and the fidelity of the quantum chip, so that the fidelity corresponding to the initial mapping of the quantum program to be executed is the highest .
  • the building blocks include:
  • an acquisition unit configured to acquire the quantum logic gates in the quantum program to be executed and the qubits operated by the quantum logic gates
  • a construction unit configured to construct a weighted circuit diagram corresponding to the quantum program to be executed based on the quantum logic gate and the qubits operated by the quantum logic gate, wherein the weighted circuit diagram includes: vertices, undirected Edges and edge weights, the vertices are used to represent the qubits operated by the quantum logic gates, the undirected edges are used to represent the quantum logic gates, and the weights of the edges are based on the quantum logic gates that operate the same qubits The number is determined.
  • the determination module includes:
  • a storage unit configured to construct a first associative container for storing undirected edges and edge weight information of the weighted road graph according to the weighted road graph;
  • a traversal unit configured to traverse the first associative container and determine the mapping priority of the quantum program node to be executed, wherein the mapping priority is arranged in descending order according to the weight;
  • a determining unit configured to sequentially determine the mapping relationship of the quantum program nodes to be executed according to the mapping priority of the quantum program nodes to be executed and the fidelity of the quantum chip;
  • An arranging unit configured to arrange the sequentially determined mapping relationships of the quantum program nodes to be executed in order of generation to obtain an initial mapping of the quantum program to be executed.
  • the determining unit includes:
  • the first determination subunit is configured to determine a first node in the quantum program to be executed, wherein the first node has the highest mapping priority in the first associative container;
  • a second determining subunit configured to determine a first mapping relationship of the first node based on the fidelity of the first node and the quantum chip;
  • a first deletion subunit configured to delete the first node in the first associative container to obtain a second associative container
  • a third determining subunit configured to determine whether there is a second node in the current second associative container, wherein the second node has the highest mapping priority in the second associative container;
  • the first judging subunit is configured to obtain the mapping relationship of all nodes determined by the quantum program to be executed if the second node does not exist in the second associative container.
  • the determining unit further includes:
  • the second judging subunit is configured to determine the second node of the second node based on the second node and the current fidelity of the quantum chip if the second node exists in the second associative container. Mapping relations;
  • the second deletion subunit is configured to delete the second node in the second associative container, update the second associative container, return to performing the step of determining whether there is a second node in the current second associative container, until the second node does not exist in the second associative container.
  • this application first obtains the quantum program to be executed and the quantum chip that can be adapted to run, constructs the weighted circuit diagram corresponding to the quantum program to be executed, and determines the weighted circuit diagram according to the fidelity of the quantum chip.
  • the initial mapping of the quantum program to be executed so that the corresponding fidelity of the initial mapping of the quantum program to be executed is the highest, solve the problem of the randomness of the initial mapping relationship of the quantum program to be executed, reduce the number of algorithm execution times, optimize the execution performance, and determine the Execute the optimal initial mapping of the quantum program, so that the fidelity of the initial mapping is high and the resource utilization of the quantum chip is maximized.
  • FIG. 7 is a schematic structural diagram of a device for determining a quantum program mapping relationship provided by an embodiment, corresponding to the process shown in FIG. 6, the device may include:
  • the first acquiring module 501 is configured to acquire the quantum program to be executed and the topology of the quantum chip, the topology is used to represent the physical qubits in the quantum chip and the connection relationship between the physical qubits;
  • a construction module 502 configured to construct a weighted undirected graph corresponding to the quantum program to be executed
  • the first determination module 503 is configured to determine the first parameter of each logical qubit in the quantum program to be executed according to the weighted undirected graph;
  • the second acquiring module 504 is configured to acquire a second parameter of each physical qubit in the quantum chip according to the quantum chip topology
  • the second determination module 505 is configured to determine the mapping relationship of the quantum program to be executed according to the first parameter, the second parameter and the fidelity of the quantum chip, so that the mapping relationship corresponding to the quantum program to be executed is guaranteed The highest degree of authenticity.
  • the building blocks include:
  • an acquisition unit configured to acquire the quantum logic gates in the quantum program to be executed and the logical qubits operated by them;
  • a construction unit configured to construct a weighted undirected graph corresponding to the quantum program to be executed based on the quantum logic gate and the logical qubits operated by it, wherein the weighted undirected graph includes: vertices, undirected edges, and edges
  • the weight of the vertex is used to represent the logical qubit operated by the quantum logic gate
  • the undirected edge is used to represent the quantum logic gate
  • the weight of the edge is determined according to the number of quantum logic gates operating the same qubit .
  • the first determination module is specifically:
  • the first determining unit is configured to determine the first parameter of each logical qubit according to the degree of each vertex in the weighted undirected graph, wherein the degree is based on the undirected edges adjacent to each vertex The sum of the weights is determined.
  • the second acquisition module includes:
  • the second determination unit is configured to determine the number of connection edges of each physical qubit according to the quantum chip topology
  • the third determination unit is configured to determine the second parameter of each physical qubit according to the number of connection edges of each physical qubit.
  • the second determination module includes:
  • a fourth determining unit configured to determine a first logical qubit in the quantum program to be executed according to the first parameter, wherein the first logical qubit has the largest value of the first parameter
  • a fifth determining unit configured to determine the first mapping relationship of the first logical qubit based on the second parameter and the fidelity of the quantum chip
  • the sixth determining unit is configured to delete the first logical qubit, and determine whether there is a second logical qubit in the quantum program to be executed, wherein the first parameter value of the second logical qubit is the largest;
  • the first judging unit is configured to obtain a mapping relationship of all logical qubits determined by the quantum program to be executed if the second logical qubit does not exist in the quantum program to be executed.
  • the second determining module further includes:
  • the second judging unit is configured to determine the second logical qubit of the second logical qubit based on the current second parameter and the fidelity of the quantum chip if the second logical qubit exists in the quantum program to be executed. Two mapping relationship;
  • An update unit configured to delete the second logical qubit, update the logical qubit in the quantum program to be executed, return to the step of determining whether there is a second logical qubit in the quantum program to be executed, until until the second logical qubit does not exist in the quantum program to be executed.
  • this application firstly acquires the quantum program to be executed and the topology structure of the quantum chip, constructs the weighted undirected graph corresponding to the quantum program to be executed, and then determines each quantum program in the quantum program to be executed according to the weighted undirected graph.
  • the first parameter of the logical qubit and then according to the topology of the quantum chip, obtain the second parameter of each physical qubit in the quantum chip, and finally according to the first parameter, the second parameter and the fidelity of the quantum chip, determine the Execute the mapping relationship of the quantum program, so that the corresponding fidelity of the quantum program mapping relationship to be executed is the highest, solve the problem of randomness in constructing the mapping relationship of the quantum program to be executed, reduce the number of algorithm execution times, optimize the execution performance, and determine the quantum program to be executed
  • the optimal initial mapping relationship of the program makes the obtained mapping relationship high in fidelity and maximizes the utilization of quantum chip resources.
  • the embodiment also provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps in any one of the above method embodiments when running.
  • the above-mentioned storage medium may be configured to store a computer program for executing the steps in FIG. 2 or FIG. 6 .
  • the above-mentioned storage medium may include but not limited to: U disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), mobile hard disk Various media that can store computer programs, such as , magnetic disk or optical disk.
  • ROM read-only memory
  • RAM random access memory
  • mobile hard disk Various media that can store computer programs, such as , magnetic disk or optical disk.
  • this application first obtains the quantum program to be executed and the quantum chip that can be adapted to run, constructs the weighted circuit diagram corresponding to the quantum program to be executed, and determines the weighted circuit diagram according to the fidelity of the quantum chip.
  • the initial mapping of the quantum program to be executed so that the corresponding fidelity of the initial mapping of the quantum program to be executed is the highest, solve the problem of the randomness of the initial mapping relationship of the quantum program to be executed, reduce the number of algorithm execution times, optimize the execution performance, and determine the Execute the optimal initial mapping of the quantum program, so that the fidelity of the initial mapping is high and the resource utilization of the quantum chip is maximized.
  • the embodiment also provides an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments .
  • the above-mentioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the above-mentioned processor, and the input-output device is connected to the above-mentioned processor.
  • the above-mentioned processor may be configured to execute the steps in FIG. 2 or FIG. 6 through a computer program.
  • this application first obtains the quantum program to be executed and the quantum chip that can be adapted to run, constructs the weighted circuit diagram corresponding to the quantum program to be executed, and determines the weighted circuit diagram according to the fidelity of the quantum chip.
  • the initial mapping of the quantum program to be executed so that the corresponding fidelity of the initial mapping of the quantum program to be executed is the highest, solve the problem of the randomness of the initial mapping relationship of the quantum program to be executed, reduce the number of algorithm execution times, optimize the execution performance, and determine the Execute the optimal initial mapping of the quantum program, so that the fidelity of the initial mapping is high and the resource utilization of the quantum chip is maximized.
  • the embodiment also provides a quantum computer operating system, the quantum computer operating system realizes the determination of the initial mapping of the quantum program according to any one of the above method embodiments provided in the embodiment.
  • Embodiments of the present application also provide a quantum computer, which includes the quantum computer operating system.
  • this application first obtains the quantum program to be executed and the quantum chip that can be adapted to run, constructs the weighted circuit diagram corresponding to the quantum program to be executed, and determines the weighted circuit diagram according to the fidelity of the quantum chip.
  • the initial mapping of the quantum program to be executed so that the corresponding fidelity of the initial mapping of the quantum program to be executed is the highest, solve the problem of the randomness of the initial mapping relationship of the quantum program to be executed, reduce the number of algorithm execution times, optimize the execution performance, and determine the Execute the optimal initial mapping of the quantum program, so that the fidelity of the initial mapping is high and the resource utilization of the quantum chip is maximized.

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Abstract

公开了一种量子程序初始映射的确定方法、装置及量子计算机。该方法包括：获取待执行量子程序和可适配运行的量子芯片，构建待执行量子程序对应的含权线路图，根据含权线路图和量子芯片的保真度，确定待执行量子程序的初始映射，以使待执行量子程序初始映射对应的保真度最高，解决构造待执行量子程序初始映射关系随机性的问题，减少算法执行次数，优化执行性能，并且可以确定待执行量子程序的最优初始映射，使得初始映射的保真度高、量子芯片资源利用最大化。

Description

量子程序与量子芯片的映射方法和量子操作系统及计算机
相关申请的交叉引用
本专利申请要求于2021年09月28日提交的、发明名称为“一种量子程序初始映射的确定方法、装置及量子计算机”、申请号为CN 202111145141.9的中国专利申请；于2021年10月13日提交的、发明名称为“量子程序映射关系的确定方法、装置、介质及电子装置”、申请号为CN 202111194665.7的中国专利申请的优先权，所述专利申请在此全部引入作为参考。
技术领域
本申请属于量子编译技术领域技术领域，特别是一种量子程序与量子芯片的映射方法、量子程序与量子芯片的映射装置、存储介质、电子装置、量子操作系统及量子计算机。
背景技术
量子计算机是一类遵循量子力学规律进行高速数学和逻辑运算、存储及处理量子信息的物理装置。当某个装置处理和计算的是量子信息，运行的是量子算法时，它就是量子计算机。量子计算机因其具有相对普通计算机更高效的处理数学问题的能力，例如，能将破解RSA密钥的时间从数百年加速到数小时，故成为一种正在研究中的关键技术。
在嘈杂中型量子计算(Noisy Intermediate-Scale Quantum)阶段，对于同一块物理芯片上的多个物理比特，其各个物理比特的状态是不稳定的，例如两比特量子逻辑门噪声参数以及物理比特的退相干时间等因素，均会对物理比特的有效利用造成干扰，从而对整个量子线路的运行结果产生未知影响。例如，由于各个物理比特的退相干时间不同，若是因为某个物理比特退相干时间短而限制了整个量子芯片可运行的量子线路深度，必然导致其他物理比特资源的浪费。
现有技术中，确定待执行量子程序的最优映射线路，通常开始需要随机构造量子程序的初始映射，但是随机构造初始映射关系存在随机性，无法保障算法的实际效果，只能通过多次随机才能使得算法获取更优质的初始映射。
基于此，如何确定随机初始映射，减少算法的执行次数，优化算法的执行性能是一个亟需解决的问题。
发明内容
实施例的一个目的是提供一种量子程序与量子芯片的映射方案，以解决因构造待执行量子程序初始映射关系存在随机性的问题，并且可以确定待执行量子程序的最优初始映射，使得初始映射的保真度高、量子芯片资源利用最大化。
一个实施例提供了一种量子程序与量子芯片的映射方法，所述方法包括：获取待执行量子程序和可适配运行的量子芯片；构建待执行量子程序对应的含权线路图；根据所述含权线路图和所述量子芯片的保真度，确定所述待执行量子程序的初始映射，以使所述待执行量子程序初始映射对应的保真度最高。
本申请的一个实施例提供了一种量子程序映射关系的确定方法，所述方法包括：获取待执行量子程序和量子芯片拓扑结构，所述拓扑结构用于表示所述量子芯片中的物理量子比特以及物理量子比特间的连接关系；构建待执行量子程序对应的带权无向图；根据所述带权无向图，确定所述待执行量子程序中每个逻辑量子比特的第一参数；根据所述量子芯片拓扑结构，获取所述量子芯片中每个物理量子比特的第二参数；根据所述第一参数、第二参数和量子芯片的保真度，确定所述待执行量子程序的映射关系，以使所述待执行量子程序映射关系对应的保真度最高。
本申请的一个实施例提供了一种量子程序与量子芯片的映射装置，所述装置包括：获取模块，用于获取待执行量子程序和可适配运行的量子芯片；构建模块，用于构建待执行量子程序对应的含权线路图；确定模块，用于根据所述含权线路图和所述量子芯片的保真度，确定所述待执行量子程序的初始映射，以使所述待执行量子程序初始映射对应的保真度最高。
本申请的一个实施例提供了一种量子程序映射关系的确定装置，所述装置包括：第一获取模块，用于获取待执行量子程序和量子芯片拓扑结构，所述拓扑结构用于表示所述量子芯片中的物理量子比特以及物理量子比特间的连接关系；构建模块，用于构建待执行量子程序对应的带权无向图；第一确定模块，用于根据所述带权无向图，确定所述待执行量子程序中每个逻辑量子比特的第一参数；第二获取模块，用于根据所述量子芯片拓扑结构，获取所述量子芯片中每个物理量子比特的第二参数；第二确定模块，用于根据所述第一参数、第二参数和量子芯片的保真度，确定所述待执行量子程序的映射关系，以使所述待执行量子程序映射关系对应的保真度最高。
本申请的又一实施例提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述任一项中所述的方法。
本申请的又一实施例提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述任一项中所述的方法。
本申请的又一实施例提供了一种量子计算机操作系统，所述量子计算机操作系统根据上述任一项中所述方法实现量子程序与量子芯片的映射。
本申请的又一实施例提供了一种量子计算机，所述量子计算机包括所述的量子计算机操作系统。
根据一个实施例，可以使得与待执行量子程序初始映射对应的保真度最高，解决构造待执行量子程序初始映射关系随机性的问题，减少算法执行次数，优化执行性能，并且可以确定待执行量子程序的最优初始映射，使得初始映射的保真度高、量子芯片资源利用最大化。
根据一个实施例，可以解决构造待执行量子程序映射关系随机性的问题，减少算法执行次数，优化执行性能，并且可以确定待执行量子程序的最优初始映射关系，使得获取的映射关系保真度高、量子芯片资源利用最大化。
附图说明
图1为实施例提供的一种量子程序初始映射的确定方法的计算机终端的硬件结构框图；
图2为实施例提供的一种量子程序初始映射的确定方法的流程示意图；
图3为实施例提供的一种含权线路图的示意图；
图4为实施例提供的一种量子芯片物理比特的拓扑结构示意图；
图5为实施例提供的一种量子程序初始映射确定装置的结构示意图。
图6为实施例提供的一种量子程序映射关系的确定方法的流程示意图；
图7为实施例提供的一种量子程序映射关系确定装置的结构示意图。
具体实施方式
下面通过参考附图描述的实施例是示例性的，仅用于解释这里的实施例，而不能解释为对实施例的限制。
实施例首先提供了一种量子程序初始映射的确定方法，该方法可以应用于电子设备，如计算机终端，具体如普通电脑、量子计算机等。
下面以运行在计算机终端上为例对其进行详细说明。图1为实施例提供的一种量子程序初始映射的确定方法的计算机终端的硬件结构框图。如图1所示，计算机终端可以包括一个或多个(图1中仅示出一个)处理器102(处理器102可以包括但不限于微处理器MCU或可编程逻辑器件FPGA等的处理装置)和用于存储数据的存储器104，可选地，上述计算机终端还可以包括用于通信功能的传输装置106以及输入输出设备108。本领域普通技术人员可以理解，图1所示的结构仅为示意，其并不对上述计算机终端的结构造成限定。例如，计算机终端还可包括比图1中所示更多或者更少的组件，或者具有与图1所示不同的配置。
存储器104可用于存储应用软件的软件程序以及模块，如本申请实施例中的实现一种 量子程序初始映射的确定方法对应的程序指令/模块，处理器102通过运行存储在存储器104内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述的方法。存储器104可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器104可进一步包括相对于处理器102远程设置的存储器，这些远程存储器可以通过网络连接至计算机终端。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输装置106用于经由一个网络接收或者发送数据。上述的网络具体实例可包括计算机终端的通信供应商提供的无线网络。在一个实例中，传输装置106包括一个网络适配器(Network Interface Controller，NIC)，其可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中，传输装置106可以为射频(Radio Frequency，RF)模块，其用于通过无线方式与互联网进行通讯。
需要说明的是，当量子程序在量子芯片(又叫物理芯片)上运行时，对于同一块物理芯片上的多个物理比特，其各个物理比特的状态是不稳定的，例如两比特量子逻辑门操作噪声、测量噪声以及物理比特的退相干时间等因素，均会对物理比特的有效利用造成干扰，从而对整个量子线路的运行结果产生未知影响。例如，由于各个物理比特的退相干时间不同，若是因为某个物理比特退相干时间短而限制了整个量子芯片可运行的量子线路深度，必然导致其他物理比特资源的浪费。
现有技术中，一般对无法被量子芯片上的两个量子比特适配的两量子比特逻辑门，通过在量子程序中加入SWAP门的方式，将不适配的两量子比特逻辑门转化为该芯片所支持的量子逻辑门。例如，量子程序中包含CNOT(q1，q3)量子逻辑门，量子芯片虽支持CNOT门，但量子芯片中的物理量子比特q1与q3并不直接相连，因此无法被直接执行。故需要对量子程序中的两量子逻辑门进行交换，交换为该芯片可直接执行的量子逻辑门。例如，量子程序包括CNOT(q1，q3)，则现有的交换方法简述为：根据量子芯片上量子比特之间的连接关系，查找CNOT操作的两个量子比特q1、q3之间的连接路径，假设该路径经过的量子比特为q1、q2，则执行CNOT(q1，q3)等价于依次执行：SWAP(q1，q2)、SWAP(q2，q3)、CNOT(q2，q3)、SWAP(q3，q2)、SWAP(q2，q1)。其中，SWAP门表示对量子比特执行交换操作。可见，为了适配量子芯片，对一个两量子比特逻辑门，交换过程就会新增较多数量的量子逻辑门，最终转化后量子程序中的量子逻辑门数量会更为庞大，从而大幅度降低量子程序的计算效率。
基于此，有必要提出一种构建待映射量子程序的最佳方案，用于解决因增加SWAP门对整个量子线路运行的影响，提高整个量子芯片的资源利用率。
图2为实施例提供的一种量子程序与量子芯片的映射方法的流程示意图。
如图2所示，S201：获取待执行量子程序和可适配运行的量子芯片。
例如，如图6所示，S5201：获取待执行量子程序和量子芯片拓扑结构，所述拓扑结构 用于表示所述量子芯片中的物理量子比特以及物理量子比特间的连接关系。
例如，待执行量子程序主要由几十上百个甚至千上万个量子逻辑门组成。量子程序的执行过程，就是对所有的量子逻辑门按照一定时序执行的过程，需要说明的是，时序即单个量子逻辑门被执行的时间顺序。
量子芯片拓扑结构用于表示电子设备中物理量子比特之间的连接关系，且拓扑结构中包含的物理量子比特数目需要大于等于待执行量子程序所需要的量子比特数目，使得量子芯片符合量子程序的执行条件。可适配运行的量子芯片具体指该量子芯片的拓扑结构中包含的物理量子比特数目大于等于待执行量子程序所需要的量子比特数目。需要说明的是，为了便于区分，一般将量子芯片中的量子比特结构称为物理量子比特，量子线路中操作的对象比特称为逻辑量子比特。逻辑量子比特与物理量子比特的映射关系，指逻辑量子比特与物理量子比特之间比特相互“对应”的关系。
示例性的，针对一段待执行量子程序CNOT(q[0]，q[1])＜＜CNOT(q[0]，q[2])＜＜CNOT(q[0]，q[3])＜＜CNOT(q[1]，q[3])＜＜CNOT(q[0]，q[1])＜＜CNOT(q[0]，q[1])＜＜CNOT(q[1]，q[3])，其操作的逻辑比特分别为q[0]、q[1]、q[2]，q[3]，因此可适配该段量子程序执行的量子芯片的物理量子比特数目至少为4个。需要说明的是，受到量子芯片结构或者生产工艺的限制，执行上述量子程序实际所提供的可适配运行的量子芯片的物理量子比特数目可能需要更多。
S202：构建待执行量子程序对应的含权线路图。
线路图的应用十分广泛，可以是有向图也可以是无向图，线路图可被用来表示事件间的驱动依赖关系、任务之间的调度等。
含权线路图可指线路图中顶点间的边含有某一因素或指标相对于某一事物的重要程度，体现某一因素或指标所占的百分比，或是强调某一因素或指标的相对重要程度。
例如，如图6所示，S5202：构建待执行量子程序对应的带权无向图。
无向图的应用十分广泛，可被用来表示事件间的驱动依赖关系、任务之间的调度等。
带权无向图可指无向图中顶点间的边含有某一因素或指标相对于某一事物的重要程度，体现某一因素或指标所占的百分比，或是强调某一因素或指标的相对重要程度。
在一种具体实现中，构建待执行量子程序对应的含权线路图，可以包括如下步骤：
S2021：获取所述待执行量子程序中的量子逻辑门和所述量子逻辑门操作的量子比特。
例如，在图6的步骤S5202中可以包括步骤S52021：获取所述待执行量子程序中的量子逻辑门及其操作的逻辑量子比特。
例如，待执行量子程序可以理解为一个操作序列，其中主要包含量子逻辑门、量子逻辑门操作的量子比特和测量操作(Measure)等。
示例性的，针对一段待执行量子程序CNOT(q[0]，q[1])＜＜CNOT(q[0]，q[2])＜＜CNOT(q[0]，q[3])＜＜CNOT(q[1]，q[3])＜＜CNOT(q[0]，q[1])＜＜CNOT(q[0]，q[1])＜＜CNOT (q[1]，q[3])，其共包含7个量子逻辑门，操作的逻辑量子比特分别为q[0]、q[1]、q[2]、q[3]。
S2022：基于所述量子逻辑门和所述量子逻辑门操作的量子比特，构建所述待执行量子程序对应的含权线路图，其中，所述含权线路图包括：顶点、无向边和边的权重，所述顶点用于表示所述量子逻辑门操作的量子比特，所述无向边用于表示所述量子逻辑门，所述边的权重根据操作相同量子比特的量子逻辑门数目确定。
例如，在图6的步骤S5202中可以包括步骤S2022：基于所述量子逻辑门及其操作的逻辑量子比特，构建待执行量子程序对应的带权无向图，其中，所述带权无向图包括：顶点、无向边和边的权重，所述顶点用于表示所述量子逻辑门操作的逻辑量子比特，所述无向边用于表示所述量子逻辑门，所述边的权重根据操作相同量子比特的量子逻辑门数目确定。
示例性的，基于上述待执行量子程序，其操作的逻辑比特分别为q[0]、q[1]、q[2]，q[3]，因此待执行量子程序对应的含权线路图共有4个顶点；待执行量子程序共有CNOT(q[0]，q[1])、CNOT(q[0]，q[2])、CNOT(q[0]，q[3])、CNOT(q[1]，q[3])、CNOT(q[0]，q[1])、CNOT(q[0]，q[1])、CNOT(q[1]，q[3])7个量子逻辑门，其中，操作相同量子比特的量子逻辑门，分别是3个CNOT(q[0]，q[1])，2个CNOT(q[1]，q[3])，CNOT(q[0]，q[2])和CNOT(q[0]，q[3])各1个。因此，可得到4条无向边及其对应的权重，分别为：q[0]与q[1]之间的无向边，边的权重为3；q[0]与q[2]之间的无向边，边的权重为1；q[0]与q[3]之间的无向边，边的权重为1；q[1]与q[3]之间的无向边，边的权重为2。从而，得到如图3所示的一种诸如带权无向图的含权线路图的示意图。
S203：根据所述含权线路图和所述量子芯片的保真度，确定所述待执行量子程序的初始映射，以使所述待执行量子程序初始映射对应的保真度最高。
例如，所述量子芯片的保真度包括所述量子芯片拓扑结构中每两个物理比特间的双量子逻辑门保真度和每个物理比特对应的测量保真度。
保真度是表征电子设备输出再现输入信号的相似程度，保真度越高，电子设备输出的声音或输出的影像越逼真。在量子芯片中，保真度越高，噪声越小，运行一段量子程序后获得的测量结果误差越小，则更接近期望的执行结果。
例如，如图6所示，S5203：根据所述带权无向图，确定所述待执行量子程序中每个逻辑量子比特的第一参数。
例如，根据带权无向图中每个顶点的度数，确定每个逻辑量子比特的第一参数，其中，所述度数根据所述每个顶点相邻的无向边权重之和确定。
示例性的，如图3所示，带权无向图中共有4个顶点，分别为顶点q[0]、q[1]、q[2]和q[3]。顶点q[0]相邻的无向边共有三条，分别为：q[0]与q[1]间的无向边，其权重为3；q[0]与q[2]间的无向边，其权重为1；q[0]与q[3]间的无向边，其权重为1。因此，顶点q[0]的 第一参数值是其三条相邻无向边的权重之和为5，同理，分别获得顶点q[1]的第一参数值5、顶点q[2]的第一参数值1和顶点q[3]的第一参数值3。
在图6中，S5204：根据所述量子芯片拓扑结构，获取所述量子芯片中每个物理量子比特的第二参数。
例如，现有技术中量子芯片拓扑结构可能呈一维链结构，即所有的物理量子比特均在一条线上；也有可能呈现二维链结构，例如，如图3所示的量子芯片拓扑结构，即为一种二维链结构。
获取所述量子芯片中每个物理量子比特的第二参数，可包括如下步骤：
根据所述量子芯片拓扑结构，确定所述每个物理量子比特连接边的数量；
根据所述每个物理量子比特连接边的数量，确定每个物理量子比特的第二参数。
示例性的，根据图4所示的量子芯片拓扑结构，其量子芯片中每个物理量子比特连接边的关系为：Q[0]与Q[1]及Q[3]连接，Q[4]与Q[1]、Q[3]及Q[5]连接，Q[2]与Q[1]、Q[5]连接，Q[5]与Q[2]及Q[4]连接，因此物理量子比特Q[0]的第二参数值为2，Q[1]的第二参数值为3，Q[2]的第二参数值为2，Q[3]的第二参数值为2，Q[4]的第二参数值为3，Q[5]的第二参数值为2。
在图6中，S5205：根据所述第一参数、第二参数和量子芯片的保真度，确定所述待执行量子程序的映射关系，以使所述待执行量子程序映射关系对应的保真度最高。
例如，所述量子芯片的保真度包括所述量子芯片拓扑结构中每两个物理量子比特间的双量子逻辑门保真度和每个物理量子比特对应的测量保真度。
保真度是表征电子设备输出再现输入信号的相似程度，保真度越高，电子设备输出的声音或输出的影像越逼真。在量子芯片中，保真度越高，噪声越小，运行一段量子程序后获得的测量结果误差越小，则更接近期望的执行结果。
示例性的，参见图4，图4为实施例提供的一种量子芯片物理比特的拓扑结构示意图，该量子芯片中包括6个物理比特，分别为Q[0]、Q[1]、Q[2]、Q[3]、Q[4]、Q[5]，这6个物理比特可通过电容耦合，且只有相邻的物理比特之间才具有耦合关系。其中，Q[0]与Q[1]及Q[3]连接，Q[4]与Q[1]、Q[3]及Q[5]连接，Q[2]与Q[1]、Q[5]连接，Q[5]与Q[2]及Q[4]连接。其中，Q[0]、Q[1]、Q[2]、Q[3]、Q[4]、Q[5]对应的测量保真度分别为0.95、0.94、0.93、0.92、0.91、0.90。
量子芯片拓扑结构中每两个物理比特间的双量子逻辑门保真度，具体获取方法为：对于能直接映射双量子逻辑门的物理比特，其保真度为对应的双量子逻辑门保真度，例如，可直接测量Q[0]与Q[1]间的双量子逻辑门保真度为0.9，Q[0]与Q[3]间的双量子逻辑门保真度为0.9，Q[3]与Q[4]间的双量子逻辑门保真度为0.95，Q[4]与Q[1]间的双量子逻辑门保真度为0.85，Q[1]与Q[2]间的双量子逻辑门保真度为0.8，Q[2]与Q[5]间的双量子逻辑门保真度为0.75，Q[4]与Q[5]间的双量子逻辑门保真度为0.7；对于无法直接映射双量子逻辑门的物 理比特，则需要借助SWAP量子逻辑门，将无法直接映射的物理比特移至相邻位置，再计算对应的双量子逻辑门保真度。
示例性的，对于量子芯片拓扑结构中物理比特Q[0]、Q[1]，可直接映射CNOT双量子逻辑门，即Q[0]与Q[1]间的双量子逻辑门保真度为0.9；而若要在物理比特Q[0]、Q[2]上映射CNOT双量子逻辑门，可选的，获取物理比特Q[0]、Q[2]保真度的路径可以为插入SWAP(q[0]，q[1])和CNOT(q[1]，q[2])，SWAP(q[0]，q[1])双量子逻辑门保真度为对应CNOT(q[0]，q[1])双量子逻辑门保真度的三次方，因此SWAP(q[0]，q[1])和CNOT(q[1]，q[2])对应的双量子逻辑门保真度为0.5832(0.9*0.9*0.9*0.8)。同样的，若要在物理比特Q[0]、Q[4]上映射CNOT双量子逻辑门，获取物理比特Q[0]、Q[4]保真度的路径可以为插入SWAP(q[0]，q[3])和CNOT(q[3]，q[4])，因此CNOT(q[0]，q[4])对应的双量子逻辑门保真度为0.69255(0.9*0.9*0.9*0.95)。
按照上述方法，以CNOT双量子逻辑门为例，下表1为各量子比特间应用CNOT双量子逻辑门保真度统计表。
表1：量子比特间应用CNOT双量子逻辑门保真度统计表
Figure PCTCN2022122010-appb-000001
根据所述含权线路图和所述量子芯片的保真度，确定所述待执行量子程序的初始映射，可以包括：
步骤1：根据所述含权线路图，构建存储所述含权线路图无向边及边的权重信息的第一关联容器。
例如，根据图3所示，构建存储该含权线路图无向边及边的权重信息的第一关联容器。可选的，第一关联容器可以为标准模板库(Standard Template Library，STL)的一个存储容器，它能够提供一对一的数据处理能力。
将含权线路图无向边及边的权重信息存储到第一关联容器中，此时第一关联容器中的存储信息为：(q[0]，q[1])：3，(q[1]，q[3])：2，(q[0]，q[2])：1，(q[0]，q[3])：1。
步骤2：遍历所述第一关联容器，确定所述待执行量子程序节点的映射优先级，其中，所述映射优先级根据所述权重从大到小依次排列。
接上述示例，遍历第一关联容器中的存储信息，确定待执行量子程序节点的映射优先级，其中，节点CNOT(q[0]，q[1])的权重为3，节点CNOT(q[1]，q[3])的权重为2，节点CNOT(q[0]，q[2])的权重为1，节点CNOT(q[0]，q[3])的权重为1，按照权重大 小依次确定待执行量子程序节点的映射顺序。
步骤3：根据所述待执行量子程序节点的映射优先级和所述量子芯片的保真度，依次确定所述待执行量子程序节点的映射关系。
例如，确定所述待执行量子程序中的第一节点，其中，所述第一节点在所述第一关联容器中映射优先级最高。
接上述示例，优先处理待执行量子程序中映射优先级最高的第一节点CNOT(q[0]，q[1])，即先将CNOT(q[0]，q[1])映射到量子芯片中保真度最高的位置。
例如，计算量子芯片的保真度，可以通过如下公式进行：
Figure PCTCN2022122010-appb-000002
且i，j∈{Q 0，Q 1，Q 2，Q 3，Q 4，Q 5}∧i≠j
其中，
Figure PCTCN2022122010-appb-000003
为双量子逻辑门保真度，
Figure PCTCN2022122010-appb-000004
和
Figure PCTCN2022122010-appb-000005
分别为第i个、第j个物理比特对应的测量保真度。
需要说明的是，若要将待执行量子程序中的优先级高的节点，首先映射到量子芯片中两个不相邻位置，需要插入额外的SWAP量子逻辑门，其保真度远低于映射到量子芯片中两个相邻位置，所以只需要获取i，j相邻时的保真度，计算结果如下表2所示。
表2：相邻量子比特间保真度统计表
i j R i，j
Q 0 Q 1 0.8037
Q 0 Q 3 0.7866
Q 1 Q 2 0.69936
Q 1 Q 4 0.72709
Q 2 Q 5 0.62775
Q 3 Q 4 0.79534
Q 4 Q 5 0.5733
基于所述第一节点和所述量子芯片的保真度，确定所述第一节点的第一映射关系。
根据上述表2，可知R i，j最高的为
Figure PCTCN2022122010-appb-000006
Figure PCTCN2022122010-appb-000007
则可确定第一节点CNOT(q[0]，q[1])的第一映射关系q[0]--Q[0]和q[1]--Q[1]。
删除所述第一关联容器中的所述第一节点，得到第二关联容器。
示例性的，删除第一关联容器中第一节点CNOT(q[0]，q[1])，得到第二关联容器，此时第二关联容器中的存储信息为：(q[1]，q[3])：2，(q[0]，q[2])：1，(q[0]，q[3])：1。
确定当前第二关联容器中是否存在第二节点，其中，所述第二节点在所述第二关联容器中映射优先级最高。
若所述第二关联容器中存在所述第二节点，则基于所述第二节点和当前所述量子芯片的保真度，确定所述第二节点的第二映射关系。
示例性的，在第二关联容器中，存在所述第二节点，即首先处理待执行量子程序中映射优先级最高的第二节点CNOT(q[1]，q[3])，即将CNOT(q[1]，q[3])映射到当前量子芯片中保真度最高的位置。
例如，由于q[1]已经被映射，只需要为q[3]找到当前保真度最高的比特位置进行映射，此时由于量子芯片拓扑结构中Q[0]、Q[1]已经被映射，所以需要在Q[2]、Q[3]、Q[4]、Q[5]中找到保真度最高的物理比特，同时考虑线路整体保真度，即在含权线路图中找到与q[3]相邻的且已被映射的顶点参与计算，由于q[0]、q[1]与q[3]相邻且已经被映射，所以当前量子芯片保真度计算，根据保真度计算公式，得：
Figure PCTCN2022122010-appb-000008
计算结果如下表3所示。
表3：当前量子芯片保真度统计表
j R j
Q 2 0.433901
Q 3 0.543251
Q 4 0.535687
Q 5 0.169275
根据上表可知，R j最高的为
Figure PCTCN2022122010-appb-000009
Figure PCTCN2022122010-appb-000010
因此第二节点的第二映射关系为q[1]--Q[1]和q[3]--Q[3]。
删除所述第二关联容器中的所述第二节点，更新第二关联容器，返回执行所述确定所述当前第二关联容器中是否存在第二节点的步骤，直至所述第二关联容器中不存在所述第二节点为止。
接上述示例，删除第二关联容器中第二节点CNOT(q[1]，q[3])，更新第二关联容器，由于q[0]、q[3]已经被映射，即可删除第二关联容器中存储的(0：3)：1信息，此时第二关联容器中的存储信息更新为：(q[0]，q[2])：1。
此时，由于在含权线路图中q[0]、q[2]边权重最高，即处理待执行量子程序中的节点CNOT(q[0]，q[2])，由于q[0]已经被映射，因此只需要在量子芯片拓扑结构中为q[2]找到当前保真度最高的物理量子比特位置进行映射，此时由于Q[0]、Q[1]、Q[3]已经被映射，所以需要在Q[2]、Q[4]、Q[5]找到保真度最高的物理比特，同时考虑线路整体保真度，即在含权线路图中找到与q[2]相邻的且已被映射的顶点参与计算，由于q[0]、q[2]相邻且已经被映射，所以当前量子芯片保真度计算，根据保真度计算公式，得：
Figure PCTCN2022122010-appb-000011
计算结果如下表4所示。
表4：当前量子芯片保真度统计表
j R j
Q 2 0.542376
Q 4 0.630221
Q 5 0.393767
根据上表可知，R j最高的为
Figure PCTCN2022122010-appb-000012
因此当前第二节点的当前第二映射关系为q[0]--Q[0]和q[2]--Q[4]。
删除第二关联容器中当前第二节点CNOT(q[0]，q[2])，更新第二关联容器，即删除存储信息(q[0]，q[2])：1，此时，第二关联容器中不存在第二节点。
若所述第二关联容器中不存在所述第二节点，则获得所述待执行量子程序所确定的所有节点的映射关系。
当第二关联容器中不存在所述第二节点，即第二关联容器中存储的信息为空时，获得待执行量子程序所确定的所有节点的映射关系，分别为q[0]--Q[0]和q[1]--Q[1]、q[1]--Q[1]和q[3]--Q[3]、q[0]--Q[0]和q[2]--Q[4]。
步骤4：将所述依次确定的待执行量子程序节点的映射关系按照生成顺序排列，得到所述待执行量子程序的初始映射。
例如，将获得的待执行量子程序所确定的所有节点的映射关系q[0]--Q[0]和q[1]--Q[1]、q[1]--Q[1]和q[3]--Q[3]、q[0]--Q[0]和q[2]--Q[4]，按照生成顺序排列，即得到待执行量子程序的初始映射关系：q[0]--Q[0]、q[1]--Q[1]、q[3]--Q[3]和q[2]--Q[4]。
需要说明的是，待执行量子程序可包括单比特量子逻辑门、两比特量子逻辑门和多比特量子逻辑门，但在确定待执行量子程序的对应的含权线路图之前，首先需要将多比特量子逻辑门转化成单比特量子逻辑门和两比特量子逻辑门的组合。由于单比特量子逻辑门可直接将逻辑比特映射到物理比特，因此可将转化后得到的单比特量子逻辑门和转化前待执行量子程序中本身存在的单量子逻辑门删除(不影响映射关系)，再基于转化后得到的两比特量子逻辑门和转化前待执行量子程序中本身存在的两比特量子逻辑门构建待执行量子程序对应的含权线路图。在这里为了方便说明，仅以包含两比特量子逻辑门的一段待执行量子程序举例。
可见，通过获取待执行量子程序和可适配运行的量子芯片，构建待执行量子程序对应的含权线路图，根据含权线路图和量子芯片的保真度，确定待执行量子程序的初始映射，以使待执行量子程序初始映射对应的保真度最高，解决构造待执行量子程序初始映射关系随机性的问题，减少算法执行次数，优化执行性能，并且可以确定待执行量子程序的最优初始映射，使得初始映射的保真度高、量子芯片资源利用最大化。
在图6的步骤S5205中，根据所述第一参数、第二参数和量子芯片的保真度，确定所述待执行量子程序的映射关系，可以包括：
步骤1：根据所述第一参数，确定所述待执行量子程序中的第一逻辑量子比特，其中，所述第一逻辑量子比特的第一参数数值最大。
例如，根据图3所示，构建存储该带权无向图顶点和第一参数的第一关联容器。可选 的，第一关联容器可以为标准模板库(Standard Template Library，STL)的一个存储容器，它能够提供一对一的数据处理能力。
将带权无向图顶点(逻辑量子比特)和第一参数存储到第一关联容器中，此时第一关联容器中的存储信息为：q[0]：5，q[1]：5，q[2]：1，q[3]：3。
遍历第一关联容器中的存储信息，确定待执行量子程序中的第一逻辑量子比特，其中，第一逻辑量子比特的第一参数数值最大。
例如，逻辑量子比特q[0]的第一参数值为5，逻辑量子比特q[1]的第一参数值为5，逻辑量子比特q[2]的第一参数值为1，逻辑量子比特q[3]的第一参数值为3，按照第一参数值依次确定待执行量子程序中的逻辑量子比特的映射顺序。
由于此时逻辑量子比特q[0]和逻辑量子比特q[1]的第一参数数值相同，因此优先映射逻辑量子比特q[0]或逻辑量子比特q[1]均可，对最终获得的映射关系结果影响不大。
步骤2：基于所述第二参数和量子芯片的保真度，确定所述第一逻辑量子比特的第一映射关系。
可选的，当优先处理第一逻辑量子比特q[0]时，获取第二参数最高的物理量子比特，即物理量子比特Q[1]与Q[4]，二者的第二参数数值均为3，同时，由于Q[1]的测量保真度大于Q[4]的测量保真度，因此将第一逻辑量子比特q[0]映射到物理量子比特Q[1]，则可确定第一逻辑量子比特q[0]的第一映射关系q[0]--Q[1]。
步骤3：删除所述第一逻辑量子比特，确定所述待执行量子程序中是否存在第二逻辑量子比特，其中，所述第二逻辑量子比特的第一参数数值最大。
示例性的，删除第一关联容器中的第一逻辑量子比特q[0]，得到第二关联容器，此时第二关联容器中的存储信息为：q[1]：5，q[2]：1，q[3]：3。
确定当前第二关联容器中是否存在第二逻辑量子比特，其中，第二逻辑量子比特在第二关联容器中第一参数数值最大。
若所述待执行量子程序中存在所述第二逻辑量子比特，则基于当前所述第二参数和量子芯片的保真度，确定所述第二逻辑量子比特的第二映射关系。
例如，此时，第二逻辑量子比特q[1]的第一参数数值最大，选择当前量子芯片中保真度最高的物理量子比特进行映射，由于q[0]被映射，且由于量子芯片拓扑结构中Q[1]已经被映射，所以需要在Q[0]、Q[2]、Q[3]、Q[4]、Q[5]中找到保真度最高的物理量子比特，同时考虑线路整体保真度，根据保真度计算方法，得：
Figure PCTCN2022122010-appb-000013
计算结果如下表5所示。
表5：当前量子芯片保真度统计表
Figure PCTCN2022122010-appb-000014
Figure PCTCN2022122010-appb-000015
根据上表可知，
Figure PCTCN2022122010-appb-000016
最高的为
Figure PCTCN2022122010-appb-000017
因此第二逻辑量子比特q[1]的第二映射关系为q[1]--Q[0]。
删除所述第二逻辑量子比特，更新所述待执行量子程序中的逻辑量子比特，返回执行所述确定所述待执行量子程序中是否存在第二逻辑量子比特的步骤，直至所述待执行量子程序中不存在所述第二逻辑量子比特为止。
接上述示例，删除第二逻辑量子比特q[1]，更新待执行量子程序中的逻辑量子比特，此时第二关联容器中的存储信息更新为：q[2]：1，q[3]：3。
此时，待执行量子程序中存在第二逻辑量子比特q[3]，基于第二逻辑量子比特q[3]、当前第二参数和量子芯片的保真度，确定当前第二逻辑量子比特的第二映射关系。
例如，此时，第二逻辑量子比特q[3]的第一参数数值最大，选择当前量子芯片中保真度最高的物理量子比特进行映射，由于q[0]、q[1]被映射，且由于量子芯片拓扑结构中Q[0]、Q[1]已经被映射，所以需要在Q[2]、Q[3]、Q[4]、Q[5]中找到保真度最高的物理量子比特，同时考虑线路整体保真度，根据保真度计算方法，得：
Figure PCTCN2022122010-appb-000018
计算结果如下表6所示。
表6：当前量子芯片保真度统计表
Figure PCTCN2022122010-appb-000019
根据上表可知，
Figure PCTCN2022122010-appb-000020
最高的为
Figure PCTCN2022122010-appb-000021
因此此时第二逻辑量子比特q[3]的第二映射关系为q[3]--Q[4]。
按照上述方法，继续删除当前第二逻辑量子比特q[3]，更新待执行量子程序中的逻辑量子比特，返回执行所述确定所述待执行量子程序中是否存在第二逻辑量子比特的步骤。
接上述示例，删除当前第二逻辑量子比特q[3]，更新待执行量子程序中的逻辑量子比特，此时第二关联容器中的存储信息更新为：q[2]：1。
此时，待执行量子程序中存在第二逻辑量子比特q[2]，基于第二逻辑量子比特q[2]、当前第二参数和量子芯片的保真度，确定当前第二逻辑量子比特的第二映射关系。
例如，此时，第二逻辑量子比特q[2]的第一参数数值最大，选择当前量子芯片中保真度最高的物理量子比特进行映射，由于q[0]、q[1]、q[3]被映射，且由于量子芯片拓扑结构中Q[0]、Q[1]、Q[4]已经被映射，所以需要在Q[2]、Q[3]、Q[5]中找到保真度最高的物理量子比特，同时考虑线路整体保真度，根据保真度计算方法，得：
Figure PCTCN2022122010-appb-000022
计算 结果如下表7所示。
表7：当前量子芯片保真度统计表
Figure PCTCN2022122010-appb-000023
根据上表可知，
Figure PCTCN2022122010-appb-000024
最高的为
Figure PCTCN2022122010-appb-000025
因此此时第二逻辑量子比特q[2]的第二映射关系为q[2]--Q[2]。
步骤4：若所述待执行量子程序中不存在所述第二逻辑量子比特，则获得所述待执行量子程序所确定的所有逻辑量子比特的映射关系。
当待执行量子程序中不存在第二逻辑量子比特，即当前第二关联容器中存储的信息为空时，获得所述待执行量子程序所确定的所有逻辑量子比特的映射关系，并将所述依次确定的待执行量子程序所确定的映射关系按照生成顺序排列，得到所述待执行量子程序的初始映射关系：q[0]--Q[1]、q[1]--Q[0]、q[3]--Q[4]和q[2]--Q[2]。
需要说明的是，待执行量子程序可包括单比特量子逻辑门、两比特量子逻辑门和多比特量子逻辑门，但在确定待执行量子程序的对应的带权无向图之前，首先需要将多比特量子逻辑门转化成单比特量子逻辑门和两比特量子逻辑门的组合。由于单比特量子逻辑门可直接将逻辑量子比特映射到物理量子比特，因此可将转化后得到的单比特量子逻辑门和转化前待执行量子程序中本身存在的单量子逻辑门删除(不影响映射关系)，再基于转化后得到的两比特量子逻辑门和转化前待执行量子程序中本身存在的两比特量子逻辑门构建待执行量子程序对应的带权无向图。在这里为了方便说明，仅以包含两比特量子逻辑门的一段待执行量子程序举例。
可见，与现有技术相比，本申请首先获取待执行量子程序和量子芯片拓扑结构，构建待执行量子程序对应的带权无向图，其次根据带权无向图，确定待执行量子程序中每个逻辑量子比特的第一参数，再根据量子芯片拓扑结构，获取量子芯片中每个物理量子比特的第二参数，最后根据所述第一参数、第二参数和量子芯片的保真度，确定待执行量子程序的映射关系，以使待执行量子程序映射关系对应的保真度最高，解决构造待执行量子程序映射关系随机性的问题，减少算法执行次数，优化执行性能，并且可以确定待执行量子程序的最优初始映射关系，使得获取的映射关系保真度高、量子芯片资源利用最大化。
参见图5，图5为实施例提供的一种量子程序初始映射确定装置的结构示意图，与图2所示的流程相对应，该装置可以包括：
获取模块501，用于获取待执行量子程序和可适配运行的量子芯片；
构建模块502，用于构建待执行量子程序对应的含权线路图；
确定模块503，用于根据所述含权线路图和所述量子芯片的保真度，确定所述待执行量 子程序的初始映射，以使所述待执行量子程序初始映射对应的保真度最高。
例如，所述构建模块，包括：
获取单元，用于获取所述待执行量子程序中的量子逻辑门和所述量子逻辑门操作的量子比特；
构建单元，用于基于所述量子逻辑门和所述量子逻辑门操作的量子比特，构建所述待执行量子程序对应的含权线路图，其中，所述含权线路图包括：顶点、无向边和边的权重，所述顶点用于表示所述量子逻辑门操作的量子比特，所述无向边用于表示所述量子逻辑门，所述边的权重根据操作相同量子比特的量子逻辑门数目确定。
例如，所述确定模块，包括：
存储单元，用于根据所述含权线路图，构建存储所述含权线路图无向边及边的权重信息的第一关联容器；
遍历单元，用于遍历所述第一关联容器，确定所述待执行量子程序节点的映射优先级，其中，所述映射优先级根据所述权重从大到小依次排列；
确定单元，用于根据所述待执行量子程序节点的映射优先级和所述量子芯片的保真度，依次确定所述待执行量子程序节点的映射关系；
排列单元，用于将所述依次确定的待执行量子程序节点的映射关系按照生成顺序排列，得到所述待执行量子程序的初始映射。
例如，所述确定单元，包括：
第一确定子单元，用于确定所述待执行量子程序中的第一节点，其中，所述第一节点在所述第一关联容器中映射优先级最高；
第二确定子单元，用于基于所述第一节点和所述量子芯片的保真度，确定所述第一节点的第一映射关系；
第一删除子单元，用于删除所述第一关联容器中的所述第一节点，得到第二关联容器；
第三确定子单元，用于确定当前第二关联容器中是否存在第二节点，其中，所述第二节点在所述第二关联容器中映射优先级最高；
第一判断子单元，用于若所述第二关联容器中不存在所述第二节点，则获得所述待执行量子程序所确定的所有节点的映射关系。
例如，所述确定单元，还包括：
第二判断子单元，用于若所述第二关联容器中存在所述第二节点，则基于所述第二节点和当前所述量子芯片的保真度，确定所述第二节点的第二映射关系；
第二删除子单元，用于删除所述第二关联容器中的所述第二节点，更新第二关联容器，返回执行所述确定所述当前第二关联容器中是否存在第二节点的步骤，直至所述第二关联容器中不存在所述第二节点为止。
与现有技术相比，本申请首先获取待执行量子程序和可适配运行的量子芯片，构建待 执行量子程序对应的含权线路图，根据含权线路图和量子芯片的保真度，确定待执行量子程序的初始映射，以使待执行量子程序初始映射对应的保真度最高，解决构造待执行量子程序初始映射关系随机性的问题，减少算法执行次数，优化执行性能，并且可以确定待执行量子程序的最优初始映射，使得初始映射的保真度高、量子芯片资源利用最大化。
参见图7，图7为实施例提供的一种量子程序映射关系确定装置的结构示意图，与图6所示的流程相对应，该装置可以包括：
第一获取模块501，用于获取待执行量子程序和量子芯片拓扑结构，所述拓扑结构用于表示所述量子芯片中的物理量子比特以及物理量子比特间的连接关系；
构建模块502，用于构建待执行量子程序对应的带权无向图；
第一确定模块503，用于根据所述带权无向图，确定所述待执行量子程序中每个逻辑量子比特的第一参数；
第二获取模块504，用于根据所述量子芯片拓扑结构，获取所述量子芯片中每个物理量子比特的第二参数；
第二确定模块505，用于根据所述第一参数、第二参数和量子芯片的保真度，确定所述待执行量子程序的映射关系，以使所述待执行量子程序映射关系对应的保真度最高。
例如，所述构建模块，包括：
获取单元，用于获取所述待执行量子程序中的量子逻辑门及其操作的逻辑量子比特；
构建单元，用于基于所述量子逻辑门及其操作的逻辑量子比特，构建待执行量子程序对应的带权无向图，其中，所述带权无向图包括：顶点、无向边和边的权重，所述顶点用于表示所述量子逻辑门操作的逻辑量子比特，所述无向边用于表示所述量子逻辑门，所述边的权重根据操作相同量子比特的量子逻辑门数目确定。
例如，所述第一确定模块，具体为：
第一确定单元，用于根据所述带权无向图中每个顶点的度数，确定每个逻辑量子比特的第一参数，其中，所述度数根据所述每个顶点相邻的无向边权重之和确定。
例如，所述第二获取模块，包括：
第二确定单元，用于根据所述量子芯片拓扑结构，确定所述每个物理量子比特连接边的数量；
第三确定单元，用于根据所述每个物理量子比特连接边的数量，确定每个物理量子比特的第二参数。
例如，所述第二确定模块，包括：
第四确定单元，用于根据所述第一参数，确定所述待执行量子程序中的第一逻辑量子比特，其中，所述第一逻辑量子比特的第一参数数值最大；
第五确定单元，用于基于所述第二参数和量子芯片的保真度，确定所述第一逻辑量子比特的第一映射关系；
第六确定单元，用于删除所述第一逻辑量子比特，确定所述待执行量子程序中是否存在第二逻辑量子比特，其中，所述第二逻辑量子比特的第一参数数值最大；
第一判断单元，用于若所述待执行量子程序中不存在所述第二逻辑量子比特，则获得所述待执行量子程序所确定的所有逻辑量子比特的映射关系。
例如，所述第二确定模块，还包括：
第二判断单元，用于若所述待执行量子程序中存在所述第二逻辑量子比特，则基于当前所述第二参数和量子芯片的保真度，确定所述第二逻辑量子比特的第二映射关系；
更新单元，用于删除所述第二逻辑量子比特，更新所述待执行量子程序中的逻辑量子比特，返回执行所述确定所述待执行量子程序中是否存在第二逻辑量子比特的步骤，直至所述待执行量子程序中不存在所述第二逻辑量子比特为止。
与现有技术相比，本申请首先获取待执行量子程序和量子芯片拓扑结构，构建待执行量子程序对应的带权无向图，其次根据带权无向图，确定待执行量子程序中每个逻辑量子比特的第一参数，再根据量子芯片拓扑结构，获取量子芯片中每个物理量子比特的第二参数，最后根据所述第一参数、第二参数和量子芯片的保真度，确定待执行量子程序的映射关系，以使待执行量子程序映射关系对应的保真度最高，解决构造待执行量子程序映射关系随机性的问题，减少算法执行次数，优化执行性能，并且可以确定待执行量子程序的最优初始映射关系，使得获取的映射关系保真度高、量子芯片资源利用最大化。
实施例还提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述任一项中方法实施例中的步骤。
例如，在本实施例中，上述存储介质可以被设置为存储用于执行图2或图6中的步骤的计算机程序。
例如，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(Read-Only Memory，简称为ROM)、随机存取存储器(Random Access Memory，简称为RAM)、移动硬盘、磁碟或者光盘等各种可以存储计算机程序的介质。
与现有技术相比，本申请首先获取待执行量子程序和可适配运行的量子芯片，构建待执行量子程序对应的含权线路图，根据含权线路图和量子芯片的保真度，确定待执行量子程序的初始映射，以使待执行量子程序初始映射对应的保真度最高，解决构造待执行量子程序初始映射关系随机性的问题，减少算法执行次数，优化执行性能，并且可以确定待执行量子程序的最优初始映射，使得初始映射的保真度高、量子芯片资源利用最大化。
实施例还提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述任一项中方法实施例中的步骤。
例如，上述电子装置还可以包括传输设备以及输入输出设备，其中，该传输设备和上述处理器连接，该输入输出设备和上述处理器连接。
例如，在本实施例中，上述处理器可以被设置为通过计算机程序执行图2或图6中的 步骤。
与现有技术相比，本申请首先获取待执行量子程序和可适配运行的量子芯片，构建待执行量子程序对应的含权线路图，根据含权线路图和量子芯片的保真度，确定待执行量子程序的初始映射，以使待执行量子程序初始映射对应的保真度最高，解决构造待执行量子程序初始映射关系随机性的问题，减少算法执行次数，优化执行性能，并且可以确定待执行量子程序的最优初始映射，使得初始映射的保真度高、量子芯片资源利用最大化。
实施例还提供了一种量子计算机操作系统，所述量子计算机操作系统根据实施例中提供的上述任一方法实施例实现量子程序初始映射的确定。
本申请的实施例还提供了一种量子计算机，所述量子计算机包括所述的量子计算机操作系统。
与现有技术相比，本申请首先获取待执行量子程序和可适配运行的量子芯片，构建待执行量子程序对应的含权线路图，根据含权线路图和量子芯片的保真度，确定待执行量子程序的初始映射，以使待执行量子程序初始映射对应的保真度最高，解决构造待执行量子程序初始映射关系随机性的问题，减少算法执行次数，优化执行性能，并且可以确定待执行量子程序的最优初始映射，使得初始映射的保真度高、量子芯片资源利用最大化。
以上依据图式所示的实施例详细说明了实施例中的构造、特征及作用效果，以上所述仅为各个实施例中的较佳实施例，但各个实施例不以图面所示限定实施范围，凡是依照各个实施例的构想所作的改变，或修改为等同变化的等效实施例，仍未超出说明书与图示所涵盖的精神时，均应在各个实施例的保护范围内。

Claims (16)

  1. 一种量子程序与量子芯片的映射方法，其特征在于，所述方法包括：
    获取待执行量子程序和可适配运行的量子芯片；
    构建待执行量子程序对应的含权线路图；
    根据所述含权线路图和所述量子芯片的保真度，确定所述待执行量子程序的初始映射，以使所述待执行量子程序初始映射对应的保真度最高。
  2. 根据权利要求1所述的方法，其特征在于，获取待执行量子程序和可适配运行的量子芯片包括：
    获取待执行量子程序和量子芯片拓扑结构，所述拓扑结构用于表示所述量子芯片中的物理量子比特以及物理量子比特间的连接关系，
    其中，含权线路图是带权无向图，
    其中，确定所述待执行量子程序的初始映射包括：
    根据所述带权无向图，确定所述待执行量子程序中每个逻辑量子比特的第一参数；
    根据所述量子芯片拓扑结构，获取所述量子芯片中每个物理量子比特的第二参数；
    根据所述第一参数、第二参数和量子芯片的保真度，确定所述待执行量子程序的映射关系，以使所述待执行量子程序映射关系对应的保真度最高。
  3. 根据权利要求1或2所述的方法，其特征在于，所述量子芯片的保真度包括所述量子芯片拓扑结构中每两个物理比特间的双量子逻辑门保真度和每个物理比特对应的测量保真度。
  4. 根据权利要求3所述的方法，其特征在于，所述构建待执行量子程序对应的含权线路图，包括：
    获取所述待执行量子程序中的量子逻辑门和所述量子逻辑门操作的量子比特；
    基于所述量子逻辑门和所述量子逻辑门操作的量子比特，构建所述待执行量子程序对应的含权线路图，其中，所述含权线路图包括：顶点、无向边和边的权重，所述顶点用于表示所述量子逻辑门操作的量子比特，所述无向边用于表示所述量子逻辑门，所述边的权重根据操作相同量子比特的量子逻辑门数目确定。
  5. 根据权利要求4所述的方法，其特征在于，所述根据所述含权线路图和所述量子芯片的保真度，确定所述待执行量子程序的初始映射，包括：
    根据所述含权线路图，构建存储所述含权线路图无向边及边的权重信息的第一关联容器；
    遍历所述第一关联容器，确定所述待执行量子程序节点的映射优先级，其中，所述映射优先级根据所述权重从大到小依次排列；
    根据所述待执行量子程序节点的映射优先级和所述量子芯片的保真度，依次确定所 述待执行量子程序节点的映射关系；
    将所述依次确定的待执行量子程序节点的映射关系按照生成顺序排列，得到所述待执行量子程序的初始映射。
  6. 根据权利要求5所述的方法，其特征在于，所述根据所述待执行量子程序节点的映射优先级和所述量子芯片的保真度，依次确定所述待执行量子程序节点的映射关系，包括：
    确定所述待执行量子程序中的第一节点，其中，所述第一节点在所述第一关联容器中映射优先级最高；
    基于所述第一节点和所述量子芯片的保真度，确定所述第一节点的第一映射关系；
    删除所述第一关联容器中的所述第一节点，得到第二关联容器；
    确定当前第二关联容器中是否存在第二节点，其中，所述第二节点在所述第二关联容器中映射优先级最高；
    若所述第二关联容器中不存在所述第二节点，则获得所述待执行量子程序所确定的所有节点的映射关系。
  7. 根据权利要求6所述的方法，其特征在于，所述方法还包括：
    若所述第二关联容器中存在所述第二节点，则基于所述第二节点和当前所述量子芯片的保真度，确定所述第二节点的第二映射关系；
    删除所述第二关联容器中的所述第二节点，更新第二关联容器，返回执行所述确定所述当前第二关联容器中是否存在第二节点的步骤，直至所述第二关联容器中不存在所述第二节点为止。
  8. 根据权利要求4所述的方法，其特征在于，所述根据所述带权无向图，确定所述待执行量子程序中每个逻辑量子比特的第一参数，具体为：
    根据所述带权无向图中每个顶点的度数，确定每个逻辑量子比特的第一参数，其中，所述度数根据所述每个顶点相邻的无向边权重之和确定。
  9. 根据权利要求8所述的方法，其特征在于，所述根据所述量子芯片拓扑结构，获取所述量子芯片中每个物理量子比特的第二参数，包括：
    根据所述量子芯片拓扑结构，确定所述每个物理量子比特连接边的数量；
    根据所述每个物理量子比特连接边的数量，确定每个物理量子比特的第二参数。
  10. 根据权利要求9所述的方法，其特征在于，所述根据所述第一参数、第二参数和量子芯片的保真度，确定所述待执行量子程序的映射关系，包括：
    根据所述第一参数，确定所述待执行量子程序中的第一逻辑量子比特，其中，所述第一逻辑量子比特的第一参数数值最大；
    基于所述第二参数和量子芯片的保真度，确定所述第一逻辑量子比特的第一映射关系；
    删除所述第一逻辑量子比特，确定所述待执行量子程序中是否存在第二逻辑量子比 特，其中，所述第二逻辑量子比特的第一参数数值最大；
    若所述待执行量子程序中不存在所述第二逻辑量子比特，则获得所述待执行量子程序所确定的所有逻辑量子比特的映射关系。
  11. 根据权利要求10所述的方法，其特征在于，所述方法还包括：
    若所述待执行量子程序中存在所述第二逻辑量子比特，则基于当前所述第二参数和量子芯片的保真度，确定所述第二逻辑量子比特的第二映射关系；
    删除所述第二逻辑量子比特，更新所述待执行量子程序中的逻辑量子比特，返回执行所述确定所述待执行量子程序中是否存在第二逻辑量子比特的步骤，直至所述待执行量子程序中不存在所述第二逻辑量子比特为止。
  12. 一种与量子芯片的映射装置，其特征在于，所述装置包括：
    获取模块，用于获取待执行量子程序和可适配运行的量子芯片；
    构建模块，用于构建待执行量子程序对应的含权线路图；
    确定模块，用于根据所述含权线路图和所述量子芯片的保真度，确定所述待执行量子程序的初始映射，以使所述待执行量子程序初始映射对应的保真度最高。
  13. 一种存储介质，其特征在于，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行所述权利要求1至11任一项中所述的方法。
  14. 一种电子装置，包括存储器和处理器，其特征在于，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行所述权利要求1至11任一项中所述的方法。
  15. 一种量子计算机操作系统，其特征在于，所述量子计算机操作系统根据权利要求1至11任一项所述的方法实现量子程序与量子芯片的映射。
  16. 一种量子计算机，其特征在于，所述量子计算机包括权利要求15所述的量子计算机操作系统。
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CN112668722A (zh) * 2020-12-31 2021-04-16 北京百度网讯科技有限公司 量子电路处理方法、装置、设备、存储介质及产品

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