WO2023016379A1 - 计算机系统、基于PCIe设备的控制方法及相关设备 - Google Patents

计算机系统、基于PCIe设备的控制方法及相关设备 Download PDF

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Publication number
WO2023016379A1
WO2023016379A1 PCT/CN2022/110656 CN2022110656W WO2023016379A1 WO 2023016379 A1 WO2023016379 A1 WO 2023016379A1 CN 2022110656 W CN2022110656 W CN 2022110656W WO 2023016379 A1 WO2023016379 A1 WO 2023016379A1
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logic chip
pcie device
pcie
signal
processor
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PCT/CN2022/110656
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English (en)
French (fr)
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王吁
李钟�
许伟强
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华为技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of electronic technology, and in particular to a computer system, a method for controlling a PCIe-based device, and related devices.
  • PCIe peripheral component interconnect express
  • PCIe devices have more and more demands for other functions (such as hot plugging).
  • PCIe devices are usually controlled in a separate management and independent control manner.
  • the processor can be connected to the motherboard logic chip through the Inter-Integrated Circuit (I2C) bus and sub-board logic chip.
  • I2C Inter-Integrated Circuit
  • the NVMe hard disk is connected to the logic chip of the secondary board
  • the network card is connected to the logic chip of the main board.
  • the logic chip of the main board communicates with the processor to complete the control of the network card
  • the logic chip of the sub-board communicates with the processor to complete the control of the NVMe hard disk.
  • the logic chip directly connected to the processor consumes a lot of resources of the logic chip. Therefore, in the process of controlling the network card and the NVMe hard disk, a lot of resources of the logic chip of the main board and the logic chip of the sub-board will be consumed.
  • the resources of logic chips are limited, and the existing discrete management method may not be suitable for continuous development of other functions of PCIe devices.
  • Embodiments of the present application provide a computer system, a PCIe device-based control method, and related devices, which can reduce logic resource consumption on a logic chip when controlling a PCIe device.
  • the embodiment of the present application provides a computer system, which may include a processor, a main logic chip, a first slave logic chip, and a first PCIe device, wherein the processor and the main logic chip pass through the integrated circuit
  • the I2C bus is connected, the master logic chip is connected to the first slave logic chip, the first slave logic chip is connected to the first PCIe device, and the first slave logic chip can communicate with the processor through the master logic chip. Since the logic chip directly connected to the processor consumes a large amount of resources of the logic chip, in the embodiment of the present application, the first slave logic chip is not directly connected to the processor, but communicates with the processor through the master logic chip, thus The consumption of logic resources on the first slave logic chip can be reduced.
  • the master logic chip is connected to the first slave logic chip through a serial general input and output bus SGPIO.
  • the I2C bus consumes a lot of logic resources, but the SGPIO bus does not consume a lot of logic resources. Therefore, consumption of logic resources can be reduced.
  • the processor is configured to send the first control signal for the first PCIe device to the master logic chip; the master logic chip is configured to receive the first control signal and send the first control signal to the first slave logic chip. A control signal; the first slave logic chip is used to control the first PCIe device according to the first control signal. For example, hot plug control is performed on the first PCIe device.
  • a master logic chip is directly connected to the processor, and the slave logic chip is not directly connected to the processor, but is connected to the master logic chip.
  • the first slave logic chip controls the first PCIe device, it only needs to consume a lot of resources on the master logic chip, and does not need to consume a lot of resources on the slave logic chip.
  • the first slave logic chip receives the control signal for the first PCIe device from the master logic chip without obtaining it from the processor, so it can Reduce the consumption of logic resources from the logic chip.
  • the computer system can also include a baseboard controller BMC chip, and the BMC chip is connected to the first slave logic chip; the first slave logic chip is also used to receive data from the baseboard controller BMC chip for the first PCIe
  • the first trigger signal of the device is used to indicate hot plugging of the first PCIe device; the first slave logic chip is also used to obtain the presence signal of the first PCIe device; the first slave logic chip is also used to obtain the presence signal of the first PCIe device; It is used for sending the first trigger signal of the first PCIe device and the presence signal of the first PCIe device to the main logic chip.
  • the device identifier of the first PCIe device is stored in the main logic chip, and the main logic chip is also used to receive the first trigger signal and the presence signal of the first PCIe device, and send the first PCIe device to the processor.
  • the presence signal of the PCIe device sends a first control signal to the main logic chip, and the second control signal is used to instruct hot plugging of the first PCIe device.
  • the presence signal of the first PCIe device and the first trigger signal of the first PCIe device are not sent directly from the logic chip to the processor, but are sent from the master logic chip to the processor.
  • the slave logic chip does not directly communicate with the processor, and the consumption of logic resources on the slave logic chip can be reduced when performing hot plugging on the first PCIe.
  • the computer system further includes a second PCIe device, and the second PCIe device is connected to the main logic chip.
  • the first slave logic chip is also used to receive a second trigger signal from the BMC chip for the second PCIe device, and the second trigger information is used to indicate that the second PCIe device is hot-swapped; the first slave logic chip is used to Sending a second trigger signal of the second PCIe device to the main logic chip.
  • the device identifier of the second PCIe device is stored in the main logic chip, and the main logic chip is also used to obtain the in-position signal of the second PCIe device; the main logic chip is also used to send the signal to the processor The device identification of the second PCIe device, the in-position signal of the second PCIe device, and the second trigger signal of the second PCIe device; the processor is also configured to based on the device identification based on the second PCIe device, the second PCIe The in-position signal of the device and the second trigger signal of the second PCIe device send a second control signal to the main logic chip; the main logic chip is also used to control the second PCIe device according to the second control signal, for example, to The second PCIe device performs hot plugging.
  • the main logic chip can also control the second PCIe device connected to the main logic chip. In this way, regardless of whether the PCIe device is connected to the master logic chip or the slave logic chip, the PCIe device can be controlled.
  • the above computer system may further include a second slave logic chip and a third PCIe device, the second slave logic chip is connected to the master logic chip, and the third PCIe device is connected to the second slave logic chip. Since the logic chip directly connected to the processor consumes a large amount of resources of the logic chip, in the embodiment of the present application, the second slave logic chip is not directly connected to the processor, but communicates with the processor through the main logic chip. The consumption of logic resources on the second slave logic chip can be reduced.
  • the main logic chip is a complex programmable logic device CPLD chip or a field programmable gate array FPGA chip.
  • the present application provides a control method based on a PCIe device, the method is applied to a computer system, and the computer system includes a processor, a master logic chip, a first slave logic chip and a first PCIe device, and the method includes:
  • the master logic chip receives first control information for the first PCIe device from the processor, wherein the processor and the master logic chip are connected through an I2C bus between integrated circuits; the master logic chip sends a first controller signal to the first slave logic chip , the first control signal is used to instruct the first slave logic chip to control the first PCIe device, wherein the master logic chip is connected to the first slave logic chip, and the first slave logic chip is connected to the first PCIe device.
  • the master logic chip is connected to the first slave logic chip through a serial general input and output bus SGPIO.
  • the device identifier of the first PCIe device is stored in the main logic chip, and before the main logic chip receives the first control information for the first PCIe device from the processor, it further includes:
  • the master logic chip receives the first trigger signal from the first PCIe device of the slave logic chip and the presence signal of the first PCIe device, and the first trigger signal is used to indicate that the first PCIe device is hot-swapped; the master logic chip Send the device identification of the first PCIe device to the processor, the first trigger signal of the first PCIe device and the presence signal of the first PCIe device, the first control signal is based on the device identification of the first PCIe device, the first trigger signal and the first Presence signal generation for a PCIe device.
  • the main logic chip is connected to the second PCIe device, and the main logic chip stores the device identification of the second PCIe device, and the method further includes: the main logic chip receives the information from the processor for the A second control signal of the second PCIe device: the main logic chip controls the second PCIe device according to the second control signal.
  • the device identifier of the second PCIe device is stored in the main logic chip, and before the main logic chip receives the second control signal for the second PCIe device from the processor, it further includes: the main logic chip receives the The second trigger signal of the first slave logic chip for the second PCIe device, the second trigger information is used to indicate that the second PCIe device is hot-swapped; the master logic chip obtains the presence signal of the second PCIe device; the master logic chip Send the device identification of the second PCIe device, the presence signal of the second PCIe device, and the second trigger signal of the second PCIe device to the processor, and the second control signal is based on the device identification of the second PCIe device, the second trigger signal, and the second trigger signal An in-position signal of the second PCIe device is generated, and the second control signal is used to instruct hot plugging of the second PCIe device.
  • the embodiment of the present application provides an electronic device, the electronic device may include a logic chip, the logic chip stores computer instructions, and when the above computer instructions are run on the logic chip, the electronic device can execute the following steps:
  • the PCIe device-based control method provided by any one of the implementation manners in the two aspects.
  • FIG. 1 is a system schematic diagram of a discrete control method provided by an embodiment of the present application
  • Fig. 2 is a transmission schematic diagram of another discrete control system provided by the embodiment of the present application.
  • Fig. 3 is a schematic diagram of a computer system provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of another computer system provided by an embodiment of the present application.
  • Fig. 5 is a schematic diagram of another computer system provided by the embodiment of the present application.
  • FIG. 6 is a schematic flow chart of a method for controlling hot plugging of a PCIe device provided in an embodiment of the present application
  • FIG. 7 is a schematic flow chart of another method for controlling hot plugging of a PCIe device provided in an embodiment of the present application.
  • FIG. 8 is a schematic flowchart of another method for controlling hot plugging of a PCIe device provided by an embodiment of the present application.
  • first and “second” in the specification and drawings of the present application are used to distinguish different objects, or to distinguish different processes for the same object, rather than to describe a specific sequence of objects.
  • the terms “including” and “having” mentioned in the description of the present application and any variations thereof are intended to cover non-exclusive inclusion.
  • a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes other unlisted steps or units, or optionally also includes Other steps or elements inherent to the process, method, product or apparatus are included.
  • words such as “exemplarily” or “for example” are used as examples, illustrations or descriptions.
  • the high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) is mainly used for data interaction between the central processing unit (CPU) and peripheral devices.
  • the peripheral device can be a multi-category PCIe device based on the PCIe bus interface, for example, a multi-category PCIe device can include a non-volatile memory host controller interface specification (Non-Volatile Memory express, NVMe) hard disk, network card, graphics card, acquisition card , standard card, GPU, and other devices with different functions.
  • NVMe non-volatile memory host controller interface specification
  • Hot-swapping means that the host is powered on and plugged in, allowing users to take out or replace the PCIe devices attached to the host without shutting down the system or cutting off the power of the host, without affecting the operation of the host server system, thereby improving the system's resistance to faults Resilience, scalability, flexibility, etc.
  • FIG. 2 is a schematic transmission diagram of another discrete control system provided by an embodiment of the present application.
  • a single processor is used as an example to control N PCIe devices, and multi-processors can also be used to control N PCIe devices, such as hot-swapping control, which is not discussed in this embodiment of the present application. any restrictions.
  • N is a positive integer greater than or equal to 2.
  • the N PCIe devices can be devices with multiple types of functions, such as NVMe hard disks with storage functions, network cards with communication functions, graphics cards with display functions, capture cards with video capture functions, and so on.
  • N logic chips can be respectively connected to the processor through an I2C link. That is, each logic chip can communicate with the processor through an I2C link. Each logic chip is connected to each PCIe device. When it is necessary to control any one of the N PCIe devices, the logic chip connected to the PCIe device needs to perform data interaction with the processor through the I2C interface to control the The PCIe device performs control, such as hot plug control.
  • N PCIe devices require N logic chips, and the processor needs to connect the I2C links to the N logic chips, and each logic chip performs data interaction with the processor through the corresponding I2C interface. Control the hot plug function of PCIe devices.
  • the logic chip directly connected to the processor consumes a lot of resources of the logic chip, so the consumption of logic resources may be increased, which is not conducive to the continuous development of other functions of the PCIe device.
  • the embodiment of the present application provides a computer system, a control method based on PCIe equipment, and related devices, which can perform data interaction with the processor through a master logic chip, and other slave logic chips obtain and process data from the master logic chip. The final data is used to complete the control of the PCIe device connected to the above-mentioned slave logic chip.
  • FIG. 3 is a schematic diagram of a computer system 300 provided in an embodiment of the present application. It can be seen from FIG. 3 that the computer system 300 includes but is not limited to a processor 301 , a master logic chip 302 , a first slave logic chip 303 and a first PCIe device 304 .
  • the processor 301 may be connected to the master logic chip 302
  • the master logic chip 302 may be connected to the first slave logic chip 303
  • the first slave logic chip 303 may be connected to the first PCIe device 304 .
  • the first slave logic chip 303 may communicate with the processor 301 through the master logic chip 302 .
  • master logic chip 302 may also be connected to other slave logic chips, and the other slave logic chips may be connected to other PCIe devices.
  • processor 301 and the master logic chip 302 may be connected through an I2C bus, and the master logic chip 302 and the first slave logic chip 303 are connected through a non-I2C bus.
  • main logic chip 302 and other logic chips can also be connected through a non-I2C bus, wherein the non-I2C bus can include one or more of the following: a serial general-purpose input/output bus (Serial general-purpose input/output, SGPIO) bus, Universal Asynchronous Receiver/Transmitter (UART) bus, LPC bus (Low pin count Bus), etc.
  • SGPIO serial general-purpose input/output
  • UART Universal Asynchronous Receiver/Transmitter
  • LPC bus Low pin count Bus
  • the processor 301 may be connected to at least one PCIe device through a PCIe bus, and then the processor 301 may perform read and write interactions with the first PCIe device 304 in the at least one PCIe device.
  • the embodiment of the present application does not impose any limitation on the quantity and type of PCIe devices.
  • at least one PCIe device includes but is not limited to a network card, an NVMe hard disk, a graphics card, a capture card, and a standard card.
  • FIG. 4 is a schematic diagram of another computer system 400 provided by an embodiment of the present application.
  • a computer system 400 may include a main board 401 , a sub-board 402 and at least one PCIe device.
  • the processor 301 and at least one slave logic chip are installed on the main board 401
  • the main logic chip 302 is installed on the sub-board 402 .
  • the processor 301 on the main board 401 can be connected with the main logic chip 302 on the sub-board 402, and the main logic chip 302 can be connected with the first slave logic chip 303 in at least one slave logic chip on the main board 401, the first slave logic chip 303 may be connected to a first PCIe device 304 in at least one PCIe device.
  • the processor 301 and the master logic chip 302 may be connected through an I2C bus, and the master logic chip 302 and the first slave logic chip 303 may be connected through a non-I2C bus (such as an SGPIO bus). It can be understood that the master logic chip 302 and other logic chips in the at least one slave logic chip can also be connected through a non-I2C bus.
  • the non-I2C bus may include one or more of the following: SGPIO bus, Universal Asynchronous Receiver/Transmitter (UART) bus, LPC bus (Low pin count Bus), and the like.
  • the processor 301 can be connected to at least one PCIe device through a PCIe bus, and then the processor 301 can perform read and write interactions with the first PCIe device 304 in the at least one PCIe device.
  • the embodiment of the present application does not impose any limitation on the quantity and type of PCIe devices.
  • at least one PCIe device includes but is not limited to a network card, an NVMe hard disk, a graphics card, a capture card, and a standard card.
  • the motherboard also known as the main board, system board or mother board
  • the main circuit system that makes up the computer is installed on the motherboard, such as the basic input output system (Basic Input Output System, BIOS) chip and so on.
  • BIOS Basic Input Output System
  • the main board is the core component of the mainframe, server and other systems, and it is covered with various slots, supporting Universal Serial Bus (Universal Serial Bus, usb), PCIE, Universal Asynchronous Receiver/Transmitter (Uart), etc. protocol interface, and tightly connect various peripheral devices to complete tasks such as resource scheduling and allocation. All the components in the host computer are connected through the motherboard, and the control of the system memory, storage devices and other I/O devices during the normal operation of the computer needs to be completed through the motherboard.
  • USB Universal Serial Bus
  • Sub-boards are boards and frames that support other boards, devices, and interconnections between devices, and provide power and data signals to the supported devices.
  • the sub-board may include one or more of the following: a hardware backplane, a signal backplane, an adapter board, an expansion board, and the like.
  • the sub-board has fewer functions to be completed. That is, when the main logic chip is placed on the sub-board, the main logic chip can better support the data interaction between the main logic chip and the processor 301, and improve the speed of hot plug control of PCIe devices.
  • FIG. 5 is a schematic diagram of another computer system 500 provided by an embodiment of the present application.
  • a computer system 500 may include a main board 501 , a sub-board 502 and at least one PCIe device.
  • a processor 301 and a main logic chip 302 are installed on the main board 501
  • at least one slave logic chip is installed on the sub-board 502 .
  • the processor 301 on the main board 501 can be connected with the main logic chip 302 on the main board 501, and the main logic chip 302 can be connected with the first slave logic chip 303 in at least one slave logic chip on the sub board 502, the first slave logic chip 303 may be connected to a first PCIe device 304 in at least one PCIe device.
  • processor 301 and the master logic chip 302 may be connected through an I2C bus, and the master logic chip 302 and the first slave logic chip 303 may be connected through a non-I2C bus (such as an SGPIO bus). It can be understood that the master logic chip 302 and other logic chips in the at least one slave logic chip can also be connected through a non-I2C bus.
  • the processor 301 may be connected to at least one PCIe device through a PCIe bus, and then the processor 301 may perform read and write interactions with the first PCIe device 304 in the at least one PCIe device.
  • the embodiment of the present application does not impose any limitation on the quantity and type of PCIe devices.
  • at least one PCIe device includes but is not limited to a network card, an NVMe hard disk, a graphics card, a capture card, and a standard card.
  • the processor 301 shown in FIG. 3 , FIG. 4 and FIG. 5 may send the first control signal for the first PCIe device to the main logic chip 302 .
  • the master logic chip 302 can receive the first control signal from the processor 301 and send the first control signal to the first slave logic chip 302 .
  • the first slave logic chip 303 controls the first PCIe device 304 according to the first control signal, for example, performs hot plugging on the first PCIe device.
  • the first control signal may include a power control signal and an indication signal, wherein the power control signal is used to perform hot plug control (for example, power-on control or power-off control) to the first PCIe device, and the indication signal is used to control
  • the LED indicator light is used to indicate whether the power-on control or power-off control of the first PCIe device is completed.
  • the first slave logic chip 303 can start the power-on sequence control of the first PCIe device 304 according to the first power-on signal. After waiting for the first PCIe device 304 to be powered on, the first slave logic chip 303 may instruct the LED to be on (for example, always on) according to the first status indication signal. After the first PCIe device 304 is powered on, the first slave logic chip performs a reset operation on the first PCIe device.
  • the first slave logic chip 303 can start the power-off sequence control of the first PCIe device 304 according to the first power-off signal. After waiting for the first PCIe device 304 to be powered off, the first slave logic chip 303 may instruct the LED to turn off according to the second status indication signal. Before powering off the first PCIe device 304, the first slave logic chip performs a reset operation on the first PCIe device.
  • the computer system 300 shown in FIG. 3 , the computer system 400 shown in FIG. 4 , and the computer system 500 shown in FIG. 5 may further include a second PCIe device 305 .
  • the second PCIe device 305 shown in FIG. 3 , FIG. 4 and FIG. 5 may be connected to the main logic chip 302 . It should be noted that the second PCIe device is not the same type of PCIe device as the first PCIe device.
  • the first PCIe device may be a network card, and the second PCIe device may be an NVMe hard disk.
  • the processor 301 may send a second control signal for the second PCIe device to the main logic chip 302 .
  • the main logic chip 302 may receive the second control signal from the processor 301, and control the second PCIe device according to the second control signal, such as hot plugging. Wherein, if the second control signal includes the second power-on signal and the third status indication signal, the main logic chip 302 can start the power-on sequence control of the second PCIe device 305 according to the second power-on signal. After waiting for the second PCIe device 305 to be powered on, the main logic chip 302 may instruct the LED to be on (for example, always on) according to the third status indication signal. If the second control signal includes the second power-off signal and the fourth status indication signal, the main logic chip 302 can start the power-off sequence control of the second PCIe device 305 according to the second power-off signal. After waiting for the second PCIe device 305 to be powered off, the main logic chip 302 may instruct the LED to turn off according to the fourth status indication signal.
  • the computer system 300 shown in FIG. 3 , the computer system 400 shown in FIG. 4 and the computer system 500 shown in FIG. 5 may further include a second slave logic chip 307 and a third PCIe device 308 .
  • the second slave logic chip 307 shown in FIG. 3 , FIG. 4 and FIG. 5 may be connected to the master logic chip 302
  • the third PCIe device 308 may be connected to the second slave logic chip 307
  • the third PCIe device 308 may not be the same type of PCIe device as the first PCIe device 304 and the second PCIe device 305 .
  • the first PCIe device 304 may be a network card
  • the second PCIe device 305 may be an NVMe hard disk
  • the third PCIe device 308 may be a capture card.
  • the processor 301 may send a third control signal for the third PCIe device 308 to the main logic chip 302 .
  • the master logic chip 302 can receive the third control signal from the processor 301 and send the third control signal to the second slave logic chip 307 .
  • the second slave logic chip 307 can control the third PCIe device 308 according to the third control signal, such as hot plugging. Wherein, if the third control signal includes the third power-on signal and the fifth status indication signal, the second slave logic chip 307 can start the power-on sequence control of the third PCIe device 308 according to the third power-on signal. After waiting for the third PCIe device 308 to be powered on, the second slave logic chip 307 may instruct the LED to be on (for example, always on) according to the fifth status indication signal. If the second control signal includes the third power-off signal and the sixth status indication signal, the second slave logic chip 307 can start the power-off sequence control of the third PCIe device 308 according to the third power-off signal. After waiting for the third PCIe device 308 to be powered off, the second slave logic chip 307 may instruct the LED to turn off according to the sixth status indication signal.
  • the third control signal includes the third power-on signal and the fifth status indication signal
  • the second slave logic chip 307 After waiting for the third
  • the computer system 300 shown in FIG. 3 and the computer system 400 shown in FIG. 4 may further include a baseboard management controller (baseboard management controller, BMC) chip 306 .
  • BMC baseboard management controller
  • the BMC chip 306 may be connected to the first slave logic chip 303 or the second slave logic chip 307 .
  • the first slave logic chip 303 can be connected to the second slave logic chip 307 .
  • the BMC chip 306 can send a first trigger signal for the first PCIe device 304 to the first slave logic chip 303, and the first trigger signal is used to indicate to perform control on the first PCIe device 304, For example, hot-swap control.
  • the BMC chip 306 may also send a third trigger signal for the third PCIe device 308 to the second slave logic chip 307, where the third trigger signal is used to instruct to perform control on the third PCIe device 308, such as hot plug control.
  • the BMC chip 306 can also send a second trigger signal for the second PCIe device to the first slave logic chip 303 or the second slave logic chip 307, and the second trigger signal is used to indicate to perform control on the second PCIe device 304, such as thermal Plug and unplug.
  • the computer system 500 shown in FIG. 5 may further include a BMC chip 306 .
  • the BMC chip 306 can be connected with the main logic chip 302 .
  • the BMC chip 306 can send a first trigger signal for the first PCIe device 304 to the main logic chip 302, and the first trigger signal is used to indicate to control the first PCIe device 304, for example, perform hot plugging on the first PCIe device 304 .
  • the BMC chip 306 may also send a second trigger signal for the second PCIe device 305 to the main logic chip 302, where the second trigger signal is used to instruct to control the second PCIe device 305, such as hot plug control.
  • the BMC chip 306 can also send a third trigger signal for the third PCIe device 308 to the main logic chip 302, and the third trigger signal is used to indicate to control the third PCIe device 308, for example, perform hot plugging on the third PCIe device 308 pull.
  • first slave logic chip 303 and the second slave logic chip 307 may not be on a single board (such as the main board 401 ).
  • first slave logic chip is on the main board 401
  • second slave logic chip is on the sub-board 402 ; or the first slave logic chip 303 , the second slave logic chip 307 and the master logic chip 302 are on different single boards.
  • processor 301 shown in FIG. 3 , FIG. 4 and FIG. 5 may be a central processing unit (central processing unit, CPU), a platform controller (platform controller hub, PCH) or a dedicated processor, etc. capable device. Further, the processor 301 may be a single-core processor or a multi-core processor.
  • FIG. 6 is a schematic flowchart of a PCIe-based device control method provided by an embodiment of the present application. This method can be applied to the computer system shown in FIG. 3 or FIG. 4. The method includes but is not limited to the following steps :
  • the computer system can also include a basic input output system (Basic Input Output System, BIOS) chip.
  • BIOS chip is a block-shaped memory that stores a basic input output system program. , to detect and initialize the various components of the system.
  • the processor 301 may also include a device driver and a hot-swap driver, through which the PCIe device can be read/written, and the hot-swap driver can be used to allocate memory resources for the PCIe device.
  • Step S601 the first slave logic chip receives a first trigger signal from the BMC chip for the first PCIe device.
  • the computer system may further include a baseboard management controller (BMC), and the BMC chip is located on the motherboard and connected to the processor 301.
  • BMC can set the corresponding virtual button BUTTON for each PCIe device.
  • the BMC can send the first trigger signal for the first PCIe device to the first slave logic chip, so the first slave logic chip can receive the trigger signal for the first PCIe device from the BMC. The first PCIe device to the first trigger signal.
  • step S602 the first slave logic chip acquires the presence signal of the first PCIe device.
  • the PCIe device has two pins corresponding to the hot plugging signals PRSNT1# and PRSNT2# for the hot plugging mechanism.
  • the two signal pins on the PCIe device are short-circuited, the PRSNT1# of the PCIe slot is fixedly connected to the ground, and the PRSNT2# is pulled up, and the length of the golden finger of the two signals on the PCIe device is longer than The golden fingers of other signals are shorter.
  • the PRSNT2# signal of the slot will always be in a high level state due to the pull-up effect.
  • the PRSNT2# signal on the slot will be Connected to ground by the short wire of the PCIE device, thus making it low.
  • the first PCIe device is connected to the first slave logic chip, and the first slave logic chip can obtain the presence signal of the first PCIe device according to PRSNT1# and PRSNT2# of the first PCIe device.
  • the PRSNT2# signal of the slot will always be in a high level state due to the pull-up effect.
  • the PRSNT2# signal on the slot The PRSNT2# signal will be connected to the ground by the short-circuit wire of the PCIe device, thereby making it low.
  • PRSNT2# when PRSNT2# is high, it is considered that the PCIe device is not inserted correctly or there is no PCIe device; when PRSNT2# is low, it indicates that the PCIe device is correctly inserted into the slot .
  • the same voltage signal may correspond to different in-position signals.
  • the low level may correspond to the presence signal being "0”
  • the low level may correspond to the absence signal being "0”. Therefore, different PCIe devices correspond to different processing rules, and the first slave logic chip can determine the presence signal of the first PCIe device corresponding to PRSNT1# and PRSNT2# according to the processing rule of the first PCIe device.
  • Step S603 the first slave logic chip sends the first trigger signal of the first PCIe device and the presence signal of the first PCIe device to the master logic chip.
  • the first slave logic chip may continuously send the first trigger signal and the first presence signal for the first PCIe device to the master logic chip.
  • Step S604 the main logic chip sends the device identifier of the first PCIe device, the first trigger signal of the first PCIe device and the presence signal of the first PCIe device to the processor.
  • the device identifier of the first PCIe device is stored in the master logic chip. After receiving the first trigger signal of the first PCIe device from the first slave logic chip and the presence signal of the first PCIe device, the master logic chip The device identification of the first PCIe device stored in the main logic chip can be queried, and then the device identification of the first PCIe device, the first trigger signal of the first PCIe device and the in-position signal of the first PCIe device are packaged, Send the packed signal to the processor.
  • the main logic chip in order to avoid falsely triggering the hot plug event, the main logic chip needs to judge the received first trigger signal, and the level of the first trigger signal remains unchanged within a preset time period In the case of , it means that there is a hot plug event of the first PCIe device; when the level of the first trigger signal changes within the preset time period, it means that the virtual button of the BMC may be misoperated. Therefore, when the main logic chip judges that there is a hot plug event of the first PCIe device according to the level change of the first trigger signal within the preset time period, step S604 is executed; If it is judged by the level change in the segment that there is no hot plug event of the first PCIe device, step S603 is executed.
  • Step S605 the processor receives the device identifier of the first PCIe device, the first trigger signal of the first PCIe device and the presence signal of the first PCIe device from the main logic chip.
  • the processor stores the slot number corresponding to the device identifier of the first PCIe device, and the processor can query the slot number of the first PCIe device according to the device identifier of the first PCIe device.
  • the processor can remove or add the first PCIe device by the controller hot-swap drive according to the detection of the first trigger signal of the first PCIe device and the change of the presence signal of the first PCIe device by the hot-swap controller, and A first control signal for the first PCIe device is generated by reading and writing the register state of the corresponding PCIe slot according to the slot number of the first PCIe device.
  • Step S606 the processor sends a first control signal to the main logic chip.
  • the processor may send the first control signal for the first PCIe device to the main logic chip through the I2C bus.
  • Step S607 the master logic chip sends a first control signal to the first slave logic chip.
  • the master logic chip may send the first control signal for the first PCIe device to the first slave logic chip through the SGPIO bus.
  • Step S608 the first slave logic chip controls the first PCIe device according to the first control signal.
  • the first slave logic chip may perform hot plugging on the first PCIe device according to the first control signal. Further, when the first control signal received by the first slave logic chip includes the first power-on signal and the first status indication signal, the first slave logic chip can start the power-on of the first PCIe device according to the first power-on signal timing control. After waiting for the first PCIe device to be powered on, the first slave logic chip may instruct the LED to be on (for example, always on) according to the first status indication signal. After the first PCIe device is powered on, the first slave logic chip performs a reset operation on the first PCIe device.
  • the first slave logic chip can The power-on signal starts the power-off sequence control of the first PCIe device. After waiting for the first PCIe device to be powered off, the first slave logic chip may instruct the LED to turn off according to the second status indication signal.
  • FIG. 7 is a schematic flow chart of another PCIe-based device manufacturing method provided by the embodiment of the present application. This method can be applied to the computer system shown in FIG. 3 or FIG. 4, and the method includes but is not limited to the following step:
  • step S701 the first slave logic chip receives a second trigger signal for the second PCIe device from the BMC chip.
  • the BMC can set a corresponding virtual button BUTTON for each PCIe device.
  • the BMC can send a second trigger signal for the second PCIe device to the first slave logic chip, so the first slave logic chip can receive the trigger signal for the second PCIe device from the BMC. Second PCIe device to second trigger signal.
  • Step S702 the first slave logic chip sends a second trigger signal for the second PCIe device to the master logic chip.
  • the first slave logic chip may send a second trigger signal for the second PCIe device to the master logic chip through the SGPIO.
  • step S703 the main logic chip acquires an in-position signal of the second PCIe device.
  • the second PCIe device is connected to the main logic chip, and the main logic chip can obtain the presence signal of the second PCIe device according to PRSNT1# and PRSNT2# of the second PCIe device.
  • Step S704 the main logic chip sends the device identification of the second PCIe device, the presence signal of the second PCIe device and the second trigger signal of the second PCIe device to the processor.
  • the device identifier of the second PCIe device is stored in the master logic chip.
  • the master logic chip can read the device identifier stored in the master logic chip.
  • the device identification of the first PCIe device in the first PCIe device, then the device identification of the first PCIe device, the first trigger signal of the first PCIe device and the in-position signal of the first PCIe device are packaged, and the packaged signal is sent to the processor send.
  • the main logic chip in order to avoid falsely triggering the hot plug event, the main logic chip needs to judge the received second trigger signal, and the level of the second trigger signal remains unchanged within a preset time period In the case of , it means that there is a hot plug event of the second PCIe device; when the level of the second trigger signal changes within the preset time period, it means that the virtual button of the BMC may be misoperated. Therefore, when the main logic chip judges that there is a hot plug event of the second PCIe device according to the level change of the second trigger signal within the preset time period, step S704 is executed; If it is judged that there is no hot plug event of the second PCIe device due to the level change in the segment, step S702 is executed.
  • Step S705 the processor receives the device identifier of the second PCIe device, the second trigger signal of the second PCIe device and the presence signal of the second PCIe device from the main logic chip.
  • the slot number corresponding to the device identifier of the second PCIe device is stored in the processor, and the processor can query the slot number of the second PCIe device according to the device identifier of the second PCIe device.
  • the processor can detect events such as the second trigger signal of the second PCIe device and the change of the presence signal of the second PCIe device by the hot-swap controller, so as to remove or add the second PCIe device by the controller for hot-swap driving, and A second control signal for the second PCIe device is generated by reading and writing the register state of the corresponding PCIe slot according to the slot number of the second PCIe device.
  • Step S706 the processor sends a second control signal to the main logic chip.
  • the processor may send a second control signal for the second PCIe device to the main logic chip through the I2C bus.
  • Step S707 the main logic chip controls the second PCIe device according to the second control signal.
  • the main logic chip may control the second PCIe device according to the second control signal, for example, perform hot plugging on the second PCIe device. Further, when the second control signal received by the main logic chip includes the second power-on signal and the third status indication signal, the main logic chip can start the power-on sequence control of the second PCIe device according to the second power-on signal. After waiting for the second PCIe device to be powered on, the main logic chip can instruct the LED to be on (for example, always on) according to the third status indication signal. After the second PCIe device is powered on, the main logic chip performs a reset operation on the first PCIe device.
  • the main logic chip can start the second PCIe device according to the second power-off signal. Power-off sequence control of PCIe devices. After waiting for the second PCIe device to be powered off, the main logic chip may instruct the LED to turn off according to the fourth status indication signal.
  • FIG. 8 is a schematic flowchart of another PCIe-based device control method provided by the embodiment of the present application. This method can be applied to the computer system shown in FIG. 3 or FIG. 4. The method includes but is not limited to the following step:
  • step S801 the second slave logic chip receives a third trigger signal from the BMC chip for the third PCIe device.
  • the computer system may further include a baseboard management controller (BMC), and the BMC chip is located on the motherboard and connected to the processor 301.
  • BMC can set the corresponding virtual button BUTTON for each PCIe device.
  • the BMC can send the third trigger signal for the third PCIe device to the second slave logic chip, so the second slave logic chip can receive the trigger signal for the third PCIe device from the BMC.
  • the third PCIe device to the third trigger signal.
  • step S802 the second slave logic chip acquires an in-position signal of the third PCIe device.
  • the PCIe device has two pins corresponding to the hot plugging signals PRSNT1# and PRSNT2# for the hot plugging mechanism.
  • the two signal pins on the PCIe device are short-circuited, the PRSNT1# of the PCIe slot is fixedly connected to the ground, and the PRSNT2# is pulled up, and the length of the golden finger of the two signals on the PCIe device is longer than The golden fingers of other signals are shorter.
  • the PRSNT2# signal of the slot will always be in a high level state due to the pull-up effect.
  • the PRSNT2# signal on the slot will be Connected to ground by the short wire of the PCIE device, thus making it low.
  • the third PCIe device is connected to the second slave logic chip, and the second slave logic chip can obtain the presence signal of the third PCIe device according to PRSNT1# and PRSNT2# of the third PCIe device.
  • the PRSNT2# signal of the slot will always be in a high level state due to the pull-up effect.
  • the PRSNT2# signal on the slot The PRSNT2# signal will be connected to the ground by the short-circuit wire of the PCIe device, thereby making it low.
  • PRSNT2# when PRSNT2# is high, it is considered that the PCIe device is not inserted correctly or there is no PCIe device; when PRSNT2# is low, it indicates that the PCIe device is correctly inserted into the slot .
  • the same voltage signal may correspond to different in-position signals.
  • the low level may correspond to the presence signal being "0”
  • the low level may correspond to the absence signal being "0”. Therefore, different PCIe devices correspond to different processing rules, and the second slave logic chip can determine the presence signal of the third PCIe device corresponding to PRSNT1# and PRSNT2# according to the processing rule of the third PCIe device.
  • Step S803 the second slave logic chip sends the third trigger signal of the third PCIe device and the presence signal of the third PCIe device to the master logic chip.
  • the second slave logic chip may continuously send the third trigger signal and the third presence signal for the third PCIe device to the master logic chip.
  • Step S804 the main logic chip sends the device identifier of the third PCIe device, the third trigger signal of the third PCIe device and the presence signal of the third PCIe device to the processor.
  • the device identification of the third PCIe device is stored in the master logic chip, and after receiving the third trigger signal and the presence signal of the third PCIe device from the second slave logic chip, the master logic chip
  • the device identification of the third PCIe device stored in the main logic chip can be queried, and then the device identification of the third PCIe device, the third trigger signal of the third PCIe device and the in-position signal of the third PCIe device are packaged, Send the packed signal to the processor.
  • the main logic chip in order to avoid falsely triggering the hot plug event, the main logic chip needs to judge the received third trigger signal, and the level of the third trigger signal remains unchanged within a preset time period In the case of , it means that there is a hot plug event of the third PCIe device; when the level of the third trigger signal changes within a preset time period, it means that the virtual button of the BMC may be misoperated. Therefore, when the main logic chip judges that there is a hot plug event of the third PCIe device according to the level change of the third trigger signal within the preset time period, step S804 is performed; If it is judged by the level change in the segment that there is no hot plug event of the third PCIe device, step S803 is executed.
  • Step S805 the processor receives the device identifier of the third PCIe device, the third trigger signal of the third PCIe device and the presence signal of the third PCIe device from the main logic chip.
  • the processor stores the slot number corresponding to the device identifier of the third PCIe device, and the processor can query the slot number of the third PCIe device according to the device identifier of the third PCIe device.
  • the processor can remove or add the third PCIe device by the controller hot-swap driver according to the detection of the third trigger signal of the third PCIe device and the change of the presence signal of the third PCIe device by the hot-swap controller, and A third control signal for the third PCIe device is generated by reading and writing the register state of the corresponding PCIe slot according to the slot number of the third PCIe device.
  • Step S806 the processor sends a third control signal to the main logic chip.
  • the processor may send a third control signal for the third PCIe device to the main logic chip through the I2C bus.
  • Step S807 the master logic chip sends a third control signal to the second slave logic chip.
  • the master logic chip may send a third control signal for the third PCIe device to the second slave logic chip through a non-I2C bus.
  • Step S808 the second slave logic chip controls the third PCIe device according to the third control signal.
  • the second slave logic chip may perform hot plug control on the third PCIe device according to the third control signal. Further, when the third control signal received by the second slave logic chip includes the third power-on signal and the fifth status indication signal, the second slave logic chip can start the power-on of the third PCIe device according to the third power-on signal timing control. After waiting for the third PCIe device to be powered on, the second slave logic chip may instruct the LED to be on (for example, always on) according to the fifth status indication signal. After the third PCIe device is powered on, the second slave logic chip performs a reset operation on the third PCIe device.
  • the second slave logic chip can The three power-off signals start the power-off sequence control of the third PCIe device. After waiting for the third PCIe device to be powered off, the second slave logic chip can indicate that the LED light is off according to the sixth status indication signal.
  • step S701 shown in FIG. 7 can be replaced with "the second slave logic chip receives the second trigger signal for the second PCIe device from the BMC chip.”
  • step S702 can be replaced with "the second slave logic chip sends the master logic chip Send a second trigger signal for the second PCIe device”.
  • a processor and a main logic chip are installed on the main board, and a first slave logic chip or a second slave logic chip is installed on the sub board.
  • the BMC is installed on the main board, so the method applied on the computer system shown in Figure 5 is relative to the method applied on the computer system shown in Figure 4, the BMC can directly send the first PCIe device to the main logic chip.
  • steps S601 to S605 shown in FIG. 6 can be replaced by the following steps:
  • step S901 the first slave logic chip acquires the presence signal of the first PCIe device.
  • step S902 the first slave logic chip sends a presence signal of the first PCIe device to the master logic chip.
  • Step S903 the main logic chip sends the device identifier of the first PCIe device and the presence signal of the first PCIe device to the processor.
  • Step S904 the processor receives a first trigger signal for the first PCIe device from the system application layer, and a device identifier of the first PCIe device and a presence signal of the first PCIe device from the main logic chip.
  • the first trigger signal carries a control command for the first PCIe device, such as a hot plug command or a hot unplug command.
  • the user may input a first trigger signal for the first PCIe device through an application installed in the system application layer, and the first trigger signal includes a control instruction for controlling the first PCIe device, for example, for controlling the first PCIe device.
  • the slot number corresponding to the device identifier of the first PCIe device is stored in the processor, and the processor can query the slot number of the first PCIe device according to the device identifier of the first PCIe device.
  • the processor can remove or add the first PCIe device by the controller hot-swap drive according to the detection of the first trigger signal of the first PCIe device and the change of the presence signal of the first PCIe device by the hot-swap controller, and A first control signal for the first PCIe device is generated by reading and writing the register state of the corresponding PCIe slot according to the slot number of the first PCIe device.
  • steps S701 to S704 shown in FIG. 7 can be replaced by the following steps:
  • step S1001 the main logic chip acquires the presence signal of the second PCIe device.
  • Step S1002 the main logic chip sends the device identification of the second PCIe device and the presence signal of the second PCIe device to the processor.
  • Step S1003 the processor receives an operation instruction for the second PCIe device from the system application layer, and the device identification of the second PCIe device and the presence signal of the second PCIe device from the main logic chip.
  • the first trigger signal carries a control command for the second PCIe device, such as a hot-plug command or a hot-swap command.
  • the user can input a second trigger signal for the second PCIe device through an application installed in the system application layer, and the second trigger signal includes a control instruction for controlling the second PCIe device, for example, for controlling the second PCIe device.
  • the slot number corresponding to the device identification of the second PCIe device is stored in the processor, and the processor can query the slot number of the second PCIe device according to the device identification of the second PCIe device.
  • the processor can detect events such as the second trigger signal of the second PCIe device and the change of the presence signal of the second PCIe device by the hot-swap controller, so as to remove or add the second PCIe device by the controller for hot-swap driving, and A second control signal for the second PCIe device is generated by reading and writing the register state of the corresponding PCIe slot according to the slot number of the second PCIe device.
  • steps S801 to S805 shown in FIG. 8 can be replaced by the following steps:
  • step S1101 the second slave logic chip acquires the presence signal of the third PCIe device.
  • step S1102 the second slave logic chip sends an in-position signal of the third PCIe device to the master logic chip.
  • Step S1103 the main logic chip sends the device identifier of the third PCIe device and the presence signal of the third PCIe device to the processor.
  • step S1104 the processor receives a third trigger signal for the third PCIe device from the system application layer, and a device identifier of the third PCIe device and a presence signal of the third PCIe device from the main logic chip.
  • the third trigger signal carries a control command for the third PCIe device, such as a hot plug command or a hot unplug command.
  • the user can input a third trigger signal for the third PCIe device through an application installed in the system application layer, and the third trigger signal includes a control instruction for controlling the operation of the third PCIe device, for example, for controlling the third PCIe device.
  • the slot number corresponding to the device identifier of the third PCIe device is stored in the processor, and the processor can query the slot number of the third PCIe device according to the device identifier of the third PCIe device.
  • the processor can remove or add the third PCIe device by the controller hot-swap driver according to the detection of the third trigger signal of the third PCIe device and the change of the presence signal of the third PCIe device by the hot-swap controller, and A third control signal for the third PCIe device is generated by reading and writing the register state of the corresponding PCIe slot according to the slot number of the third PCIe device.
  • An electronic device provided in an embodiment of the present application may include a logic chip, and the logic chip may be the main logic chip 302 in FIG. 3 , FIG. 4 or FIG. 5 .
  • the main logic chip 302 may specifically be a complex programmable logic device (Complex programmable logic device, CPLD), and computer instructions are stored in the main logic chip 302.
  • CPLD complex programmable logic device
  • the electronic device can execute the above-mentioned A control method based on PCIe devices. For example, the flow of the PCIe device-based control method described in any one of the embodiments in FIG. 6 , FIG. 7 or FIG. 8 .
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

Abstract

本申请实施例提供一种计算机系统、基于PCIe设备的控制方法及相关设备，该计算机系统可以包括处理器、主逻辑芯片、第一从逻辑芯片和第一PCIe设备，其中，处理器与主逻辑芯片通过集成电路间I2C总线连接，主逻辑芯片与第一从逻辑芯片连接，第一从逻辑芯片和第一PCIe设备连接，第一从逻辑芯片通过主逻辑芯片与处理器通信。采用本申请实施例，能够在控制PCIe设备时，减少逻辑芯片上的逻辑资源消耗。

Description

计算机系统、基于PCIe设备的控制方法及相关设备
本申请要求于2021年08月12日提交中国专利局、申请号为202110924620.4、申请名称为“计算机系统、基于PCIe设备的控制方法及相关设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，尤其涉及一种计算机系统、基于PCIe设备的控制方法及相关设备。
背景技术
当前计算行业向多算力计算系统演进，对不同的输入/输出(Input/Output，IO)通信以及算力的要求越来越多元化。为了实现上述诉求，一般可以通过快捷外围部件互连总线标准(peripheral component interconnect express，PCIe)总线作为桥梁来完成所算力计算系统的集成工作。在硬件池化的思路下，基于PCIe协议的各种PCIe设备，比如说图像处理器(graphics processing unit，GPU)，非易失性存储器(non-volatile memory express，NVMe)、固态硬盘(solid state drives，SSD)、网卡等多种设备也可以被集成在一个硬件框架系统下工作。
随着PCIe池化技术的发展，对PCIe设备的管理提出了更高的要求，比如说资源利用最大化、PCIe设备可拓展性等。在这种背景下，PCIe设备对其他功能(比如说热插拔)的需求也越来越多。目前，通常使用分立管理和独立控制的方式对PCIe设备进行控制。以NVMe硬盘和网卡这两种类型的PCIe设备为例，请参见图1所示的分立控制方法的系统示意图，处理器可以通过集成电路间总线(Inter－Integrated Circuit，I2C)连接到主板逻辑芯片和副板逻辑芯片上。其中，NVMe硬盘连接在副板逻辑芯片上，网卡连接在主板逻辑芯片上。然后，由主板逻辑芯片与处理器进行通信来完成对网卡的控制，由副板逻辑芯片与处理器进行通信来完成对NVMe硬盘的控制。
但是，与处理器直接连接的逻辑芯片会消耗逻辑芯片大量的资源，因此，对网卡和NVMe硬盘进行控制过程中，会消耗主板逻辑芯片和副板逻辑芯片大量的资源。而随着越来越多PCIe设备对其他功能需求的增多，逻辑芯片的资源有限，现有的分立管理的方法可能不适合对PCIe设备的其他功能的持续开发。
发明内容
本申请实施例提供一种计算机系统、基于PCIe设备的控制方法及相关设备，能够在控制PCIe设备时，减少逻辑芯片上的逻辑资源消耗。
第一方面，本申请实施例提供了一种计算机系统，该计算机系统可以包括处理器、主逻辑芯片、第一从逻辑芯片和第一PCIe设备，其中，处理器与主逻辑芯片通过集成电路间I2C总线连接，主逻辑芯片与第一从逻辑芯片连接，第一从逻辑芯片和第一PCIe设备连接，第一从逻辑芯片通过上述主逻辑芯片可以与处理器通信。由于与处理器直接连接的逻辑芯片会消耗逻辑芯片大量的资源，因此在本申请实施例中，第一从逻辑芯片不与处理器直接连接，而是通过主逻辑芯片与处理器进行通信，这样可以减少第一从逻辑芯片上的逻辑资源的消耗。
可选地，主逻辑芯片与第一从逻辑芯片通过串行通用输入输出总线SGPIO连接。在逻辑芯片中，I2C总线会消耗大量的逻辑资源，而SGPIO总线不会消耗大量的逻辑资源。因此，可以减少逻辑资源的消耗。
一种可能的实施方式中，处理器，用于向主逻辑芯片发送针对第一PCIe设备的第一控制信号；主逻辑芯片，用于接收第一控制信号，并向第一从逻辑芯片发送第一控制信号；第一从逻辑芯片，用于根据第一控制信号对第一PCIe设备进行控制。比如说对第一PCIe设备进行热插拔控制。
由于与处理器直接连接的逻辑芯片会消耗逻辑芯片大量的资源，在本申请中通过一个主逻辑芯片与处理器直接连接，从逻辑芯片不与处理器直接连接，而是与主逻辑芯片连接。这样，在第一从逻辑芯片对第一PCIe设备进行控制时，只需要消耗主逻辑芯片上的大量的资源，不用消耗从逻辑芯片上的大量资源。举例来说，通过本申请对第一PCIe设备的热插拔进行控制时，第一从逻辑芯片接收来自主逻辑芯片的针对第一PCIe设备的控制信号，而不用从处理器处获得，因此可以减少从逻辑芯片上的逻辑资源的消耗。
一种可能的实施方式中，计算机系统还可以包括基板控制器BMC芯片，BMC芯片和第一从逻辑芯片连接；第一从逻辑芯片，还用于接收来自基板控制器BMC芯片的针对第一PCIe设备的第一触发信号，第一触发信号用于指示对第一PCIe设备执行热插拔；第一从逻辑芯片，还用于获取第一PCIe设备的在位信号；第一从逻辑芯片，还用于向主逻辑芯片发送第一PCIe设备的第一触发信号和第一PCIe设备的在位信号。
一种可能的实施方式中，主逻辑芯片中存储有第一PCIe设备的设备标识，主逻辑芯片，还用于接收第一触发信号和第一PCIe设备的在位信号，并向处理器发送第一PCIe设备的设备标识、第一PCIe设备的第一触发信号和第一PCIe设备的在位信号；处理器，具体用于基于所述第一PCIe设备的设备标识、第一触发信号以及第一PCIe设备的在位信号向主逻辑芯片发送第一控制信号，第二控制信号用于指示对第一PCIe设备执行热插拔。
可以看出，第一PCIe设备的在位信号、第一PCIe设备的第一触发信号不是由从逻辑芯片直接向处理器发送的，而是由主逻辑芯片向处理器发送的。这样，从逻辑芯片没有与处理器进行直接通信，在对第一PCIe执行热插时，可以减少从逻辑芯片上的逻辑资源的消耗。
一种可能的实施方式中，计算机系统还包括第二PCIe设备，第二PCIe设备与主逻辑芯片连接。第一从逻辑芯片，还用于接收来自BMC芯片的针对第二PCIe设备的第二触发信号，第二触发信息用于指示对第二PCIe设备执行热插拔；第一从逻辑芯片，用于向主逻辑芯片发送第二PCIe设备的第二触发信号。
一种可能的实施方式中，主逻辑芯片中存储有第二PCIe设备的设备标识，主逻辑芯片，还用于获取第二PCIe设备的在位信号；主逻辑芯片，还用于向处理器发送第二PCIe设备的设备标识、第二PCIe设备的在位信号和第二PCIe设备的第二触发信号；处理器，还用于基于基于所述第二PCIe设备的设备标识、所述第二PCIe设备的在位信号和所述第二PCIe设备的第二触发信号向主逻辑芯片发送第二控制信号；主逻辑芯片，还用于根据第二控制信号对第二PCIe设备进行控制，比如说对第二PCIe设备执行热插拔。
可以看出，主逻辑芯片也可以对连接在主逻辑芯片上的第二PCIe设备进行控制。这样，不论PCIe设备是与主逻辑芯片连接还是与从逻辑芯片，都可以对PCIe设备进行控制。
一种可能的实施方式中，上述计算机系统还可以包括第二从逻辑芯片和第三PCIe设备，第二从逻辑芯片和主逻辑芯片连接，第三PCIe设备和第二从逻辑芯片连接。由于与处理器直接连接的逻辑芯片会消耗逻辑芯片大量的资源，因此在本申请实施例中，第二从逻辑芯片不 与处理器直接连接，而是通过主逻辑芯片与处理器进行通信，这样可以减少第二从逻辑芯片上的逻辑资源的消耗。
一种可能的实施方式中，主逻辑芯片为复杂可编程逻辑器件CPLD芯片或现场可编程门阵列FPGA芯片。
第二方面，本申请提供一种基于PCIe设备的控制方法，该方法应用于计算机系统，计算机系统包括处理器、主逻辑芯片、第一从逻辑芯片和第一PCIe设备，方法包括：
主逻辑芯片接收来自处理器的针对第一PCIe设备的第一控制信息，其中，处理器与主逻辑芯片通过集成电路间I2C总线连接；主逻辑芯片向第一从逻辑芯片发送第一控制器信号，第一控制信号用于指示第一从逻辑芯片对第一PCIe设备进行控制，其中，主逻辑芯片与第一从逻辑芯片连接，第一从逻辑芯片和第一PCIe设备连接。
一种可能的实施方式中，主逻辑芯片与第一从逻辑芯片通过串行通用输入输出总线SGPIO连接。
一种可能的实施方式中，主逻辑芯片中存储有第一PCIe设备的设备标识，主逻辑芯片接收来自处理器的针对第一PCIe设备的第一控制信息之前，还包括：
主逻辑芯片接收来自从逻辑芯片的第一PCIe设备的第一触发信号和第一PCIe设备的在位信号，第一触发信号用于指示对所述第一PCIe设备执行热插拔；主逻辑芯片向处理器发送第一PCIe设备的设备标识，第一PCIe设备的第一触发信号和第一PCIe设备的在位信号，第一控制信号基于第一PCIe设备的设备标识、第一触发信号以及第一PCIe设备的在位信号生成。
一种可能的实施方式中，主逻辑芯片与第二PCIe设备连接，主逻辑芯片中存储有第二PCIe设备的设备标识，该方法还包括：主逻辑芯片接收来自所述处理器的针对所述第二PCIe设备的第二控制信号；主逻辑芯片根据所述第二控制信号对所述第二PCIe设备进行控制。
一种可能的实施方式中，主逻辑芯片中存储有第二PCIe设备的设备标识，主逻辑芯片接收来自处理器的针对第二PCIe设备的第二控制信号之前，还包括：主逻辑芯片接收来自第一从逻辑芯片的针对第二PCIe设备的第二触发信号，第二触发信息用于指示对第二PCIe设备执行热插拔；主逻辑芯片获取第二PCIe设备的在位信号；主逻辑芯片向处理器发送第二PCIe设备的设备标识、第二PCIe设备的在位信号和第二PCIe设备的第二触发信号，第二控制信号基于第二PCIe设备的设备标识、第二触发信号以及第二PCIe设备的在位信号生成，第二控制信号用于指示对第二PCIe设备执行热插拔。
第三方面，本申请实施例提供了一种电子设备，该电子设备可以包括逻辑芯片，该逻辑芯片中存储有计算机指令，当上述计算机指令在逻辑芯片上运行时，使得电子设备可以执行如第二方面中的任意一种实现方式所提供的基于PCIe设备的控制方法。
上述第二方面和第三方面提供的方案，用于实现或配合实现上述第一方面提供的计算机系统，因此可以与第一方面达到相同或相应的有益效果，此处不再进行赘述。
附图说明
以下对本申请实施例用到的附图进行介绍。
图1是本申请实施例提供的一种分立控制方法的系统示意图；
图2是本申请实施例提供的另一种分立控制系统的传输示意图；
图3是本申请实施例提供的一种计算机系统的示意图；
图4是本申请实施例提供的另一种计算机系统的示意图；
图5是本申请实施例提供的再一种计算机系统的示意图；
图6是本申请实施例提供的一种PCIe设备的热插拔控制方法的流程示意图；
图7是本申请实施例提供的另一种PCIe设备的热插拔控制方法的流程示意图；
图8是本申请实施例提供的再一种PCIe设备的热插拔控制方法的流程示意图。
具体实施方式
下面结合附图对本申请实施例中的技术方案进行清楚、完整的描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
本申请的说明书以及附图中的术语“第一”和“第二”等是用于区分不同的对象，或者用于区别对同一对象的不同处理，而不是用于描述对象的特定顺序。此外，本申请的描述中所提到的术语“包括”和“具有”以及它们的任何变形，意图在于覆盖不排他的包含。例如包含了一些列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括其他没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其他步骤或单元。需要说明的是，本申请实施例中，“示例性地”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性地”或者“例如”的任何实施例或设计方法不应被解释为比其他实施例或设计方案更优地或更具优势。确切而言，使用“示例性地”或者“例如”等词旨在以具体方式呈现相关概念。在本申请实施例中，“A和/或B”表示A和B，A或B两个含义。“A，和/或B，和/或C”表示A、B、C中的任一个，或者，表示A、B、C中的任两个，或者，表示A和B和C。下面将结合附图，对本申请中的技术方案进行描述。
首先，对本申请中所涉及的部分用语和相关技术进行解释说明，以便于本领域技术人员理解。
(1)高速串行计算机扩展总线标准
高速串行计算机扩展总线标准(peripheral component interconnect express，PCIe)，主要用于中央处理器(central processing unit，CPU)与外围器件的数据交互。其中，外围器件可以是基于PCIe总线接口的多类别PCIe设备，比如说多类别PCIe设备可以包括非易失忆内存主机控制器接口规范(Non-Volatile Memory express，NVMe)硬盘、网卡、显卡、采集卡、标卡、GPU，等具有不同功能的设备。
(2)热插拔
热插拔即主机带电拔插，允许用户在不关闭系统，在不切断主机电源的情况下能够取出或更换主机下挂的PCIe设备，而不影响主机服务器系统的运行，从而提高系统对故障的及时恢复能力、扩展性和灵活性等。
请参见图2，图2是本申请实施例提供的另一种分立控制系统的传输示意图。需要说明的是，图2是以单处理器为例对N个PCIe设备进行控制，也可以通过多处理器对N个PCIe设备进行控制，比如说热插拔控制，本申请实施例对此不作任何限制。其中，N为大于等于2的正整数。需要说明的是，N个PCIe设备可以是包含多种功能类型的设备，比如说具有存 储功能的NVMe硬盘，具有通信功能的网卡、具有显示功能的显卡、具有视频采集功能的采集卡等等。
从图2可以看出，N个逻辑芯片可以通过I2C链路分别连接到处理器上。也即，每个逻辑芯片与处理器之间可以通过I2C链路进行通信。每个逻辑芯片与每个PCIe设备进行连接，当需要对N个PCIe设备中的任意一个PCIe设备进行控制时，该PCIe设备所连接的逻辑芯片需要通过I2C接口与处理器进行数据交互，来对该PCIe设备进行控制，比如说热插拔控制。
综上所述，N个PCIe设备需要N个逻辑芯片，而处理器需要将I2C链路分别连接到N个逻辑芯片上，每个逻辑芯片再单独通过对应的I2C接口与处理器进行数据交互来控制PCIe设备的热插拔功能。而与处理器直接连接的逻辑芯片会消耗逻辑芯片大量的资源，所以可能会增加逻辑资源的消耗，不利于对PCIe设备的其他功能的持续开发。
本申请实施例为解决上述技术问题，提供了一种计算机系统、基于PCIe设备的控制方法及相关装置，可以通过一个主逻辑芯片与处理器进行数据交互，其他从逻辑芯片从主逻辑芯片获取处理后的数据来完成与上述从逻辑芯片连接的PCIe设备的控制。
请参见图3，图3是本申请实施例提供的一种计算机系统300的示意图。从图3可以看出，计算机系统300包括但不限于处理器301、主逻辑芯片302、第一从逻辑芯片303和第一PCIe设备304。其中，处理器301可以与主逻辑芯片302连接，主逻辑芯片302可以与第一从逻辑芯片303连接，第一从逻辑芯片303可以和第一PCIe设备304连接。进一步地，第一从逻辑芯片303可以通过主逻辑芯片302与处理器301通信。
需要说明的是，主逻辑芯片302还可以与其他从逻辑芯片连接，其他从逻辑芯片可以和其他PCIe设备连接。
进一步地，处理器301与主逻辑芯片302之间可以通过I2C总线连接，主逻辑芯片302与第一从逻辑芯片303通过非I2C总线连接。可以理解的是，主逻辑芯片302与其他逻辑芯片也可以通过非I2C总线连接，其中，非I2C总线可以包括以下一种或多种：串行通用输入输出总线(Serial general-purpose input/output，SGPIO)总线、通用异步收发传输器(Universal Asynchronous Receiver/Transmitter，UART)总线、LPC总线(Low pin count Bus)，等等。
其中，处理器301可以通过PCIe总线与至少一个PCIe设备连接，进而处理器301可以与至少一个PCIe设备中的第一PCIe设备304进行读写交互。本申请实施例对PCIe设备的数量和类型不不进行任何限制。举例来说，至少一个PCIe设备包括但不限于网卡、NVMe硬盘、显卡、采集卡和标卡。
请参见图4，图4是本申请实施例提供的另一种计算机系统400的示意图。从图4可以看出，计算机系统400可以包括主板401，副板402和至少一个PCIe设备。其中，主板401上安装有处理器301和至少一个从逻辑芯片，副板402上安装有主逻辑芯片302。主板401上的处理器301可以与副板402上的主逻辑芯片302连接，主逻辑芯片302可以与主板401上的至少一个从逻辑芯片中的第一从逻辑芯片303连接，第一从逻辑芯片303可以与至少一个PCIe设备中的第一PCIe设备304连接。
进一步地，处理器301与主逻辑芯片302之间可以通过I2C总线连接，主逻辑芯片302与第一从逻辑芯片303之间可以通过非I2C总线(比如说SGPIO总线)连接。可以理解的是，主逻辑芯片302与至少一个从逻辑芯片中的其他逻辑芯片也可以通过非I2C总线连接。其中，非I2C总线可以包括以下一种或多种：SGPIO总线，通用异步收发传输器(Universal Asynchronous Receiver/Transmitter，UART)总线，LPC总线(Low pin count Bus)，等等。其 中，处理器301可以通过PCIe总线与至少一个PCIe设备连接，进而处理器301可以与至少一个PCIe设备中的第一PCIe设备304进行读写交互。本申请实施例对PCIe设备的数量和类型不进行任何限制。举例来说，至少一个PCIe设备包括但不限于网卡、NVMe硬盘、显卡、采集卡和标卡。
可以理解的是，主板又叫主机板(main board)、系统板(system board)或母板(mother board)，是计算机最重要的部件之一。在主板上安装了组成计算机的主要电路系统，比如说基本输入输出系统(Basic Input Output System，BIOS)芯片等等。主板是主机、服务器等系统中的核心部件，上面布满各种槽位，支持通用串行总线(Universal Serial Bus，usb)、PCIE、通用异步收发传输器(Universal Asynchronous Receiver/Transmitter，uart)等协议接口，并把各种周边设备紧紧连接一起，完成资源调度、分配等任务。计算机主机中的各个部件都是通过主板来连接的，计算机在正常运行时对系统内存、存储设备和其他I/O设备的操控都需要通过主板来完成。
副板是支撑其他电路板、器件和器件之间的相互连接，并为所支撑的器件提供电源和数据信号的电路板和框架。其中，副板可以包括以下一种或多种：硬件背板，信号背板，转接板，扩展板，等等。
可以看出，副板相对于主板来说，需要完成的功能较少。也即，当主逻辑芯片放置在副板上时，主逻辑芯片可以更好地支撑主逻辑芯片与处理器301之间的数据交互，提高对PCIe设备的热插拔控制速度。
请参见图5，图5是本申请实施例提供的再一种计算机系统500的示意图。从图5可以看出，计算机系统500可以包括主板501，副板502和至少一个PCIe设备。其中，主板501上安装有处理器301和主逻辑芯片302，副板502上安装有至少一个从逻辑芯片。主板501上的处理器301可以与主板501上的主逻辑芯片302连接，主逻辑芯片302可以与副板502上的至少一个从逻辑芯片中的第一从逻辑芯片303连接，第一从逻辑芯片303可以与至少一个PCIe设备中的第一PCIe设备304连接。
进一步地，处理器301与主逻辑芯片302之间可以通过I2C总线连接，主逻辑芯片302与第一从逻辑芯片303之间可以通过非I2C总线(比如说SGPIO总线)连接。可以理解的是，主逻辑芯片302与至少一个从逻辑芯片中的其他逻辑芯片也可以通过非I2C总线连接。
其中，处理器301可以通过PCIe总线与至少一个PCIe设备连接，进而处理器301可以与至少一个PCIe设备中的第一PCIe设备304进行读写交互。本申请实施例对PCIe设备的数量和类型不不进行任何限制。举例来说，至少一个PCIe设备包括但不限于网卡、NVMe硬盘、显卡、采集卡和标卡。
图3、图4和图5中所示的处理器301可以向主逻辑芯片302发送针对第一PCIe设备的第一控制信号。
主逻辑芯片302可以接收来自处理器301的第一控制信号，并向第一从逻辑芯片302发送第一控制信号。
第一从逻辑芯片303接收来自主逻辑芯片302的第一控制信号后，根据第一控制信号对第一PCIe设备304进行控制，比如说对第一PCIe设备执行热插拔。进一步地，第一控制信号可以包含电源控制信号和指示信号，其中，电源控制信号用于对第一PCIe设备进行热插拔控制(比如说上电控制或者下电控制)，指示信号用于控制LED指示灯，上述LED指示灯用于表示是否完成对第一PCIe设备的上电控制或者下电控制。
可以理解的是，若第一控制信号包含第一上电信号和第一状态指示信号，则第一从逻辑 芯片303可以根据第一上电信号启动第一PCIe设备304的上电时序控制。等待第一PCIe设备304上电完成后，第一从逻辑芯片303可以根据第一状态指示信号指示LED灯亮(比如说常亮)。在对第一PCIe设备304上电之后，第一从逻辑芯片对第一PCIe设备进行解复位操作。
若第一控制信号包含第一下电信号和第二状态指示信号，则第一从逻辑芯片303可以根据第一下电信号启动第一PCIe设备304的下电时序控制。等待第一PCIe设备304下电完成后，第一从逻辑芯片303可以根据第二状态指示信号指示LED灯灭。在对第一PCIe设备304下电之前，第一从逻辑芯片对第一PCIe设备进行复位操作。
在一种可能的实现方式中，如图3所示的计算机系统300、如图4所示的计算机系统400和如图5所示的计算机系统500还可以包括第二PCIe设备305。
其中，图3、图4和图5所示的第二PCIe设备305可以与主逻辑芯片302连接。需要说明的是第二PCIe设备与第一PCIe设备不是一个类型的PCIe设备。比如说第一PCIe设备可以是网卡，第二PCIe设备可以是NVMe硬盘。
处理器301可以向主逻辑芯片302发送针对第二PCIe设备的第二控制信号。
主逻辑芯片302可以接收来自处理器301的第二控制信号，根据第二控制信号对第二PCIe设备进行控制，比如说热插拔。其中，若第二控制信号包含第二上电信号和第三状态指示信号，则主逻辑芯片302可以根据第二上电信号启动第二PCIe设备305的上电时序控制。等待第二PCIe设备305上电完成后，主逻辑芯片302可以根据第三状态指示信号指示LED灯亮(比如说常亮)。若第二控制信号包含第二下电信号和第四状态指示信号，则主逻辑芯片302可以根据第二下电信号启动第二PCIe设备305的下电时序控制。等待第二PCIe设备305下电完成后，主逻辑芯片302可以根据第四状态指示信号指示LED灯灭。
在一种可能的实现方式中，如图3所示的计算机系统300、如图4所示的计算机系统400和如图5所示的计算机系统500还可以包括第二从逻辑芯片307和第三PCIe设备308。
其中，图3、图4和图5所示的第二从逻辑芯片307可以与主逻辑芯片302连接，第三PCIe设备308可以和第二从逻辑芯片307连接。需要说明的是第三PCIe设备308与第一PCIe设备304、第二PCIe设备305可以不是一个类型的PCIe设备。比如说第一PCIe设备304可以是网卡，第二PCIe设备305可以是NVMe硬盘，第三PCIe设备308可以是采集卡。
处理器301可以向主逻辑芯片302发送针对第三PCIe设备308的第三控制信号。
主逻辑芯片302可以接收来自处理器301的第三控制信号，并向第二从逻辑芯片307发送第三控制信号。
第二从逻辑芯片307可以根据第三控制信号对第三PCIe设备308进行控制，比如说热插拔。其中，若第三控制信号包含第三上电信号和第五状态指示信号，则第二从逻辑芯片307可以根据第三上电信号启动第三PCIe设备308的上电时序控制。等待第三PCIe设备308上电完成后，第二从逻辑芯片307可以根据第五状态指示信号指示LED灯亮(比如说常亮)。若第二控制信号包含第三下电信号和第六状态指示信号，则第二从逻辑芯片307可以根据第三下电信号启动第三PCIe设备308的下电时序控制。等待第三PCIe设备308下电完成后，第二从逻辑芯片307可以根据第六状态指示信号指示LED灯灭。
在一种可能的实现方式中，如图3所示的计算机系统300和如图4所示的计算机系统400还可以包括基板管理器(baseboard management controller，BMC)芯片306。其中，BMC芯片306可以与第一从逻辑芯片303或者第二从逻辑芯片307连接。进一步地，第一从逻辑芯片303可以第二从逻辑芯片307连接。在计算机系统300和计算机系统400中，BMC芯片306可以向第一从逻辑芯片303发送针对第一PCIe设备304的第一触发信号，第一触发信号 用于指示对第一PCIe设备304执行控制，比如说热插拔控制。BMC芯片306还可以向第二从逻辑芯片307发送针对第三PCIe设备308的第三触发信号，第三触发信号用于指示对第三PCIe设备308执行控制，比如说热插拔控制。BMC芯片306还可以向第一从逻辑芯片303或者第二从逻辑芯片307发送针对第二PCIe设备的第二触发信号，第二触发信号用于指示对第二PCIe设备304执行控制，比如说热插拔。
在一种可能的实现方式，如图5所示的计算机系统500还可以包括BMC芯片306。其中，BMC芯片306可以和主逻辑芯片302连接。BMC芯片306可以向主逻辑芯片302发送针对第一PCIe设备304的第一触发信号，第一触发信号用于指示对第一PCIe设备304进行控制，比如说对第一PCIe设备304执行热插拔。BMC芯片306还可以向主逻辑芯片302发送针对第二PCIe设备305的第二触发信号，第二触发信号用于指示对第二PCIe设备305进行控制，比如说热插拔控制。BMC芯片306还可以向主逻辑芯片302发送针对第三PCIe设备308的第三触发信号，第三触发信号用于指示对第三PCIe设备308进行控制，比如说对第三PCIe设备308执行热插拔。
需要说明的是，第一从逻辑芯片303和第二从逻辑芯片307可以不在一个单板(比如说主板401)上。比如说第一从逻辑芯片在主板401上，第二从逻辑芯片在副板402上；或者第一从逻辑芯片303、第二从逻辑芯片307和主逻辑芯片302在不同的单板上。
需要说明的是，图3、图4和图5所示的处理器301可以是中央处理器(central processing unit，CPU)、平台控制器(platform controller hub、PCH)或者专用处理器等具有计算处理能力的器件。进一步地，处理器301可以是单核处理器或多核处理器。
请参见图6，图6是本申请实施例提供的一种基于PCIe设备的控制方法的流程示意图，该方法可应用在图3或图4所示的计算机系统，该方法包括但不限于如下步骤：
需要说明的是，计算机系统还可以包括基本输入输出系统(Basic Input Output System，BIOS)芯片，BIOS芯片是一块方块状的存储器，里面存储有基本输入输出系统程序，该程序在开机后首先运行，对系统的各个部件进行检测和初始化。处理器301还可以包括设备驱动和热插拔驱动，通过设备驱动(比如说PCIe设备的驱动)可以对PCIe设备进行读/写操作，通过热插拔驱动可以为PCIe设备分配内存资源。
步骤S601，第一从逻辑芯片接收来自BMC芯片的针对第一PCIe设备的第一触发信号。
具体地，计算机系统还可以包括基板管理器(baseboard management controller，BMC)，BMC芯片位于主板上，与处理器301连接。BMC可以为每一个PCIe设备设置对应的虚拟按钮BUTTON，当用户要控制第一PCIe设备时，比如说将第一PCIe设备热插入PCIe插槽中，或者将第一PCIe设备从PCIe插槽热拔出。用户通过BMC对第一PCIe设备对应的虚拟按钮BUTTON进行操作后，BMC可以向第一从逻辑芯片发送针对第一PCIe设备的第一触发信号，因此第一从逻辑芯片可以接收到来自BMC的针对第一PCIe设备到第一触发信号。
步骤S602，第一从逻辑芯片获取第一PCIe设备的在位信号。
具体地，对于热插拔来说，PCIe设备有两个用于热插拔机制的热插拔信号PRSNT1#和PRSNT2#对应的引脚。PCIe设备上的这两个信号引脚之间是短路的，PCIe插槽的PRSNT1#被固定连接到地，PRSNT2#则被上拉，且PCIe设备上的这两个信号的金手指长度要比其他的信号的金手指长度要短一点。当PCIe设备未被完全插入插槽时，插槽的PRSNT2#信号由于上拉的作用，将一直处于高电平状态，当PCIe设备被完全插入插槽后，插槽上的PRSNT2#信号则会被PCIE设备的短路线连接到地，从而使其变为低电平。第一PCIe设备与第一从逻 辑芯片连接，第一从逻辑芯片可以根据第一PCIe设备的PRSNT1#和PRSNT2#得到第一PCIe设备的在位信号。
可以理解的是，当PCIe设备未被完全插入插槽时，插槽的PRSNT2#信号由于上拉的作用，将一直处于高电平状态，当PCIe设备被完全插入插槽后，插槽上的PRSNT2#信号则会被PCIe设备的短路线连接到地，从而使其变为低电平。换句话说，从插槽的角度看，当PRSNT2#为高电平时，则认为PCIe设备未能正确插入或者无PCIe设备，当PRSNT2#为低电平时，表明PCIe设备被正确地插入插槽中。而不同的PCIe设备，可能同一电压信号对应不同的在位信号。比如说，对于PCIe设备1来说，低电平可能对应的是在位信号是“0”，而对应PCIe设备2来说，低电平可能对应的是不在位信号是“0”。因此，不同的PCIe设备对应不同的处理规则，第一从逻辑芯片可以根据第一PCIe设备的处理规则确定PRSNT1#和PRSNT2#对应的第一PCIe设备的在位信号。
步骤S603，第一从逻辑芯片向主逻辑芯片发送第一PCIe设备的第一触发信号和第一PCIe设备的在位信号。
具体地，第一从逻辑芯片可以持续向主逻辑芯片发送针对第一PCIe设备的第一触发信号和第一在位信号。
步骤S604，主逻辑芯片向处理器发送第一PCIe设备的设备标识，第一PCIe设备的第一触发信号和第一PCIe设备的在位信号。
具体地，主逻辑芯片中存储有第一PCIe设备的设备标识，当接收到来自第一从逻辑芯片的第一PCIe设备的第一触发信号和第一PCIe设备的在位信号后，主逻辑芯片可以查询到存储在主逻辑芯片中的第一PCIe设备的设备标识，然后将第一PCIe设备的设备标识，第一PCIe设备的第一触发信号和第一PCIe设备的在位信号进行打包处理，将打包后的信号向处理器发送。
在一种可能的实现方式中，为了避免误触发热插拔事件，主逻辑芯片需要对接收到的第一触发信号进行判断，在第一触发信号的电平在预设时间段内保持不变的情况下，说明存在第一PCIe设备的热插拔事件；在第一触发信号的电平在预设时间段内发生变化时，说明可能是对BMC的虚拟按钮进行误操作。因此，主逻辑芯片根据第一触发信号在预设时间段内的电平变化判断存在第一PCIe设备的热插拔事件情况下，执行步骤S604；主逻辑芯片根据第一触发信号在预设时间段内的电平变化判断不存在第一PCIe设备的热插拔事件情况下，执行步骤S603。
步骤S605，处理器接收来自主逻辑芯片的第一PCIe设备的设备标识，第一PCIe设备的第一触发信号和第一PCIe设备的在位信号。
具体地，处理器中存储有第一PCIe设备的设备标识对应的槽位号，处理器可以根据第一PCIe设备的设备标识查询到第一PCIe设备的槽位号。处理器可以根据热插拔控制器检测第一PCIe设备的第一触发信号和第一PCIe设备的在位信号的变化等事件，来控制器热插拔驱动移除或添加第一PCIe设备，并根据第一PCIe设备的槽位号读写对应的PCIe插槽的寄存器状态来生成针对第一PCIe设备的第一控制信号。
步骤S606，处理器向主逻辑芯片发送第一控制信号。
具体地，处理器可以通过I2C总线向主逻辑芯片发送针对第一PCIe设备的第一控制信号。
步骤S607，主逻辑芯片向第一从逻辑芯片发送第一控制信号。
具体地，主逻辑芯片可以通过SGPIO总线向第一从逻辑芯片发送针对第一PCIe设备的第一控制信号。
步骤S608，第一从逻辑芯片根据第一控制信号对第一PCIe设备进行控制。
具体地，第一从逻辑芯片可以根据第一控制信号对第一PCIe设备执行热插拔。进一步地，当第一从逻辑芯片接收到的第一控制信号包含第一上电信号和第一状态指示信号，则第一从逻辑芯片可以根据第一上电信号启动第一PCIe设备的上电时序控制。等待第一PCIe设备上电完成后，第一从逻辑芯片可以根据第一状态指示信号指示LED灯亮(比如说常亮)。在对第一PCIe设备上电完成之后，第一从逻辑芯片对第一PCIe设备进行解复位操作。
当第一从逻辑芯片接收到的第一控制信号为第一下电信号和第二状态指示信号时，第一从逻辑芯片对第一PCIe设备进行复位操作之后，第一从逻辑芯片可以根据第一下电信号启动第一PCIe设备的下电时序控制。等待第一PCIe设备下电完成后，第一从逻辑芯片可以根据第二状态指示信号指示LED灯灭。
请参见图7，图7是本申请实施例提供的另一种基于PCIe设备的制方法的流程示意图，该方法可应用于图3或图4所示的计算机系统，该方法包括但不限于如下步骤：
步骤S701，第一从逻辑芯片接收来自BMC芯片的针对第二PCIe设备的第二触发信号。
具体地，BMC可以为每一个PCIe设备设置对应的虚拟按钮BUTTON，当用户要控制第二PCIe设备时，比如说将第二PCIe设备热插入PCIe插槽中，或者将第二PCIe设备从PCIe插槽热拔出。用户通过BMC对第二PCIe设备对应的虚拟按钮BUTTON进行操作后，BMC可以向第一从逻辑芯片发送针对第二PCIe设备的第二触发信号，因此第一从逻辑芯片可以接收到来自BMC的针对第二PCIe设备到第二触发信号。
步骤S702，第一从逻辑芯片向主逻辑芯片发送针对第二PCIe设备的第二触发信号。
具体地，第一从逻辑芯片可以通过SGPIO向主逻辑芯片发送针对第二PCIe设备的第二触发信号。
步骤S703，主逻辑芯片获取第二PCIe设备的在位信号。
具体地，第二PCIe设备与主逻辑芯片连接，主逻辑芯片可以根据第二PCIe设备的PRSNT1#和PRSNT2#得到第二PCIe设备的在位信号。
步骤S704，主逻辑芯片向处理器发送第二PCIe设备的设备标识，第二PCIe设备的在位信号和第二PCIe设备的第二触发信号。
具体地，主逻辑芯片中存储有第二PCIe设备的设备标识，当接收到来自第一从逻辑芯片的第二PCIe设备的第二触发信号后，主逻辑芯片可以读取到存储在主逻辑芯片中的第一PCIe设备的设备标识，然后将第一PCIe设备的设备标识，第一PCIe设备的第一触发信号和第一PCIe设备的在位信号进行打包处理，将打包后的信号向处理器发送。
在一种可能的实现方式中，为了避免误触发热插拔事件，主逻辑芯片需要对接收到的第二触发信号进行判断，在第二触发信号的电平在预设时间段内保持不变的情况下，说明存在第二PCIe设备的热插拔事件；在第二触发信号的电平在预设时间段内发生变化时，说明可能是对BMC的虚拟按钮进行误操作。因此，主逻辑芯片根据第二触发信号在预设时间段内的电平变化判断存在第二PCIe设备的热插拔事件情况下，执行步骤S704；主逻辑芯片根据第二触发信号在预设时间段内的电平变化判断不存在第二PCIe设备的热插拔事件情况下，执行步骤S702。
步骤S705，处理器接收来自主逻辑芯片的第二PCIe设备的设备标识，第二PCIe设备的第二触发信号和第二PCIe设备的在位信号。
具体地，处理器中存储有第二PCIe设备的设备标识对应的槽位号，处理器可以根据第二 PCIe设备的设备标识查询到第二PCIe设备的槽位号。处理器可以根据热插拔控制器检测第二PCIe设备的第二触发信号和第二PCIe设备的在位信号的变化等事件，来控制器热插拔驱动移除或添加第二PCIe设备，并根据第二PCIe设备的槽位号读写对应的PCIe插槽的寄存器状态来生成针对第二PCIe设备的第二控制信号。
步骤S706，处理器向主逻辑芯片发送第二控制信号。
具体地，处理器可以通过I2C总线向主逻辑芯片发送针对第二PCIe设备的第二控制信号。
步骤S707，主逻辑芯片根据第二控制信号对第二PCIe设备进行控制。
具体地，主逻辑芯片可以根据第二控制信号对第二PCIe设备进行控制，比如说对第二PCIe设备执行热插拔。进一步地，当主逻辑芯片接收到的第二控制信号包含第二上电信号和第三状态指示信号，则主逻辑芯片可以根据第二上电信号启动第二PCIe设备的上电时序控制。等待第二PCIe设备上电完成后，主逻辑芯片可以根据第三状态指示信号指示LED灯亮(比如说常亮)。在对第二PCIe设备上电完成之后，主逻辑芯片对第一PCIe设备进行解复位操作。
当主逻辑芯片接收到的第一控制信号为第二下电信号和第四状态指示信号时，主逻辑芯片对第二PCIe设备进行复位操作后，主逻辑芯片可以根据第二下电信号启动第二PCIe设备的下电时序控制。等待第二PCIe设备下电完成后，主逻辑芯片可以根据第四状态指示信号指示LED灯灭。
请参见图8，图8是本申请实施例提供的另一种基于PCIe设备的控制方法的流程示意图，该方法可应用于图3或图4所示的计算机系统，该方法包括但不限于如下步骤：
步骤S801，第二从逻辑芯片接收来自BMC芯片的针对第三PCIe设备的第三触发信号。
具体地，计算机系统还可以包括基板管理器(baseboard management controller，BMC)，BMC芯片位于主板上，与处理器301连接。BMC可以为每一个PCIe设备设置对应的虚拟按钮BUTTON，当用户要控制第三PCIe设备时，比如说将第三PCIe设备热插入PCIe插槽中，或者将第三PCIe设备从PCIe插槽热拔出。用户通过BMC对第三PCIe设备对应的虚拟按钮BUTTON进行操作后，BMC可以向第二从逻辑芯片发送针对第三PCIe设备的第三触发信号，因此第二从逻辑芯片可以接收到来自BMC的针对第三PCIe设备到第三触发信号。
步骤S802，第二从逻辑芯片获取第三PCIe设备的在位信号。
具体地，对于热插拔来说，PCIe设备有两个用于热插拔机制的热插拔信号PRSNT1#和PRSNT2#对应的引脚。PCIe设备上的这两个信号引脚之间是短路的，PCIe插槽的PRSNT1#被固定连接到地，PRSNT2#则被上拉，且PCIe设备上的这两个信号的金手指长度要比其他的信号的金手指长度要短一点。当PCIe设备未被完全插入插槽时，插槽的PRSNT2#信号由于上拉的作用，将一直处于高电平状态，当PCIe设备被完全插入插槽后，插槽上的PRSNT2#信号则会被PCIE设备的短路线连接到地，从而使其变为低电平。第三PCIe设备与第二从逻辑芯片连接，第二从逻辑芯片可以根据第三PCIe设备的PRSNT1#和PRSNT2#得到第三PCIe设备的在位信号。
可以理解的是，当PCIe设备未被完全插入插槽时，插槽的PRSNT2#信号由于上拉的作用，将一直处于高电平状态，当PCIe设备被完全插入插槽后，插槽上的PRSNT2#信号则会被PCIe设备的短路线连接到地，从而使其变为低电平。换句话说，从插槽的角度看，当PRSNT2#为高电平时，则认为PCIe设备未能正确插入或者无PCIe设备，当PRSNT2#为低电平时，表明PCIe设备被正确地插入插槽中。而不同的PCIe设备，可能同一电压信号对应不同的在位信号。比如说，对于PCIe设备1来说，低电平可能对应的是在位信号是“0”，而对应PCIe设备2来说，低电平可能对应的是不在位信号是“0”。因此，不同的PCIe设备对应不 同的处理规则，第二从逻辑芯片可以根据第三PCIe设备的处理规则确定PRSNT1#和PRSNT2#对应的第三PCIe设备的在位信号。
步骤S803，第二从逻辑芯片向主逻辑芯片发送第三PCIe设备的第三触发信号和第三PCIe设备的在位信号。
具体地，第二从逻辑芯片可以持续向主逻辑芯片发送针对第三PCIe设备的第三触发信号和第三在位信号。
步骤S804，主逻辑芯片向处理器发送第三PCIe设备的设备标识，第三PCIe设备的第三触发信号和第三PCIe设备的在位信号。
具体地，主逻辑芯片中存储有第三PCIe设备的设备标识，当接收到来自第二从逻辑芯片的第三PCIe设备的第三触发信号和第三PCIe设备的在位信号后，主逻辑芯片可以查询到存储在主逻辑芯片中的第三PCIe设备的设备标识，然后将第三PCIe设备的设备标识，第三PCIe设备的第三触发信号和第三PCIe设备的在位信号进行打包处理，将打包后的信号向处理器发送。
在一种可能的实现方式中，为了避免误触发热插拔事件，主逻辑芯片需要对接收到的第三触发信号进行判断，在第三触发信号的电平在预设时间段内保持不变的情况下，说明存在第三PCIe设备的热插拔事件；在第三触发信号的电平在预设时间段内发生变化时，说明可能是对BMC的虚拟按钮进行误操作。因此，主逻辑芯片根据第三触发信号在预设时间段内的电平变化判断存在第三PCIe设备的热插拔事件情况下，执行步骤S804；主逻辑芯片根据第三触发信号在预设时间段内的电平变化判断不存在第三PCIe设备的热插拔事件情况下，执行步骤S803。
步骤S805，处理器接收来自主逻辑芯片的第三PCIe设备的设备标识，第三PCIe设备的第三触发信号和第三PCIe设备的在位信号。
具体地，处理器中存储有第三PCIe设备的设备标识对应的槽位号，处理器可以根据第三PCIe设备的设备标识查询到第三PCIe设备的槽位号。处理器可以根据热插拔控制器检测第三PCIe设备的第三触发信号和第三PCIe设备的在位信号的变化等事件，来控制器热插拔驱动移除或添加第三PCIe设备，并根据第三PCIe设备的槽位号读写对应的PCIe插槽的寄存器状态来生成针对第三PCIe设备的第三控制信号。
步骤S806，处理器向主逻辑芯片发送第三控制信号。
具体地，处理器可以通过I2C总线向主逻辑芯片发送针对第三PCIe设备的第三控制信号。
步骤S807，主逻辑芯片向第二从逻辑芯片发送第三控制信号。
具体地，主逻辑芯片可以通过非I2C总线向第二从逻辑芯片发送针对第三PCIe设备的第三控制信号。
步骤S808，第二从逻辑芯片根据第三控制信号对第三PCIe设备进行控制。
具体地，第二从逻辑芯片可以根据第三控制信号对第三PCIe设备进行热插拔控制。进一步地，当第二从逻辑芯片接收到的第三控制信号包含第三上电信号和第五状态指示信号，则第二从逻辑芯片可以根据第三上电信号启动第三PCIe设备的上电时序控制。等待第三PCIe设备上电完成后，第二从逻辑芯片可以根据第五状态指示信号指示LED灯亮(比如说常亮)。在对第三PCIe设备上电完成之后，第二从逻辑芯片对第三PCIe设备进行解复位操作。
当第二从逻辑芯片接收到的第三控制信号为第三下电信号和第六状态指示信号时，第二从逻辑芯片对第三PCIe设备进行复位操作之后，第二从逻辑芯片可以根据第三下电信号启动第三PCIe设备的下电时序控制。等待第三PCIe设备下电完成后，第二从逻辑芯片可以根据 第六状态指示信号指示LED灯灭。
需要说明的是，图8所示的步骤S801至步骤S808、图7所示的步骤S701至步骤S707和图6所示的步骤S601至步骤S608可以一起组合使用，应用于图3和图4所示的计算机系统。因此，图7所示的步骤S701可以替换为“第二从逻辑芯片接收来自BMC芯片的针对第二PCIe设备的第二触发信号。”步骤S702可以替换为“第二从逻辑芯片向主逻辑芯片发送针对第二PCIe设备的第二触发信号”。
可以理解的是，对于图5所示的计算机系统500，主板上安装有处理器和主逻辑芯片，副板上安装有第一从逻辑芯片或者第二从逻辑芯片。因为BMC安装在主板上，所以应用在图5所示的计算机系统上的方法相对于应用在图4所示的计算机系统上的方法而言，BMC可以直接向主逻辑芯片发送针对第一PCIe设备的第一触发信号或者针对第二PCIe设备的第二触发信号或者针对第三PCIe设备第三触发信号。
需要说明的是，图6所示的步骤S601至步骤S605可替换为如下步骤：
步骤S901，第一从逻辑芯片获取第一PCIe设备的在位信号。
步骤S902，第一从逻辑芯片向主逻辑芯片发送第一PCIe设备的在位信号。
步骤S903，主逻辑芯片向处理器发送第一PCIe设备的设备标识和第一PCIe设备的在位信号。
步骤S904，处理器接收来自系统应用层的针对第一PCIe设备的第一触发信号，以及来自主逻辑芯片的第一PCIe设备的设备标识和第一PCIe设备的在位信号。
具体地，第一触发信号携带有针对第一PCIe设备的控制指令，比如说热插指令或者热拔指令。
用户可以通过安装在系统应用层的应用来输入针对第一PCIe设备的第一触发信号，该第一触发信号包括用于对第一PCIe设备进行控制操作的控制指令，比如说用于对第一PCIe设备进行热插操作的热插指令或者用于对第一PCIe设备进行热拔操作的热拔指令。
处理器中存储有第一PCIe设备的设备标识对应的槽位号，处理器可以根据第一PCIe设备的设备标识查询到第一PCIe设备的槽位号。处理器可以根据热插拔控制器检测第一PCIe设备的第一触发信号和第一PCIe设备的在位信号的变化等事件，来控制器热插拔驱动移除或添加第一PCIe设备，并根据第一PCIe设备的槽位号读写对应的PCIe插槽的寄存器状态来生成针对第一PCIe设备的第一控制信号。
需要说明的是，图7所示的步骤S701至步骤S704可替换为如下步骤：
步骤S1001，主逻辑芯片获取第二PCIe设备的在位信号。
步骤S1002，主逻辑芯片向处理器发送第二PCIe设备的设备标识和第二PCIe设备的在位信号。
步骤S1003，处理器接收来自系统应用层的针对第二PCIe设备的操作指令，以及来自主逻辑芯片的二PCIe设备的设备标识和第二PCIe设备的在位信号。
具体地，其中，第一触发信号携带有针对第二PCIe设备的控制指令，比如说热插指令或者热拔指令。
用户可以通过安装在系统应用层的应用来输入针对第二PCIe设备的第二触发信号，该第二触发信号包括用于对第二PCIe设备进行控制操作的控制指令，比如说用于对第二PCIe设备进行热插操作的热插指令或者用于对第二PCIe设备进行热拔操作的热拔指令。
处理器中存储有第二PCIe设备的设备标识对应的槽位号，处理器可以根据第二PCIe设 备的设备标识查询到第二PCIe设备的槽位号。处理器可以根据热插拔控制器检测第二PCIe设备的第二触发信号和第二PCIe设备的在位信号的变化等事件，来控制器热插拔驱动移除或添加第二PCIe设备，并根据第二PCIe设备的槽位号读写对应的PCIe插槽的寄存器状态来生成针对第二PCIe设备的第二控制信号。
需要说明的是，图8所示的步骤S801至步骤S805可替换为如下步骤：
步骤S1101，第二从逻辑芯片获取第三PCIe设备的在位信号。
步骤S1102，第二从逻辑芯片向主逻辑芯片发送第三PCIe设备的在位信号。
步骤S1103，主逻辑芯片向处理器发送第三PCIe设备的设备标识和第三PCIe设备的在位信号。
步骤S1104，处理器接收来自系统应用层的针对第三PCIe设备的第三触发信号，以及来自主逻辑芯片的第三PCIe设备的设备标识和第三PCIe设备的在位信号。
具体地，第三触发信号携带有针对第三PCIe设备的控制指令，比如说热插指令或者热拔指令。
用户可以通过安装在系统应用层的应用来输入针对第三PCIe设备的第三触发信号，该第三触发信号包括用于对第三PCIe设备进行控制操作的控制指令，比如说用于对第三PCIe设备进行热插操作的热插指令或者用于对第三PCIe设备进行热拔操作的热拔指令。
处理器中存储有第三PCIe设备的设备标识对应的槽位号，处理器可以根据第三PCIe设备的设备标识查询到第三PCIe设备的槽位号。处理器可以根据热插拔控制器检测第三PCIe设备的第三触发信号和第三PCIe设备的在位信号的变化等事件，来控制器热插拔驱动移除或添加第三PCIe设备，并根据第三PCIe设备的槽位号读写对应的PCIe插槽的寄存器状态来生成针对第三PCIe设备的第三控制信号。
本申请实施例提供的一种电子设备，该电子设备可以包括逻辑芯片，该逻辑芯片可以是图3、图4或图5中的主逻辑芯片302。其中，主逻辑芯片302具体可以是复杂可编程逻辑器件(Complex programmable logic device，CPLD)，主逻辑芯片302中存储有计算机指令，当上述计算机指令在逻辑芯片上运行时，使得电子设备可以执行上述的基于PCIe设备的控制方法。例如图6、图7或图8任意一个实施例所描述的基于PCIe设备的控制方法流程。
以上所述仅为本发明的几个实施例，本领域的技术人员依据申请文件公开的可以对本发明进行各种改动或变型而不脱离本发明的精神和范围。例如本发明实施例的附图中的各个部件具体形状或结构是可以根据实际应用场景进行调整的。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。

Claims (13)

  1. 一种计算机系统，其特征在于，所述计算机系统包括处理器、主逻辑芯片、第一从逻辑芯片和第一PCIe设备，其中，所述处理器与所述主逻辑芯片通过集成电路间I2C总线连接，所述主逻辑芯片与所述第一从逻辑芯片连接，所述第一从逻辑芯片和所述第一PCIe设备连接，所述第一从逻辑芯片通过所述主逻辑芯片与所述处理器通信。
  2. 根据权利要求1所述的系统，其特征在于，
    所述处理器，用于向所述主逻辑芯片发送针对所述第一PCIe设备的第一控制信号；
    所述主逻辑芯片，用于接收所述第一控制信号，并向所述第一从逻辑芯片发送所述第一控制信号；
    所述第一从逻辑芯片，用于根据所述第一控制信号对所述第一PCIe设备进行控制。
  3. 根据权利要求2所述的系统，其特征在于，所述计算机系统还包括基板控制器BMC芯片，其中所述BMC芯片和所述第一从逻辑芯片连接；
    所述第一从逻辑芯片，还用于接收来自BMC芯片的针对所述第一PCIe设备的第一触发信号，所述第一触发信号用于指示对所述第一PCIe设备执行热插拔；
    所述第一从逻辑芯片，还用于获取所述第一PCIe设备的在位信号；
    所述第一从逻辑芯片，还用于向所述主逻辑芯片发送所述第一PCIe设备的第一触发信号和所述第一PCIe设备的在位信号。
  4. 根据权利要求3所述的系统，其特征在于，所述主逻辑芯片中存储有所述第一PCIe设备的设备标识，
    所述主逻辑芯片，还用于接收所述第一触发信号和所述第一PCIe设备的在位信号，并向所述处理器发送所述第一PCIe设备的设备标识、所述第一PCIe设备的第一触发信号和所述第一PCIe设备的在位信号；
    所述处理器，具体用于基于所述第一PCIe设备的设备标识、所述第一触发信号以及所述第一PCIe设备的在位信号向所述主逻辑芯片发送所述第一控制信号，所述第一控制信号用于指示对所述第一PCIe设备执行热插拔。
  5. 根据权利要求1至4任一项所述的系统，其特征在于，所述计算机系统还包括第二PCIe设备，所述第二PCIe设备与所述主逻辑芯片连接；
    所述第一从逻辑芯片，还用于接收来自BMC芯片的针对所述第二PCIe设备的第二触发信号，所述第二触发信息用于指示对所述第二PCIe设备执行热插拔；
    所述第一从逻辑芯片，用于向所述主逻辑芯片发送所述第二PCIe设备的第二触发信号。
  6. 根据权利要求5所述的系统，其特征在于，所述主逻辑芯片中存储有所述第二PCIe设备的设备标识，
    所述主逻辑芯片，还用于获取所述第二PCIe设备的在位信号；
    所述主逻辑芯片，还用于向所述处理器发送所述第二PCIe设备的设备标识、所述第二PCIe设备的在位信号和所述第二PCIe设备的第二触发信号；
    所述处理器，还用于基于所述第二PCIe设备的设备标识、所述第二PCIe设备的在位信号和所述第二PCIe设备的第二触发信号向所述主逻辑芯片发送第二控制信号；
    所述主逻辑芯片，还用于根据所述第二控制信号对所述第二PCIe设备进行控制。
  7. 根据权利要求1至6任一项所述的系统，其特征在于，
    所述计算机系统还包括第二从逻辑芯片和第三PCIe设备，所述第二从逻辑芯片和所述主逻辑芯片连接，所述第三PCIe设备和所述第二从逻辑芯片连接。
  8. 根据权利要求1至7任一项所述的系统，其特征在于，所述主逻辑芯片为复杂可编程逻辑器件CPLD芯片或现场可编程门阵列FPGA芯片。
  9. 一种基于PCIe设备的控制方法，其特征在于，所述方法应用于计算机系统，所述计算机系统包括处理器、主逻辑芯片、第一从逻辑芯片和第一PCIe设备，所述方法包括：
    所述主逻辑芯片接收来自所述处理器的针对所述第一PCIe设备的第一控制信号，其中，所述处理器与所述主逻辑芯片通过集成电路间I2C总线连接；
    所述主逻辑芯片向所述第一从逻辑芯片发送所述第一控制信号，所述第一控制信号用于指示所述第一从逻辑芯片对所述第一PCIe设备进行控制，其中，所述主逻辑芯片与所述第一从逻辑芯片连接，所述第一从逻辑芯片和所述第一PCIe设备连接。
  10. 根据权利要求9所述的方法，其特征在于，所述主逻辑芯片中存储有所述第一PCIe设备的设备标识，所述主逻辑芯片接收来自处理器的针对第一PCIe设备的第一控制信号之前，还包括：
    所述主逻辑芯片接收来自所述从逻辑芯片的所述第一PCIe设备的第一触发信号和所述第一PCIe设备的在位信号，所述第一触发信号用于指示对所述第一PCIe设备执行热插拔；
    所述主逻辑芯片向所述处理器发送所述第一PCIe设备的设备标识，所述第一PCIe设备的第一触发信号和所述第一PCIe设备的在位信号，其中，所述第一控制信号基于所述第一PCIe设备的设备标识、所述第一触发信号以及所述第一PCIe设备的在位信号生成，所述第一控制信号用于指示对所述第一PCIe设备执行热插拔。
  11. 根据权利要求9或10所述的方法，其特征在于，所述主逻辑芯片与第二PCIe设备连接，所述方法还包括：
    所述主逻辑芯片接收来自所述处理器的针对所述第二PCIe设备的第二控制信号；
    所述主逻辑芯片根据所述第二控制信号对所述第二PCIe设备进行控制。
  12. 根据权利要求11所述的方法，其特征在于，所述主逻辑芯片中存储有所述第二PCIe设备的设备标识，所述主逻辑芯片接收来自所述处理器的针对所述第二PCIe设备的第二控制信号之前，还包括：
    所述主逻辑芯片接收来自所述第一从逻辑芯片的针对所述第二PCIe设备的第二触发信号，所述第二触发信息用于指示对所述第二PCIe设备执行热插拔；
    所述主逻辑芯片获取所述第二PCIe设备的在位信号；
    所述主逻辑芯片向所述处理器发送所述第二PCIe设备的设备标识，所述第二PCIe设备 的在位信号和所述第二PCIe设备的第二触发信号，其中，所述第二控制信号基于所述第二PCIe设备的设备标识、所述第二触发信号以及所述第二PCIe设备的在位信号生成，所述第二控制信号用于指示对所述第二PCIe设备执行热插拔。
  13. 一种电子设备，其特征在于，所述电子设备包括逻辑芯片，所述逻辑芯片中存储有计算机指令，当所述计算机指令在所述逻辑芯片上运行时，使得所述电子设备执行如权利要求9至12任一项所述的方法。
PCT/CN2022/110656 2021-08-12 2022-08-05 计算机系统、基于PCIe设备的控制方法及相关设备 WO2023016379A1 (zh)

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