WO2023010275A1 - 图像数据传输装置、方法、电子设备、介质和显示系统 - Google Patents

图像数据传输装置、方法、电子设备、介质和显示系统 Download PDF

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Publication number
WO2023010275A1
WO2023010275A1 PCT/CN2021/110281 CN2021110281W WO2023010275A1 WO 2023010275 A1 WO2023010275 A1 WO 2023010275A1 CN 2021110281 W CN2021110281 W CN 2021110281W WO 2023010275 A1 WO2023010275 A1 WO 2023010275A1
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WIPO (PCT)
Prior art keywords
frame
image data
signal
frame synchronization
synchronization signal
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PCT/CN2021/110281
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English (en)
French (fr)
Inventor
马希通
李太亮
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/908,000 priority Critical patent/US20240212562A1/en
Priority to PCT/CN2021/110281 priority patent/WO2023010275A1/zh
Priority to CN202180002076.6A priority patent/CN115943624A/zh
Publication of WO2023010275A1 publication Critical patent/WO2023010275A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/128—Frame memory using a Synchronous Dynamic RAM [SDRAM]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present disclosure relates to the technical field of video images, and in particular to an image data transmission device, an image data transmission method, electronic equipment, a computer-readable medium, and a display system.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides an image data transmission device, an image data transmission method, electronic equipment, a computer-readable medium, and a display system.
  • an image data transmission device which includes:
  • the receiving sub-circuit is used to receive the image data sent by the main board
  • write control module for responding to the receiving sub-circuit being in the locked state, according to the first frame synchronizing signal, the image data received by the receiving sub-circuit in each clock cycle of the first frame synchronizing signal Write one frame of the memory respectively, wherein the first frame synchronization signal is an associated clock signal; and, in response to the receiving sub-circuit being in an unlocked state, stop writing the image data into the memory;
  • a readout control module configured to read out a frame from the memory in each clock cycle of the second frame synchronization signal according to the second frame synchronization signal in response to the receiving subcircuit being in the locked state , wherein, for the same frame, there is a first time interval between writing and reading, the first time interval is greater than or equal to the clock cycle length of the first frame synchronization signal, and the second frame synchronization signal is local clock signal;
  • the sending module is used to send the frame read by the readout control module to the display module.
  • the device further includes: a selection module
  • the readout control module is specifically configured to read out a frame from the memory in each clock cycle of the second frame synchronization signal and send it to the selection module;
  • the selection module is configured to send each frame read by the readout control module to the sending module in response to the receiving subcircuit being in the locked state; and, in response to the receiving subcircuit being in the Unlocked state, sending the preset prompt frame to the sending module;
  • the sending module is configured to send the frame selected by the selection module to the display module.
  • the device also includes:
  • a phase-locked loop module configured to analyze and recover the first frame synchronization signal; and adjust the receiving sub-circuit to the locked state or the unlocked state.
  • the phase-locked loop module is further configured to set the clock recovery lock signal sent to the main board to a low level when the receiving sub-circuit is adjusted to the locked state; and, When the receiving sub-circuit is adjusted to the unlocked state, the clock recovery locking signal sent to the main board is set to a high level.
  • the readout control module is specifically configured to respond to the receiving subcircuit being adjusted to the locking state, after the first target falling edge of the first frame synchronization signal, at the A frame is read from the memory in each clock cycle of the second frame synchronization signal, wherein the first target falling edge is a second falling edge after the falling edge of the clock recovery locking signal.
  • the selection module is specifically configured to send the prompt frame to the sending module after a second time interval has elapsed in response to the receiving subcircuit being adjusted to the unlocked state, wherein, the second time interval is less than or equal to the clock cycle length of the second frame synchronization signal.
  • the selection module is specifically configured to, in response to the receiving subcircuit being adjusted to the unlocked state, after the second target falling edge of the second frame synchronization signal, set the prompt The frame is sent to the sending module, wherein the second target falling edge is the first falling edge after the rising edge of the clock recovery locking signal.
  • the phase-locked loop module when handshaking with the main board according to the VBO protocol, is specifically configured to adjust the receiving sub-circuit to the locked state after clock data recovery is completed.
  • the phase-locked loop module is specifically configured to adjust the receiving sub-circuit from the locked state to the Unlocked state.
  • the embodiment of the present disclosure also provides an image data transmission method, which includes:
  • the receiving sub-circuit In response to the receiving sub-circuit being in a locked state, the receiving sub-circuit receives the image data sent by the main board, and according to the first frame synchronizing signal, will receive from the main board within each clock cycle of the first frame synchronizing signal The image data are respectively written into one frame of the memory, and the first frame synchronization signal is an accompanying clock signal;
  • the second frame synchronization signal In response to the receiving subcircuit being in the locked state, according to the second frame synchronization signal, reading a frame from the memory in each clock cycle of the second frame synchronization signal, wherein, for the same frame, There is a first time interval between writing and reading, the first time interval is greater than or equal to the clock cycle length of the first frame synchronization signal, and the second frame synchronization signal is a local clock signal;
  • reading a frame from the memory and sending it to the display module within each clock cycle of the second frame synchronization signal includes:
  • a frame is read from the memory every clock cycle of the second frame synchronization signal.
  • the receiving sub-circuit in response to the increase or decrease of the clock frequency of the associated clock signal of the main board, the receiving sub-circuit is adjusted from the locked state to the unlocked state, and the The clock recovery lock signal is asserted high.
  • the sending a preset prompt frame to the display module in response to the receiving sub-circuit being in the unlocked state includes:
  • the prompt frame is sent to the display module, wherein the second time interval is less than or equal to the The clock period length of the second frame sync signal.
  • the sending the prompt frame to the display module after the second time interval has elapsed includes:
  • the prompt frame is sent to the display module.
  • an embodiment of the present disclosure also provides an electronic device, which includes:
  • processors one or more processors
  • memory for storing one or more programs
  • the one or more processors When the one or more programs are executed by the one or more processors, the one or more processors implement the image data transmission method as described in any one of the above embodiments.
  • the processor includes a field programmable gate array.
  • an embodiment of the present disclosure further provides a computer-readable medium, on which a computer program is stored, wherein, when the computer program is executed by a processor, the image data described in any one of the above-mentioned embodiments is realized.
  • the steps in the transfer method are described in any one of the above-mentioned embodiments.
  • the embodiment of the present disclosure further provides a display system, which includes:
  • FIG. 1 is a schematic structural diagram of an image data transmission device provided by an embodiment of the present disclosure
  • FIG. 2 is a flowchart of an image data transmission method provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic flowchart of another image data transmission method provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic flowchart of another image data transmission method provided by an embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a specific implementation method of step S2 in an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of multiple signals in an embodiment of the present disclosure.
  • FIG. 7 is a flow chart of a specific implementation method of step S5 in the embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a specific implementation method of step S501 in the embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.
  • Fig. 10 is a schematic structural diagram of a computer-readable medium provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of an image data transmission device provided by an embodiment of the present disclosure. As shown in FIG. 1 , the image data transmission device includes: a receiving sub-circuit, a writing control module, a reading control module and a sending module.
  • the receiving sub-circuit is used for receiving image data sent by the main board.
  • the receiving sub-circuit maintains the image data path (lane) with the main board in the locked state, and loses lock to the clock in the unlocked state, and cannot receive image data based on the original clock;
  • the identification of the receiving sub-circuit is mostly RX;
  • the motherboard can be a System on Chip (SoC for short), also known as a system on a chip, which is used to process video image signals in various formats, convert them into signal formats agreed with the image data transmission device, or convert them into The signal format corresponding to the receiving subcircuit.
  • SoC System on Chip
  • the writing control module is used to respond to the receiving sub-circuit being in the locked state, according to the first frame synchronizing signal of the main board, write the image data received by the receiving sub-circuit in each clock cycle of the first frame synchronizing signal into the memory respectively One frame, wherein the first frame synchronization signal is an associated clock signal; and, in response to the receiving sub-circuit being in an unlocked state, stop writing image data into the memory.
  • the channel-associated clock is a clock synchronized with the input data signal, and the receiver of the data signal performs corresponding operations on the received data according to the channel-associated clock.
  • the synchronous clock signal corresponding to the data needs to change with the changes of various parameters of the image data (such as frame rate, etc.).
  • Each frame is stored in the corresponding frame area according to the frame address allocated when writing; in some embodiments, the memory is Double Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate Synchronous Dynamic Random Access Memory, referred to as DDR SDRAM, also known as DDR).
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • the readout control module is used to respond to the receiving sub-circuit being in a locked state, according to the second frame synchronization signal, to read a frame from the memory in each clock cycle of the second frame synchronization signal, wherein, for the same frame, it writes There is a first time interval between the input and the readout, the first time interval is greater than or equal to the clock cycle length of the first frame synchronization signal, and the second frame synchronization signal is a local clock signal.
  • the second frame synchronization signal corresponds to the local clock of the image data transmission device, which can be generated by a corresponding module inside the image data transmission device, such as a local crystal oscillator or a local clock module as shown in the figure, which is only changed according to the local configuration and does not follow the input
  • the frequency of the signal varies, and, in some embodiments, the local clock is fixed and stable in order to ensure a stable connection to the output object.
  • the time for writing one or more frames is reserved for the write control module, and after waiting at least one clock cycle of the first frame synchronization signal, start to read a frame from the memory. frame; in some embodiments, the clock period length of the second frame synchronization signal is equal to that of the first frame synchronization signal; or, in some embodiments, the clock period length of the second frame synchronization signal is equal to that of the first frame synchronization signal and There is a preset phase difference between the two.
  • the sending module is used to send the frame read by the readout control module to the display module.
  • the display module includes a Tcon board and a display
  • the sending module is used to send the frames read by the readout control module to the Tcon board.
  • the device further includes: a selection module.
  • the read control module is specifically configured to read a frame from the memory in each clock cycle of the second frame synchronization signal and send it to the selection module.
  • the read control module is further configured to stop reading data from the memory in response to the receiving subcircuit being in an unlocked state.
  • the selection module is used to send each frame read by the readout control module to the sending module in response to the receiving subcircuit being in a locking state; and, in response to the receiving subcircuit being in an unlocked state, sending a preset prompt frame to the sending module module.
  • the selection module sends a prompt frame to the sending module;
  • the prompt frame is used to prompt signal loss, for example, by means of screen adjustment (On Screen Display, referred to as OSD) displays specific fonts or graphics to prompt that there is currently no signal, etc.; in some embodiments, the prompt frame is also called a background frame (Backgroud).
  • the image data transmission device further includes a prompt frame control module, the prompt frame control module is used to store the prompt frame, and transmit the prompt frame according to the second frame synchronization signal in each clock cycle sent to the selection module, so that the selection module can send the preset prompt frame to the sending module when the receiving sub-circuit is in an unlocked state.
  • the prompt frame control module is used to store the prompt frame, and transmit the prompt frame according to the second frame synchronization signal in each clock cycle sent to the selection module, so that the selection module can send the preset prompt frame to the sending module when the receiving sub-circuit is in an unlocked state.
  • the sending module sends the frame selected by the selection module, the frame read by the readout control module, or the prompt frame to the display module;
  • the identification of the sending module is mostly TX; in some embodiments, the sending module sends the frame to be sent
  • the image frame is sent to the Tcon board in the display module.
  • the Tcon board is also called logic board and control board. After receiving the image frame, the Tcon board group sends it to the display terminal in the display module for display.
  • the receiving side corresponding to the write control module and the receiving sub-circuit belongs to the first clock domain based on the first frame synchronization signal
  • the sending side corresponding to the read control module, the selection module, and the sending module belongs to the clock domain based on the second frame synchronization signal.
  • the second clock domain, the prompt frame control module in the above embodiment also belongs to the second clock domain.
  • the image data transmission device further includes: a read-write arbitration module and a memory control module, the former is used to control and coordinate the read-write operations, and the latter is used to maintain and manage the memory Addresses, etc., the storage side corresponding to the read-write arbitration module and the memory control module belong to the third clock domain based on the memory clock.
  • the receiving side and the sending side of the image data transmission device belong to the same clock domain.
  • the clock domain of the first frame synchronization signal when the frame rate of the video signal of the signal source changes, the image signal sent by the main board The corresponding associated clock will also change adaptively. Since the interface of the device (such as a high-speed serial interface) does not support the dynamic change of the clock, the synchronization signal of the first frame cannot be adjusted in time, and the overall clock of the device will lose lock.
  • the display terminal When the signal connection between the main board and the display terminal is disconnected, the display terminal will immediately enter the self-test state due to signal loss. Among them, the display terminal will enter the self-test state when the data cannot be locked. In the self-test state, it will display the internal screen, the internal screen Usually red, green, blue and other colors cycle through the picture.
  • the receiving side uses the main board (signal source) and the associated clock corresponding to the image signal as the reference clock for image data transmission
  • the sending side uses the local clock of the image data transmission device as the image
  • the reference clock for data transmission when the clock loses lock on the receiving side, the sending side continues to work based on the second frame synchronization signal, continues to read and send the pre-stored valid data or other valid data, and is not connected to the signal of the display module and the display terminal.
  • the image data transmission device further includes: a phase-locked loop module.
  • the phase-locked loop module is used to analyze and restore the first frame synchronization signal; and adjust the receiving sub-circuit to a locked state or an unlocked state.
  • the phase-locked loop module is specifically configured to send the receiving sub The circuit is adjusted to a locked state. And, in some embodiments, the phase-locked loop module is specifically used to adjust the receiving sub-circuit from the locked state to the unlocked state in response to the increase or decrease of the clock frequency of the associated clock signal of the main board; wherein, the main board and the receiving The sub-circuits are connected through corresponding multiple pairs of signal lines.
  • the frame rate of the video signal of the signal source changes, the frequency of the associated clock corresponding to the image signal sent by the motherboard will also change adaptively. After the reception is affected, the receiving sub-circuit is adjusted from the locked state to the unlocked state, and the connection between the main board and the device is disconnected.
  • the phase-locked loop module is also used to set the clock recovery lock signal (Lockn) sent to the mainboard to a low level when the receiving sub-circuit is adjusted to a locked state; and, when adjusting the receiving sub-circuit When in the unlocked state, put the clock recovery lock signal sent to the main board at a high level.
  • Lockn clock recovery lock signal
  • the clock recovery locking signal can be sent to the main board by the receiving sub-circuit.
  • the main board does not directly transmit the associated clock signal, and the image data transmission device needs to analyze the clock data from the data transmitted by the main board during the clock data recovery phase of the handshake to restore
  • the channel-associated clock is output to obtain the first frame synchronization signal, that is, the first frame synchronization signal is the channel-associated clock signal of the main board recovered on the side of the device.
  • the device shakes hands with the motherboard according to the VBO protocol, it first establishes a connection, and when the VBO connection with the motherboard is stable, it pulls the Hot Plug Detect Signal (HTPDN for short) sent to the motherboard from a high level to Low to low level; the main board responds to this situation and sends a clock data recovery test sequence to the receiving sub-circuit, entering the clock data recovery stage, so that the device recovers the data clock; after the device clock data recovery is completed, the phase-locked loop will receive the sub-circuit Adjust to the locked state, and pull down the clock recovery lock signal sent to the main board from high level to low level; the main board responds to this situation by sending an alignment test sequence to the receiving sub-circuit to enter alignment (Alignment training, ALN training for short) stage, to correspond to the effective pixels and bytes in the signal sent by the main board subsequently; after the alignment is completed, the main board starts to send image data.
  • HPDN Hot Plug Detect Signal
  • the readout control module is specifically configured to respond to the receiving subcircuit being adjusted to the locked state, after the first target falling edge of the first frame synchronization signal, within each clock cycle of the second frame synchronization signal A frame is read from the memory, wherein the first target falling edge is the second falling edge after the falling edge of the clock recovery lock signal.
  • the description of the receiving subcircuit being in the locked state or the unlocked state in various embodiments of the present disclosure is intended to emphasize the continuation of the state within a period of time, and the adjustment of the receiving subcircuit to the locked state or the unlocked state means In emphasizing the state change at a certain moment.
  • the first target falling edge of the first frame synchronization signal is detected by a control plane or a corresponding module of the image transmission device.
  • it first generates the first frame synchronization enable signal according to the first frame synchronization signal, wherein the high level area of the first frame synchronization enable signal includes on the time axis The high-level region of the first frame synchronization signal; generate the first frame synchronization selection signal according to the AND operation result between the first frame synchronization signal and the first frame synchronization enable signal; delay the first frame synchronization selection signal for a certain time interval , generate the first frame synchronization selection delay signal; determine the pulse width according to the falling edge of the first frame synchronization selection signal and the falling edge of the first frame synchronization selection delay signal, and generate according to the falling edge and pulse width of the first frame synchronization selection signal
  • the first frame synchronization pulse signal wherein the rising edge of the first frame synchronization pulse signal and the falling edge of the first
  • the selection module is specifically configured to send a prompt frame to the sending module after the second time interval has elapsed in response to the receiving subcircuit being adjusted to an unlocked state, wherein the second time interval is less than or equal to the second Clock period length of the frame sync signal.
  • the readout control module in order to prevent readout conflicts, at most one clock cycle of the second frame synchronization signal is reserved, and after ensuring that the readout control module can completely read out the current frame and output it by the selection module, the prompt frame is sent to the sending module.
  • the selection module is specifically configured to respond to the receiving subcircuit being adjusted to an unlocked state, and send the prompt frame to the sending module after the second target falling edge of the second frame synchronization signal, wherein the second The target falling edge is the first falling edge after the rising edge of the clock recovery lock signal.
  • the falling edge of the second target corresponds to the end moment of the second time interval.
  • the second target falling edge of the second frame synchronization signal is detected by a control plane or a corresponding module of the image transmission device.
  • it first generates the second frame synchronization enable signal according to the second frame synchronization signal, wherein the second frame synchronization enable
  • the high-level area of the signal includes the high-level area of the second frame synchronization signal on the time axis;
  • the second frame synchronization selection signal is generated according to the AND operation result between the second frame synchronization signal and the second frame synchronization enable signal;
  • the second frame synchronization selection signal is delayed by one clock cycle to generate a second frame synchronization selection delay signal;
  • the pulse width is determined according to the falling edge of the second frame synchronization selection signal and the falling edge of the second frame synchronization selection delay signal, and according to the second
  • the falling edge and pulse width of the frame synchronization selection signal generate a second frame synchronization pulse signal, wherein the rising edge of
  • a prompt frame is sent to the display module after the reading of the current frame of the readout control module is completed, so as to keep the data output of the sending side and ensure its The connection is stable.
  • Fig. 2 is a flowchart of an image data transmission method provided by an embodiment of the present disclosure. As shown in Figure 2, the method includes:
  • Step S1 in response to the receiving sub-circuit being in a locked state, receiving the image data sent by the main board through the receiving sub-circuit, and according to the first frame synchronization signal, receiving the image data received from the main board within each clock cycle of the first frame synchronization signal Image data is written to the memory for one frame each.
  • the first frame synchronization signal is an associated clock signal, which can be used to divide the image data and determine each video frame transmitted by the main board; specifically, the receiving sub-circuit maintains the image data path with the main board in the locked state, and in the unlocked state That is, the clock is out of lock, and the image data cannot be received based on the original clock; and, the memory is pre-configured with multiple frame areas, and each frame is stored in the corresponding frame area according to the frame address allocated during writing.
  • step S1 respectively writes the image data received from the main board into one frame of the memory in each clock cycle of the first frame synchronization signal, including: In any clock cycle of the frame synchronization signal, write the image data received from the main board into the frame corresponding to the current frame address, and add 1 to the current frame address.
  • the method further includes: after power-on, initializing the current frame address.
  • Step S2 in response to the receiving sub-circuit being in a locked state, according to the second frame synchronization signal, read a frame from the memory within each clock cycle of the second frame synchronization signal.
  • the first time interval is greater than or equal to the clock cycle length of the first frame synchronization signal, which is reflected in the clock signal, that is, the second frame synchronization signal.
  • the second frame synchronization signal is a local clock signal; in order to prevent reading empty data, a write is reserved before reading data
  • step S2 reads a frame from the memory in each clock cycle of the second frame synchronization signal, including: in any clock cycle of the second frame synchronization signal , using the frame address obtained by subtracting 1 from the current frame address as the target frame address, and reading data from the frame corresponding to the target frame address.
  • Step S3 sending each frame read from the memory to the display module.
  • Step S4 in response to the receiving sub-circuit being in an unlocked state, stop writing image data into the memory.
  • the receiving subcircuit in response to an increase or decrease in the clock frequency of the main board's associated clock signal, the receiving subcircuit is adjusted from a locked state to an unlocked state, and the clock recovery lock signal sent to the main board is placed at a high power. flat.
  • the frequency of the associated clock corresponding to the image signal sent by the main board will also change adaptively, that is, the frequency of the corresponding clock will increase or decrease.
  • An embodiment of the present disclosure provides an image data transmission method, which distinguishes the timing control of the receiving side corresponding to the data receiving operation and data writing operation from the timing control of the sending side corresponding to the data read operation and data sending operation.
  • Timing control is performed based on the first frame synchronization signal corresponding to the main board (signal source) and its image signal, and the timing control is performed on the sending side based on its own second frame synchronization signal.
  • the channel clock signal changes with the When it changes, the clock on the receiving side loses lock, but the sending side continues to work based on the second frame synchronization signal, and continues to send valid data, and the signal connection with the display module and the display terminal will not be disconnected.
  • FIG. 3 is a schematic flowchart of another image data transmission method provided by an embodiment of the present disclosure. As shown in FIG. 3 , the method is an optional embodiment based on the method shown in FIG. 2 . Specifically, the method not only includes step S1, step S2 and step S4, but also includes step S5 and step S6. Only step S5 and step S6 will be described in detail below.
  • Step S5 in response to the receiving sub-circuit being in a locked state, sending each frame read from the memory to the display module.
  • Step S6 in response to the receiving sub-circuit being in an unlocked state, sending a preset prompt frame to the display module.
  • the reading of data from the memory is stopped, and a preset prompt frame is sent to the display module.
  • the prompt frame is used to prompt signal loss, and can be used as the display content of the display terminal when there is no image data input to the main board or the receiving sub-circuit is out of lock and cannot receive the image data sent by the main board.
  • the embodiment of the present disclosure provides an image data transmission method, the corresponding receiving side performs timing control based on the main board (signal source) and the first frame synchronization signal corresponding to the image signal, and the corresponding sending side performs timing control based on its own first frame synchronization signal
  • the timing control of the two-frame synchronization signal ensures that the sending side will not be affected by the change of the accompanying clock signal, and the signal connection with the display module and the display terminal remains stable.
  • the clock on the receiving side is out of lock, it provides a prompt to the display terminal.
  • the frame is displayed, and the valid data that can be displayed is kept continuously transmitted, so as to avoid abnormal display on the display end and enter the self-test state.
  • FIG. 4 is a schematic flowchart of another image data transmission method provided by an embodiment of the present disclosure. As shown in FIG. 4 , the method is an optional embodiment based on the method shown in FIG. 2 or FIG. 3 . Specifically, the figure shows the situation based on the method shown in FIG. 2 , which not only includes steps S1 to S3, but also includes step S01 before step S1. Only step S01 will be described in detail below.
  • Step S01 Shake hands with the main board according to the VBO protocol. After the clock data recovery is completed, the receiving sub-circuit is adjusted to a locked state, and the clock recovery locking signal sent to the main board is set to a low level.
  • the main board does not directly transmit the associated clock signal, and the image data transmission device needs to analyze the clock data from the data transmitted by the main board during the clock data recovery phase of the handshake to recover the associated clock , get the first frame sync signal.
  • the method further includes: in response to the receiving sub-circuit being adjusted to the unlocked state, performing handshaking with the main board again according to the VBO protocol, and correspondingly, after the clock data recovery is completed, re-adjusting the receiving sub-circuit to the locked state state.
  • the recovered first frame synchronization signal is adjusted through this step so that it is synchronized with the main board and the signal source, and then the corresponding steps in step S1 to step S5 are continued to be executed.
  • Fig. 5 is a flow chart of a specific implementation method of step S2 in the embodiment of the present disclosure. Specifically, when the receiving sub-circuit is adjusted to the locked state, the clock recovery locking signal sent to the main board is placed at a low level; as shown in Figure 5, step S2, according to the second frame synchronization signal, in the second frame synchronization signal
  • the step of reading out one frame from the memory in each clock cycle of includes: step S201 and step S202.
  • Step S201 in response to the receiving subcircuit being adjusted to a locked state, detecting a first target falling edge of a first frame synchronization signal.
  • Step S202 after the falling edge of the first target, read one frame from the memory in each clock cycle of the second frame synchronization signal.
  • the falling edge of the first target is the second falling edge after the falling edge of the clock recovery locking signal; thus, the data is read from the memory from the first clock cycle of the local clock after the falling edge of the first target , to allow enough time to write one frame.
  • the step of detecting the first target falling edge of the first frame synchronization signal includes: generating a first frame synchronization enable signal according to the first frame synchronization signal; The AND operation result between one frame synchronization enable signal generates the first frame synchronization selection signal; delays the first frame synchronization selection signal for a certain time interval to generate the first frame synchronization selection delay signal; according to the decline of the first frame synchronization selection signal.
  • the edge and the falling edge of the first frame synchronization selection delay signal determine the pulse width, and the first frame synchronization pulse signal is generated according to the falling edge and the pulse width of the first frame synchronization selection signal.
  • the high-level region of the first frame synchronization enable signal includes the high-level region of the first frame synchronization signal on the time axis, and the rising edge of the first frame synchronization pulse signal and the falling edge of the first target are at the same moment, by This is triggered by the first frame sync pulse signal to read the frame from the memory and send it to the display module.
  • FIG. 6 is a schematic diagram of multiple signals in an embodiment of the disclosure. As shown in Figure 6, it corresponds to step S201 and step S202, which exemplarily shows that in some embodiments, the clock recovery lock signal (LOCKN), the first frame synchronization signal (Source VS), and the first frame synchronization enable Signal (Source VS EN), first frame sync selection signal (Source VS Sel), first frame sync selection delay signal (Source VS Sel dly) and first frame sync pulse signal (Source VS PLS).
  • the clock recovery lock signal LCKN
  • the first frame synchronization signal Source VS
  • the first frame synchronization enable Signal Source VS EN
  • first frame sync selection signal Source VS Sel
  • first frame sync selection delay signal Source VS Sel dly
  • first frame sync pulse signal Source VS PLS
  • Fig. 7 is a flowchart of a specific implementation method of step S5 in the embodiment of the present disclosure. Specifically, at this time the receiving sub-circuit is adjusted to an unlocked state, and the clock recovery locking signal sent to the main board is placed at a high level; as shown in Figure 7, step S5, in response to the receiving sub-circuit being in an unlocked state, the The step of sending the preset prompt frame to the display module includes step S501.
  • Step S501 in response to the receiving sub-circuit being adjusted to an unlocked state, after a second time interval, sending a prompt frame to the display module.
  • the second time interval is less than or equal to the clock period length of the second frame synchronization signal; by reserving the second time interval, waiting for the current frame corresponding to the readout operation to be read, and then sending the prompt frame to the display module; Wherein, during the process of waiting for the second time interval, the current frame that has been read has been sent to the display module.
  • FIG. 8 is a flowchart of a specific implementation method of step S501 in the embodiment of the present disclosure. As shown in FIG. 8, step S501, in response to the receiving sub-circuit being adjusted to an unlocked state, sends a prompt frame to the display module after a second time interval, including steps S5011 and S5012.
  • Step S5011 in response to the receiving subcircuit being adjusted to an unlocked state, detecting the second target falling edge of the second frame synchronization signal.
  • the second target falling edge is the first falling edge after the rising edge of the clock recovery locking signal.
  • Step S5012 after the falling edge of the second target, send the prompt frame to the display module.
  • the second target falling edge is the first falling edge after the rising edge of the clock recovery locking signal; it is determined according to the second target falling edge to prevent the data read before and after the alternate switching of the locked state and the unlocked state from being generated.
  • the step of detecting the second target falling edge of the second frame synchronization signal includes: generating a second frame synchronization signal according to the second frame synchronization signal Enable signal; Generate a second frame synchronization selection signal according to the AND operation result between the second frame synchronization signal and the second frame synchronization enable signal; Delay the second frame synchronization selection signal by one clock cycle to generate a second frame synchronization selection delay signal; determine the pulse width according to the falling edge of the second frame synchronization selection signal and the falling edge of the second frame synchronization selection delay signal, and generate the second frame synchronization pulse signal according to the falling edge and pulse width of the second frame synchronization selection signal; wherein , the high level region of the second frame synchronization enable signal includes the high level region of the second frame synchronization signal on the time axis, the rising edge of the second frame synchronization pulse signal and the falling edge of the second target are at the same moment, thus The prompt frame is sent
  • the image data transmission method is applied to a corresponding image data transmission device, which belongs to a display system.
  • the image data transmission device is based on a field programmable gate array (Field Programmable Gate Array, referred to as FPGA); the display system It includes: a main board, an image data transmission device, a display module, and a display.
  • the main board, the image data transmission device, and the display module perform image data transmission based on the VBO protocol.
  • the image data transmission device and the main board shake hands according to the VBO protocol, wherein, after the clock data recovery is completed, the phase-locked loop module of the image data transmission adjusts its receiving sub-circuit to a locked state, and restores the clock sent to the main board to lock
  • the signal is placed at a low level; after the handshake is completed, the main board converts the video image signal from the signal source into the VBO signal format corresponding to the receiving sub-circuit (interface), and sends it to the receiving sub-circuit; the writing control of the image data transmission device
  • the module writes the image data received by the receiving sub-circuit in each clock cycle of the first frame synchronization signal into one frame of the memory; image data transmission
  • the readout control module of the device reads a frame from the memory in each clock cycle of the second frame synchronization signal according to the second frame synchronization signal, wherein the second frame synchronization signal is a local clock signal, and the second frame synchronization signal
  • the frequency of the associated clock signal corresponding to the main board and the image data sent by it changes accordingly. Since the receiving sub-circuit (interface) does not support the dynamic change of the clock, the first The frame synchronization signal is no longer corresponding to the main board’s accompanying clock signal, and the clock is out of lock.
  • the phase-locked loop adjusts the receiving sub-circuit from the locked state to the unlocked state; the writing control module immediately stops writing the image data into the memory, and the readout control module After the module reads the current frame, it stops reading data from the memory; the selection module responds to the receiving sub-circuit in an unlocked state, and after the second time interval, sends the preset prompt frame to the sending module, and passes The sending module sends it to the display module, wherein the second time interval is less than or equal to the clock cycle length of the second frame synchronization signal; the display module sends the prompt frame to the display for display. Therefore, when the clock is out of lock on the receiving side of the image data transmission device, the sending side sends a reminder frame to the display instead, so as to prevent the display from entering the self-checking state and display abnormality.
  • FIG. 9 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. As shown in Figure 9, the electronic equipment includes:
  • processors 101 one or more processors 101;
  • Memory 102 on which one or more programs are stored, and when the one or more programs are executed by the one or more processors, the one or more processors realize image data transmission as in any one of the above-mentioned embodiments method;
  • One or more I/O interfaces 103 are connected between the processor and the memory, and are configured to realize information exchange between the processor and the memory.
  • the processor 101 is a device with data processing capability, which includes but not limited to a central processing unit (CPU), etc.
  • the memory 102 is a device with data storage capability, which includes but not limited to a random access memory (RAM, more specifically Such as SDRAM, DDR, etc.), read-only memory (ROM), electrified erasable programmable read-only memory (EEPROM), flash memory (FLASH); I/O interface (read-write interface) 103 is connected between processor 101 and memory 102 , can realize information exchange between the processor 101 and the memory 102, which includes but not limited to a data bus (Bus) and the like.
  • RAM random access memory
  • ROM read-only memory
  • EEPROM electrified erasable programmable read-only memory
  • FLASH flash memory
  • I/O interface (read-write interface) 103 is connected between processor 101 and memory 102 , can realize information exchange between the processor 101 and the memory 102, which includes but not limited to a data bus (Bus) and the like.
  • the processor 101 , the memory 102 and the I/O interface 103 are connected to each other through the bus 104 , and are further connected to other components of the computing device.
  • the one or more processors 101 include field programmable gate arrays.
  • Fig. 10 is a schematic structural diagram of a computer-readable medium provided by an embodiment of the present disclosure.
  • a computer program is stored on the computer-readable medium, wherein, when the program is executed by a processor, the steps in the image data transmission method in any one of the above-mentioned embodiments are implemented.
  • An embodiment of the present disclosure also provides a display system, which includes: a main board, an image data transmission device and a display module, wherein the image data transmission device adopts the image data transmission device in any one of the above-mentioned embodiments.
  • the display module includes a Tcon board and a display.
  • the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components. Components cooperate to execute.
  • Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit .
  • Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
  • computer storage media includes both volatile and nonvolatile media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. permanent, removable and non-removable media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, tape, magnetic disk storage or other magnetic storage devices, or can Any other medium used to store desired information and which can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

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Abstract

一种图像数据传输装置，包括：接收子电路、写入控制模块以及读出控制模块。还提供了一种图像数据传输方法，包括：响应于接收子电路处于锁定状态，通过接收子电路接收主板发送的图像数据，并根据第一帧同步信号，将在第一帧同步信号的每个时钟周期内从主板处接收到的图像数据分别写入存储器的一帧；根据第二帧同步信号，在第二帧同步信号的每个时钟周期内从存储器中读出一帧；将从存储器中读出的每一帧送至显示模组；响应于接收子电路处于非锁定状态的情况，停止将图像数据写入存储器。还提供了一种电子设备、计算机可读介质和显示系统。

Description

图像数据传输装置、方法、电子设备、介质和显示系统 技术领域
本公开涉及视频图像技术领域，特别涉及一种图像数据传输装置、图像数据传输方法、电子设备、计算机可读介质和显示系统。
背景技术
现阶段，当信号源输入的视频信号的帧率发生改变时，主板发送的视频图像数据对应的参考时钟随之发生改变，但由于主板和显示端之间的中间设备的接口不支持时钟的动态变化，导致信号失锁，该中间设备与主板之间的信号连接会断开，并且该中间设备与显示端之间的信号连接也会受此影响而断开，并且，显示端由于信号连接断开，当即进入自检状态，播放自检状态对应的循环画面，出现显示异常的问题。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提供一种图像数据传输装置、图像数据传输方法、电子设备、计算机可读介质和显示系统。
为实现上述目的，第一方面，本公开实施例提供了一种图像数据传输装置，其包括：
接收子电路，用于接收主板发送的图像数据；
写入控制模块，用于响应于所述接收子电路处于锁定状态，根据第一帧同步信号，将所述接收子电路在所述第一帧同步信号的每个时钟周期内接收到的图像数据分别写入存储器的一帧，其中，所述第一帧同步信号为随路时钟信号；以及，响应于所述接收子电路处于非锁定状态，停止将图像数据写入存储器；
读出控制模块，用于响应于所述接收子电路处于所述锁定状态，根据第二帧同步信号，在所述第二帧同步信号的每个时钟周期内从所述存储器中读出一帧，其中，对于同一帧，其写入和读出之间存在第一时间间隔，所述第一时间间隔大于或等于所述第一帧同步信号的时钟周期长度，所述第二帧同 步信号为本地时钟信号；
发送模块，用于将所述读出控制模块读出的帧送至显示模组。
在一些实施例中，所述装置还包括：选择模块；
所述读出控制模块，具体用于在所述第二帧同步信号的每个时钟周期内从所述存储器中读出一帧并送至所述选择模块；
所述选择模块，用于响应于所述接收子电路处于所述锁定状态，将所述读出控制模块读出的每一帧送至发送模块；以及，响应于所述接收子电路处于所述非锁定状态，将预设的提示帧送至所述发送模块；
所述发送模块，用于将所述选择模块选择出的帧送至所述显示模组。
在一些实施例中，所述装置还包括：
锁相环模块，用于解析并恢复出所述第一帧同步信号；以及，将所述接收子电路调整为所述锁定状态或所述非锁定状态。
在一些实施例中，所述锁相环模块，还用于在将所述接收子电路调整为所述锁定状态时，将发送至所述主板的时钟恢复锁定信号置于低电平；以及，在将所述接收子电路调整为所述非锁定状态时，将发送至所述主板的时钟恢复锁定信号置于高电平。
在一些实施例中，所述读出控制模块，具体用于响应于所述接收子电路被调整为所述锁定状态，在所述第一帧同步信号的第一目标下降沿之后，在所述第二帧同步信号的每个时钟周期内从所述存储器中读出一帧，其中，所述第一目标下降沿为位于所述时钟恢复锁定信号的下降沿之后的第二个下降沿。
在一些实施例中，所述选择模块，具体用于响应于所述接收子电路被调整为所述非锁定状态，在经过第二时间间隔后，将所述提示帧送至所述发送模块，其中，所述第二时间间隔小于或等于所述第二帧同步信号的时钟周期长度。
在一些实施例中，所述选择模块，具体用于响应于所述接收子电路被调 整为所述非锁定状态，在所述第二帧同步信号的第二目标下降沿之后，将所述提示帧送至所述发送模块，其中，所述第二目标下降沿为位于所述时钟恢复锁定信号的上升沿之后的第一个下降沿。
在一些实施例中，在根据VBO协议与所述主板进行握手时，所述锁相环模块具体用于，在时钟数据恢复完成后，将所述接收子电路调整为所述锁定状态。
在一些实施例中，所述锁相环模块，具体用于响应于所述主板的随路时钟信号的时钟频率增大或减小，将所述接收子电路从所述锁定状态调整为所述非锁定状态。
第二方面，本公开实施例还提供了一种图像数据传输方法，其包括：
响应于接收子电路处于锁定状态，通过接收子电路接收主板发送的图像数据，并根据第一帧同步信号，将在所述第一帧同步信号的每个时钟周期内从所述主板处接收到的图像数据分别写入存储器的一帧，所述第一帧同步信号为随路时钟信号；
响应于所述接收子电路处于所述锁定状态，根据第二帧同步信号，在所述第二帧同步信号的每个时钟周期内从所述存储器中读出一帧，其中，对于同一帧，其写入和读出之间存在第一时间间隔，所述第一时间间隔大于或等于所述第一帧同步信号的时钟周期长度，所述第二帧同步信号为本地时钟信号；
将从所述存储器中读出的每一帧送至显示模组；
响应于所述接收子电路处于非锁定状态的情况，停止将图像数据写入存储器。
在一些实施例中，响应于所述接收子电路处于所述锁定状态，将从所述存储器中读出的每一帧送至显示模组；
响应于所述接收子电路处于所述非锁定状态，将预设的提示帧送至所述显示模组。
在一些实施例中，在所述根据第一帧同步信号，将在所述第一帧同步信号的每个时钟周期内从所述主板处接收到的图像数据分别写入存储器的一帧之前，还包括：
根据VBO协议与所述主板进行握手；其中，在时钟数据恢复完成后，将所述接收子电路调整为锁定状态，并将发送至所述主板的时钟恢复锁定信号置于低电平。
在一些实施例中，所述根据第二帧同步信号，在所述第二帧同步信号的每个时钟周期内从所述存储器中读出一帧并送至显示模组，包括：
响应于所述接收子电路被调整为所述锁定状态，检测所述第一帧同步信号的第一目标下降沿，其中，所述第一目标下降沿为位于所述时钟恢复锁定信号的下降沿之后的第二个下降沿；
在所述第一目标下降沿之后，在所述第二帧同步信号的每个时钟周期内从所述存储器中读出一帧。
在一些实施例中，响应于所述主板的随路时钟信号的时钟频率增大或减小，将所述接收子电路从锁定状态调整为所述非锁定状态，并将发送至所述主板的时钟恢复锁定信号置于高电平。
在一些实施例中，所述响应于所述接收子电路处于所述非锁定状态，将预设的提示帧送至所述显示模组，包括：
响应于所述接收子电路被调整为所述非锁定状态，在经过第二时间间隔后，将所述提示帧送至所述显示模组，其中，所述第二时间间隔小于或等于所述第二帧同步信号的时钟周期长度。
在一些实施例中，所述在经过第二时间间隔后，将所述提示帧送至所述显示模组，包括：
响应于所述接收子电路被调整为所述非锁定状态，检测第二帧同步信号的第二目标下降沿，其中，所述第二目标下降沿为位于所述时钟恢复锁定信号的上升沿之后的第一个下降沿；
在所述第二目标下降沿之后，将所述提示帧送至所述显示模组。
第三方面，本公开实施例还提供了一种电子设备，其包括：
一个或多个处理器；
存储器，用于存储一个或多个程序；
当所述一个或多个程序被所述一个或多个处理器执行，使得所述一个或多个处理器实现如上述实施例中任一所述的图像数据传输方法。
在一些实施例中，所述处理器包括现场可编程门阵列。
第四方面，本公开实施例还提供了一种计算机可读介质，其上存储有计算机程序，其中，所述计算机程序在被处理器执行时实现如上述实施例中任一所述的图像数据传输方法中的步骤。
第五方面，本公开实施例还提供了一种显示系统，其包括：
主板、图像数据传输装置和显示模组，其中，所述图像数据传输装置采用如上述实施例中任一所述的图像数据传输装置。
附图说明
图1为本公开实施例提供的一种图像数据传输装置的结构示意图；
图2为本公开实施例提供的一种图像数据传输方法的流程图；
图3为本公开实施例提供的另一种图像数据传输方法的流程示意图；
图4为本公开实施例提供的又一种图像数据传输方法的流程示意图；
图5为本公开实施例中步骤S2的一种具体实施方法流程图；
图6为本公开实施例中多个信号的示意图；
图7为本公开实施例中步骤S5的一种具体实施方法流程图；
图8为本公开实施例中步骤S501的一种具体实施方法流程图；
图9为本公开实施例提供的一种电子设备的结构示意图；
图10为本公开实施例提供的一种计算机可读介质的结构示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的图像数据传输装置、图像数据传输方法、电子设备、计算机可读介质和显示系统进行详细描述。
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现且不应当被解释为限于本文阐述的实施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
本文所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其他特征、整体、步骤、操作、元件、组件和/或其群组。
将理解的是，虽然本文可以使用术语第一、第二等来描述各种元件，但这些元件不应当受限于这些术语。这些术语仅用于区分一个元件和另一元件。因此，在不背离本公开的指教的情况下，下文讨论的第一元件、第一组件或第一模块可称为第二元件、第二组件或第二模块。
除非另外限定，否则本文所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
图1为本公开实施例提供的一种图像数据传输装置的结构示意图。如图1所示，该图像数据传输装置包括：接收子电路、写入控制模块、读出控制模块以及发送模块。
具体地，接收子电路用于接收主板发送的图像数据。
其中，该接收子电路在锁定状态下维持与主板的图像数据通路(lane)，在非锁定状态下即对时钟失锁，无法基于原时钟接收图像数据；该接收子电路的标识多为RX；主板可为系统级芯片(System on Chip，简称SoC)，又称片上系统，用于处理各种格式的视频图像信号，将其转换为与图像数据传输装置约定的信号格式，或将其转换为该接收子电路对应的信号格式。
写入控制模块用于响应于接收子电路处于锁定状态，根据主板的第一帧同步信号，将接收子电路在第一帧同步信号的每个时钟周期内接收到的图像数据分别写入存储器的一帧，其中，第一帧同步信号为随路时钟信号；以及，响应于接收子电路处于非锁定状态，停止将图像数据写入存储器。
其中，随路时钟是与输入的数据信号同步的时钟，数据信号的接收方根据随路时钟对接收的数据进行相应操作，在本公开的实施例中，随路时钟信号为与主板发送的图像数据对应的同步时钟信号，其需要随图像数据各项参数(如帧率等)的变化而变化，第一帧同步信号与主板的随路时钟信号属于相同的时钟域；存储器中预先配置有多个帧区域，每一帧根据写入时分配得到的帧地址存入对应的帧区域中；在一些实施例中，存储器为双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory，简称DDR SDRAM，又称DDR)。
读出控制模块用于响应于接收子电路处于锁定状态，根据第二帧同步信号，在第二帧同步信号的每个时钟周期内从存储器中读出一帧，其中，对于同一帧，其写入和读出之间存在第一时间间隔，第一时间间隔大于或等于第一帧同步信号的时钟周期长度，第二帧同步信号为本地时钟信号。
其中，第二帧同步信号对应图像数据传输装置的本地时钟，可由图像数据传输装置内部的相应模块，如本地晶振或如图所示的本地时钟模块产生，其仅根据本地配置进行改变，不随输入信号的频率变化而改变，并且，为保证与输出对象的稳定连接，在一些实施例中，本地时钟为固定且稳定的。
其中，为防止读取到空数据，则给写入控制模块预留出写入一帧或多帧的时间，在至少等待第一帧同步信号的一个时钟周期后，开始从存储器中读出一帧；在一些实施例中，第二帧同步信号与第一帧同步信号的时钟周期长度相等；或者，在一些实施例中，第二帧同步信号与第一帧同步信号的时钟周期长度相等且二者之间存在预设的相位差。
发送模块用于将读出控制模块读出的帧送至显示模组。
在一些实施例中，显示模组包括Tcon板和显示器，发送模块用于将读出控制模块读出的帧送至Tcon板。
在一些实施例中，如图所示，该装置还包括：选择模块。
具体地，读出控制模块，具体用于在第二帧同步信号的每个时钟周期内从存储器中读出一帧并送至选择模块。
在一些实施例中，读出控制模块还被配置为响应于接收子电路处于非锁定状态，停止从存储器中读出数据。
选择模块用于响应于接收子电路处于锁定状态，将读出控制模块读出的每一帧送至发送模块；以及，响应于接收子电路处于非锁定状态，将预设的提示帧送至发送模块。
在一些实施例中，在读出控制模块开始读出一帧之前，即在等待第一时间间隔时，选择模块将提示帧送至发送模块；提示帧用于提示信号丢失，例如通过屏幕调节方式(On Screen Display，简称OSD)显示特定字形或图形以提示当前无信号等；在一些实施例中，提示帧又称为背景帧(Backgroud)。
在一些实施例中，如图所示，该图像数据传输装置还包括提示帧控制模块，该提示帧控制模块用于存储提示帧，并根据第二帧同步信号在其每个时钟周期将提示帧送至选择模块，由此选择模块可在接收子电路处于非锁定状态时，将预设的提示帧送至发送模块。
其中，发送模块将选择模块选择出的、读出控制模块读出的帧，或提示帧送至显示模组；该发送模块的标识多为TX；在一些实施例中，发送模块 将需发送的图像帧发送至显示模组中的Tcon板，Tcon板又称逻辑板、控制板，Tcon板组接受到图像帧后将其送至显示模组中的显示端进行显示。
具体地，写入控制模块和接收子电路对应的接收侧属于基于第一帧同步信号的第一时钟域，读出控制模块、选择模块、以及发送模块对应的发送侧属于基于第二帧同步信号的第二时钟域，上述实施例中的提示帧控制模块同样属于第二时钟域。
以及，在一些实施例中，如图所示，该图像数据传输装置还包括：读写仲裁模块和存储器控制模块，前者用于对读写操作进行控制协调，后者用于维护存储器及管理存储器地址等，读写仲裁模块和存储器控制模块对应的存储侧属于基于存储器时钟的第三时钟域。
在现有技术中，图像数据传输装置的接收侧和发送侧属于同一时钟域，如基于第一帧同步信号的时钟域，则当信号源的视频信号帧率发生变化时，主板发送的图像信号对应的随路时钟也会适应性发生变化，由于该装置的接口(如高速串行接口)不支持时钟的动态变化，第一帧同步信号不能及时调整，装置整体会出现时钟失锁，装置与主板及显示端的信号连接断开，显示端当即会因为信号丢失进入自检状态，其中，显示端在无法进行数据锁定时会进入自检状态，在自检状态下，其显示内部画面，内部画面通常为红、绿、蓝等色彩进行循环的画面。
本公开实施例所提供的图像数据传输装置，由于其接收侧采用主板(信号源)及图像信号对应的随路时钟作为图像数据传递的参考时钟，发送侧采用图像数据传输装置的本地时钟作为图像数据传递的参考时钟，在接收侧出现时钟失锁时，发送侧基于第二帧同步信号持续工作，继续读出并发送预存的有效数据或其他有效数据，与显示模组及显示端的信号连接不会断开；以及在一些实施例中，在接收侧时钟失锁需要与主板调整连接关系时，停止读出数据，向显示端提供提示帧进行显示，由此保证发送侧的稳定连接，发送侧与显示端之间存在有效数据的传输，避免显示端出现显示异常，因为信号源的变化进入自检状态。
在一些实施例中，如图所示，该图像数据传输装置还包括：锁相环模块。
其中，锁相环模块用于解析并恢复出第一帧同步信号；以及，将接收子电路调整为锁定状态或非锁定状态。
在一些实施例中，锁相环模块具体用于在根据VBO协议(V-BY-ONE)与主板进行握手时，在时钟数据恢复(Clock Data Recovery training，简称CDR training)完成后，将接收子电路调整为锁定状态。以及，在一些实施例中，锁相环模块具体用于响应于主板的随路时钟信号的时钟频率增大或减小，将接收子电路从锁定状态调整为非锁定状态；其中，主板与接收子电路通过相应的多对信号线连接，当信号源的视频信号帧率发生变化时，主板发送的图像信号对应的随路时钟也会适应性地进行频率变化，在装置感知到时钟不同步数据接收收到影响后，接收子电路从锁定状态调整为非锁定状态，主板与装置的连接断开。
在一些实施例中，锁相环模块还用于在将接收子电路调整为锁定状态时，将发送至主板的时钟恢复锁定信号(Lockn)置于低电平；以及，在将接收子电路调整为非锁定状态时，将发送至主板的时钟恢复锁定信号置于高电平。
其中，时钟恢复锁定信号可由接收子电路发送至主板。
在一些实施例中，针对根据VBO协议建立的连接关系，主板并不直接传输随路时钟信号，图像数据传输装置需要在握手时的时钟数据恢复阶段从主板传输的数据中解析时钟数据，以恢复出随路时钟，得到第一帧同步信号，即第一帧同步信号为在本装置侧恢复出的主板的随路时钟信号。
具体地，装置根据VBO协议与主板进行握手时，首先建立连接，在与主板的VBO连接稳定时，将发送至主板的热拔插检测信号(Hot Plug Detect Signal，简称HTPDN)从高电平拉低至低电平；主板响应于该情况向接收子电路发送时钟数据恢复测试序列，进入时钟数据恢复阶段，以使得装置恢复出数据时钟；装置时钟数据恢复完成后，锁相环将接收子电路调整为锁定状态，并将发送至主板的时钟恢复锁定信号从高电平拉低至低电平；主板响应 于该情况向接收子电路发送对齐测试序列，进入对齐(Alignment training，简称ALN training)阶段，以将主板后续发送的信号中的有效像素和字节相对应；对齐完成后，主板开始发送图像数据。
在一些实施例中，读出控制模块具体用于响应于接收子电路被调整为锁定状态，在第一帧同步信号的第一目标下降沿之后，在第二帧同步信号的每个时钟周期内从存储器中读出一帧，其中，第一目标下降沿为位于时钟恢复锁定信号的下降沿之后的第二个下降沿。
需要说明的是，本公开各实施例中所描述的接收子电路处于锁定状态或非锁定状态意在强调在一段时间内的状态持续情况，而接收子电路被调整为锁定状态或非锁定状态意在强调在某一时刻的状态变化情况。
在一些实施例中，由图像传输装置的控制面或相应模块根据检测第一帧同步信号的第一目标下降沿。其中，在一些实施例中，基于必要的硬件逻辑，其首先根据第一帧同步信号生成第一帧同步使能信号，其中，第一帧同步使能信号的高电平区域在时间轴上包含第一帧同步信号的高电平区域；根据第一帧同步信号和第一帧同步使能信号之间的与运算结果生成第一帧同步选择信号；将第一帧同步选择信号延迟一定时间间隔，生成第一帧同步选择延迟信号；根据第一帧同步选择信号的下降沿和第一帧同步选择延迟信号的下降沿确定脉冲宽度，并根据第一帧同步选择信号的下降沿和脉冲宽度生成第一帧同步脉冲信号，其中，第一帧同步脉冲信号的上升沿和第一目标下降沿位于同一时刻；此后，将第一帧同步脉冲信号送至选择模块以指示第一目标下降沿的对应时刻，并触发选择模块将读出控制模块读出的每一帧送至发送模块。由此，在预留第一时间间隔的基础上，在第一目标下降沿之后开始读出数据，以保证预存有足够的帧。
需要说明的是，上述对确定目标下降沿的相关描述，仅为本公开实施例提供的一种可选实施方式，其不会对本公开技术方案产生限制，其他下降沿确定方式同样适用于本公开的技术方案。
在一些实施例中，选择模块具体用于响应于接收子电路被调整为非锁定 状态，在经过第二时间间隔后，将提示帧送至发送模块，其中，第二时间间隔小于或等于第二帧同步信号的时钟周期长度。
其中，为防止读出冲突，则至多预留第二帧同步信号的一个时钟周期，在保证读出控制模块能够完整地读出当前帧并由选择模块输出后，将提示帧送至发送模块。
在一些实施例中，选择模块，具体用于响应于接收子电路被调整为非锁定状态，在第二帧同步信号的第二目标下降沿之后，将提示帧送至发送模块，其中，第二目标下降沿为位于时钟恢复锁定信号的上升沿之后的第一个下降沿。在一些实施例中，第二目标下降沿即对应第二时间间隔的结束时刻。
在一些实施例中，由图像传输装置的控制面或相应模块根据检测第二帧同步信号的第二目标下降沿。其中，在一些实施例中，基于必要的硬件逻辑，与确定第一目标下降沿相类似地，其首先根据第二帧同步信号生成第二帧同步使能信号，其中，第二帧同步使能信号的高电平区域在时间轴上包含第二帧同步信号的高电平区域；根据第二帧同步信号和第二帧同步使能信号之间的与运算结果生成第二帧同步选择信号；将第二帧同步选择信号延迟一个时钟周期，生成第二帧同步选择延迟信号；根据第二帧同步选择信号的下降沿和第二帧同步选择延迟信号的下降沿确定脉冲宽度，并根据第二帧同步选择信号的下降沿和脉冲宽度生成第二帧同步脉冲信号，其中，第二帧同步脉冲信号的上升沿和第二目标下降沿位于同一时刻；此后，将第二帧同步脉冲信号送至选择模块以指示第二目标下降沿的对应时刻，并触发选择模块将提示帧送至发送模块。
由此，通过预留第二时间间隔，响应于接收子电路处于非锁定状态，在读出控制模块的当前帧读取完成后向显示模组发送提示帧，以保持发送侧数据输出，保证其连接稳定。
图2为本公开实施例提供的一种图像数据传输方法的流程图。如图2所示，该方法包括：
步骤S1、响应于接收子电路处于锁定状态，通过接收子电路接收主板发送的图像数据，并根据第一帧同步信号，将在第一帧同步信号的每个时钟周期内从主板处接收到的图像数据分别写入存储器的一帧。
其中，第一帧同步信号为随路时钟信号，可用于划分图像数据，确定主板传输的各个视频帧；具体地，接收子电路在锁定状态下维持与主板的图像数据通路，在非锁定状态下即对时钟失锁，无法基于原时钟接收图像数据；以及，存储器中预先配置有多个帧区域，每一帧根据写入时分配得到的帧地址存入对应的帧区域中。
在一些实施例中，步骤S1，根据第一帧同步信号，将在第一帧同步信号的每个时钟周期内从主板处接收到的图像数据分别写入存储器的一帧，包括：在第一帧同步信号的任意一个时钟周期内，将从主板处接收到的图像数据写入当前帧地址对应的帧中，并将当前帧地址进行加1处理。在一些实施例中，该方法还包括：在上电后，对当前帧地址进行初始化。
步骤S2、响应于接收子电路处于锁定状态，根据第二帧同步信号，在第二帧同步信号的每个时钟周期内从存储器中读出一帧。
其中，对于同一帧，其写入和读出之间存在第一时间间隔，第一时间间隔大于或等于第一帧同步信号的时钟周期长度，体现在时钟信号上，即第二帧同步信号的起始时刻与第一帧同步信号的起始时刻之间存在第一时间间隔；第二帧同步信号为本地时钟信号；为防止读取到空数据，则在读出数据前预留出写入一帧或多帧的时间，在至少等待第一帧同步信号的一个时钟周期后，开始从存储器中读出一帧。
在一些实施例中，步骤S2，根据第二帧同步信号，在第二帧同步信号的每个时钟周期内从存储器中读出一帧，包括：在第二帧同步信号的任意一个时钟周期内，将当前帧地址减1后得到的帧地址作为目标帧地址，从目标帧地址所对应的帧中读出数据。
步骤S3、将从存储器中读出的每一帧送至显示模组。
步骤S4、响应于接收子电路处于非锁定状态，停止将图像数据写入存储器。
其中，在接收子电路处于非锁定状态时，停止写入数据，而读出数据以及向显示模组输出数据不受影响。
在一些实施例中，响应于主板的随路时钟信号的时钟频率增大或减小，将接收子电路从锁定状态调整为非锁定状态，并将发送至主板的时钟恢复锁定信号置于高电平。
其中，当信号源的视频信号帧率发生变化时，主板发送的图像信号对应的随路时钟也会适应性地进行频率变化，即对应时钟频率增大或减小。
本公开实施例提供了一种图像数据传输方法，将数据接收操作、数据写入操作对应的接收侧的时序控制与数据读出操作、数据发送操作对应的发送侧的时序控制区分开，接收侧基于主板(信号源)及其图像信号对应的第一帧同步信号进行时序控制，发送侧基于自身的第二帧同步信号进行时序控制，在信号源视频图像帧率发生变化，随路时钟信号随之变化时，接收侧时钟失锁，但发送侧基于第二帧同步信号持续工作，继续发送有效数据，与显示模组及显示端的信号连接不会断开。
图3为本公开实施例提供的另一种图像数据传输方法的流程示意图。如图3所示，该方法为基于图2所示方法的一种具体化可选实施方案。具体地，该方法不仅包括步骤S1、步骤S2和步骤S4，还包括步骤S5和步骤S6。下面仅对步骤S5和步骤S6进行详细描述。
步骤S5、响应于接收子电路处于锁定状态，将从存储器中读出的每一帧送至显示模组。
步骤S6、响应于接收子电路处于非锁定状态，将预设的提示帧送至显示模组。
在一些实施例中，响应于接收子电路处于非锁定状态，停止从所述存储器中读出数据，并将预设的提示帧送至显示模组。
其中，提示帧用于提示信号丢失，在主板无图像数据输入以及接收子电路失锁无法接收主板发送的图像数据时，可作为显示端的显示内容。
由此，本公开实施例提供了一种图像数据传输方法，其对应的接收侧基于主板(信号源)及其图像信号对应的第一帧同步信号进行时序控制，对应的发送侧基于自身的第二帧同步信号进行时序控制，保证发送侧不会因随路时钟信号的改变而受到影响，与显示模组及显示端的信号连接保持稳定，同时在接收侧时钟失锁期间，向显示端提供提示帧进行显示，保持可显示的有效数据持续传输，避免显示端出现显示异常，进入自检状态。
图4为本公开实施例提供的又一种图像数据传输方法的流程示意图。如图4所示，该方法为基于图2或图3所示方法的一种具体化可选实施方案。具体地，图中示出了基于图2所示方法的情况，其不仅包括步骤S1至步骤S3，在步骤S1之前，还包括步骤S01。下面仅对步骤S01进行详细描述。
步骤S01、根据VBO协议与主板进行握手，其中，在时钟数据恢复完成后，将接收子电路调整为锁定状态，并将发送至主板的时钟恢复锁定信号置于低电平。
其中，针对根据VBO协议建立的连接关系，主板并不直接传输随路时钟信号，图像数据传输装置需要在握手时的时钟数据恢复阶段从主板传输的数据中解析时钟数据，以恢复出随路时钟，得到第一帧同步信号。
在一些实施例中，该方法还包括：响应于接收子电路被调整为非锁定状态，根据VBO协议与主板再次进行握手，相应地，在时钟数据恢复完成后，将接收子电路重新调整为锁定状态。其中，通过该步骤调整恢复出的第一帧同步信号，使得其与主板及信号源同步，并在此后继续执行步骤S1至步骤S5中的对应步骤。
图5为本公开实施例中步骤S2的一种具体实施方法流程图。具体地，接收子电路被调整为锁定状态时，发送至主板的时钟恢复锁定信号被置于低电平；如图5所示，步骤S2，根据第二帧同步信号，在第二帧同步信号的每 个时钟周期内从存储器中读出一帧的步骤，包括：步骤S201和步骤S202。
步骤S201、响应于接收子电路被调整为锁定状态，检测第一帧同步信号的第一目标下降沿。
步骤S202、在第一目标下降沿之后，在第二帧同步信号的每个时钟周期内从存储器中读出一帧。
其中，第一目标下降沿为位于时钟恢复锁定信号的下降沿之后的第二个下降沿；由此，从第一目标下降沿之后的本地时钟的第一个时钟周期开始从存储器中读出数据，以预留出足够写入一帧的时间。
在一些实施例中，步骤S201中，检测第一帧同步信号的第一目标下降沿的步骤，包括：根据第一帧同步信号生成第一帧同步使能信号；根据第一帧同步信号和第一帧同步使能信号之间的与运算结果生成第一帧同步选择信号；将第一帧同步选择信号延迟一定时间间隔，生成第一帧同步选择延迟信号；根据第一帧同步选择信号的下降沿和第一帧同步选择延迟信号的下降沿确定脉冲宽度，并根据第一帧同步选择信号的下降沿和脉冲宽度生成第一帧同步脉冲信号。其中，第一帧同步使能信号的高电平区域在时间轴上包含第一帧同步信号的高电平区域，第一帧同步脉冲信号的上升沿和第一目标下降沿位于同一时刻，由此根据第一帧同步脉冲信号触发将从存储器中读出帧并送至显示模组。
图6为本公开实施例中多个信号的示意图。如图6所示，其对应步骤S201和步骤S202，示例性地示出了一些实施例中的，时钟恢复锁定信号(LOCKN)、第一帧同步信号(Source VS)、第一帧同步使能信号(Source VS EN)、第一帧同步选择信号(Source VS Sel)、第一帧同步选择延迟信号(Source VS Sel dly)以及第一帧同步脉冲信号(Source VS PLS)。
需要说明的是，上述对确定目标下降沿的相关描述，仅为本公开实施例提供的一种可选实施方式，其不会对本公开技术方案产生限制，其他下降沿确定方式同样适用于本公开的技术方案。
图7为本公开实施例中步骤S5的一种具体实施方法流程图。具体地，此时接收子电路被调整为非锁定状态，发送至主板的时钟恢复锁定信号被置于高电平；如图7所示，步骤S5，响应于接收子电路处于非锁定状态，将预设的提示帧送至显示模组的步骤，包括步骤S501。
步骤S501、响应于接收子电路被调整为非锁定状态，在经过第二时间间隔后，将提示帧送至显示模组。
其中，第二时间间隔小于或等于第二帧同步信号的时钟周期长度；通过预留第二时间间隔，以等待读出操作对应的当前帧读取完成，此后将提示帧送至显示模组；其中，在等待第二时间间隔的过程中，读取完成的当前帧已送至显示模组。
图8为本公开实施例中步骤S501的一种具体实施方法流程图。如图8所示，步骤S501，响应于接收子电路被调整为非锁定状态，在经过第二时间间隔后，将提示帧送至显示模组的步骤，包括步骤S5011和步骤S5012。
步骤S5011、响应于接收子电路被调整为非锁定状态，检测第二帧同步信号的第二目标下降沿。
其中，第二目标下降沿为位于时钟恢复锁定信号的上升沿之后的第一个下降沿。
步骤S5012、在第二目标下降沿之后，将提示帧送至显示模组。
其中，第二目标下降沿为位于时钟恢复锁定信号的上升沿之后的第一个下降沿；根据第二目标下降沿确定出为防止在锁定状态和非锁定状态的交替切换前后读出的数据产生冲突而预留的第二时间间隔。
在一些实施例中，与确定第一目标下降沿相类似地，步骤S5011中，检测第二帧同步信号的第二目标下降沿的步骤，包括：根据第二帧同步信号生成第二帧同步使能信号；根据第二帧同步信号和第二帧同步使能信号之间的与运算结果生成第二帧同步选择信号；将第二帧同步选择信号延迟一个时钟周期，生成第二帧同步选择延迟信号；根据第二帧同步选择信号的下降沿和 第二帧同步选择延迟信号的下降沿确定脉冲宽度，并根据第二帧同步选择信号的下降沿和脉冲宽度生成第二帧同步脉冲信号；其中，第二帧同步使能信号的高电平区域在时间轴上包含第二帧同步信号的高电平区域，第二帧同步脉冲信号的上升沿和第二目标下降沿位于同一时刻，由此根据第二帧同步脉冲信号触发将提示帧送至显示模组。
下面对本公开提供的图像数据传输方法结合实际应用进行详细描述。该图像数据传输方法应用于相应的图像数据传输装置，该装置属于显示系统，在本实施例中，该图像数据传输装置基于现场可编程门阵列(Field Programmable Gate Array，简称FPGA)；该显示系统包括：主板、图像数据传输装置、显示模组和显示器，示例性地，主板、图像数据传输装置、显示模组之间基于VBO协议进行图像数据传输。
首先，图像数据传输装置与主板根据VBO协议进行握手，其中，在时钟数据恢复完成后，图像数据传输的锁相环模块将其接收子电路调整为锁定状态，并将发送至主板的时钟恢复锁定信号置于低电平；握手完成后，主板将来自信号源的视频图像信号，转换为接收子电路(接口)对应的VBO信号格式，并发送至接收子电路；图像数据传输装置的写入控制模块根据由锁相环模块解析并恢复出的第一帧同步信号，将接收子电路在第一帧同步信号的每个时钟周期内接收到的图像数据分别写入存储器的一帧；图像数据传输装置的读出控制模块根据第二帧同步信号，在第二帧同步信号的每个时钟周期内从存储器中读出一帧，其中，第二帧同步信号为本地时钟信号，第二帧同步信号的起始时刻与第一帧同步信号的起始时刻之间存在第一时间间隔，第一时间间隔大于或等于第一帧同步信号的时钟周期长度；图像数据传输装置的选择模块响应于接收子电路当前处于锁定状态，将读出控制模块读出的帧送至发送模块，并通过发送模块送至显示模组；显示模组将帧送至显示器面板(panel)以使得显示器显示该帧。
此后，响应于信号源的视频信号帧率发生变化，主板及其发送的图像数据对应的随路时钟信号的频率随之发生变化，由于接收子电路(接口)不支 持时钟的动态变化，第一帧同步信号与主板的随路时钟信号不再对应，时钟失锁，锁相环将接收子电路从锁定状态调整为非锁定状态；写入控制模块立刻停止将图像数据写入存储器，读出控制模块在读出完当前帧后，停止从存储器中读出数据；选择模块响应于接收子电路处于非锁定状态，在经过第二时间间隔后，将预设的提示帧送至发送模块，并通过发送模块送至显示模组，其中，第二时间间隔小于或等于第二帧同步信号的时钟周期长度；显示模组将提示帧送至显示器以进行显示。由此，在图像数据传输装置的接收侧出现时钟失锁时，其发送侧以提示帧作为替代发送至显示器，以防止显示器进入自检状态，出现显示异常的问题。
图9为本公开实施例提供的一种电子设备的结构示意图。如图9所示，该电子设备包括：
一个或多个处理器101；
存储器102，其上存储有一个或多个程序，当该一个或多个程序被该一个或多个处理器执行，使得该一个或多个处理器实现如上述实施例中任一的图像数据传输方法；
一个或多个I/O接口103，连接在处理器与存储器之间，配置为实现处理器与存储器的信息交互。
其中，处理器101为具有数据处理能力的器件，其包括但不限于中央处理器(CPU)等；存储器102为具有数据存储能力的器件，其包括但不限于随机存取存储器(RAM，更具体如SDRAM、DDR等)、只读存储器(ROM)、带电可擦可编程只读存储器(EEPROM)、闪存(FLASH)；I/O接口(读写接口)103连接在处理器101与存储器102间，能实现处理器101与存储器102的信息交互，其包括但不限于数据总线(Bus)等。
在一些实施例中，处理器101、存储器102和I/O接口103通过总线104相互连接，进而与计算设备的其它组件连接。
在一些实施例中，该一个或多个处理器101包括现场可编程门阵列。
图10为本公开实施例提供的一种计算机可读介质的结构示意图。该计算机可读介质上存储有计算机程序，其中，该程序被处理器执行时实现如上述实施例中任一的图像数据传输方法中的步骤。
本公开实施例还提供了一种显示系统，其包括：主板、图像数据传输装置和显示模组，其中，该图像数据传输装置采用如上述实施例中任一的图像数据传输装置。在一些实施例中，显示模组包括Tcon板和显示器。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
本文已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则可单独使用与特 定实施例相结合描述的特征、特性和/或元素，或可与其他实施例相结合描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。

Claims (20)

  1. 一种图像数据传输装置，其包括：
    接收子电路，用于接收主板发送的图像数据；
    写入控制模块，用于响应于所述接收子电路处于锁定状态，根据第一帧同步信号，将所述接收子电路在所述第一帧同步信号的每个时钟周期内接收到的图像数据分别写入存储器的一帧，其中，所述第一帧同步信号为随路时钟信号；以及，响应于所述接收子电路处于非锁定状态，停止将图像数据写入存储器；
    读出控制模块，用于响应于所述接收子电路处于所述锁定状态，根据第二帧同步信号，在所述第二帧同步信号的每个时钟周期内从所述存储器中读出一帧，其中，对于同一帧，其写入和读出之间存在第一时间间隔，所述第一时间间隔大于或等于所述第一帧同步信号的时钟周期长度，所述第二帧同步信号为本地时钟信号；
    发送模块，用于将所述读出控制模块读出的帧送至显示模组。
  2. 根据权利要求1所述的图像数据传输装置，其中，还包括：选择模块；
    所述读出控制模块，具体用于在所述第二帧同步信号的每个时钟周期内从所述存储器中读出一帧并送至所述选择模块；
    所述选择模块，用于响应于所述接收子电路处于所述锁定状态，将所述读出控制模块读出的每一帧送至发送模块；以及，响应于所述接收子电路处于所述非锁定状态，将预设的提示帧送至所述发送模块；
    所述发送模块，用于将所述选择模块选择出的帧送至所述显示模组。
  3. 根据权利要求2所述的图像数据传输装置，其中，还包括：
    锁相环模块，用于解析并恢复出所述第一帧同步信号；以及，将所述接收子电路调整为所述锁定状态或所述非锁定状态。
  4. 根据权利要求3所述的图像数据传输装置，其中，
    所述锁相环模块，还用于在将所述接收子电路调整为所述锁定状态时，将发送至所述主板的时钟恢复锁定信号置于低电平；以及，在将所述接收子电路调整为所述非锁定状态时，将发送至所述主板的时钟恢复锁定信号置于高电平。
  5. 根据权利要求1至4中任一所述的图像数据传输装置，其中，
    所述读出控制模块，具体用于响应于所述接收子电路被调整为所述锁定状态，在所述第一帧同步信号的第一目标下降沿之后，在所述第二帧同步信号的每个时钟周期内从所述存储器中读出一帧，其中，所述第一目标下降沿为位于所述时钟恢复锁定信号的下降沿之后的第二个下降沿。
  6. 根据权利要求4所述的图像数据传输装置，其中，
    所述选择模块，具体用于响应于所述接收子电路被调整为所述非锁定状态，在经过第二时间间隔后，将所述提示帧送至所述发送模块，其中，所述第二时间间隔小于或等于所述第二帧同步信号的时钟周期长度。
  7. 根据权利要求6所述的图像数据传输装置，其中，
    所述选择模块，具体用于响应于所述接收子电路被调整为所述非锁定状态，在所述第二帧同步信号的第二目标下降沿之后，将所述提示帧送至所述发送模块，其中，所述第二目标下降沿为位于所述时钟恢复锁定信号的上升沿之后的第一个下降沿。
  8. 根据权利要求3所述的图像数据传输装置，其中，
    在根据VBO协议与所述主板进行握手时，所述锁相环模块具体用于在时钟数据恢复完成后，将所述接收子电路调整为所述锁定状态。
  9. 根据权利要求3所述的图像数据传输装置，其中，
    所述锁相环模块，具体用于响应于所述主板的随路时钟信号的时钟频率增大或减小，将所述接收子电路从所述锁定状态调整为所述非锁定状态。
  10. 一种图像数据传输方法，其包括：
    响应于接收子电路处于锁定状态，通过所述接收子电路接收主板发送的图像数据，并根据第一帧同步信号，将在所述第一帧同步信号的每个时钟周期内从所述主板处接收到的图像数据分别写入存储器的一帧，所述第一帧同步信号为随路时钟信号；
    响应于所述接收子电路处于所述锁定状态，根据第二帧同步信号，在所述第二帧同步信号的每个时钟周期内从所述存储器中读出一帧，其中，对于同一帧，其写入和读出之间存在第一时间间隔，所述第一时间间隔大于或等于所述第一帧同步信号的时钟周期长度，所述第二帧同步信号为本地时钟信号；
    将从所述存储器中读出的每一帧送至显示模组；
    响应于所述接收子电路处于非锁定状态的情况，停止将所述主板发送的图像数据写入存储器。
  11. 根据权利要求10所述的图像数据传输方法，其中，
    响应于所述接收子电路处于所述锁定状态，将从所述存储器中读出的每一帧送至所述显示模组；
    响应于所述接收子电路处于所述非锁定状态，将预设的提示帧送至所述显示模组。
  12. 根据权利要求11所述的图像数据传输方法，其中，在所述根据第一帧同步信号，将在所述第一帧同步信号的每个时钟周期内从所述主板处接收到的图像数据分别写入存储器的一帧之前，还包括：
    根据VBO协议与所述主板进行握手；其中，在时钟数据恢复完成后，将所述接收子电路调整为锁定状态，并将发送至所述主板的时钟恢复锁定信号置于低电平。
  13. 根据权利要求10至12中任一所述的图像数据传输方法，其中，所述根据第二帧同步信号，在所述第二帧同步信号的每个时钟周期内从所述存储器中读出一帧，包括：
    响应于所述接收子电路被调整为所述锁定状态，检测所述第一帧同步信号的第一目标下降沿，其中，所述第一目标下降沿为位于所述时钟恢复锁定信号的下降沿之后的第二个下降沿；
    在所述第一目标下降沿之后，在所述第二帧同步信号的每个时钟周期内从所述存储器中读出一帧。
  14. 根据权利要求11所述的图像数据传输方法，其中，
    响应于所述主板的随路时钟信号的时钟频率增大或减小，将所述接收子电路从锁定状态调整为所述非锁定状态，并将发送至所述主板的时钟恢复锁定信号置于高电平。
  15. 根据权利要求14所述的图像数据传输方法，其中，所述响应于所述接收子电路处于所述非锁定状态，将预设的提示帧送至所述显示模组，包括：
    响应于所述接收子电路被调整为所述非锁定状态，在经过第二时间间隔后，将所述提示帧送至所述显示模组，其中，所述第二时间间隔小于或等于所述第二帧同步信号的时钟周期长度。
  16. 根据权利要求15所述的图像数据传输方法，其中，所述响应于所述接收子电路被调整为所述非锁定状态，在经过第二时间间隔后，将所述提示帧送至所述显示模组，包括：
    响应于所述接收子电路被调整为所述非锁定状态，检测第二帧同步信号的第二目标下降沿，其中，所述第二目标下降沿为位于所述时钟恢复锁定信号的上升沿之后的第一个下降沿；
    在所述第二目标下降沿之后，将所述提示帧送至所述显示模组。
  17. 一种电子设备，其包括：
    一个或多个处理器；
    存储器，用于存储一个或多个程序；
    当所述一个或多个程序被所述一个或多个处理器执行，使得所述一个或多个处理器实现如权利要求10至16中任一所述的图像数据传输方法。
  18. 根据权利要求17所述的电子设备，其中，
    所述处理器包括现场可编程门阵列。
  19. 一种计算机可读介质，其上存储有计算机程序，其中，所述计算机程序在被处理器执行时实现如权利要求10至16中任一所述的图像数据传输方法中的步骤。
  20. 一种显示系统，其包括：
    主板、图像数据传输装置和显示模组，其中，所述图像数据传输装置采用如权利要求1至9中任一所述的图像数据传输装置。
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