WO2022226835A1 - 视频数据处理装置及方法、显示系统 - Google Patents

视频数据处理装置及方法、显示系统 Download PDF

Info

Publication number
WO2022226835A1
WO2022226835A1 PCT/CN2021/090542 CN2021090542W WO2022226835A1 WO 2022226835 A1 WO2022226835 A1 WO 2022226835A1 CN 2021090542 W CN2021090542 W CN 2021090542W WO 2022226835 A1 WO2022226835 A1 WO 2022226835A1
Authority
WO
WIPO (PCT)
Prior art keywords
image quality
quality adjustment
module
adjustment parameter
video data
Prior art date
Application number
PCT/CN2021/090542
Other languages
English (en)
French (fr)
Inventor
马希通
耿立华
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/090542 priority Critical patent/WO2022226835A1/zh
Priority to CN202180000961.0A priority patent/CN115606171A/zh
Priority to US17/638,266 priority patent/US12045965B2/en
Publication of WO2022226835A1 publication Critical patent/WO2022226835A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/10—Image acquisition modality
    • G06T2207/10016—Video; Image sequence
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30168—Image quality inspection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0693—Calibration of display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/06—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour palettes, e.g. look-up tables

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a video data processing device, a video data processing method, and a display system.
  • the terminal device adjusts the image according to an instruction input by the user. For example, the color gamut of the image is adjusted according to the user's color gamut switching instruction; or, the color of the image is adjusted according to the user's color adjustment instruction.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a video data processing apparatus and method, and a display system.
  • a video data processing device comprising: a first acquisition module, a second acquisition module, a storage module and a processing module, wherein,
  • the first acquisition module is configured to, in response to the received image quality adjustment parameter, determine whether the image quality adjustment parameter satisfies a preset condition, and when the image quality adjustment parameter satisfies the preset condition, convert the image quality adjustment parameter to the image quality adjustment parameter. sending adjustment parameters to the storage module;
  • the storage module is configured to cache the image quality adjustment parameters, and in response to the control of the frame synchronization signal, send the image quality adjustment parameters to the processing module;
  • the second acquisition module is configured to acquire original video data, and send the original video data to the processing module in response to a valid data strobe signal; wherein, the transmission time period of the image quality adjustment parameter is the same as that of the image quality adjustment parameter.
  • the transmission time periods of the original video data do not overlap;
  • the processing module is configured to perform data processing on the original video data according to the image quality adjustment parameters to generate target video data.
  • the first obtaining module includes: a receiving sub-module and a checking sub-module, wherein,
  • the receiving sub-module is configured to receive the image quality adjustment parameter sent by the system chip
  • the verification sub-module is configured to determine whether the image quality adjustment parameter satisfies the preset condition, and when the image quality adjustment parameter satisfies the preset condition, control the receiving sub-module to send the image quality adjustment parameter to the The storage module; when the image quality adjustment parameter does not meet a preset condition, sending a data request signal to the system chip, so that the system chip re-sends the image quality adjustment parameter.
  • the image quality adjustment parameter is serial data
  • the serial data includes: a first keyword, at least one valid data, a second keyword, and a check value in order;
  • the verification value is obtained after performing the first operation on the first keyword, the second keyword and the valid data between them;
  • the syndrome sub-module is specifically configured to adjust the first keyword, the second keyword, the valid data between the first keyword and the second keyword in the received image quality adjustment parameters, and Perform a second operation on the check value, and compare the result of the second operation with the target value, and when the result of the second operation is equal to the target value, determine that the image quality adjustment parameter satisfies a preset condition; Otherwise, it is determined that the image quality adjustment parameter does not meet the preset condition.
  • the first operation includes an exclusive-OR operation and the second operation includes an exclusive-OR operation.
  • the first obtaining module receives the image quality adjustment parameter in a first clock domain
  • the device further includes: a timing generation module configured to generate the frame synchronization signal and the valid data strobe signal in a second clock domain; wherein the start time of the valid state of the frame synchronization signal is the same as the valid state start time of the frame synchronization signal. There is a preset time interval between the valid state start moments of the data strobe signal, and the clock frequency of the second clock domain is greater than the clock frequency of the first clock domain;
  • the storage module is specifically configured to cache the image quality adjustment parameters, and send the image quality adjustment parameters to the The processing module, wherein the clock frequency of the third clock domain is greater than the clock frequency of the second clock domain.
  • the storage module includes: a pulse generator and a first memory; wherein,
  • the first memory is configured to store the image quality adjustment parameter
  • the pulse generator is configured to generate a pulse signal in a third clock domain, where the pulse signal is used to control the first memory to output the image quality adjustment parameter to the processing module; wherein the pulse signal
  • the frequency of the pulse signal is the same as the frequency of the frame synchronization signal, and the rising edge time of the pulse signal is the same as the start time of the effective state of the frame synchronization signal.
  • the pulse generator includes: a first generating unit and a second generating unit, wherein,
  • the first generating unit is configured to delay the frame synchronization signal by a first time to obtain a delayed signal; wherein, the first time is a single clock pulse width of the third clock domain;
  • the second generating unit is configured to, after inverting the delay signal, perform an AND operation with the frame synchronization signal to obtain the pulse signal.
  • the second acquisition module includes: a receiver, a write memory controller, and a read memory controller;
  • the receiver is configured to receive the original video data in a fourth clock domain
  • the write memory controller is configured to write the original video data into the second memory in a fifth clock domain
  • the read memory controller is configured to read raw video data in the second memory in the fifth clock domain and send the raw video data to the processing in the second clock domain module.
  • Embodiments of the present disclosure further provide a display system, including: a display module, a system chip, and the above-mentioned video data processing device,
  • the system chip is configured to, in response to the image quality adjustment instruction, output corresponding image quality adjustment parameters
  • the display module is configured to display in response to the target video data output by the display driving device.
  • the present disclosure also provides a video data processing method applied to a video data processing device, wherein the video data processing device includes: a first acquisition module, a second acquisition module, a storage module and a processing module, and the method includes:
  • the first acquisition module determines whether the image quality adjustment parameter satisfies the preset condition, and when the image quality adjustment parameter satisfies the preset condition, sends the image quality adjustment parameter to the storage module;
  • the storage module buffers the image quality adjustment parameters, and sends the image quality adjustment parameters to the processing module in response to the control of the frame synchronization signal;
  • the second acquisition module acquires original video data, and sends the original video data to the processing module in response to a valid data gating signal; wherein, the transmission time period of the picture quality adjustment parameter is the same as the original video data.
  • the data transmission time periods do not overlap;
  • the processing module performs data processing on the original video data according to the image quality adjustment parameter to generate target video data.
  • the first obtaining module includes: a receiving sub-module and a checking sub-module,
  • the first acquisition module determines whether the image quality adjustment parameter satisfies the preset condition, and when the image quality adjustment parameter satisfies the preset condition, sends the image quality adjustment parameter To the storage module, it specifically includes:
  • the receiving sub-module receives the picture quality adjustment parameters sent by the system chip
  • the verification sub-module determines whether the image quality adjustment parameter satisfies the preset condition, and when the image quality adjustment parameter satisfies the preset condition, controls the receiving sub-module to output the image quality adjustment parameter to the storage module; when the image quality adjustment parameter does not meet the preset condition, send a data request signal to the system chip, so that the system chip re-sends the image quality adjustment parameter.
  • the image quality adjustment parameter is serial data
  • the serial data includes: a first keyword, at least one valid data, a second keyword, and a check value in order;
  • the verification value is obtained after performing the first operation on the first keyword, the second keyword and the valid data between them;
  • the check sub-module determines whether the image quality adjustment parameter satisfies a preset condition, and specifically includes:
  • the verification sub-module performs the first keyword, the second keyword, the valid data between the first keyword and the second keyword, and the check value in the received image quality adjustment parameters. Two operations are performed, and the result of the second operation is compared with the target value. When the result of the second operation is equal to the target value, it is determined that the image quality adjustment parameter satisfies the preset condition; otherwise, it is determined that the The image quality adjustment parameters do not meet the preset conditions.
  • the first operation includes an exclusive-OR operation and the second operation includes an exclusive-OR operation.
  • the first obtaining module receives the image quality adjustment parameter in a first clock domain; the apparatus further includes: a timing generation module;
  • both the frame synchronization signal and the valid data strobe signal are generated by the timing generation module in the second clock domain, and the start time of the valid state of the frame synchronization signal and the valid data strobe signal are There is a preset time interval between the starting moments of the valid state, and the clock frequency of the second clock domain is greater than the clock frequency of the first clock domain;
  • the storage module buffers the image quality adjustment parameters, and sends the image quality adjustment parameters to the processing module in the third clock domain from the starting moment of the valid state of the frame synchronization signal, wherein , the clock frequency of the third clock domain is greater than the clock frequency of the second clock domain.
  • the storage module includes: a pulse generator and a first memory
  • the storage module buffers the image quality adjustment parameters, and sends the image quality adjustment parameters to the processing module in the third clock domain from the start time of the valid state of the frame synchronization signal, which specifically includes:
  • the first memory stores the image quality adjustment parameter
  • the pulse generator generates a pulse signal in the third clock domain, and the pulse signal is used to control the first memory to output the image quality adjustment parameter to the processing module; wherein the frequency of the pulse signal is the same as the frequency of the pulse signal.
  • the frequency of the frame synchronization signal is the same, and the rising edge time of the pulse signal is the same as the start time of the effective state of the frame synchronization signal.
  • the pulse generator generates a pulse signal in the third clock domain, which specifically includes:
  • the pulse generator delays the frame synchronization signal by a first time to obtain a delay signal; after inverting the delay signal, performs AND operation with the frame synchronization signal to obtain the pulse signal; wherein, the The first time is a single clock pulse width of the third clock domain.
  • the second acquisition module includes: a receiver, a write memory controller, and a read memory controller;
  • the receiver receives the original video data in a fourth clock domain
  • the write memory controller writes the original video data into the second memory in a fifth clock domain
  • the read memory controller reads the original video data in the second memory under the fifth clock domain, and sends the original video data to the processing module under the second clock domain.
  • FIG. 1 is a schematic diagram of a video data processing apparatus provided in some embodiments of the present disclosure.
  • FIG. 2 is a schematic diagram of a video data processing apparatus provided in other embodiments of the present disclosure.
  • FIG. 3 is a schematic diagram of the composition of image quality adjustment parameters provided in some embodiments of the present disclosure.
  • FIG. 4 is a waveform diagram of some signals provided in some embodiments of the present disclosure.
  • FIG. 5 is a schematic diagram of a video data processing method provided in some embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of an optional manner of step S10 provided in some embodiments of the present disclosure.
  • FIG. 7 is a schematic diagram of a display system provided in some embodiments of the present disclosure.
  • FIG. 8 is a schematic diagram of a display process of a display system provided in some embodiments of the present disclosure.
  • the terminal device can use 3D LUT (Look Up Table, lookup table) technology to adjust the color gamut of the image to be adjusted. Specifically, according to the original pixel value of each pixel in the image to be adjusted, the target pixel value of each pixel is obtained according to the data in the lookup table, and then the adjusted image is displayed according to the target pixel value of each pixel .
  • 3D LUT Look Up Table, lookup table
  • gamut adjustment parameters i.e., data in 3D LUTs
  • the heterogeneous system includes a system chip and an FPGA (Field-Programmable Gate Array, Field Programmable Gate Array). Set the interface) to output the color gamut adjustment parameters to the FPGA.
  • FPGA Field-Programmable Gate Array, Field Programmable Gate Array
  • Set the interface to output the color gamut adjustment parameters to the FPGA.
  • the amount of data for the color gamut adjustment parameters is large, and the transmission of the parameters takes several frames, and the color gamut adjustment parameters will be dynamically updated, which may cause the pixels in some areas of the same frame image to be adjusted according to the original color gamut.
  • the pixel value is adjusted according to the parameters, while the pixels in another part of the area are adjusted according to the updated color gamut adjustment parameters, resulting in inconsistent display effects in different areas in the same frame image.
  • FIG. 1 is a schematic diagram of a video data processing apparatus provided in some embodiments of the present disclosure.
  • the video data processing apparatus 100 may be integrated in an FPGA.
  • the video data processing apparatus 100 includes: a first obtaining module 110 , a second obtaining module 120 , a storage module 130 and a processing module 140 .
  • the first obtaining module 110 is configured to, in response to the received image quality adjustment parameters, determine whether the image quality adjustment parameters satisfy a preset condition, and when the image quality adjustment parameters satisfy the preset conditions, adjust the image quality The parameters are sent to the storage module 130 .
  • the image quality adjustment parameters may be sent by the system chip to the video processing apparatus.
  • the system chip generates image quality adjustment parameters when receiving an image quality adjustment instruction input by the user.
  • the image quality adjustment instruction may be a color gamut adjustment instruction, a Gama adjustment instruction, or the like.
  • the image quality adjustment parameters may be: parameters corresponding to the Gama adjustment instruction, and parameters corresponding to the color gamut adjustment instruction.
  • the color gamut adjustment instruction may further include: a first color gamut adjustment instruction for adjusting the picture color gamut to a first color gamut, and a second color gamut for adjusting the picture color gamut to a second color gamut Adjustment instructions, third color gamut adjustment instructions for adjusting the screen color gamut to the third color gamut, etc.
  • the color gamut adjustment parameters output by the system chip may also be different.
  • the first acquisition module 110 may receive the image quality adjustment parameters sent by the system chip through the SPI interface.
  • the SPI interface can transmit image quality adjustment parameters in the first clock domain (ie, the SPI clock domain).
  • the first clock domain is used to generate a first reference signal, and the first reference signal is a clock signal; the SPI interface responds to a rising edge (or falling edge, or a high-level state, or a low-level state of the first reference signal) ) to perform data transmission, therefore, the data transmission rate in the first clock domain is related to the clock frequency of the first reference signal.
  • the storage module 130 is configured to store the image quality adjustment parameters, and in response to the control of the frame synchronization signal, send the image quality adjustment parameters to the processing module 140 .
  • the frame synchronization signal may be generated in the local clock domain, and the period of the frame synchronization signal is the display period of each frame of the video in the video.
  • the active state is the high state.
  • the second acquisition module 120 is configured to acquire original video data, and in response to the valid data strobe signal, transmit the original video data to the processing module 140; wherein, the original video data can be sent to the video data processing apparatus 100 by the video source, and the valid data
  • the preset time interval is the frame blanking phase of each frame image display period.
  • the transmission time period of the image quality adjustment parameter does not overlap with the transmission time period of the original video data.
  • the picture quality adjustment parameters may be transmitted to the processing module 140 in the local clock domain, or the picture quality adjustment parameters may be transmitted to the processing module 140 in the high-speed clock domain with a higher clock frequency.
  • the processing module 140 is configured to perform data processing on the original video data according to the image quality adjustment parameters to generate target video data.
  • the target video data can be sent to the display module through the sending module 160 for the display module to display according to the target video data.
  • the sending module 160 may use the V-BY-ONE standard to send data.
  • the time at which the processing module 140 receives the image quality adjustment parameters is different from that of the original video data. After the processing module 140 receives the image quality adjustment parameters, it can store the image quality adjustment parameters and use the image quality adjustment parameters. The parameters process the subsequently received original video data. In some time periods, the processing module 140 may not receive the image quality adjustment parameters, but only receive the original video data including multiple frames of image data. In this case, the processing module 140 may use the currently stored image quality adjustment parameters to pair raw video data for processing.
  • the image quality adjustment parameter is a parameter required when using 3D-LUT to perform color gamut adjustment, and the processing module 140 may specifically perform three-dimensional interpolation processing on the original video data according to the image quality adjustment parameter.
  • the storage module 130 first buffers the received image quality adjustment parameters, and then, under the control of the frame synchronization signal, Send the image quality adjustment parameters to the processing module 140; and the second acquisition module 120 sends the original video data to the processing module 140 under the control of the valid data strobe signal, and the transmission time period of the image quality adjustment parameters is the same as the original video data.
  • the transmission time periods of the video data do not overlap, so that when the processing module 140 processes the same frame of video image, it is processed based on the same image quality adjustment parameters, thereby ensuring that the display effects of different regions in the same frame of video image are consistent. .
  • FIG. 2 is a schematic diagram of a video data processing apparatus provided in other embodiments of the present disclosure.
  • the first acquisition module 110 includes: a receiving sub-module 112 and a syndrome sub-module 113.
  • the receiving sub-module 112 is configured to receive the image quality adjustment parameters sent by the system chip.
  • the image quality adjustment parameters are serial data
  • FIG. 3 is a schematic diagram of the composition of the image quality adjustment parameters.
  • the image quality adjustment parameters are arranged in order: the first keyword HEAD, at least one valid data DATA0 ⁇ DATAn, the second keyword END and the check value CRC.
  • the check value CRC is generated by the system chip, and the check value CRC is obtained by performing the first operation on the first keyword HEAD, the second keyword END and the valid data DATA0 to DATAn therebetween.
  • the receiving sub-module 112 may specifically include: a first detection unit 112a and a second detection unit 112b, the first detection unit 112a is used to detect the first keyword in the serial data, and the second detection unit 112b is used to detect the serial For the second keyword in the data, after the receiving sub-module 112 detects the first keyword and the second keyword, it can further determine the valid data between the first keyword and the second keyword, and the data after the second keyword. Check code.
  • the overall bit width of the image quality adjustment parameter can be set to 32 bits; the bit width of the valid data can be set to 30 bits, and The upper two bits of the valid data are filled with 0, and the upper two bits of the first keyword and the upper two bits of the second keyword are selected from "01", "10", and "11” respectively.
  • the first keyword is a 32-bit hexadecimal number: FFFF_FFFF_FFFF; the second keyword is a 32-bit hexadecimal number: 7FFF_FFFF_FFFF_FFFF.
  • the first operation includes an exclusive OR operation.
  • the verification sub-module 113 is configured to determine whether the image quality adjustment parameter satisfies the preset condition, and when the image quality adjustment parameter satisfies the preset condition, controls the receiving sub-module 112 to output the image quality adjustment parameter to the storage module 130; When the parameters do not meet the preset conditions, a data request signal is sent to the SoC 300, so that the SoC 300 resends the image quality adjustment parameters.
  • the check sub-module 113 is specifically configured to, in the received image quality adjustment parameters, the first keyword, the second keyword, the valid data between the first keyword and the second keyword, and the calibration parameters.
  • the second operation is performed on the test value, and the result of the second operation is compared with the target value.
  • the result of the second operation is equal to the target value, it is determined that the image quality adjustment parameter meets the preset condition; otherwise, it is determined that the image quality adjustment parameter is not
  • a data request signal is sent to the SoC 300 to request the SoC 300 to resend the image quality adjustment data.
  • the second operation includes an exclusive OR operation.
  • the result of the second operation is recorded as CRC', then:
  • the first operation is an XOR operation
  • the video data processing apparatus 100 further includes a timing generation module 150, and the timing generation module 150 is configured to generate frames in a second clock domain (ie, the local clock domain above) Sync signal and valid data strobe signal.
  • a second clock domain ie, the local clock domain above
  • Sync signal and valid data strobe signal There is a preset time interval between the start time of the valid state of the frame synchronization signal and the start time of the valid state of the valid data strobe signal, and the clock frequency of the second clock domain is greater than the clock frequency of the first clock domain.
  • the start time of the valid state of the frame synchronization signal may be the rising edge of the frame synchronization signal, and the preset time interval between the start time of the valid state of the frame synchronization signal and the start time of the valid state of the valid data strobe signal is , the frame blanking phase in a frame image display cycle.
  • the second clock domain is used to generate a second reference signal, and the second reference signal is a clock signal.
  • the timing generation module 150 can generate a frame synchronization signal and a valid data strobe signal according to the second reference signal; the sending module 160 can also The target video data is sent to the display module according to the second reference signal.
  • the second reference signal is generated by a local crystal oscillator.
  • the frame synchronization signal when the local crystal oscillator generates the rising edge (or falling edge) of the mth second reference signal, the frame synchronization signal is on the rising edge; when the local crystal oscillator generates the nth When the two reference signals are on the rising edge (or falling edge), the frame synchronization signal is on the falling edge, m>n, and both m and n are integers.
  • Timing parameter name Numerical value HTT (period of horizontal sync signal) 2200 (unit: 1VCLK) HAC (effective display time in one line) 1920 (unit: 1VCLK) HFP (front shoulder of horizontal sync signal) 88 (unit: 1VCLK) HSW (pulse width of horizontal sync signal) 44 (unit: 1VCLK) HBP (back shoulder of horizontal sync signal) 148 (unit: 1VCLK) VTT (period of frame sync signal) 1125 (unit: 1Line) VAC (effective display time in display cycle) 1080 (unit: 1Line) VFP (front shoulder of frame sync signal) 4 (unit: 1Line) VSW (width of frame sync signal) 5 (unit: 1Line) VBP (back shoulder of frame sync signal) 36 (unit: 1Line)
  • the storage module 130 sends the image quality adjustment parameters to the processing module 140 in the third clock domain from the start time of the valid state of the frame synchronization signal, wherein the third clock domain is used to generate the third reference signal, and the third clock domain is used to generate the third reference signal.
  • the three reference signals are clock signals; in the third clock domain, the storage module 130 can perform data transmission in response to a rising edge (or falling edge, or a high-level state, or a low-level state) of the third reference signal, so , the data transmission rate in the third clock domain is related to the clock frequency of the third reference signal.
  • the clock frequency of the third clock domain is greater than the clock frequency of the second clock domain. For example, the clock frequency of the third clock domain is twice that of the second clock domain.
  • the picture quality adjustment parameters are sent in the third clock domain, so as to ensure that the transmission of the picture quality adjustment parameters is completed in the frame blanking stage.
  • the starting moment of the valid state of the frame synchronization signal may be the rising edge moment, and because in the actual circuit design, it is difficult for the storage module 130 to directly detect the edge of the signal. Therefore, in practical applications, the third clock domain can be Next, a pulse signal is generated according to the frame synchronization signal, and image quality adjustment parameters are sent under the control of the pulse signal.
  • the storage module 130 includes: a pulse generator 132 and a first memory 131, and the first memory 131 may be RAM (random access memory, RAM).
  • the pulse generator 132 is configured to generate a pulse signal in the third clock domain, and the pulse signal is used to control the first memory 131 to output the image quality adjustment parameter to the processing module 140 .
  • DE is a valid data strobe signal.
  • the frequency of the pulse signal SOF is the same as that of the frame synchronization signal VS, the rising edge time of the pulse signal SOF is the same as the start time of the effective state of the frame synchronization signal VS; the clock frequency of the third clock domain is greater than that of the second clock domain.
  • the pulse generator 132 includes: a first generating unit and a second generating unit.
  • the first generating unit is configured to delay the frame synchronization signal VS by a first time T1 to obtain a delayed signal VS_DLY (as shown in FIG. 4 ); wherein, the first time T1 is a single clock pulse width of the third clock domain.
  • the second generating unit is configured to perform AND operation with the frame synchronization signal VS after inverting the delay signal VS_DLY to obtain the pulse signal SOF.
  • the frame synchronization signal VS and the delay signal VS_DLY are both signals that switch between the high-level state and the low-level state; inverting the signal is the high-level state and the low-level state of the signal. exchange.
  • the pulse signal is obtained by ANDing the two signals, that is, in the stage when both signals are in the high level state, the pulse signal SOF is in the high level state; and in other stages, the pulse signal SOF is in the low level state.
  • the second acquisition module 120 includes a receiver 121 , a write memory controller 122 and a read memory controller 123 .
  • the receiver 121 is configured to receive original video data in the fourth clock domain, the receiver 121 receives the original video data through an SDI (serial digital interface, serial digital) interface, and converts the received serial data into parallel video data.
  • SDI serial digital interface, serial digital
  • the fourth clock domain is the clock domain of the video source, the fourth clock domain is used to generate a fourth reference signal, the fourth reference signal is a clock signal, and the video source responds to the rising edge (or falling edge of the fourth reference signal) , or a high-level state, or a low-level state) to perform data transmission, therefore, the data transmission rate in the fourth clock domain is related to the clock frequency of the fourth reference signal.
  • the write memory controller 122 is configured to write raw video data to the second memory 200 in the fifth clock domain.
  • the second memory 200 is a DDR (Double Data Rate, double rate) memory
  • the fifth clock domain is a read and write clock domain of the DDR.
  • the read memory controller 123 is configured to, when the valid data strobe signal reaches a valid state, read the original video data in the memory in the fifth clock domain, and send the original video data to the processing module 140 in the second clock domain .
  • the fifth clock domain is used to generate a fifth reference signal
  • the fifth reference signal is a clock signal
  • the write memory controller 122 responds to the rising edge (or falling edge, or high level state, or low state) of the fifth reference signal level state) to write data into the second memory
  • the read memory controller 123 performs data reading in response to the rising edge (or falling edge, or high level state, or low level state) of the fifth reference signal. Therefore, the data read rate and the data write rate in the fifth clock domain are related to the clock frequency of the fifth reference signal.
  • the original video data of the video source is transmitted to the receiver 121 in the fourth clock domain, and the original video data received by the processing module 140 is transmitted in the second clock domain, the original video data is transmitted by the video source In the process to the processing module 140, the transmission across the clock domain needs to be performed.
  • the transmission across the clock domain needs to be performed.
  • the video data processing apparatus 100 may further include a switching module configured to, when the receiver 121 does not receive the original video data, acquire pre-stored preset image data from the second memory 200 or other locations, and output to the processing module 140, or directly to the display module through the sending module 160, so that when the video data processing device 100 does not receive video data, the display module can still display a preset image, which is used to prompt the user There is currently no video data input.
  • a switching module configured to, when the receiver 121 does not receive the original video data, acquire pre-stored preset image data from the second memory 200 or other locations, and output to the processing module 140, or directly to the display module through the sending module 160, so that when the video data processing device 100 does not receive video data, the display module can still display a preset image, which is used to prompt the user There is currently no video data input.
  • FIG. 5 is a schematic diagram of a video data processing method provided in some embodiments of the present disclosure, and the video data processing method is applied to the above video data processing apparatus 100 . 2 and 5, the video data processing method includes:
  • the first acquisition module 110 determines whether the image quality adjustment parameter satisfies the preset condition in response to the received image quality adjustment parameter, and sends the image quality adjustment parameter to the storage module 130 when the image quality adjustment parameter satisfies the preset condition.
  • the image quality adjustment parameter is sent by the system chip to the first acquisition module 110, and the first acquisition module 110 transmits it to the first acquisition module 110 in the first clock domain.
  • the system chip sends the image quality adjustment parameter to the first acquisition module 110 through the SPI interface, and the first clock domain is the SPI clock domain.
  • the storage module 130 buffers the image quality adjustment parameters, and sends the image quality adjustment parameters to the processing module 140 in response to the control of the frame synchronization signal.
  • the second acquisition module 120 acquires the original video data, and transmits the original video data to the processing module 140 in response to the valid data gating signal; wherein, the transmission time period of the image quality adjustment parameter is not the same as the transmission time period of the original video data. overlap.
  • the frame synchronization signal and the valid data strobe signal are generated by the timing generation module 150 in the second clock domain; wherein the start time of the valid state of the frame synchronization signal and the start of the valid state of the valid data strobe signal There is a preset time interval between the instants, and the clock frequency of the second clock domain is greater than the clock frequency of the first clock domain.
  • the processing module 140 performs data processing on the original video data according to the image quality adjustment parameters to generate target video data.
  • step S30 is independent of the processes of steps S10 to S20.
  • FIG. 6 is a schematic diagram of an optional manner of step S10 provided in some embodiments of the present disclosure. As shown in FIG. 6 , in some embodiments, step S10 specifically includes:
  • the receiving sub-module 112 receives the image quality adjustment parameter sent by the system chip.
  • the verification sub-module 113 determines whether the image quality adjustment parameter satisfies the preset condition, and when the image quality adjustment parameter satisfies the preset condition, controls the receiving sub-module 112 to output the image quality adjustment parameter to the storage module 130; When the preset condition is not met, a data request signal is sent to the SoC 300, so that the SoC 300 resends the image quality adjustment parameters.
  • the image quality adjustment parameter is serial data
  • the serial data includes: a first keyword, at least one valid data, a second keyword and a check value in order; wherein, the check value is the first keyword , the second keyword and the valid data between them are obtained after the first operation.
  • step S12 specifically includes: the verification sub-module 113 compares the first keyword, the second keyword, the valid data between the first keyword and the second keyword in the received image quality adjustment parameters, and The second operation is performed on the check value, and the result of the second operation is compared with the target value. When the result of the second operation is equal to the target value, it is determined that the image quality adjustment parameter satisfies the preset condition; otherwise, it is determined that the image quality adjustment parameter is not meet the preset conditions.
  • both the first operation and the second operation may be an exclusive OR operation.
  • step S20 specifically includes: S20a, the storage module 130 sends the image quality adjustment parameter to the processing module 140 in a third clock domain starting from the start time of the valid state of the frame synchronization signal, wherein the third clock The clock frequency of the domain is greater than the clock frequency of the second clock domain.
  • the storage module 130 specifically includes: a pulse generator 132 and a first memory 131 .
  • step S20a specifically includes: the first memory 131 stores the image quality adjustment parameters; the pulse generator 132 generates a pulse signal in the third clock domain, and the pulse signal is used to control the first memory 131 to output the image quality adjustment parameters to Processing module 140; wherein, the frequency of the pulse signal is the same as the frequency of the frame synchronization signal, and the rising edge time of the pulse signal is the same as the start time of the valid state of the frame synchronization signal; the clock frequency of the third clock domain is greater than the clock of the second clock domain frequency.
  • the pulse generator 132 generates a pulse signal in the third clock domain, which specifically includes: the pulse generator 132 delays the frame synchronization signal by a first time to obtain a delay signal; and operation to obtain the pulse signal; wherein, the first time is a single clock pulse width of the third clock domain.
  • step S30 specifically includes: the receiver 121 receives the original video data in the fourth clock domain; the write memory controller 122 writes the original video data into the second memory 200 in the fifth clock domain; read the memory control The controller 123 reads the original video data in the memory under the fifth clock domain, and sends the original video data to the processing module 140 under the second clock domain.
  • FIG. 7 is a schematic diagram of a display system provided in some embodiments of the present disclosure, and the display system may be a terminal device such as a monitor system, a computer, and a smart phone. As shown in FIG. 7 , the display system includes: a display module 400 , a system chip 300 and the above-mentioned video data processing apparatus 100 .
  • the system chip 300 is configured to, in response to the image quality adjustment instruction, output corresponding image quality adjustment parameters.
  • the display module 400 is configured to display in response to the target video data output by the video data processing apparatus 100 .
  • the display module 400 includes a display panel and a driving circuit, and the driving circuit is configured to provide a driving signal for the display panel according to target video data, so as to control the display panel to display.
  • FIG. 8 is a schematic diagram of a display process of a display system provided in some embodiments of the present disclosure. As shown in FIG. 8 , the display process includes:
  • step S1a the system chip 300 sends the image quality adjustment parameter to the video data processing apparatus 100 .
  • step S1b After receiving the image quality adjustment parameters, the first obtaining module 110 of the video data processing apparatus 100 determines whether the image quality adjustment parameters satisfy the preset conditions, and if so, proceeds to step S1c; otherwise, sends a data request instruction to the system chip 300 , so that step S1a is performed again.
  • S1c Output the image quality adjustment parameters to the storage module 130, so that the storage module 130 caches the image quality adjustment parameters.
  • the storage module 130 sends the buffered image quality adjustment parameters to the processing module 140.
  • the processing module 140 updates the parameters originally stored therein according to the received image quality adjustment parameters.
  • the video source sends the original video data to the video data processing apparatus 100, so that the video data processing module 140 executes steps S2a to S3.
  • the write memory controller 122 of the video data processing module 140 writes the received original video data to the second memory.
  • the read memory controller 123 of the video data processing module 140 reads the original video data from the second memory.
  • the read memory controller 123 sends the original video data to the processing module 140 in response to the valid data strobe signal.
  • the image quality adjustment parameters currently stored by the processing module 140 process the original video data to obtain target video data.
  • the display module displays according to the target video data.
  • the "currently stored image quality adjustment parameter" in step S3 is the image quality adjustment parameter sent by the SoC according to the image quality adjustment instruction; when the SoC does not receive the image quality adjustment instruction
  • the processing module 140 keeps the stored image quality adjustment parameters unchanged. At this time, the video source can still send the original video data. At this time, the processing module 140 can process according to the image quality adjustment parameters that have not been updated. .

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

公开了一种视频数据处理装置及方法、显示系统，包括：第一获取模块、第二获取模块、存储模块和处理模块，第一获取模块配置为，响应于接收到的画质调整参数，判断画质调整参数是否满足预设条件，当画质调整参数满足预设条件时，将画质调整参数发送至存储模块；存储模块配置为，对画质调整参数进行缓存，并响应于帧同步信号的控制，将画质调整参数发送至处理模块；第二获取模块配置为，获取原始视频数据，并响应于有效数据选通信号，将原始视频数据发送至处理模块；其中，画质调整参数的传输时间段与原始视频数据的传输时间段无交叠；处理模块配置为，根据画质调整参数对原始视频数据进行数据处理，生成目标视频数据。

Description

视频数据处理装置及方法、显示系统 技术领域
本公开涉及显示技术领域，具体涉及一种视频数据处理装置及视频数据处理方法、显示系统。
背景技术
随着科学技术的不断发展，诸如专业监视器、计算机、智能手机等终端设备被人们广泛使用。为了获得符合用户要求的图像显示效果，终端设备在显示图像时，会根据用户输入的指令对图像进行调整。例如，根据用户的色域切换指令，对图像的色域进行调整；或者，根据用户的颜色调整指令，对图像的颜色进行调整。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提出了一种视频数据处理装置及方法、显示系统。
为了实现上述目的，本公开提供一种视频数据处理装置，包括：第一获取模块、第二获取模块、存储模块和处理模块，其中，
所述第一获取模块配置为，响应于接收到的画质调整参数，判断所述画质调整参数是否满足预设条件，当所述画质调整参数满足预设条件时，将所述画质调整参数发送至所述存储模块；
所述存储模块配置为，对所述画质调整参数进行缓存，并响应于帧同步信号的控制，将所述画质调整参数发送至所述处理模块；
所述第二获取模块配置为，获取原始视频数据，并响应于有效数据选通信号，将所述原始视频数据发送至所述处理模块；其中，所述画质调整参数的传输时间段与所述原始视频数据的传输时间段无交叠；
所述处理模块配置为，根据所述画质调整参数对所述原始视频数 据进行数据处理，生成目标视频数据。
在一些实施例中，所述第一获取模块包括：接收子模块和校验子模块，其中，
所述接收子模块配置为，接收系统芯片所发送的所述画质调整参数；
所述校验子模块配置为，判断所述画质调整参数是否满足预设条件，当所述画质调整参数满足预设条件时，控制所述接收子模块将所述画质调整参数发送至所述存储模块；当所述画质调整参数不满足预设条件时，向所述系统芯片发送数据请求信号，以使所述系统芯片重新发送画质调整参数。
在一些实施例中，所述画质调整参数为串行数据，该串行数据包括依次排列的：第一关键字、至少一个有效数据、第二关键字和校验值；其中，所述校验值是对所述第一关键字、所述第二关键字以及二者之间的有效数据进行第一运算后得到的；
所述校验子模块具体被配置为，对接收到的画质调整参数中第一关键字、第二关键字、所述第一关键字与所述第二关键字之间的有效数据、以及校验值进行第二运算，并将所述第二运算的结果与目标值对比，当所述第二运算的结果与所述目标值相等时，确定所述画质调整参数满足预设条件；否则，确定所述画质调整参数不满足预设条件。
在一些实施例中，所述第一运算包括异或运算，所述第二运算包括异或运算。
在一些实施例中，所述第一获取模块在第一时钟域下接收所述画质调整参数；
所述装置还包括：时序产生模块，配置为在第二时钟域下产生所述帧同步信号和所述有效数据选通信号；其中，所述帧同步信号的有效状态起始时刻与所述有效数据选通信号的有效状态起始时刻之间具 有预设时间间隔，所述第二时钟域的时钟频率大于所述第一时钟域的时钟频率；
其中，所述存储模块具体配置为，对所述画质调整参数进行缓存，并从帧同步信号的有效状态起始时刻开始，在第三时钟域下将所述画质调整参数发送至所述处理模块，其中，所述第三时钟域的时钟频率大于所述第二时钟域的时钟频率。
在一些实施例中，所述存储模块包括：脉冲生成器和第一存储器；其中，
所述第一存储器配置为，存储所述画质调整参数；
所述脉冲生成器配置为，在第三时钟域下生成脉冲信号，所述脉冲信号用于控制所述第一存储器将所述画质调整参数输出至所述处理模块；其中，所述脉冲信号的频率与所述帧同步信号的频率相同，所述脉冲信号的上升沿时刻与所述帧同步信号的有效状态起始时刻相同。
在一些实施例中，所述脉冲生成器包括：第一生成单元和第二生成单元，其中，
所述第一生成单元配置为，将所述帧同步信号延迟第一时间，以获得延迟信号；其中，所述第一时间为所述第三时钟域的单时钟脉冲宽度；
所述第二生成单元配置为，将所述延迟信号取反后，与所述帧同步信号进行与操作，得到所述脉冲信号。
在一些实施例中，所述第二获取模块包括：接收器、写内存控制器和读内存控制器；
所述接收器配置为，在第四时钟域下接收所述原始视频数据；
所述写内存控制器配置为，在第五时钟域下将所述原始视频数据写入第二存储器；
所述读内存控制器配置为，在所述第五时钟域下读取所述第二存 储器中的原始视频数据，并在所述第二时钟域下将所述原始视频数据发送至所述处理模块。
本公开实施例还提供一种显示系统，包括：显示模组、系统芯片和上述的视频数据处理装置，
所述系统芯片配置为，响应于画质调整指令，输出相应的画质调整参数；
所述显示模组配置为，响应于所述显示驱动装置输出的目标视频数据进行显示。
本公开还提供一种应用于视频数据处理装置的视频数据处理方法，其中，所述视频数据处理装置包括：第一获取模块、第二获取模块、存储模块和处理模块，所述方法包括：
所述第一获取模块响应于接收到的画质调整参数，判断所述画质调整参数是否满足预设条件，当所述画质调整参数满足预设条件时，将所述画质调整参数发送至所述存储模块；
所述存储模块对所述画质调整参数进行缓存，并响应于帧同步信号的控制，将所述画质调整参数发送至所述处理模块；
所述第二获取模块获取原始视频数据，并响应于有效数据选通信号，将所述原始视频数据发送至所述处理模块；其中，所述画质调整参数的传输时间段与所述原始视频数据的传输时间段无交叠；
所述处理模块根据所述画质调整参数对所述原始视频数据进行数据处理，生成目标视频数据。
在一些实施例中，所述第一获取模块包括：接收子模块和校验子模块，
所述第一获取模块响应于接收到的画质调整参数，判断所述画质调整参数是否满足预设条件，当所述画质调整参数满足预设条件时，将所述画质调整参数发送至所述存储模块，具体包括：
所述接收子模块接收系统芯片所发送的画质调整参数；
所述校验子模块判断所述画质调整参数是否满足预设条件，当所述画质调整参数满足预设条件时，控制所述接收子模块将所述画质调整参数输出至所述存储模块；当所述画质调整参数不满足预设条件时，向所述系统芯片发送数据请求信号，以使所述系统芯片重新发送画质调整参数。
在一些实施例中，所述画质调整参数为串行数据，该串行数据包括依次排列的：第一关键字、至少一个有效数据、第二关键字和校验值；其中，所述校验值是对所述第一关键字、所述第二关键字以及二者之间的有效数据进行第一运算后得到的；
所述校验子模块判断所述画质调整参数是否满足预设条件，具体包括：
所述校验子模块对接收到的画质调整参数中第一关键字、第二关键字、所述第一关键字与所述第二关键字之间的有效数据、以及校验值进行第二运算，并将所述第二运算的结果与目标值对比，当所述第二运算的结果与所述目标值相等时，确定所述画质调整参数满足预设条件；否则，确定所述画质调整参数不满足预设条件。
在一些实施例中，所述第一运算包括异或运算，所述第二运算包括异或运算。
在一些实施例中，所述第一获取模块在第一时钟域下接收所述画质调整参数；所述装置还包括：时序产生模块；
其中，所述帧同步信号和所述有效数据选通信号均由所述时序产生模块在第二时钟域下产生，所述帧同步信号的有效状态起始时刻与所述有效数据选通信号的有效状态起始时刻之间具有预设时间间隔，所述第二时钟域的时钟频率大于所述第一时钟域的时钟频率；
其中，所述存储模块对所述画质调整参数进行缓存，并从帧同步 信号的有效状态起始时刻开始，在第三时钟域下将所述画质调整参数发送至所述处理模块，其中，所述第三时钟域的时钟频率大于所述第二时钟域的时钟频率。
在一些实施例中，所述存储模块包括：脉冲生成器和第一存储器；
所述存储模块对所述画质调整参数进行缓存，并从帧同步信号的有效状态起始时刻开始，在第三时钟域下将所述画质调整参数发送至所述处理模块，具体包括：
所述第一存储器存储所述画质调整参数；
所述脉冲生成器在第三时钟域下生成脉冲信号，所述脉冲信号用于控制所述第一存储器将所述画质调整参数输出至所述处理模块；其中，所述脉冲信号的频率与所述帧同步信号的频率相同，所述脉冲信号的上升沿时刻与所述帧同步信号的有效状态起始时刻相同。
在一些实施例中，所述脉冲生成器在第三时钟域下生成脉冲信号，具体包括：
所述脉冲生成器将所述帧同步信号延迟第一时间，以获得延迟信号；并将所述延迟信号取反后，与所述帧同步信号进行与操作，得到所述脉冲信号；其中，所述第一时间为所述第三时钟域的单时钟脉冲宽度。
在一些实施例中，所述第二获取模块包括：接收器、写内存控制器和读内存控制器；
所述接收器在第四时钟域下接收所述原始视频数据；
所述写内存控制器在第五时钟域下将所述原始视频数据写入第二存储器；
所述读内存控制器在所述第五时钟域下读取所述第二存储器中的原始视频数据，并在所述第二时钟域下将所述原始视频数据发送至所述处理模块。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为本公开的一些实施例中提供的视频数据处理装置的示意图。
图2为本公开的另一些实施例中提供的视频数据处理装置的示意图。
图3为本公开的一些实施例中提供的画质调整参数的组成示意图。
图4为本公开的一些实施例中提供的一些信号的波形图。
图5为本公开的一些实施例中提供的视频数据处理方法示意图。
图6为本公开的一些实施例中提供的步骤S10的一种可选方式示意图。
图7为本公开的一些实施例中提供的显示系统的示意图。
图8为本公开的一些实施例中提供的显示系统的显示过程示意图。
具体实施方式
以下结合附图对本实用新型的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本实用新型，并不用于限制本实用新型。
除非另作定义，本实用新型实施例使用的技术术语或者科学术语应当为本实用新型所属领域内具有一般技能的人士所理解的通常意义。本实用新型中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
在显示设备的使用过程中，可以根据用户的需要，对显示图像进 行色域调整、GAMA调整等处理。以色域调整为例，终端设备可以采用3D LUT(Look Up Table，查找表格)技术对待调整图像的色域进行调整。具体地，根据待调整的图像中每个像素点的原始像素值，根据查找表格中的数据获得每个像素点的目标像素值，之后，根据每个像素点的目标像素值显示调整后的图像。
通常，色域调整参数(即，3D LUT中的数据)会在异构系统中传输。具体地，异构系统包括系统芯片和FPGA(Field-Programmable Gate Array，现场可编程门阵列)，其中，当系统芯片接收到用户的色域调整指令时，通过SPI(Serial Peripheral Interface，串行外设接口)向FPGA输出色域调整参数。而色域调整参数的数据量较大，参数的传输需要几帧的时间，且色域调整参数会进行动态更新，这样就可能导致同一帧图像中，部分区域的像素是根据原来的色域调整参数来进行像素值调整的，而另一部分区域的像素是根据更新的色域调整参数来进行像素值调整的，从而导致同一帧图像中不同区域的显示效果不一致。
图1为本公开的一些实施例中提供的视频数据处理装置的示意图，可选地，该视频数据处理装置100可以集成在FPGA中。如图1所示，该视频数据处理装置100包括：第一获取模块110、第二获取模块120、存储模块130和处理模块140。
其中，第一获取模块110配置为，响应于接收到的画质调整参数，判断所述画质调整参数是否满足预设条件，当所述画质调整参数满足预设条件时，将画质调整参数发送至存储模块130。
其中，画质调整参数可以由系统芯片发送给视频处理装置。例如，系统芯片在接收到用户所输入的画质调整指令时，生成的画质调整参数。画质调整指令可以为色域调整指令、Gama调整指令等。画质调整参数可以为：与Gama调整指令所对应的参数、与色域调整指令所对应的参数。以色域调整指令为例，该色域调整指令可以进一步包括： 将画面色域调整为第一色域的第一色域调整指令、将画面色域调整为第二色域的第二色域调整指令、将画面色域调整为第三色域的第三色域调整指令等。对于不同的色域调整指令，系统芯片所输出的色域调整参数也可以不同。
其中，第一获取模块110可以通过SPI接口接收系统芯片所发送的画质调整参数。SPI接口可以在第一时钟域(即SPI时钟域)下传输画质调整参数。其中，第一时钟域用于产生第一参考信号，该第一参考信号为时钟信号；SPI接口响应于第一参考信号的上升沿(或者下降沿、或者高电平状态、或者低电平状态)来进行数据传输，因此，第一时钟域下的数据传输速率与第一参考信号的时钟频率相关。
存储模块130配置为存储画质调整参数，并响应于帧同步信号的控制，将画质调整参数发送至处理模块140。其中，帧同步信号可以在本地时钟域下产生，帧同步信号的周期即为视频中的每帧图像的显示周期。另外，“响应于帧同步信号的控制，将画质调整参数发送至处理模块140”是指，从帧同步信号的有效状态的起始时刻开始，或者从帧同步信号处于有效状态的结束时刻开始，或者从帧同步信号的有效状态起始时刻与结束时刻之间的某一时刻开始，将画质调整参数发送至处理模块140，直至画质调整参数发送完毕。例如，有效状态为高电平状态。
第二获取模块120配置为获取原始视频数据，并响应于有效数据选通信号，将原始视频数据传输至处理模块140；其中，原始视频数据可以由视频源发送给视频数据处理装置100，有效数据选通信号的有效状态起始时刻与帧同步信号的有效状态起始时刻之间有预设时间间隔。该预设时间间隔即为每帧图像显示周期的帧消隐阶段。画质调整参数的传输时间段与原始视频数据的传输时间段无交叠。
在一些实施例中，画质调整参数可以在本地时钟域传输至处理模 块140，或者，画质调整参数可以在时钟频率更高的高速时钟域传输至处理模块140。
处理模块140配置为根据画质调整参数对原始视频数据进行数据处理，生成目标视频数据。该目标视频数据可以通过发送模块160发送至显示模组，以供显示模组根据目标视频数据进行显示。其中，发送模块160可以采用V-BY-ONE的标准进行数据发送。
需要说明的是，处理模块140接收到画质调整参数和原始视频数据的时间不同，当处理模块140接收到画质调整参数后，则可以对画质调整参数进行存储，并利用该画质调整参数对后续接收到的原始视频数据进行处理。在一些时间段，处理模块140可能未接收到画质调整参数，而仅接收到包括多帧图像数据的原始视频数据，这种情况下，处理模块140则可以利用当前存储的画质调整参数对原始视频数据进行处理。
在一些示例中，画质调整参数为利用3D-LUT来进行色域调整时所需要的参数，处理模块140具体可以根据画质调整参数对原始视频数据进行三维插值处理。
在本公开实施例中，系统芯片所输出的画质调整参数发送至视频数据处理装置100后，存储模块130先对接收到的画质调整参数进行缓存，之后，在帧同步信号的控制下，将画质调整参数发送至处理模块140；而第二获取模块120是在有效数据选通信号的控制下，将原始视频数据发送至处理模块140的，且画质调整参数的传输时间段与原始视频数据的传输时间段无交叠，从而使得处理模块140对同一帧视频图像进行处理时，是基于相同的画质调整参数来进行处理的，进而保证同一帧视频图像中不同区域的显示效果一致。
图2为本公开的另一些实施例中提供的视频数据处理装置的示意图，如图2所示，第一获取模块110包括：接收子模块112和校验子 模块113。
其中，接收子模块112配置为，接收系统芯片所发送的画质调整参数。
可选地，画质调整参数为串行数据，图3为画质调整参数的组成示意图，如图3所示，画质调整参数依次排列的：第一关键字HEAD、至少一个有效数据DATA0～DATAn、第二关键字END和校验值CRC。其中，校验值CRC由系统芯片所生成，并且，校验值CRC是对第一关键字HEAD、第二关键字END以及二者之间的有效数据DATA0～DATAn进行第一运算后得到的。
其中，接收子模块112具体可以包括：第一检测单元112a和第二检测单元112b，第一检测单元112a用于检测串行数据中的第一关键字，第二检测单元112b用于检测串行数据中的第二关键字，接收子模块112检测出第一关键字和第二关键字之后，可以进一步确定第一关键字与第二关键字之间的有效数据、以及第二关键字之后的校验码。
示例性地，为了区分出串行数据中的第一关键字、第二关键字和有效数据，可以将画质调整参数整体的位宽设置为32bit；将有效数据的位宽为30bit，并在有效数据的高两位补0，第一关键字的高两位和第二关键字的高两位分别选自“01”、“10”、“11”中的两者。例如，第一关键字为32位16进制数：FFFF_FFFF_FFFF_FFFF；第二关键字为32位16进制数：7FFF_FFFF_FFFF_FFFF。
示例性地，第一运算包括异或运算。
即，关键字CRC＝HEAD^DATA0^DATA1……^DATAn^END。
校验子模块113配置为，判断画质调整参数是否满足预设条件，当画质调整参数满足预设条件时，控制接收子模块112将画质调整参数输出至存储模块130；当画质调整参数不满足预设条件时，向系统芯片300发送数据请求信号，以使系统芯片300重新发送画质调整参 数。
可选地，校验子模块113具体被配置为，对接收到的画质调整参数中第一关键字、第二关键字、第一关键字与第二关键字之间的有效数据、以及校验值进行第二运算，并将该第二运算的结果与目标值对比，当第二运算的结果与目标值相等时，确定画质调整参数满足预设条件；否则，确定画质调整参数不满足预设条件，即，确定画质调整参数在传输过程中发生传输错误，此时，向系统芯片300发送数据请求信号，以请求系统芯片300重新发送画质调整数据。
其中，第二运算包括异或运算。第二运算的结果记作CRC’，则：
CRC’＝HEAD^DATA0^DATA1……^DATAn^END^CRC
当第一运算为异或运算时，则在画质调整参数传输准确的情况下，CRC’＝CRC^CRC＝0；因此，在一些实施例中，第一运算和第二运算均为异或运算时，目标值可以设置为0。
在一些实施例中，如图2所示，视频数据处理装置100还包括时序产生模块150，该时序产生模块150配置为，在第二时钟域(也即上文中的本地时钟域)下产生帧同步信号和有效数据选通信号。其中，帧同步信号的有效状态起始时刻与有效数据选通信号的有效状态起始时刻之间具有预设时间间隔，第二时钟域的时钟频率大于第一时钟域的时钟频率。例如，帧同步信号的有效状态起始时刻可以为帧同步信号的上升沿，帧同步信号的有效状态起始时刻与有效数据选通信号的有效状态起始时刻之间的预设时间间隔即为，一帧图像显示周期中的帧消隐阶段。其中，第二时钟域用于产生第二参考信号，该第二参考信号为时钟信号，时序产生模块150可以根据第二参考信号来生成帧同步信号和有效数据选通信号；发送模块160也可以根据第二参考信号来将目标视频数据发送给显示模组。例如，第二参考信号由本地晶振产生，例如，当本地晶振产生第m个第二参考信号的上升沿(或下 降沿)时，则帧同步信号处于上升沿；当本地晶振产生第n个第二参考信号的上升沿(或下降沿)时，则帧同步信号处于下降沿，m＞n，m、n均为整数。
其中，时序产生模块150输出的信号时序说明如下表1所示，其中，1VCLK表示第二时钟域中的一个时钟的时间；1Line表示显示一行的时间。
表1
时序参数名称 数值
HTT(行同步信号的周期) 2200(单位：1VCLK)
HAC(一行中的有效显示时间) 1920(单位：1VCLK)
HFP(行同步信号的前肩) 88(单位：1VCLK)
HSW(行同步信号的脉宽) 44(单位：1VCLK)
HBP(行同步信号的后肩) 148(单位：1VCLK)
VTT(帧同步信号的周期) 1125(单位：1Line)
VAC(显示周期中的有效显示时间) 1080(单位：1Line)
VFP(帧同步信号的前肩) 4(单位：1Line)
VSW(帧同步信号的宽度) 5(单位：1Line)
VBP(帧同步信号的后肩) 36(单位：1Line)
其中，存储模块130从帧同步信号的有效状态起始时刻开始，在第三时钟域下将画质调整参数发送至处理模块140，其中，第三时钟域用于产生第三参考信号，该第三参考信号为时钟信号；在第三时钟域下，存储模块130可以响应于第三参考信号的上升沿(或者下降沿、或者高电平状态、或者低电平状态)来进行数据传输，因此，第三时钟域下的数据传输速率与第三参考信号的时钟频率相关。第三时钟域的时钟频率大于第二时钟域的时钟频率。例如，第三时钟域的时钟频 率为第二时钟域的两倍。在第三时钟域下发送画质调整参数，从而保证画质调整参数在帧消隐阶段传输完毕。
其中，帧同步信号的有效状态起始时刻可以为上升沿时刻，而由于在实际的电路设计中，存储模块130难以直接检测到信号的边沿，因此，在实际应用中，可以在第三时钟域下根据帧同步信号生成脉冲信号，并在该脉冲信号的控制下发送画质调整参数。具体地，存储模块130包括：脉冲生成器132和第一存储器131，第一存储器131可以为RAM(random access memory，RAM)。脉冲生成器132配置为，在第三时钟域下生成脉冲信号，脉冲信号用于控制第一存储器131将画质调整参数输出至处理模块140。图4为本公开中的一些实施例中提供的一些信号的波形图，如图4所示，DE为有效数据选通信号。脉冲信号SOF的频率与帧同步信号VS的频率相同，脉冲信号SOF的上升沿时刻与帧同步信号VS的有效状态起始时刻相同；第三时钟域的时钟频率大于第二时钟域的时钟频率。
可选地，脉冲生成器132包括：第一生成单元和第二生成单元。其中，第一生成单元配置为，将帧同步信号VS延迟第一时间T1，以获得延迟信号VS_DLY(如图4所示)；其中，第一时间T1为第三时钟域的单时钟脉冲宽度。第二生成单元配置为，将延迟信号VS_DLY取反后，与帧同步信号VS进行与操作，得到脉冲信号SOF。
需要说明的是，帧同步信号VS、延迟信号VS_DLY均为在高电平状态和低电平状态之间切换的信号；将信号取反即为，将信号的高电平状态和低电平状态互换。将两个信号进行与操作得到脉冲信号即为，在两个信号均处于高电平状态的阶段，脉冲信号SOF处于高电平状态；而在其他阶段，脉冲信号SOF处于低电平状态。
在一些实施例中，第二获取模块120包括：接收器121、写内存控制器122和读内存控制器123。
其中，接收器121配置为在第四时钟域下接收原始视频数据，接收器121通过SDI(serial digital interface，串行数字)接口接收原始视频数据，并将接收到的串行数据转换为并行的视频数据。
其中，第四时钟域即为视频源的时钟域，第四时钟域用于产生第四参考信号，该第四参考信号为时钟信号，视频源响应于第四参考信号的上升沿(或者下降沿、或者高电平状态、或者低电平状态)来进行数据传输，因此，第四时钟域下的数据传输速率与第四参考信号的时钟频率相关。
写内存控制器122配置为，在第五时钟域下将原始视频数据写入第二存储器200。例如，第二存储器200为DDR(Double Data Rate，双倍速率)存储器，第五时钟域为DDR的读写时钟域。
读内存控制器123配置为，当有效数据选通信号达到有效状态时，在第五时钟域下读取存储器中的原始视频数据，并在第二时钟域下将原始视频数据发送至处理模块140。
其中，第五时钟域用于产生第五参考信号，该第五参考信号为时钟信号，写内存控制器122响应于第五参考信号的上升沿(或者下降沿、或者高电平状态、或者低电平状态)来将数据写入第二存储器；读内存控制器123响应于第五参考信号的上升沿(或者下降沿、或者高电平状态、或者低电平状态)来进行数据读取。因此，第五时钟域下的数据读取速率和数据写入速率与第五参考信号的时钟频率相关。
由于视频源的原始视频数据是在第四时钟域下传输给接收器121的，而处理模块140接收到的原始视频数据是在第二时钟域下传输的，因此，原始视频数据由视频源传输至处理模块140的过程中，需要进行跨时钟域的传输。而通过读内存控制器123、写内存控制器122的设置，可以实现数据的跨时钟域传输。另外，视频数据处理装置100还可以包括切换模块，该切换模块配置为，在接收器121未接收到原 始视频数据时，从第二存储器200或其他位置获取预先存储的预设图像数据，并输出至处理模块140，或直接通过发送模块160发送至显示模组，从而在视频数据处理装置100未接收到视频数据的情况下，显示模组仍能够显示预设的图像，该图像用于提示用户当前无视频数据输入。
图5为本公开的一些实施例中提供的视频数据处理方法示意图，该视频数据处理方法应用于上述视频数据处理装置100。结合图2和图5所示，该视频数据处理方法包括：
S10、第一获取模块110响应于接收到的画质调整参数，判断画质调整参数是否满足预设条件，当画质调整参数满足预设条件时，将画质调整参数发送至存储模块130。在一些实施例中，画质调整参数由系统芯片发送至第一获取模块110，第一获取模块110在第一时钟域下传输至第一获取模块110。例如，系统芯片通过SPI接口将画质调整参数发送至第一获取模块110，第一时钟域为SPI时钟域。
S20、存储模块130对画质调整参数进行缓存，并响应于帧同步信号的控制，将画质调整参数发送至处理模块140。
S30、第二获取模块120获取原始视频数据，并响应于有效数据选通信号，将原始视频数据传输至处理模块140；其中，画质调整参数的传输时间段与原始视频数据的传输时间段无交叠。在一些实施例中，帧同步信号和有效数据选通信号由时序产生模块150在第二时钟域下产生；其中，帧同步信号的有效状态起始时刻与有效数据选通信号的有效状态起始时刻之间具有预设时间间隔，第二时钟域的时钟频率大于第一时钟域的时钟频率。
S40、处理模块140根据画质调整参数对原始视频数据进行数据处理，生成目标视频数据。
需要说明的是，步骤S30的过程与步骤S10～S20的过程独立开。
图6为本公开的一些实施例中提供的步骤S10的一种可选方式示意图，如图6所示，在一些实施例中，步骤S10具体包括：
S11、接收子模块112接收系统芯片所发送的画质调整参数。
S12、校验子模块113判断画质调整参数是否满足预设条件，当画质调整参数满足预设条件时，控制接收子模块112将画质调整参数输出至存储模块130；当画质调整参数不满足预设条件时，向系统芯片300发送数据请求信号，以使系统芯片300重新发送画质调整参数。
其中，画质调整参数为串行数据，该串行数据包括依次排列的：第一关键字、至少一个有效数据、第二关键字和校验值；其中，校验值是对第一关键字、第二关键字以及二者之间的有效数据进行第一运算后得到的。这种情况下，步骤S12具体包括：校验子模块113对接收到的画质调整参数中第一关键字、第二关键字、第一关键字与第二关键字之间的有效数据、以及校验值进行第二运算，并将第二运算的结果与目标值对比，当第二运算的结果与目标值相等时，确定画质调整参数满足预设条件；否则，确定画质调整参数不满足预设条件。
其中，第一运算和第二运算均可以为异或运算。
其中，步骤S20具体包括：S20a、存储模块130从帧同步信号的有效状态起始时刻开始，在第三时钟域下将所述画质调整参数发送至处理模块140，其中，所述第三时钟域的时钟频率大于所述第二时钟域的时钟频率。
如上文所述，存储模块130具体包括：脉冲生成器132和第一存储器131。这种情况下，步骤S20a具体包括：第一存储器131存储画质调整参数；脉冲生成器132在第三时钟域下生成脉冲信号，脉冲信号用于控制第一存储器131将画质调整参数输出至处理模块140；其中，脉冲信号的频率与帧同步信号的频率相同，脉冲信号的上升沿时刻与帧同步信号的有效状态起始时刻相同；第三时钟域的时钟频率大 于第二时钟域的时钟频率。
其中，脉冲生成器132在第三时钟域下生成脉冲信号，具体包括：脉冲生成器132将帧同步信号延迟第一时间，以获得延迟信号；并将延迟信号取反后，与帧同步信号进行与操作，得到所述脉冲信号；其中，第一时间为第三时钟域的单时钟脉冲宽度。
在一些实施例中，步骤S30具体包括：接收器121在第四时钟域下接收原始视频数据；写内存控制器122在第五时钟域下将原始视频数据写入第二存储器200；读内存控制器123在所述第五时钟域下读取所述存储器中的原始视频数据，并在第二时钟域下将原始视频数据发送至处理模块140。
利用视频数据处理装置100进行数据处理的过程参见上文描述，这里不再赘述。
图7为本公开的一些实施例中提供的显示系统的示意图，该显示系统可以为监视器系统、计算机、智能手机等终端设备。如图7所示，显示系统包括：显示模组400、系统芯片300和上述视频数据处理装置100。
其中，系统芯片300配置为，响应于画质调整指令，输出相应的画质调整参数。
显示模组400配置为，响应于视频数据处理装置100输出的目标视频数据进行显示。其中，显示模组400包括显示面板和驱动电路，驱动电路配置为根据目标视频数据为显示面板提供驱动信号，以控制显示面板进行显示。
图8为本公开的一些实施例中提供的显示系统的显示过程示意图，如图8所示，该显示过程包括：
当系统芯片300接收到画质调整指令时，进行步骤S1a：系统芯片300向视频数据处理装置100发送画质调整参数。
S1b、视频数据处理装置100的第一获取模块110接收到画质调整参数后，判断画质调整参数是否满足预设条件，若满足，则进行步骤S1c；否则，向系统芯片300发送数据请求指令，从而再次执行步骤S1a。
S1c、将画质调整参数输出至存储模块130，以使存储模块130对画质调整参数进行缓存。
S1d、当帧同步信号开始达到有效状态时，存储模块130将缓存的画质调整参数发送至处理模块140。
S1e、处理模块140根据接收到的画质调整参数对其内部原来存储的参数进行更新。
另外，视频源向视频数据处理装置100发送原始视频数据，从而使视频数据处理模块140执行步骤S2a至步骤S3。
S2a、视频数据处理模块140的写内存控制器122将接收到的原始视频数据向写入第二内存器。
S2b、视频数据处理模块140的读内存控制器123从第二内存器中读出原始视频数据。
S2c、读内存控制器123响应于有效数据选通信号，将原始视频数据发送至处理模块140。
S3、处理模块140当前存储的画质调整参数对原始视频数据进行处理，得到目标视频数据。
S4、显示模组根据目标视频数据进行显示。
其中，当系统芯片接收到画质调整指令时，则步骤S3中“当前存储的画质调整参数”即为系统芯片根据画质调整指令所发出的画质调整参数；当系统芯片未接收到画质调整指令时，则处理模块140保持其存储的画质调整参数不变，此时，视频源仍可以发送原始视频数据，此时，处理模块140可以根据未被更新的画质调整参数进行处理。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (17)

  1. 一种视频数据处理装置，包括：第一获取模块、第二获取模块、存储模块和处理模块，其中，
    所述第一获取模块配置为，响应于接收到的画质调整参数，判断所述画质调整参数是否满足预设条件，当所述画质调整参数满足预设条件时，将所述画质调整参数发送至所述存储模块；
    所述存储模块配置为，对所述画质调整参数进行缓存，并响应于帧同步信号的控制，将所述画质调整参数发送至所述处理模块；
    所述第二获取模块配置为，获取原始视频数据，并响应于有效数据选通信号，将所述原始视频数据发送至所述处理模块；其中，所述画质调整参数的传输时间段与所述原始视频数据的传输时间段无交叠；
    所述处理模块配置为，根据所述画质调整参数对所述原始视频数据进行数据处理，生成目标视频数据。
  2. 根据权利要求1所述的装置，其中，所述第一获取模块包括：接收子模块和校验子模块，其中，
    所述接收子模块配置为，接收系统芯片所发送的所述画质调整参数；
    所述校验子模块配置为，判断所述画质调整参数是否满足预设条件，当所述画质调整参数满足预设条件时，控制所述接收子模块将所述画质调整参数发送至所述存储模块；当所述画质调整参数不满足预设条件时，向所述系统芯片发送数据请求信号，以使所述系统芯片重新发送画质调整参数。
  3. 根据权利要求1或2所述的装置，其中，所述画质调整参数为串行数据，该串行数据包括依次排列的：第一关键字、至少一个有效 数据、第二关键字和校验值；其中，所述校验值是对所述第一关键字、所述第二关键字以及二者之间的有效数据进行第一运算后得到的；
    所述校验子模块具体被配置为，对接收到的画质调整参数中第一关键字、第二关键字、所述第一关键字与所述第二关键字之间的有效数据、以及校验值进行第二运算，并将所述第二运算的结果与目标值对比，当所述第二运算的结果与所述目标值相等时，确定所述画质调整参数满足预设条件；否则，确定所述画质调整参数不满足预设条件。
  4. 根据权利要求3所述的装置，其中，所述第一运算包括异或运算，所述第二运算包括异或运算。
  5. 根据权利要求1至4中任意一项所述的装置，其中，所述第一获取模块在第一时钟域下接收所述画质调整参数；
    所述装置还包括：时序产生模块，配置为在第二时钟域下产生所述帧同步信号和所述有效数据选通信号；其中，所述帧同步信号的有效状态起始时刻与所述有效数据选通信号的有效状态起始时刻之间具有预设时间间隔，所述第二时钟域的时钟频率大于所述第一时钟域的时钟频率；
    其中，所述存储模块具体配置为，对所述画质调整参数进行缓存，并从帧同步信号的有效状态起始时刻开始，在第三时钟域下将所述画质调整参数发送至所述处理模块，其中，所述第三时钟域的时钟频率大于所述第二时钟域的时钟频率。
  6. 根据权利要求5所述的装置，其中，所述存储模块包括：脉冲生成器和第一存储器；其中，
    所述第一存储器配置为，存储所述画质调整参数；
    所述脉冲生成器配置为，在第三时钟域下生成脉冲信号，所述脉冲信号用于控制所述第一存储器将所述画质调整参数输出至所述处理模块；其中，所述脉冲信号的频率与所述帧同步信号的频率相同，所述脉冲信号的上升沿时刻与所述帧同步信号的有效状态起始时刻相同。
  7. 根据权利要求5所述的装置，其中，所述脉冲生成器包括：第一生成单元和第二生成单元，其中，
    所述第一生成单元配置为，将所述帧同步信号延迟第一时间，以获得延迟信号；其中，所述第一时间为所述第三时钟域的单时钟脉冲宽度；
    所述第二生成单元配置为，将所述延迟信号取反后，与所述帧同步信号进行与操作，得到所述脉冲信号。
  8. 根据权利要求5所述的装置，其中，所述第二获取模块包括：接收器、写内存控制器和读内存控制器；
    所述接收器配置为，在第四时钟域下接收所述原始视频数据；
    所述写内存控制器配置为，在第五时钟域下将所述原始视频数据写入第二存储器；
    所述读内存控制器配置为，在所述第五时钟域下读取所述第二存储器中的原始视频数据，并在所述第二时钟域下将所述原始视频数据发送至所述处理模块。
  9. 一种显示系统，包括：显示模组、系统芯片和权利要求1至8中任意一项所述的视频数据处理装置，
    所述系统芯片配置为，响应于画质调整指令，输出相应的画质调整参数；
    所述显示模组配置为，响应于所述显示驱动装置输出的目标视频数据进行显示。
  10. 一种应用于视频数据处理装置的视频数据处理方法，其中，所述视频数据处理装置包括：第一获取模块、第二获取模块、存储模块和处理模块，所述方法包括：
    所述第一获取模块响应于接收到的画质调整参数，判断所述画质调整参数是否满足预设条件，当所述画质调整参数满足预设条件时，将所述画质调整参数发送至所述存储模块；
    所述存储模块对所述画质调整参数进行缓存，并响应于帧同步信号的控制，将所述画质调整参数发送至所述处理模块；
    所述第二获取模块获取原始视频数据，并响应于有效数据选通信号，将所述原始视频数据发送至所述处理模块；其中，所述画质调整参数的传输时间段与所述原始视频数据的传输时间段无交叠；
    所述处理模块根据所述画质调整参数对所述原始视频数据进行数据处理，生成目标视频数据。
  11. 根据权利要求10所述的方法，其中，所述第一获取模块包括：接收子模块和校验子模块，
    所述第一获取模块响应于接收到的画质调整参数，判断所述画质调整参数是否满足预设条件，当所述画质调整参数满足预设条件时，将所述画质调整参数发送至所述存储模块，具体包括：
    所述接收子模块接收系统芯片所发送的画质调整参数；
    所述校验子模块判断所述画质调整参数是否满足预设条件，当所述画质调整参数满足预设条件时，控制所述接收子模块将所述画质调整参数输出至所述存储模块；当所述画质调整参数不满足预设条件时， 向所述系统芯片发送数据请求信号，以使所述系统芯片重新发送画质调整参数。
  12. 根据权利要求11所述的方法，其中，所述画质调整参数为串行数据，该串行数据包括依次排列的：第一关键字、至少一个有效数据、第二关键字和校验值；其中，所述校验值是对所述第一关键字、所述第二关键字以及二者之间的有效数据进行第一运算后得到的；
    所述校验子模块判断所述画质调整参数是否满足预设条件，具体包括：
    所述校验子模块对接收到的画质调整参数中第一关键字、第二关键字、所述第一关键字与所述第二关键字之间的有效数据、以及校验值进行第二运算，并将所述第二运算的结果与目标值对比，当所述第二运算的结果与所述目标值相等时，确定所述画质调整参数满足预设条件；否则，确定所述画质调整参数不满足预设条件。
  13. 根据权利要求12所述的方法，其中，所述第一运算包括异或运算，所述第二运算包括异或运算。
  14. 根据权利要求10至13中任意一项所述的方法，其中，所述第一获取模块在第一时钟域下接收所述画质调整参数；所述装置还包括：时序产生模块；
    其中，所述帧同步信号和所述有效数据选通信号均由所述时序产生模块在第二时钟域下产生，所述帧同步信号的有效状态起始时刻与所述有效数据选通信号的有效状态起始时刻之间具有预设时间间隔，所述第二时钟域的时钟频率大于所述第一时钟域的时钟频率；
    其中，所述存储模块对所述画质调整参数进行缓存，并从帧同步 信号的有效状态起始时刻开始，在第三时钟域下将所述画质调整参数发送至所述处理模块，其中，所述第三时钟域的时钟频率大于所述第二时钟域的时钟频率。
  15. 根据权利要求14所述的方法，其中，所述存储模块包括：脉冲生成器和第一存储器；
    所述存储模块对所述画质调整参数进行缓存，并从帧同步信号的有效状态起始时刻开始，在第三时钟域下将所述画质调整参数发送至所述处理模块，具体包括：
    所述第一存储器存储所述画质调整参数；
    所述脉冲生成器在第三时钟域下生成脉冲信号，所述脉冲信号用于控制所述第一存储器将所述画质调整参数输出至所述处理模块；其中，所述脉冲信号的频率与所述帧同步信号的频率相同，所述脉冲信号的上升沿时刻与所述帧同步信号的有效状态起始时刻相同。
  16. 根据权利要求15所述的方法，其中，所述脉冲生成器在第三时钟域下生成脉冲信号，具体包括：
    所述脉冲生成器将所述帧同步信号延迟第一时间，以获得延迟信号；并将所述延迟信号取反后，与所述帧同步信号进行与操作，得到所述脉冲信号；其中，所述第一时间为所述第三时钟域的单时钟脉冲宽度。
  17. 根据权利要求10至13中任意一项所述的方法，其中，所述第二获取模块包括：接收器、写内存控制器和读内存控制器；
    所述接收器在第四时钟域下接收所述原始视频数据；
    所述写内存控制器在第五时钟域下将所述原始视频数据写入第二 存储器；
    所述读内存控制器在所述第五时钟域下读取所述第二存储器中的原始视频数据，并在所述第二时钟域下将所述原始视频数据发送至所述处理模块。
PCT/CN2021/090542 2021-04-28 2021-04-28 视频数据处理装置及方法、显示系统 WO2022226835A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/CN2021/090542 WO2022226835A1 (zh) 2021-04-28 2021-04-28 视频数据处理装置及方法、显示系统
CN202180000961.0A CN115606171A (zh) 2021-04-28 2021-04-28 视频数据处理装置及方法、显示系统
US17/638,266 US12045965B2 (en) 2021-04-28 2021-04-28 Device and method for processing video data, and display system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/090542 WO2022226835A1 (zh) 2021-04-28 2021-04-28 视频数据处理装置及方法、显示系统

Publications (1)

Publication Number Publication Date
WO2022226835A1 true WO2022226835A1 (zh) 2022-11-03

Family

ID=83847672

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/090542 WO2022226835A1 (zh) 2021-04-28 2021-04-28 视频数据处理装置及方法、显示系统

Country Status (3)

Country Link
US (1) US12045965B2 (zh)
CN (1) CN115606171A (zh)
WO (1) WO2022226835A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116721740A (zh) * 2023-05-12 2023-09-08 天津御锦人工智能医疗科技有限公司 一种智能医疗显示系统

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1744722A (zh) * 2004-09-02 2006-03-08 上海乐金广电电子有限公司 数字画质调节装置及其方法
CN1753076A (zh) * 2005-11-04 2006-03-29 友达光电股份有限公司 时序控制方法和装置及其应用的液晶显示器
CN104954769A (zh) * 2015-06-15 2015-09-30 中国科学院自动化研究所 一种浸入式超高清视频处理系统及方法
US20150296193A1 (en) * 2012-05-31 2015-10-15 Apple Inc. Systems and methods for rgb image processing
CN109194928A (zh) * 2018-10-20 2019-01-11 中国航空工业集团公司洛阳电光设备研究所 一种任意分辨率Camera link视频转SDI视频的方法及装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101753261B1 (ko) * 2016-03-21 2017-07-03 박은홍 촬영 시스템 및 그 영상품질 동기화 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1744722A (zh) * 2004-09-02 2006-03-08 上海乐金广电电子有限公司 数字画质调节装置及其方法
CN1753076A (zh) * 2005-11-04 2006-03-29 友达光电股份有限公司 时序控制方法和装置及其应用的液晶显示器
US20150296193A1 (en) * 2012-05-31 2015-10-15 Apple Inc. Systems and methods for rgb image processing
CN104954769A (zh) * 2015-06-15 2015-09-30 中国科学院自动化研究所 一种浸入式超高清视频处理系统及方法
CN109194928A (zh) * 2018-10-20 2019-01-11 中国航空工业集团公司洛阳电光设备研究所 一种任意分辨率Camera link视频转SDI视频的方法及装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116721740A (zh) * 2023-05-12 2023-09-08 天津御锦人工智能医疗科技有限公司 一种智能医疗显示系统

Also Published As

Publication number Publication date
CN115606171A (zh) 2023-01-13
US12045965B2 (en) 2024-07-23
US20240054625A1 (en) 2024-02-15

Similar Documents

Publication Publication Date Title
US10049642B2 (en) Sending frames using adjustable vertical blanking intervals
KR101727792B1 (ko) 수신장치, 비디오 리프레쉬 주파수의 제어 방법, 장치 및 시스템
US9607542B2 (en) Display panel driving method, driving device and display device
WO2020249019A1 (zh) 驱动电路控制方法及装置和驱动电路
US20210056938A1 (en) Switching method and switching device for display channel, dipslay driving device and display device
US9460649B2 (en) Timing controller for image display and associated control method
WO2022226835A1 (zh) 视频数据处理装置及方法、显示系统
US8305368B2 (en) Method for determining an optimum skew and adjusting a clock phase of a pixel clock signal and data driver utilizing the same
WO2014110856A1 (zh) 一种液晶拼接屏及其校正方法和一种液晶显示装置
US11955051B2 (en) Receiver of display driver and operating method thereof
CN113794850B (zh) 时序修正方法、装置、电子设备及可读存储介质
WO2020249010A1 (zh) 时序控制器控制方法和时序控制器
CN114257772A (zh) 数据传输的调整方法、装置、计算机设备及可读存储介质
TWI410949B (zh) 資料驅動器與用以決定資料驅動器之最佳偏移之方法
CN106952600B (zh) 时序控制器及其信号输出方法
KR101957970B1 (ko) 표시장치와 그 제어 방법
US9262998B2 (en) Display system and data transmission method thereof
JP2019532330A (ja) 駆動制御回路及びその駆動方法、表示装置
JP2601125B2 (ja) 液晶パネル駆動装置
CN114173054A (zh) 多帧频拼接视频源显示控制方法及其系统和led显示系统
WO2021223270A1 (zh) 显示装置和应用于显示装置的充电控制方法
TW202105982A (zh) 接收裝置、影像紀錄系統以及降低影像紀錄系統之影像延遲的方法
US20220301468A1 (en) Control method of display apparatus, display apparatus, and computer-readable storage medium
CN114257739B (zh) 视频数据速率调整方法和装置
US11631363B2 (en) Display driver and operating method thereof

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 17638266

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21938320

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM1205A DATED 26.03.2024)