WO2023005628A1 - 移位寄存器单元及其驱动方法、栅极驱动电路及其驱动方法 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路及其驱动方法 Download PDF

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WO2023005628A1
WO2023005628A1 PCT/CN2022/104151 CN2022104151W WO2023005628A1 WO 2023005628 A1 WO2023005628 A1 WO 2023005628A1 CN 2022104151 W CN2022104151 W CN 2022104151W WO 2023005628 A1 WO2023005628 A1 WO 2023005628A1
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pull
transistor
output
node
clock signal
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PCT/CN2022/104151
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English (en)
French (fr)
Inventor
杨涛
缪应蒙
陈东川
廖燕平
刘建涛
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Publication of WO2023005628A1 publication Critical patent/WO2023005628A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register unit and its driving method, and a gate driving circuit and its driving method.
  • At least one gate driving circuit is generally included.
  • the gate driving circuit can realize the scanning of each sub-pixel row of the display device, so as to charge each sub-pixel in the sub-pixel row according to the image data corresponding to the image to be displayed, so as to realize image display.
  • a shift register unit including a pull-up circuit, a control circuit, a cascade circuit and N output circuits.
  • the pull-up circuit is connected to the input signal terminal of the shift register unit, the total pull-up node and the pull-down node, and the pull-up circuit is configured to provide the signal of the input signal terminal to the total pull-up node, and in the The potential of the total pull-up node is pulled down under the control of the potential of the pull-down node.
  • a control circuit is connected to the overall pull-up node and the pull-down node, the control circuit being configured to control the potential of the pull-down node according to the potential of the overall pull-up node.
  • the cascade circuit is connected to the total pull-up node, the pull-down node, and the cascade output end and the control clock signal end of the shift register unit, and the cascade circuit is configured to be on the total pull-up node
  • the signal of the control clock signal terminal is provided to the cascade output terminal under the control of the potential, and the potential of the cascade output terminal is pulled down under the control of the potential of the pull-down node.
  • N output circuits are respectively connected to the input signal end, the pull-down node, and the N output clock signal ends, N sub-pull-up nodes, and N output signal ends of the shift register unit, wherein the nth output The circuit is connected to the input signal terminal, the pull-down node, the nth output signal terminal and the nth pull-up node, and is configured to input the signal of the input signal terminal to the nth pull-up node, providing the signal of the nth output clock signal terminal to the nth output signal terminal under the control of the potential of the nth pull-up node, and pulling down the potential of the nth output signal terminal under the control of the potential of the pull-down node,
  • N is an integer greater than 1
  • n is an integer and 1 ⁇ n ⁇ N.
  • the nth output circuit includes: an input subcircuit, an output subcircuit and a pull-down subcircuit.
  • the input subcircuit is connected to the input signal terminal and the nth pull-up node, and is configured to provide a signal of the input signal terminal to the nth pull-up node.
  • the output subcircuit is connected to the n-th pull-up node, the n-th output clock signal terminal, and the n-th output signal end, and is configured to, under the control of the potential of the n-th pull-up node,
  • the signal of the nth output clock signal terminal is provided to the nth output signal terminal.
  • the pull-down subcircuit is connected to the pull-down node, and is configured to pull down the potential of the nth pull-up node and the nth output signal terminal under the control of the potential of the pull-down node.
  • the pull-down node includes a first pull-down node and a second pull-down node
  • the pull-down sub-circuit includes a first pull-down sub-circuit and a second pull-down sub-circuit.
  • the first pull-down sub-circuit is connected to the first pull-down node, and is configured to pull down the n-th sub-pull-up node and the n-th pull-up node under the control of the potential of the first pull-down node.
  • the potential of at least one of the signal terminals is output.
  • the second pull-down sub-circuit is connected to the second pull-down node, and is configured to pull down the n-th pull-up node and the n-th output signal terminal under the control of the potential of the second pull-down node at least one of the potentials.
  • control circuit includes: a first control subcircuit and a second control subcircuit.
  • a first control subcircuit is connected to the overall pull-up node and the first pull-down node, and is configured to control the potential of the first pull-down node according to the potential of the overall pull-up node.
  • a second control subcircuit connected to the general pull-up node and the second pull-down node, and configured to control the potential of the second pull-down node according to the potential of the general pull-up node.
  • the nth output circuit further includes: a reset subcircuit, connected to the nth pull-up node and the reset signal terminal and the reference signal terminal of the shift register unit, and configured to Under the control of the signal of the reset signal terminal, the potential of the reference signal terminal is used to reset the nth pull-up node.
  • the input subcircuit is further connected to a power signal terminal, and is configured to provide the potential of the power signal terminal to the nth pull-up node under the control of the signal of the input signal terminal.
  • a first output clock signal terminal among the N output clock signal terminals is connected to the control clock signal terminal.
  • the input sub-circuit includes: a first transistor, the gate of the first transistor and the first pole of the first transistor are connected to the input signal terminal, and the first transistor of the first transistor The diode is connected to the nth pull-up node.
  • the input sub-circuit includes: a first transistor, the gate of the first transistor is connected to the input signal terminal, the first pole of the first transistor is connected to the power signal terminal, The second pole of the first transistor is connected to the nth pull-up node.
  • the output subcircuit includes a second transistor and a first capacitor.
  • the gate of the second transistor is connected to the nth pull-up node, the first pole of the second transistor is connected to the nth output clock signal terminal, and the second pole of the second transistor is connected to The nth output signal terminal.
  • a first capacitor, the first end of the first capacitor is connected to the nth pull-up node, and the second end of the first capacitor is connected to the nth output signal end.
  • the pull-down sub-circuit includes: a third transistor and a fourth transistor.
  • the gate of the third transistor is connected to the pull-down node, the first pole of the third transistor is connected to the first reference signal terminal of the shift register unit, and the second pole of the third transistor is connected to The nth pull-up node.
  • the gate of the fourth transistor is connected to the pull-down node, the first pole of the fourth transistor is connected to the second reference signal terminal of the shift register unit, and the second pole of the fourth transistor is connected to The nth output signal terminal.
  • the first pull-down sub-circuit includes a third transistor and a fourth transistor, the gate of the third transistor is connected to the first pull-down node, and the first pole of the third transistor connected to the first reference signal terminal of the shift register unit, the second pole of the third transistor is connected to the nth pull-up node, and the gate of the fourth transistor is connected to the first lower A pull node, the first pole of the fourth transistor is connected to the second reference signal terminal of the shift register unit, and the second pole of the fourth transistor is connected to the nth output signal terminal.
  • the second pull-down sub-circuit includes a fifth transistor and a sixth transistor, the gate of the fifth transistor is connected to the second pull-down node, and the first pole of the fifth transistor is connected to the first reference signal terminal, the second pole of the fifth transistor is connected to the nth pull-up node, the gate of the sixth transistor is connected to the second pull-down node, and the first pole of the sixth transistor is connected to The second reference signal terminal and the second pole of the sixth transistor are connected to the nth output signal terminal.
  • the reset subcircuit includes a seventh transistor, the gate of the seventh transistor is connected to the reset signal terminal, and the first electrode of the seventh transistor is connected to the reference signal terminal, so The second pole of the seventh transistor is connected to the nth pull-up node.
  • the control circuit includes: an eighth transistor and a ninth transistor.
  • An eighth transistor, the gate of the eighth transistor and the first pole of the eighth transistor are connected to the power signal terminal of the shift register unit, and the second pole of the eighth transistor is connected to the pull-down node .
  • a ninth transistor, the gate of the ninth transistor is connected to the general pull-up node, the first pole of the ninth transistor is connected to the reference signal terminal of the shift register unit, and the first pole of the ninth transistor is connected to the reference signal terminal of the shift register unit.
  • a diode is connected to the pull-down node.
  • the first control subcircuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor, the gate of the tenth transistor and the first gate of the tenth transistor pole is connected to the power signal terminal of the shift register unit, the second pole of the tenth transistor is connected to the gate of the eleventh transistor, and the first pole of the eleventh transistor is connected to the power supply Signal terminal, the second pole of the eleventh transistor is connected to the first pull-down node, the gate of the twelfth transistor is connected to the general pull-up node, the first of the twelfth transistor pole is connected to the reference signal terminal of the shift register unit, the second pole of the twelfth transistor is connected to the gate of the eleventh transistor, and the gate of the thirteenth transistor is connected to the total A pull-up node, the first pole of the thirteenth transistor is connected to the reference signal terminal, and the second pole of the thirteenth transistor is connected to the first pull-down node.
  • the second control sub-circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a seventeenth transistor, the gate of the fourteenth transistor and the first pole of the fourteenth transistor are connected to The power signal terminal, the second pole of the fourteenth transistor is connected to the gate of the fifteenth transistor, the first pole of the fifteenth transistor is connected to the power signal terminal, and the tenth transistor is connected to the gate of the fifteenth transistor.
  • the second pole of the fifth transistor is connected to the second pull-down node
  • the gate of the sixteenth transistor is connected to the overall pull-up node
  • the first pole of the sixteenth transistor is connected to the reference signal terminal
  • the second pole of the sixteenth transistor is connected to the gate of the fifteenth transistor
  • the gate of the seventeenth transistor is connected to the general pull-up node
  • the first of the seventeenth transistor The pole is connected to the reference signal terminal
  • the second pole of the seventeenth transistor is connected to the second pull-down node.
  • the pull-up circuit includes: an eighteenth transistor, a nineteenth transistor and a twentieth transistor.
  • the gate of the eighteenth transistor and the first pole of the eighteenth transistor are connected to the input signal terminal, and the second pole of the eighteenth transistor is connected to the general pull-up node.
  • a nineteenth transistor, the gate of the nineteenth transistor is connected to the pull-down node, the first pole of the nineteenth transistor is connected to the reference signal terminal of the shift register unit, and the nineteenth transistor The second pole of is connected to the general pull-up node.
  • the twentieth transistor, the gate of the twentieth transistor is connected to the reset signal end of the shift register unit, the first pole of the twentieth transistor is connected to the reference signal end, and the twentieth transistor is connected to the reference signal end.
  • the second pole of the transistor is connected to the overall pull-up node.
  • the pull-down node includes a first pull-down node and a second pull-down node
  • the pull-up circuit further includes a twenty-first transistor.
  • the gate of the nineteenth transistor is connected to the first pull-down node
  • the gate of the twenty-first transistor is connected to the second pull-down node
  • the first pole of the twenty-first transistor is connected to To the reference signal terminal
  • the second pole of the twenty-first transistor is connected to the overall pull-up node.
  • the cascade circuit includes: a twenty-second transistor, a twenty-third transistor and a second capacitor.
  • the gate of the twenty-second transistor is connected to the general pull-up node, the first pole of the twenty-second transistor is connected to the control clock signal terminal, and the second pole of the twenty-second transistor Connect to the cascade output.
  • a twenty-third transistor, the gate of the twenty-third transistor is connected to the pull-down node, the first pole of the twenty-third transistor is connected to the reference signal terminal of the shift register unit, and the first pole of the twenty-third transistor is connected to the reference signal terminal of the shift register unit.
  • the second pole of the twenty-three transistors is connected to the cascaded output terminal.
  • a second capacitor, the first terminal of the second capacitor is connected to the gate of the twenty-second transistor, and the second terminal of the second capacitor is connected to the cascaded output terminal.
  • the pull-down node includes a first pull-down node and a second pull-down node
  • the cascade circuit further includes a twenty-fourth transistor.
  • the gate of the twenty-fourth transistor is connected to the first pull-down node
  • the gate of the twenty-fourth transistor is connected to the second pull-down node
  • the first pole of the twenty-fourth transistor connected to the reference signal terminal
  • the second pole of the twenty-fourth transistor is connected to the cascaded output terminal.
  • the shift register unit further includes a general reset circuit.
  • the total reset circuit includes a twenty-fifth transistor, the gate of the twenty-fifth transistor is connected to the total reset terminal of the shift register unit, and the first pole of the twenty-fifth transistor is connected to the The reference signal end of the shift register unit, the second pole of the twenty-fifth transistor is connected to the general pull-up node.
  • N 4 or 2.
  • a gate driving circuit comprising M stages of cascaded shift register units, where the shift register units are the above shift register units.
  • the input signal end of the mth stage shift register unit is connected to the cascaded output end of the m-1st stage shift register unit, and the reset signal end of the mth stage shift register unit is connected to the m+2th stage shift register unit.
  • Cascade output terminals are connected, wherein M is an integer greater than 1, m is an integer and 1 ⁇ m ⁇ M-1.
  • the M stages of cascaded shift register units are connected to K clock signal lines, wherein K is an even number greater than or equal to 2N.
  • the M-level cascaded shift register units are divided into multiple groups, and each group includes a 3-level cascaded first shift register unit, a second shift register unit and the third shift register unit, wherein the N output clock signal terminals of the first shift register unit are connected in one-to-one correspondence with the first clock signal line to the fourth clock signal line, and the N output clock signal terminals of the second shift register unit
  • the output clock signal terminals are connected to the fifth clock signal line to the eighth clock signal line in a one-to-one correspondence
  • the N output clock signal terminals of the third shift register unit are connected to the ninth to the twelfth clock signal lines in a one-to-one correspondence .
  • the first output clock signal terminal among the N output clock signal terminals of each shift register unit is connected to the control clock signal terminal of the shift register unit.
  • the M-level cascaded shift register units are divided into multiple groups, and each group includes 2-level cascaded first shift register units and second shift register units, wherein the N output clocks of the first shift register units The signal end is connected to the first output clock signal line and the second output clock signal line in one-to-one correspondence, the control clock signal end of the first shift register unit is connected to the first control clock signal line, and the N of the second shift register unit The two output clock signal terminals are connected to the third clock signal line and the fourth clock signal line in one-to-one correspondence, and the control clock signal terminal of the second shift register unit is connected to the second control clock signal line.
  • a driving method of the above-mentioned shift register unit includes: in the first period, the pull-up circuit supplies the first level of the input signal terminal to the general pull-up node, and the nth output circuit among the N output circuits inputs the first level of the input signal terminal to all The nth sub-pull-up node; in the second period, the cascade circuit provides the signal of the control clock signal terminal to the cascade output terminal under the control of the potential of the total pull-up node, and the nth output circuit in the N The output circuit provides the signal of the nth output clock signal terminal to the nth output signal terminal under the control of the potential of the nth pull-up node; and, in the third period, the pull-up circuit provides the second level of the input signal terminal to The total pull-up node, the potential of the pull-up node enables the control circuit to control the pull-down node to a first level, the potential of the pull-down node causes the cascade circuit to pull
  • another method for driving the above-mentioned shift register unit includes: in the first mode, applying K first clock signals that are sequentially shifted row by row to the K clock signal lines, so that the M-stage shift register units of the gate drive circuit generate sequential shift row by row a plurality of first output signals; in the second mode, K second clock signals that are sequentially shifted by k rows are applied to the K clock signal lines, so that the M-stage shift register unit of the gate drive circuit generates A plurality of second output signals sequentially shifted row by k, wherein the frequency of the K second clock signals is k times that of the K first clock signals, where k is an integer less than or equal to K.
  • a driving method of the above-mentioned gate driving circuit includes: in a first mode, applying a plurality of first output clock signals sequentially shifted row by row to the plurality of output clock signal lines, Make the M-level shift register unit of the gate drive circuit generate a plurality of first output signals that are sequentially shifted row by row, wherein the N output circuits of each level of shift register unit generate output signals; in the second mode, to Some of the output clock signal lines in the plurality of output clock signal lines apply a plurality of second output clock signals, so that the M-stage shift register unit of the gate drive circuit generates a plurality of second output signals shifted sequentially, wherein each At least one output circuit among the N output circuits of the stage shift register does not generate an output signal.
  • the K clock signal lines include a first control clock signal line, a second control clock signal line, a first output clock signal line, a second output clock signal line, The third output clock signal line and the fourth output clock signal line.
  • the first control clock signal is applied to the first control clock signal line
  • the second control clock signal is applied to the second control clock signal line
  • the clock signal line, the third output clock signal line and the fourth output clock signal line respectively apply four first output clock signals shifted sequentially, so that the 2 output circuits of each stage of shift register unit generate output signals
  • the first control clock signal is applied to the first control clock signal line
  • the second control clock signal is applied to the second control clock signal line, and the first output clock signal line
  • the odd-numbered or even-numbered clock signal lines in the second output clock signal line, the third output clock signal line and the fourth output clock signal line are respectively applied with two second output clock signals shifted sequentially, so that each stage of shift register unit
  • the period of the second output clock signal is equal to the period of the first output clock signal, and the duty cycle of the second output clock signal is greater than the duty cycle of the first output clock signal .
  • Figure 1 is a schematic block diagram of a shift register unit according to some embodiments.
  • Figure 2 is a circuit diagram of a shift register unit according to some embodiments.
  • Figure 3 is a circuit diagram of another shift register cell according to some embodiments.
  • FIG. 4 is a circuit diagram of yet another shift register unit according to some embodiments.
  • FIG. 5 is a circuit diagram of yet another shift register unit according to some embodiments.
  • FIG. 6 is a schematic structural diagram of a gate driving circuit according to some embodiments.
  • FIG. 7 is a schematic structural diagram of another gate driving circuit according to some embodiments.
  • Fig. 8 is a schematic structural diagram of another gate driving circuit according to some embodiments.
  • FIG. 9 is a signal timing diagram of a driving method of a shift register unit according to some embodiments.
  • FIG. 10 is a signal timing diagram in a first mode of a driving method of a gate driving circuit according to some embodiments.
  • FIG. 11 is a signal timing diagram in a second mode of a driving method of a gate driving circuit according to some embodiments.
  • FIG. 12 is a signal timing diagram in the first mode of another gate driving circuit driving method according to some embodiments.
  • 13 is a signal timing diagram in the second mode of another gate driving circuit driving method according to some embodiments.
  • FIG. 14 is a timing diagram of signals in the first mode and the second mode of still another driving method of the gate driving circuit according to some embodiments.
  • first means for describing various components, components, elements, regions, layers and/or sections
  • these components, components, elements, regions, layers and/or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, component, element, region, layer and/or section from another.
  • a first component, first member, first element, first region, first layer, and/or first portion discussed below could be termed a second component, second member, second element, second region , the second layer and/or the second portion, without departing from the teachings of the present disclosure.
  • connection to may refer to two components being directly connected, or may refer to two components being connected via one or more other components.
  • a display device generally includes a display panel and at least one gate driving circuit electrically connected to the display panel.
  • the gate driving circuit and the display panel can be manufactured independently, and the latter two can be connected together through, for example, a flexible printed circuit board.
  • the above-mentioned gate driving circuit can be directly manufactured on the substrate of the display panel, for example, in the peripheral area around the display area of the display panel.
  • This technology is also called GOA (Gate On Array) technology.
  • GOA Gate On Array
  • the number of shift register units required by the display device is relatively large, which will cause the frame of the display device The larger size will affect the aesthetics of the product.
  • the shift register unit 100 includes a pull-up circuit 10 , a control circuit 20 , a cascade circuit 30 and N output circuits 40 .
  • the pull-up circuit 10 is connected to the input signal terminal INPUT of the shift register unit 100, the total pull-up node PU and the pull-down node PD, and the pull-up circuit 10 is configured to provide the signal of the input signal terminal INPUT to the total pull-up node PU , and pull down the potential of the general pull-up node PU under the control of the potential of the pull-down node PD.
  • the control circuit 20 is connected to the total pull-up node PU and the pull-down node PD, and the control circuit 20 is configured to control the potential of the pull-down node PD according to the potential of the total pull-up node PU.
  • the cascade circuit 30 is connected to the total pull-up node PU, the pull-down node PD, the cascade output terminal OUT_C and the control clock signal terminal CLK_C of the shift register unit 100, and the cascade circuit 30 is configured to be connected to the total pull-up node PU. Under the control of the potential, the signal of the control clock signal terminal CLK_C is provided to the cascade output terminal OUT_C, and the potential of the cascade output terminal OUT_C is pulled down under the control of the potential of the pull-down node PD.
  • the N output circuits 40 are respectively connected to the input signal terminal INPUT, the pull-down node PD, and the N output clock signal terminals (for example, CLK_1 to CLK_N in FIG. 1 ) of the shift register unit 100, and N sub-pull-up nodes. (for example, PU_1 to PU_N in FIG. 1 ) and N output signal terminals (for example, OUT_1 to OUT_N in FIG. 1 ).
  • the nth output circuit 40 is connected to the input signal terminal INPUT, the pull-down node PD, the nth output signal terminal OUT_n, and the nth pull-up node PU_n, and is configured to input the signal of the input signal terminal INPUT to the nth branch.
  • N is an integer greater than 1
  • n is an integer and 1 ⁇ n ⁇ N.
  • 2 ⁇ N ⁇ 8, for example, N can be 2, 3, 4, 5 or 6.
  • Embodiments of the present disclosure adopt a structure in which N output circuits share one control circuit in the shift register unit, so that the shift register unit can replace multiple traditional shift register units to independently generate multiple output signals, compared to Compared with the traditional combination of multiple shift register units, it has a simpler circuit structure.
  • the N output circuits share one control circuit, that is, are controlled by the same potential of the pull-down node PD.
  • Each output circuit contains its own sub-pull-up node and can generate outputs independently of each other.
  • the shift register unit of the embodiment of the present disclosure can reduce the number of control circuits that need to be set, and has a simpler circuit structure, which is beneficial to reduce The bezel size of small display devices.
  • FIG. 2 is a circuit diagram of a shift register unit 200 according to some embodiments.
  • the shift register unit 200 includes a pull-up circuit 10 , a control circuit 20 , a cascade circuit 30 and N output circuits.
  • N may be 2, that is, the N output circuits include a first output circuit 40_1 and a second output circuit 40_2 (hereinafter collectively referred to as output circuits 40 ).
  • the first output circuit 40_1 and the second output circuit 40_2 share one control circuit 20 .
  • the shift register unit 200 may include a first output clock signal terminal CLK_1 and a second output clock signal terminal CLK_2, a first output signal terminal OUT_1 and a second output signal terminal OUT_2, a first pull-up node PU_1 and the second pull-up node PU_2.
  • each output circuit 40 includes an input subcircuit 401 , an output subcircuit 402 and a pull-down subcircuit 403 .
  • the input sub-circuit 401 is connected to the input signal terminal INPUT and the nth pull-up node PU_n, and is configured to provide a signal of the input signal terminal INPUT to the nth pull-up node PU_n.
  • the output sub-circuit 402 is connected to the nth pull-up node PU_n, the nth output clock signal terminal CLK_n, and the nth output signal terminal OUT_n, and is configured to be at the potential of the nth pull-up node PU_n Under the control of , the signal of the nth output clock signal terminal CLK_n is provided to the nth output signal terminal OUT_n.
  • the pull-down sub-circuit 403 is connected to the pull-down node PD, and is configured to pull down the potential of the nth pull-up node PU_n and the nth output signal terminal OUT_n under the control of the potential of the pull-down node PD.
  • the input sub-circuit 401 may include a first transistor M1 .
  • the gate of the first transistor M1 and the first pole of the first transistor M1 are connected to the input signal terminal INPUT, and the second pole of the first transistor M1 is connected to the first pull-up node PU_1 .
  • the output sub-circuit 402 may include a second transistor M2 and a first capacitor C1.
  • the gate of the second transistor M2 is connected to the first pull-up node PU_1, the first pole of the second transistor M2 is connected to the first output clock signal terminal CLK_1, and the second pole of the second transistor M2 is connected to the first output signal terminal OUT_1.
  • a first terminal of the first capacitor C1 is connected to the first sub-pull-up node PU_1 , and a second terminal of the first capacitor C1 is connected to the first output signal terminal OUT_1 .
  • the pull-down sub-circuit 403 may include a third transistor M3 and a fourth transistor M4.
  • the gate of the third transistor M3 is connected to the pull-down node PD, the first pole of the third transistor M3 is connected to the reference signal terminal (for example, the first reference signal terminal LVGL) of the shift register unit 200, and the third transistor M3
  • the second pole of is connected to the first sub-pull-up node PU_1.
  • the gate of the fourth transistor M4 is connected to the pull-down node PD, the first pole of the fourth transistor M4 is connected to the reference signal terminal (such as the second reference signal terminal VGL) of the shift register unit 200, the The second pole of the fourth transistor M4 is connected to the first output signal terminal OUT_1.
  • the second output circuit 40_2 has a structure similar to that of the second output circuit 40_1 , except that it is connected to the second pull-up node PU_2 , the second output clock signal terminal CLK_2 and the second output signal terminal OUT_2 . As shown in FIG. 2, in the second output circuit 40_2, the gate of the first transistor M1 and the first pole of the first transistor M1 are connected to the input signal terminal INPUT, and the second pole of the first transistor M1 is connected to the second branch Pull up node PU_2.
  • the gate of the second transistor M2 is connected to the second pull-up node PU_2, the first pole of the second transistor M2 is connected to the second output clock signal terminal CLK_2, and the second pole of the second transistor M2 is connected to the second output signal terminal OUT_2.
  • a first terminal of the first capacitor C1 is connected to the second pull-up node PU_2 , and a second terminal of the first capacitor C1 is connected to the second output signal terminal OUT_2 .
  • the gate of the third transistor M3 is connected to the pull-down node PD, the first pole of the third transistor M3 is connected to the first reference signal terminal LVGL, and the second pole of the third transistor M3 is connected to the second pull-up node PU_2.
  • the gate of the fourth transistor M4 is connected to the pull-down node PD, the first pole of the fourth transistor M4 is connected to the second reference signal terminal VGL, and the second pole of the fourth transistor M4 is connected to the second Output signal terminal OUT_2.
  • the control circuit 20 may include an eighth transistor M8 and a ninth transistor M9.
  • the gate and first pole of the eighth transistor M8 are connected to the power signal terminal VDD of the shift register unit 200 , and the second pole of the eighth transistor M8 is connected to the pull-down node PD.
  • the gate of the ninth transistor M9 is connected to the general pull-up node PU, and the first pole of the ninth transistor M9 is connected to the reference signal terminal (for example, the first reference signal terminal LVGL) of the shift register unit 200,
  • the second pole of the ninth transistor M9 is connected to the pull-down node PD.
  • the pull-up circuit 10 includes an eighteenth transistor M18, a nineteenth transistor M19, and a twentieth transistor M20.
  • the gate and first pole of the eighteenth transistor M18 are connected to the input signal terminal INPUT, and the second pole of the eighteenth transistor M18 is connected to the general pull-up node PU.
  • the gate of the nineteenth transistor M19 is connected to the pull-down node, and the first pole of the nineteenth transistor M19 is connected to the reference signal terminal (for example, the first reference signal terminal LVGL) of the shift register unit 200, so
  • the second pole of the nineteenth transistor M19 is connected to the overall pull-up node PU.
  • the gate of the twentieth transistor M20 is connected to the reset signal terminal RST_PU of the shift register unit, the first pole of the twentieth transistor M20 is connected to a reference signal terminal (for example, the first reference signal terminal LVGL), and the second The second pole of the ten-transistor M20 is connected to the overall pull-up node PU.
  • the cascade circuit 30 may include a twenty-second transistor M22, a twenty-third transistor M23 and a second capacitor C2.
  • the gate of the twenty-second transistor M22 is connected to the general pull-up node PU, the first pole of the twenty-second transistor M22 is connected to the control clock signal terminal CLK_C, and the second pole of the twenty-second transistor M22 is connected to to the cascade output OUT_C.
  • the gate of the twenty-third transistor M23 is connected to the pull-down node PD, and the first pole of the twenty-third transistor M23 is connected to the reference signal terminal (for example, the first reference signal terminal LVGL) of the shift register unit 100,
  • the second pole of the twenty-third transistor M23 is connected to the cascade output terminal OUT_C.
  • a first end of the second capacitor C2 is connected to the gate of the twenty-second transistor M22, and a second end of the second capacitor C2 is connected to the cascade output terminal OUT_C.
  • FIG. 3 is a circuit diagram of another shift register cell 300 according to some embodiments.
  • the circuit in FIG. 3 is similar to that in FIG. 2 , except that the pull-down nodes of the shift register unit include a first pull-down node PD_1 and a second pull-down node PD_2 .
  • the pull-down nodes of the shift register unit include a first pull-down node PD_1 and a second pull-down node PD_2 .
  • the pull-down sub-circuit of each output circuit 40_1 and 40_2 may include a first pull-down sub-circuit and a second pull-down sub-circuit.
  • the first pull-down sub-circuit includes a third transistor M3 and a fourth transistor M4.
  • the second pull-down sub-circuit includes a fifth transistor M5 and a sixth transistor M6. The structure of the output circuit will be described below by taking the first output circuit 40_1 as an example.
  • the first pull-down sub-circuit is connected to the first pull-down node PD_1, and is configured to pull down the first sub-pull-up subcircuit under the control of the potential of the first pull-down node PD_1 The potentials of the node PU_1 and the first output signal terminal OUT_1.
  • the first pull-down sub-circuit includes a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 is connected to the first pull-down node PD_1, the first pole of the third transistor M3 is connected to the first reference signal terminal LVGL, and the second pole of the third transistor M3 is connected to to the first sub-pull-up node PU_1.
  • the gate of the fourth transistor M4 is connected to the first pull-down node PD_1, the first pole of the fourth transistor M4 is connected to the second reference signal terminal VGL, and the second pole of the fourth transistor M4 is connected to to the first output signal terminal OUT_1.
  • the second pull-down sub-circuit is connected to the second pull-down node PD_2, and is configured to pull down the second sub-pull-up node PU_2 and the The potential of the second output signal terminal OUT_2.
  • the second pull-down sub-circuit includes a fifth transistor M5 and a sixth transistor M6.
  • the gate of the fifth transistor M5 is connected to the second pull-down node PD_2, the first pole of the fifth transistor M5 is connected to the first reference signal terminal LVGL, and the second pole of the fifth transistor M5 is connected to The first point is to pull up the node PU_1.
  • the gate of the sixth transistor M6 is connected to the second pull-down node PD_2, the first pole of the sixth transistor M6 is connected to the second reference signal terminal VGL, and the second pole of the sixth transistor M6 is connected to The first output signal terminal OUT_1.
  • the pull-down subcircuit of the second output circuit 40_2 has a structure similar to that of the first output circuit 40_1 , which will not be repeated here.
  • each output circuit 40_1 and 40_2 may further include a reset subcircuit.
  • the reset subcircuit may include a seventh transistor M7. Taking the first output circuit 40_1 as an example, the gate of the seventh transistor M7 is connected to the reset signal terminal RST_PU, and the first pole of the seventh transistor M7 is connected to the reference signal terminal (for example, the first reference signal terminal LVGL ), the second pole of the seventh transistor M7 is connected to the first sub-pull-up node PU_1.
  • the reset subcircuit of the second output circuit 40_2 has a similar structure, which will not be repeated here.
  • the control circuit 20 may include a first control subcircuit 201 and a second control subcircuit 202 .
  • the first control subcircuit 201 is connected to the overall pull-up node PU and the first pull-down node PD_1, and is configured to control the voltage of the first pull-down node PD_1 according to the potential of the overall pull-up node PU. potential.
  • the second control subcircuit 202 is connected to the total pull-up node PU and the second pull-down node PD_2, and is configured to control the potential PD_2 of the second pull-down node according to the potential of the total pull-up node PU.
  • the first control sub-circuit 201 may include a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13.
  • the gate of the tenth transistor M10 and its first pole are connected to the power signal terminal (such as power signal terminal VDDO) of the shift register unit 300, and the second pole of the tenth transistor M10 is connected to the tenth transistor M10.
  • a gate of a transistor M11 is connected, and a first electrode of the eleventh transistor M11 is connected to the power signal terminal (for example, the power signal terminal VDDO).
  • the second pole of the eleventh transistor M11 is connected to the first pull-down node PD_1.
  • the gate of the twelfth transistor M12 is connected to the general pull-up node PU, and the first pole of the twelfth transistor M12 is connected to the reference signal terminal of the shift register unit 300 (for example, the first reference signal terminal LVGL), the second electrode of the twelfth transistor M12 is connected to the gate of the eleventh transistor M11.
  • the gate of the thirteenth transistor M13 is connected to the general pull-up node PU, the first pole of the thirteenth transistor M13 is connected to a reference signal terminal (such as a first reference signal terminal LVGL), and the thirteenth transistor M13
  • the second pole of M13 is connected to the first pull-down node PD_1.
  • the second control sub-circuit 202 may include a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16 and a seventeenth transistor M17.
  • the gate of the fourteenth transistor M14 and the first pole of the fourteenth transistor M14 are connected to a power signal terminal (such as a power signal terminal VDDE), and the second pole of the fourteenth transistor M14 is connected to the first pole of the fourteenth transistor M14.
  • Fifteen gate connections of transistor M15 A first pole of the fifteenth transistor M15 is connected to a power signal terminal (such as a power signal terminal VDDE), and a second pole of the fifteenth transistor M15 is connected to the second pull-down node PD_2.
  • the gate of the sixteenth transistor M16 is connected to the general pull-up node PU, the first pole of the sixteenth transistor M16 is connected to the reference signal terminal (for example, the first reference signal terminal LVGL), the The second pole of the sixteenth transistor M16 is connected to the gate of the fifteenth transistor M15.
  • the gate of the seventeenth transistor M17 is connected to the general pull-up node, the first pole of the seventeenth transistor M17 is connected to the reference signal terminal (for example, the first reference signal terminal LVGL), the first The second pole of the seventeenth transistor M17 is connected to the second pull-down node PD_2.
  • the N output circuits 40 can be divided into two independent parts, one of which is controlled by the first control subcircuit 201 The other part is controlled by the first control sub-circuit 201 to output the signal. Therefore, the gates of the sub-pixels in the corresponding two sub-pixel rows can be alternately turned on and off.
  • the cascade circuit 30 may include a twenty-fourth transistor M24 in addition to the twenty-second transistor M22 , the twenty-third transistor M23 and the second capacitor C2 .
  • the above descriptions for the twenty-second transistor M22 and the twenty-third transistor M23 are also applicable to FIG. 3 .
  • FIG. 3 In FIG. 3 ,
  • the gate of the twenty-fourth transistor M24 is connected to the first pull-down node PD_1, the gate of the twenty-fourth transistor M24 is connected to the second pull-down node PD_2, and the second A first pole of the fourteenth transistor M24 is connected to the reference signal terminal (for example, the first reference signal terminal LVGL), and a second pole of the twenty-fourth transistor M24 is connected to the cascade output terminal OUT_C.
  • the pull-up circuit 10 includes a twenty-first transistor M21 in addition to the eighteenth transistor M18 , the nineteenth transistor M19 and the twentieth transistor M20 .
  • the difference from FIG. 2 is that the gate of the nineteenth transistor M19 is connected to the first pull-down node PD_1, the gate of the twentieth transistor M20 is connected to the reset signal terminal RST_PU of the shift register unit 300, and the twenty A first pole of the transistor M20 is connected to a reference signal terminal (for example, a first reference signal terminal LVGL), and a second pole of the twentieth transistor M20 is connected to the general pull-up node PU.
  • the shift register unit 300 further includes a general reset circuit 50 .
  • the general reset circuit 50 may include a twenty-fifth transistor M25.
  • the gate of the twenty-fifth transistor M25 is connected to the general reset terminal RST_T of the shift register unit 300, and the first pole of the twenty-fifth transistor M25 is connected to a reference signal terminal (for example, a first reference signal terminal LVGL), the second pole of the twenty-fifth transistor M25 is connected to the overall pull-up node PU.
  • FIG. 4 is a circuit diagram of yet another shift register unit 400 according to some embodiments.
  • the shift register 400 in FIG. 4 is similar to the shift register 200 in FIG. 2 , the difference lies at least in the way of connecting the input sub-circuits of each output circuit. For the sake of brevity, the following will mainly describe the differences in detail.
  • the input subcircuit 401 of the first input subcircuit 40_1 is connected to the power signal terminal VGH in addition to the input signal terminal INPUT.
  • the input sub-circuit 401 can provide the signal of the power signal terminal VGH to the first pull-up node PU_1 based on the potential of the signal of the input signal terminal INPUT.
  • the gate of the first transistor M1 is connected to the input signal terminal INPUT
  • the first pole is connected to the power signal terminal VGH
  • the second pole is connected to the first pull-up node PU_1.
  • the input sub-circuit 401 of the second input sub-circuit 40_2 is similar to the first input sub-circuit 40_1 and will not be repeated here.
  • the eighteenth transistor M18 in the input circuit 10 can also be connected in a similar manner. As shown in Figure 14, the gate of the eighteenth transistor M18 is connected to the input signal terminal INPUT, the first pole of the eighteenth transistor M18 is connected to the power signal terminal VGH, and the second pole of the eighteenth transistor M18 is connected to the general pull-up node PU .
  • FIG. 5 is a circuit diagram of yet another shift register cell according to some embodiments.
  • the shift register unit 500 in FIG. 5 is similar to the shift register unit 200 in FIG. 2 , the difference lies at least in the number of output circuits and the connection mode of the clock signal terminals. For the convenience of description, the following will mainly describe the difference parts in detail.
  • N 4, that is, it includes 4 output circuits, 4 output clock signal terminals, 4 output signal terminals and 4 sub-pull-up nodes.
  • the shift register unit 500 includes a first output circuit 40_1 , a second output circuit 40_2 , a third output circuit 40_3 and a fourth output circuit 40_4 .
  • the shift register unit 500 also includes a first output clock signal terminal CLK_1 to a fourth output clock signal terminal CLK_4, a first output signal terminal OUT_1 to a fourth output signal terminal OUT_4, a first output pull-up node PU_1 to a fourth output Pull node PU_2.
  • Each output circuit is connected to a corresponding output clock signal terminal, a corresponding output signal terminal and a corresponding pull-up node.
  • the first output circuit 40_1 is connected to the first output clock signal terminal CLK_1, the first output signal terminal OUT_1 and the first output pull-up node PU_1
  • the second output circuit 40_2 is connected to the second output clock signal terminal CLK_2, the second output signal terminal OUT_2 and the first output pull-up node PU_3, and so on.
  • the respective structures and connection methods of the first output circuit 40_1 , the second output circuit 40_2 , the third output circuit 40_3 and the fourth output circuit 40_4 are similar to those described above with reference to FIG. 2 , and will not be repeated here. .
  • the first output clock signal terminal CLK_1 is connected to the control clock signal terminal CLK_C as a signal terminal. In this way, wiring can be reduced and the circuit structure can be further simplified.
  • FIG. 5 is taken as an example to illustrate that the first output clock signal terminal CLK_1 and the control clock signal terminal CLK_C can be connected to each other, the embodiments of the present disclosure are not limited thereto.
  • one of the N output clock signal terminals may be connected to the control clock signal terminal CLK_C.
  • FIG. 5 increases the number of output circuits on the basis of the shift register unit of FIG. 2
  • embodiments of the present disclosure are not limited thereto.
  • the number of output circuits of the shift register unit in any of the above embodiments can be set as required.
  • the number of output circuits of the above-mentioned shift register units 300 and 400 can be set to 3, 4 or more.
  • Some implementations of the present disclosure provide a gate driving circuit, which will be described below with reference to FIGS. 6 and 7 .
  • Fig. 6 is a schematic structural diagram of a gate driving circuit according to some embodiments.
  • the gate drive circuit includes M stages of cascaded shift register units GOA1 , GOA2 , .
  • the input signal terminal INPUT of the shift register unit GOAm of the mth stage is connected to the cascaded output terminal OUT_C of the shift register unit GOA(m-1) of the m-1st stage, and the shift register unit of the mth stage
  • the reset signal terminal RST_PU of GOAm is connected to the cascaded output terminal OUT_C of the m+2th stage shift register unit GOA(m+2), where M is an integer greater than 1, m is an integer and 1 ⁇ m ⁇ M-1.
  • M stages of cascaded shift register units GOA1 , GOA2 , . . . , GOAM are connected to K clock signal lines, where K is an even number greater than or equal to 2N.
  • the M-level cascaded shift register units GOA1, GOA2, ..., GOAM are divided into multiple groups, and each group includes 3-level cascaded first shift register unit, second shift register unit and third shift register unit.
  • the first group includes first to third stage shift register units GOA1, GOA2 and GOA3 respectively as the first to third shift register units in the first group
  • the second group includes fourth to third shift register units.
  • the shift register units GOA4, GOA5 and GOA6 of the sixth stage serve as the first to third shift register units in the second group respectively, and so on.
  • the four output clock signal terminals CLK_1 to CLK_4 of the first shift register unit GOA1 in this group are connected to the first clock signal line CLK1 to the fourth clock signal line CLK4 in one-to-one correspondence
  • the second The four output clock signal terminals CLK_1 to CLK_4 of the shift register GOA2 unit are connected to the fifth clock signal line CLK5 to the eighth clock signal line CLK8 in one-to-one correspondence
  • the clock signal lines CLK_4 to CLK_4 are connected to the ninth clock signal line CLK9 to the twelfth clock signal line CLK12 in a one-to-one correspondence.
  • the four output clock signal terminals CLK_1 to CLK_4 of the first shift register unit GOA4 in the second group are connected in one-to-one correspondence with the first clock signal line CLK1 to the fourth clock signal line CLK4, and the second shift register
  • the four output clock signal terminals CLK_1 to CLK_4 of the GOA5 unit are connected to the fifth clock signal line CLK5 to the eighth clock signal line CLK8 in one-to-one correspondence
  • the four output clock signal terminals CLK_1 to CLK_4 of the third shift register unit GOA6 are connected to
  • the ninth clock signal line CLK9 to the twelfth clock signal line CLK12 are connected in a one-to-one correspondence, and so on.
  • the input signal terminal INPUT of the first-stage shift register unit GOA1 is connected to the start signal line STV to receive the start signal.
  • the first-stage shift register unit GOA1 outputs 4 output signals at the 4 output signal terminals OUT_1 to OUT_4 based on the signal on the start signal line STV under the control of the clock signal on the clock signal line CLK1 to CLK4 G1 to G4, and output the cascade signal at the cascade output terminal OUT_C to the input signal terminal INPUT of the second-stage shift register unit GOA2.
  • the second-stage shift register unit GOA2 outputs four output signals G5 to G8 at the four output signal terminals OUT_1 to OUT_4 based on the cascade signal at the input signal terminal INPUT under the control of the clock signal lines CLK5 to CLK8, thereby analogy.
  • FIG. 7 is a schematic structural diagram of another gate driving circuit according to some embodiments.
  • the gate driving circuit includes M stages of cascaded shift register units GOA1 , GOA2 , . . . , GOAM.
  • the input signal terminal INPUT of the shift register unit GOAm of the mth stage is connected to the cascaded output terminal OUT_C of the shift register unit GOA (m-1) of the m-1st stage, and the shift register unit GOAm of the mth stage
  • the reset signal terminal RST_PU of is connected to the cascaded output terminal OUT_C of the m+2th shift register unit GOA(m+2), wherein M is an integer greater than 1, m is an integer and 1 ⁇ m ⁇ M-1.
  • M stages of cascaded shift register units GOA1 , GOA2 , . . . , GOAM are connected to eight clock signal lines CLK1 to CLK8 .
  • the first group includes the first stage and the second stage shift register unit GOA1, GOA2 respectively as the first and second shift register unit in the first group
  • the second group includes the third stage and the second stage
  • the six-stage shift register units GOA3 and GOA4 respectively serve as the first and second shift register units in the second group, and so on.
  • the four output clock signal terminals CLK_1 to CLK_4 of the first shift register unit GOA1 in this group are connected in one-to-one correspondence with the first clock signal line CLK1 to the fourth clock signal line CLK4, and the second The four output clock signal terminals CLK_1 to CLK_4 of the shift register unit GOA2 are connected to the fifth clock signal line CLK5 to the eighth clock signal line CLK8 in a one-to-one correspondence.
  • the shift register units GOA3 and GOA4 in the second group are connected to the clock signal lines CLK1 to CLK8 in a similar manner, which will not be repeated here.
  • the first output clock signal terminal CLK_1 of the N output clock signal terminals CLK_1 to CLK_N of each shift register unit is connected to the control clock signal terminal of the shift register unit CLK_C, so that the first output circuit and the cascade circuit generate outputs based on the same clock signal, so that the first output signal terminal OUT_1 and the cascade output terminal OUT_C output signals with the same waveform.
  • Fig. 8 is a schematic structural diagram of another gate driving circuit according to some embodiments.
  • the gate driving circuit includes M stages of cascaded shift register units GOA1 , GOA2 , . . . , GOAM.
  • Each shift register unit can be realized by the shift register unit with 2 output circuits in the above embodiment, for example, can be realized by any shift register unit described above with reference to FIG. 2 to FIG. 4 .
  • the input signal terminal INPUT of the shift register unit GOAm of the mth stage is connected to the cascaded output terminal OUT_C of the shift register unit GOA (m-1) of the m-1st stage, and the shift register unit GOAm of the mth stage
  • the reset signal terminal RST_PU of is connected to the cascaded output terminal OUT_C of the m+2th shift register unit GOA(m+2), wherein M is an integer greater than 1, m is an integer and 1 ⁇ m ⁇ M-1.
  • the six clock signal lines include the first control clock signal line CLKC1, the second control clock signal line CLKC2, the first output clock signal line CLK1, the second output clock signal line CLK2, the third output clock signal line CLK3 and The fourth output clock signal line CLK4.
  • the first group includes first-stage and second-stage shift register units GOA1, GOA2 as the first and second shift register units in the first group, respectively, and the second group includes third-stage and second-stage shift register units.
  • the six-stage shift register units GOA3 and GOA4 respectively serve as the first and second shift register units in the second group, and so on.
  • the two output clock signal terminals CLK_1 and CLK_2 of the first shift register unit GOA1 are connected to the first output clock signal line CLK1 and the second output clock signal line CLK2 in a one-to-one correspondence, and the first shift
  • the control clock signal terminal CLK_C of the register unit GOA1 is connected to the first control clock signal line CLKC1
  • the two output clock signal terminals CLK_1 and CLK_2 of the second shift register unit GOA2 are connected to the third clock signal line CLK3 and the fourth clock signal line CLK4
  • the control clock signal terminal CLK_C of the second shift register unit GOA2 is connected to the second control clock signal line CLKC2 .
  • the shift register units GOA3 and GOA4 in the second group are connected to the clock signal lines CLKC1, CLKC2, CLK1-CLK8 in a similar manner, which will not be repeated here.
  • the N output clock signal terminals CLK_1 to CLK_N of each shift register unit are separated from the control clock signal terminal CLK_C of the shift register unit, so that the cascaded circuit can be compared to the N
  • the output circuit is controlled by an independent clock, which improves the control flexibility.
  • FIG. 9 is a signal timing diagram of a driving method of a shift register unit according to some embodiments. This method is applicable to the shift register unit of any of the above embodiments. Taking the shift register unit shown in FIG. 2 as an example, the driving method will be exemplarily introduced below.
  • the pull-up circuit 10 supplies the first level of the input signal terminal INPUT to the total pull-up node PU, and the n-th output circuit 40 among the N output circuits 40 supplies the first level of the input signal terminal INPUT.
  • the level is input to the nth pull-up node PU_n.
  • the high level of the input signal terminal INPUT turns on the transistor M11, thereby providing the high level of the input signal terminal INPUT to the total pull-up node PU, and the high level of the pull-up node PU makes the transistor M11 turn on. M22 is turned on.
  • the high level of the input signal terminal INPUT also turns on the respective transistors M1 of the first output circuit 40_1 and the second output circuit 40_2 , thereby providing the high level of the input signal terminal INPUT to the first sub-pull-up node PU_1 and the second pull-up node PU_1 respectively.
  • the high level of the first pull-up node PU_1 turns on the transistor M2 in the first output circuit 40_1
  • the high level of the second pull-up node PU_2 turns on the transistor M2 in the second output circuit 40_2 .
  • the cascade circuit 30 provides the signal of the control clock signal terminal CLK_C to the cascade output terminal OUT_C under the control of the potential of the total pull-up node PU, and the nth output of the N output circuits 40
  • the circuit 40 provides the signal of the nth output clock signal terminal CLK_n to the nth output signal terminal OUT_n under the control of the potential of the nth pull-up node PU_n.
  • the high levels of the first output clock signal terminal CLK_1 and the second output clock signal terminal CLK_2 arrive sequentially, since the respective transistors M2 of the first output circuit 40_1 and the second output circuit 40_2 are turned on state, so the signals of the first output clock signal terminal CLK_1 and the second output clock signal terminal CLK_2 are provided to the first output signal terminal OUT_1 and the second output signal terminal OUT_2 respectively.
  • the high levels of the first output signal terminal OUT_1 and the second output signal terminal OUT_2 respectively further increase the potentials of the first sub-pull-up node PU_1 and the second sub-pull-up node PU_2 .
  • the signal at the control clock signal terminal CLK_C is the same as the signal at the first output clock signal terminal CLK_1, and because the transistor M22 is turned on, the signal at the control clock signal terminal CLK_C is provided to the cascaded output terminal OUT_C.
  • the pull-up circuit 10 provides the second level of the reset signal terminal RST_PU to the overall pull-up node PU, and the potential of the pull-up node PU makes the control circuit 20 control the pull-down node PD to be the first level. level, the potential of the pull-down node PD makes the cascade circuit 30 pull down the cascade output terminal OUT_C to the second level, and makes the nth output circuit 40 of the N output circuits 40 pull down the nth output signal terminal OUT_n to the second level Two levels. Referring to FIG.
  • the reset signal terminal RST_PU is at a high level, and the transistor M20 is turned on, thereby pulling the overall pull-up node PU down to the low level of the first reference signal terminal LVGL.
  • the low level of the overall pull-up node PU turns off the transistor M9, so that the pull-down node PD becomes high level.
  • the high level of the pull-down node PD turns on the transistor M23 and the respective transistors M3 and M4 of the first output circuit 40_1 and the second output circuit 40_2 .
  • the turn-on of the transistor M23 causes the cascade output terminal OUT_C to be pulled down to the low level of the first reference signal terminal LVGL.
  • the turn-on of the two transistors M3 makes the first sub-pull-up node PU_1 and the second sub-pull-up node PU_12 pulled down to the low level of the first reference signal terminal LVGL.
  • the conduction of the two transistors M4 causes the first output signal terminal OUT_1 and the second output signal terminal OUT_2 to be pulled down to the low level of the second reference signal terminal VGL.
  • Some embodiments of the present disclosure also provide a driving method for a gate driving circuit, the method includes: in the first mode, applying K first clocks sequentially shifted row by row to the K clock signal lines signal, so that the M-level shift register unit of the gate drive circuit generates a plurality of first output signals that are sequentially shifted row by row; K second clock signals, so that the M-stage shift register unit of the gate drive circuit generates a plurality of second output signals sequentially shifted by k rows, wherein the frequency of the K second clock signals is the K k times of the first clock signal, where k is an integer less than or equal to K.
  • K is an integer less than or equal to K.
  • Fig. 10 is a signal timing diagram of a driving method of a gate driving circuit in the first mode according to some embodiments
  • Fig. 11 is a timing diagram of a driving method of a gate driving circuit in the second mode according to some embodiments Signal timing diagram. This method is applicable to the gate driving circuit of any of the above embodiments.
  • the driving method will be exemplarily introduced below by taking the gate driving circuit in FIG. 6 as an example.
  • 12 first clock signals sequentially shifted row by row are applied to the 12 clock signal lines CLK1 to CLK12 of the gate drive circuit, so that the M stages of the gate drive circuit shift
  • the bit register units GOA1, GOA2, . . . , GOAM generate a plurality of first output signals G1, G2, .
  • the 12 first clock signals may be periodic signals.
  • the so-called progressive shift refers to the shifting of the first clock signal on the second clock signal line CLK2 relative to the first clock signal on the first clock signal line.
  • the first clock signal on the clock signal line CLK3 is shifted relative to the first clock signal on the second clock signal line CKK2, and so on.
  • the magnitudes of the shifts can be equal, for example, both are H or an integer multiple of H, where H represents the time required to scan a row of sub-pixels, also referred to as a unit scan time.
  • the signal on the start signal line STV is at a high level
  • the first-stage shift register unit GOA1 is controlled by the clock signals on the clock signal lines CLK1 to CLK4 based on the signal on the start signal line STV.
  • the signals of the four output signal terminals OUT_1 to OUT_4 respectively output four sequentially shifted output signals G1 to G4, and output the same cascade signal as the output signal G1 at the cascade output terminal OUT_C to the second-stage shift register unit
  • the second-stage shift register unit GOA2 outputs four sequential shift output signals G5 at the four output signal terminals OUT_1 to OUT_4 under the control of the clock signal lines CLK5 to CLK8 based on the cascade signal received at the input signal terminal INPUT to G8.
  • the fourth-stage shift register unit GOA4 generates a high-level output signal G9 and the same cascaded signal as G9.
  • the cascaded signal is received by the reset signal terminal RST_PU of the first-stage shift register GOA1, so that the general pull-up node PU and the four sub-pull-up nodes PU_1 to PU_4 of the first-stage shift register GOA1 are all pulled low, thereby realizing reset.
  • the gate drive circuit outputs sequentially shifted output signals G1, G2, . . . GM.
  • 12 second clocks sequentially shifted by k rows are applied to the 12 clock signal lines CLK1 to CLK12 of the gate drive circuit. signal, so that the M-level shift register unit of the gate drive circuit generates a plurality of second output signals G1 to G4 that are sequentially shifted by k rows, wherein the frequency of the 12 second clock signals is the frequency of the 12 second clock signals A clock signal CLK1 to CLK12 k times.
  • k 2 in the second mode
  • the first clock signal on the first clock signal line CLK1 and the second clock signal line CLK2 are the same
  • the first clock signal on the third clock signal line CLK3 and the fourth clock signal line CLK3 are the same
  • the clock signals on the fifth and sixth clock signal lines CLK5 and CLK6 are identical and shifted relative to the first clock signal on the third and fourth clock signal lines CLK3 and CLK4, and so on.
  • the start signal STV is at a high level
  • the shift register unit GOA1 of the first stage of the gate drive circuit is based on the start signal STV
  • the first to fourth clock signal lines CLK1-CLK4 Four output signals G1 to G4 are generated under the control of a clock signal, wherein the output signals G1 and G2 are the same, and the output signals G3 and G4 are the same and shifted relative to the output signals G1 and G2.
  • every two lines can be scanned simultaneously.
  • the frequency of the 12 second clock signals on the clock signal lines CLK1 to CLK12 is twice that of the 12 first clock signals CLK1 to CLK12 in FIG. 10 , thereby increasing the scanning speed.
  • the charging time of the pixel data line can be the same as the first mode (still 1H, because two rows of pixels are charged at the same time), so the image quality will not be reduced, so as to realize the 2 times refresh rate drive display.
  • FIGS. 10 and 11 are described above by taking the gate driving circuit of FIG. 6 as an example, embodiments of the present disclosure are not limited thereto.
  • this driving method is applied to the gate driving circuit of FIG. 7, eight clock signals are applied to the eight clock signal lines CLK1 to CLK8, respectively.
  • the pulse width of the first clock signal on the clock signal lines CLK1 to CLK8 is 4H, and the duty cycle is 50%; in the second mode, the pulse width of the second clock signal on the clock signal lines CLK1 to CLK8 is The pulse width is 2H, the duty cycle is still 50%, and the frequency is twice that of the first clock signal.
  • Embodiments of the present disclosure also provide another method for driving a gate drive circuit, wherein the K clock signal lines connected to the gate circuit include a plurality of output clock signal lines, and the method includes: in the first mode, supplying The plurality of output clock signal lines apply a plurality of first output clock signals that are sequentially shifted row by row, so that the M-stage shift register unit of the gate drive circuit generates a plurality of first output signals that are sequentially shifted row by row, wherein The N output circuits of each shift register unit generate output signals; in the second mode, a plurality of second output clock signals are applied to a part of the output clock signal lines in the plurality of output clock signal lines, so that the gate The M stages of shift register units of the driving circuit generate a plurality of sequentially shifted second output signals, wherein at least one output circuit among the N output circuits of each stage of shift register does not generate an output signal.
  • the method will be illustrated below with reference to FIG. 12 and FIG. 13 .
  • Fig. 12 is a signal timing diagram of another driving method of a gate driving circuit in the first mode according to some embodiments;
  • Fig. 13 is a signal timing diagram of another driving method of a gate driving circuit in a second mode according to some embodiments The signal timing diagram below.
  • This method is applicable to a gate driving circuit in which the control clock signal terminal CLK_C of the shift register unit is separated from the output signal terminals CLK_1 to CLK_N, such as the gate driving circuit described above with reference to FIG. 8 .
  • first output clock signals sequentially shifted row by row are applied to the four output clock signal lines CLK1 to CLK4 of the gate drive circuit, so that M of the gate drive circuit
  • the stage shift register units GOA1, GOA2, . . . , GOAM generate a plurality of first output signals G1, G2, .
  • the pulse width of the first output clock signal is 4H, and the duty cycle is 50%.
  • the first control clock signal may be applied to the first control clock signal line CLKC1
  • the second control clock signal may be applied to the second control clock signal line CLKC2
  • the first output clock signal line CLK1 , the second output clock signal line CLK2, the third output clock signal line CLK3 and the fourth output clock signal line CLK4 respectively apply four first output clock signals shifted sequentially, so that each stage of shift register units GOA1, GOA2, ... , GOAM's 2 output circuits both generate output signals.
  • the signal on the start signal line STV is at a high level, and the first-stage shift register unit GOA1 is controlled by the clock signal on the output clock signal lines CLK1 and CLK2, based on the start signal
  • the signal on the line STV outputs two sequentially shifted output signals G1 and G2 respectively at the two output signal terminals OUT_1 and OUT_2, and is output at the cascaded output terminal OUT_C under the control of the control clock signal on the control clock signal line CLKC1 cascade signal.
  • the cascade signal is provided to the input signal terminal INPUT of the shift register unit GOA2 of the second stage.
  • the second-stage shift register unit GOA2 is based on the cascaded signal received at the input signal terminal INPUT, and outputs two sequential shift output signals at the two output signal terminals OUT_1 and OUT_2 under the control of the output clock signal lines CLK3 and CLK4 G3 and G4, and output the cascade signal at the cascade output terminal OUT_C under the control of the control clock signal on the control clock signal line CLKC2.
  • the gate drive circuit outputs sequentially shifted output signals G1, G2, . . . GM.
  • a second output clock is applied to some of the output clock signal lines CLK1 to CLK4 (even-numbered output clock signal lines CLK2 and CLK4 in FIG. 13 ).
  • the M-level shift register units GOA1, GOA2, ..., GOAM of the gate drive circuit generate a plurality of second output signals G2, G4, G6, ... that are sequentially shifted, and two of the shift register units of each level At least one of the output circuits produces no output signal.
  • the first control clock signal CLKC1 may be applied to the first control clock signal line CLKC1
  • the second control clock signal CLKC2 may be applied to the second control clock signal line CLKC2
  • the second control clock signal CLKC2 may be applied to the second control clock signal line CLKC2.
  • the odd-numbered or even-numbered output clock signal lines among the first output clock signal line CLK1, the second output clock signal line CLK2, the third output clock signal line CLK3, and the fourth output clock signal line CLK4 respectively apply two second outputs shifted sequentially.
  • the clock signal makes one of the two output circuits of each stage of shift register unit generate an output signal.
  • FIG. 8 the example of FIG.
  • the first output circuit of each shift register unit does not produce an output because no clock signal is received, and the second output circuit produces an output based on the received clock signal, so that the first stage shift register
  • the unit GOA1 generates the output signal G2
  • the second-stage shift register unit GOA2 generates the output signal G4, and so on, realizing that the odd-numbered rows of pixels are turned off, and the even-numbered rows are scanned, and vice versa.
  • the output clock signal may be applied to the output clock signal lines CLK1 and CLK3 without applying the output clock signal to the output clock signal lines CLK2 and CLK4, so that the second output circuit of each stage of shift register unit generates a signal while the first The output circuit does not generate an output signal, so that even rows of pixels are turned off and odd rows are scanned.
  • the gates of one or more sub-pixel rows are kept closed to avoid writing data signals.
  • the delay caused by the heavy load of the data signal and the short switching time can be avoided, thereby avoiding serial problems caused by wrongly writing the data signal into adjacent sub-pixel rows, and improving the display quality of the display device.
  • the gates of the sub-pixels located in the odd-numbered sub-pixel rows can be turned off, and the gates of the sub-pixels located in the even-numbered sub-pixel rows can be normally opened to write corresponding data signals.
  • the gate driving signal may be generated by scanning even-numbered rows in one frame, and the gate driving signal may be generated by scanning odd-numbered rows in the next frame.
  • FIG. 14 is a timing diagram of signals in the first mode and the second mode of still another driving method of the gate driving circuit according to some embodiments.
  • the driving method shown in FIG. 14 is similar to the driving method described above with reference to FIGS. 12 and 13, the difference is at least that in FIG.
  • Signal lines CLK2 and CLK4 apply an output clock signal, so that the second output circuit of each stage of shift register unit generates a signal, while the first output circuit does not generate an output signal, thereby realizing that even rows of pixels are turned off and odd rows are scanned.
  • the period of the second output clock signal applied to the output clock signal lines CLK1 to CLK4 in the second mode is equal to the period of the first output clock signal applied to the clock signal lines CLK1 to CLK4 in the first mode, and
  • the duty cycle is greater than the duty cycle of the first output clock signal, for example, the active level duration of the former is longer than that of the latter, T ⁇ H.
  • the pulse width of the data signal Data can be correspondingly increased by T, so that the charging time of each odd row is increased by T, thereby increasing the charging rate.
  • the odd-numbered lines are turned off, and the same principle is used to increase the charging time.
  • the mode of parity switching in the second mode is used as an example for illustration, the embodiments of the present disclosure are not limited thereto.
  • Multiple output circuits of the shift register unit of the gate drive circuit can be switched as required to generate different gate drive signals.
  • the clock signal can be used to control each shift register unit to close the first output circuit in one frame, and the second to fourth output circuits generate output; and in the next frame, the first output circuit generates an output, while the fourth output circuit of the second value is closed, thereby realizing 1:3 switching.
  • Other switching modes are also allowed, which is not limited in the present disclosure.

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Abstract

一种移位寄存器单元及其驱动方法、栅极驱动电路及其驱动方法，移位寄存器单元（100,200,300,400,500）包括：上拉电路（10），连接至输入信号端、总上拉节点和下拉节点，被配置为将输入信号端信号提供至总上拉节点，并在下拉节点的电位的控制下下拉总上拉节点的电位；控制电路（20），连接至总上拉节点和下拉节点，被配置为控制下拉节点电位；级联电路（30），连接至总上拉节点、下拉节点以及级联输出端和控制时钟信号端，被配置为将控制时钟信号端信号提供至级联输出端，以及下拉级联输出端的电位；N个输出电路（40）中第n输出电路连接至输入信号端、下拉节点、第n输出信号端和第n分上拉节点，被配置为将输入信号端信号输入至第n分上拉节点，在第n分上拉节点的电位控制下将第n输出时钟信号端信号提供至第n输出信号端，以及在下拉节点电位控制下下拉第n输出信号端电位。

Description

移位寄存器单元及其驱动方法、栅极驱动电路及其驱动方法
本申请要求于2021年7月29日提交的、申请号为202110868017.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元及其驱动方法，以及一种栅极驱动电路及其驱动方法。
背景技术
在现有的显示装置中，通常包括至少一个栅极驱动电路。在显示装置显示图像时，通过栅极驱动电路可实现显示装置的各子像素行的扫描，从而根据待显示图像对应的图像数据，对子像素行中的各子像素充电，以实现图像显示。
发明内容
一方面，提供了一种移位寄存器单元，包括上拉电路、控制电路、级联电路和N个输出电路。上拉电路连接至所述移位寄存器单元的输入信号端、总上拉节点和下拉节点，所述上拉电路被配置为将输入信号端的信号提供至所述总上拉节点，并在所述下拉节点的电位的控制下下拉所述总上拉节点的电位。控制电路连接至所述总上拉节点和所述下拉节点，所述控制电路被配置为根据所述总上拉节点的电位来控制所述下拉节点的电位。级联电路连接至所述总上拉节点、所述下拉节点以及所述移位寄存器单元的级联输出端和控制时钟信号端，所述级联电路被配置为在所述总上拉节点的电位的控制下将所述控制时钟信号端的信号提供至所述级联输出端，以及在所述下拉节点的电位的控制下下拉所述级联输出端的电位。N个输出电路分别连接至所述输入信号端、所述下拉节点，以及所述移位寄存器单元的N个输出时钟信号端、N个分上拉节点和N个输出信号端，其中第n输出电路连接至所述输入信号端、所述下拉节点、第n输出信号端和第n分上拉节点，并且被配置为将所述输入信号端的信号输入至所述第n分上拉节点，在第n分上拉节点的电位的控制下将所述第n输出时钟信号端的信号提供至第n输出信号端，以及在所述下拉节点的电位的控制下下拉所述第n输出信号端的电位，其中N为大于1的整数，n为整数且1≤n≤N。
在一些实施例中，第n输出电路包括：输入子电路、输出子电路和下拉子电路。输入子电路连接至所述输入信号端和所述第n分上拉节点，并且被配置为将所述输入信号端的信号提供至所述第n分上拉节点。输出子电路连接至所述第n分上拉节点、所述第n输出时钟信号端以及所述第n输出信号端，并且被配置为在所述第n分上拉节点的电位的控制下将所述第n输出时钟信号端的信号提供至所述第n输出信号端。下拉子电路连接至所述下拉节点，并且被配置为在所述下拉节点的电位的控制下，下拉所述第n分上拉节点和所述第n输出信号端的电位。
在一些实施例中，所述下拉节点包括第一下拉节点和第二下拉节点，所述下拉子电路包括第一下拉子电路和第二下拉子电路。所述第一下拉子电路连接至所述第一下拉节点，并且被配置为在所述第一下拉节点的电位的控制下，下拉所述第n分上拉节点和所述第n输出信号端中至少之一的电位。所述第二下拉子电路连接至所述第二下拉节点，并且被配置为在所述第二下拉节点的电位的控制下，下拉所述第n分上拉节点和所述第n输出信号端中至少之一的电位。
在一些实施例中，所述控制电路包括：第一控制子电路和第二控制子电路。第一控制子电路连接至所述总上拉节点和所述第一下拉节点，并且被配置为根据所述总上拉节点的电位来控制所述第一下拉节点的电位。第二控制子电路，连接至所述总上拉节点和所述第二下拉节点，并且被配置为根据所述总上拉节点的电位来控制所述第二下拉节点的电位。
在一些实施例中，第n输出电路还包括：复位子电路，连接至所述第n分上拉节点以及所述移位寄存器单元的复位信号端和参考信号端，并且被配置为在所述复位信号端的信号的控制下利用所述参考信号端的电位来复位所述第n分上拉节点。
在一些实施例中，所述输入子电路还连接至电源信号端，并且被配置为在所述输入信号端的信号的控制下将所述电源信号端的电位提供至所述第n分上拉节点。
在一些实施例中，所述N个输出时钟信号端中的第一输出时钟信号端与所述控制时钟信号端连接。
在一些实施例中，所述输入子电路包括：第一晶体管，所述第一晶体管的栅极和所述第一晶体管的第一极连接至所述输入信号端，所述第一晶体管的第二极连接至所述第n分上拉节点。
在一些实施例中，所述输入子电路包括：第一晶体管，所述第一晶体管的栅极连接至所述输入信号端，所述第一晶体管的第一极连接至所述电源信号端，所述第一晶体管 的第二极连接至所述第n分上拉节点。
在一些实施例中，所述输出子电路包括第二晶体管和第一电容。所述第二晶体管的栅极连接至所述第n分上拉节点，所述第二晶体管的第一极连接至所述第n输出时钟信号端，所述第二晶体管的第二极连接至所述第n输出信号端。第一电容，所述第一电容的第一端连接至所述第n分上拉节点，所述第一电容的第二端连接至所述第n输出信号端。
在一些实施例中，所述下拉子电路包括：第三晶体管和第四晶体管。所述第三晶体管的栅极连接至所述下拉节点，所述第三晶体管的第一极连接至所述移位寄存器单元的第一参考信号端，所述第三晶体管的第二极连接至所述第n分上拉节点。所述第四晶体管的栅极连接至所述下拉节点，所述第四晶体管的第一极连接至所述移位寄存器单元的第二参考信号端，所述第四晶体管的第二极连接至所述第n输出信号端。
在一些实施例中，所述第一下拉子电路包括第三晶体管和第四晶体管，所述第三晶体管的栅极连接至所述第一下拉节点，所述第三晶体管的第一极连接至所述移位寄存器单元的第一参考信号端，所述第三晶体管的第二极连接至所述第n分上拉节点，所述第四晶体管的栅极连接至所述第一下拉节点，所述第四晶体管的第一极连接至所述移位寄存器单元的第二参考信号端，所述第四晶体管的第二极连接至所述第n输出信号端。所述第二下拉子电路包括第五晶体管和第六晶体管，所述第五晶体管的栅极连接至所述第二下拉节点，所述第五晶体管的第一极连接至所述第一参考信号端，所述第五晶体管的第二极连接至所述第n分上拉节点，所述第六晶体管的栅极连接至所述第二下拉节点，所述第六晶体管的第一极连接至所述第二参考信号端，所述第六晶体管的第二极连接至所述第n输出信号端。
在一些实施例中，所述复位子电路包括第七晶体管，所述第七晶体管的栅极连接至所述复位信号端，所述第七晶体管的第一极连接至所述参考信号端，所述第七晶体管的第二极连接至所述第n分上拉节点。
在一些实施例中，所述控制电路包括：第八晶体管和第九晶体管。第八晶体管，所述第八晶体管的栅极和所述第八晶体管的第一极连接至所述移位寄存器单元的电源信号端，所述第八晶体管的第二极连接至所述下拉节点。第九晶体管，所述第九晶体管的栅极连接至所述总上拉节点，所述第九晶体管的第一极连接至所述移位寄存器单元的参考信号端，所述第九晶体管的第二极连接至所述下拉节点。
在一些实施例中，所述第一控制子电路包括第十晶体管、第十一晶体管、第十二晶 体管和第十三晶体管，所述第十晶体管的栅极和所述第十晶体管的第一极连接至所述移位寄存器单元的电源信号端，所述第十晶体管的第二极与所述第十一晶体管的栅极连接，所述第十一晶体管的第一极连接至所述电源信号端，所述第十一晶体管的第二极连接至所述第一下拉节点，所述第十二晶体管的栅极连接至所述总上拉节点，所述第十二晶体管的第一极连接至所述移位寄存器单元的参考信号端，所述第十二晶体管的第二极连接至所述第十一晶体管的栅极，所述第十三晶体管的栅极连接至所述总上拉节点，所述第十三晶体管的第一极连接至所述参考信号端，所述第十三晶体管的第二极连接至所述第一下拉节点。所述第二控制子电路包括第十四晶体管、第十五晶体管、第十六晶体管和第十七晶体管，所述第十四晶体管的栅极和所述第十四晶体管的第一极连接至所述电源信号端，所述第十四晶体管的第二极与所述第十五晶体管的栅极连接，所述第十五晶体管的第一极连接至所述电源信号端，所述第十五晶体管的第二极连接至所述第二下拉节点，所述第十六晶体管的栅极连接至所述总上拉节点，所述第十六晶体管的第一极连接至所述参考信号端，所述第十六晶体管的第二极连接至所述第十五晶体管的栅极，所述第十七晶体管的栅极连接至所述总上拉节点，所述第十七晶体管的第一极连接至所述参考信号端，所述第十七晶体管的第二极连接至所述第二下拉节点。
在一些实施例中，所述上拉电路包括：第十八晶体管、第十九晶体管和第二十晶体管。所述第十八晶体管的栅极和所述第十八晶体管的第一极连接至所述输入信号端，所述第十八晶体管的第二极连接至所述总上拉节点。第十九晶体管，所述第十九晶体管的栅极连接至所述下拉节点，所述第十九晶体管的第一极连接至所述移位寄存器单元的参考信号端，所述第十九晶体管的第二极连接至所述总上拉节点。第二十晶体管，所述第二十晶体管的栅极连接至所述移位寄存器单元的复位信号端，所述第二十晶体管的第一极连接至所述参考信号端，所述第二十晶体管的第二极连接至所述总上拉节点。
在一些实施例中，所述下拉节点包括第一下拉节点和第二下拉节点，所述上拉电路还包括第二十一晶体管。所述第十九晶体管的栅极连接至所述第一下拉节点，所述第二十一晶体管的栅极连接至所述第二下拉节点，所述第二十一晶体管的第一极连接至所述参考信号端，所述第二十一晶体管的第二极连接至所述总上拉节点。
在一些实施例中，所述级联电路包括：第二十二晶体管、第二十三晶体管和第二电容。所述第二十二晶体管的栅极连接至所述总上拉节点，所述第二十二晶体管的第一极连接至所述控制时钟信号端，所述第二十二晶体管的第二极连接至所述级联输出端。第二十三晶体管，所述第二十三晶体管的栅极连接至所述下拉节点，所述第二十三晶体管 的第一极连接至所述移位寄存器单元的参考信号端，所述第二十三晶体管的第二极连接至所述级联输出端。第二电容，所述第二电容的第一端连接至所述第二十二晶体管的栅极，所述第二电容的第二端连接至所述级联输出端。
在一些实施例中，所述下拉节点包括第一下拉节点和第二下拉节点，所述级联电路还包括第二十四晶体管。所述第二十四晶体管的栅极连接至所述第一下拉节点，所述第二十四晶体管的栅极连接至所述第二下拉节点，所述第二十四晶体管的第一极连接至所述参考信号端，所述第二十四晶体管的第二极连接至所述级联输出端。
在一些实施例中，所述移位寄存器单元还包括总复位电路。所述总复位电路包括第二十五晶体管，所述第二十五晶体管的栅极连接至所述移位寄存器单元的总复位端，所述第二十五晶体管的第一极连接至所述移位寄存器单元的参考信号端，所述第二十五晶体管的第二极连接至所述总上拉节点。
在一些实施例中，N＝4或2。
另一方面，提供一种栅极驱动电路，包括M级级联的移位寄存器单元，所述移位寄存器单元是如上所述的移位寄存器单元。第m级移位寄存器单元的输入信号端与第m-1级移位寄存器单元的级联输出端连接，第m级移位寄存器单元的复位信号端与第m+2级移位寄存器单元的级联输出端连接，其中M为大于1的整数，m为整数且1＜m＜M-1。所述M级级联的移位寄存器单元连接至K条时钟信号线，其中K为大于或等于2N的偶数。
在一些实施例中，N＝4，K＝12，所述M级级联的移位寄存器单元分为多组，每组包括3级级联的第一移位寄存器单元、第二移位寄存器单元和第三移位寄存器单元，其中第一移位寄存器单元的N个输出时钟信号端与第一时钟信号线至第四时钟信号线一一对应地连接，第二移位寄存器单元的N个输出时钟信号端与第五时钟信号线至第八时钟信号线一一对应地连接，第三移位寄存器单元的N个输出时钟信号端与第九至第十二时钟信号线一一对应地连接。
在一些实施例中，N＝4，K＝8，所述M级级联的移位寄存器单元分为多组，每组包括2级级联的第一移位寄存器单元和第二移位寄存器单元，其中第一移位寄存器单元的N个输出时钟信号端与第一时钟信号线至第四时钟信号线一一对应地连接，第二移位寄存器单元的N个输出时钟信号端与第五时钟信号线至第八时钟信号线一一对应地连接。
在一些实施例中，每个移位寄存器单元的N个输出时钟信号端中的第一输出时钟信号端与该移位寄存器单元的控制时钟信号端连接。
在一些实施例中，N＝2，K＝6，所述K个时钟信号线包括第一控制时钟信号线、第二控制时钟信号线、第一输出时钟信号线、第二输出时钟信号线、第三输出时钟信号线和第四输出时钟信号线。所述M级级联的移位寄存器单元分为多组，每组包括2级级联的第一移位寄存器单元和第二移位寄存器单元，其中第一移位寄存器单元的N个输出时钟信号端与第一输出时钟信号线和第二输出时钟信号线一一对应地连接，第一移位寄存器单元的控制时钟信号端与第一控制时钟信号线连接，第二移位寄存器单元的N个输出时钟信号端与第三时钟信号线和第四时钟信号线一一对应地连接，第二移位寄存器单元的控制时钟信号端与第二控制时钟信号线连接。
再一方面，提供一种上述移位寄存器单元的驱动方法。该方法包括：在第一时段，上拉电路将输入信号端的第一电平提供至总上拉节点，N个输出电路中的第n输出电路将所述输入信号端的第一电平输入至所述第n分上拉节点；在第二时段，级联电路在所述总上拉节点的电位的控制下将控制时钟信号端的信号提供至级联输出端，并且N个输出电路中的第n输出电路在第n分上拉节点的电位的控制下将第n输出时钟信号端的信号提供至第n输出信号端；以及，在第三时段，上拉电路将输入信号端的第二电平提供至所述总上拉节点，上拉节点的电位使控制电路将所述下拉节点控制为第一电平，下拉节点的电位使得级联电路将级联输出端下拉至第二电平，并且使得N个输出电路中的第n输出电路将第n输出信号端下拉至第二电平。
又一方面，提供另一种上述移位寄存器单元的驱动方法。该方法包括：在第一模式下，向所述K条时钟信号线施加逐行顺序移位的K个第一时钟信号，使得栅极驱动电路的M级移位寄存器单元产生逐行顺序移位的多个第一输出信号；在第二模式下，向所述K条时钟信号线施加逐k行顺序移位的K个第二时钟信号，使得栅极驱动电路的M级移位寄存器单元产生逐k行顺序移位的多个第二输出信号，其中在所述K个第二时钟信号的频率是所述K个第一时钟信号的k倍，其中k为小于或等于K的整数。
在一些实施例中，N＝4，K＝12或8，k＝2或4。
又一方面，提供一种上述栅极驱动电路的驱动方法。所述K条时钟信号线包括多条输出时钟信号线，所述方法包括：在第一模式下，向所述多条输出时钟信号线施加逐行顺序移位的多个第一输出时钟信号，使得栅极驱动电路的M级移位寄存器单元产生逐行顺序移位的多个第一输出信号，其中每级移位寄存器单元的N个输出电路均产生输出信号；在第二模式下，向所述多条输出时钟信号线中的一部分输出时钟信号线施加多个第二输出时钟信号，使得栅极驱动电路的M级移位寄存器单元产生顺序移位的多个第 二输出信号，其中每级移位寄存器的N个输出电路中的至少一个输出电路不产生输出信号。
在一些实施例中，N＝2，K＝6，所述K条时钟信号线包括第一控制时钟信号线、第二控制时钟信号线、第一输出时钟信号线、第二输出时钟信号线、第三输出时钟信号线和第四输出时钟信号线。在第一模式下，向所述第一控制时钟信号线施加第一控制时钟信号，向所述第二控制时钟信号线施加第二控制时钟信号，并且向第一输出时钟信号线、第二输出时钟信号线、第三输出时钟信号线和第四输出时钟信号线分别施加顺序移位的四个第一输出时钟信号，使得每级移位寄存器单元的2个输出电路均产生输出信号；以及在第二模式下，向所述第一控制时钟信号线施加所述第一控制时钟信号，向所述第二控制时钟信号线施加所述第二控制时钟信号，并且向第一输出时钟信号线、第二输出时钟信号线、第三输出时钟信号线和第四输出时钟信号线中的奇数或偶数时钟信号线分别施加顺序移位的两个第二输出时钟信号，使得每级移位寄存器单元的2个输出电路之一产生输出信号。
在一些实施例中，所述第二输出时钟信号的周期与所述第一输出时钟信号的周期相等，并且所述第二输出时钟信号占空比大于所述第一输出时钟信号的占空比。
附图说明
图1是根据一些实施例的一种移位寄存器单元的示意性框图；
图2是根据一些实施例的一种移位寄存器单元的电路图；
图3是根据一些实施例的另一种移位寄存器单元的电路图；
图4是根据一些实施例的又一种移位寄存器单元的电路图；
图5是根据一些实施例的又一种移位寄存器单元的电路图；
图6是根据一些实施例的一种栅极驱动电路的结构示意图；
图7是根据一些实施例的另一种栅极驱动电路的结构示意图；
图8是根据一些实施例的又一种栅极驱动电路的结构示意图；
图9是根据一些实施例的移位寄存器单元的驱动方法的信号时序图；
图10是根据一些实施例的一种栅极驱动电路的驱动方法在第一模式下的信号时序图；
图11是根据一些实施例的一种栅极驱动电路的驱动方法在第二模式下的信号时序图；
图12是根据一些实施例的另一种栅极驱动电路的驱动方法在第一模式下的信号时序图；
图13是根据一些实施例的另一种栅极驱动电路的驱动方法在第二模式下的信号时序图；以及
图14是根据一些实施例的又一种栅极驱动电路的驱动方法在第一模式和第二模式下的信号时序图。
具体实施方式
虽然将参照含有本公开的较佳实施例的附图充分描述本公开，但在此描述之前应了解本领域的普通技术人员可修改本文中所描述的公开，同时获得本公开的技术效果。因此，须了解以上的描述对本领域的普通技术人员而言为一广泛的揭示，且其内容不在于限制本公开所描述的示例性实施例。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
在本公开实施例的描述中，术语“连接至”、“相连”或“电连接”可以是指两个组件直接连接，也可以是指两个组件之间经由一个或多个其他组件相连。
在相关技术中，显示装置通常包括显示面板和与显示面板电连接的至少一个栅极驱动电路。示例性的，该栅极驱动电路可以与显示面板独立制作，而后二者可以通过，例如柔性印刷电路板，连接在一起。作为另一种示例，在显示面板的制程中，可以将上述栅极驱动电路直接制作在显示面板的基板上，例如制作在显示面板的显示区周围的周边 区中，该技术也被称为GOA(Gate On Array)技术。在显示装置采用GOA技术的情况下，显示面板中的子像素行中的各子像素可由栅极驱动电路中的一个对应的移位寄存器单元驱动。
然而，在显示装置的分辨率较高，以及显示装置的刷新率较高(例如，8K分辨率)的情况下，显示装置所需要的移位寄存器单元的数量较大，这将造成显示装置边框的尺寸较大，影响产品的美观度。
参见图1，本公开的一些实施例提供了一种移位寄存器单元100。该移位寄存器单元100包括上拉电路10、控制电路20、级联电路30和N个输出电路40。
上拉电路10连接至所述移位寄存器单元100的输入信号端INPUT、总上拉节点PU和下拉节点PD，上拉电路10被配置为将输入信号端INPUT的信号提供至总上拉节点PU，并在下拉节点PD的电位的控制下下拉所述总上拉节点PU的电位。
控制电路20连接至总上拉节点PU和下拉节点PD，控制电路20被配置为根据总上拉节点PU的电位来控制下拉节点PD的电位。
级联电路30连接至总上拉节点PU、下拉节点PD以及移位寄存器单元100的级联输出端OUT_C和控制时钟信号端CLK_C，所述级联电路30被配置为在总上拉节点PU的电位的控制下，将所述控制时钟信号端CLK_C的信号提供至级联输出端OUT_C，以及在下拉节点PD的电位的控制下下拉级联输出端OUT_C的电位。
N个输出电路40分别连接至输入信号端INPUT、下拉节点PD，以及所述移位寄存器单元100的N个输出时钟信号端(例如，图1中的CLK_1至CLK_N)、N个分上拉节点(例如，图1中的PU_1至PU_N)和N个输出信号端(例如，图1中的OUT_1至OUT_N)。第n输出电路40连接至所述输入信号端INPUT、下拉节点PD、第n输出信号端OUT_n和第n分上拉节点PU_n，并且被配置为将输入信号端INPUT的信号输入至第n分上拉节点PU_n，在第n分上拉节点PU_n的电位的控制下将第n输出时钟信号端CLK_n的信号提供至第n输出信号端OUT_n，以及在下拉节点PD的电位的控制下下拉第n输出信号端OUT_n的电位。这里，N为大于1的整数，n为整数且1≤n≤N。在一些实施例中，2≤N≤8，例如，N可以为2、3、4、5或6。
本公开的实施例通过在移位寄存器单元中采用N个输出电路共用一个控制电路的结构，使得移位寄存器单元够代替传统的多个移位寄存器单元来独立产生多个输出信号，相比于传统的多个移位寄存器单元的组合来说，具备更简单的电路结构。例如，在上述移位寄存器单元中，N个输出电路共用一个控制电路，即，通过同一个下拉节点 PD的电位控制。每个输出电路包含各自的分上拉节点，能够彼此独立地产生输出。与相关技术相比，在驱动同样数量的子像素行数的情况下，本公开的实施例的移位寄存器单元可以减少所需设置的控制电路的数量，具有更简单的电路结构，有利于减小显示装置的边框尺寸。
图2是根据一些实施例的一种移位寄存器单元200的电路图。
如图2所示，移位寄存器单元200包括上拉电路10、控制电路20、级联电路30和N个输出电路。N可以为2，即，N个输出电路包括第一输出电路40_1和第二输出电路40_2(下文统称输出电路40)。第一输出电路40_1和第二输出电路40_2共用一个控制电路20。在这种情况下，移位寄存器单元200可以包括第一输出时钟信号端CLK_1和第二输出时钟信号端CLK_2、第一输出信号端OUT_1和第二输出信号端OUT_2、第一上拉结点PU_1和第二上拉结点PU_2。
参见图2，每个输出电路40包括输入子电路401、输出子电路402和下拉子电路403。下面以其中任一个输出子电路40(即第n输出子电路40，n＝1或2)为例来说明输出子电路的结构。
输入子电路401连接至输入信号端INPUT和第n分上拉节点PU_n，并且被配置为将输入信号端INPUT的信号提供至第n分上拉节点PU_n。
输出子电路402连接至所述第n分上拉节点PU_n、所述第n输出时钟信号端CLK_n，以及所述第n输出信号端OUT_n，并且被配置为在第n分上拉节点PU_n的电位的控制下，将所述第n输出时钟信号端CLK_n的信号提供至第n输出信号端OUT_n。
下拉子电路403连接至下拉节点PD，并且被配置为在所述下拉节点PD的电位的控制下，下拉第n分上拉节点PU_n和第n输出信号端OUT_n的电位。
如图2所示，在第一输出电路40_1中，输入子电路401可以包括第一晶体管M1。第一晶体管M1的栅极和第一晶体管M1的第一极连接至输入信号端INPUT，第一晶体管M1的第二极连接至第一分上拉节点PU_1。
在第一输出电路40_1中，输出子电路402可以包括第二晶体管M2和第一电容C1。第二晶体管M2的栅极连接至第一分上拉节点PU_1，第二晶体管M2的第一极连接至第一输出时钟信号端CLK_1，第二晶体管M2的第二极连接至第一输出信号端OUT_1。第一电容C1的第一端连接至第一分上拉节点PU_1，所述第一电容C1的第二端连接至第一输出信号端OUT_1。
在第一输出电路40_1中，下拉子电路403可以包括第三晶体管M3和第四晶体管 M4。第三晶体管M3的栅极连接至所述下拉节点PD，所述第三晶体管M3的第一极连接至移位寄存器单元200的参考信号端(例如第一参考信号端LVGL)，第三晶体管M3的第二极连接至第一分上拉节点PU_1。第四晶体管M4的栅极连接至所述下拉节点PD，所述第四晶体管M4的第一极连接至所述移位寄存器单元200的参考信号端(例如第二参考信号端VGL)，所述第四晶体管M4的第二极连接至所述第一输出信号端OUT_1。
第二输出电路40_2具有与第二输出电路40_1类似的结构，区别在于其连接第二分上拉节点PU_2、第二输出时钟信号端CLK_2和第二输出信号端OUT_2。如图2所示，在第二输出电路40_2中，第一晶体管M1的栅极和第一晶体管M1的第一极连接至输入信号端INPUT，第一晶体管M1的第二极连接至第二分上拉节点PU_2。第二晶体管M2的栅极连接至第二分上拉节点PU_2，第二晶体管M2的第一极连接至第二输出时钟信号端CLK_2，第二晶体管M2的第二极连接至第二输出信号端OUT_2。第一电容C1的第一端连接至第二分上拉节点PU_2，所述第一电容C1的第二端连接至第二输出信号端OUT_2。第三晶体管M3的栅极连接至所述下拉节点PD，所述第三晶体管M3的第一极连接至第一参考信号端LVGL，第三晶体管M3的第二极连接至第二分上拉节点PU_2。第四晶体管M4的栅极连接至所述下拉节点PD，所述第四晶体管M4的第一极连接至第二参考信号端VGL，所述第四晶体管M4的第二极连接至所述第二输出信号端OUT_2。
控制电路20可以包括第八晶体管M8和第九晶体管M9。第八晶体管M8的栅极和其第一极连接至所述移位寄存器单元200的电源信号端VDD，所述第八晶体管M8的第二极连接至所述下拉节点PD。第九晶体管M9的栅极连接至所述总上拉节点PU，所述第九晶体管M9的第一极连接至所述移位寄存器单元200的参考信号端(例如第一参考信号端LVGL)，所述第九晶体管M9的第二极连接至所述下拉节点PD。
上拉电路10包括第十八晶体管M18、第十九晶体管M19和第二十晶体管M20。所述第十八晶体管M18的栅极和其第一极连接至所述输入信号端INPUT，所述第十八晶体管M18的第二极连接至所述总上拉节点PU。第十九晶体管M19的栅极连接至所述下拉节点，所述第十九晶体管M19的第一极连接至所述移位寄存器单元200的参考信号端(例如第一参考信号端LVGL)，所述第十九晶体管M19的第二极连接至所述总上拉节点PU。第二十晶体管M20的栅极连接至所述移位寄存器单元的复位信号端RST_PU，第二十晶体管M20的第一极连接至参考信号端(例如第一参考信号端LVGL)，所述第二十晶体管M20的第二极连接至所述总上拉节点PU。
级联电路30可以包括第二十二晶体管M22、第二十三晶体管M23和第二电容C2。 第二十二晶体管M22的栅极连接至所述总上拉节点PU，所述第二十二晶体管M22的第一极连接至控制时钟信号端CLK_C，第二十二晶体管M22的第二极连接至所述级联输出端OUT_C。第二十三晶体管M23的栅极连接至下拉节点PD，所述第二十三晶体管M23的第一极连接至所述移位寄存器单元100的参考信号端(例如第一参考信号端LVGL)，所述第二十三晶体管M23的第二极连接至所述级联输出端OUT_C。第二电容C2的第一端连接至所述第二十二晶体管M22的栅极，所述第二电容C2的第二端连接至所述级联输出端OUT_C。
图3是根据一些实施例的另一种移位寄存器单元300的电路图。图3的电路与图2类似，区别至少在于移位寄存器单元的下拉节点包括第一下拉节点PD_1和第二下拉节点PD_2。为了简化描述，下面将主要对区别部分进行详细说明。
参见图3，每个输出电路40_1和40_2的下拉子电路可以包括第一下拉子电路和第二下拉子电路。在图3中，第一下拉子电路包括第三晶体管M3和第四晶体管M4。第二下拉子电路包括第五晶体管M5和第六晶体管M6。下面以第一输出电路40_1为例来对输出电路的结构进行说明。
在输出电路40_1中，第一下拉子电路连接至所述第一下拉节点PD_1，并且被配置为在所述第一下拉节点PD_1的电位的控制下，下拉所述第一分上拉节点PU_1和所述第一输出信号端OUT_1的电位。例如，第一下拉子电路包括第三晶体管M3和第四晶体管M4。所述第三晶体管M3的栅极连接至所述第一下拉节点PD_1，所述第三晶体管M3的第一极连接至第一参考信号端LVGL，所述第三晶体管M3的第二极连接至所述第一分上拉节点PU_1。所述第四晶体管M4的栅极连接至所述第一下拉节点PD_1，所述第四晶体管M4的第一极连接至第二参考信号端VGL，所述第四晶体管M4的第二极连接至所述第一输出信号端OUT_1。
在输出电路40_1中，第二下拉子电路连接至第二下拉节点PD_2，并且被配置为在所述第二下拉节点PD_2的电位的控制下，下拉所述第二分上拉节点PU_2和所述第二输出信号端OUT_2的电位。例如，第二下拉子电路包括第五晶体管M5和第六晶体管M6。第五晶体管M5的栅极连接至所述第二下拉节点PD_2，所述第五晶体管M5的第一极连接至所述第一参考信号端LVGL，所述第五晶体管M5的第二极连接至第一分上拉节点PU_1。第六晶体管M6的栅极连接至所述第二下拉节点PD_2，所述第六晶体管M6的第一极连接至所述第二参考信号端VGL，所述第六晶体管M6的第二极连接至所述第一输出信号端OUT_1。
第二输出电路40_2的下拉子电路具有与第一输出电路40_1类似的结构，在此不再赘述。
在一些实施例中，参见图3，每个输出电路40_1和40_2还可以包括复位子电路。复位子电路可以包括第七晶体管M7。以第一输出电路40_1为例，第七晶体管M7的栅极连接至所述复位信号端RST_PU，所述第七晶体管M7的第一极连接至所述参考信号端(例如第一参考信号端LVGL)，第七晶体管M7的第二极连接至所述第一分上拉节点PU_1。第二输出电路40_2的复位子电路具有类似的结构，这里不再赘述。
在图3中，控制电路20可以包括第一控制子电路201和第二控制子电路202。第一控制子电路201连接至所述总上拉节点PU和所述第一下拉节点PD_1，并且被配置为根据所述总上拉节点PU的电位来控制所述第一下拉节点PD_1的电位。第二控制子电路202连接至所述总上拉节点PU和所述第二下拉节点PD_2，并且被配置为根据所述总上拉节点PU的电位来控制所述第二下拉节点的电位PD_2。
第一控制子电路201可以包括第十晶体管M10、第十一晶体管M11、第十二晶体管M12和第十三晶体管M13。所述第十晶体管M10的栅极和其第一极连接至所述移位寄存器单元300的电源信号端(例如电源信号端VDDO)，所述第十晶体管M10的第二极与所述第十一晶体管M11的栅极连接，所述第十一晶体管M11的第一极连接至所述电源信号端(例如电源信号端VDDO)。第十一晶体管M11的第二极连接至所述第一下拉节点PD_1。所述第十二晶体管M12的栅极连接至所述总上拉节点PU，所述第十二晶体管M12的第一极连接至所述移位寄存器单元300的参考信号端(例如第一参考信号端LVGL)，所述第十二晶体管M12的第二极连接至所述第十一晶体管M11的栅极。所述第十三晶体管M13的栅极连接至所述总上拉节点PU，第十三晶体管M13的第一极连接至参考信号端(例如第一参考信号端LVGL)，所述第十三晶体管M13的第二极连接至所述第一下拉节点PD_1。
第二控制子电路202可以包括第十四晶体管M14、第十五晶体管M15、第十六晶体管M16和第十七晶体管M17。所述第十四晶体管M14的栅极和所述第十四晶体管M14的第一极连接至电源信号端(例如电源信号端VDDE)，所述第十四晶体管M14的第二极与所述第十五晶体管M15的栅极连接。所述第十五晶体管M15的第一极连接至电源信号端(例如电源信号端VDDE)，所述第十五晶体管M15的第二极连接至所述第二下拉节点PD_2。所述第十六晶体管M16的栅极连接至所述总上拉节点PU，所述第十六晶体管M16的第一极连接至所述参考信号端(例如第一参考信号端LVGL)，所述第十 六晶体管M16的第二极连接至所述第十五晶体管M15的栅极。所述第十七晶体管M17的栅极连接至所述总上拉节点，所述第十七晶体管M17的第一极连接至所述参考信号端(例如第一参考信号端LVGL)，所述第十七晶体管M17的第二极连接至所述第二下拉节点PD_2。
通过设置第一控制子电路201和第二控制子电路202，来控制N个输出电路40的信号输出，可以将N个输出电路40分为独立的两部分，其中一部分由第一控制子电路201控制来进行信号输出，另一部分由第一控制子电路201控制来进行信号输出。因此，可以可实现对应的两个子像素行中子像素的栅极的交替开、关。
在图3中，级联电路30除了包括第二十二晶体管M22、第二十三晶体管M23和第二电容C2之外，还可以包括第二十四晶体管M24。上文对于第二十二晶体管M22、第二十三晶体管M23的描述同样适用于图3。在图3中，第二十四晶体管M24的栅极连接至所述第一下拉节点PD_1，所述第二十四晶体管M24的栅极连接至所述第二下拉节点PD_2，所述第二十四晶体管M24的第一极连接至所述参考信号端(例如第一参考信号端LVGL)，所述第二十四晶体管M24的第二极连接至所述级联输出端OUT_C。
在图3中，上拉电路10除了包括第十八晶体管M18、第十九晶体管M19和第二十晶体管M20之外，还包括第二十一晶体管M21。与图2不同的是，第十九晶体管M19的栅极连接至第一下拉节点PD_1，第二十晶体管M20的栅极连接至所述移位寄存器单元300的复位信号端RST_PU，第二十晶体管M20的第一极连接至参考信号端(例如第一参考信号端LVGL)，所述第二十晶体管M20的第二极连接至所述总上拉节点PU。
在一些实施例中，参见图3，移位寄存器单元300还包括总复位电路50。总复位电路50可以包括第二十五晶体管M25。所述第二十五晶体管M25的栅极连接至所述移位寄存器单元300的总复位端RST_T，所述第二十五晶体管M25的第一极连接至参考信号端(例如第一参考信号端LVGL)，所述第二十五晶体管M25的第二极连接至所述总上拉节点PU。
图4是根据一些实施例的又一种移位寄存器单元400的电路图。图4的移位寄存器400与图2的移位寄存器200类似，区别至少在于每个输出电路的输入子电路的连接方式。为了简明起见，下面将主要对区别部分进行详细说明。
参见图4，第一输入子电路40_1的输入子电路401除了连接输入信号端INPUT之外还连接至电源信号端VGH。输入子电路401可以基于所述输入信号端INPUT的信号的电位，将所述电源信号端VGH的信号提供至第一分上拉节点PU_1。例如，在输入子 电路401中，第一晶体管M1的栅极连接输入信号端INPUT，第一极连接电源信号端VGH，第二极连接第一分上拉节点PU_1。第二输入子电路40_2的输入子电路401与第一输入子电路40_1类似，这里不再赘述。
在一些实施例中，输入电路10中的第十八晶体管M18也可以采用类似的方式连接。如图14所示，第十八晶体管M18的栅极连接输入信号端INPUT，第十八晶体管M18的第一极连接电源信号端VGH，第十八晶体管M18的第二极连接总上拉节点PU。
由于电源信号端VGH的信号较为稳定，且不会被串扰，因此可以提高移位寄存器单元的工作稳定性。
图5是根据一些实施例的又一种移位寄存器单元的电路图。图5的移位寄存器单元500与图2的移位寄存器单元200类似，区别至少在于输出电路的数量以及时钟信号端的连接方式。为了便于描述，下面将主要对区别部分进行详细说明。
移位寄存器单元500中，N＝4，即包括4个输出电路、4个输出时钟信号端、4个输出信号端和4个分上拉节点。如图5所示，移位寄存器单元500包括第一输出电路40_1、第二输出电路40_2、第三输出电路40_3和第四输出电路40_4。移位寄存器单元500还包括第一输出时钟信号端CLK_1至第四输出时钟信号端CLK_4、第一输出信号端OUT_1至第四输出信号端OUT_4、第一输出上拉结点PU_1至第四输出上拉结点PU_2。每个输出电路连接一个相应的输出时钟信号端、一个相应的输出信号端以及一个相应的分上拉节点。例如，第一输出电路40_1连接第一输出时钟信号端CLK_1、第一输出信号端OUT_1和第一输出上拉结点PU_1，第二输出电路40_2连接第二输出时钟信号端CLK_2、第二输出信号端OUT_2和第一输出上拉结点PU_3，以此类推。如图5所示，第一输出电路40_1、第二输出电路40_2、第三输出电路40_3和第四输出电路40_4各自的结构及其连接方式与以上参考图2描述输出电路类似，这里不再赘述。
在图5中，第一输出时钟信号端CLK_1与控制时钟信号端CLK_C连接作为一个信号端。通过这种方式，可以减少布线，进一步简化电路结构。
虽然以图5为例说明了第一输出时钟信号端CLK_1与控制时钟信号端CLK_C可以彼此连接，然而本公开的实施例不限于此。在上述任意实施例的移位寄存器单元中，可以将N个输出时钟信号端中的一个与控制时钟信号端CLK_C连接。
虽然图5的实施例在图2的移位寄存器单元的基础上增加了输出电路的数量，然而本公开的实施例不限于此。以上任意实施例的移位寄存器单元的输出电路的数量均可以根据需要来设置。例如上述移位寄存器单元300和400的输出电路的数量均可以设置为 3个、4个或更多个。
本公开的一些实施提供了一种栅极驱动电路，下面将参考图6和图7对此进行说明。
图6是根据一些实施例的一种栅极驱动电路的结构示意图。
参见图6，栅极驱动电路包括M级级联的移位寄存器单元GOA1，GOA2，…，GOAM，每个移位寄存器单元可以由上述任意实施例的移位寄存器单元来实现。图6中为了便于描述以M＝3进行了示意，即GOA1、GOA2和GOA3。如图6所示，第m级移位寄存器单元GOAm的输入信号端INPUT与第m-1级移位寄存器单元GOA(m-1)的级联输出端OUT_C连接，第m级移位寄存器单元GOAm的复位信号端RST_PU与第m+2级移位寄存器单元GOA(m+2)的级联输出端OUT_C连接，其中M为大于1的整数，m为整数且1＜m＜M-1。如图6所示，M级级联的移位寄存器单元GOA1，GOA2，…，GOAM连接至K条时钟信号线，其中K为大于或等于2N的偶数。
参见图6，N＝4，K＝12，即栅极驱动电路与12个时钟信号线连接，栅极驱动电路中的每个移位寄存器单元具有4个输出电路，例如可以由以上参考图5描述的移位寄存器单元来实现。所述M级级联的移位寄存器单元GOA1，GOA2，…，GOAM分为多组，每组包括3级级联的第一移位寄存器单元、第二移位寄存器单元和第三移位寄存器单元。例如在图6中，第一组包括第一级至第三级移位寄存器单元GOA1、GOA2和GOA3分别作为第一组中的第一至第三移位寄存器单元，第二组包括第四至第六级移位寄存器单元GOA4、GOA5和GOA6分别作为第二组中的第一至第三移位寄存器单元，以此类推。
以第一组为例，该组中的第一移位寄存器单元GOA1的4个输出时钟信号端CLK_1至CLK_4与第一时钟信号线CLK1至第四时钟信号线CLK4一一对应地连接，第二移位寄存器GOA2单元的4个输出时钟信号端CLK_1至CLK_4与第五时钟信号线CLK5至第八时钟信号线CLK8一一对应地连接，第三移位寄存器单元GOA3的4个输出时钟信号端CLK_1至CLK_4与第九时钟信号线CLK9至第十二时钟信号线CLK12一一对应地连接。
类似地，第二组中的第一移位寄存器单元GOA4的4个输出时钟信号端CLK_1至CLK_4与第一时钟信号线CLK1至第四时钟信号线CLK4一一对应地连接，第二移位寄存器GOA5单元的4个输出时钟信号端CLK_1至CLK_4与第五时钟信号线CLK5至第八时钟信号线CLK8一一对应地连接，第三移位寄存器单元GOA6的4个输出时钟信号端CLK_1至CLK_4与第九时钟信号线CLK9至第十二时钟信号线CLK12一一对应地连接，以此类推。
在图6中，第一级移位寄存器单元GOA1的输入信号端INPUT连接启动信号线STV以接收启动信号。
在工作中，第一级移位寄存器单元GOA1在时钟信号线CLK1至CLK4上的时钟信号的控制下，基于启动信号线STV上的信号在4个输出信号端OUT_1至OUT_4分别输出4个输出信号G1至G4，并在级联输出端OUT_C输出级联信号至第二级移位寄存器单元GOA2的输入信号端INPUT。第二级移位寄存器单元GOA2在时钟信号线CLK5至CLK8的控制下，基于输入信号端INPUT处的级联信号在4个输出信号端OUT_1至OUT_4分别输出4个输出信号G5至G8，以此类推。
图7是根据一些实施例的另一种栅极驱动电路的结构示意图。图7的栅极驱动电路与图6类似，区别至少在于K＝8，即，栅极驱动电路与8个时钟信号线连接。
如图7所示，栅极驱动电路包括M级级联的移位寄存器单元GOA1，GOA2，…，GOAM。图7中为了便于描述以M＝3进行了示意，即GOA1、GOA2和GOA3。每个移位寄存器单元可以由上述实施例中具有4个输出电路(即N＝4)的移位寄存器单元来实现，例如可以由以上参考图5描述的移位寄存器单元来实现。
类似于图6，第m级移位寄存器单元GOAm的输入信号端INPUT与第m-1级移位寄存器单元GOA(m-1)的级联输出端OUT_C连接，第m级移位寄存器单元GOAm的复位信号端RST_PU与第m+2级移位寄存器单元GOA(m+2)的级联输出端OUT_C连接，其中M为大于1的整数，m为整数且1＜m＜M-1。
如图7所示，M级级联的移位寄存器单元GOA1，GOA2，…，GOAM连接至8条时钟信号线CLK1至CLK8。M级级联的移位寄存器单元GOA1，GOA2，…，GOAM分为多组，每组包括2级级联的第一移位寄存器单元和第二移位寄存器单元。例如在图7中，第一组包括第一级和第二级移位寄存器单元GOA1、GOA2分别作为第一组中的第一和第二移位寄存器单元，第二组包括第三级和第六级移位寄存器单元GOA3、GOA4分别作为第二组中的第一和第二移位寄存器单元，以此类推。以第一组为例，该组中的第一移位寄存器单元GOA1的4个输出时钟信号端CLK_1至CLK_4与第一时钟信号线CLK1至第四时钟信号线CLK4一一对应地连接，第二移位寄存器单元GOA2的4个输出时钟信号端CLK_1至CLK_4与第五时钟信号线CLK5至第八时钟信号线CLK8一一对应地连接。第二组中的移位寄存器单元GOA3和GOA4以类似的方式连接时钟信号线CLK1至CLK8，这里不再赘述。
在图6和图7的栅极驱动电路中，每个移位寄存器单元的N个输出时钟信号端 CLK_1至CLK_N中的第一输出时钟信号端CLK_1与该移位寄存器单元的控制时钟信号端连接CLK_C，使得第一输出电路和级联电路基于同一个时钟信号来产生输出，从而在第一输出信号端OUT_1和级联输出端OUT_C输出波形相同的信号。
图8是根据一些实施例的又一种栅极驱动电路的结构示意图。图8的栅极驱动电路与图7类似，区别至少在于N＝2，K＝6，即，栅极驱动电路与6个时钟信号线连接，栅极驱动电路的每个移位寄存器单元可以由上述实施例中具有2个输出电路的移位寄存器单元来实现。
参见图8，栅极驱动电路包括M级级联的移位寄存器单元GOA1，GOA2，…，GOAM。图8中为了便于描述以M＝3进行了示意，即GOA1、GOA2和GOA3。每个移位寄存器单元可以由上述实施例中具有2个输出电路的移位寄存器单元来实现，例如可以由以上参考图2至图4描述的任意移位寄存器单元来实现。
类似于图7，第m级移位寄存器单元GOAm的输入信号端INPUT与第m-1级移位寄存器单元GOA(m-1)的级联输出端OUT_C连接，第m级移位寄存器单元GOAm的复位信号端RST_PU与第m+2级移位寄存器单元GOA(m+2)的级联输出端OUT_C连接，其中M为大于1的整数，m为整数且1＜m＜M-1。
参见图8，6个时钟信号线包括第一控制时钟信号线CLKC1、第二控制时钟信号线CLKC2、第一输出时钟信号线CLK1、第二输出时钟信号线CLK2、第三输出时钟信号线CLK3和第四输出时钟信号线CLK4。
所述M级级联的移位寄存器单元GOA1，GOA2，…，GOAM分为多组，每组包括2级级联的第一移位寄存器单元和第二移位寄存器单元。例如在图8中，第一组包括第一级和第二级移位寄存器单元GOA1、GOA2分别作为第一组中的第一和第二移位寄存器单元，第二组包括第三级和第六级移位寄存器单元GOA3、GOA4分别作为第二组中的第一和第二移位寄存器单元，以此类推。以第一组为例，第一移位寄存器单元GOA1的2个输出时钟信号端CLK_1和CLK_2与第一输出时钟信号线CLK1和第二输出时钟信号线CLK2一一对应地连接，第一移位寄存器单元GOA1的控制时钟信号端CLK_C与第一控制时钟信号线CLKC1连接，第二移位寄存器单元GOA2的2个输出时钟信号端CLK_1和CLK_2与第三时钟信号线CLK3和第四时钟信号线CLK4一一对应地连接，第二移位寄存器单元GOA2的控制时钟信号端CLK_C与第二控制时钟信号线CLKC2连接。第二组中的移位寄存器单元GOA3和GOA4以类似的方式连接时钟信号线CLKC1、CLKC2、CLK1-CLK8，这里不再赘述。
在图8的栅极驱动电路中，每个移位寄存器单元的N个输出时钟信号端CLK_1至CLK_N与该移位寄存器单元的控制时钟信号端CLK_C彼此分离，使得级联电路可以相对于N个输出电路而被独立的时钟控制，提高了控制灵活性。
图9是根据一些实施例的移位寄存器单元的驱动方法的信号时序图。该方法适用于上述任意实施例的移位寄存器单元。下面以图2所示的移位寄存器单元为例，对该驱动方法进行示例性的介绍。
在第一时段T1，上拉电路10将输入信号端INPUT的第一电平提供至总上拉节点PU，N个输出电路40中的第n输出电路40将所述输入信号端INPUT的第一电平输入至所述第n分上拉节点PU_n。结合图2，在该时段，输入信号端INPUT的高电平使晶体管M11导通，从而将输入信号端INPUT的高电平提供至总上拉节点PU，上拉节点PU的高电平使晶体管M22导通。输入信号端INPUT的高电平还使第一输出电路40_1和第二输出电路40_2各自的晶体管M1导通，从而将输入信号端INPUT的高电平分别提供至第一分上拉节点PU_1和第二分上拉节点PU_2。第一分上拉节点PU_1的高电平使第一输出电路40_1中的晶体管M2导通，第二分上拉节点PU_2的高电平使第二输出电路40_2中的晶体管M2导通。
在第二时段T2，级联电路30在所述总上拉节点PU的电位的控制下将控制时钟信号端CLK_C的信号提供至级联输出端OUT_C，并且N个输出电路40中的第n输出电路40在第n分上拉节点PU_n的电位的控制下将第n输出时钟信号端CLK_n的信号提供至第n输出信号端OUT_n。结合图2，在该时段，第一输出时钟信号端CLK_1和第二输出时钟信号端CLK_2的高电平依次到来，由于第一输出电路40_1和第二输出电路40_2各自的晶体管M2均处于导通状态，所以分别将第一输出时钟信号端CLK_1和第二输出时钟信号端CLK_2的信号提供至第一输出信号端OUT_1和第二输出信号端OUT_2。在此期间，由于电容C1的自举作用，第一输出信号端OUT_1和第二输出信号端OUT_2的高电平分别使第一分上拉节点PU_1和第二分上拉节点PU_2的电位进一步提高。
控制时钟信号端CLK_C处的信号与第一输出时钟信号端CLK_1处的信号相同，同样，由于晶体管M22处于导通状态，控制时钟信号端CLK_C处的信号被提供至级联输出端OUT_C。
在第三时段T3，上拉电路10将复位信号端RST_PU的第二电平提供至所述总上拉节点PU，上拉节点PU的电位使控制电路20将所述下拉节点PD控制为第一电平，下 拉节点PD的电位使得级联电路30将级联输出端OUT_C下拉至第二电平，并且使得N个输出电路40中的第n输出电路40将第n输出信号端OUT_n下拉至第二电平。结合图2，在该时段，复位信号端RST_PU为高电平，晶体管M20导通，从而将总上拉节点PU下拉至第一参考信号端LVGL的低电平。总上拉节点PU的低电平使晶体管M9关断，从而下拉节点PD变为高电平。下拉节点PD的高电平使晶体管M23以及第一输出电路40_1和第二输出电路40_2各自的晶体管M3和M4均导通。晶体管M23的导通使得级联输出端OUT_C被下拉至第一参考信号端LVGL的低电平。两个晶体管M3的导通使第一分上拉节点PU_1和第二分上拉节点PU_12被下拉至第一参考信号端LVGL的低电平。两个晶体管M4的导通使第一输出信号端OUT_1和第二输出信号端OUT_2被下拉至第二参考信号端VGL的低电平。
本公开的一些实施例中还提供了一种栅极驱动电路的驱动方法，该方法包括：在第一模式下，向所述K条时钟信号线施加逐行顺序移位的K个第一时钟信号，使得栅极驱动电路的M级移位寄存器单元产生逐行顺序移位的多个第一输出信号；在第二模式下，向所述K条时钟信号线施加逐k行顺序移位的K个第二时钟信号，使得栅极驱动电路的M级移位寄存器单元产生逐k行顺序移位的多个第二输出信号，其中在所述K个第二时钟信号的频率是所述K个第一时钟信号的k倍，其中k为小于或等于K的整数。下面将参考图10和图11来对该方法进行示例说明。
图10是根据一些实施例的一种栅极驱动电路的驱动方法在第一模式下的信号时序图；图11是根据一些实施例的一种栅极驱动电路的驱动方法在第二模式下的信号时序图。该方法适用于上述任意实施例的栅极驱动电路。下面将以图6的栅极驱动电路为例对该驱动方法进行示例性的介绍。
参见图10和图6，在第一模式下，向栅极驱动电路的12条时钟信号线CLK1至CLK12施加逐行顺序移位的12个第一时钟信号，使得栅极驱动电路的M级移位寄存器单元GOA1，GOA2，…，GOAM产生逐行顺序移位的多个第一输出信号G1，G2，…GM。12个第一时钟信号可以是周期信号，所谓逐行移位指的是第二时钟信号线CLK2上的第一时钟信号相对于第一时钟信号线上的第一时钟信号而移位，第三时钟信号线CLK3上的第一时钟信号相对于第二时钟信号线CKK2上的第一时钟信号而移位，以此类推。移位大小可以相等，例如均为H或者H的整数倍，其中H表示扫描一行子像素需要的时间，也称作单位扫描时间。
结合图6，在扫描开始时，启动信号线STV上的信号为高电平，第一级移位寄存器 单元GOA1在时钟信号线CLK1至CLK4上的时钟信号的控制下，基于启动信号线STV上的信号在4个输出信号端OUT_1至OUT_4分别输出4个顺序移位的输出信号G1至G4，并在级联输出端OUT_C输出与输出信号G1相同的级联信号至第二级移位寄存器单元GOA2的输入信号端INPUT。第二级移位寄存器单元GOA2基于输入信号端INPUT处接收到的级联信号，在时钟信号线CLK5至CLK8的控制下在4个输出信号端OUT_1至OUT_4分别输出4个顺序移位输出信号G5至G8。在图10中虚线指示的时刻，第4级移位寄存器单元GOA4产生高电平的输出信号G9以及与G9相同的级联信号。该级联信号被第一级移位寄存器GOA1的复位信号端RST_PU接收，使得第一级移位寄存器GOA1的总上拉节点PU和四个分上拉节点PU_1至PU_4均被拉低，从而实现复位。以此类推，通过这种方式，栅极驱动电路输出了顺序移位的输出信号G1，G2，…GM。
参见图11和图6，在第二模式下，向栅极驱动电路的12条时钟信号线CLK1至CLK12施加逐k行(例如，图11中k＝2)顺序移位的12个第二时钟信号，使得栅极驱动电路的M级移位寄存器单元产生逐k行顺序移位的多个第二输出信号G1至G4，其中在所述12个第二时钟信号的频率是所述12个第一时钟信号CLK1至CLK12的k倍。例如在图11中，第一时钟信号线CLK1和第二时钟信号线CLK2上的第一时钟信号相同，第三时钟信号线CLK3和第四时钟信号线CLK3上的第一时钟信号相同，并且相对于第一和第二时钟信号线CLK1和CLK2上的第一时钟信号而移位。同样，第五和第六时钟信号线CLK5和CLK6上的时钟信号相同，并且相对于第三和第四时钟信号线CLK3和CLK4上的第一时钟信号而移位，以此类推。
结合图6，在扫描开始时，启动信号STV为高电平，栅极驱动电路的第一级移位寄存器单元GOA1基于启动信号STV，在第一至第四时钟信号线CLK1-CLK4上的第一时钟信号的控制下产生4个输出信号G1至G4，其中输出信号G1和G2相同，输出信号G3和G4相同并且相对于输出信号G1和G2而移位。以此类推，可以实现每两行同时扫描。在图11的第二模式下，时钟信号线CLK1至CLK12上的12个第二时钟信号的频率是图10中12个第一时钟信号CLK1至CLK12的2倍，从而提高了扫描速度。像素数据线充电的时间可以同第一模式一样(仍为1H，因为是两行像素同时充电)，因此不降低画质，从而实现2倍刷新率驱动显示。
虽然在图11中以K＝12，k＝2为例进行了说明，然而本公开的实施例不限于此，k和K可以根据需要设置为小于等于K的其他整数。例如，K＝12，k＝4，也就是说在采用12个时钟信号的情况下，在第二模式下可以进行逐4行扫描，驱动原理与上述类似， 不同的是第二模式下使用的第二时钟信号的频率是第一模式下使用的第一时钟信号的频率的1/4。类似地，在K＝8的情况下，也可以进行逐2行扫描(k＝2)，或者逐4行扫描(k＝4)。
虽然上文以图6的栅极驱动电路为例对图10和图11的驱动方法进行了说明，然而本公开的的实施例不限于此。上述驱动方法还适用于其他栅极驱动电路，例如K＝8，N＝4的栅极驱动电路，例如图7的栅极驱动电路。在该驱动方法应用于图7的栅极驱动电路时，分别向8条时钟信号线CLK1至CLK8施加8个时钟信号。在第一模式下，时钟信号线CLK1至CLK8上的第一时钟信号的脉宽为4H，占空比为50％；在第二模式下，时钟信号线CLK1至CLK8上的第二时钟信号的脉宽为2H，占空比仍为50％，频率是第一时钟信号的2倍。
本公开的实施例还提供了另一种栅极驱动电路的驱动方法，该栅极电路连接的K条时钟信号线包括多条输出时钟信号线，所述方法包括：在第一模式下，向所述多条输出时钟信号线施加逐行顺序移位的多个第一输出时钟信号，使得栅极驱动电路的M级移位寄存器单元产生逐行顺序移位的多个第一输出信号，其中每级移位寄存器单元的N个输出电路均产生输出信号；在第二模式下，向所述多条输出时钟信号线中的一部分输出时钟信号线施加多个第二输出时钟信号，使得栅极驱动电路的M级移位寄存器单元产生顺序移位的多个第二输出信号，其中每级移位寄存器的N个输出电路中的至少一个输出电路不产生输出信号。下面将参考图12和图13来对该方法进行示例说明。
图12是根据一些实施例的另一种栅极驱动电路的驱动方法在第一模式下的信号时序图；图13是根据一些实施例的另一种栅极驱动电路的驱动方法在第二模式下的信号时序图。该方法适用于移位寄存器单元的控制时钟信号端CLK_C与输出信号端CLK_1至CLK_N分离的栅极驱动电路，例如以上参考图8描述的栅极驱动电路。
下面将参照图12和13，以图8所示的栅极驱动电路为例，对该驱动方法进行实示例性介绍。
参见图12和图8，在第一模式下，向栅极驱动电路的4个输出时钟信号线CLK1至CLK4施加逐行顺序移位的4个第一输出时钟信号，使得栅极驱动电路的M级移位寄存器单元GOA1，GOA2，…，GOAM产生逐行顺序移位的多个第一输出信号G1，G2，…GM，其中每级移位寄存器单元的2个输出电路均产生输出信号。在一些实施例中，第一输出时钟信号的脉宽为4H，占空比为50％。
例如，结合图8，可以向所述第一控制时钟信号线CLKC1施加第一控制时钟信号， 向所述第二控制时钟信号线CLKC2施加第二控制时钟信号，并且向第一输出时钟信号线CLK1、第二输出时钟信号线CLK2、第三输出时钟信号线CLK3和第四输出时钟信号线CLK4分别施加顺序移位的四个第一输出时钟信号，使得每级移位寄存器单元GOA1，GOA2，…，GOAM的2个输出电路均产生输出信号。
如图12所示，在扫描开始时，启动信号线STV上的信号为高电平，第一级移位寄存器单元GOA1在输出时钟信号线CLK1和CLK2上的时钟信号的控制下，基于启动信号线STV上的信号在2个输出信号端OUT_1和OUT_2分别输出2个顺序移位的输出信号G1和G2，并在控制时钟信号线CLKC1上的控制时钟信号的控制下在级联输出端OUT_C输出级联信号。该级联信号被提供至第二级移位寄存器单元GOA2的输入信号端INPUT。第二级移位寄存器单元GOA2基于输入信号端INPUT处接收到的级联信号，在输出时钟信号线CLK3和CLK4的控制下在2个输出信号端OUT_1和OUT_2分别输出2个顺序移位输出信号G3和G4，并在控制时钟信号线CLKC2上的控制时钟信号的控制下在级联输出端OUT_C输出级联信号。以此类推，通过这种方式，栅极驱动电路输出了顺序移位的输出信号G1，G2，…GM。
参见图13和图8，在第二模式下，向所述输出时钟信号线CLK1至CLK4中的一部分输出时钟信号线(在图13中是偶数输出时钟信号线CLK2和CLK4)施加第二输出时钟信号，使得栅极驱动电路的M级移位寄存器单元GOA1，GOA2，…，GOAM产生顺序移位的多个第二输出信号G2，G4，G6，…，其中每级移位寄存器单元的2个输出电路中的至少一个输出电路不产生输出信号。
例如，结合图8，可以向所述第一控制时钟信号线CLKC1施加所述第一控制时钟信号CLKC1，向所述第二控制时钟信号线CLKC2施加所述第二控制时钟信号CLKC2，并且向第一输出时钟信号线CLK1、第二输出时钟信号线CLK2、第三输出时钟信号线CLK3和第四输出时钟信号线CLK4中的奇数或偶数输出时钟信号线分别施加顺序移位的两个第二输出时钟信号，使得每级移位寄存器单元的2个输出电路之一产生输出信号。在图13的示例中，每个移位寄存器单元的第一输出电路由于没有接收到时钟信号而不产生输出，而第二输出电路基于接收到的时钟信号产生输出，使得第一级移位寄存器单元GOA1产生输出信号G2，第二级移位寄存器单元GOA2产生输出信号G4，以此类推，实现了像素的奇数行关闭、偶数行被扫描，反之亦然。例如，可以向输出时钟信号线CLK1和CLK3施加输出时钟信号，而不向输出时钟信号线CLK2和CLK4施加输出时钟信号，使得每一级移位寄存器单元的第二输出电路产生信号，而第一输出电路不产生 输出信号，由此实现像素的偶数行关闭、奇数行被扫描。
通过关闭某一个或多个输出信号，使某一个或多个子像素行的栅极保持关闭，避免写入数据信号。这样，可避免因数据信号负载大及切换时间短而引起的延迟，从而可以避免错误地将数据信号写入相邻的子像素行而产生串行问题，提高显示装置的显示质量。例如，可以关闭位于奇数子像素行的子像素的栅极，而使位于偶数自像素行的子像素的栅极正常开启以写入相应的数据信号。这样，即使某一行偶数子像素行的数据信号的传输产生了延迟，由于其下一奇数子像素行的各子像素的栅极是关闭的，因此，也不会发生将该偶数子像素行的数据信号写入至其后的奇数自像素行的现象，因此可以避免图像显示过程中的显示串行现象的发生。
在一些实施例中，可以在一帧中采用偶数行扫描的方式产生栅极驱动信号，在下一帧采用奇数行扫描的方式产生栅极驱动信号。通过在不同帧之间交替奇数行和偶数行关闭模式，利用人眼的视觉暂留现象，可以实现帧间叠加显示完整画面的效果。
图14是根据一些实施例的又一种栅极驱动电路的驱动方法在第一模式和第二模式下的信号时序图。图14所示的驱动方法与以上参考图12和图13描述的驱动方法类似，区别至少在于图14中在第二模式下向输出时钟信号线CLK1和CLK3施加输出时钟信号，而不向输出时钟信号线CLK2和CLK4施加输出时钟信号，使得每一级移位寄存器单元的第二输出电路产生信号，而第一输出电路不产生输出信号，由此实现像素的偶数行关闭、奇数行被扫描。
参见图14，在第二模式下向输出时钟信号线CLK1至CLK4施加的第二输出时钟信号的周期与第一模式下向时钟信号线CLK1至CLK4施加的第一输出时钟信号的周期相等，而占空比大于所述第一输出时钟信号的占空比，例如前者的有效电平持续时间比后者长T，T≤H。这种情况下，可以相比于第一模式将数据信号Data的脉冲宽度也相应增加T，使得每个奇数行的充电时间增加T，从而提高充电率。下帧显示时，奇数行关闭，采用同样的原理增加充电时间。
需要说明的是，虽然上述实施例中在第二模式下以奇偶切换的方式为例进行了说明，但本公开的实施例并不限于此。栅极驱动电路的移位寄存器单元的多个输出电路可以根据需要被切换，以产生不同的栅极驱动信号。例如，对于栅极驱动电路的各个移位寄存器单元具有4个输出电路的情况，可以通过时钟信号来控制各移位寄存器单元在一帧中第一输出电路关闭，第二至第四输出电路产生输出；而在下一帧中第一输出电路产生输出，而第二值第四输出电路关闭，由此实现1∶3切换。其他切换方式也是允许的， 本公开对此不作限制。
本领域的技术人员可以理解，上面所描述的实施例都是示例性的，并且本领域的技术人员可以对其进行改进，各种实施例中所描述的结构在不发生结构或者原理方面的冲突的情况下可以进行自由组合。
在详细说明本公开的较佳实施例之后，熟悉本领域的技术人员可清楚的了解，在不脱离随附权利要求的保护范围与精神下可进行各种变化与改变，且本公开亦不受限于说明书中所举示例性实施例的实施方式。

Claims (32)

  1. 一种移位寄存器单元，包括：
    上拉电路，连接至所述移位寄存器单元的输入信号端、总上拉节点和下拉节点，所述上拉电路被配置为将输入信号端的信号提供至所述总上拉节点，并在所述下拉节点的电位的控制下下拉所述总上拉节点的电位；
    控制电路，连接至所述总上拉节点和所述下拉节点，所述控制电路被配置为根据所述总上拉节点的电位来控制所述下拉节点的电位；
    级联电路，连接至所述总上拉节点、所述下拉节点以及所述移位寄存器单元的级联输出端和控制时钟信号端，所述级联电路被配置为在所述总上拉节点的电位的控制下将所述控制时钟信号端的信号提供至所述级联输出端，以及在所述下拉节点的电位的控制下下拉所述级联输出端的电位；
    N个输出电路，分别连接至所述输入信号端、所述下拉节点以及所述移位寄存器单元的N个输出时钟信号端、N个分上拉节点和N个输出信号端，其中第n输出电路连接至所述输入信号端、所述下拉节点、第n输出信号端和第n分上拉节点，并且被配置为将所述输入信号端的信号输入至所述第n分上拉节点，在第n分上拉节点的电位的控制下将所述第n输出时钟信号端的信号提供至第n输出信号端，以及在所述下拉节点的电位的控制下下拉所述第n输出信号端的电位，其中N为大于1的整数，n为整数且1≤n≤N。
  2. 根据权利要求1所述的移位寄存器单元，其中，第n输出电路包括：
    输入子电路，连接至所述输入信号端和所述第n分上拉节点，并且被配置为将所述输入信号端的信号提供至所述第n分上拉节点；
    输出子电路，连接至所述第n分上拉节点、所述第n输出时钟信号端以及所述第n输出信号端，并且被配置为在所述第n分上拉节点的电位的控制下将所述第n输出时钟信号端的信号提供至所述第n输出信号端；以及，
    下拉子电路，连接至所述下拉节点，并且被配置为在所述下拉节点的电位的控制下，下拉所述第n分上拉节点和所述第n输出信号端的电位。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述下拉节点包括第一下拉节点和第二下拉节点，所述下拉子电路包括第一下拉子电路和第二下拉子电路，其中，
    所述第一下拉子电路连接至所述第一下拉节点，并且被配置为在所述第一下拉节点的电位的控制下，下拉所述第n分上拉节点和所述第n输出信号端中至少之一的电 位；
    所述第二下拉子电路连接至所述第二下拉节点，并且被配置为在所述第二下拉节点的电位的控制下，下拉所述第n分上拉节点和所述第n输出信号端中至少之一的电位。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述控制电路包括：
    第一控制子电路，连接至所述总上拉节点和所述第一下拉节点，并且被配置为根据所述总上拉节点的电位来控制所述第一下拉节点的电位；
    第二控制子电路，连接至所述总上拉节点和所述第二下拉节点，并且被配置为根据所述总上拉节点的电位来控制所述第二下拉节点的电位。
  5. 根据权利要求2或3所述的移位寄存器单元，其中，第n输出电路还包括：
    复位子电路，连接至所述第n分上拉节点以及所述移位寄存器单元的复位信号端和参考信号端，并且被配置为在所述复位信号端的信号的控制下利用所述参考信号端的电位来复位所述第n分上拉节点。
  6. 根据权利要求2至5中任一项所述的移位寄存器单元，其中，所述输入子电路还连接至电源信号端，并且被配置为在所述输入信号端的信号的控制下将所述电源信号端的电位提供至所述第n分上拉节点。
  7. 根据权利要求1至6中任一项所述的移位寄存器单元，其中，所述N个输出时钟信号端中的第一输出时钟信号端与所述控制时钟信号端连接。
  8. 根据权利要求2所述的移位寄存器单元，其中，所述输入子电路包括：第一晶体管，所述第一晶体管的栅极和所述第一晶体管的第一极连接至所述输入信号端，所述第一晶体管的第二极连接至所述第n分上拉节点。
  9. 根据权利要求6所述的移位寄存器单元，其中，所述输入子电路包括：第一晶体管，所述第一晶体管的栅极连接至所述输入信号端，所述第一晶体管的第一极连接至所述电源信号端，所述第一晶体管的第二极连接至所述第n分上拉节点。
  10. 根据权利要求2所述的移位寄存器单元，其中，所述输出子电路包括：
    第二晶体管，所述第二晶体管的栅极连接至所述第n分上拉节点，所述第二晶体管的第一极连接至所述第n输出时钟信号端，所述第二晶体管的第二极连接至所述第n输出信号端；以及
    第一电容，所述第一电容的第一端连接至所述第n分上拉节点，所述第一电容的第二端连接至所述第n输出信号端。
  11. 根据权利要求2所述的移位寄存器单元，其中，所述下拉子电路包括：
    第三晶体管，所述第三晶体管的栅极连接至所述下拉节点，所述第三晶体管的第一极连接至所述移位寄存器单元的第一参考信号端，所述第三晶体管的第二极连接至所述第n分上拉节点；
    第四晶体管，所述第四晶体管的栅极连接至所述下拉节点，所述第四晶体管的第一极连接至所述移位寄存器单元的第二参考信号端，所述第四晶体管的第二极连接至所述第n输出信号端。
  12. 根据权利要求3所述的移位寄存器单元，其中，
    所述第一下拉子电路包括第三晶体管和第四晶体管，所述第三晶体管的栅极连接至所述第一下拉节点，所述第三晶体管的第一极连接至所述移位寄存器单元的第一参考信号端，所述第三晶体管的第二极连接至所述第n分上拉节点，所述第四晶体管的栅极连接至所述第一下拉节点，所述第四晶体管的第一极连接至所述移位寄存器单元的第二参考信号端，所述第四晶体管的第二极连接至所述第n输出信号端；
    所述第二下拉子电路包括第五晶体管和第六晶体管，所述第五晶体管的栅极连接至所述第二下拉节点，所述第五晶体管的第一极连接至所述第一参考信号端，所述第五晶体管的第二极连接至所述第n分上拉节点，所述第六晶体管的栅极连接至所述第二下拉节点，所述第六晶体管的第一极连接至所述第二参考信号端，所述第六晶体管的第二极连接至所述第n输出信号端。
  13. 根据权利要求5所述的移位寄存器单元，其中，所述复位子电路包括第七晶体管，所述第七晶体管的栅极连接至所述复位信号端，所述第七晶体管的第一极连接至所述参考信号端，所述第七晶体管的第二极连接至所述第n分上拉节点。
  14. 根据权利要求1所述的移位寄存器单元，其中，所述控制电路包括：
    第八晶体管，所述第八晶体管的栅极和所述第八晶体管的第一极连接至所述移位寄存器单元的电源信号端，所述第八晶体管的第二极连接至所述下拉节点；
    第九晶体管，所述第九晶体管的栅极连接至所述总上拉节点，所述第九晶体管的第一极连接至所述移位寄存器单元的参考信号端，所述第九晶体管的第二极连接至所述下拉节点。
  15. 根据权利要求4所述的移位寄存器单元，其中，
    所述第一控制子电路包括第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管，所述第十晶体管的栅极和所述第十晶体管的第一极连接至所述移位寄存器单元 的电源信号端，所述第十晶体管的第二极与所述第十一晶体管的栅极连接，所述第十一晶体管的第一极连接至所述电源信号端，所述第十一晶体管的第二极连接至所述第一下拉节点，所述第十二晶体管的栅极连接至所述总上拉节点，所述第十二晶体管的第一极连接至所述移位寄存器单元的参考信号端，所述第十二晶体管的第二极连接至所述第十一晶体管的栅极，所述第十三晶体管的栅极连接至所述总上拉节点，所述第十三晶体管的第一极连接至所述参考信号端，所述第十三晶体管的第二极连接至所述第一下拉节点；
    所述第二控制子电路包括第十四晶体管、第十五晶体管、第十六晶体管和第十七晶体管，所述第十四晶体管的栅极和所述第十四晶体管的第一极连接至所述电源信号端，所述第十四晶体管的第二极与所述第十五晶体管的栅极连接，所述第十五晶体管的第一极连接至所述电源信号端，所述第十五晶体管的第二极连接至所述第二下拉节点，所述第十六晶体管的栅极连接至所述总上拉节点，所述第十六晶体管的第一极连接至所述参考信号端，所述第十六晶体管的第二极连接至所述第十五晶体管的栅极，所述第十七晶体管的栅极连接至所述总上拉节点，所述第十七晶体管的第一极连接至所述参考信号端，所述第十七晶体管的第二极连接至所述第二下拉节点。
  16. 根据权利要求1所述的移位寄存器单元，其中，所述上拉电路包括：
    第十八晶体管，所述第十八晶体管的栅极和所述第十八晶体管的第一极连接至所述输入信号端，所述第十八晶体管的第二极连接至所述总上拉节点；
    第十九晶体管，所述第十九晶体管的栅极连接至所述下拉节点，所述第十九晶体管的第一极连接至所述移位寄存器单元的参考信号端，所述第十九晶体管的第二极连接至所述总上拉节点，
    第二十晶体管，所述第二十晶体管的栅极连接至所述移位寄存器单元的复位信号端，所述第二十晶体管的第一极连接至所述参考信号端，所述第二十晶体管的第二极连接至所述总上拉节点。
  17. 根据权利要求16所述的移位寄存器单元，其中，所述下拉节点包括第一下拉节点和第二下拉节点，所述上拉电路还包括第二十一晶体管，其中，
    所述第十九晶体管的栅极连接至所述第一下拉节点，所述第二十一晶体管的栅极连接至所述第二下拉节点，所述第二十一晶体管的第一极连接至所述参考信号端，所述第二十一晶体管的第二极连接至所述总上拉节点。
  18. 根据权利要求1所述的移位寄存器单元，其中，所述级联电路包括：
    第二十二晶体管，所述第二十二晶体管的栅极连接至所述总上拉节点，所述第二十二晶体管的第一极连接至所述控制时钟信号端，所述第二十二晶体管的第二极连接至所述级联输出端；
    第二十三晶体管，所述第二十三晶体管的栅极连接至所述下拉节点，所述第二十三晶体管的第一极连接至所述移位寄存器单元的参考信号端，所述第二十三晶体管的第二极连接至所述级联输出端；
    第二电容，所述第二电容的第一端连接至所述第二十二晶体管的栅极，所述第二电容的第二端连接至所述级联输出端。
  19. 根据权利要求18所述的移位寄存器单元，其中，所述下拉节点包括第一下拉节点和第二下拉节点，所述级联电路还包括第二十四晶体管，其中，
    所述第二十四晶体管的栅极连接至所述第一下拉节点，所述第二十四晶体管的栅极连接至所述第二下拉节点，所述第二十四晶体管的第一极连接至所述参考信号端，所述第二十四晶体管的第二极连接至所述级联输出端。
  20. 根据权利要求1所述的移位寄存器单元，还包括总复位电路，所述总复位电路包括第二十五晶体管，所述第二十五晶体管的栅极连接至所述移位寄存器单元的总复位端，所述第二十五晶体管的第一极连接至所述移位寄存器单元的参考信号端，所述第二十五晶体管的第二极连接至所述总上拉节点。
  21. 根据权利要求1至20中任一项所述的移位寄存器单元，其中，2≤N≤8。
  22. 一种栅极驱动电路，包括M级级联的移位寄存器单元，所述移位寄存器单元是如权利要求1至21中任一项所述的移位寄存器单元，
    其中，第m级移位寄存器单元的输入信号端与第m-1级移位寄存器单元的级联输出端连接，第m级移位寄存器单元的复位信号端与第m+2级移位寄存器单元的级联输出端连接，其中M为大于1的整数，m为整数且1＜m＜M-1，并且
    其中，所述M级级联的移位寄存器单元连接至K条时钟信号线，其中K为大于或等于2N的偶数。
  23. 根据权利要求22所述的栅极驱动电路，其中N＝4，K＝12，所述M级级联的移位寄存器单元分为多组，每组包括3级级联的第一移位寄存器单元、第二移位寄存器单元和第三移位寄存器单元，其中第一移位寄存器单元的N个输出时钟信号端与第一时钟信号线至第四时钟信号线一一对应地连接，第二移位寄存器单元的N个输出时钟信号端与第五时钟信号线至第八时钟信号线一一对应地连接，第三移位寄存器单元 的N个输出时钟信号端与第九至第十二时钟信号线一一对应地连接。
  24. 根据权利要求22所述的栅极驱动电路，其中N＝4，K＝8，所述M级级联的移位寄存器单元分为多组，每组包括2级级联的第一移位寄存器单元和第二移位寄存器单元，其中第一移位寄存器单元的N个输出时钟信号端与第一时钟信号线至第四时钟信号线一一对应地连接，第二移位寄存器单元的N个输出时钟信号端与第五时钟信号线至第八时钟信号线一一对应地连接。
  25. 根据权利要求23或24所述的栅极驱动电路，其中，每个移位寄存器单元的N个输出时钟信号端中的第一输出时钟信号端与该移位寄存器单元的控制时钟信号端连接。
  26. 根据权利要求22所述的栅极驱动电路，其中N＝2，K＝6，所述K个时钟信号线包括第一控制时钟信号线、第二控制时钟信号线、第一输出时钟信号线、第二输出时钟信号线、第三输出时钟信号线和第四输出时钟信号线，
    其中，所述M级级联的移位寄存器单元分为多组，每组包括2级级联的第一移位寄存器单元和第二移位寄存器单元，其中第一移位寄存器单元的N个输出时钟信号端与第一输出时钟信号线和第二输出时钟信号线一一对应地连接，第一移位寄存器单元的控制时钟信号端与第一控制时钟信号线连接，第二移位寄存器单元的N个输出时钟信号端与第三时钟信号线和第四时钟信号线一一对应地连接，第二移位寄存器单元的控制时钟信号端与第二控制时钟信号线连接。
  27. 一种如权利要求1至21中任一项所述的移位寄存器单元的驱动方法，包括：
    在第一时段，上拉电路将输入信号端的第一电平提供至总上拉节点，N个输出电路中的第n输出电路将所述输入信号端的第一电平输入至所述第n分上拉节点；
    在第二时段，级联电路在所述总上拉节点的电位的控制下将控制时钟信号端的信号提供至级联输出端，并且N个输出电路中的第n输出电路在第n分上拉节点的电位的控制下将第n输出时钟信号端的信号提供至第n输出信号端；以及，
    在第三时段，上拉电路将复位信号端的第二电平提供至所述总上拉节点，上拉节点的电位使控制电路将所述下拉节点控制为第一电平，下拉节点的电位使得级联电路将级联输出端下拉至第二电平，并且使得N个输出电路中的第n输出电路将第n输出信号端下拉至第二电平。
  28. 一种如权利要求22至26中任一项所述的栅极驱动电路的驱动方法，包括：
    在第一模式下，向所述K条时钟信号线施加逐行顺序移位的K个第一时钟信号， 使得栅极驱动电路的M级移位寄存器单元产生逐行顺序移位的多个第一输出信号；
    在第二模式下，向所述K条时钟信号线施加逐k行顺序移位的K个第二时钟信号，使得栅极驱动电路的M级移位寄存器单元产生逐k行顺序移位的多个第二输出信号，其中在所述K个第二时钟信号的频率是所述K个第一时钟信号的k倍，其中k为小于或等于K的整数。
  29. 根据权利要求28所述的方法，其中，N＝4，K＝12或8，k＝2或4。
  30. 一种如权利要求22至26中任一项所述的栅极驱动电路的驱动方法，所述K条时钟信号线包括多条输出时钟信号线，所述方法包括：
    在第一模式下，向所述多条输出时钟信号线施加逐行顺序移位的多个第一输出时钟信号，使得栅极驱动电路的M级移位寄存器单元产生逐行顺序移位的多个第一输出信号，其中每级移位寄存器单元的N个输出电路均产生输出信号；
    在第二模式下，向所述多条输出时钟信号线中的一部分输出时钟信号线施加多个第二输出时钟信号，使得栅极驱动电路的M级移位寄存器单元产生顺序移位的多个第二输出信号，其中每级移位寄存器单元的N个输出电路中的至少一个输出电路不产生输出信号。
  31. 根据权利要求30所述的方法，其中，N＝2，K＝6，所述K条时钟信号线包括第一控制时钟信号线、第二控制时钟信号线、第一输出时钟信号线、第二输出时钟信号线、第三输出时钟信号线和第四输出时钟信号线，其中，
    在第一模式下，向所述第一控制时钟信号线施加第一控制时钟信号，向所述第二控制时钟信号线施加第二控制时钟信号，并且向第一输出时钟信号线、第二输出时钟信号线、第三输出时钟信号线和第四输出时钟信号线分别施加顺序移位的四个第一输出时钟信号，使得每级移位寄存器单元的2个输出电路均产生输出信号；以及
    在第二模式下，向所述第一控制时钟信号线施加所述第一控制时钟信号，向所述第二控制时钟信号线施加所述第二控制时钟信号，并且向第一输出时钟信号线、第二输出时钟信号线、第三输出时钟信号线和第四输出时钟信号线中的奇数或偶数时钟信号线分别施加顺序移位的两个第二输出时钟信号，使得每级移位寄存器单元的2个输出电路之一产生输出信号。
  32. 根据权利要求30或31所述的方法，其中，所述第二输出时钟信号的周期与所述第一输出时钟信号的周期相等，并且所述第二输出时钟信号占空比大于所述第一输出时钟信号的占空比。
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