WO2023004890A1 - Structure semi-conductrice et son procédé de formation - Google Patents

Structure semi-conductrice et son procédé de formation Download PDF

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Publication number
WO2023004890A1
WO2023004890A1 PCT/CN2021/112299 CN2021112299W WO2023004890A1 WO 2023004890 A1 WO2023004890 A1 WO 2023004890A1 CN 2021112299 W CN2021112299 W CN 2021112299W WO 2023004890 A1 WO2023004890 A1 WO 2023004890A1
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Prior art keywords
layer
bit line
sacrificial
spacer
forming
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PCT/CN2021/112299
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English (en)
Chinese (zh)
Inventor
李冉
段蕾蕾
金星
程明
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长鑫存储技术有限公司
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Priority to US17/580,771 priority Critical patent/US20230033022A1/en
Publication of WO2023004890A1 publication Critical patent/WO2023004890A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • Embodiments of the present application relate to but are not limited to a semiconductor structure and a method for forming the same.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor storage device commonly used in computers. DRAM is composed of many repeated storage units. Each memory cell includes a transistor and a capacitor, wherein the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.
  • An embodiment of the present application provides a method for forming a semiconductor structure, including: providing a base structure, the base structure at least including a bit line structure and a plurality of landings formed around the bit line structure and covering part of the bit line structure Pads; wherein there is a gap between two adjacent landing pads; a capacitive structure is formed on the top surface of the landing pads and in the gap.
  • An embodiment of the present application provides a semiconductor structure, including: a base structure, the base structure at least including a bit line structure and a plurality of landing pads formed around the bit line structure and covering part of the bit line structure; wherein , there is a gap between two adjacent landing pads; the capacitor structure is located on the top surface of the landing pads and in the gap.
  • FIG. 1 is an optional schematic flowchart of a method for forming a semiconductor structure provided in an embodiment of the present application
  • 2a-2k are structural schematic diagrams of the formation process of the semiconductor structure provided by the embodiment of the present application.
  • 3a-3i are another structural schematic diagram of the semiconductor structure formation process provided by the embodiment of the present application.
  • FIG. 4a is an optional structural schematic diagram of the semiconductor structure provided in the embodiment of the present application.
  • FIG. 4b is a schematic structural diagram of another optional semiconductor structure provided in the embodiment of the present application.
  • Embodiments of the present application provide a semiconductor structure and a method for forming the same. Through the method for forming a semiconductor device provided by the embodiment of the present application, a semiconductor structure with relatively large charge capacity can be prepared.
  • Fig. 1 is an optional structural schematic diagram of a method for forming a semiconductor structure provided in an embodiment of the present application. As shown in Fig. 1, the method includes the following steps:
  • Step S101 providing a base structure, the base structure at least including a bit line structure and a plurality of landing pads formed around the bit line structure and covering part of the bit line structure; wherein, two adjacent landing pads with gaps in between.
  • the base structure further includes a semiconductor substrate, the bit line structure is formed on the surface of the semiconductor substrate, and in the embodiment of the present application, the base structure includes a plurality of bit lines arranged in parallel structure.
  • the semiconductor substrate may be a silicon substrate, and the semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs ), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InP) or indium antimonide (InSb), or include other semiconductor alloys such as: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP ), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/
  • the semiconductor substrate may include a top surface at the front side and a bottom surface at the back side opposite to the front side; under the condition of ignoring the flatness of the top surface and the bottom surface, the direction vertical to the top surface and the bottom surface of the semiconductor substrate is defined as first direction.
  • the direction of the top surface and the bottom surface of the semiconductor substrate that is, the plane where the semiconductor substrate is located
  • two second directions and a third direction that intersect each other for example, are perpendicular to each other
  • the arrangement of multiple bit line structures can be defined
  • the direction is the second direction
  • the extension direction of the bit line structure is defined as the third direction
  • the plane direction of the semiconductor substrate can be determined based on the second direction and the third direction.
  • first direction is defined as the Z-axis direction
  • second direction is defined as the X-axis direction
  • third direction is defined as the Y-axis direction.
  • the landing pads are used to electrically connect the subsequently formed capacitor structure, and there is a gap between two adjacent landing pads.
  • the two adjacent landing pads refer to the arrangement along the bit line structure two adjacent landing pads in the direction (that is, the second direction).
  • Step S102 forming a capacitor structure on the top surface of the landing pad and in the gap.
  • the capacitance structure may be a cup-shaped (Cup-shape) capacitor.
  • the capacitive structure can be formed not only on the upper surface of the landing pads, but also in the gap between adjacent landing pads, thus, a semiconductor structure with a larger charge capacity can be prepared.
  • FIGS. 2a-2k are schematic flow charts of forming a semiconductor structure provided in the embodiment of the present application.
  • FIGS. 2a-2k please refer to FIGS. 2a-2k to further describe the method of forming the semiconductor structure provided in the embodiment of the present application in detail.
  • step S101 is performed to provide a base structure, the base structure at least including a bit line structure and a plurality of landing pads formed around the bit line structure and covering part of the bit line structure ; Wherein, there is a gap between two adjacent landing pads.
  • the base structure includes a semiconductor substrate 101 and a plurality of bit line structures 102 formed on the surface of the semiconductor substrate 101 .
  • the semiconductor substrate 101 includes a plurality of active regions 1011 arranged in an array and a shallow trench isolation structure 1012 for isolating each active region 1011, and the bit line structure 102 is formed in the active region 1011 surface and is in contact with the active region 1011 through a bit line contact structure.
  • the base structure further includes a plurality of landing pads (Landing Pad, LP) 103 formed around the bit line structure and covering part of the bit line structure, and along the X-axis direction, two adjacent landing pads There is a gap V1 between 103 .
  • Each of the bit line structures 102 includes a bit line contact layer 1021 , a bit line metal layer 1022 and a bit line mask layer 1023 arranged sequentially along the Z-axis direction from bottom to top.
  • the material of the bit line contact layer 1021 can be polysilicon; the material of the bit line metal layer 1022 includes: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, Silicide or any combination thereof; the material of the bit line mask layer may be silicon nitride.
  • the base structure further includes a word line structure (not shown in the figure) buried in the semiconductor substrate 101 and a first spacer layer sequentially formed on the sidewall of the bit line structure 102, The spacer layer 102a and the second spacer layer 102b are sacrificed. Wherein, along the Z-axis direction, the sizes of the first spacer layer, the sacrificial spacer layer 102a and the second spacer layer 102b decrease sequentially.
  • the base structure further includes a storage node contact (Node Contact, NC) 104 formed around the bit line structure 102 and in contact with each of the landing pads 103 .
  • NC storage node contact
  • the landing pad and the void can be formed by the following steps:
  • Step S1011 forming a conductive layer covering the bit line structure on the surface of each storage node contact; wherein, the top surface of the conductive layer exceeds the top surface of the bit line structure.
  • a conductive layer 103 a covering the bit line structure 102 is formed on the surface of each storage node contact 104 , and the top surface of the conductive layer 103 a exceeds the top surface of the bit line structure 102 .
  • the conductive layer can be formed by any suitable deposition process, for example, chemical vapor deposition (Chemical Vapor Deposition, CVD) process, physical vapor deposition (Physical Vapor Deposition, PVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process, spin coating process or coating process.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • spin coating process or coating process for example, spin coating process or coating process.
  • Step S1012 forming a patterned second mask layer on the surface of the conductive layer.
  • a patterned second mask layer 105 is formed on the surface of the conductive layer 103a, and the patterned second mask layer 105 has a plurality of openings, and each opening exposes part of the conductive layer 103a of the top surface.
  • the second mask layer may be an amorphous carbon layer (Armorphous Carbon Layer, ACL), a spin-on hard mask layer (Spin-on Hardmask, SOH), a polysilicon layer or a silicon oxynitride layer.
  • ACL amorphous Carbon Layer
  • SOH spin-on Hardmask
  • Step S1013 through the patterned second mask layer, etch part of the conductive layer and the first spacer layer until the sacrificial spacer layer is exposed, forming a contact surface located on each of the storage nodes.
  • a part of the conductive layer 103a and a part of the first spacer layer are etched until the sacrificial spacer layer 102a is exposed, forming a contact at each storage node.
  • the gap V1 formed between adjacent landing pads in the embodiment of the present application has a stepped section along the XZ direction, wherein the Z-axis direction (ie, the first direction) is perpendicular to the extension direction of the bit line structure (ie the third direction) and the arrangement direction of the bit line structures (ie the second direction).
  • step S102 is performed to form a capacitor structure on the top surface of the landing pad and in the gap.
  • step S102 may include the following steps:
  • Step S1021 forming a first insulating layer in the gap, the first insulating layer being flush with the surface of the landing pad.
  • an insulating material is filled in the gap V1 to form an initial insulating layer 106a, and due to the influence of the process, the initial insulating layer 106a usually covers the surface of the landing pad 103; secondly, Perform dry etching or chemical mechanical polishing (CMP) on the initial insulating layer 106a to expose the surface of the landing pad 103, so that a first insulating layer 106 .
  • the first insulating layer may be a silicon oxide layer.
  • Step S1022 forming a laminate structure on the surface of the landing pad and the first insulating layer.
  • the laminated structure includes a sacrificial layer and a supporting layer, wherein the sacrificial layer and the supporting layer are alternately stacked along the Z-axis direction.
  • the sacrificial layer may be an oxide layer, such as a silicon oxide layer;
  • the support layer may be a nitride layer, such as a silicon nitride layer.
  • the stacked structure may be formed by any suitable deposition process.
  • a stacked structure 107 is formed on the surface of the landing pad 103 and the first insulating layer 106.
  • Step S1023 processing the laminated structure and the first insulating layer to form the capacitor structure.
  • step S1023 may be implemented through the following steps:
  • Step S1 patterning the stacked structure to form capacitor holes in the stacked structure on the surface of the landing pad.
  • the method for forming the semiconductor structure before performing step S1, further includes: forming a first mask layer on the surface of the second support layer.
  • the first mask layer 108 is formed on the surface of the second supporting layer 1074 .
  • the material of the first mask layer 108 and the material of the patterned second mask layer 105 may be the same or different.
  • step S1 may be formed by the following steps:
  • Step S11 patterning the first mask layer.
  • Step S12 using the patterned first mask layer as a mask to etch the second supporting layer, the second sacrificial layer, the first supporting layer and the first sacrificial layer on the surface of each landing pad , forming a plurality of capacitor holes.
  • the second supporting layer 1074, the second sacrificial layer 1073, the first supporting layer 1072 and the first sacrificial layer 1071 located on the surface of the landing pad 103 are etched through the patterned first mask layer to form A plurality of capacitance holes 109 .
  • Step S2 forming a first electrode layer on the inner wall of each capacitor hole and the surface of the patterned stacked structure.
  • a first electrode layer 110 is formed on the inner wall of each capacitor hole 109 and the surface of the patterned stacked structure.
  • the first electrode layer 110 may be a titanium nitride layer.
  • Step S3 patterning the supporting layer to form openings between a plurality of adjacent capacitance holes.
  • Step S4 etching the sacrificial layer and the first insulating layer through the opening.
  • the patterned stack structure includes the first sacrificial layer, the first support layer, the second sacrificial layer and the second support layer stacked in sequence, and the patterned stack
  • the first mask layer and the first electrode layer are formed on the surface of the structure.
  • Step S3 and step S4 can be formed by the following steps:
  • a first opening is formed in the first mask layer and the second support layer.
  • the second sacrificial layer is removed.
  • a first opening 111a is formed in the first mask layer 108 and the second support layer 1074 by using a conventional etching process, and the second sacrificial layer 1073 is removed through the first opening 111a.
  • the second sacrificial layer 1073 may be removed by using a wet etching solution using a wet etching technique.
  • the first opening 111 a is formed, the first electrode layer located on the top surface of the first mask layer 108 is removed at the same time.
  • a second opening is formed in the first support layer.
  • the first sacrificial layer and the first insulating layer are removed.
  • a second opening 111b is formed in the second supporting layer 1072 by using a conventional etching process, and the first sacrificial layer 1071 and the first insulating layer 106 are removed through the second opening 111b.
  • the first sacrificial layer 1071 and the first insulating layer 106 may be removed by using a wet etching solution.
  • the second sacrificial layer 1074 and the first insulating layer 106 may be made of the same material or different materials.
  • the first opening 111 a and the second opening 111 b may be formed by using a dry etching technique, for example, a plasma etching technique.
  • a first spacer layer, a second spacer layer 102a, and a sacrificial spacer layer between the first spacer layer and the second spacer layer are formed on the sidewall of each bit line structure 102 102b, and the first insulating layer 102b is connected to the sacrificial spacer layer 102a.
  • the method for forming the semiconductor structure further includes: when removing the first sacrificial layer and the first insulating layer through the second opening, removing the sacrificial spacer layer; wherein, the first sacrificial layer and the first insulating layer are The sacrificial spacer layer is formed of the same material.
  • the sacrificial spacer layer 102a on the sidewall of each bit line structure 102 is removed, forming an air gap G located on the side wall of the bit line structure.
  • the air gap G communicates with the gap V1 , and the air gap G can reduce the leakage of the semiconductor structure.
  • wet etching technology can be used, for example, sulfuric acid, hydrofluoric acid, nitric acid and other etching solutions can be used to remove the second sacrificial layer, the first sacrificial layer, the first insulating layer and the Describe the first spacer layer.
  • Step S5 forming the capacitance structure in the patterned support layer.
  • step S5 may be implemented through the following steps:
  • a dielectric layer and a second electrode layer are sequentially deposited on the surface of the first electrode layer.
  • a dielectric layer 112 and a second electrode layer 113 are formed on the surface of the first electrode layer, and the dielectric layer 112 and the second electrode layer 113 are also used to seal the air gap G.
  • the dielectric layer 112 may be a zirconia layer and/or an aluminum oxide layer, or other high dielectric constant material layers; the second electrode layer 113 and the first electrode layer 110 may be Same or different.
  • the conductive material fills the gap between the second electrode layers and covers the upper surface of the laminated structure; wherein the first electrode layer, the dielectric layer, and the second electrode layer and the conductive material make up the capacitive structure.
  • a conductive material 114 is deposited in the gap between the second electrode layers to form a complete capacitor structure.
  • the capacitor structure includes a first electrode layer 110 , a dielectric layer 112 , a second electrode layer 113 and a conductive material 114 .
  • the conductive material may be polysilicon, or any other suitable conductive material, such as tungsten, cobalt or doped polysilicon.
  • the semiconductor structure in the embodiment of the present application forms an air gap on the sidewall of the bit line structure when forming the capacitor structure, so that the leakage performance of the semiconductor structure can be improved.
  • a device with increased capacitance and air gap is designed to reduce leakage
  • the production process through the over-etching of the landing pad, and then filling the insulating material (for example, SiO2) around the landing pad, on the basis of traditional capacitors, BL/BLC/LP is formed by pickling (for example, hydrofluoric acid)
  • pickling for example, hydrofluoric acid
  • FIGS. 3a-3i are another schematic flow chart of forming a semiconductor structure provided by the embodiment of the present application.
  • FIGS. 3a-3i please refer to FIGS. 3a-3i to further describe the method of forming the semiconductor structure provided in the embodiment of the present application in detail.
  • step S101 is performed to provide a base structure, the base structure at least including a bit line structure and a plurality of landing pads formed around the bit line structure and covering part of the bit line structure; Wherein, there is a gap between two adjacent landing pads.
  • the base structure includes a semiconductor substrate 101 and a plurality of bit line structures 102 formed on the surface of the semiconductor substrate 101 .
  • the semiconductor substrate 101 includes a plurality of active regions 1011 and shallow trench isolation structures 1012 arranged alternately along the X-axis direction.
  • the bit line structure 102 includes a bit line contact layer 1021 , a bit line metal layer 1022 and a bit line mask layer 1023 stacked sequentially from bottom to top along the Z-axis direction.
  • the base structure further includes a first spacer layer, a sacrificial spacer layer 102 a and a second spacer layer 102 b sequentially formed on the sidewall of the bit line structure 102 .
  • the base structure further includes a plurality of landing pads 103 formed around the bit line structure 102 and covering part of the bit line structure 102 .
  • a void between adjacent landing pads may be formed by:
  • Step S301 forming a second insulating layer between two adjacent landing pads, wherein the second insulating layer is flush with the surface of the landing pads.
  • a second insulating layer 301 is formed between two adjacent landing pads 103 , wherein the surface of the second insulating layer 301 is flush with the surface of the landing pads 103 .
  • the second insulating layer may be a silicon oxide layer or other insulating layers.
  • Step S302 etching the second insulating layer and part of the bit line mask layer to form the gap, the cross section of the gap along the first direction is U-shaped.
  • the second insulating layer and the bit line mask layer may be etched using a dry etching technique or a wet etching technique. As shown in FIG. 3b, the second insulating layer 301 and part of the bit line mask layer 1023 are removed by etching along the Z-axis direction, forming a gap V2 between adjacent landing pads 103 along the Z-axis direction. , the section of the void V2 along the XZ direction is U-shaped.
  • step S102 is performed to form a capacitor structure on the top surface of the landing pad and in the gap.
  • step S102 may include the following steps:
  • Step S1021 forming a first insulating layer in the gap, the first insulating layer being flush with the surface of the landing pad.
  • an insulating material is filled in the gap V2 to form a first insulating layer 302 , and the surface of the first insulating layer 302 is flush with the surface of the landing pad 103 .
  • the first insulating layer 302 and the second insulating layer 301 may be the same or different.
  • the process of forming the first insulating layer 302 in the implementation of the present application is the same as the process of forming the first insulating layer 106 in the above-mentioned embodiment.
  • Step S1022 forming a laminate structure on the surface of the landing pad and the first insulating layer.
  • the laminated structure includes a sacrificial layer and a supporting layer.
  • a stacked structure 107 is formed on the surface of the landing pad 103 and the first insulating layer 302.
  • Step S1023 processing the laminated structure and the first insulating layer to form the capacitor structure.
  • step S1023 may be implemented through the following steps:
  • Step S1 patterning the stacked structure to form capacitor holes in the stacked structure on the surface of the landing pad.
  • the method for forming the semiconductor structure further includes: forming a first mask layer on the surface of the second supporting layer.
  • the first mask layer 108 is formed on the surface of the second supporting layer 1074 .
  • step S1 may be formed by the following steps:
  • Step S11 patterning the first mask layer.
  • Step S12 using the patterned first mask layer as a mask to etch the second supporting layer, the second sacrificial layer, the first supporting layer and the first sacrificial layer on the surface of each landing pad , forming a plurality of capacitor holes.
  • the second supporting layer 1074, the second sacrificial layer 1073, the first supporting layer 1072 and the first sacrificial layer 1071 located on the surface of the landing pad 103 are sequentially etched through the patterned first mask layer, A plurality of capacitive holes 109 are formed.
  • Step S2 forming a first electrode layer on the inner wall of each capacitor hole and the surface of the patterned stacked structure.
  • a first electrode layer 110 is formed on the inner wall of each capacitor hole 109 and the surface of the patterned stacked structure.
  • Step S3 patterning the supporting layer to form openings between a plurality of adjacent capacitance holes.
  • Step S4 etching the sacrificial layer and the first insulating layer through the opening.
  • the patterned stack structure includes the first sacrificial layer, the first support layer, the second sacrificial layer and the second support layer stacked in sequence, and the patterned stack
  • the first mask layer and the first electrode layer are formed on the surface of the structure.
  • Step S3 and step S4 can be formed by the following steps:
  • a first opening is formed in the first mask layer and the second support layer.
  • the second sacrificial layer is removed.
  • a first opening 111a is formed in the first mask layer 108 and the second support layer 1074 by using a conventional etching process, and the second sacrificial layer 1073 is removed through the first opening 111a.
  • a second opening is formed in the first support layer.
  • the first sacrificial layer and the first insulating layer are removed.
  • a second opening 111b is formed in the second support layer 1072 by using a conventional etching process, and the first sacrificial layer 1071 and the first insulating layer 302 are removed through the second opening 111b.
  • the first opening 111 a and the second opening 111 b may be formed by using a dry etching technique, for example, a plasma etching technique.
  • the sacrificial spacer layer 102a is connected to the first insulating layer 302, and when the first sacrificial layer and the first insulating layer are removed through the second opening, the sacrificial spacer layer is removed. layer.
  • the sacrificial spacer layer 102b on the sidewall of each bit line structure 102 is removed to form the bit line structure or the bit line contact layer.
  • the air gap G, the air gap communicates with the gap V2, and the air gap G can reduce the leakage of the semiconductor structure.
  • the first sacrificial layer and the sacrificial spacer layer may be formed of the same material, or may be formed of different materials.
  • Step S5 forming the capacitor structure in the patterned support layer.
  • step S5 may be implemented through the following steps:
  • Step S51 depositing a dielectric layer and a second electrode layer sequentially on the surface of the first electrode layer.
  • Step S52 depositing a conductive material, the conductive material fills the gap between the second electrode layers and covers the upper surface of the laminated structure; wherein, the first electrode layer, the dielectric layer, the The second electrode layer and the conductive material constitute the capacitor structure.
  • a dielectric layer 112 and a second electrode layer 113 are formed on the surface of the first electrode layer, and the dielectric layer 112 and the second electrode layer 113 are also used to seal the air gap G.
  • a conductive material 114 is deposited in the gap between the second electrode layers to form a complete capacitor structure.
  • the capacitor structure includes a first electrode layer 110 , a dielectric layer 112 , a second electrode layer 113 and a conductive material 114 .
  • the formation process of the semiconductor structure in the embodiment of the present application is similar to the formation process of the semiconductor structure in the above-mentioned embodiment.
  • the technical features not disclosed in detail in the embodiment of the present application please refer to the above-mentioned embodiment for understanding, and details are not repeated here.
  • the semiconductor structure in the embodiment of the present application forms an air gap on the sidewall of the bit line structure when forming the capacitor structure, so that the leakage performance of the semiconductor structure can be improved.
  • the embodiment of the present application also provides a semiconductor structure.
  • the semiconductor structure 40 includes: a base structure and a capacitor structure 401 .
  • the base structure includes a plurality of bit line structures 102 arranged in parallel along the X-axis direction and a plurality of landing pads 103 formed around each bit line structure 102 and covering part of the bit line structure; wherein, two adjacent There is a gap V1 or a gap V2 between the landing pads 103 . As shown in FIG.
  • the cross-section of the void V1 along the XZ direction is stepped, and the Z-axis direction is perpendicular to the extending direction of the bit line structure 201 and the arrangement direction of the bit line structure 201 (that is, the X-axis direction );
  • the bit line structure 201 includes a bit line contact layer 1021 , a bit line metal layer 1022 and a bit line mask layer 1023 stacked sequentially along the Z-axis direction from bottom to top.
  • the cross-section of the void V2 along the XZ direction is U-shaped;
  • the bit line structure 201 includes the bit line contact layer 1021 and the bit line metal layer stacked in sequence along the Z axis direction from bottom to top. 1022 and part of the bit line mask layer 1023.
  • the base structure further includes a semiconductor substrate 101, and the semiconductor substrate 101 includes a plurality of active regions 1011 arranged in an array and a shallow trench isolation structure 1012 for isolating each active region 1011 , the bit line structure 102 is formed on the surface of the active region 1011 and is in contact with the active region 1011 through a bit line contact structure.
  • the base structure further includes a storage node contact 104 formed around the bit line structure 102 and in contact with each of the landing pads 103 .
  • the base structure further includes a word line structure (not shown in the figure) buried in the semiconductor substrate 101 .
  • the capacitive structure 401 is located on the top surface of the landing pad 103 and in the void V1 or the void V2.
  • the capacitive structure 401 includes a first electrode layer 110 , a dielectric layer 112 and a second electrode layer 113 stacked in sequence, and a conductive material 114 is filled between adjacent second electrode layers 113 .
  • the capacitive structure 401 is a cup-shaped structure, and the extension direction (Z-axis direction) of the capacitive structure is perpendicular to the top surface of the landing pad 103;
  • the first supporting layer 1072 and the second supporting layer 1074 arranged in parallel; wherein, the first supporting layer 1072 is arranged on the middle periphery of the capacitor structure 401, and the second supporting layer 1074 is arranged on the outer periphery of the capacitor structure 401 On the outer periphery of the top, the first support layer 1072 and the second support layer 1074 are jointly used to support the capacitor structure 401 .
  • the thickness h1 of the second supporting layer 1074 is greater than the thickness h2 of the first supporting layer 1072 , so that a better supporting effect can be achieved.
  • the sidewall of the bit line structure 102 is formed with a first spacer layer, a second spacer layer 102b, and an air gap G between the first spacer layer and the second spacer layer 102b; Wherein, the air gap G is in contact with the dielectric layer 112 .
  • the semiconductor structure provided in the embodiment of the present application is similar to the method for forming the semiconductor structure in the above-mentioned embodiment.
  • the technical features not disclosed in detail in the embodiment of the present application please refer to the above-mentioned embodiment for understanding, and details will not be repeated here.
  • the capacitor structure is not only located on the top surface of the landing pads, but also located in the gap between two adjacent landing pads. In this way, the prepared semiconductor structure can have a large charge capacity. Moreover, the semiconductor structure in the embodiment of the present application has an air gap located on the sidewall of the bit line structure, so that the leakage performance of the formed semiconductor structure can be improved.
  • the disclosed devices and methods may be implemented in non-target ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the various components shown or discussed are coupled with each other, or directly coupled.

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Abstract

Sont prévus dans des modes de réalisation de la présente demande une structure semi-conductrice et son procédé de formation. Le procédé consiste à : fournir une structure de substrat, la structure de substrat comprenant au moins une structure de lignes de bits et une pluralité de plages de pose qui sont formées autour de la structure de lignes de bits et qui recouvrent une partie de la structure de lignes de bits, deux plages de pose adjacentes présentant un espace entre elles ; et former des structures de condensateur sur les surfaces supérieures des plages de pose et dans les espaces.
PCT/CN2021/112299 2021-07-27 2021-08-12 Structure semi-conductrice et son procédé de formation WO2023004890A1 (fr)

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US17/580,771 US20230033022A1 (en) 2021-07-27 2022-01-21 Semiconductor structure and method for forming semiconductor structure

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CN202110853181.2A CN115701213A (zh) 2021-07-27 2021-07-27 半导体结构及其形成方法
CN202110853181.2 2021-07-27

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