WO2023000506A1 - 一种基于同一同轴线实现数据、控制和输电装置 - Google Patents

一种基于同一同轴线实现数据、控制和输电装置 Download PDF

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Publication number
WO2023000506A1
WO2023000506A1 PCT/CN2021/122611 CN2021122611W WO2023000506A1 WO 2023000506 A1 WO2023000506 A1 WO 2023000506A1 CN 2021122611 W CN2021122611 W CN 2021122611W WO 2023000506 A1 WO2023000506 A1 WO 2023000506A1
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Prior art keywords
module
signal
voltage
resistor
coaxial line
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PCT/CN2021/122611
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English (en)
French (fr)
Inventor
蔡泳成
李昌绿
张常华
朱正辉
赵定金
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广州市保伦电子有限公司
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Publication of WO2023000506A1 publication Critical patent/WO2023000506A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/10—Adaptations for transmission by electrical cable
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/54—Systems for transmission via power distribution lines
    • H04B3/548—Systems for transmission via power distribution lines the power on the line being DC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/54—Systems for transmission via power distribution lines
    • H04B3/56—Circuits for coupling, blocking, or by-passing of signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division

Definitions

  • the invention relates to the technical field of coaxial line data, control signal transmission and power transmission, in particular to a device for realizing data, control and power transmission based on the same coaxial line.
  • the coaxial line has good anti-interference performance and makes data transmission stable. At the same time, it is widely used due to the characteristics of long transmission distance and low cost, especially in data communication. In the prior art, it has not been found that data, control signal transmission and power transmission can be simultaneously realized on the same coaxial cable.
  • video signals as data as an example
  • one of the coaxial cables is often used to transmit video signals
  • one coaxial cable is used to transmit control signals
  • the other coaxial cable is used to transmit power to other devices.
  • the technical requirements are also high, resulting in restrictions on many application scenarios. Especially in some places where space is limited and a large number of cables cannot be laid out, it may result in the inability to use coaxial cables to meet its needs.
  • the object of the present invention is to provide a data, control and power transmission device based on the same coaxial line, which can solve the problem of realizing data transmission, control signal and power transmission on the same coaxial line.
  • a data, control and power transmission device based on the same coaxial line, including a power supply and reception module, a data transmission module, an encoding module, a decoding module and an isolation module,
  • the power supply and receiving module includes a power transmission terminal and a first filter circuit, one end of the power transmission terminal is connected to an external coaxial line through the first filter circuit,
  • the first filter circuit is used to isolate the data signal loaded on the coaxial line by the data transmission module and the encoded signal loaded on the coaxial line by the encoding module, so as to prevent the data signal and the encoded signal from being poured back into the power supply and receiving module.
  • the power transmission end is used to connect the first DC voltage so that the first DC voltage is loaded onto the coaxial line through the first filter circuit, or receive the first DC voltage transmitted from the coaxial line through the first filter circuit,
  • the data transmission module includes a second filter circuit, the data transmission module is used to load the data signal onto the coaxial line through the second filter circuit, or receive the data signal transmitted from the coaxial line through the second filter circuit, the data signal
  • the frequency is n
  • the encoding module is used to encode the control signal and output the encoded signal, the control signal is a square wave signal with a frequency of m, m ⁇ n,
  • the encoding signal When the control signal is at a high level, the encoding signal is a DC voltage q; when the control signal is at a low level, the encoding signal is a square wave signal p, the voltage value of the DC voltage q is less than the high level of the square wave signal p, and the square wave signal The high level of p is less than the high level of the control signal,
  • the decoding module is used to decode the coded signal to restore the control signal
  • the isolation module is used to load the encoded signal to the coaxial line after passing through the isolation module or load the encoded signal transmitted by the coaxial line to the encoding module, and isolate the data signal to prevent the data signal from being loaded to the encoding module or On the decoding module,
  • Both the encoding module and the decoding circuit are based on a discrete component gate circuit composed of logic gates and discrete components.
  • the second filtering circuit can isolate the coded signal transmitted from the coaxial line, preventing the coded signal from being loaded to the data transmission module.
  • the first filter circuit includes an inductor L1, a magnetic bead LB1, an inductor L2 and a magnetic bead LB2 connected in series in sequence, one end of the inductor L1 is connected to one end of the power transmission end, and one end of the magnetic bead LB2 is connected to the coaxial line.
  • the second filtering circuit is a capacitor C1.
  • the encoding module includes a control signal input interface, a first reference signal interface, a NAND gate U1, a NAND gate U3, an exclusive OR gate U2, a resistor R1, a resistor R2, and a resistor R5,
  • the control signal input interface is used to receive the control signal
  • the first reference signal interface is used to receive the first reference signal
  • the first reference signal is a square wave signal with frequency f
  • the control signal input interface is respectively connected to the two input terminals of the NAND gate U1, and the first input terminal of the NAND gate U2, and the output terminal of the NAND gate U1 is connected to the first input terminal of the NAND gate U3.
  • a reference signal interface is connected to the second input terminal of the NAND gate U3, the output terminal of the NAND gate U3 is respectively connected to the second input terminal of the exclusive OR gate U2, and one end of the resistor R5, and the output terminal of the exclusive OR gate U2 is connected to the resistor R5.
  • One end of R1 is connected, the other end of the resistor R1 and the other end of the resistor R5 are jointly connected with one end of the resistor R2, and the other end of the resistor R2 is grounded.
  • the coded module further includes a capacitor C4, which is connected in parallel with both ends of the resistor R2, and the capacitor C4 is used for bypass filtering.
  • the isolation module includes a capacitor C2, a resistor R1, an inductor L3, a magnetic bead LB3 and a magnetic bead LB4, the resistor R1 and the inductor L3 are connected in parallel to form a parallel branch, and the capacitor C2, the parallel branch, the magnetic bead LB4 and the magnetic bead LB3 After being connected in series, they are connected with the coaxial line.
  • the decoding module includes a sequentially connected non-inverting amplification module, a signal shaping module and a hysteresis comparator module, and the non-inverting amplifying module is connected to the signal shaping module through a capacitor C7,
  • the in-phase amplifying module is connected to the coaxial line through the isolation module, and is used to amplify the voltage of the encoded signal sent from the co-axial line, so that the difference between the high level and the low level output by the in-phase amplifying module is greater than the first difference, the first difference is the difference between the high level of the square wave signal p and the low level of the DC voltage q,
  • the signal shaping module is used to generate a level signal t1 equal to the voltage of the DC voltage q when the DC voltage q cannot pass through the capacitor C7 after being output by the non-inverting amplification module, and the voltage of the level signal t1 is r1, and used for
  • the square wave signal p is amplified by the in-phase amplifying module and then shaped into a level signal t2 of voltage r2, and the voltage r2 is greater than the voltage value of the square wave signal p amplified by the in-phase amplifying module.
  • the hysteresis comparator module is provided with a second reference voltage, the second reference voltage is greater than the voltage r1 and less than the voltage r2, and the hysteresis comparator module is used to output the decoding signal according to the comparison result of the second reference voltage distribution with the voltage r1 and the voltage r2,
  • the hysteresis comparator module When the second reference voltage is greater than the voltage r1, the hysteresis comparator module outputs a low level, and when the second reference voltage is lower than the voltage r2, the hysteresis comparator module outputs a high level, thereby completing the decoding of the encoded signal and restoring the control signal.
  • the decoding module also includes a level isolation module, the output terminal of the hysteresis comparator module is connected to the level isolation module, and the level isolation module is used to isolate the post-stage circuit connected to the hysteresis comparator from the hysteresis comparator module. Influence, to prevent the stability of the operation of the hysteresis comparator.
  • the level isolation module includes a NAND gate U5, a NAND gate U6, a resistor R13, a resistor R14, a resistor R15 and a resistor R19, one end of the resistor R14 is connected to the first reference voltage, and the other end of the resistor R14 is connected to the NAND
  • the output terminal is connected, and the second input terminal of the NAND gate U6 is also connected with the output terminal of the NAND gate U5 through the series resistance R16, and the output terminal of the NAND gate U6 is connected with the second input terminal of the NAND gate U5, and the NAND gate U5 is connected with the output terminal of the NAND gate U5.
  • the output terminal of the gate U5 is connected in series
  • the voltage value of the DC voltage q is half of the high level of the square wave signal p.
  • the present invention can realize the simultaneous transmission of data signals, control signals and power supply on the same coaxial cable, can reduce operational troubles such as wiring in actual application, and improve the universality of application.
  • Fig. 1 is the realization of the circuit schematic diagram of realizing data, control and power transmission device based on the same coaxial line in a preferred embodiment
  • Fig. 2 is a schematic circuit diagram of the coding module in Fig. 1;
  • Fig. 3 is a schematic circuit diagram of the decoding module in Fig. 1;
  • Fig. 4 is the schematic circuit diagram of the in-phase amplification module in Fig. 3;
  • Fig. 5 is a schematic circuit diagram of the signal shaping module in Fig. 3;
  • Fig. 6 is a schematic circuit diagram of a hysteresis comparator module in Fig. 3;
  • Fig. 7 is a schematic circuit diagram of the level isolation module in Fig. 3;
  • Fig. 8 is a schematic diagram of the corresponding relationship between the control signal in the encoding module, the second square wave signal, the output of three NAND gates in the encoding module and the encoding signal finally output by the encoding module;
  • Fig. 9 is a schematic view of the use state of connecting the device provided by this embodiment to both ends of the same coaxial line.
  • the power transmission in this embodiment includes external power supply and inward power reception.
  • the device When the device is used as a power supply end, it is used to supply power to the outside, and when it is used as a power receiving end, it receives power inward, that is, it accepts externally provided power.
  • a data, control and power transmission device based on the same coaxial line can be used as a power supply terminal to supply power to the outside through the coaxial line; it can also be used as a power receiving terminal through the coaxial line Receive power from another device.
  • the device When the device is used as a power supply terminal, the device receives data and control signals sent by another device, and responds to the control signals by returning a response signal.
  • the device acts as a receiving end, the device sends data and control signals to another device.
  • the video signal is taken as the data as an example for detailed description, that is, the video signal is used as the data that needs to be transmitted or communicated.
  • One of the devices is the master, the other device is the slave, the master is used as the power supply end, the slave is used as the power receiver, the slave sends video signals to the master, the master sends control signals to the slave, and the slave receives the control signal Afterwards, the response signal is returned, and the response signal is also sent after encoding by the encoding module.
  • Two devices cannot send or receive at the same time, only one end is sending and the other end is receiving.
  • the video signal may be a video signal generated inside the device, or a video signal transmitted to the device from outside.
  • the device includes a power supply and receiving module, a data transmission module, an encoding module, a decoding module and an isolation module.
  • the output ends of the encoding module and the decoding module are connected in series with the input end of the isolation module, the common connection point of the output end of the isolation module, the output end of the power supply and receiving module, and the data transmission module is used as a unified output end, and the unified output end is connected to the coaxial line.
  • the device is connected to one end of the coaxial line, and the other end of the coaxial line is connected to another device identical to the device.
  • the output end of the isolation module, the output end of the power supply and receiving module and the output end of the data transmission module are connected to one end of the coaxial line, and the other end of the coaxial line is connected to the isolation module of another device, the power supply and receiving module and the data transmission module.
  • the common connection point of the transmission module, and at this time the common connection point of the other end is used as the input end. That is to say, the two devices connected at both ends of the coaxial line can be converted to each other. When one is used as the power supply end, the other is used as the power receiving end.
  • the power supply and receiving module includes a power transmission end, and one end of the power transmission end is connected to the coaxial line after being connected in series with the first filter circuit. That is, one end of the inductor L1 is connected to one end of the power transmission end, and one end of the magnetic bead LB2 is connected to the coaxial line.
  • the first filter circuit is used to isolate the video signal and the control signal on the coaxial line, preventing the video signal and the control signal from being transmitted to the power transmission end.
  • the other end of the power transmission end is connected to a power supply that provides the first DC voltage, and the power supply inputs the first DC voltage to the power transmission end.
  • the voltage is preferably a DC voltage of 24V, and the first DC voltage is supplied to the outside through the coaxial line after passing through the first filter circuit.
  • the power supply and receiving module When the power supply and receiving module is used to receive power (that is, receive voltage), that is, when the device where the power supply and receiving module is located is the power receiving end, the other end of the power transmission end is connected to other electrical equipment (including circuits) or electronic components, and the coaxial
  • the first DC voltage transmitted by the line passes through the first filter circuit and then is transmitted to other equipment or electronic components in the subsequent stage through the other end of the power transmission end.
  • the voltage is loaded on the coaxial line for transmission after passing through the filter circuit composed of inductance and magnetic beads, and then transmitted to the power receiving equipment through the coaxial line, that is, to the Another device.
  • the voltage value of the first DC voltage is usually relatively large, so that the first DC voltage can be transmitted to the coaxial line through the first filter circuit, while the small-voltage DC voltage transmitted on the coaxial line cannot pass through the first filter circuit.
  • the filter circuit is transmitted to the power transmission end, that is, the first filter circuit can well maintain the first DC voltage to pass through and isolate the video signal and the control signal on the coaxial line.
  • the data transmission module includes a data interface, and the data interface is connected to the coaxial line with the power supply and reception module after a capacitor C1 is connected in series.
  • the data interface receives the video signal transmitted through the coaxial line, the video signal is transmitted to the data interface after passing through the capacitor C1, and the data interface transmits the video signal to the subsequent equipment.
  • the data interface receives the video signal sent by the subsequent equipment, and the data interface transmits the video signal to the coaxial line through the capacitor C1, and then the coaxial line transmits the video signal to the outside, that is, to the another terminal.
  • Video_signal_RX in Figure 1 means receiving the video signal transmitted over the coaxial line.
  • the device is used as the power supply end, and the received video signal is only transmitted over the coaxial line by other terminals.
  • the video signal may use an SDI (Serial Digital Component Interface) signal.
  • SDI Serial Digital Component Interface
  • the video signal received by the data interface through the coaxial line or the video signal transmitted to the coaxial line is a signal with a certain frequency, for example, a square wave signal with a certain frequency.
  • Capacitor C1 can isolate the first DC voltage on the coaxial line to prevent the first DC voltage from passing through the data transmission module from damaging subsequent equipment connected to the data interface, and capacitor C1 can allow video signals with a certain frequency to pass through. In this way, power transmission and data are transmitted on the same coaxial cable.
  • the capacitor C1 can also isolate the low-frequency square wave signal, preventing the coded signal from being transmitted to the data transmission module through the capacitor C1, that is, to the data interface.
  • Capacitor C1 allows high-frequency video signals to pass through, that is, among the first DC voltage, coded signals and video signals, only video signals are allowed to pass through.
  • the encoding module includes a control signal input interface, a first reference signal interface, a NAND gate U1, a NAND gate U3, an exclusive OR gate U2, a resistor R1, a resistor R2, a resistor R5 and a capacitor C4.
  • the control signal input interface ie, Control_signal_Tx in FIG. 2
  • the output terminal of the NAND gate U1 (the Y terminal of U1 in FIG. 2 ) is connected to the first input terminal of the NAND gate U3.
  • the first reference signal interface ie 500KHz_PWM in FIG.
  • the output end of the NAND gate U3 is respectively connected with the second input end of the exclusive OR gate U2 and one end of the resistor R5.
  • the output end of the XOR gate U2 is connected to one end of the resistor R1, the other end of the resistor R1 and the other end of the resistor R5 are jointly connected to one end of the resistor R2, and the other end of the resistor R2 is grounded. It can be seen that the two ends of the resistor R5 are respectively at the input end and the output end of the XOR gate U2.
  • the common connection of the resistor R1, the resistor R2 and the resistor R5 is marked as the connection point M, such as point M in FIG. 2 .
  • the capacitor C4 is connected in parallel with both ends of the resistor R2, that is, one end of the capacitor C4 is connected to the connection point M, and the other end of the capacitor C4 is commonly grounded with the other ground of the resistor R2.
  • Capacitor C4 functions as a bypass filter to filter the encoded signal, which is equivalent to filtering the control signal.
  • the encoding module is a logic circuit.
  • the encoded signal output by the encoding module is also directly transmitted to the decoding module through the capacitor C8, in practical applications it can be distinguished whether it is directly transmitted or transmitted through the coaxial line.
  • the data frame of the control signal sent and the response signal returned in response to the control signal can be distinguished, and the coded signal transmitted directly or through the coaxial line can be distinguished through the data frame header, or the control signal sent and received It is distinguished by the number of data bits and data checksum of the response signal.
  • the directly transmitted encoded signal can be discarded, so that the encoded signal transmitted by another device can be distinguished from the local encoded signal for accurate decoding.
  • connection point M is also the output end of the encoding module, that is, the common connection end of the resistor R1, the resistor R2, the resistor R5 and the capacitor C4 is the output end of the encoding module, and the output end is connected to the coaxial line after the isolation module is connected in series, thereby
  • the coding module, the power receiving module and the data transmission module are connected to the coaxial line together.
  • the resistor R1, the resistor R2, and the resistor R5 form a voltage divider circuit, which is used to output the levels of the first square wave signal and the second square wave signal, then step down and output a level signal.
  • the resistance values of the resistor R1, the resistor R2, and the resistor R5 are 470 ⁇ , 100 ⁇ , and 470 ⁇ in sequence, and the capacitance value of the capacitor C1 is 220pF.
  • the input of the first reference signal interface is the second square wave signal.
  • a PWM signal with a frequency of 500 KHz and a duty cycle of 50% is selected, which is a continuous square wave signal.
  • the input of the control signal input interface is the first square wave signal, the high level of the first square wave signal and the second square wave signal are the same (the low level is 0V), and the duty cycle can be the same or different.
  • the high level of the first square wave signal and the second square wave signal are both 3.3V as an example, to illustrate the working principle process of the encoding module to realize encoding.
  • the first square wave signal is marked as Control_signal_Tx
  • the second square wave signal is marked as 500KHz_PWM.
  • the second square wave signal is used to convert the level of the control signal.
  • the high level and low level here refer to the high and low levels of the logic level, and their specific voltage values correspond to actual voltage values.
  • the high level corresponds to 3.3V
  • the low level corresponds to 0V.
  • Control_signal_Tx is 0V (that is, the first square wave signal is low)
  • the NAND gate U1 outputs a high level, that is, the NAND gate U1 outputs 3.3V (the high level at this time corresponds to the first square wave signal or the new high level of the second square wave), and
  • the NAND gate U3 also outputs a high level, and the NAND gate U3 outputs a high level of 3.3V.
  • the levels of the two input terminals of the XOR gate U2 are different (one 0V low level, one 3.3V high level), and the XOR gate U2 outputs a high level, outputting 3.3V, that is, outputting to the connection resistor R1
  • the voltage at one end is 3.3V.
  • resistor R1 and resistor R5 are connected in parallel and then connected in series with resistor R2.
  • the voltage at the connection point M after being divided by the voltage divider circuit is about 0.99V.
  • the resistance value is not 100% of the nominal value, there will be a very small error. Of course, in practical applications, since the error is very small, it can be assumed that the voltage at the connection point M is equal to 0.99V.
  • NAND gate U1 outputs high level, that is, NAND gate U1 outputs 3.3V
  • NAND gate U3 outputs low level, that is, NAND gate U3 outputs low level 0V.
  • the levels of the two input terminals of the XOR gate U2 are the same (both are 0V low level), and the XOR gate U2 outputs a low level and outputs 0V, that is, the voltage output to the end of the connection resistor R1 is 0V.
  • the end of the resistance R1 connected to the output end of the XOR gate U2 is 0V
  • the end of the resistance R5 connected to the output end of the NAND gate U3 is also 0V.
  • the voltage at the connection point M is 0V.
  • Control_signal_Tx is 3.3V (that is, the first square wave signal is high)
  • the NAND gate U1 outputs a low level, that is, the NAND gate U1 outputs 0V, the NAND gate U3 outputs a high level, and the NAND gate U3 outputs a high level of 3.3V.
  • the levels of the two input terminals of the XOR gate U2 are different (one 0V low level, one 3.3V high level), and the XOR gate U2 outputs a high level, outputting 3.3V, that is, outputting to the connection resistor R1
  • the voltage at one end is 3.3V.
  • the resistor R2 and the resistor R5 are connected in parallel and connected in series with the resistor R1, and the voltage at the connection point M after voltage division is about 0.49V.
  • the NAND gate U1 outputs a low level, that is, the NAND gate U1 outputs 0V
  • the NAND gate U3 outputs a high level, that is, the NAND gate U3 outputs a high level of 3.3V.
  • the levels of the two input ends of the XOR gate U2 are the same (both are 3.3V low level), and the XOR gate U2 outputs a low level and outputs 0V, that is, the voltage output to the end of the connection resistor R1 is 0V.
  • the terminal connected to the output terminal of the resistor R5 and the NAND gate U3 is 3.3V.
  • the resistor R2 and the resistor R5 are connected in parallel and connected in series with the resistor R1, and the voltage at the connection point M after voltage division is about 0.49V.
  • the truth table of the input control signal, the first reference signal and the output terminal of the coding module (that is, the connection point M) is as follows:
  • the logic level of the control signal at the top in the figure refers to Control_signal_Tx
  • the logic level of the square wave signal refers to 500KHz_PWM
  • the signal voltage/u after encoding refers to the output end after encoding by this encoding module (ie, the connection point M) the output encoded signal, so as to realize the encoding of the control signal.
  • the encoding signal output by the encoding module is a straight line level (that is, DC voltage), and the level value is 0.49V, which is about the highest level of the encoding signal (0.99V ) half;
  • the coded signal follows the first reference signal and keeps inversion, that is, when the first reference signal is low, the coded signal is just at high level, while the first reference signal is high
  • the level is low, the encoded signal is just at low level, and the high level of the encoded signal is 0.99V.
  • the output end of the encoding module is connected to the coaxial line through the isolation module, that is, the end connected to the connection point M and the capacitor C4 is connected to the isolation module together.
  • the isolation module includes capacitor C2, resistor R1, inductor L3, magnetic bead LB3 and magnetic bead LB4. Resistor R1 and inductor L3 are connected in parallel to form a parallel branch. Capacitor C2, parallel branch, magnetic bead LB4 and magnetic bead LB3 are connected in series and connected axis connection. Capacitor C2 has a certain capacitance value.
  • the isolation module composed of capacitor C2 and other resistors and magnetic beads can isolate the DC voltage on the coaxial line, preventing the direct reaction of the DC voltage transmitted by the power supply and receiving module to the coaxial line. Fill it on the encoding module. Since the control signal is a square wave with a certain frequency, the output coding signal is also a square wave with a certain frequency, and the coding module output by the coding module can be loaded onto the coaxial line through the isolation module. Thus, the control signal, video signal and power transmission are transmitted on the same coaxial line.
  • the decoding module includes a non-inverting amplification module, a signal shaping module, a hysteresis comparator module and a level isolation module connected in sequence.
  • the in-phase amplification module is connected to the coaxial line through the isolation module, and is used to amplify the voltage of the encoded signal sent from the coaxial line.
  • the amplification factor is a times, and a is a positive number greater than 1, and a is usually 3. That is, zoom in 3 times.
  • the signal shaping module is used to output DC voltage after the control signal is high level and encoded by the encoding module. Generate a level value whose voltage value is the same as the DC voltage output by the encoding module.
  • the signal shaping module when the control signal is at a high level, the encoding signal output by the encoding module is a DC voltage, and the DC voltage is 0.49V. Therefore, the signal shaping module also generates a regulated 0.5V level at this time. It is equivalent to making the coded signal be transmitted to the hysteresis comparator module after passing through the signal shaping module when it is a DC voltage.
  • the hysteresis comparator module is provided with a second reference voltage, and the hysteresis comparator module is used to compare the voltage output by the signal shaping module with the second reference voltage to output a voltage in phase with the encoded signal, thereby completing decoding.
  • the encoding signal is a group of square wave signals with a high level (that is, peak value) of 0.99V.
  • a square wave signal with a high level of 2.97V is formed.
  • the signal is an AC signal and can be input to the signal shaping module through the capacitor C7, but the DC signal cannot be transmitted to the signal shaping module through the capacitor C7.
  • the output voltage is about 3V and output to the hysteresis comparison circuit.
  • the signal shaping module functions to stabilize the voltage and generate a DC voltage with the same voltage value as the DC voltage corresponding to the encoded signal when the control signal is at a high level.
  • the level isolation module is used for the post-stage circuit (equipment or component) connected to the output end of the decoding circuit to directly act on the hysteresis comparator circuit, which affects the stability of the hysteresis comparator module and isolates the output signal of the hysteresis comparator module.
  • the high level of the encoded signal output by the encoding module includes two level values of 0.99V and 0.49V, and the difference between the two levels is about 0.5V, which is not conducive to distinguishing. Therefore, the voltage of the encoded signal is amplified by 3 times , the corresponding level values are 2.97V and 1.47V respectively. At this time, the difference between the two levels is about 1.5V, which can be well distinguished. After the level difference is amplified, it is beneficial in subsequent signal shaping and signal comparison, so as to help distinguish two level signals and avoid false triggering.
  • the non-inverting amplification module is connected to the signal shaping module through a capacitor C7, and the capacitor C7 is used to prevent the DC voltage from passing through.
  • in-phase amplifying module capacitance C6, electric capacity C8, in-phase amplifier U4, resistance R4, resistance R6, resistance R7, resistance R8 and resistance R9, one end of electric capacity C8 and the connection point M of encoding module, one end of electric capacity C4 are common with electric capacity C2
  • One end of the connection that is, they are connected to the coaxial line through the isolation module.
  • the other end of the capacitor C8 and one end of the resistor R9 are jointly connected with the non-inverting input end of the non-inverting amplifier U4 (pin No. 2 in Fig.
  • the first parallel branch includes a resistor R7 and a capacitor C6 connected in parallel.
  • the other end of the resistor R4 is connected to the first reference voltage, the first reference voltage is a DC voltage of 3.3V, and the voltage value of the first reference voltage remains the same as the level value of the control signal.
  • the other end of the resistor R6 is connected to the output terminal of the non-inverting amplifier U4 (pin No. 3 in Fig. 4) in series with the resistor R8, and the inverting input terminal of the non-inverting amplifier (pin 1 in Fig. 4) is also connected between the resistor R6 and the resistor R8. number pin), that is, the output terminal of the non-inverting amplifier U4 is connected to the direction input terminal after passing through the resistor R8.
  • the signal shaping module includes a transistor Q1, a transistor Q2, a second parallel branch, a third parallel branch, a resistor R3 and a resistor R12.
  • the second parallel branch includes resistors R10, R11 and capacitor C5 connected in parallel. One end of the second parallel branch is grounded, and the other end is connected to the collector of the transistor Q1 (pin No. 3 in Figure 5) after connecting the resistor R3 in series. , and directly connected to the base of the transistor Q1, the collector of the transistor Q1 is also connected to the first reference voltage, that is, the first reference voltage and one end of the resistor R3 are jointly connected to the collector of the transistor Q1.
  • the emitter of the transistor Q1 is respectively connected in series with the resistor R12 to be grounded, and connected to the base of the transistor Q2.
  • the collector of the transistor Q2 is connected to the first reference voltage, and the emitter of the transistor Q2 is connected to the input end of the hysteresis comparator through a third parallel branch.
  • the third parallel branch circuit includes a resistor R16, a resistor R17, a resistor R18, a capacitor C9, a capacitor C10, and a capacitor C11.
  • One end of the parallel connection of the capacitor C11 and the resistor R18 is connected to the emitter of the transistor Q2 and connected to one end of the resistor R17, and the capacitor C11 and The other end of the parallel connection of resistor R18 is grounded.
  • One end of the resistor R17 is respectively connected to the resistor R16 and one end of the capacitor C10, the other end of the resistor R16 is respectively connected to one end of the capacitor C9 and the input end of the hysteresis comparator module, the other end of the capacitor C9, the other end of the capacitor C10, and the capacitor C11
  • the other end connected in parallel with the resistor R18 is commonly grounded.
  • the hysteresis comparator module includes a non-inverting amplifier U7, a resistor R20, a resistor R21, a resistor R22, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C15 and a diode D2.
  • the inverting input terminal of the non-inverting amplifier U7 is connected to the output terminal of the signal shaping circuit, that is, to the other terminal of the resistor R16.
  • the output terminal of the non-inverting amplifier U7 is connected in series with the resistor R21 to the non-inverting input terminal of the non-inverting amplifier U7, and the output terminal of the non-inverting amplifier U7 is also connected to the input terminal of the level isolation module.
  • the fourth parallel branch circuit includes a resistor R22, a diode D2, a capacitor C13, a capacitor C14, and a capacitor C15.
  • One end of the parallel connection of the capacitor C13 and the capacitor C14 is connected to one end of the resistor R12 and is jointly connected to the first reference voltage, and the capacitor C13 and the capacitor C14 are connected in parallel.
  • the non-inverting amplifier U7 and peripheral circuits are used to form a hysteresis comparator module, and a comparator may also be used instead of the non-inverting amplifier U7.
  • the level isolation module includes a NAND gate U5, a NAND gate U6, a resistor R13, a resistor R14, a resistor R15 and a resistor R19, one end of the resistor R14 is connected to the first reference voltage, and the other end of the resistor R14 is connected to the NAND gate U6. first input. One end of the resistor R13 is also connected to the first reference voltage, and the other end of the resistor R13 is connected to the first input end of the NAND gate U5.
  • the second input terminal of the NAND gate U6 is connected to the output terminal of the hysteresis comparator module, that is, connected to the output terminal of the non-inverting amplifier U7, and the second input terminal of the NAND gate U6 is also connected to the NAND gate U5 after passing through the series resistor R16
  • the output end of the NAND gate U6 is connected to the second input end of the NAND gate U5.
  • the output terminal of the NAND gate U5 is connected in series with a resistor R15 to the output interface, which is the decoded signal obtained by outputting the decoding module, that is, Control_signal_RX in Figure 3 represents the decoded signal output by the output interface, and the decoded signal is That is, the received coded signal is the control signal before coding, so that the coded signal is decoded and the control signal is restored.
  • the above encoding module and decoding module are both based on a discrete element gate circuit composed of logic gates and discrete components.
  • the discrete components include resistors, capacitors, and triodes, and the logic gates include elements such as NAND gates and XOR gates.
  • the frequency of the control signal is much lower than the frequency of the video signal, and the frequency of the video signal is a high-frequency signal relative to the control signal.
  • the high frequency or much lower here does not refer to the specific quantitative numerical probability, but refers to Relative comparison concept.
  • the frequency of the control signal is 10KHz-500KHz, and the frequency of the video signal is 200MHz-3GHz. It can be considered that the frequency of the control signal is much lower than the frequency of the video signal, or it can be considered that the video signal is a high-frequency signal.
  • the frequency of the control signal is at least one order of magnitude lower than the frequency of the video signal. Generally, it can be considered that the frequency of the control signal is much lower than the frequency of the video signal.
  • the video signal cannot be loaded to the encoding module and the decoding module through the isolation module, and the isolation module can effectively isolate high-frequency signals. Therefore, the frequency of the control signal is much lower than the frequency of the video signal, which means that the encoded signal that can satisfy the control signal can be loaded to the coaxial line through the isolation module, but the video signal cannot be loaded to the encoding module and the decoding module through the isolation module. .
  • the working principle of the encoding module to realize the encoding of the control signal is as follows: when the control signal is at a high level, according to the working principle of the encoding module and Figure 8, no matter whether the second square wave signal input by the first reference signal interface is at a high level or Still low level, the encoding signal is a straight line with a voltage of 0.49V (that is, a DC voltage).
  • the DC voltage is amplified to 1.47V by the non-inverting amplifier module, and the DC voltage with a voltage of 1.47V cannot be transmitted to the subsequent circuit through the capacitor C7.
  • the signal shaping module generates a DC voltage with the same voltage as the encoded signal output by the encoding module, that is, generates a DC voltage of about 0.5V.
  • the output of the signal shaping module to the inverting input terminal of the non-inverting amplifier U7 in the hysteresis comparator module is 0.5V
  • the second reference voltage input by the non-inverting input terminal of the non-inverting amplifier U7 is 2.5V
  • the second reference voltage of 2.5V is passed through the stabilized It is realized by voltage diode D2, and its specification is a 2.5V Zener diode.
  • the input DC voltage of 0.5V is less than the second reference voltage
  • the non-inverting amplifier U7 outputs a high level, that is, the hysteresis comparator module outputs a high level, that is, outputs a 3.3V voltage
  • the high level output by the hysteresis comparator module passes through the voltage
  • the two NAND gates (U5, U6) in the flat isolation module act, they can output high level stably, that is, output 3.3V voltage.
  • the level output by the decoding module is the same as the level of the control signal, and the decoding is completed when the control signal is at a high level.
  • the encoding signal output by the encoding module is a group of square wave signals with a peak-to-peak value of 0.99V, and the 0.99V square wave signal is output as a 2.97V square wave signal after passing through the non-inverting amplifier module.
  • the 2.97V square wave signal can be transmitted to the subsequent circuit through the capacitor C7, and the signal shaping module shapes the 2.97V square wave signal into a 3V DC voltage, which is equivalent to stabilizing the square wave signal to a certain fixed voltage value to form The effect of DC voltage.
  • the voltage input from the signal shaping module to the non-inverting amplifier U7 is 3V, which is higher than the second reference voltage of 2.5V.
  • the hysteresis comparator outputs a low level, that is, outputs 0V.
  • the low level output by the hysteresis comparator passes through the two NAND gates (U5, U6) in the level isolation module, and outputs a low level stably.
  • the level output by the decoding module is the same as the level of the control signal, and the decoding is completed when the control signal is at a low level.
  • the decoding module completes the decoding of the control signal encoded by the encoding module, and can restore the control signal.
  • control signals, video signals and power transmission can be transmitted on the same coaxial line.
  • the second reference voltage in the hysteresis comparator module is 2.5V, and the voltage value of the second reference voltage needs to be between the output voltage (0V) of the signal shaping module when the control signal is at a high level and when the control signal is at a low level Signal shaping module output voltage (3V).
  • the first reference voltage connected to the hysteresis comparator module is 3.3V, and the first reference voltage of 3.3V forms the second reference voltage after being acted on by the Zener diode D2, which can provide the non-inverting amplifier U7 with a voltage of about 2.5V. second reference voltage.
  • the devices provided in this embodiment are generally connected to both ends of the same coaxial line.
  • Device A and device B in the figure both adopt the device provided by this embodiment, wherein device A is used as a power supply end, and device B is used as a power receiving end.
  • Both the power supply circuit in device A and the power receiving circuit in device B refer to the power supply and reception module of this embodiment, and the video receiving circuit and video sending circuit are both data transmission modules, that is, their data interfaces.
  • the communication signal encoding module refers to the encoding module
  • the communication signal decoding circuit refers to the decoding module.
  • the A device When the A device is used as the power supply end and the B device is used as the power receiving end, the A device provides 24V DC voltage to the B device through the coaxial cable, and the A device receives the video signal sent by the B device through the coaxial cable and encodes the control signal The coded signal of the device A decodes the coded signal. The device B receives and decodes the response signal returned by the control signal from the device A, so that the device B controls the device A through the control signal.
  • the respective functions are just reversed, that is, the device can realize encoding and decoding.

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Abstract

本发明公开一种基于同一同轴线实现数据、控制和输电装置，其包括供受电模块、数据传输模块、编码模块、解码模块和隔离模块，供受电模块用于将第一直流电压加载到同轴线上或者接收从同轴线传输过来的第一直流电压，数据传输模块用于将数据信号加载到同轴线上，或者接收从同轴线传输过来的数据信号，编码模块用于将控制信号进行编码，解码模块用于对所述编码信号进行解码，以还原出控制信号，隔离模块用于将编码信号经隔离模块后加载到同轴线上或将同轴线传输过来的编码信号加载到编码模块上，且隔离所述数据信号，阻止数据信号加载到编码模块或解码模块上。本发明能够很好地在同一根同轴线实现同时传输数据信号、控制信号和进行供电。

Description

一种基于同一同轴线实现数据、控制和输电装置 技术领域
本发明涉及同轴线数据、控制信号传输和输电技术领域，具体涉及一种基于同一同轴线实现数据、控制和输电装置。
背景技术
同轴线具有很好抗干扰性能使得数据传输稳定，同时还因传输距离远和成本低的特点而应用广泛，特别在数据通信中得到大范围应用。现有技术中，还没有发现可以在同一根同轴线同时实现数据、控制信号传输和输电。以视频信号作为数据为例，往往用其中一根同轴线用于传输视频信号，一根同轴线传输控制信号，另一根同轴线用于向其他设备输电。这导致在实际应用时，为了实现两个终端通信和输电需求，至少需要布设3根同轴线，布线复杂，不能翻板快捷实现系统搭建且代理搭建成本高，以及对现场布设的实施人员的技术要求也高，导致很多应用场景受到限制。特别是在一些空间受限而无法大量布设线缆的场地，可能导致无法采用同轴线实现其需求。
发明内容
针对现有技术的不足，本发明的目的提供一种基于同一同轴线实现数据、控制和输电装置，其能够解决同一根同轴线实现传输数据、控制信号和输电的问题。
实现本发明的目的之一的技术方案为：一种基于同一同轴线实现数据、控制和输电装置，包括供受电模块、数据传输模块、编码模块、解码模块和隔离模块，
所述供受电模块包括输电端和第一滤波电路，输电端的一端通过第一滤波电路与外部的同轴线连接，
第一滤波电路用于隔离数据传输模块加载在同轴线上的数据信号、编码模块加载到同轴线上的编码信号，防止数据信号和编码信号倒灌至供受电模块，
输电端用于连接第一直流电压以使得第一直流电压经第一滤波电路加载到同轴线上，或者接收从同轴线经第一滤波电路传输过来的第一直流电压，
所述数据传输模块包括第二滤波电路，数据传输模块用于将数据信号经第二滤波电路加载到同轴线上，或者接收从同轴线经第二滤波电路传输过来的数据信号，数据信号的频率为n，
所述编码模块用于将控制信号进行编码并输出编码信号，控制信号是频率为m的方波信号，m<<n，
当控制信号为高电平时，编码信号为直流电压q；当控制信号为低电平时，编码信号为方波信号p，直流电压q的电压值小于方波信号p的高电平，方波信号p的高电平小于控制信号的高电平，
所述解码模块用于对所述编码信号进行解码，以还原出控制信号，
所述隔离模块用于将编码信号经隔离模块后加载到同轴线上或将同轴线传输过来的编码信号加载到编码模块上，且隔离所述数据信号，阻止数据信号加载到编码模块或解码模块上，
编码模块和解码电路均是基于由逻辑门与分立元件构成的分立元件门 电路，
其中，所述第二滤波电路能够隔离从同轴线上传输过来的编码信号，防止编码信号加载到数据传输模块。
进一步地，所述第一滤波电路包括依次串联的电感L1、磁珠LB1、电感L2和磁珠LB2，电感L1的一端与输电端的一端连接，磁珠LB2的一端与同轴线连接。
进一步地，所述第二滤波电路为电容C1。
进一步地，所述编码模块包括控制信号输入接口、第一基准信号接口、与非门U1、与非门U3、异或门U2、电阻R1、电阻R2和电阻R5，
控制信号输入接口用于接收所述控制信号，第一基准信号接口用于接收第一基准信号，第一基准信号是频率为f的方波信号，
控制信号输入接口分别和与非门U1的两个输入端连接，以及和异或门U2的第一输入端连接，与非门U1的输出端和与非门U3的第一输入端连接，第一基准信号接口和与非门U3的第二输入端连接，与非门U3的输出端分别和异或门U2的第二输入端、电阻R5的一端连接，异或门U2的输出端与电阻R1的一端连接，电阻R1的另一端、电阻R5的另一端共同与电阻R2的一端连接，电阻R2的另一端接地。
进一步地，所编码模块还包括电容C4，电容C4并联在电阻R2的两端，电容C4为用于旁路滤波。
进一步地，所述隔离模块包括电容C2、电阻R1、电感L3、磁珠LB3和磁珠LB4，电阻R1和电感L3并联形成并联支路，电容C2、并联支路、磁珠 LB4和磁珠LB3依次串联后与同轴线连接。
进一步地，所述解码模块包括依次连接的同相放大模块、信号整形模块和迟滞比较器模块，同相放大模块通过电容C7与信号整形模块连接，
同相放大模块通过所述隔离模块与同轴线连接，用于对从同轴线发送过来的编码信号进行电压放大，以使得同相放大模块输出的高电平与低电平的差值大于第一差值，第一差值为方波信号p的高电平与直流电压q的低电平的差值，
信号整形模块用于直流电压q经过同相放大模块输出后无法通过电容C7时，信号整形模块生成一个与直流电压q的电压相等的电平信号t1，电平信号t1的电压为r1，以及用于方波信号p经同相放大模块放大后整形成电压r2的电平信号t2，电压r2大于同相放大模块对方波信号p放大后的电压值，
迟滞比较器模块内设有第二基准电压，第二基准电压大于电压r1且小于电压r2，迟滞比较器模块用于根据第二基准电压分布与电压r1和电压r2进行比较结果输出解码信号，
当第二基准电压大于电压r1时，迟滞比较器模块输出低电平，当第二基准电压小于电压r2时，迟滞比较器模块输出高电平，从而完成对编码信号解码，还原出控制信号。
进一步地，所述解码模块还包括电平隔离模块，迟滞比较器模块的输出端与电平隔离模块连接，电平隔离模块用于隔离与迟滞比较器连接的后级电路对迟滞比较器模块的影响，防止影响迟滞比较器工作的稳定性。
进一步地，所述电平隔离模块包括与非门U5、与非门U6、电阻R13、电阻R14、电阻R15和电阻R19，电阻R14的一端连接第一基准电压，电阻R14的另一端连接与非门U6的第一输入端，电阻R13的一端也连接第一基准电压，电阻R13的另一端连接与非门U5的第一输入端，与非门U6的第二输入端与迟滞比较器模块的输出端连接，与非门U6的第二输入端还通过串联电阻R16后和与非门U5的输出端连接，与非门U6的输出端和与非门U5的第二输入端连接，与非门U5的输出端串联一个电阻R15后作为用于与后级电路连接的输出端，第一基准电压的电平值与控制信号的高电平相等。
进一步地，所述直流电压q的电压值为方波信号p的高电平的一半。
本发明的有益效果为：本发明能够很好地在同一根同轴线实现同时传输数据信号、控制信号和进行供电，能够减少在实际应用时的布线等操作麻烦，提高应用的普适性。
附图说明
图1是较佳实施例的实现基于同一同轴线实现数据、控制和输电装置的电路示意图；
图2是图1中编码模块的电路示意图；
图3是图1中解码模块的电路示意图；
图4是图3中同相放大模块的电路示意图；
图5是图3中信号整形模块的电路示意图；
图6是图3中迟滞比较器模块的电路示意图；
图7是图3中电平隔离模块的电路示意图；
图8是编码模块中控制信号、第二方波信号与编码模块中三个与非门的输出以及编码模块最终输出的编码信号的对应关系示意图；
图9是将本实施例提供的装置分别连接在同一根同轴线的两端的使用状态示意图。
具体实施方式
下面，下面结合附图以及具体实施方案，对本发明做进一步描述。
首先，本实施例的输电包括向外供电和向内受电，当本装置作为供电端时用于向外供电，作为受电端时则向内受电，即接受外部提供的电源。
如图1-图8所示，一种基于同一同轴线实现数据、控制和输电装置，该装置可以作为供电端，通过同轴线向外供电；也可以作为受电端，通过同轴线接受另一装置传输过来的电源。当该装置作为供电端时，该装置接收另一装置发送过来的数据和控制信号，并且通过返回应答信号来响应控制信号。当该装置作为受电端时，该装置向另一装置发送数据和控制信号。本实施例以视频信号作为所述数据为例进行详细说明，即视频信号作为需要传输或通信的数据。其中一个装置作为主机，另一个装置作为从机，主机用作供电端，从机用作受电端，从机向主机发送视频信号，主机向从机发送控制信号，且从机接收到控制信号后返回应答信号，应答信号也是通过编码模块编码后发出。两个装置不能同时发送或同时接收，只能一端为发送、另一端接收。
其中，视频信号是可以本装置内部生成的视频信号，也可以是外部向本装置传送过来的视频信号。
所述装置包括供受电模块、数据传输模块、编码模块、解码模块和隔离模块。编码模块和解码模块的输出端共同串联隔离模块的输入端，隔离模块的输出端、供受电模块的输出端与数据传输模块的共同连接点作为统一输出端，统一输出端连接同轴线。在实际使用时，本装置连接同轴线的一端，同轴线的另一端连接与本装置相同的另一个装置。也即隔离模块的输出端、供受电模块的输出端与数据传输模块的输出端共同连接同轴线的一端，同轴线的另一端连接另一个装置的隔离模块、供受电模块与数据传输模块的共同连接点，而此时另一端的共同连接点作为输入端。也即同轴线两端连接的两个装置可以相互转换，一个作为供电端时，另一个作为受电端。
所述供受电模块包括输电端，输电端的一端通过串联连接第一滤波电路后与同轴线连接，第一滤波电路包括依次串联的电感L1、磁珠LB1、电感L2和磁珠LB2，也即电感L1的一端与输电端的一端连接，磁珠LB2的一端与同轴线连接。第一滤波电路用于隔离同轴线上的视频信号和控制信号，防止视频信号和控制信号传输到输电端。当供受电模块用于供电时，即供受电模块所在的装置为供电端时，输电端的另一端连接提供第一直流电压的电源，该电源向输电端输入第一直流电压，第一直流电压优选为24V的直流电压，第一直流电压通过第一滤波电路后经同轴线向外供电。当供受电模块用于受电(即接收电压)时，即供受电模块所在的装置为受电端时，输电端的另一端连接其他用电设备(包括电路)或电子元件，经同轴线传输过来的第一直流电压经过第一滤波电路后经输电端的另一端传输给后级的其他设备或电子元件供电。
当通过输电端向供受电模块输入24V直流电压后，经过由电感和磁珠构 成的滤波电路后把电压加载到同轴线上传输，并经同轴线传输给受电设备，即传输给另一个装置。
其中，第一直流电压的电压值通常较大，以使得第一直流电压能够通过第一滤波电路传输到同轴线上，而同轴线上传输过来的小电压的直流电压又无法经第一滤波电路传输到输电端，也即第一滤波电路能够很好地维持第一直流电压通过、隔离同轴线上的视频信号和控制信号。
所述数据传输模块包括数据接口，数据接口串联一电容C1后和供受电模块共同连接同轴线。当本装置作为供电端时，数据接口接收经同轴线传输过来的视频信号，视频信号经过电容C1后传输给数据接口，数据接口再将视频信号传送给后级设备。当本装置作为受电端时，数据接口接收后级设备发送过来的视频信号，数据接口将视频信号经过电容C1后传输至同轴线，同轴线再将视频信号向外传输，即传输给另一个终端。图1中的Video_signal_RX表示接收经同轴线传输过来的视频信号，此时的装置是作为供电端，接收的视频信号是由其他终端仅同轴线传输过来的。视频信号可以采用SDI(数字分量串行接口)信号。数据接口经同轴线接收的视频信号或向同轴线传输的视频信号是具有一定频率的信号，例如为一定频率的方波信号。
电容C1能够对同轴线上的第一直流电压进行隔离，防止第一直流电压通过数据传输模块损坏数据接口连接的后级设备，而电容C1能够允许具有一定频率的视频信号通过。从而实现输电与数据在同一根同轴线上进行传输。电容C1还能够隔离低频方波信号，防止编码信号能够经电容C1传输到数据传输模块，即传输到数据接口。电容C1允许高频的视频信号通过，也 即在第一直流电压、编码信号和视频信号三者之中，只允许视频信号通过。
所述编码模块包括控制信号输入接口、第一基准信号接口、与非门U1、与非门U3、异或门U2、电阻R1、电阻R2、电阻R5和电容C4。控制信号输入接口(即图2中的Control_signal_Tx)分别和与非门U1的两个输入端连接，以及和异或门U2的第一输入端(图2中U2的A端)连接。与非门U1的输出端(图2中U1的Y端)和与非门U3的第一输入端连接。第一基准信号接口(即图2中的500KHz_PWM)和与非门U3的第二输入端连接。与非门U3的输出端分别和异或门U2的第二输入端、电阻R5的一端连接。异或门U2的输出端与电阻R1的一端连接，电阻R1的另一端、电阻R5的另一端共同与电阻R2的一端连接，电阻R2的另一端接地。可见电阻R5的两端分别在异或门U2的输入端和输出端。电阻R1、电阻R2和电阻R5共同连接处记为连接点M，如图2中的M点。电容C4并联在电阻R2的两端，即电容C4的一端与连接点M连接，另一端与电阻R2的另一地共同接地。电容C4起到旁路滤波，对编码信号进行滤波，对编码信号滤波也即相当于对控制信号进行滤波。编码模块是一个逻辑电路。
需要说明的是，虽然编码模块输出的编码信号也会直接经过电容C8传输至解码模块，但在实际应用中可以区分出是直接传输过来的还是经过同轴线传输过来的。通过发送的控制信号和响应控制信号而返回的应答信号的数据帧可以区分出，通过数据帧头能够区分是直接传输还是经同轴线传输过来的编码信号，或者通过发送的控制信号和接收的应答信号的数据位数、数据校验来区分。直接传输过来的编码信号可以进行舍弃，从而能够对另一个装置传输的编码信号和本地的编码信号进行区分，以便准确解码。
其中，连接点M也即是编码模块的输出端，即电阻R1、电阻R2、电阻R5和电容C4的共同连接端是编码模块的输出端，输出端串联隔离模块后与同轴线连接，从而使得编码模块、供电受模块和数据传输模块共同连接到同轴线上。电阻R1、电阻R2、电阻R5构成分压电路，用于将第一方波信号和第二方波信号的电平输出后进行降压输出一个电平信号。
在本实施例中，电阻R1、电阻R2、电阻R5的阻值依次为470Ω、100Ω和470Ω，电容C1的电容值为220pF。
第一基准信号接口输入的是第二方波信号，本实施例选取频率为500KHz、占空比为50％的PWM信号，是一个连续的方波信号。控制信号输入接口输入的是第一方波信号，第一方波信号和第二方波信号的高电平相同(其低电平即是0V)，占空比可以相同也可以不同。本实施例以第一方波信号和第二方波信号的高电平均为3.3V为例，阐述编码模块实现编码的工作原理过程。其中，第一方波信号记为Control_signal_Tx，第二方波信号记为500KHz_PWM。第二方波信号用于对控制信号电平进行转换。
这里的高电平和低电平是指逻辑电平的高低电平，其具体电压值对应到实际的电压值，本实施例，高电平对应3.3V，低电平对应0V。
当Control_signal_Tx为0V(即第一方波信号为低电平)时，
若500KHz_PWM为0V，与非门U1输出高电平，即与非门U1输出3.3V(此时的高电平对应的是第一方波信号或第二方波新的高电平)，与非门U3也是输出高电平，与非门U3输出高电平3.3V。此时，异或门U2的两个输入端的电平相异(一个0V低电平，一个3.3V高电平)，异或门U2输出高电平， 输出3.3V，即输出到连接电阻R1一端的电压为3.3V。此时，电阻R1和电阻R5并联后与电阻R2串联，连接点M处经分压电路的分压后的电压大小约为0.99V，约为0.99V是因电阻R1、电阻R2、电阻R5的阻值不是100％的标称值，会存在极小误差。当然，在实际应用中，由于误差很小，可以认定连接点M处的电压等于0.99V。
若500KHz_PWM为3.3V，与非门U1输出高电平，即与非门U1输出3.3V，与非门U3输出低电平，即与非门U3输出低电平0V。此时，异或门U2的两个输入端的电平相同(均为0V低电平)，异或门U2输出低电平，输出0V，即输出到连接电阻R1一端的电压为0V。电阻R1与异或门U2输出端连接的一端处为0V，电阻R5的与非门U3输出端连接的一端也为0V。此时，连接点M处的电压为0V。
当Control_signal_Tx为3.3V(即第一方波信号为高电平)时，
若500KHz_PWM为0V，与非门U1输出低电平，即与非门U1输出0V，与非门U3输出高电平，与非门U3输出高电平3.3V。此时，异或门U2的两个输入端的电平相异(一个0V低电平，一个3.3V高电平)，异或门U2输出高电平，输出3.3V，即输出到连接电阻R1一端的电压为3.3V。此时，电阻R2和电阻R5并联后与电阻R1串联，连接点M处经分压后的电压大小约为0.49V。
若500KHz_PWM为3.3V，与非门U1输出低电平，即与非门U1输出0V，与非门U3输出高电平，即与非门U3输出高电平3.3V。此时，异或门U2的两个输入端的电平相同(均为3.3V低电平)，异或门U2输出低电平，输出 0V，即输出到连接电阻R1一端的电压为0V。但此时，电阻R5和与非门U3输出端连接的一端为3.3V。此时，电阻R2和电阻R5并联后与电阻R1串联，连接点M处经分压后的电压大小约为0.49V。
综上，输入的控制信号、第一基准信号和编码模块输出端(即连接点M)的真值表如下：
Figure PCTCN2021122611-appb-000001
参考图8，图中最上端的控制信号逻辑电平即是指Control_signal_Tx，方波信号逻辑电平即是指500KHz_PWM，编码后信号电压/u即是指经此编码模块编码后输出端(即连接点M)输出的编码信号，从而实现对控制信号的编码。从该图中可看出，当控制信号为高电平时，编码模块输出的编码信号为一条直线电平(即直流电压)，电平值为0.49V，约为编码信号最高电平(0.99V)的一半；当控制信号为低电平时，编码信号跟随第一基准信号变化并且保持反相，即第一基准信号为低电平时，编码信号正好处于高电平，而第一基准信号为高电平时，编码信号正好处于低电平，且编码信号的高电平为0.99V。实现了对控制信号的编码。
以上四种情况，从逻辑电平来说，大致是这样的：
当控制信号为0、第一基准信号为0时，与非门U1输出为1，与非门U3输出为1，异或门U2输出为1。
当控制信号为0、第一基准信号为1时，与非门U1输出为1，与非门U3 输出为0，异或门U2输出为0。
当控制信号为1、第一基准信号为0时，与非门U1输出为0，与非门U3输出为1，异或门U2输出为0。
当控制信号为1、第一基准信号为1时，与非门U1输出为1，与非门U3输出为1，异或门U2输出为0。
编码模块的输出端通过隔离模块与同轴线连接，也即连接点M和电容C4连接的一端共同与隔离模块连接。隔离模块包括电容C2、电阻R1、电感L3、磁珠LB3和磁珠LB4，电阻R1和电感L3并联形成并联支路，电容C2、并联支路、磁珠LB4和磁珠LB3依次串联后与同轴线连接。电容C2具有一定电容值大小的电容，电容C2和其他电阻、磁珠构成的隔离模块能够对同轴线上的直流电压进行隔离，防止供受电模块传输到同轴线上的直流电压直接反灌到编码模块上。由于控制信号是一定频率的方波，输出的编码信号也是具有一定频率的方波，编码模块输出的编码模块可以经过隔离模块加载到同轴线上。从而实现了控制信号、视频信号和输电在同一根同轴线上进行传输。
所述解码模块包括依次连接的同相放大模块、信号整形模块、迟滞比较器模块和电平隔离模块。同相放大模块通过所述隔离模块与同轴线连接，用于对接收从同轴线发送过来的编码信号进行电压放大，放大倍数为a倍，a为大于1的正数，a通常为3，即放大3倍。信号整形模块用于当控制信号为高电平经编码模块编码后输出直流电压，直流电压经过同相放大模块输出后因电容C7隔离而导致同相放大模块无法给信号整形模块输出电压时，信号整形模块生成一个电压值与编码模块输出的直流电压相同的电平值。本实 施例中，当控制信号为高电平时，编码模块输出的编码信号为直流电压，该直流电压为0.49V，因此，信号整形模块也在此时生成一个稳压的0.5V电平。相当于使得编码信号为直流电压时也经过信号整形模块后传输到迟滞比较器模块。迟滞比较器模块内设置有第二基准电压，迟滞比较器模块用于根据信号整形模块输出的电压和第二基准电压进行比较而输出与编码信号同相电压，从而完成解码。而当控制信号为低电平时，编码信号是一组高电平(即峰值)为0.99V的方波信号，经过同相放大模块后，形成高电平为2.97V的方波信号，该方波信号属于交流信号，可以通过电容C7而输入至信号整形模块，但直流信号无法通过电容C7传输至信号整形模块。信号整形模块对该方波信号进行整形后输出电压约为3V左右输出至迟滞比较电路。信号整形模块起到稳压和生成一个与控制信号为高电平时对应编码信号的直流电压相同电压值的直流电压。电平隔离模块用于解码电路输出端连接的后级电路(设备或部件)直接作用在迟滞比较器电路上，影响迟滞比较器模块工作的稳定性，起到对迟滞比较器模块输出信号隔离。
编码模块输出的编码信号的高电平包括0.99V和0.49V两个电平值，两个电平差值大约在0.5V左右，不利于区分，为此将编码信号的电压进行放大3倍后，对应的电平值分别为2.97V和1.47V，此时两个电平差值大约在1.5V，能够很好地进行区分。电平差值放大后，在后续的信号整形、信号比较时都是有利的，以有利于区分两种电平信号，避免误触发。
在一个可选的实施方式中，同相放大模块通过电容C7与信号整形模块连接，电容C7用于阻止直流电压经过。
所述同相放大模块电容C6、电容C8、同相放大器U4、电阻R4、电阻R6、 电阻R7、电阻R8和电阻R9，电容C8的一端和编码模块的连接点M、电容C4的一端共同与电容C2的一端连接，也即共同通过隔离模块与同轴线连接。电容C8的另一端和电阻R9的一端共同与同相放大器U4的同相输入端(图4中的2号引脚)连接，电阻R9的另一端分别与第一并联支路的一端、电阻R4的一端和电阻R6的一端连接，也即电阻R9的另一端、第一并联支路的一端、电阻R4的一端和电阻R6的一端共同连接，第一并联支路的另一端接地。第一并联支路包括并联连接的电阻R7和电容C6。电阻R4的另一端连接第一基准电压，第一基准电压为3.3V的直流电压，第一基准电压的电压值保持与控制信号的电平值相同。电阻R6的另一端串联电阻R8后与同相放大器U4的输出端(图4中的3号引脚)连接，电阻R6与电阻R8之间还与同相放大器的反相输入端(图4中的1号引脚)连接，也即同相放大器U4的输出端通过电阻R8后与方向输入端连接。
所述信号整形模块包括三极管Q1、三极管Q2、第二并联支路、第三并联支路、电阻R3和电阻R12。第二并联支路包括并联的电阻R10、电阻R11和电容C5，第二并联支路的一端接地，另一端分别串联电阻R3后与三极管Q1的集电极(图5中的3号引脚)连接，以及直接与三极管Q1的基极连接，三极管Q1的集电极还连接第一基准电压，也即第一基准电压和电阻R3的一端共同连接三极管Q1的集电极。三极管Q1的发射极分别串联电阻R12后接地，以及与三极管Q2的基极连接。三极管Q2的集电极连接第一基准电压，三极管Q2的发射极通过第三并联支路连接迟滞比较器的输入端。第三并联支路包括电阻R16、电阻R17、电阻R18、电容C9、电容C10和电容C11，电容C11和电阻R18并联的一端与三极管Q2的发射极连接且与电阻R17的一 端连接，电容C11和电阻R18并联的另一端接地。电阻R17的一端分别与电阻R16、电容C10的一端连接，电阻R16的另一端分别与电容C9的一端和迟滞比较器模块的输入端连接，电容C9的另一端、电容C10的另一端、电容C11和电阻R18并联的另一端共同接地。
所述迟滞比较器模块包括同相放大器U7、电阻R20、电阻R21、电阻R22、电容C12、电容C13、电容C14、电容C15和二极管D2。同相放大器U7的反相输入端与信号整形电路的输出端连接，即与电阻R16的另一端连接。同相放大器U7的输出端串联电阻R21后与同相放大器U7的同相输入端连接，同相放大器U7的输出端还与电平隔离模块的输入端连接。电容C12的一端、电阻R20的一端与电阻R21的一端共同与同相放大器U7的同相输入端连接，电容C12的另一端接地，电阻R20的另一端与第四并联支路的一端连接，第四并联支路的另一端接地。第四并联支路包括电阻R22、二极管D2、电容C13、电容C14、电容C15，电容C13、电容C14并联连接的一端与电阻R12的一端连接且共同连接第一基准电压，电容C13、电容C14并联连接的另一端、电容C15的一端和二极管D2的正极共同接地，电容C15的另一端、电阻R22的另一端、电阻R20的另一地共同连接二极管D2的负极。
本实施例中，采用同相放大器U7和外围电路构成迟滞比较器模块，也可以采用比较器替代同相放大器U7。
所述电平隔离模块包括与非门U5、与非门U6、电阻R13、电阻R14、电阻R15和电阻R19，电阻R14的一端连接第一基准电压，电阻R14的另一端连接与非门U6的第一输入端。电阻R13的一端也连接第一基准电压，电阻R13的另一端连接与非门U5的第一输入端。与非门U6的第二输入端与迟滞 比较器模块的输出端连接，也即与同相放大器U7的输出端连接，与非门U6的第二输入端还通过串联电阻R16后和与非门U5的输出端连接，与非门U6的输出端和与非门U5的第二输入端连接。与非门U5的输出端串联一个电阻R15后与输出接口连接，该输出接口即是输出解码模块经解码得到的解码信号，也即图3中的Control_signal_RX表述输出接口输出的解码信号，解码信号也即是接收到的编码信号编码前的控制信号，从而实现了对编码信号进行解码，还原出控制信号。
上述编码模块和解码模块均是基于由逻辑门与分立元件构成的分立元件门电路，分立元件包括电阻、电容和三极管等元件，逻辑门包括与非门、异或门等元件，
本实施例控制信号的频率远低于视频信号的频率，视频信号的频率相对于控制信号来说属于高频信号，这里的高频或者远低于并不是指具体量化的数值概率，而是指相对比较概念。例如，控制信号频率在10KHz-500KHz，视频信号频率在200MHz-3GHz，可以认为控制信号频率远低于视频信号频率，或者此时可以认为视频信号属于高频信号。控制信号频率至少低于视频信号频率一个单位数量级，一般就可以认为控制信号的频率远低于视频信号的频率。例如，以在KHz数量级，另一个在MHz数量级。从而使得视频信号无法通过隔离模块而加载到编码模块和解码模块，隔离模块可以有效隔离高频信号。因此，控制信号的频率远低于视频信号的频率，是指能够满足控制信号经编码后的编码信号能够通过隔离模块加载到同轴线，而视频信号无法通过隔离模块加载到编码模块和解码模块。
编码模块实现对控制信号编码的工作原理如下：当控制信号为高电平 时，根据编码模块的工作原理和图8可知，此时第一基准信号接口输入的第二方波信号无论处于高电平还是低电平，编码信号是一条电压为0.49V的直线(即直流电压)，该直流电压经过同相放大模块放大为1.47V，电压为1.47V的直流电压无法通过电容C7传输到后级电路。此时的信号整形模块生成一个与编码模块输出的编码信号相同电压的直流电压，即生成一个约为0.5V的直流电压。信号整形模块输出到迟滞比较器模块中同相放大器U7的反相输入端为0.5V，而同相放大器U7的同相输入端所输入的第二基准电压为2.5V，2.5V的第二基准电压通过稳压二极管D2实现，其规格是2.5V稳压二极管。因此，输入的0.5V直流电压小于第二基准电压，同相放大器U7输出高电平，也即迟滞比较器模块输出高电平，即输出3.3V电压，迟滞比较器模块输出的高电平经过电平隔离模块中的两个与非门(U5，U6)作用后，能够稳定地输出高电平，即输出3.3V电压。解码模块输出的电平与控制信号的电平相同，完成控制信号为高电平时的解码。
当控制信号为低电平时，编码模块输出的编码信号是一组峰峰值为0.99V的方波信号，0.99V的方波信号经过同相放大模块后输出为2.97V的方波信号。2.97V的方波信号能够通过电容C7传输给后级电路，信号整形模块将2.97V的方波信号整形为3V直流电压，相当于起到将方波信号稳压到某一固定电压值而形成直流电压的作用。信号整形模块输入到同相放大器U7的电压为3V，高于2.5V的第二基准电压，因此，迟滞比较器输出低电平，即输出0V。迟滞比较器输出的低电平经过电平隔离模块中的两个与非门(U5，U6)作用后，稳定地输出低电平。解码模块输出的电平与控制信号的电平相同，完成控制信号为低电平时的解码。
最终，解码模块完成控制信号经编码模块编码后的解码，能够还原出控制信号。从而使得控制信号、视频信号和输电能够在同一根同轴线上进行传输。
在上述过程中，迟滞比较器模块中的第二基准电压为2.5V，第二基准电压的电压值需要介于控制信号为高电平时信号整形模块输出电压(0V)和控制信号为低电平时信号整形模块输出电压(3V)。其中，迟滞比较器模块连接的第一基准电压为3.3V，3.3V的第一基准电压经稳压二极管D2作用后形成所述第二基准电压，能够给同相放大器U7提供一个约为2.5V的第二基准电压。
参考图9，在实际应用中，通常将本实施例提供的装置分别连接在同一根同轴线的两端。图中的A设备和B设备均是采用本实施例提供的装置，其中A设备作为供电端，B设备作为受电端。A设备中的电源供电电路和B设备中的电源受电电路都是指本实施例的供受电模块，视频接收电路和视频发送电路均是数据传输模块，也即是其数据接口。通信信号编码模块是指编码模块，通信信号解码电路是指解码模块。
A设备作为供电端、B设备作为受电端时，A设备通过同轴线向B设备提供24V的直流电压，A设备接收由B设备经同轴线发送过来的视频信号和对控制信号进行编码的编码信号，A设备对编码信号进行解码。B设备接收A设备对控制信号返回的响应信号进行解码，实现B设备通过控制信号控制A设备。当A设备作为受电端、B设备作为供电端时，各自起到的作用刚好反过来，也即本装置能够实现编码和解码。
本说明书所公开的实施例只是对本发明单方面特征的一个例证，本发明的保护范围不限于此实施例，其他任何功能等效的实施例均落入本发明的保护范围内。对于本领域的技术人员来说，可根据以上描述的技术方案以及构思，做出其它各种相应的改变以及变形，而所有的这些改变以及变形都应该属于本发明权利要求的保护范围之内。

Claims (10)

  1. 一种基于同一同轴线实现数据、控制和输电装置，其特征在于，包括供受电模块、数据传输模块、编码模块、解码模块和隔离模块，
    所述供受电模块包括输电端和第一滤波电路，输电端的一端通过第一滤波电路与外部的同轴线连接，
    第一滤波电路用于隔离数据传输模块加载在同轴线上的数据信号、编码模块加载到同轴线上的编码信号，防止数据信号和编码信号倒灌至供受电模块，
    输电端用于连接第一直流电压以使得第一直流电压经第一滤波电路加载到同轴线上，或者接收从同轴线经第一滤波电路传输过来的第一直流电压，
    所述数据传输模块包括第二滤波电路，数据传输模块用于将数据信号经第二滤波电路加载到同轴线上，或者接收从同轴线经第二滤波电路传输过来的数据信号，数据信号的频率为n，
    所述编码模块用于将控制信号进行编码并输出编码信号，控制信号是频率为m的方波信号，m<<n，
    当控制信号为高电平时，编码信号为直流电压q；当控制信号为低电平时，编码信号为方波信号p，直流电压q的电压值小于方波信号p的高电平，方波信号p的高电平小于控制信号的高电平，
    所述解码模块用于对所述编码信号进行解码，以还原出控制信号，
    所述隔离模块用于将编码信号经隔离模块后加载到同轴线上或将同轴线传输过来的编码信号加载到编码模块上，且隔离所述数据信号，阻止数据信号加载到编码模块或解码模块上，
    编码模块和解码电路均是基于由逻辑门与分立元件构成的分立元件门电路，
    其中，所述第二滤波电路能够隔离从同轴线上传输过来的编码信号，防止编码信号加载到数据传输模块。
  2. 根据权利要求1所述的基于同一同轴线实现数据、控制和输电装置，其特征在于，所述第一滤波电路包括依次串联的电感L1、磁珠LB1、电感L2和磁珠LB2，电感L1的一端与输电端的一端连接，磁珠LB2的一端与同轴线连接。
  3. 根据权利要求1所述的基于同一同轴线实现数据、控制和输电装置，其特征在于，所述第二滤波电路为电容C1。
  4. 根据权利要求1所述的基于同一同轴线实现数据、控制和输电装置，其特征在于，所述编码模块包括控制信号输入接口、第一基准信号接口、与非门U1、与非门U3、异或门U2、电阻R1、电阻R2和电阻R5，
    控制信号输入接口用于接收所述控制信号，第一基准信号接口用于接收第一基准信号，第一基准信号是频率为f的方波信号，
    控制信号输入接口分别和与非门U1的两个输入端连接，以及和异或门U2的第一输入端连接，与非门U1的输出端和与非门U3的第 一输入端连接，第一基准信号接口和与非门U3的第二输入端连接，与非门U3的输出端分别和异或门U2的第二输入端、电阻R5的一端连接，异或门U2的输出端与电阻R1的一端连接，电阻R1的另一端、电阻R5的另一端共同与电阻R2的一端连接，电阻R2的另一端接地。
  5. 根据权利要求4所述的基于同一同轴线实现数据、控制和输电装置，其特征在于，所编码模块还包括电容C4，电容C4并联在电阻R2的两端，电容C4为用于旁路滤波。
  6. 根据权利要求1所述的基于同一同轴线实现数据、控制和输电装置，其特征在于，所述隔离模块包括电容C2、电阻R1、电感L3、磁珠LB3和磁珠LB4，电阻R1和电感L3并联形成并联支路，电容C2、并联支路、磁珠LB4和磁珠LB3依次串联后与同轴线连接。
  7. 根据权利要求1所述的基于同一同轴线实现数据、控制和输电装置，其特征在于，所述解码模块包括依次连接的同相放大模块、信号整形模块和迟滞比较器模块，同相放大模块通过电容C7与信号整形模块连接，
    同相放大模块通过所述隔离模块与同轴线连接，用于对从同轴线发送过来的编码信号进行电压放大，以使得同相放大模块输出的高电平与低电平的差值大于第一差值，第一差值为方波信号p的高电平与直流电压q的低电平的差值，
    信号整形模块用于直流电压q经过同相放大模块输出后无法通过电容C7时，信号整形模块生成一个与直流电压q的电压相等的电 平信号t1，电平信号t1的电压为r1，以及用于方波信号p经同相放大模块放大后整形成电压r2的电平信号t2，电压r2大于同相放大模块对方波信号p放大后的电压值，
    迟滞比较器模块内设有第二基准电压，第二基准电压大于电压r1且小于电压r2，迟滞比较器模块用于根据第二基准电压分布与电压r1和电压r2进行比较结果输出解码信号，
    当第二基准电压大于电压r1时，迟滞比较器模块输出低电平，当第二基准电压小于电压r2时，迟滞比较器模块输出高电平，从而完成对编码信号解码，还原出控制信号。
  8. 根据权利要求7所述的基于同一同轴线实现数据、控制和输电装置，其特征在于，所述解码模块还包括电平隔离模块，迟滞比较器模块的输出端与电平隔离模块连接，电平隔离模块用于隔离与迟滞比较器连接的后级电路对迟滞比较器模块的影响，防止影响迟滞比较器工作的稳定性。
  9. 根据权利要求8所述的基于同一同轴线实现数据、控制和输电装置，其特征在于，所述电平隔离模块包括与非门U5、与非门U6、电阻R13、电阻R14、电阻R15和电阻R19，电阻R14的一端连接第一基准电压，电阻R14的另一端连接与非门U6的第一输入端，电阻R13的一端也连接第一基准电压，电阻R13的另一端连接与非门U5的第一输入端，与非门U6的第二输入端与迟滞比较器模块的输出端连接，与非门U6的第二输入端还通过串联电阻R16后和与非门U5的 输出端连接，与非门U6的输出端和与非门U5的第二输入端连接，与非门U5的输出端串联一个电阻R15后作为用于与后级电路连接的输出端，第一基准电压的电平值与控制信号的高电平相等。
  10. 根据权利要求1所述的基于同一同轴线实现数据、控制和输电装置，其特征在于，所述直流电压q的电压值为方波信号p的高电平的一半。
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