WO2023000345A1 - 近场通信nfc装置及开环控制方法 - Google Patents

近场通信nfc装置及开环控制方法 Download PDF

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Publication number
WO2023000345A1
WO2023000345A1 PCT/CN2021/108291 CN2021108291W WO2023000345A1 WO 2023000345 A1 WO2023000345 A1 WO 2023000345A1 CN 2021108291 W CN2021108291 W CN 2021108291W WO 2023000345 A1 WO2023000345 A1 WO 2023000345A1
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WIPO (PCT)
Prior art keywords
frequency
clock signal
signal
phase
digital
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PCT/CN2021/108291
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English (en)
French (fr)
Inventor
于锐
陈雪松
刘苏鹏
王磊
余展
杨腾智
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180099555.4A priority Critical patent/CN117652122A/zh
Priority to EP21950594.8A priority patent/EP4362380A1/en
Priority to PCT/CN2021/108291 priority patent/WO2023000345A1/zh
Publication of WO2023000345A1 publication Critical patent/WO2023000345A1/zh
Priority to US18/418,693 priority patent/US20240195454A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/40—Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by components specially adapted for near-field transmission
    • H04B5/45—Transponders
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/20—Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by the transmission technique; characterised by the transmission medium
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/20—Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by the transmission technique; characterised by the transmission medium
    • H04B5/24—Inductive coupling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • the present application relates to the technical field of near field communication, in particular to a near field communication NFC device and an open-loop control method.
  • NFC Near Field Communication
  • RFID radio frequency identification
  • interconnection technology is evolved from the integration of non-contact radio frequency identification (RFID) and interconnection technology.
  • Devices using NFC technology can exchange data when they are in close proximity to each other.
  • the NFC technology can be used on an electronic device, such as a mobile phone, to realize the scene of swiping a card when the NFC is turned off, as shown in FIG. 1 .
  • the NFC card reader 11 can send a carrier signal to the mobile phone 12, and the mobile phone 12 can use passive load modulation to modulate data onto the carrier signal, and radiate the modulated signal to the NFC card reader 11.
  • the handset 12 can also use active load modulation to modulate the data onto the carrier signal.
  • active load modulation to modulate the data onto the carrier signal.
  • the first method requires a local clock generator to generate a clock signal, which will generate additional power consumption, and the second method will cause active load modulation or when the modulation depth of the carrier signal received from the NFC card reader 11 is large If the recovered field clock signal is not ideal, the output of the phase-locked loop will be unsatisfactory, which will affect the communication between the mobile phone 12 and the NFC card reader 11 .
  • an embodiment of the present application provides a near-field communication NFC device
  • the near-field communication NFC device includes: a clock extractor, configured to perform clock recovery according to the first carrier signal sent by the NFC card reader, to obtain A field clock signal; a digital phase-locked loop, used for frequency tracking of the field clock signal, and outputting a first clock signal; a digital baseband chip, used for load modulation according to the first clock signal, and generating a second carrier signal;
  • the controller is used to detect the frequency or phase of the vertical clock signal, and selectively control the digital phase-locked loop to open the loop according to the frequency or phase detection result.
  • the controller detects the frequency or phase of the field clock signal, and selectively controls the digital phase-locked loop to open the loop according to the frequency or phase detection result, which can be modulated according to the first carrier signal Deep selective control of the digital phase-locked loop for open loop.
  • the controller is configured to: generate a first open-loop control signal if there is a deviation in the frequency or phase of the field clock signal; the first open-loop control signal is used to control the digital PLL open loop.
  • the first open-loop control signal is generated to control the digital phase-locked loop to open the loop, and the digital phase-locked loop can be controlled when the modulation depth of the first carrier signal received is relatively large.
  • An open loop is performed to prevent the digital phase-locked loop from performing a phase tracking operation according to the discontinuous first carrier signal.
  • the controller is configured to: if there is no deviation in frequency or phase of the field clock signal, control the digital phase-locked loop to perform closed loop.
  • the present application controls the closed-loop of the digital phase-locked loop if there is no deviation in the frequency or phase of the field clock signal, and can control the closed-loop of the digital phase-locked loop when the received first carrier signal is continuous, so that the digital phase-locked loop can be controlled according to the continuous first
  • the carrier signal performs a phase tracking operation.
  • the controller is further configured to: receive the first clock signal output by the digital phase-locked loop, perform frequency multiplication on the first clock signal to obtain a second clock signal, and use The second clock signal samples the vertical clock signal, and detects the frequency or phase of the vertical clock signal according to the sampling result.
  • This application samples the field clock signal after multiplying the frequency of the first clock signal output by the digital phase-locked loop, and detects the frequency or phase of the field clock signal according to the sampling result, so that the frequency or phase of the field clock signal can be realized. detection.
  • the controller includes a frequency multiplier, a processor, and a digital circuit: the frequency multiplier is used to multiply the frequency of the first clock signal and then output a second clock signal; the processing The device is used to determine the number of high-frequency clocks in the second clock signal, and use the field clock signal to determine the sampling result, and detect the frequency or phase of the field clock signal according to the sampling result, wherein the sampling result is in the The number of high-frequency clocks in the clock cycle of the vertical clock signal; if there is a deviation in the number of high-frequency clocks in the clock cycle of the vertical clock signal, there is a deviation in the frequency or phase of the vertical clock signal, and the frequency Or the phase detection result is a first level; the digital circuit is used to generate the first open-loop control signal according to the frequency or phase detection result of the first level.
  • the processor calculates the number of high-frequency clocks in the clock cycle of the field clock signal, and determines whether there is a deviation in the frequency or phase of the field clock signal according to the number of high-frequency clocks in the clock cycle of the field clock signal, and generates a frequency Or the phase detection result to the digital circuit, the digital circuit is used to generate the first open-loop control signal to the digital phase-locked loop according to the frequency or phase detection result of the first level, which can quickly and accurately identify the frequency or phase deviation of the field clock signal , and can quickly generate the first open-loop control signal to the digital phase-locked loop.
  • the processor includes a counter and a digital signal processor; the counter is used to receive the second clock signal and record the number of the high-frequency clocks in the second clock signal.
  • the digital signal processor is used to obtain the number of high-frequency clocks from the counter in the current clock cycle of the field clock signal, and obtain the number of high-frequency clocks according to the current clock cycle and the previous clock cycle. The number of high-frequency clocks determines the number of high-frequency clocks in the current clock cycle.
  • the application records the number of high-frequency clocks through a counter, and calculates the number of high-frequency clocks in the current clock cycle of the field clock signal through a digital signal processor according to the number of high-frequency clocks recorded by the counter and the field clock signal, which can realize Quickly and accurately calculate the number of high-frequency clocks in the clock cycle of the field clock signal.
  • the digital signal processor is further configured to: compare the number of high-frequency clocks in the current clock cycle with a preset range to determine the high-frequency clock in the current clock cycle of the field clock signal Whether there is a deviation in the number of clocks, and correspondingly determine whether there is a deviation in the frequency or phase of the field clock signal; wherein, the preset range corresponds to the second clock signal one by one; if the current clock period If the number of internal high-frequency clocks is not within the preset range, there is a deviation in the number of high-frequency clocks in the current clock cycle of the vertical clock signal, and there is a deviation in the frequency or phase of the vertical clock signal.
  • This application determines whether there is a deviation in the number of high-frequency clocks in the current clock cycle through the number of high-frequency clocks in the current clock cycle and the preset range, and generates corresponding results. According to the high-frequency clock in the clock cycle of the clock signal The number of clocks determines whether there is a skew in the frequency or phase of the clock signal.
  • the controller is configured to: receive the first carrier signal, detect the amplitude of the first carrier signal, and if the amplitude of the first carrier signal is greater than a preset value, control the The above-mentioned digital phase-locked loop is closed-loop.
  • the present application controls the digital phase-locked loop to close the loop if the amplitude of the first carrier signal is greater than the preset value.
  • the digital phase-locked loop can be controlled to close the loop, and the digital phase-locked loop can be controlled.
  • the phase loop performs a phase tracking operation based on the continuous first carrier signal.
  • the controller includes an amplitude detection circuit, a delay circuit, and a digital circuit: the amplitude detection circuit is configured to receive the first carrier signal, detect the amplitude of the first carrier signal, and The amplitude of the first carrier signal generates an amplitude detection result; wherein, if the amplitude of the first carrier signal is greater than a preset value, the amplitude detection result is a second level; the delay circuit is used to convert the The amplitude detection result is delayed for a preset time and then output to the digital circuit; the digital circuit is used to control the digital phase-locked loop to close the loop according to the amplitude detection result of the second level.
  • the application detects the amplitude of the first carrier signal through the amplitude detection circuit, and the delay circuit delays the amplitude detection result for a preset time before outputting, and the digital circuit controls the digital phase-locked loop to close the loop according to the delayed amplitude detection result, which can provide a received
  • the interval of the more continuous first carrier signal can further prevent the digital phase-locked loop from performing a phase tracking operation according to the discontinuous first carrier signal.
  • the digital phase-locked loop includes a time-to-digital converter, a digital filter, a numerically controlled oscillator, and a frequency divider: the time-to-digital converter and the digital filter are used to receive the first An open-loop control signal, and is used to stop working according to the first open-loop control signal, and maintain the value before receiving the first open-loop control signal to continue to output; the numerically controlled oscillator is used to maintain the value before the open-loop state The oscillating signal continues to oscillate to output the first clock signal; the frequency divider is used to receive the first clock signal and divide the frequency of the first clock signal to reduce the frequency of the first clock signal to equal to or close to the frequency of the field clock signal recovered by the clock extractor.
  • the time-to-digital converter and the digital filter stop working according to the first open-loop control signal, and keep outputting the value before receiving the first open-loop control signal, and the digitally controlled oscillator
  • the oscillation signal used to keep the open-loop state continues to oscillate, which can control the open-loop of the digital phase-locked loop.
  • the digital baseband chip when the load modulation is active load modulation, is further configured to generate a second carrier signal when outputting the second carrier signal to the NFC card reader.
  • An open-loop control signal; the controller also includes a multiplexer MUX, and the multiplexer MUX is used to select according to at least one of the first open-loop control signal and the second open-loop control signal Open-loop control is performed on the digital phase-locked loop.
  • the digital baseband chip when the active load is modulated, the digital baseband chip generates the second open-loop control signal to control the digital phase-locked loop to open the loop, which can control the digital phase-locked loop to open the loop when the active load is modulated, avoiding digital phase-locked
  • the ring performs phase tracking operation according to the discontinuous first carrier signal; through the multiplexer MUX, the two cases of active load modulation and large modulation depth are integrated into one circuit, and the same circuit can be used in different cases, reducing The overall size and cost of the circuit is reduced.
  • an embodiment of the present application also provides an open-loop control method, the open-loop control method includes: the clock extractor of the near field communication NFC device performs clock recovery according to the first carrier signal sent by the NFC card reader , to obtain a field clock signal; the digital phase-locked loop of the near field communication NFC device carries out frequency tracking to the field clock signal, and outputs a first clock signal; the digital baseband chip of the near field communication NFC device according to the first The clock signal is subjected to load modulation to generate a second carrier signal; the controller of the near field communication NFC device detects the frequency or phase of the field clock signal, and selectively controls the digital phase-locked loop according to the detection result.
  • the open-loop control method further includes: if there is a deviation in the frequency or phase of the field clock signal, generating a first open-loop control signal; the first open-loop control signal is used to control The digital phase locked loop is open loop.
  • the controller detecting the frequency or phase of the field clock signal includes: the controller receiving the first clock signal output by the digital phase-locked loop, and converting the first clock signal to A second clock signal is obtained after the signal is frequency multiplied, and the second clock signal is used to sample the field clock signal, and the frequency or phase of the field clock signal is detected according to the sampling result.
  • the controller multiplies the frequency of the first clock signal to obtain a second clock signal, uses the second clock signal to sample the field clock signal, and detects The frequency or phase of the field clock signal includes: forming a controller including a frequency multiplier, a processor, and a digital circuit: the frequency multiplier multiplies the frequency of the first clock signal and then outputs a second clock signal; The processor determines the number of high-frequency clocks in the second clock signal, and uses the field clock signal to determine the sampling result, and detects the frequency or phase of the field clock signal according to the sampling result, wherein the sampling result is in the The number of high-frequency clocks in the clock cycle of the field clock signal; if there is a deviation in the number of high-frequency clocks in the clock cycle of the field clock signal, there is a deviation in the frequency or phase of the field clock signal, and the The frequency or phase detection result is a first level; the digital circuit generates the first open-loop control signal according to the frequency or phase detection result of the
  • the processor determining the number of high-frequency clocks in the second clock signal, and using the field clock signal to determine the sampling result includes: forming the processor comprising a counter and a digital signal processor ;
  • the counter receives the second clock signal, and records the number of the high-frequency clock in the second clock signal;
  • the number of high-frequency clocks is obtained, and the number of high-frequency clocks in the current clock cycle is determined according to the number of high-frequency clocks obtained in the current clock cycle and the number of high-frequency clocks obtained in the previous clock cycle.
  • the processor detecting the frequency or phase of the vertical clock signal according to the sampling result includes: the digital signal processor comparing the number of high-frequency clocks in the current clock cycle with the preset The preset range determines whether there is a deviation in the number of high-frequency clocks in the current clock cycle of the field clock signal, and accordingly determines whether there is a deviation in the frequency or phase of the field clock signal; wherein, the preset range One-to-one correspondence with the second clock signal; if the number of high-frequency clocks in the current clock cycle is not within the preset range, the number of high-frequency clocks in the current clock cycle of the field clock signal There is a deviation in the number, and there is a deviation in the frequency or phase of the field clock signal.
  • the open-loop control method further includes: the controller receives the first carrier signal, detects the amplitude of the first carrier signal, and if the amplitude of the first carrier signal is greater than preset value, then control the digital phase-locked loop to perform closed-loop.
  • the controller detects the amplitude of the first carrier signal, and if the amplitude of the first carrier signal is greater than a preset value, controlling the digital phase-locked loop to close the loop includes: forming The controller comprising an amplitude detection circuit, a delay circuit and a digital circuit; the amplitude detection circuit receives the first carrier signal, detects the amplitude of the first carrier signal, and generates Amplitude detection result; wherein, if the amplitude of the first carrier signal is greater than a preset value, the amplitude detection result is at the second level; the delay circuit delays the amplitude detection result for a preset time and outputs it to the The digital circuit; the digital circuit controls the digital phase-locked loop to close the loop according to the amplitude detection result of the second level.
  • the open-loop control method further includes: when the load modulation is active load modulation, the digital baseband chip of the near field communication NFC device outputs the second carrier signal Generate a second open-loop control signal to the NFC card reader; the multiplexer MUX of the controller selects according to at least one of the first open-loop control signal and the second open-loop control signal Open-loop control is performed on the digital phase-locked loop.
  • FIG. 1 is a schematic diagram of an existing NFC shutdown card swiping scenario.
  • FIG. 2 is a block diagram of an existing phase-locked loop control circuit.
  • FIG. 3 is a schematic diagram of an open-loop signal generated by a pause detector of a conventional PLL control circuit.
  • Fig. 4 is a block diagram of a near field communication NFC device and an NFC card reader according to the first embodiment of the present application.
  • FIG. 5 is a schematic diagram of a controller of the near field communication NFC device in FIG. 4 controlling a digital phase-locked loop according to a first carrier signal.
  • FIG. 6 is a block diagram of a processor of the controller of FIG. 5 .
  • FIG. 7 is a state transition diagram of a digital phase-locked loop of the near field communication NFC device in FIG. 4 .
  • FIG. 8 is a working sequence diagram of the near field communication NFC device in FIG. 4 .
  • FIG. 9 is a block diagram of a near field communication NFC device and an NFC card reader according to a second embodiment of the present application.
  • Fig. 10 is a block diagram of a near-field communication NFC device and an NFC card reader according to the second embodiment of the present application, wherein the thick line shows the near-field communication NFC device when the modulation depth of the first carrier signal received is relatively large work process.
  • Fig. 11 is a block diagram of a near field communication NFC device and an NFC card reader according to the second embodiment of the present application, where the thick line shows the working process of the near field communication NFC device during active load modulation.
  • Fig. 12 is a flowchart of an open-loop control method according to an embodiment of the present application.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of said features.
  • words such as “for example” are used as examples, illustrations or descriptions. Any embodiment or design solution described as “for example” in the embodiments of the present application shall not be interpreted as being more preferable or more advantageous than other embodiments or design solutions. Rather, the use of words such as “such as” is intended to present related concepts in a concrete manner.
  • FIG. 2 is a block diagram of a conventional PLL control circuit
  • FIG. 3 is a schematic diagram of an open-loop signal generated by a pause detector of the conventional PLL control circuit.
  • the PLL control circuit 2 may include a clock buffer 21 , a reference clock prescaler 22 , a clock extractor 23 , a pause detector 24 , a multiplexer 25 and an analog PLL 26 .
  • the clock buffer 21 is used for buffering the clock signal generated by the local clock generator.
  • the clock extractor 23 is used to recover a clock signal from the received signal.
  • the clock buffer 21 is connected to the multiplexer 25 through the reference clock prescaler 22 .
  • the clock extractor 23 is connected to the multiplexer 25 .
  • the output of the multiplexer 25 is connected to an analog phase locked loop 26 .
  • the output of the clock extractor 23 is connected to a pause detector 24 .
  • the output of the pause detector 24 is connected to an analog phase locked loop 26 .
  • the pause detector 24 detects the amplitude according to the output of the clock extractor 23 and the phase difference between the clock signal recovered by the clock extractor and the output of the analog phase-locked loop, and outputs the detection signal to the analog phase-locked loop 26 according to the amplitude and phase difference , to control the analog phase-locked loop 26 to open the loop.
  • the precision of the analog phase-locked loop 26 of the existing phase-locked loop control circuit 2 is difficult to control, the open loop easily affects the stability of the loop, and the closed-loop establishment takes a long time.
  • FIG. 4 is a block diagram of a near field communication NFC device and an NFC card reader according to the first embodiment of the present application.
  • the NFC card reader 5 sends the first carrier signal (radio frequency field with a frequency of 13.56MHZ) to the near field communication NFC device 4 .
  • the NFC device 4 transmits the load-modulated second carrier signal to the NFC card reader 5 .
  • the near field communication NFC device 4 includes an antenna 41 , a matching circuit 42 , a clock extractor 43 , a controller 44 , a digital phase-locked loop 45 , a digital baseband chip 46 , and a transmitter 47 .
  • the antenna 41 may be an antenna supporting radio frequency transmission and reception.
  • the antenna 41 is used for receiving the first carrier signal sent by the NFC card reader 5 .
  • the matching circuit 42 is connected to the antenna 41 to form a resonant circuit together with the antenna 41 .
  • the clock extractor 43 is connected with the matching circuit 42, and is used for performing clock recovery according to the first carrier signal sent by the NFC card reader 5 to obtain a field clock signal.
  • the digital phase-locked loop 45 is connected with the clock extractor 43, and is used to track the frequency of the field clock signal and output the first clock signal.
  • the digital baseband chip 46 is connected to the digital phase-locked loop 45, and is used for performing load modulation according to the first clock signal to generate a second carrier signal.
  • a frequency divider can be connected between the digital baseband chip 46 and the digital phase-locked loop 45, and the frequency divider is used to divide the first clock signal in frequency, and the digital baseband chip 46 is used for the first clock signal after frequency division
  • the target data is up-modulated to generate the second carrier signal. It can be understood that there are other ways to realize the generation of the second carrier signal according to the first clock signal, which is not limited in the present application.
  • the transmitter 47 is connected between the digital baseband chip 46 and the matching circuit 42 for converting the second carrier signal into a radio frequency signal and transmitting it to the NFC card reader 5 through the antenna 41 .
  • the controller 44 is connected with the digital phase-locked loop 45 for detecting the frequency or phase of the vertical clock signal, and selectively controlling the digital phase-locked loop 45 to open the loop according to the detection result.
  • the controller 44 is also used to generate a first open-loop control signal if there is a deviation in the frequency or phase of the field clock signal; the first open-loop control signal is used to control the open-loop of the digital phase-locked loop 45 .
  • the controller 44 is further configured to control the digital phase-locked loop 45 to close the loop if there is no deviation in the frequency or phase of the vertical clock signal.
  • the controller 44 also receives the first carrier signal, detects the amplitude of the first carrier signal, and if the amplitude of the first carrier signal is greater than a preset value, controls the digital phase-locked loop 45 to perform a closed loop .
  • the modulation depth of the first carrier signal can be determined based on the frequency or phase of the vertical clock signal. If there is a deviation in the frequency or phase of the vertical clock signal, the modulation depth of the received signal is large; if there is no deviation in the frequency or phase of the vertical clock signal, the modulation depth of the received signal is normal.
  • the controller 44 can also receive the first clock signal output by the digital phase-locked loop 45, and obtain a second clock signal after frequency multiplication of the first clock signal, and use the second clock signal to control the field
  • the clock signal is sampled, and the frequency or phase of the field clock signal is detected according to the sampling result.
  • FIG. 5 is a schematic diagram of a controller of a near field communication NFC device controlling a digital phase-locked loop according to a first carrier signal.
  • the controller 44 includes a processor 441 and a digital circuit 442 .
  • the processor 441 is connected between the clock extractor 43 and the digital circuit 442, and is used for detecting the frequency or phase of the field clock signal, and generates a level signal to the digital circuit 442 according to the frequency or phase detection result, and the digital circuit 442 is based on the specified
  • the level signal selectively controls the digital phase-locked loop 45 to open the loop.
  • the controller 44 may further include a frequency multiplier 443 .
  • the frequency multiplier 443 is connected between the digital phase-locked loop 45 and the processor 441 .
  • the frequency multiplier 443 is used to multiply the frequency of the first clock signal to output a second clock signal.
  • the frequency multiplier 443 multiplies the frequency of the first clock signal, so that the output second clock signal is 13.56MHZ ⁇ 128, that is, 1.7GHZ.
  • the frequency multiplier 443 can also perform other frequency multiplications on the frequency of the first clock signal, as long as the frequency of the second clock signal output by the frequency multiplier 443 is greater than twice the frequency of the field clock signal, this Applications are not limited to this.
  • the processor 441 is used to determine the number of high-frequency clocks in the second clock signal, and use the field clock signal to determine the sampling result, and detect the frequency or phase of the field clock signal according to the sampling result, wherein the sampling The result is the number of high frequency clocks in the clock period of the field clock signal. If there is a deviation in the number of high-frequency clocks within the clock period of the vertical clock signal, there is a deviation in the frequency or phase of the vertical clock signal, and the frequency or phase detection result is a first level. If there is no deviation in the number of high-frequency clocks within the clock period of the vertical clock signal, there is no deviation in the frequency or phase of the vertical clock signal, and the frequency or phase detection result is at the second level.
  • the first level is a high level
  • the second level is a low level. It can be understood that the first level may also be a low level, and the second level may also be a high level, which is not limited in the present application.
  • the digital circuit 442 is used to generate the first open-loop control signal according to the frequency or phase detection result of the first level.
  • the digital circuit 442 is also used to control the digital phase-locked loop 45 to close the loop according to the frequency or phase detection result of the second level.
  • the first open-loop control signal is at a high level. It can be understood that the first open-loop control signal may also be at a low level, which is not limited in the present application.
  • the processor 441 includes a counter 4411 and a digital signal processor 4412 .
  • the counter 4411 is an 8-bit counter. It can be understood that the counter 4411 may also be other counters, which is not limited in this application.
  • the counter 4411 is connected with the frequency multiplier 443, and is used for receiving the second clock signal, and recording the number of the high-frequency clocks in the second clock signal.
  • the digital signal processor 4412 is connected with the counter 4411 and the clock extractor 43, and is used to obtain the number of high-frequency clocks from the counter 4411 in the current clock cycle of the field clock signal, and obtain the high-frequency clock according to the current clock cycle.
  • the number of high-frequency clocks obtained in the current clock cycle is less than the number of high-frequency clocks obtained in the previous clock cycle, determine the number of high-frequency clocks in the current clock cycle as the number of high-frequency clocks obtained in the current clock cycle plus The difference between the sum of the maximum number of counts (for example, 256) counted by the upper counter 4411 and the number of high-frequency clocks obtained in the previous clock cycle.
  • the number of high-frequency clocks obtained by the digital signal processor 4412 in the current clock cycle can be obtained at the end of the current clock cycle of the field clock signal, and the high-frequency clocks obtained by the digital signal processor 4412 in the previous clock cycle The number of can be obtained at the end of the previous clock period of the field clock signal.
  • the digital signal processor 4412 is further configured to compare the number of high-frequency clocks in the current clock cycle with a preset range to determine whether there is a deviation in the number of high-frequency clocks in the current clock cycle of the field clock signal, And correspondingly determine whether there is a deviation in the frequency or phase of the field clock signal.
  • the preset range is in one-to-one correspondence with the second clock signal.
  • the second clock signal is 13.56MHZ ⁇ 128, and the preset range may be 127-129. It can be understood that the preset range may also be other ranges or values, such as 128, and the preset range may also be a different range according to the second clock signal, which is not limited in the present application.
  • the preset range may be the range or value set by the system by default or the range or value set by the user according to the second clock signal. If the number of high-frequency clocks in the current clock cycle is not within the preset range, there is a deviation in the number of high-frequency clocks in the current clock cycle of the field clock signal, and the number of high-frequency clocks in the field clock signal There is a deviation in frequency or phase. If the number of high-frequency clocks in the current clock cycle is within the preset range, there is no deviation in the number of high-frequency clocks in the current clock cycle of the field clock signal, and the field clock signal There is no deviation in frequency or phase.
  • the digital signal processor 4412 is connected to the digital circuit 442 and is also used to output frequency or phase detection results to the digital circuit 442, and the digital circuit 442 can selectively control the digital phase-locked loop 45 to open the loop accordingly.
  • the digital PLL 45 includes a time-to-digital converter 451 , a digital filter 452 , a numerically controlled oscillator 453 and a frequency divider 454 .
  • a time-to-digital converter 451, a digital filter 452, a digitally controlled oscillator 453, and a frequency divider 454 are connected in sequence.
  • the time-to-digital converter 451 is connected to the clock extractor 43 .
  • the time-to-digital converter 451 is used to receive the field clock signal recovered by the clock extractor 43, and compare the phase of the field clock signal with the phase of the signal output by the frequency divider 454 to output a digital signal.
  • the frequency multiplier 443 can also be connected with the frequency divider 454, as long as the frequency multiplier 443 can output the preset second clock signal, for example, the frequency multiplied by 5 of the frequency of the first clock signal above 13.56MHZ, it can be understood that the multiplier The frequency divider 443 can also be located in the digital phase-locked loop 45 and connected to the frequency divider 454 or the digitally controlled oscillator 453, only the frequency multiplier 443 can output the preset high-frequency clock, which is not limited in this application.
  • the digital circuit 442 is connected with a time-to-digital converter 451 and a digital filter 452 .
  • the digital circuit 442 is used to generate the first open-loop control signal to the time-to-digital converter 451 and the digital filter 452 .
  • the time-to-digital converter 451 and the digital filter 452 are used to receive the first open-loop control signal, and to stop working according to the first open-loop control signal, and keep receiving the first open-loop control signal. The value before the control signal continues to be output.
  • the digital phase-locked loop 45 turns into an open-loop state, and the digitally controlled oscillator 453 maintains the oscillation signal before the open-loop state and continues to oscillate and output the first clock signal.
  • the digital circuit 442 can also control the time-to-digital converter 451 and the digital filter 452 to continue to work, and the digital phase-locked loop 45 to continue to perform phase tracking operations.
  • FIG. 7 is a state transition diagram of the digital phase-locked loop of the near field communication NFC device.
  • the digital phase-locked loop 45 includes process voltage temperature calibration (PVT) state, close to lock (ACQ) state, phase tracking (TRK) state and hold (HOLD) state, a total of four states.
  • the phase tracking (TRK) state represents the closed-loop state
  • the hold (HOLD) state represents the open-loop state.
  • Process Voltage Temperature Calibration (PVT) state, Approach Lock (ACQ) state and Phase Tracking (TRK) state are executed sequentially.
  • an arrow points to the process voltage temperature calibration (PVT) state, indicating that the process voltage temperature calibration (PVT) is performed when a reset signal is received or the near field communication NFC device 4 is turned on.
  • An arrow points from the phase tracking (TRK) state to the phase tracking (TRK) state, indicating that it remains in the phase tracking (TRK) state.
  • An arrow pointing from the phase tracking (TRK) state to the holding (HOLD) state means that if the first open-loop control signal is received in the phase tracking (TRK) state, the state jumps from the phase tracking (TRK) state to the holding (HOLD) state.
  • An arrow pointing from the hold (HOLD) state to the phase tracking (TRK) state means that if the digital phase-locked loop 45 is closed in the hold (HOLD) state, then jump from the hold (HOLD) state to the phase tracking (TRK) state.
  • the controller 44 may further include an amplitude detection circuit 444 .
  • the amplitude detection circuit 444 is also connected to the matching circuit 42 and the digital circuit 442 for receiving the first carrier signal, detecting the amplitude of the first carrier signal, and generating an amplitude detection result to the digital circuit 442 according to the amplitude of the first carrier signal.
  • the amplitude detection result is the first level.
  • the digital phase-locked loop 45 is in an open-loop state. If the amplitude of the first carrier signal is greater than a preset value, the amplitude detection result is a second level.
  • the controller 44 may also include a delay circuit 445 .
  • the amplitude detection circuit 444 can also be connected to the digital circuit 442 through a delay circuit 445 .
  • the delay circuit 445 can also be set in the amplitude detection circuit 444 .
  • the delay circuit 445 is used to delay the amplitude detection result to the digital circuit 442 after a preset time.
  • the digital circuit 442 is also used to control the digital phase-locked loop 45 to close the loop according to the amplitude detection result of the second level.
  • FIG. 8 is a working sequence diagram of the NFC device for near field communication.
  • Figure 8 shows that when the first carrier signal of the NFC card reader 5 is received by the antenna 41 and the signal is discontinuous due to the large modulation depth, the digital phase-locked loop 45 is between the phase tracking (TRK) state and the hold (HOLD) state Mutual switching working status.
  • the antenna 41 starts to receive the continuous first carrier signal of the NFC card reader 5 .
  • the field clock signal recovered by the clock extractor 43 is stable, and the digital signal processor 4412 of the processor 441 determines that there is no deviation in the frequency or phase of the recovered field clock signal, and outputs the frequency of the second level (low level) or phase detection results.
  • the amplitude detection circuit 444 also determines that the amplitude of the first carrier signal of the NFC card reader 5 received by the antenna 41 is greater than a preset value, then the amplitude detection circuit 444 delays the amplitude detection result of the second level (low level) for a preset time After output.
  • the digital circuit 442 controls the digital phase-locked loop 45 to keep in the phase tracking (TRK) state or enter the phase tracking (TRK) state according to the frequency or phase detection result of the second level and the amplitude detection result of the second level.
  • the antenna 41 receives the first carrier signal of the NFC card reader 5 from a continuous signal to a discontinuous signal, the field clock signal recovered by the clock extractor 43 is unstable, and the digital signal processor of the processor 441 4412 determines that there is a deviation in the frequency or phase of the recovered vertical clock signal, and outputs a frequency or phase detection result of the first level (high level).
  • the digital circuit 442 outputs the first open-loop control signal of the first level (high level) according to the frequency or phase detection result of the first level.
  • the digital phase-locked loop 45 is opened according to the first open-loop control signal.
  • the digital phase-locked loop 45 jumps from the phase tracking (TRK) state to the holding (HOLD) state.
  • the amplitude detection circuit 444 also determines that the amplitude of the first carrier signal of the NFC card reader 5 received by the antenna 41 is less than a preset value, then the amplitude detection circuit 444 delays the amplitude detection result of the first level (high level) by a predetermined period. Output after a set time.
  • the antenna 41 receives the first carrier signal of the NFC card reader 5 from a discontinuous signal to a continuous signal, the field clock signal recovered by the clock extractor 43 is stable, and the amplitude detection circuit 444 determines that the signal received by the antenna 41 is stable. If the amplitude of the first carrier signal of the NFC card reader 5 is greater than the preset value, then the amplitude detection circuit 444 outputs the amplitude detection result of the second level (low level) after a preset time delay.
  • the digital circuit 442 controls the digital phase-locked loop 45 to enter the phase tracking (TRK) state from the holding (HOLD) state according to the amplitude detection result of the second level.
  • the digital signal processor 4412 of the processor 441 also determines that there is no deviation in the frequency or phase of the recovered vertical clock signal, and outputs the frequency or phase detection result of the second level (low level).
  • the present application can just produce the first open-loop control signal when receiving the first level (high level) frequency or phase detection result, control digital phase-locked loop 45 to jump from phase tracking (TRK) state to holding ( HOLD) state; control the digital phase-locked loop 45 to jump from the hold (HOLD) state to the phase tracking (TRK) state when receiving the second level (low level) amplitude detection result.
  • the near field communication NFC device 4 can control the state of the digital phase-locked loop 45 according to the frequency or phase detection result and the amplitude detection result.
  • the digital signal processor 4412 is provided with a delay circuit 445, and the amplitude detection circuit 444 is not connected to the digital circuit 442 through the delay circuit 445, then the first level is generated when the amplitude detection result of the first level (high level) is received.
  • the open-loop control signal controls the digital phase-locked loop 45 to jump from the phase tracking (TRK) state to the holding (HOLD) state; when receiving the frequency or phase detection result of the second level (low level), it controls the digital phase-locking
  • the ring 45 jumps from the holding (HOLD) state to the phase tracking (TRK) state, which is not limited in the present application.
  • the frequency or phase of the field clock signal is detected by the controller 44, and the digital phase-locked loop 45 is selectively controlled to open the loop according to the frequency or phase detection result, which can be selected according to the modulation depth of the first carrier signal.
  • Control digital phase-locked loop 45 to carry out open-loop If there is deviation in the frequency or phase of field clock signal, produce the first open-loop control signal to control digital phase-locked loop 45 to carry out open-loop, the modulation of the first carrier signal that can be received
  • Phase loop 45 closed-loop can control digital phase-locked loop 45 closed-loops when the first carrier signal that receives is continuous, makes digital phase-locked loop 45 carry out phase tracking operation according to continuous first carrier signal; After the frequency of the first clock signal is multiplied, the field clock signal is sampled, and the frequency or phase of the field clock signal is detected according to the sampling result,
  • the digital phase-locked loop 45 is controlled to close the loop, and when the modulation depth of the first carrier signal received is normal, the digital phase-locked loop 45 is controlled to close the loop, and the digital phase-locked loop is controlled.
  • the ring 45 performs a phase tracking operation according to the continuous first carrier signal; the amplitude of the first carrier signal is detected by the amplitude detection circuit 444, and the delay circuit 445 outputs the amplitude detection result after delaying the preset time, and the digital circuit 442 outputs it according to the delayed amplitude
  • the detection result controls the digital phase-locked loop 45 to close the loop, which can provide a more continuous interval of the first carrier signal received, and can further prevent the digital phase-locked loop 45 from performing phase tracking operation according to the discontinuous first carrier signal.
  • FIG. 9 is a block diagram of a near field communication NFC device and an NFC card reader according to a second embodiment of the present application.
  • the near field communication NFC device 9 of the second embodiment is similar to the near field communication NFC device of the first embodiment, the near field communication NFC device 9 of the second embodiment communicates with the NFC card reader 10, and the near field communication NFC device 9 includes Antenna 91 , matching circuit 92 , clock extractor 93 , controller 94 , digital phase-locked loop 95 , digital baseband chip 96 , and transmitter 97 .
  • the antenna 91 of the second embodiment, the matching circuit 92, the clock extractor 93, the digital phase-locked loop 95, the digital baseband chip 96, and the connection relationship and the effect between the transmitter 97 are the same as the antenna of the first embodiment, the matching circuit, Clock extractor, digital phase-locked loop, digital baseband chip, and transmitter have the same connection relationship and effect, and the controller 94 of the second implementation also includes processor 941, digital circuit 942, frequency multiplier 943, amplitude detection circuit 944 and Delay circuit 945, the difference is:
  • the controller 94 also includes a multiplexer MUX 946 .
  • the multiplexer MUX946 is used for selectively performing open-loop control on the digital phase-locked loop 95 according to at least one of the first open-loop control signal and the second open-loop control signal.
  • the multiplexer MUX946 includes an input terminal, a control terminal and an output terminal.
  • the input terminal of the multiplexer MUX946 is connected with the digital baseband chip 96 and the digital circuit 942 of the controller 94 for receiving the first open-loop control signal and the second open-loop control signal.
  • the control terminal of the multiplexer MUX946 is connected with the digital baseband chip 96 for receiving the control signal of the digital baseband chip 96 .
  • the output terminal of the multiplexer MUX946 is connected with the digital phase-locked loop 95.
  • the multiplexer MUX946 determines to connect to the digital baseband chip 96 or the digital circuit 942 according to the control signal of the digital baseband chip 96 .
  • the digital baseband chip 96 when the load modulation is active load modulation, the digital baseband chip 96 outputs the first control signal to the multiplexer MUX946, and the multiplexer MUX946 is controlled to communicate with the digital baseband chip 96, and the digital baseband chip 96 can pass multiple
  • the channel selector MUX946 outputs the second open-loop control signal to control the digital phase-locked loop 95 to perform open-loop.
  • the digital baseband chip 96 also outputs a second control signal to the multiplexer MUX946 when the load modulation is passive load modulation, and controls the multiplexer MUX946 to communicate with the digital circuit 942, and the digital circuit 942 can pass through the multiplexer MUX946. Outputting the first open-loop control signal to control the digital phase-locked loop 95 to perform open-loop.
  • the thick line in FIG. 10 shows the working process of the near field communication NFC device when the modulation depth of the received first carrier signal is relatively large.
  • the working process of the near field communication NFC device 9 when the modulation depth of the received first carrier signal is relatively large is similar to the working process of the near field communication NFC device in the first embodiment, the difference is that the digital circuit 942 passes multiple The road selector MUX946 is connected with the digital phase-locked loop 95.
  • the digital circuit 942 outputs the first open-loop control signal through the multiplexer MUX946 to control the digital phase-locked loop 95 to open the loop; and through the multiplexer MUX946 to control the digital phase-locked loop 95 to close the loop.
  • the antenna 91 may be an antenna supporting radio frequency transmission and reception.
  • the antenna 91 is used for receiving the first carrier signal sent by the NFC card reader 10 .
  • the matching circuit 92 is connected to the antenna 91 to form a resonant circuit together with the antenna 91 .
  • the clock extractor 93 is connected with the matching circuit 92, and is used for performing clock recovery according to the first carrier signal sent by the NFC card reader 10 to obtain a field clock signal.
  • the digital phase-locked loop 95 is connected with the clock extractor 93, and is used to track the frequency of the field clock signal and output the first clock signal.
  • the digital baseband chip 96 is connected to the digital phase-locked loop 95, and is used for performing load modulation according to the first clock signal to generate a second carrier signal.
  • a frequency divider can be connected between the digital baseband chip 96 and the digital phase-locked loop 95, and the frequency divider is used to divide the first clock signal in frequency, and the digital baseband chip 96 is used for the first clock signal after frequency division
  • the target data is up-modulated to generate the second carrier signal. It can be understood that there are other ways to realize the generation of the second carrier signal according to the first clock signal, which is not limited in the present application.
  • the transmitter 97 is connected between the digital baseband chip 96 and the matching circuit 92 for converting the second carrier signal into a radio frequency signal and transmitting it to the NFC card reader 10 through the antenna 91 .
  • the digital baseband chip 96 can be connected with the digital phase-locked loop 95 through the multiplexer MUX946, and is used to output the second open-loop control signal to the digital phase-locked loop 95 through the multiplexer MUX946, and controls the digital phase-locked loop 95 to open the loop .
  • the period in which the digital baseband chip 96 outputs the second open-loop control signal is related to the time when the digital baseband chip 96 outputs the second carrier signal.
  • the digital baseband chip 96 generates the period of the second open-loop control signal according to the period of the second carrier signal, and then the digital baseband chip 96 can set several periods of the digital phase-locked loop 95 as open-loop.
  • the digital baseband chip 96 when the active load is modulated, the digital baseband chip 96 generates a second open-loop control signal to control the digital phase-locked loop 95 to open the loop, and the digital phase-locked loop 95 can be controlled to open the loop when the active load is modulated. Avoid the digital phase-locked loop 95 to perform phase tracking operation according to the discontinuous first carrier signal; through the multiplexer MUX946, the two cases of active load modulation and large modulation depth are integrated in one circuit, which can be used in different situations The same circuit, reducing the overall size and cost of the circuit.
  • FIG. 12 is a flowchart of an open-loop control method according to an embodiment of the present application.
  • the open-loop control method is applied to a near-field communication NFC device.
  • Open-loop control methods include:
  • the clock extractor of the near field communication NFC device performs clock recovery according to the first carrier signal sent by the NFC card reader to obtain a field clock signal.
  • S1203 The digital phase-locked loop of the near field communication NFC device performs frequency tracking on the field clock signal, and outputs a first clock signal.
  • S1205 The digital baseband chip of the near field communication NFC device performs load modulation according to the first clock signal to generate a second carrier signal.
  • S1207 The controller of the near field communication NFC device detects the frequency or phase of the field clock signal, and selectively controls the digital phase locked loop according to the detection result.
  • the open-loop control method also includes:
  • a first open-loop control signal is generated; the first open-loop control signal is used to control the open-loop of the digital phase-locked loop.
  • the open-loop control method also includes:
  • the digital phase-locked loop is controlled to close the loop.
  • the controller detecting the frequency or phase of the field clock signal includes:
  • the controller receives the first clock signal output by the digital phase-locked loop, multiplies the frequency of the first clock signal to obtain a second clock signal, and uses the second clock signal to update the field clock signal Sampling is performed, and the frequency or phase of the vertical clock signal is detected according to the sampling result.
  • the controller multiplies the frequency of the first clock signal to obtain a second clock signal, uses the second clock signal to sample the field clock signal, and detects the
  • the frequency or phase of the field clock signal includes:
  • a controller comprising frequency multipliers, processors, and digital circuits is formed:
  • the frequency multiplier outputs a second clock signal after multiplying the frequency of the first clock signal
  • the processor determines the number of high-frequency clocks in the second clock signal, uses the field clock signal to determine a sampling result, and detects the frequency or phase of the field clock signal according to the sampling result, wherein the sampling result is in The number of high-frequency clocks in the clock cycle of the field clock signal; if there is a deviation in the number of high-frequency clocks in the clock cycle of the field clock signal, there is a deviation in the frequency or phase of the field clock signal, so The frequency or phase detection result is the first level;
  • the digital circuit generates the first open-loop control signal according to the frequency or phase detection result of the first level.
  • the processor determining the number of high-frequency clocks in the second clock signal, and using the field clock signal to determine the sampling result includes:
  • processor comprising a counter and a digital signal processor
  • the counter receives the second clock signal, and records the number of the high-frequency clocks in the second clock signal
  • the digital signal processor obtains the number of high-frequency clocks from the counter in the current clock cycle of the field clock signal, and obtains the number of high-frequency clocks according to the number of high-frequency clocks obtained in the current clock cycle and the high-frequency clock obtained in the previous clock cycle.
  • the number of clocks determines the number of high-frequency clocks in the current clock cycle.
  • the processor detecting the frequency or phase of the field clock signal according to the sampling result includes:
  • the digital signal processor compares the number of high-frequency clocks in the current clock cycle with a preset range to determine whether there is a deviation in the number of high-frequency clocks in the current clock cycle of the field clock signal, and determines accordingly Whether there is a deviation in the frequency or phase of the vertical clock signal; wherein, the preset range corresponds to the second clock signal one by one; if the number of high-frequency clocks in the current clock cycle is not within the preset Within the range, there is a deviation in the number of high-frequency clocks in the current clock period of the vertical clock signal, and there is a deviation in the frequency or phase of the vertical clock signal.
  • the open-loop control method further includes:
  • the controller receives the first carrier signal, detects the amplitude of the first carrier signal, and controls the digital phase-locked loop to close the loop if the amplitude of the first carrier signal is greater than a preset value.
  • the controller detects the amplitude of the first carrier signal, and if the amplitude of the first carrier signal is greater than a preset value, controlling the digital phase-locked loop to close the loop includes:
  • controller comprising an amplitude detection circuit, a delay circuit and a digital circuit
  • the amplitude detection circuit receives the first carrier signal, detects the amplitude of the first carrier signal, and generates an amplitude detection result according to the amplitude of the first carrier signal; wherein, if the amplitude of the first carrier signal is greater than preset value, the amplitude detection result is the second level;
  • the delay circuit outputs the amplitude detection result to the digital circuit after a preset time delay
  • the digital circuit controls the digital phase-locked loop to close the loop according to the amplitude detection result of the second level.
  • the open-loop control method further includes:
  • said digital phase locked loop comprising a time-to-digital converter, a digital filter, a numerically controlled oscillator and a frequency divider;
  • the time-to-digital converter and the digital filter receive the first open-loop control signal, and are used to stop working according to the first open-loop control signal, and maintain the state before receiving the first open-loop control signal The value continues to be output;
  • the oscillating signal before the numerical control oscillator maintains the open-loop state continues to oscillate and output the first clock signal
  • the frequency divider receives the first clock signal and divides the frequency of the first clock signal to reduce the frequency of the first clock signal to be equal to or close to the field clock recovered by the clock extractor the frequency of the signal.
  • the open-loop control method further includes:
  • the digital baseband chip of the near field communication NFC device generates a second open-loop control signal when outputting the second carrier signal to the NFC card reader;
  • the multiplexer MUX of the controller selectively performs open-loop control on the digital phase-locked loop according to at least one of the first open-loop control signal and the second open-loop control signal.
  • the method can also have other modifications, and for details, please refer to the description of the NFC device for near field communication, which will not be repeated here.

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Abstract

本申请公开了一种近场通信NFC装置及开环控制方法，可避免数字锁相环根据不连续的第一载波信号执行相位跟踪操作。一种近场通信NFC装置，所述近场通信NFC装置包括：时钟提取器，用于根据NFC读卡器发送的第一载波信号进行时钟恢复，得到场时钟信号；数字锁相环，用于对所述场时钟信号进行频率跟踪，输出第一时钟信号；数字基带芯片，用于根据所述第一时钟信号进行负载调制，生成第二载波信号；控制器，用于检测所述场时钟信号的频率或相位，并根据检测结果选择性控制所述数字锁相环进行开环。

Description

近场通信NFC装置及开环控制方法 技术领域
本申请涉及近场通信技术领域，尤其涉及一种近场通信NFC装置及开环控制方法。
背景技术
近场通信(Near Field Communication，NFC)技术是由非接触式射频识别(RFID)及互连互通技术整合演变而来。使用了NFC技术的设备可在彼此靠近的情况下进行数据交换。例如，NFC技术可使用在电子设备上，例如手机上，实现NFC关机刷卡场景，如图1所示。在NFC关机刷卡场景下，NFC读卡器11可发送载波信号至手机12，手机12可采用被动负载调制将数据调制到载波信号上，并将调制后的信号辐射到NFC读卡器11。为了减少天线面积，手机12也可采用有源负载调制将数据调制到载波信号上。目前可通过两种方式来为手机12提供载波信号，第一种方式为根据锁相环以本地时钟发生器产生的时钟信号为参考时钟信号后相应输出的信号，第二种方式为根据锁相环以从NFC读卡器11发送的载波信号中恢复的时钟信号为参考时钟信号后相应输出的信号。但是，第一种方式需要本地时钟发生器产生时钟信号，如此将会产生额外功耗，第二种方式会导致有源负载调制或者从NFC读卡器11接收的载波信号的调制深度较大时恢复的场时钟信号不理想，将会导致锁相环的输出不理想，会影响手机12与NFC读卡器11的通信。
发明内容
鉴于以上内容，有必要提供一种近场通信NFC装置及方法，可避免数字锁相环根据不连续的第一载波信号执行相位跟踪操作。
第一方面，本申请的一实施例提供一种近场通信NFC装置，所述近场通信NFC装置包括：时钟提取器，用于根据NFC读卡器发送的第一载波信号进行时钟恢复，得到场时钟信号；数字锁相环，用于对所述场时钟信号进行频率跟踪，输出第一时钟信号；数字基带芯片，用于根据所述第一时钟信号进行负载调制，生成第二载波信号；控制器，用于检测所述场时钟信号的频率或相位，并根据频率或相位检测结果选择性控制所述数字锁相环进行开环。
通过本申请的第一方面，通过控制器对场时钟信号的频率或相位进行检测，并根据频率或相位检测结果选择性控制所述数字锁相环进行开环，可根据第一载波信号的调制深度选择性控制数字锁相环进行开环。
根据本申请的一些实施例，所述控制器用于：若所述场时钟信号的频率或相位存在偏差，则生成第一开环控制信号；所述第一开环控制信号用于控制所述数字锁相环开环。
本申请通过若场时钟信号的频率或相位存在偏差，产生第一开环控制信号以控制数字锁相环进行开环，可在接收的第一载波信号的调制深度较大时控制数字锁相环进行开环，避免数字锁相环根据不连续的第一载波信号执行相位跟踪操作。
根据本申请的一些实施例，所述控制器用于：若所述场时钟信号的频率或相位不存在偏差，则控制所述数字锁相环进行闭环。
本申请通过若场时钟信号的频率或相位不存在偏差，则控制数字锁相环闭环，可在接收的第一载波信号连续时控制数字锁相环闭环，使得数字锁相环根据连续的第一载波信号执行相位跟踪操作。
根据本申请的一些实施例，所述控制器还用于：接收所述数字锁相环输出的所述第一时钟信号，将所述第一时钟信号进行频率倍增后得到第二时钟信号，利用所述第二时钟信号对所述场时钟信号进行采样，并根据采样结果检测所述场时钟信号的频率或相位。
本申请通过将数字锁相环输出的第一时钟信号的频率倍增后对场时钟信号进行采样，并根据采样结果对场时钟信号的频率或相位进行检测，可实现对场时钟信号的频率或相位的检测。
根据本申请的一些实施例，所述控制器包括倍频器、处理器、及数字电路：所述倍频器用于将所述第一时钟信号进行频率倍增后输出第二时钟信号；所述处理器用于确定所述第二时钟信号中高频时钟的个数，并利用场时钟信号来确定采样结果，并根据所述采样结果检测所述场时钟信号的频率或相位，其中采样结果为在所述场时钟信号的时钟周期内高频时钟的个数；若在所述场时钟信号的时钟周期内高频时钟的个数存在偏差，则所述场时钟信号的频率或相位存在偏差，所述频率或相位检测结果为第一电平；所述数字电路用于根据第一电平的频率或相位检测结果生成所述第一开环控制信号。
本申请通过处理器计算在场时钟信号的时钟周期内高频时钟的个数，并根据场时钟信号的时钟周期内高频时钟的个数确定场时钟信号的频率或相位是否存在偏差，及产生频率或相位检测结果至数字电路，数字电路用于根据第一电平的频率或相位检测结果生成第一开环控制信号至数字锁相环，可迅速精确的识别场时钟信号的频率或相位的偏差，并可迅速的产生第一开环控制信号至数字锁相环。
根据本申请的一些实施例，所述处理器包括计数器和数字信号处理器；所述计数器用于接收所述第二时钟信号，并记录所述第二时钟信号中所述高频时钟的个数；所述数字信号处理器用于在所述场时钟信号的当前时钟周期从所述计数器获取高频时钟的个数，并根据当前时钟周期获取的高频时钟的个数与前一时钟周期获取的高频时钟的个数确定当前时钟周期内高频时钟的个数。
本申请通过计数器记录高频时钟的个数，并通过数字信号处理器根据计数器记录的高频时钟的个数及场时钟信号计算在场时钟信号的当前时钟周期内高频时钟的个数，可实现迅速精确的计算在场时钟信号的时钟周期内高频时钟的个数。
根据本申请的一些实施例，所述数字信号处理器还用于：比较所述当前时钟周期内高频时钟的个数与预设的范围确定在所述场时钟信号的当前时钟周期内高频时钟的个数是否存在偏差，并相应的确定所述场时钟信号的频率或相位是否存在偏差；其中，所述预设的范围与所述第二时钟信号一一对应；若所述当前时钟周期内高频时钟的个数不在所述预设的范围内，则在所述场时钟信号的当前时钟周期内高频时钟的个数存在偏差，且所述场时钟信号的频率或相位存在偏差。
本申请通过当前时钟周期内高频时钟的个数与预设的范围来确定当前时钟周期内高频时钟的个数是否存在偏差，并产生相应的结果，可根据时钟信号的时钟周期内高频时钟的个数 确定时钟信号的频率或相位是否存在偏差。
根据本申请的一些实施例，所述控制器用于：接收所述第一载波信号，检测所述第一载波信号的幅度，并若所述第一载波信号的幅度大于预设值，则控制所述数字锁相环进行闭环。
本申请通过若所述第一载波信号的幅度大于预设值，则控制数字锁相环进行闭环，可在在接收的第一载波信号的调制深度正常时控制数字锁相环闭环，控制数字锁相环根据连续的第一载波信号执行相位跟踪操作。
根据本申请的一些实施例，所述控制器包括幅度检测电路、延迟电路及数字电路：所述幅度检测电路用于接收所述第一载波信号，检测所述第一载波信号的幅度，并根据所述第一载波信号的幅度产生幅度检测结果；其中，若所述第一载波信号的幅度大于预设值，则所述幅度检测结果为第二电平；所述延迟电路用于将所述幅度检测结果延迟预设时间后输出至所述数字电路；所述数字电路用于根据第二电平的幅度检测结果控制所述数字锁相环进行闭环。
本申请通过幅度检测电路检测第一载波信号的幅度，且延迟电路将幅度检测结果延迟预设时间后输出，数字电路根据延迟后的幅度检测结果控制数字锁相环进行闭环，可提供一个接收到的更加连续的第一载波信号的区间，可进一步避免数字锁相环根据不连续的第一载波信号执行相位跟踪操作。
根据本申请的一些实施例，所述数字锁相环包括时间数字转换器、数字滤波器、数控振荡器和分频器：所述时间数字转换器和所述数字滤波器用于接收所述第一开环控制信号，并用于根据所述第一开环控制信号停止工作，且保持接收到所述第一开环控制信号前的值继续输出；所述数控振荡器用于保持开环状态前的振荡信号继续振荡输出所述第一时钟信号；所述分频器用于接收所述第一时钟信号，并对所述第一时钟信进行分频，以将所述第一时钟信的频率降低至等于或接近于所述时钟提取器恢复的场时钟信号的频率。
本申请通过所述时间数字转换器和所述数字滤波器根据所述第一开环控制信号停止工作，且保持接收到所述第一开环控制信号前的值继续输出，所述数控振荡器用于保持开环状态前的振荡信号继续振荡，可控制数字锁相环开环。
根据本申请的一些实施例，在所述负载调制为有源负载调制的情况下，所述数字基带芯片，还用于在输出所述第二载波信号至所述NFC读卡器时生成第二开环控制信号；所述控制器还包括多路选择器MUX，所述多路选择器MUX用于根据所述第一开环控制信号和所述第二开环控制信号中的至少一个，选择性地对所述数字锁相环进行开环控制。
本申请通过在有源负载调制时，数字基带芯片生成第二开环控制信号以控制数字锁相环进行开环，可在有源负载调制时控制数字锁相环进行开环，避免数字锁相环根据不连续的第一载波信号执行相位跟踪操作；通过多路选择器MUX将有源负载调制和调制深度较大两种情况集成在一个电路中，可在不同情况下使用相同的电路，减小了电路的整体尺寸和成本。
第二方面，本申请的一实施例还提供一种开环控制方法，所述开环控制方法包括：近场通信NFC装置的时钟提取器根据NFC读卡器发送的第一载波信号进行时钟恢复，得到场时钟信号；所述近场通信NFC装置的数字锁相环对所述场时钟信号进行频率跟踪，输出第一时钟信号；所述近场通信NFC装置的数字基带芯片根据所述第一时钟信号进行负载调制，生成第二载波信号；所述近场通信NFC装置的控制器检测所述场时钟信号的频率或相位，并根据检测结果选择性控制所述数字锁相环。
根据本申请的一些实施例，所述开环控制方法还包括：若所述场时钟信号的频率或相位 存在偏差，则生成第一开环控制信号；所述第一开环控制信号用于控制所述数字锁相环开环。
根据本申请的一些实施例，所述控制器检测所述场时钟信号的频率或相位包括：所述控制器接收所述数字锁相环输出的所述第一时钟信号，将所述第一时钟信号进行频率倍增后得到第二时钟信号，利用所述第二时钟信号对所述场时钟信号进行采样，并根据采样结果检测所述场时钟信号的频率或相位。
根据本申请的一些实施例，所述控制器将所述第一时钟信号进行频率倍增后得到第二时钟信号，利用所述第二时钟信号对所述场时钟信号进行采样，并根据采样结果检测所述场时钟信号的频率或相位包括：形成包括倍频器、处理器、及数字电路的控制器：所述倍频器将所述第一时钟信号进行频率倍增后输出第二时钟信号；所述处理器确定所述第二时钟信号中高频时钟的个数，并利用场时钟信号来确定采样结果，并根据所述采样结果检测所述场时钟信号的频率或相位，其中采样结果为在所述场时钟信号的时钟周期内高频时钟的个数；若在所述场时钟信号的时钟周期内高频时钟的个数存在偏差，则所述场时钟信号的频率或相位存在偏差，所述频率或相位检测结果为第一电平；所述数字电路根据第一电平的频率或相位检测结果生成所述第一开环控制信号。
根据本申请的一些实施例，所述处理器确定所述第二时钟信号中高频时钟的个数，并利用场时钟信号来确定采样结果包括：形成包括计数器和数字信号处理器的所述处理器；所述计数器接收所述第二时钟信号，并记录所述第二时钟信号中所述高频时钟的个数；所述数字信号处理器在所述场时钟信号的当前时钟周期从所述计数器获取高频时钟的个数，并根据当前时钟周期获取的高频时钟的个数与前一时钟周期获取的高频时钟的个数确定当前时钟周期内高频时钟的个数。
根据本申请的一些实施例，所述处理器根据所述采样结果检测所述场时钟信号的频率或相位包括：所述数字信号处理器比较所述当前时钟周期内高频时钟的个数与预设的范围确定在所述场时钟信号的当前时钟周期内高频时钟的个数是否存在偏差，并相应的确定所述场时钟信号的频率或相位是否存在偏差；其中，所述预设的范围与所述第二时钟信号一一对应；若所述当前时钟周期内高频时钟的个数不在所述预设的范围内，则在所述场时钟信号的当前时钟周期内高频时钟的个数存在偏差，且所述场时钟信号的频率或相位存在偏差。
根据本申请的一些实施例，所述开环控制方法还包括：所述控制器接收所述第一载波信号，检测所述第一载波信号的幅度，并若所述第一载波信号的幅度大于预设值，则控制所述数字锁相环进行闭环。
根据本申请的一些实施例，所述控制器检测所述第一载波信号的幅度，并若所述第一载波信号的幅度大于预设值，则控制所述数字锁相环进行闭环包括：形成包括幅度检测电路、延迟电路及数字电路的所述控制器；所述幅度检测电路接收所述第一载波信号，检测所述第一载波信号的幅度，并根据所述第一载波信号的幅度产生幅度检测结果；其中，若所述第一载波信号的幅度大于预设值，则所述幅度检测结果为第二电平；所述延迟电路将所述幅度检测结果延迟预设时间后输出至所述数字电路；所述数字电路根据第二电平的幅度检测结果控制所述数字锁相环进行闭环。
根据本申请的一些实施例，所述开环控制方法还包括：在所述负载调制为有源负载调制的情况下，所述近场通信NFC装置的数字基带芯片在输出所述第二载波信号至所述NFC读卡器时生成第二开环控制信号；所述控制器的多路选择器MUX根据所述第一开环控制信号 和所述第二开环控制信号中的至少一个，选择性地对所述数字锁相环进行开环控制。
本申请中第二方面及其各种实现方式的具体描述，可以参考第一方面及其各种实现方式中的详细描述；并且，第二方面及其各种实现方式的有益效果，可以参考第一方面及其各种实现方式中的有益效果分析，此处不再赘述。
附图说明
图1为现有的NFC关机刷卡场景的示意图。
图2为现有的锁相环控制电路的方框图。
图3为现有的锁相环控制电路的暂停侦测器产生开环信号的示意图。
图4为本申请第一实施例的一种近场通信NFC装置和NFC读卡器的方框图。
图5为图4的近场通信NFC装置的控制器根据第一载波信号控制数字锁相环的示意图。
图6为图5的控制器的处理器的方框图。
图7为图4的近场通信NFC装置的数字锁相环的状态转换图。
图8为图4的近场通信NFC装置的工作时序图。
图9为本申请第二实施例的一种近场通信NFC装置和NFC读卡器的方框图。
图10为本申请第二实施例的一种近场通信NFC装置和NFC读卡器的方框图，其中粗线示出了近场通信NFC装置在接收的第一载波信号的调制深度较大时的工作过程。
图11为本申请第二实施例的一种近场通信NFC装置和NFC读卡器的方框图，其中粗线示出了近场通信NFC装置在有源负载调制时的工作过程。
图12为本申请实施例的一种开环控制方法的流程图。
具体实施方式
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请实施例的描述中，“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“例如”等词旨在以具体方式呈现相关概念。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请中的技术领域的技术人员通常理解的含义相同。本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。应理解，本申请中除非另有说明，“多个”是指两个或多于两个。
参阅图2和图3，图2为现有的锁相环控制电路的方框图，图3为现有的锁相环控制电路的暂停侦测器产生开环信号的示意图。锁相环控制电路2可以包括时钟缓存器21、参考时钟预分频器22、时钟提取器23、暂停侦测器24、复用器25及模拟锁相环26。时钟缓存器21用于缓存本地时钟发生器产生的时钟信号。时钟提取器23用于从接收的信号中恢复时钟信号。时钟缓存器21通过参考时钟预分频器22与复用器25连接。时钟提取器23与复用器25连接。复用器25的输出与模拟锁相环26连接。时钟提取器23的输出与暂停侦测器24连接。暂停侦测器24的输出与模拟锁相环26连接。暂停侦测器24根据时钟提取器23的输出检测幅度和时钟提取器恢复的时钟信号与模拟锁相环的输出之间的相位差，并根据幅度和相位差输出检测信号至模拟锁相环26，以控制模拟锁相环26开环。但是，现有的锁相环控制电路2 的模拟锁相环26的精度难以控制，开环容易影响环路的稳定性，且闭环建立时间较长。
请参阅图4，为本申请第一实施例的一种近场通信NFC装置和NFC读卡器的方框图。当近场通信NFC装置4和NFC读卡器5在短距离(几厘米)内时，NFC读卡器5向近场通信NFC装置4发送第一载波信号(频率为13.56MHZ的射频场)。为了响应所述第一载波信号，近场通信NFC装置4向NFC读卡器5传输负载调制后的第二载波信号。近场通信NFC装置4包括天线41、匹配电路42、时钟提取器43、控制器44、数字锁相环45、数字基带芯片46、及发射器47。天线41可以为支持射频传输和接收的天线。天线41用于接收NFC读卡器5发送的第一载波信号。匹配电路42与天线41连接，用于与天线41一起形成谐振电路。时钟提取器43与匹配电路42连接，用于根据NFC读卡器5发送的第一载波信号进行时钟恢复，得到场时钟信号。数字锁相环45与时钟提取器43连接，用于对所述场时钟信号进行频率跟踪，输出第一时钟信号。数字基带芯片46与数字锁相环45连接，用于根据所述第一时钟信号进行负载调制，生成第二载波信号。在数字基带芯片46与数字锁相环45之间可连接有分频器，分频器用于将所述第一时钟信号进行分频，数字基带芯片46用于在分频后的第一时钟信号上调制目标数据，生成第二载波信号，可理解的是，还可有其他方式来实现根据第一时钟信号生成第二载波信号，本申请对此不作限制。发射器47连接在数字基带芯片46和匹配电路42之间，用于将第二载波信号转换为射频信号，并通过天线41传输至NFC读卡器5。控制器44与数字锁相环45连接，用于检测所述场时钟信号的频率或相位，并根据检测结果选择性控制所述数字锁相环45进行开环。所述控制器44还用于若所述场时钟信号的频率或相位存在偏差，则生成第一开环控制信号；所述第一开环控制信号用于控制所述数字锁相环45开环。所述控制器44还用于若所述场时钟信号的频率或相位不存在偏差，则控制所述数字锁相环45进行闭环。所述控制器44还接收所述第一载波信号，检测所述第一载波信号的幅度，并若所述第一载波信号的幅度大于预设值，则控制所述数字锁相环45进行闭环。在本实施例中，基于所述场时钟信号的频率或相位可确定第一载波信号的调制深度。若所述场时钟信号的频率或相位存在偏差，则接收信号的调制深度较大；若所述场时钟信号的频率或相位不存在偏差，则接收信号的调制深度正常。
控制器44还可接收所述数字锁相环45输出的所述第一时钟信号，将所述第一时钟信号进行频率倍增后得到第二时钟信号，利用所述第二时钟信号对所述场时钟信号进行采样，并根据采样结果检测所述场时钟信号的频率或相位。
具体的，请同时参阅图5，图5为近场通信NFC装置的控制器根据第一载波信号控制数字锁相环的示意图。控制器44包括处理器441及数字电路442。处理器441连接在时钟提取器43和数字电路442之间，用于检测场时钟信号的频率或相位，并根据频率或相位检测结果产生电平信号至数字电路442，所述数字电路442根据所述电平信号选择性控制数字锁相环45进行开环。
所述控制器44还可包括倍频器443。倍频器443连接在数字锁相环45和处理器441之间。所述倍频器443用于将所述第一时钟信号进行频率倍增后输出第二时钟信号。在本实施例中，倍频器443将所述第一时钟信号的频率进行倍增，使得输出的第二时钟信号为13.56MHZ×128，即1.7GHZ。可理解的是，倍频器443还可将所述第一时钟信号的频率进行其他的倍频，只要倍频器443输出的第二时钟信号的频率大于场时钟信号的频率的2倍，本申请对此不作限制。所述处理器441用于确定所述第二时钟信号中高频时钟的个数，并利 用场时钟信号来确定采样结果，并根据所述采样结果检测所述场时钟信号的频率或相位，其中采样结果为在所述场时钟信号的时钟周期内高频时钟的个数。若在所述场时钟信号的时钟周期内高频时钟的个数存在偏差，则所述场时钟信号的频率或相位存在偏差，所述频率或相位检测结果为第一电平。若在所述场时钟信号的时钟周期内高频时钟的个数不存在偏差，则所述场时钟信号的频率或相位不存在偏差，所述频率或相位检测结果为第二电平。在本实施例中，所述第一电平为高电平，所述第二电平为低电平。可理解的是，所述第一电平也可为低电平，所述第二电平也可为高电平，本申请对此不作限制。所述数字电路442用于根据第一电平的频率或相位检测结果生成所述第一开环控制信号。所述数字电路442还用于根据第二电平的频率或相位检测结果控制所述数字锁相环45进行闭环。在本实施例中，第一开环控制信号为高电平。可理解的是，第一开环控制信号也可为低电平，本申请对此不作限制。
请同时参阅图6，图6为控制器的处理器的方框图。处理器441包括计数器4411和数字信号处理器4412。在本实施例中，计数器4411为8位计数器。可理解，计数器4411还可为其他计数器，本申请对此不作限制。计数器4411与倍频器443连接，用于接收所述第二时钟信号，并记录所述第二时钟信号中所述高频时钟的个数。数字信号处理器4412与计数器4411和时钟提取器43连接，用于在所述场时钟信号的当前时钟周期从所述计数器4411获取高频时钟的个数，并根据当前时钟周期获取的高频时钟的个数与前一时钟周期获取的高频时钟的个数确定当前时钟周期内高频时钟的个数。根据当前时钟周期获取的高频时钟的个数与前一时钟周期获取的高频时钟的个数确定当前时钟周期内高频时钟的个数可包括若当前时钟周期获取的高频时钟的个数大于前一时钟周期获取的高频时钟的个数，确定当前时钟周期内高频时钟的个数为当前时钟周期获取的高频时钟的个数与前一时钟周期获取的高频时钟的个数之差。若当前时钟周期获取的高频时钟的个数小于前一时钟周期获取的高频时钟的个数，确定当前时钟周期内高频时钟的个数为当前时钟周期获取的高频时钟的个数加上计数器4411的计数的最大个数(例如256)后的和，再与前一时钟周期获取的高频时钟的个数之差。所述数字信号处理器4412当前时钟周期获取的高频时钟的个数可为在所述场时钟信号的当前时钟周期结束时刻获取，所述数字信号处理器4412前一时钟周期获取的高频时钟的个数可为在所述场时钟信号的前一时钟周期结束时刻获取。
所述数字信号处理器4412还用于比较所述当前时钟周期内高频时钟的个数与预设的范围确定在所述场时钟信号的当前时钟周期内高频时钟的个数是否存在偏差，并相应的确定所述场时钟信号的频率或相位是否存在偏差。所述预设的范围与所述第二时钟信号一一对应。在本实施例中，第二时钟信号为13.56MHZ×128，则预设的范围可为127～129。可理解，预设的范围还可为其他范围或值，例如为128，预设的范围还可根据第二时钟信号的不同而为不同的范围，本申请对此不作限制。预设的范围可为系统默认设置的范围或值或者用户根据第二时钟信号设置的范围或值。若所述当前时钟周期内高频时钟的个数不在所述预设的范围内，则在所述场时钟信号的当前时钟周期内高频时钟的个数存在偏差，且所述场时钟信号的频率或相位存在偏差。若所述当前时钟周期内高频时钟的个数在所述预设的范围内，则在所述场时钟信号的当前时钟周期内高频时钟的个数不存在偏差，且所述场时钟信号的频率或相位不存在偏差。数字信号处理器4412与所述数字电路442连接，还用于输出频率或相位检测结果至数字电路442，数字电路442则可相应选择性控制所述数字锁相环45进行开环。
请继续参考图4及图5，数字锁相环45包括时间数字转换器451、数字滤波器452、数 控振荡器453和分频器454。时间数字转换器451、数字滤波器452、数控振荡器453和分频器454按顺序连接。时间数字转换器451与时钟提取器43连接。时间数字转换器451用于接收时钟提取器43恢复的场时钟信号，并将场时钟信号的相位与分频器454输出的信号的相位进行比较以输出数字信号。数字滤波器452用于接收时间数字转换器451输出的数字信号，对数字信号进行滤波操作，并产生与数字信号相关的控制信号。数控振荡器453用于接收控制信号，根据控制信号输出第一时钟信号。分频器454用于接收第一时钟信号，并对第一时钟信号进行分频(例如N分频)，以将第一时钟信号的频率降低至等于或接近于时钟提取器43恢复的场时钟信号的频率。其中N可为任意合适的值。在本实施例中，倍频器443可与数控振荡器453连接。可理解，倍频器443还可与分频器454连接，只要倍频器443可输出预设的第二时钟信号，例如上述第一时钟信号的频率13.56MHZ的5倍频，可理解，倍频器443还可位于数字锁相环45内，并与分频器454或者数控振荡器453连接，只需要倍频器443可输出所述预设的高频时钟，本申请对此不作限制。
在本实施例中，数字电路442与时间数字转换器451和数字滤波器452连接。数字电路442用于生成第一开环控制信号至时间数字转换器451和数字滤波器452。所述时间数字转换器451和所述数字滤波器452用于接收所述第一开环控制信号，并用于根据所述第一开环控制信号停止工作，且保持接收到所述第一开环控制信号前的值继续输出。此时数字锁相环45转为开环状态，数控振荡器453保持开环状态前的振荡信号继续振荡输出第一时钟信号。数字电路442还可控制时间数字转换器451和数字滤波器452继续工作，数字锁相环45继续执行相位跟踪操作。
请同时参考图7，图7为近场通信NFC装置的数字锁相环的状态转换图。数字锁相环45包括工艺电压温度校准(PVT)状态、接近锁定(ACQ)状态、相位跟踪(TRK)状态及保持(HOLD)状态共四个状态。其中，相位跟踪(TRK)状态代表闭环状态，保持(HOLD)状态代表开环状态。工艺电压温度校准(PVT)状态、接近锁定(ACQ)状态和相位跟踪(TRK)状态顺序执行。在工艺电压温度校准(PVT)状态，一箭头指向工艺电压温度校准(PVT)状态，表示在接收到复位信号或者近场通信NFC装置4开启时，执行工艺电压温度校准(PVT)。一箭头从相位跟踪(TRK)状态指向相位跟踪(TRK)状态，表示保持在相位跟踪(TRK)状态。一箭头从相位跟踪(TRK)状态指向保持(HOLD)状态代表若在相位跟踪(TRK)状态接收到第一开环控制信号从相位跟踪(TRK)状态跳转至保持(HOLD)状态。一箭头从保持(HOLD)状态指向保持(HOLD)状态，表示保持在保持(HOLD)状态。一箭头从保持(HOLD)状态指向相位跟踪(TRK)状态代表若在保持(HOLD)状态时数字锁相环45闭环，则从保持(HOLD)状态跳转至相位跟踪(TRK)状态。
请继续参考图4、图5和图6，控制器44还可包括幅度检测电路444。幅度检测电路444还与匹配电路42和数字电路442连接，用于接收第一载波信号，检测第一载波信号的幅度，并根据第一载波信号的幅度产生幅度检测结果至数字电路442。其中，若所述第一载波信号的幅度小于或等于预设值，则所述幅度检测结果为第一电平。其中，若幅度检测结果为第一电平，数字锁相环45处于开环状态。若所述第一载波信号的幅度大于预设值，则所述幅度检测结果为第二电平。
所述控制器44还可包括延迟电路445。幅度检测电路444还可通过延迟电路445与数字电路442连接。可选的，延迟电路445还可设置在幅度检测电路444内。延迟电路445用于 将幅度检测结果延迟预设时间后输出至数字电路442。数字电路442还用于根据第二电平的幅度检测结果控制所述数字锁相环45进行闭环。
请同时参阅图8，图8为近场通信NFC装置的工作时序图。图8示出了天线41接收到NFC读卡器5的第一载波信号由于调制深度较大导致信号不连续时，数字锁相环45在相位跟踪(TRK)状态和保持(HOLD)状态之间相互转换的工作状态。在图8中，天线41开始接收到NFC读卡器5的连续的第一载波信号。此时时钟提取器43恢复的场时钟信号是稳定的，处理器441的数字信号处理器4412确定恢复的场时钟信号的频率或相位不存在偏差，输出第二电平(低电平)的频率或相位检测结果。幅度检测电路444也确定天线41接收的NFC读卡器5的第一载波信号的幅度大于预设值，则幅度检测电路444将第二电平(低电平)的幅度检测结果延迟预设时间后输出。数字电路442根据第二电平的频率或相位检测结果和第二电平的幅度检测结果控制数字锁相环45保持在相位跟踪(TRK)状态或者进入相位跟踪(TRK)状态。
若天线41接收到NFC读卡器5的第一载波信号从连续的信号变为不连续的信号，此时时钟提取器43恢复的场时钟信号是不稳定的，处理器441的数字信号处理器4412确定恢复的场时钟信号的频率或相位存在偏差，并输出第一电平(高电平)的频率或相位检测结果。数字电路442根据第一电平的频率或相位检测结果输出第一电平(高电平)的第一开环控制信号。数字锁相环45根据第一开环控制信号开环。数字锁相环45从相位跟踪(TRK)状态跳转至保持(HOLD)状态。此时幅度检测电路444也确定天线41接收的NFC读卡器5的第一载波信号的幅度小于预设值，则幅度检测电路444将第一电平(高电平)的幅度检测结果延迟预设时间后输出。
若天线41接收到NFC读卡器5的第一载波信号从不连续的信号变为连续的信号，此时时钟提取器43恢复的场时钟信号是稳定的，幅度检测电路444确定天线41接收的NFC读卡器5的第一载波信号的幅度大于预设值，则幅度检测电路444将第二电平(低电平)的幅度检测结果延迟预设时间后输出。数字电路442根据第二电平的幅度检测结果控制数字锁相环45从保持(HOLD)状态进入相位跟踪(TRK)状态。在场时钟信号切换至稳定时，处理器441的数字信号处理器4412也确定恢复的场时钟信号的频率或相位不存在偏差，并输出第二电平(低电平)的频率或相位检测结果。
因此，本申请可在接收到第一电平(高电平)频率或相位检测结果时就产生第一开环控制信号，控制数字锁相环45从相位跟踪(TRK)状态跳转至保持(HOLD)状态；在接收到第二电平(低电平)幅度检测结果时控制数字锁相环45从保持(HOLD)状态跳转至相位跟踪(TRK)状态。
可理解的是，近场通信NFC装置4根据频率或相位检测结果和幅度检测结果控制数字锁相环45的状态还可有其他变形，例如数字信号处理器4412通过延迟电路445与数字电路442连接，或者数字信号处理器4412内设置有延迟电路445，幅度检测电路444不通过延迟电路445与数字电路442连接，则在接收到第一电平(高电平)的幅度检测结果时产生第一开环控制信号，控制数字锁相环45从相位跟踪(TRK)状态跳转至保持(HOLD)状态；在接收到第二电平(低电平)的频率或相位检测结果时控制数字锁相环45从保持(HOLD)状态跳转至相位跟踪(TRK)状态，本申请对此不作限制。
本实施例通过控制器44对场时钟信号的频率或相位进行检测，并根据频率或相位检测结 果选择性控制所述数字锁相环45进行开环，可根据第一载波信号的调制深度选择性控制数字锁相环45进行开环；通过若场时钟信号的频率或相位存在偏差，产生第一开环控制信号以控制数字锁相环45进行开环，可在接收的第一载波信号的调制深度较大时控制数字锁相环45进行开环，避免数字锁相环45根据不连续的第一载波信号执行相位跟踪操作；通过若场时钟信号的频率或相位不存在偏差，则控制数字锁相环45闭环，可在接收的第一载波信号连续时控制数字锁相环45闭环，使得数字锁相环45根据连续的第一载波信号执行相位跟踪操作；通过将数字锁相环45输出的第一时钟信号的频率倍增后对场时钟信号进行采样，并根据采样结果对场时钟信号的频率或相位进行检测，可实现对场时钟信号的频率或相位的检测；通过控制器44包括处理器441、数字电路442和倍频器443，处理器441用于计算在场时钟信号的时钟周期内高频时钟的个数，并根据场时钟信号的时钟周期内高频时钟的个数确定场时钟信号的频率或相位是否存在偏差，及产生频率或相位检测结果至数字电路442，数字电路442用于根据第一电平的频率或相位检测结果生成第一开环控制信号至数字锁相环45，可迅速精确的识别场时钟信号的频率或相位的偏差，并可迅速的产生第一开环控制信号至数字锁相环45；通过处理器441包括计数器4411和数字信号处理器4412，可通过计数器4411记录高频时钟的个数，并通过数字信号处理器4412根据计数器4411记录的高频时钟的个数及场时钟信号计算在场时钟信号的当前时钟周期内高频时钟的个数，可实现迅速精确的计算在场时钟信号的时钟周期内高频时钟的个数；通过产生第一开环控制信号至时间数字转换器451和数字滤波器452，可实现数字锁相环45开环，且无需增加额外的元件，节省了成本。通过若所述第一载波信号的幅度大于预设值，则控制数字锁相环45进行闭环，可在接收的第一载波信号的调制深度正常时控制数字锁相环45闭环，控制数字锁相环45根据连续的第一载波信号执行相位跟踪操作；通过幅度检测电路444检测第一载波信号的幅度，且延迟电路445将幅度检测结果延迟预设时间后输出，数字电路442根据延迟后的幅度检测结果控制数字锁相环45进行闭环，可提供一个接收到的更加连续的第一载波信号的区间，可进一步避免数字锁相环45根据不连续的第一载波信号执行相位跟踪操作。
请参考图9，为本申请第二实施例的一种近场通信NFC装置和NFC读卡器的方框图。第二实施例的近场通信NFC装置9与第一实施例的近场通信NFC装置相似，第二实施例的近场通信NFC装置9与NFC读卡器10通信，近场通信NFC装置9包括天线91、匹配电路92、时钟提取器93、控制器94、数字锁相环95、数字基带芯片96、及发射器97。第二实施例的天线91、匹配电路92、时钟提取器93、数字锁相环95、数字基带芯片96、及发射器97之间的连接关系和作用与第一实施例的天线、匹配电路、时钟提取器、数字锁相环、数字基带芯片、及发射器的连接关系和作用相同，第二实施的控制器94也包括处理器941、数字电路942、倍频器943、幅度检测电路944和延迟电路945，不同之处在于：
在所述负载调制为有源负载调制的情况下，近场通信NFC装置9的数字基带芯片96在输出所述第二载波信号至所述NFC读卡器10时生成第二开环控制信号。控制器94还包括多路选择器MUX946。多路选择器MUX946用于根据所述第一开环控制信号和所述第二开环控制信号中的至少一个，选择性地对所述数字锁相环95进行开环控制。多路选择器MUX946包括输入端、控制端和输出端。多路选择器MUX946的输入端与数字基带芯片96和控制器94的数字电路942连接，用于接收第一开环控制信号和第二开环控制信号。多路选择器MUX946的控制端与数字基带芯片96连接，用于接收数字基带芯片96的控制信号。多路选择器 MUX946的输出端与数字锁相环95连接。多路选择器MUX946根据数字基带芯片96的控制信号确定连通数字基带芯片96或者数字电路942。其中，在所述负载调制为有源负载调制的情况下，数字基带芯片96输出第一控制信号至多路选择器MUX946，控制多路选择器MUX946连通数字基带芯片96，数字基带芯片96可通过多路选择器MUX946输出第二开环控制信号控制数字锁相环95进行开环。数字基带芯片96还在所述负载调制为被动负载调制的情况下，输出第二控制信号至多路选择器MUX946，控制多路选择器MUX946连通数字电路942，数字电路942可通过多路选择器MUX946输出第一开环控制信号控制数字锁相环95进行开环。
请同时参考图10，图10中的粗线示出了近场通信NFC装置在接收的第一载波信号的调制深度较大时的工作过程。其中，近场通信NFC装置9在接收的第一载波信号的调制深度较大时的工作过程和第一实施例的近场通信NFC装置的工作过程相似，不同之处在于，数字电路942通过多路选择器MUX946与数字锁相环95连接。数字电路942通过多路选择器MUX946输出第一开环控制信号控制数字锁相环95进行开环；并通过多路选择器MUX946控制数字锁相环95进行闭环。
请同时参考图11，图11中的粗线示出了近场通信NFC装置在有源负载调制时的工作过程。在图11中，天线91可以为支持射频传输和接收的天线。天线91用于接收NFC读卡器10发送的第一载波信号。匹配电路92与天线91连接，用于与天线91一起形成谐振电路。时钟提取器93与匹配电路92连接，用于根据NFC读卡器10发送的第一载波信号进行时钟恢复，得到场时钟信号。数字锁相环95与时钟提取器93连接，用于对所述场时钟信号进行频率跟踪，输出第一时钟信号。数字基带芯片96与数字锁相环95连接，用于根据所述第一时钟信号进行负载调制，生成第二载波信号。在数字基带芯片96与数字锁相环95之间可连接有分频器，分频器用于将所述第一时钟信号进行分频，数字基带芯片96用于在分频后的第一时钟信号上调制目标数据，生成第二载波信号，可理解的是，还可有其他方式来实现根据第一时钟信号生成第二载波信号，本申请对此不作限制。发射器97连接在数字基带芯片96和匹配电路92之间，用于将第二载波信号转换为射频信号，并通过天线91传输至NFC读卡器10。数字基带芯片96可通过多路选择器MUX946与数字锁相环95连接，用于通过多路选择器MUX946输出第二开环控制信号至数字锁相环95，控制数字锁相环95进行开环。其中，数字基带芯片96输出第二开环控制信号的周期与数字基带芯片96输出第二载波信号的时间有关。数字基带芯片96根据第二载波信号的周期产生第二开环控制信号的周期，则数字基带芯片96可设置数字锁相环95若干个周期为开环。
本实施例通过在有源负载调制时，数字基带芯片96生成第二开环控制信号以控制数字锁相环95进行开环，可在有源负载调制时控制数字锁相环95进行开环，避免数字锁相环95根据不连续的第一载波信号执行相位跟踪操作；通过多路选择器MUX946将有源负载调制和调制深度较大两种情况集成在一个电路中，可在不同情况下使用相同的电路，减小了电路的整体尺寸和成本。
请参阅图12，为本申请实施例的一种开环控制方法的流程图。开环控制方法应用于近场通信NFC装置上。开环控制方法包括：
S1201：近场通信NFC装置的时钟提取器根据NFC读卡器发送的第一载波信号进行时钟恢复，得到场时钟信号。
S1203：所述近场通信NFC装置的数字锁相环对所述场时钟信号进行频率跟踪，输出第一时钟信号。
S1205：所述近场通信NFC装置的数字基带芯片根据所述第一时钟信号进行负载调制，生成第二载波信号。
S1207：所述近场通信NFC装置的控制器检测所述场时钟信号的频率或相位，并根据检测结果选择性控制所述数字锁相环。
在本实施例中，开环控制方法还包括：
若所述场时钟信号的频率或相位存在偏差，则生成第一开环控制信号；所述第一开环控制信号用于控制所述数字锁相环开环。
在本实施例中，开环控制方法还包括：
若所述场时钟信号的频率或相位不存在偏差，则控制所述数字锁相环进行闭环。
在本实施例中，所述控制器检测所述场时钟信号的频率或相位包括：
所述控制器接收所述数字锁相环输出的所述第一时钟信号，将所述第一时钟信号进行频率倍增后得到第二时钟信号，利用所述第二时钟信号对所述场时钟信号进行采样，并根据采样结果检测所述场时钟信号的频率或相位。
在本实施例中，所述控制器将所述第一时钟信号进行频率倍增后得到第二时钟信号，利用所述第二时钟信号对所述场时钟信号进行采样，并根据采样结果检测所述场时钟信号的频率或相位包括：
形成包括倍频器、处理器、及数字电路的控制器：
所述倍频器将所述第一时钟信号进行频率倍增后输出第二时钟信号；
所述处理器确定所述第二时钟信号中高频时钟的个数，并利用场时钟信号来确定采样结果，并根据所述采样结果检测所述场时钟信号的频率或相位，其中采样结果为在所述场时钟信号的时钟周期内高频时钟的个数；若在所述场时钟信号的时钟周期内高频时钟的个数存在偏差，则所述场时钟信号的频率或相位存在偏差，所述频率或相位检测结果为第一电平；
所述数字电路根据第一电平的频率或相位检测结果生成所述第一开环控制信号。
在本实施例中，所述处理器确定所述第二时钟信号中高频时钟的个数，并利用场时钟信号来确定采样结果包括：
形成包括计数器和数字信号处理器的所述处理器；
所述计数器接收所述第二时钟信号，并记录所述第二时钟信号中所述高频时钟的个数；
所述数字信号处理器在所述场时钟信号的当前时钟周期从所述计数器获取高频时钟的个数，并根据当前时钟周期获取的高频时钟的个数与前一时钟周期获取的高频时钟的个数确定当前时钟周期内高频时钟的个数。
在本实施例中，所述处理器根据所述采样结果检测所述场时钟信号的频率或相位包括：
所述数字信号处理器比较所述当前时钟周期内高频时钟的个数与预设的范围确定在所述场时钟信号的当前时钟周期内高频时钟的个数是否存在偏差，并相应的确定所述场时钟信号的频率或相位是否存在偏差；其中，所述预设的范围与所述第二时钟信号一一对应；若所述当前时钟周期内高频时钟的个数不在所述预设的范围内，则在所述场时钟信号的当前时钟周期内高频时钟的个数存在偏差，且所述场时钟信号的频率或相位存在偏差。
在本实施例中，所述开环控制方法还包括：
所述控制器接收所述第一载波信号，检测所述第一载波信号的幅度，并若所述第一载波信号的幅度大于预设值，则控制所述数字锁相环进行闭环。
在本实施例中，所述控制器检测所述第一载波信号的幅度，并若所述第一载波信号的幅度大于预设值，则控制所述数字锁相环进行闭环包括：
形成包括幅度检测电路、延迟电路及数字电路的所述控制器；
所述幅度检测电路接收所述第一载波信号，检测所述第一载波信号的幅度，并根据所述第一载波信号的幅度产生幅度检测结果；其中，若所述第一载波信号的幅度大于预设值，则所述幅度检测结果为第二电平；
所述延迟电路将所述幅度检测结果延迟预设时间后输出至所述数字电路；
所述数字电路根据第二电平的幅度检测结果控制所述数字锁相环进行闭环。
在本实施例中，所述开环控制方法还包括：
形成包括时间数字转换器、数字滤波器、数控振荡器和分频器的所述数字锁相环；
所述时间数字转换器和所述数字滤波器接收所述第一开环控制信号，并用于根据所述第一开环控制信号停止工作，且保持接收到所述第一开环控制信号前的值继续输出；
所述数控振荡器保持开环状态前的振荡信号继续振荡输出所述第一时钟信号；
所述分频器接收所述第一时钟信号，并对所述第一时钟信进行分频，以将所述第一时钟信的频率降低至等于或接近于所述时钟提取器恢复的场时钟信号的频率。
在本实施例中，所述开环控制方法还包括：
在所述负载调制为有源负载调制的情况下，所述近场通信NFC装置的数字基带芯片在输出所述第二载波信号至所述NFC读卡器时生成第二开环控制信号；
所述控制器的多路选择器MUX根据所述第一开环控制信号和所述第二开环控制信号中的至少一个，选择性地对所述数字锁相环进行开环控制。
显然，所述方法还可有其他变形，具体请参考对所述近场通信NFC装置的描述，在此不进行赘述。
最后应说明的是，以上实施例仅用以说明本申请的技术方案而非限制，尽管参照较佳实施例对本申请进行了详细说明，本领域的普通技术人员应当理解，可以对本申请的技术方案进行修改或等同替换，而不脱离本申请技术方案的精神和范围。

Claims (20)

  1. 一种近场通信NFC装置，其特征在于，所述近场通信NFC装置包括：
    时钟提取器，用于根据NFC读卡器发送的第一载波信号进行时钟恢复，得到场时钟信号；
    数字锁相环，用于对所述场时钟信号进行频率跟踪，输出第一时钟信号；
    数字基带芯片，用于根据所述第一时钟信号进行负载调制，生成第二载波信号；
    控制器，用于检测所述场时钟信号的频率或相位，并根据频率或相位检测结果选择性控制所述数字锁相环进行开环。
  2. 如权利要求1所述的近场通信NFC装置，其特征在于，所述控制器用于：
    若所述场时钟信号的频率或相位存在偏差，则生成第一开环控制信号；所述第一开环控制信号用于控制所述数字锁相环开环。
  3. 如权利要求2所述的近场通信NFC装置，其特征在于，所述控制器用于：
    若所述场时钟信号的频率或相位不存在偏差，则控制所述数字锁相环进行闭环。
  4. 如权利要求2所述的近场通信NFC装置，其特征在于，所述控制器还用于：接收所述数字锁相环输出的所述第一时钟信号，将所述第一时钟信号进行频率倍增后得到第二时钟信号，利用所述第二时钟信号对所述场时钟信号进行采样，并根据采样结果检测所述场时钟信号的频率或相位。
  5. 如权利要求4所述的近场通信NFC装置，其特征在于，所述控制器包括倍频器、处理器、及数字电路：
    所述倍频器用于将所述第一时钟信号进行频率倍增后输出第二时钟信号；
    所述处理器用于确定所述第二时钟信号中高频时钟的个数，并利用场时钟信号来确定采样结果，并根据所述采样结果检测所述场时钟信号的频率或相位，其中采样结果为在所述场时钟信号的时钟周期内高频时钟的个数；若在所述场时钟信号的时钟周期内高频时钟的个数存在偏差，则所述场时钟信号的频率或相位存在偏差，频率或相位检测结果为第一电平；
    所述数字电路用于根据第一电平的频率或相位检测结果生成所述第一开环控制信号。
  6. 如权利要求5所述的近场通信NFC装置，其特征在于，所述处理器包括计数器和数字信号处理器；
    所述计数器用于接收所述第二时钟信号，并记录所述第二时钟信号中所述高频时钟的个数；
    所述数字信号处理器用于在所述场时钟信号的当前时钟周期从所述计数器获取高频时钟的个数，并根据当前时钟周期获取的高频时钟的个数与前一时钟周期获取的高频时钟的个数确定当前时钟周期内高频时钟的个数。
  7. 如权利要求6所述的近场通信NFC装置，其特征在于，所述数字信号处理器还用于：
    比较所述当前时钟周期内高频时钟的个数与预设的范围确定在所述场时钟信号的当前时钟周期内高频时钟的个数是否存在偏差，并相应的确定所述场时钟信号的频率或相位是否存在偏差；其中，所述预设的范围与所述第二时钟信号一一对应；若所述当前时钟周期内高频时钟的个数不在所述预设的范围内，则在所述场时钟信号的当前时钟周期内高频时钟的个数存在偏差，且所述场时钟信号的频率或相位存在偏差。
  8. 如权利要求2所述的近场通信NFC装置，其特征在于，所述控制器用于：
    接收所述第一载波信号，检测所述第一载波信号的幅度，并若所述第一载波信号的幅度大于预设值，则控制所述数字锁相环进行闭环。
  9. 如权利要求8所述的近场通信NFC装置，其特征在于，所述控制器包括幅度检测电路、延迟电路及数字电路：
    所述幅度检测电路用于接收所述第一载波信号，检测所述第一载波信号的幅度，并根据所述第一载波信号的幅度产生幅度检测结果；其中，若所述第一载波信号的幅度大于预设值，则所述幅度检测结果为第二电平；
    所述延迟电路用于将所述幅度检测结果延迟预设时间后输出至所述数字电路；
    所述数字电路用于根据第二电平的幅度检测结果控制所述数字锁相环进行闭环。
  10. 如权利要求2所述的近场通信NFC装置，其特征在于，所述数字锁相环包括时间数字转换器、数字滤波器、数控振荡器和分频器：
    所述时间数字转换器和所述数字滤波器用于接收所述第一开环控制信号，并用于根据所述第一开环控制信号停止工作，且保持接收到所述第一开环控制信号前的值继续输出；
    所述数控振荡器用于保持开环状态前的振荡信号继续振荡输出所述第一时钟信号；
    所述分频器用于接收所述第一时钟信号，并对所述第一时钟信进行分频，以将所述第一时钟信的频率降低至等于或接近于所述时钟提取器恢复的场时钟信号的频率。
  11. 如权利要求2所述的近场通信NFC装置，其特征在于：
    在所述负载调制为有源负载调制的情况下，所述数字基带芯片，还用于在输出所述第二载波信号至所述NFC读卡器时生成第二开环控制信号；
    所述控制器还包括多路选择器MUX，所述多路选择器MUX用于根据所述第一开环控制信号和所述第二开环控制信号中的至少一个，选择性地对所述数字锁相环进行开环控制。
  12. 一种开环控制方法，其特征在于，所述开环控制方法包括：
    近场通信NFC装置的时钟提取器根据NFC读卡器发送的第一载波信号进行时钟恢复，得到场时钟信号；
    所述近场通信NFC装置的数字锁相环对所述场时钟信号进行频率跟踪，输出第一时钟信号；
    所述近场通信NFC装置的数字基带芯片根据所述第一时钟信号进行负载调制，生成第二载波信号；
    所述近场通信NFC装置的控制器检测所述场时钟信号的频率或相位，并根据检测结果选择性控制所述数字锁相环。
  13. 如权利要求12所述的开环控制方法，其特征在于，所述开环控制方法还包括：
    若所述场时钟信号的频率或相位存在偏差，则生成第一开环控制信号；所述第一开环控制信号用于控制所述数字锁相环开环。
  14. 如权利要求13所述的开环控制方法，其特征在于，所述控制器检测所述场时钟信号的频率或相位包括：
    所述控制器接收所述数字锁相环输出的所述第一时钟信号，将所述第一时钟信号进行频率倍增后得到第二时钟信号，利用所述第二时钟信号对所述场时钟信号进行采样，并根据采样结果检测所述场时钟信号的频率或相位。
  15. 如权利要求14所述的开环控制方法，其特征在于，所述控制器将所述第一时钟信号 进行频率倍增后得到第二时钟信号，利用所述第二时钟信号对所述场时钟信号进行采样，并根据采样结果检测所述场时钟信号的频率或相位包括：
    形成包括倍频器、处理器、及数字电路的控制器：
    所述倍频器将所述第一时钟信号进行频率倍增后输出第二时钟信号；
    所述处理器确定所述第二时钟信号中高频时钟的个数，并利用场时钟信号来确定采样结果，并根据所述采样结果检测所述场时钟信号的频率或相位，其中采样结果为在所述场时钟信号的时钟周期内高频时钟的个数；若在所述场时钟信号的时钟周期内高频时钟的个数存在偏差，则所述场时钟信号的频率或相位存在偏差，频率或相位检测结果为第一电平；
    所述数字电路根据第一电平的频率或相位检测结果生成所述第一开环控制信号。
  16. 如权利要求15所述的开环控制方法，其特征在于，所述处理器确定所述第二时钟信号中高频时钟的个数，并利用场时钟信号来确定采样结果包括：
    形成包括计数器和数字信号处理器的所述处理器；
    所述计数器接收所述第二时钟信号，并记录所述第二时钟信号中所述高频时钟的个数；
    所述数字信号处理器在所述场时钟信号的当前时钟周期从所述计数器获取高频时钟的个数，并根据当前时钟周期获取的高频时钟的个数与前一时钟周期获取的高频时钟的个数确定当前时钟周期内高频时钟的个数。
  17. 如权利要求16所述的开环控制方法，其特征在于，所述处理器根据所述采样结果检测所述场时钟信号的频率或相位包括：
    所述数字信号处理器比较所述当前时钟周期内高频时钟的个数与预设的范围确定在所述场时钟信号的当前时钟周期内高频时钟的个数是否存在偏差，并相应的确定所述场时钟信号的频率或相位是否存在偏差；其中，所述预设的范围与所述第二时钟信号一一对应；若所述当前时钟周期内高频时钟的个数不在所述预设的范围内，则在所述场时钟信号的当前时钟周期内高频时钟的个数存在偏差，且所述场时钟信号的频率或相位存在偏差。
  18. 如权利要求13所述的开环控制方法，其特征在于，所述开环控制方法还包括：
    所述控制器接收所述第一载波信号，检测所述第一载波信号的幅度，并若所述第一载波信号的幅度大于预设值，则控制所述数字锁相环进行闭环。
  19. 如权利要求18所述的开环控制方法，其特征在于，所述控制器检测所述第一载波信号的幅度，并若所述第一载波信号的幅度大于预设值，则控制所述数字锁相环进行闭环包括：
    形成包括幅度检测电路、延迟电路及数字电路的所述控制器；
    所述幅度检测电路接收所述第一载波信号，检测所述第一载波信号的幅度，并根据所述第一载波信号的幅度产生幅度检测结果；其中，若所述第一载波信号的幅度大于预设值，则所述幅度检测结果为第二电平；
    所述延迟电路将所述幅度检测结果延迟预设时间后输出至所述数字电路；
    所述数字电路根据第二电平的幅度检测结果控制所述数字锁相环进行闭环。
  20. 如权利要求13所述的开环控制方法，其特征在于，所述开环控制方法还包括：
    在所述负载调制为有源负载调制的情况下，所述近场通信NFC装置的数字基带芯片在输出所述第二载波信号至所述NFC读卡器时生成第二开环控制信号；
    所述控制器的多路选择器MUX根据所述第一开环控制信号和所述第二开环控制信号中的至少一个，选择性地对所述数字锁相环进行开环控制。
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