WO2022269886A1

WO2022269886A1 - Output signal generation device, phased array antenna, and output signal calibration method for phased array antenna

Info

Publication number: WO2022269886A1
Application number: PCT/JP2021/024067
Authority: WO
Inventors: 健吾川▲崎▼; 英之中溝; 平和田; 道也早馬
Original assignee: 三菱電機株式会社
Priority date: 2021-06-25
Filing date: 2021-06-25
Publication date: 2022-12-29

Abstract

An output signal generation device (2) is provided with: a transmission signal generation unit (21) for generating modulated wave signals; bit delay units (22-1 to 22-2n, 22-1 to 22-n) for setting the amount of delay or a phase of the modulated wave signal; variable gain amplification units (23-1 to 23-2n, 23-1 to 23-n) for setting the amplitude of the modulated wave signal to which the amount of delay or the phase has been set; and phase-amplitude comparison units (8-1 to 8-(n-1)) for outputting an error signal indicating a phase difference and an amplitude difference between the modulated wave signal that has been output from one of mutually different output terminals, among output terminals (5-1 to 5-2n, 5-1 to 5-n), and the modulated wave signal that has been output from the other one of the output terminals. The bit delay units (22-1 to 22-2n, 22-1 to 22-n) and the variable gain amplification units (23-1 to 23-2n, 23-1 to 23-n) use a correction value calculated on the basis of the error signal, and calibrate the modulated wave signal, which has been output from one of mutually different output terminals, by applying the modulated wave signal output from the other one of the output terminals as a reference signal.

Description

Output signal generator, phased array antenna, and output signal calibration method for phased array antenna

The present disclosure relates to an output signal generation device, a phased array antenna, and a phased array antenna output signal calibration method.

In recent years, a technique called direct digital RF (Radio Frequency) has been proposed. Direct digital RF technology is technology that directly outputs an RF signal from a digital signal generation circuit. The direct digital RF technology uses many communication digital signal output circuits provided in a digital signal generation circuit realized by an FPGA (Field Programmable Gate Array).

A digital signal generation circuit generally has tens to hundreds of digital signal output circuits for communication, and by using direct digital RF technology, it is possible to configure an array antenna with a single digital signal generation circuit. An array antenna configured using direct digital RF technology combines orthogonal signals to form the phase and amplitude of a desired signal, so the phase and amplitude must be calibrated for each orthogonal signal.

For example, Patent Document 1 describes a calibration path measurement device for a phased array antenna provided with a switch for switching between a termination state and a total reflection state for a termination terminal of a directional coupler for inputting a calibration signal in a plurality of antenna modules. It is When measuring the calibration path, the switch is switched to the total internal reflection state and the reflected signal of the calibration signal is separated by the circulator. Next, the phase difference and amplitude ratio between the calibration signal and the reflected signal are measured, and the results of multiplying each measurement by 1/2 are subtracted from the measurement results when calibrating a plurality of antenna modules. This makes it possible to correct errors in the calibration path without measuring or adjusting the calibration path alone.

JP 2013-152135 A

In the conventional active phased array antenna described in Patent Document 1, in order to calibrate the path of the high frequency signal, the phase of the reference signal generated by the reference transmitter is changed to the phase of a part of the high frequency signal output from the antenna element. was compared with Therefore, the active phased array antenna has a problem that it is necessary to provide an output terminal dedicated to calibration for outputting a reference signal for calibration, in addition to the input/output terminal connected to the antenna element.

The present disclosure solves the above problems, and aims to obtain an output signal generation device, a phased array antenna, and a phased array antenna output signal calibration method that can calibrate an output signal without providing an output terminal dedicated to calibration. aim.

An output signal generation device according to the present disclosure includes a transmission signal generation unit that generates a modulated wave signal output from each of a plurality of output terminals, and a delay amount or phase of the modulated wave signal that is provided for each output terminal. a plurality of bit delay units connected to each of the plurality of bit delay units, setting the amplitude of the modulated wave signal for which the delay amount or phase is set, and outputting the modulated wave signal for which the amplitude is set from the output terminal and the phase difference and amplitude difference between the modulated wave signal output from one output terminal and the modulated wave signal output from the other output terminal, which are different from each other, among the plurality of output terminals. and a plurality of phase/amplitude comparators for outputting error signals, wherein the bit delay unit and the variable gain amplifier unit modulate output from one output terminal different from each other using a correction value calculated based on the error signal. The wave signal is calibrated using the modulated wave signal output from the other output terminal as a reference signal.

According to the present disclosure, among a plurality of output terminals, calculation based on an error signal indicating a phase difference and an amplitude difference between a signal output from one output terminal that is different from each other and a signal output from the other output terminal Using the corrected correction value, the signal output from one output terminal is calibrated using the signal output from the other output terminal as a reference signal. Thereby, the output signal generation device according to the present disclosure can calibrate the output signal without providing an output terminal dedicated to calibration.

1 is a block diagram showing a configuration example of a phased array antenna according to Embodiment 1; FIG. Fig. 3 is a graph showing a vector of desired phase output signals; Fig. 4 is a graph showing vectors of output signals with phase errors; 4 is a graph showing vectors of output signals with phase error calibrated; 4 is a flow chart showing a method for calibrating the output signal of the phased array antenna according to Embodiment 1; 6 is a flowchart showing detailed processing of the output signal calibration method of FIG. 5; 7A and 7B are block diagrams showing the hardware configuration for realizing the functions of the output signal generation device according to Embodiment 1. FIG. FIG. 8 is a block diagram showing a configuration example of a phased array antenna according to Embodiment 2; FIG. 11 is a block diagram showing a configuration example of a phased array antenna according to Embodiment 3;

Embodiment 1.
FIG. 1 is a block diagram showing a configuration example of a phased array antenna 1 according to Embodiment 1. As shown in FIG. A phased array antenna 1 shown in FIG. 1 is an active phased array antenna (APAA) and includes an output signal generator 2 and n antenna elements 3-1 to 3-n. Note that n is a natural number of 2 or more. The output signal generating device 2 has n output terminals 2-1 to 2-n, and the antenna elements 3-1 to 3-n are connected to these output terminals 2-1 to 2-n in order. . That is, the antenna element 3-1 is connected to the output terminal 2-1, the antenna element 3-2 is connected to the output terminal 2-2, and similarly the antenna element 3-n is connected to the output terminal 2-n. there is

The output signal generation device 2 generates output signals that are radiated into space as electromagnetic waves by the antenna elements 3-1 to 3-n. The phase error and amplitude error of the output signal are calibrated by the output signal generator 2 . As shown in FIG. 1, the output signal generation device 2 includes a digital signal generation circuit 4, 2n output terminals 5-1 to 5-2n, n signal synthesizing units 6-1 to 6-n, n It includes demultiplexers 7-1 to 7-n, phase/amplitude comparators 8-1 to 8-(n−1), a switching unit 9, and a correction value setting unit .

The digital signal generation circuit 4 is a circuit to which direct digital RF technology is applied, and is realized by FPGA or ASIC (Application Specific Integrated Circuit), for example. As shown in FIG. 1, the digital signal generation circuit 4 has 2n output terminals 5-1 to 5-2n, a transmission

signal generation section

21, and 2n bit delay sections 22-1 to 2n. 22-2n, n variable gain amplifiers 23-1 to 23-2n, a phase controller 24 and a delay controller 25 are provided.

The transmission signal generator 21 uses transmission data set by an external device to generate transmission signals of modulated waves to be output from the output terminals 5-1 to 5-2n. The modulated waves generated by the transmission signal generator 21 are output to bit delay units 22-1 to 22-2n, respectively. The bit delay units 22-1 to 22-2n are provided for each output terminal, that is, for each of the output terminals 5-1 to 5-2n, and set the delay amount or phase of the modulated wave signal.

For example, when k is a natural number greater than or equal to 1 and less than or equal to n, the bit delay units 22-1 to 22-2n are paired with a bit delay unit 22-(2k-1) and a bit delay unit 22-2k. there is The bit delay section 22-(2k-1) and the bit delay section 22-2k are configured to divide the modulated wave signal output from the bit delay section 22-(2k-1) and the modulated wave signal output from the bit delay section 22-2k. The delay amounts or phases of the modulated wave signals are set so that the phase difference between them is 90 degrees, that is, they are orthogonal to each other.

Variable gain amplifiers 23-1 to 23-2n are variable gain amplifiers connected to bit delay units 22-1 to 22-2n, respectively. For example, the input terminal of the variable gain amplifier section 23-1 is connected to the output terminal of the bit delay section 22-1, and the input terminal of the variable gain amplifier section 23-2 is connected to the output terminal of the bit delay section 22-2. It is Similarly, the input terminal of the variable gain amplifier section 23-2n is connected to the output terminal of the bit delay section 22-2n. The variable gain amplifiers 23-1 to 23-2n set the amplitude of the signal whose delay amount or phase is set by the bit delay unit, and output the signal with the set amplitude from the output terminals 5-1 to 5-2n. .

The signal synthesizing units 6-1 to 6-n are provided for each pair of output terminals different from each other among the output terminals 5-1 to 5-2n, and combine orthogonal modulated wave signals respectively output from the pair of output terminals. Synthesize. For example, the signal synthesizing section 6-1 is connected to the output terminal 5-1 and the output terminal 5-2. The output terminal 5-1 and the output terminal 5-2 are terminals for outputting a signal Sh1 and a signal Sv1 orthogonal to each other. The signal synthesizing unit 6-1 outputs a signal S1 obtained by synthesizing the signal Sh1 and the signal Sv1 to the demultiplexing unit 7-1. Similarly, the signal synthesizer 6-n is connected to the output terminal 5-(2n-1) and the output terminal 5-2n. The signal Shn output from the output terminal 5-(2n-1) and the signal Svn output from the output terminal 5-2 are orthogonal to each other. The signal synthesizing unit 6-n outputs a signal Sn obtained by synthesizing the signal Shn and the signal Svn to the demultiplexing unit 7-n.

The demultiplexing units 7-1 to 7-n demultiplex the signals output from the signal synthesizing units 6-1 to 6-n, output the signals to the output terminals 2-1 to 2-n, and phase and amplitude comparators. Output to 8-1 to 8-(n-1). For example, the demultiplexing unit 7-1 demultiplexes the signal S1 output from the signal synthesizing unit 6-1, and outputs it to the output terminal 2-1 and the phase/amplitude comparing unit 8-1. The signal output to the output terminal 2-1 is radiated into space as an electromagnetic wave by the antenna element 3-1.

Phase-amplitude comparators 8-1 to 8-(n-1) compare the signals output from one of the output terminals 5-1 to 5-2n, which are different from each other, and the signals output from the other output terminals. outputs an error signal indicative of the phase and amplitude differences between For example, the phase/amplitude comparison section 8-1 generates an error signal indicating the phase difference and the amplitude difference between the signal output from the signal synthesis section 6-1 and the signal output from the signal synthesis section 6-2. , and outputs an error signal to the switching unit 9 . The signal output from the signal synthesizing unit 6-1 is the signal Sh1 output from the output terminal 5-1 or the signal Sv1 output from the output terminal 5-2. The signal output from the signal synthesizing section 6-2 is the signal Sh2 output from the output terminal 5-3 different from the output terminals 5-1 and 5-2.

The phase/amplitude comparator 8-1 generates an error signal Scal1 indicating the phase difference and amplitude difference between the signal Sh1 and the signal Sh2, and generates an error signal indicating the phase difference and amplitude difference between the signal Sv1 and the signal Sh2. Generate Scal2. The phase/amplitude comparison section 8-1 outputs the error signal Scal1 and the error signal Scal2 to the switching section 9. FIG.

The switching unit 9 selects one of the phase/amplitude comparison units 8-1 to 8-(n−1), and converts the error signal output from the selected phase/amplitude comparison unit into an output signal. switch to For example, when the signal Sh1 or the signal Sv1 is to be calibrated, the switching unit 9 selects the error signal generated by the phase/amplitude comparison unit 8-1 among the phase/amplitude comparison units 8-1 to 8-(n−1). Scal1 and error signal Scal2 are output to correction value setting section 10 .

Correction value setting section 10 sets correction values for calibrating the phase difference and amplitude difference indicated by the output signal output from switching section 9 to bit delay sections 22-1 to 22-2n and variable gain amplification sections 23-1 to 23-. Set to 2n. For example, if the signal Sh1 is to be calibrated, the correction value setting unit 10 generates a correction value for the amplitude of the signal Sh1 that reduces the amplitude difference indicated by the error signal Scal1, sets it in the phase control unit 24, and A correction value for the phase of the signal Sh1 that reduces the phase difference indicated by Scal1 is generated and set in the delay control unit 25 . When the signal Sv1 is to be calibrated, the correction value setting unit 10 generates a correction value for the amplitude of the signal Sv1 that reduces the amplitude difference indicated by the error signal Scal2 and sets it in the phase control unit 24, so that the error signal Scal2 is A correction value for the phase of the signal Sv<b>1 that reduces the indicated phase difference is generated and set in the delay control unit 25 .

The phase control unit 24, when transmitting a modulated wave transmission signal using the antenna elements 3-1 to 3-n, according to the antenna phase information set by the external device, the variable gain amplifier units 23-1 to 23- 2n to control the setting of the amplitude of the modulated wave. The delay control unit 25 uses the antenna elements 3-1 to 3-n to transmit modulated wave transmission signals, and the bit delay units 22-1 to 22-2n according to the antenna phase information set by the external device. Controls the setting of the delay amount or phase of the modulated wave by . Here, the antenna phase information is information for setting the phase and amplitude of the output signal (transmission signal). The phase controller 24 controls the variable gain amplifiers 23-1 to 23-2n to set the amplitude indicated by the antenna phase information as the amplitude of the output signal. The delay control unit 25 sets the phase indicated by the antenna phase information as the phase of the output signal by controlling the bit delay units 22-1 to 22-2n.

Also, the phase control section 24 sets the amplitude corresponding to the correction value set by the correction value setting section 10 to the signal Sh1 by controlling the variable gain amplification section 23-1. The delay control unit 25 controls the bit delay unit 22-1 to set the phase according to the correction value set by the correction value setting unit 10 to the signal Sh1. Thereby, the phase and amplitude of the signal Sh1 are calibrated using the signal Sh2 as a reference signal. Similarly, the phase and amplitude of signal Sv1 are calibrated using signal Sh2 as a reference signal.

FIG. 2 is a graph showing the vector of the desired phase output signal S1. The vector of the signal S1 shown in FIG. 2 is a vector obtained by synthesizing the vector of the signal Sh1 output from the output terminal 5-1 and the vector of the signal Sv1 output from the output terminal 5-2. generated by the section 6-1. When the signal Sh1 and the signal Sv1 have a phase difference of 90 degrees, that is, when they are orthogonal to each other, the signal S1 having the desired phase indicated by the antenna phase information is obtained.

FIG. 3 is a graph showing vectors of the output signal S1' with phase error. As shown in FIG. 2, ideally, the signal Sh1 and the signal Sv1 are orthogonal. However, in reality, the signal Sh1 and the signal Sv1 are completely different from each other due to the asymmetric characteristics of the output terminal 5-1, the output terminal 5-2 and the signal synthesizing unit 6-1 or the variation of the antenna elements. may not be orthogonal. For example, as shown in FIG. 3, when the signal Sh1 becomes a signal Sh1′ that is not orthogonal to the signal Sv1, the signal S1 having the desired phase indicated by the antenna phase information is changed as indicated by the dashed arrow. A vector of the signal S1' is obtained which is not obtained and which contains the phase error.

FIG. 4 is a graph showing the vector of the output signal S1 whose phase error has been calibrated. shows the vector. The correction value setting unit 10 sets the correction value of the amplitude of the signal Sh1′ whose amplitude difference with the signal Sh1 is reduced in the phase control unit 24, and sets the signal Sh1′ whose phase difference with the signal Sh1 is reduced. A correction value for the phase of Sh1' is set in the delay control unit 25. FIG. The phase control section 24 and the delay control section 25 use the correction value set by the correction value setting section 10 to calibrate the phase and amplitude of the signal Sh1'. As a result, the signal Sh1″ shown in FIG. 4 is obtained, and the signal combining unit 6-1 combines the signal Sh1″ and the signal Sv1 to generate the signal S1″ having the desired phase indicated by the antenna phase information. Output.

FIG. 5 is a flow chart showing a method for calibrating the output signal of the phased array antenna 1, showing calibration processing of the output signal by the output signal generator 2. In FIG.
In the conventional technology for calibrating the signal generated by the digital signal generation circuit (the signal transmitted from the phased array antenna), the reference signal Sref prepared in the digital signal generation circuit is distributed to the output terminal for outputting the signal to be calibrated. and the output signal is calibrated using the reference signal Sref. Therefore, it is necessary to provide the digital signal generation circuit with an output terminal dedicated to calibration used for distributing the reference signal Sref.

On the other hand, in the output signal calibration method of the output signal generation device 2 and the phased array antenna 1, one of the output terminals 5-1 to 5-2n, which is different from each other, is the output terminal 5-k or 5-(k+1). and the signal Sh(k+1) output from the output terminal 5-(k+2). are used to calibrate the signals Shk and Svk using the signal Sh(k+1) output from the output terminal 5-(k+2) as a reference signal. Thereby, the output signal generation device 2 can calibrate the output signal Shk and the signal Svk without providing an output terminal dedicated to calibration.

The transmission signal generator 21 generates modulated wave signals Sh1 to Shn and Sv1 to Svn output from the output terminals 5-1 to 5-2n, respectively (step ST1). The bit delay units 22-1 to 22-2n set delay amounts or phases of the signals Sh1 to Shn and Sv1 to Svn, respectively (step ST2). The variable gain amplifiers 23-1 to 23-2n set the amplitudes of the signals Sh1 to Shn and Sv1 to Svn for which the delay amounts or phases are set, and output the signals Sh1 to Shn and Sv1 to Svn to the output terminals 5- 1 to 5-2n are output (step ST3).

The phase/amplitude comparator 8-k outputs a signal Shk output from the output terminal 5-k and a signal Sh(k+1) output from the output terminal 5-(k+2) among the output terminals 5-1 to 5-2n. and an error (phase difference or amplitude difference), an error signal Scal1 indicating the error is generated. When there is an error between the signal Svk output from the output terminal 5-(k+1) and the signal Sh(k+1) output from the output terminal 5-(k+2), the phase/amplitude comparator 8-k An error signal Scal2 indicating the error is generated. Note that k is a natural number equal to or greater than 1 and equal to or less than n.

The correction value setting unit 10 acquires the error signals Scal1 and Scal2 from the phase/amplitude comparison unit 8-k through the switching unit 9, and calculates correction values that reduce the errors indicated by the error signals Scal1 and Scal2. Subsequently, the correction value setting section 10 sets the calculated correction values in the phase control section 24 and the delay control section 25 . The phase control unit 24 sets the correction value for amplitude to the variable gain amplifiers 23-k and 23-(k+1), and the delay control unit 25 sets the correction value for the phase to the bit delay units 22-k and 22-(k+1). ).

Using the correction value set by the delay control unit 25, the bit delay units 22-k and 22-(k+1) shift the phase error of the signal Shk output from the output terminal 5-k to the output terminal 5-(k+2). The signal Sh(k+1) output from is calibrated as a reference signal. Further, the bit delay units 22-k and 22-(k+1) use the correction value set by the delay control unit 25 to adjust the phase error of the signal Svk output from the output terminal 5-(k+1) to the output terminal 5 The signal Sh(k+1) output from -(k+2) is calibrated as a reference signal.

The variable gain amplifiers 23-k and 23-(k+1) use the correction value set by the phase controller 24 to output the amplitude error of the signal Shk whose phase error has been calibrated from the output terminal 5-(k+2). The resulting signal Sh(k+1) is calibrated as a reference signal. Furthermore, the variable gain amplifiers 23-k and 23-(k+1) use the correction value set by the phase controller 24 to output the amplitude error of the signal Svk whose phase error has been calibrated to the output terminal 5-(k+2). The signal Sh(k+1) output from is calibrated as a reference signal. The processing up to this point is the processing of step ST4.

FIG. 6 is a flow chart showing detailed processing of the output signal calibrating method of FIG.
In the following description, signals Sh1 and Sv1 are calibrated using signal Sh2 as a reference signal.
First, the switching unit 9 sets a calibration target (step ST1a). For example, the switching unit 9 switches the output destination of the error signals Scal1 and Scal2 from the phase/amplitude comparing unit 8-k used for calibrating the output signal to the correction value setting unit 10. FIG. Since the signals Sh1 and Sv1 are to be calibrated, the output destination of the phase/amplitude comparison section 8-k is switched to the correction value setting section 10. FIG.

The delay control unit 25 sets initial values of delay amounts for the bit delay units 22-1 and 22-2 (step ST2a). The phase control section 24 sets initial values of gains for the variable gain amplification sections 23-1 and 23-2 (step ST3a).
Subsequently, the phase control section 24 controls the variable gain amplification section 23-1 and the variable gain amplification section 23-3 to output only the signal Sh1 from the output terminal 5-1 and output only the signal Sh2 from the output terminal 5-1. -3 is output (step ST4a).

Since only the signal Sh1 is input to the signal synthesizing unit 6-1, the synthesized signal remains the signal Sh1. Since the signal synthesizing section 6-2 receives only the signal Sh2, the synthesized signal remains the signal Sh2. The signal combiner 6-1 outputs the signal Sh1 to the demultiplexer 7-1, and the signal combiner 6-2 outputs the signal Sh2 to the demultiplexer 7-2. The demultiplexer 7-1 outputs the signal Sh1 to the phase/amplitude comparator 8-1, and the demultiplexer 7-2 outputs the signal Sh2 to the phase/amplitude comparator 8-1. The phase/amplitude comparison section 8-1 uses the signal Sh2 as a reference signal to generate an error signal Scal1 indicating the phase and amplitude errors of the signal Sh1, and outputs the error signal Scal1 to the switching section 9 (step ST5a).

Subsequently, the phase control section 24 controls the variable gain amplification section 23-2 and the variable gain amplification section 23-3 to output only the signal Sv1 from the output terminal 5-2 and output only the signal Sh2 from the output terminal 5-2. -3 is output (step ST6a). At this time, the signal synthesizing unit 6-1 receives only the signal Sv1, so the synthesized signal remains the signal Sv1. Since the signal synthesizing section 6-2 receives only the signal Sh2, the synthesized signal remains the signal Sh2. The signal combiner 6-1 outputs the signal Sv1 to the demultiplexer 7-1, and the signal combiner 6-2 outputs the signal Sh2 to the demultiplexer 7-2. The demultiplexer 7-1 outputs the signal Sv1 to the phase/amplitude comparator 8-1, and the demultiplexer 7-2 outputs the signal Sh2 to the phase/amplitude comparator 8-1.

The phase/amplitude comparison section 8-1 uses the signal Sh2 as a reference signal to generate an error signal Scal2 indicating the phase and amplitude errors of the signal Sv1, and outputs the error signal Scal2 to the switching section 9 (step ST7a). The switching unit 9 switches the output destination of the phase/amplitude comparing unit 8-1 to the correction value setting unit 10. FIG. When the error signal Scal1 and the error signal Scal2 are input, the correction value setting unit 10 calculates a correction value that reduces the error indicated by the error signal Scal1 and the error signal Scal2. Set in the control unit 25 .

The bit delay units 22-1 and 22-2 use the correction value set by the delay control unit 25 to calibrate the phase error between the signals Sh1 and Sv1 using the signal Sh2 as a reference signal. The variable gain amplifiers 23-1 and 23-2 use the correction value set by the phase controller 24 to convert the phase error-calibrated signal Sh1 and the amplitude error of the signal Sv1 using the signal Sh2 as a reference signal. calibrate. These processes are the processes of step ST8a.

So far, the signal Shk and the signal Svk have been calibrated using the signal Sh(k+1) as the reference signal, but the reference signal is not limited to the signal Sh(k+1).
For example, the reference signal may be a signal output from any of the output terminals 5-1 to 5-2n other than the output terminal for outputting the signal Shk and the signal Svk. It may be the output signal Sv(k+1). That is, when the signals to be calibrated are Sh1 and Sv1, the signal Sv2 may be used as the reference signal.

Signal synthesizing units 6-1 to 6-n, demultiplexing units 7-1 to 7-n, phase/amplitude comparing units 8-1 to 8-(n-1), switching unit 9, and correction in the output signal generation device 2 The functions of the value setting unit 10, the transmission signal generation unit 21, the bit delay units 22-1 to 22-2n, the variable gain amplification units 23-1 to 23-2n, the phase control unit 24, and the delay control unit 25 are performed by the processing circuit. Realized. That is, the output signal generation device 2 includes a processing circuit for executing each process from step ST1 to step ST4 shown in FIG. The processing circuit may be dedicated hardware, or may be a CPU (Central Processing Unit) that executes a program stored in memory.

FIG. 7A is a block diagram showing a hardware configuration that implements the functions of the output signal generation device 2. FIG. FIG. 7B is a block diagram showing a hardware configuration for executing software realizing the functions of the output signal generation device 2. As shown in FIG. 7A and 7B, an input interface 100 is an interface that relays transmission data or antenna phase information output from an external device to the output signal generation device 2. FIG. The output interface 101 is an interface that relays signals output from the output signal generator 2 to the antenna elements 3-1 to 3-n.

Where the processing circuit is the dedicated hardware processing circuit 102 shown in FIG. 7A, the processing circuit 102 may be, for example, a single circuit, multiple circuits, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or any of these. A combination of is applicable.
Signal synthesizing units 6-1 to 6-n, demultiplexing units 7-1 to 7-n, phase/amplitude comparing units 8-1 to 8-(n-1), switching unit 9, and correction in the output signal generation device 2 The functions of the value setting unit 10, the transmission signal generation unit 21, the bit delay units 22-1 to 22-2n, the variable gain amplification units 23-1 to 23-2n, the phase control unit 24, and the delay control unit 25 are provided by separate processing circuits. , or these functions may be collectively realized by one processing circuit.

When the processing circuit is the processor 103 shown in FIG. 7B, the signal synthesizing units 6-1 to 6-n, the demultiplexing units 7-1 to 7-n, the phase/amplitude comparing units 8-1 to 8-n in the output signal generating device 2 8-(n-1), switching unit 9, correction value setting unit 10, transmission signal generation unit 21, bit delay units 22-1 to 22-2n, variable gain amplification units 23-1 to 23-2n, phase control unit 24 and delay control unit 25 are implemented by software, firmware, or a combination of software and firmware. Note that software or firmware is written as a program and stored in the memory 104 .

The processor 103 reads out and executes the program stored in the memory 104 so that the signal synthesizing units 6-1 to 6-n, the demultiplexing units 7-1 to 7-n, the phase/amplitude Comparison units 8-1 to 8-(n-1), switching unit 9, correction value setting unit 10, transmission signal generation unit 21, bit delay units 22-1 to 22-2n, variable gain amplification units 23-1 to 23 -2n, the functions of the phase control unit 24 and the delay control unit 25 are realized.
For example, the output signal generation device 2 includes a memory 104 for storing a program that, when executed by the processor 103, results in execution of the processes from steps ST1 to ST4 in the flowchart shown in FIG. there is These programs include signal synthesizing units 6-1 to 6-n, demultiplexing units 7-1 to 7-n, phase/amplitude comparing units 8-1 to 8-(n-1), switching unit 9, correction value setting The procedure or method of processing performed by the unit 10, the transmission signal generation unit 21, the bit delay units 22-1 to 22-2n, the variable gain amplification units 23-1 to 23-2n, the phase control unit 24, and the delay control unit 25 is let the computer do it.
The memory 104 comprises a computer including signal synthesis units 6-1 to 6-n, demultiplexing units 7-1 to 7-n, phase/amplitude comparison units 8-1 to 8-(n-1), a switching unit 9, a correction A program for functioning as the value setting unit 10, the transmission signal generation unit 21, the bit delay units 22-1 to 22-2n, the variable gain amplification units 23-1 to 23-2n, the phase control unit 24, and the delay control unit 25 is provided. It may be a computer readable storage medium.

The memory 104 includes, for example, non-volatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically-EPROM), magnetic Discs, flexible discs, optical discs, compact discs, mini discs, DVDs, and the like are applicable.

Signal synthesizing units 6-1 to 6-n, demultiplexing units 7-1 to 7-n, phase/amplitude comparing units 8-1 to 8-(n-1), switching unit 9, and correction in the output signal generation device 2 Some of the functions of the value setting unit 10, the transmission signal generation unit 21, the bit delay units 22-1 to 22-2n, the variable gain amplification units 23-1 to 23-2n, the phase control unit 24, and the delay control unit 25 are dedicated. may be implemented in hardware, and a part may be implemented in software or firmware.

For example, signal synthesizing units 6-1 to 6-n, demultiplexing units 7-1 to 7-n, phase/amplitude comparing units 8-1 to 8-(n-1), switching unit 9, and correction value setting unit 10 realizes the function by processing circuit 102, which is dedicated hardware, and includes transmission signal generation section 21, bit delay sections 22-1 to 22-2n, variable gain amplification sections 23-1 to 23-2n, phase control section 24 And the delay control unit 25 realizes its function by the processor 103 reading and executing a program stored in the memory 104 . As such, the processing circuitry may implement the above functions in hardware, software, firmware, or a combination thereof.

As described above, the method for calibrating the output signal of the output signal generating device 2 and the phased array antenna 1 according to the first embodiment can The output signal Shk, the signal Svk output from the output terminal 5-(k+1), and the signal Sh output from the other output terminal 5-(k+2) different from the output terminal 5-k or 5-(k+1) Signals Shk and Svk are calibrated using signal Sh(k+1) as a reference signal using correction values calculated based on error signals Scal1 and Scal2 indicating the phase and amplitude differences between (k+1) and (k+1). As a result, the output signal generator 2 can calibrate the signals Shk and Svk, which are output signals, without providing an output terminal dedicated to calibration.

The output signal generation device 2 according to Embodiment 1 includes a delay control section 25 that controls setting of the delay amount or phase of the modulated wave signal by the bit delay sections 22-1 to 22-2n, and a variable gain amplification section 23-1. 23-2n and a phase control unit 24 for controlling the setting of the amplitude of the modulated wave signal by the output terminals 5-1 to 5-2n. It has signal synthesizing units 6-1 to 6-n for synthesizing output orthogonal modulated wave signals.
The phase/amplitude comparison unit 8-k combines the signal Shk or Svk synthesized by one of the signal synthesis units 6-1 to 6-n, which are different from each other, and the other signal synthesis unit 6-( k+1) and the synthesized signal Sh(k+1), and output error signals Scal1 and Scal2 indicating the phase and amplitude differences.
The bit delay units 22-k and 22-(k+1) and the variable gain amplifier units 23-k and 23-(k+1) combine the signals Shk and Svk synthesized by the signal synthesis unit 6-k with the other signal synthesis unit. The signal Sh(k+1) synthesized by 6-(k+1) is calibrated as a reference signal. As a result, the output signal generator 2 can calibrate the signals Shk and Svk, which are output signals, without providing an output terminal dedicated to calibration.

The output signal generating device 2 according to Embodiment 1 selects any one of the phase/amplitude comparison units 8-1 to 8-(n−1), and from the selected phase/amplitude comparison unit A switching unit 9 for switching an output error signal to an output signal, and bit delay units 22-1 to 22-2n and variable gains for correcting the phase difference and amplitude difference indicated by the output signal output from the switching unit 9. and a correction value setting unit 10 for setting the amplification units 23-1 to 23-2n. Bit delay units 22-1 to 22-2n and variable gain amplifier units 23-1 to 23-2n calibrate modulated wave signals using the correction values set by correction value setting unit 10. FIG. As a result, the output signal generation device 2 can calibrate the output signal without providing an output terminal dedicated to calibration.

The phased array antenna 1 according to Embodiment 1 includes an output signal generation device 2 and antenna elements 3-1 to 3-3 for radiating modulated wave signals output from signal combining units 6-1 to 6-n into space, respectively. -n. By providing the output signal generator 2, it is possible to provide the phased array antenna 1 that transmits a calibrated output signal without providing an output terminal dedicated to calibration.

Embodiment 2.
FIG. 8 is a block diagram showing a configuration example of a phased array antenna 1A according to the second embodiment. In FIG. 8, a phased array antenna 1A is an APAA and includes an output signal generator 2A and n antenna elements 3-1 to 3-n. The output signal generation device 2A includes a digital signal generation circuit 4, 2n output terminals 5-1 to 5-2n, n signal synthesizing units 6-1 to 6-n, n demultiplexing units 7-1 to 7-n, phase/amplitude comparison units 8-1 to 8-{(n/2)-1}, switching unit 9, correction value setting unit 10, and low-pass filters 11-1 to 11-n. The low-pass filters 11-1 to 11-n are hereinafter referred to as LPFs 11-1 to 11-n.

The LPFs 11-1 to 11-n remove noise contained in the signals output to the phase/amplitude comparators 8-1 to 8-{(n/2)-1} through the demultiplexers 7-1 to 7-n. It is a filter that For example, the LPFs 11-1 to 11-n remove harmonics (high frequency noise) in the signals output to the phase/amplitude comparators 8-1 to 8-{(n/2)-1}. Two signals output from different pairs of signal synthesizing units are input to the individual phase/amplitude comparing units 8-1 to 8-{(n/2)-1}. Two LPFs are provided for each phase/amplitude comparator to remove harmonics contained in these signals.

In the output signal generator 2A, the transmission signal generator 21 generates modulated wave signals Sh1 to Shn and Sv1 to Svn output from the output terminals 5-1 to 5-2n, respectively. The bit delay units 22-1 to 22-2n set delay amounts or phases of the signals Sh1 to Shn and Sv1 to Svn, respectively. The variable gain amplifiers 23-1 to 23-2n set the amplitudes of the signals Sh1 to Shn and Sv1 to Svn for which the delay amounts or phases are set, and output the signals Sh1 to Shn and Sv1 to Svn to the output terminals 5- Output from 1 to 5-2n. Signals output from the output terminals 5-1 to 5-2n are output to the signal synthesizing units 6-1 to 6-n.

The LPF 11-k removes harmonics contained in the signal Shk or Svk output from the signal synthesizing unit 6-k through the demultiplexing unit 7-k, and converts the signal Shk or Svk from which the harmonics have been removed to a phase/amplitude comparator. output to 8-k. Furthermore, the LPF 11-(k+1) removes harmonics contained in the signal Sh(k+1) output from the signal synthesis unit 6-(k+1) through the demultiplexing unit 7-(k+1), and removes the harmonics from the signal Sh(k+1). Sh(k+1) is output to the phase/amplitude comparator 8-k. Note that k is a natural number equal to or greater than 1 and equal to or less than n.

The phase/amplitude comparator 8-k determines an error (phase difference or amplitude difference), it generates an error signal Scal1 indicating the error.
Similarly, the phase amplitude comparator 8-k has an error between the signal Svk from which the harmonics have been removed by the LPF 11-k and the signal Sh(k+1) from which the harmonics have been removed by the LPF 11-(k+1). , an error signal Scal2 indicating the error is generated.
This makes it possible to eliminate the influence of errors due to harmonics contained in each signal input to the phase/amplitude comparator 8-k, thereby improving error detection accuracy in the phase/amplitude comparator 8-k.

The bit delay units 22-k and 22-(k+1) use the correction value calculated based on the error signal Scal1 to calibrate the phase error of the signal Shk and calibrate the phase error of the signal Svk. Further, the variable gain amplifiers 23-k and 23-(k+1) use the correction value calculated based on the error signal Scal2 to calibrate the amplitude error of the signal Shk and calibrate the amplitude error of the signal Svk.

In the output signal generation device 2A, signal synthesizing units 6-1 to 6-n, demultiplexing units 7-1 to 7-n, phase/amplitude comparing units 8-1 to 8-(n-1), switching unit 9 , correction value setting unit 10, LPF 11-1 to 11-n, transmission signal generation unit 21, bit delay units 22-1 to 22-2n, variable gain amplification units 23-1 to 23-2n, phase control unit 24 and delay The functions of the control unit 25 are realized by the processing circuit shown in FIG. 7A or 7B. That is, the output signal generation device 2A includes a processing circuit for executing the processing shown in the second embodiment. The processing circuit may be dedicated hardware, or may be a CPU that executes a program stored in memory.

As described above, the output signal generation device 2A according to the second embodiment can detect harmonics contained in the modulated wave signals output to the phase/amplitude comparators 8-1 to 8-{(n/2)-1}. LPFs 11-1 to 11-n to be removed are provided. It is possible to remove the influence of errors due to harmonics contained in each signal input to the phase/amplitude comparator 8-k, and the error detection accuracy in the phase/amplitude comparator 8-k is improved.

Embodiment 3.
FIG. 9 is a block diagram showing a configuration example of a phased array antenna 1B according to the third embodiment. In FIG. 9, a phased array antenna 1B is an APAA and includes an output signal generator 2B and n antenna elements 3-1 to 3-n. The output signal generation device 2B includes a digital signal generation circuit 4, n output terminals 5-1 to 5-n, n demultiplexers 7-1 to 7-n, phase amplitude comparators 8-1 to 8- {(n/2)-1}, a switching unit 9, a correction value setting unit 10, and LPFs 11-1 to 11-n.

The transmission signal generator 21 generates modulated wave signals S1 to Sn output from the output terminals 5-1 to 5-n, respectively. The bit delay units 22-1 to 22-n set delay amounts or phases of the signals S1 to Sn, respectively. The variable gain amplifiers 23-1 to 23-n set the amplitudes of the signals S1 to Sn for which the delay amounts or phases are set, and output the signals S1 to Sn from the output terminals 5-1 to 5-n. The signals output from the output terminals 5-1 to 5-n are not subjected to signal synthesis (IQ synthesis), and are passed through the demultiplexers 7-1 to 7-n to the phase amplitude comparators 8-1 to 8-{ (n/2)-1}.

The phase/amplitude comparator 8-k outputs the signal Sk output from the output terminal 5-k among the output terminals 5-1 to 5-n and the signal S(k+1) output from the output terminal 5-(k+1). produces an error signal indicative of the difference if there is a difference in the output waveform between . Note that k is a natural number equal to or greater than 1 and equal to or less than n. The correction value setting unit 10 acquires the error signal from the phase/amplitude comparison unit 8-k through the switching unit 9, and calculates a correction value for the output waveform that reduces the difference indicated by the error signal.

Subsequently, the correction value setting section 10 sets the correction values in the phase control section 24 and the delay control section 25 . The phase control section 24 sets the correction value to the variable gain amplification section 23-k, and the delay control section 25 sets the correction value to the bit delay section 22-k. The bit delay unit 22-k and the variable gain amplification unit 23-k use the correction value to change the output waveform of the signal Sk output from the output terminal 5-k to the output terminal 5-(k+1). The signal S(k+1) is calibrated as a reference signal. As a result, the output signal generation device 2B can calibrate the output waveform of the output signal without providing an output terminal dedicated to calibration. That is, the output signal generator 2B does not calibrate the quadrature signals Shk and Svk, but corrects the phases of the output signals output from the antenna elements 3-1 to 3-n.
The waveform of the phased array antenna 1B can be formed by changing the output amplitudes of the variable gain amplifiers 23-1 to 23-n. Therefore, the phased array antenna 1B may control the beam shape by controlling the amplitude of the variable gain amplifiers 23-1 to 23-n in addition to adjusting the delay amounts of the signals S1 to Sn.

Note that, in the output signal generation device 2B, demultiplexing units 7-1 to 7-n, phase amplitude comparison units 8-1 to 8-(n−1), switching unit 9, correction value setting unit 10, LPF 11-1 to 11-n, transmission signal generation unit 21, bit delay units 22-1 to 22-n, variable gain amplification units 23-1 to 23-n, phase control unit 24, and delay control unit 25 are shown in FIG. It is realized by the processing circuit shown in 7B. That is, the output signal generation device 2B includes a processing circuit for executing the processing shown in the third embodiment. The processing circuit may be dedicated hardware, or may be a CPU that executes a program stored in memory.

As described above, the phased array antenna 1B according to the third embodiment is an antenna that radiates each of the modulated wave signals output from the output signal generation device 2B and the variable gain amplifiers 23-1 to 23-n into space. and elements 3-1 to 3-n. By providing the output signal generating device 2B, it is possible to provide a phased array antenna 1B that transmits an output signal whose output waveform is calibrated without providing an output terminal dedicated to calibration.

It should be noted that it is possible to omit any component in each of the combinations of the embodiments, the modification of the components of each of the embodiments, or the configuration of each of the embodiments.

The output signal generation device according to the present disclosure can be used for APPA, for example.

1, 1A, 1B phased array antenna, 2, 2A, 2B output signal generator, 2-1 to 2-n, 5-1 to 5-2n, 5-1 to 5-n output terminals, 3-1 to 3 -n antenna element, 4 digital signal generation circuit, 6-1 to 6-n signal synthesizing section, 7-1 to 7-n demultiplexing section, 8-1 to 8-(n-1), 8-1 to 8 -{(n/2)-1} Phase/amplitude comparison section, 9 switching section, 10 correction value setting section, 11-1 to 11-n LPF, 21 transmission signal generation section, 22-1 to 22-2n, 22- 1 to 22-n bit delay section, 23-1 to 23-2n, 23-1 to 23-n variable gain amplifier section, 24 phase control section, 25 delay control section, 100 input interface, 101 output interface, 102 processing circuit , 103 Processor, 104 Memory.

Claims

a transmission signal generator that generates a modulated wave signal that is output from each of a plurality of output terminals;
a plurality of bit delay units provided for each of the output terminals and respectively setting a delay amount or a phase of the modulated wave signal;
a plurality of variable gain amplifiers connected to each of the plurality of bit delay units, setting the amplitude of the modulated wave signal with a set delay amount or phase, and outputting the amplitude-set modulated wave signal from the output terminal Department and
An error signal indicating a phase difference and an amplitude difference between the modulated wave signal output from one output terminal and the modulated wave signal output from the other output terminal among the plurality of output terminals. and a plurality of phase-amplitude comparators that output
The bit delay section and the variable gain amplification section use a correction value calculated based on the error signal to convert the modulated wave signal output from one of the different output terminals to the other output terminal. An output signal generation device characterized by calibrating the output modulated wave signal as a reference signal.
a delay control unit that controls setting of the delay amount or phase of the modulated wave signal by the bit delay unit;
a phase control section that controls setting of the amplitude of the modulated wave signal by the variable gain amplification section;
a plurality of signal synthesizing units provided for each pair of the output terminals that are different from each other among the plurality of the output terminals, and synthesizing the orthogonal modulated wave signals output from the pair of the output terminals,
The plurality of phase/amplitude comparators combine the modulated wave signals synthesized by one of the signal synthesizing units different from each other and the modulated wave signals synthesized by the other signal synthesizing unit among the plurality of signal synthesizing units. comparing respectively the phase difference and the amplitude difference between and outputting said error signal indicative of the phase difference and the amplitude difference;
The bit delay section and the variable gain amplification section calibrate the modulated wave signals synthesized by one of the signal synthesizing sections different from each other using the modulated wave signal synthesized by the other signal synthesizing section as a reference signal. The output signal generation device according to claim 1, characterized in that:
a switching unit that selects one of the plurality of phase and amplitude comparison units and switches the error signal output from the selected phase and amplitude comparison unit to an output signal;
a correction value setting unit that sets correction values for calibrating the phase difference and the amplitude difference indicated by the output signal output from the switching unit to the bit delay unit and the variable gain amplification unit;
3. The output signal according to claim 1, wherein the bit delay section and the variable gain amplification section calibrate the modulated wave signal using the correction value set by the correction value setting section. generator.
An output signal generating device according to claim 1;
A phased array antenna comprising: a plurality of antenna elements for radiating into space each of the modulated wave signals output from the plurality of variable gain amplifiers.
An output signal generating device according to claim 2;
A phased array antenna comprising: a plurality of antenna elements for radiating into space each of the modulated wave signals output from the plurality of signal synthesizing units.
6. The phased array antenna according to claim 4, further comprising a filter for removing noise contained in the modulated wave signal output to the phase/amplitude comparator.
A phased array antenna output signal calibration method according to claim 4,
a step in which the transmission signal generator generates the modulated wave signal output from each of the plurality of output terminals;
a step in which the plurality of bit delay units respectively sets the delay amount or phase of the modulated wave signal;
setting the amplitude of the modulated wave signal with the set delay amount or phase, and outputting the modulated wave signal with the set amplitude from the output terminal;
A plurality of the phase and amplitude comparators are arranged to determine the difference between the modulated wave signal output from one of the output terminals that are different from each other and the modulated wave signal output from the other output terminal of the plurality of output terminals. and outputting the error signal indicative of the phase difference and the amplitude difference;
The bit delay section and the variable gain amplification section use a correction value calculated based on the error signal to convert the modulated wave signal output from one of the different output terminals to the other output terminal. A method for calibrating an output signal of a phased array antenna, comprising calibrating the output modulated wave signal as a reference signal.